From: Keith Packard <keithp@keithp.com>
Date: Tue, 13 Apr 2021 07:10:01 +0000 (-0700)
Subject: Decrease ADC clock to pclk/4 (12MHz)
X-Git-Url: https://git.gag.com/?a=commitdiff_plain;h=0642bc895acc593d34ec3a5e852f4ee08ba29e36;p=fw%2Faltos

Decrease ADC clock to pclk/4 (12MHz)

ADC isn't supposed to run faster than 14MHz

Signed-off-by: Keith Packard <keithp@keithp.com>
---

diff --git a/src/stmf0/ao_adc_stm.c b/src/stmf0/ao_adc_stm.c
index 4ba99ad7..b276c487 100644
--- a/src/stmf0/ao_adc_stm.c
+++ b/src/stmf0/ao_adc_stm.c
@@ -285,7 +285,7 @@ ao_adc_init(void)
 			 (1 << STM_ADC_CFGR1_DMAEN));				  /* enable DMA */
 
 	/* Set the clock */
-	stm_adc.cfgr2 = STM_ADC_CFGR2_CKMODE_PCLK_2 << STM_ADC_CFGR2_CKMODE;
+	stm_adc.cfgr2 = STM_ADC_CFGR2_CKMODE_PCLK_4 << STM_ADC_CFGR2_CKMODE;
 
 	/* Shortest sample time */
 	stm_adc.smpr = STM_ADC_SMPR_SMP_239_5 << STM_ADC_SMPR_SMP;