From: Maxime Coquelin Date: Fri, 11 Mar 2016 17:51:15 +0000 (+0100) Subject: stlink-common: Introduce type of flash controller enum X-Git-Url: https://git.gag.com/?a=commitdiff_plain;ds=sidebyside;h=abcd47f4216d40d1497eb4e07fc100e5979dd284;p=fw%2Fstlink stlink-common: Introduce type of flash controller enum Having a type of flash information has some advantages: - Make the code easier to read - Make adding family derivatives easier (only add a new entry in header file) - Make the backends error propagation easier to implement (less places to fix) Signed-off-by: Maxime Coquelin --- diff --git a/src/stlink-common.c b/src/stlink-common.c index fd9baba..f15738e 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -183,15 +183,17 @@ static inline uint32_t read_flash_obr(stlink_t *sl) { } static inline uint32_t read_flash_cr(stlink_t *sl) { - uint32_t res; - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||(sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) - stlink_read_debug32(sl, FLASH_F4_CR, &res); - else if (sl->chip_id == STM32_CHIPID_L4) - stlink_read_debug32(sl, STM32L4_FLASH_CR, &res); + uint32_t reg, res; + + if (sl->flash_type == FLASH_TYPE_F4) + reg = FLASH_F4_CR; + else if (sl->flash_type == FLASH_TYPE_L4) + reg = STM32L4_FLASH_CR; else - stlink_read_debug32(sl, FLASH_CR, &res); + reg = FLASH_CR; + + stlink_read_debug32(sl, reg, &res); + #if DEBUG_FLASH fprintf(stdout, "CR:0x%x\n", res); #endif @@ -200,37 +202,34 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ - uint32_t cr = read_flash_cr(sl); + uint32_t cr_lock_shift, cr = read_flash_cr(sl); - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) - return cr & (1 << FLASH_F4_CR_LOCK); - else if (sl->chip_id == STM32_CHIPID_L4) - return cr & (1lu << STM32L4_FLASH_CR_LOCK); + if (sl->flash_type == FLASH_TYPE_F4) + cr_lock_shift = FLASH_F4_CR_LOCK; + else if (sl->flash_type == FLASH_TYPE_L4) + cr_lock_shift = STM32L4_FLASH_CR_LOCK; else - return cr & (1 << FLASH_CR_LOCK); + cr_lock_shift = FLASH_CR_LOCK; + + return cr & (1 << cr_lock_shift); } static void unlock_flash(stlink_t *sl) { + uint32_t key_reg; /* the unlock sequence consists of 2 write cycles where 2 key values are written to the FLASH_KEYR register. an invalid sequence results in a definitive lock of the FPEC block until next reset. */ - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { - stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); - stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); - } else if (sl->chip_id == STM32_CHIPID_L4) { - stlink_write_debug32(sl, STM32L4_FLASH_KEYR, FLASH_KEY1); - stlink_write_debug32(sl, STM32L4_FLASH_KEYR, FLASH_KEY2); - } else { - stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1); - stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2); - } + if (sl->flash_type == FLASH_TYPE_F4) + key_reg = FLASH_F4_KEYR; + else if (sl->flash_type == FLASH_TYPE_L4) + key_reg = STM32L4_FLASH_KEYR; + else + key_reg = FLASH_KEYR; + stlink_write_debug32(sl, key_reg, FLASH_KEY1); + stlink_write_debug32(sl, key_reg, FLASH_KEY2); } static int unlock_flash_if(stlink_t *sl) { @@ -248,48 +247,56 @@ static int unlock_flash_if(stlink_t *sl) { } static void lock_flash(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { - const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); - stlink_write_debug32(sl, FLASH_F4_CR, n); - } else if (sl->chip_id == STM32_CHIPID_L4) { - const uint32_t n = read_flash_cr(sl) | (1lu << STM32L4_FLASH_CR_LOCK); - stlink_write_debug32(sl, STM32L4_FLASH_CR, n); + uint32_t cr_lock_shift, cr_reg, n; + + if (sl->flash_type == FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_lock_shift = STM32L4_FLASH_CR_LOCK; + } else if (sl->flash_type == FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_lock_shift = STM32L4_FLASH_CR_LOCK; } else { - /* write to 1 only. reset by hw at unlock sequence */ - const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK); - stlink_write_debug32(sl, FLASH_CR, n); + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; } + + n = read_flash_cr(sl) | (1 << cr_lock_shift); + stlink_write_debug32(sl, cr_reg, n); } static void set_flash_cr_pg(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { - uint32_t x = read_flash_cr(sl); - x |= (1 << FLASH_CR_PG); - stlink_write_debug32(sl, FLASH_F4_CR, x); - } else if (sl->chip_id == STM32_CHIPID_L4) { - uint32_t x = read_flash_cr(sl); - x &=~ STM32L4_FLASH_CR_OPBITS; - x |= (1 << STM32L4_FLASH_CR_PG); - stlink_write_debug32(sl, STM32L4_FLASH_CR, x); + uint32_t cr_reg, x; + + x = read_flash_cr(sl); + + if (sl->flash_type == FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + x &= ~STM32L4_FLASH_CR_OPBITS; + x |= 1 << STM32L4_FLASH_CR_PG; } else { - const uint32_t n = 1 << FLASH_CR_PG; - stlink_write_debug32(sl, FLASH_CR, n); + cr_reg = FLASH_CR; + x = 1 << FLASH_CR_PG; } + + stlink_write_debug32(sl, cr_reg, x); } static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { - const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) - stlink_write_debug32(sl, FLASH_F4_CR, n); + uint32_t cr_reg, n; + + if (sl->flash_type == FLASH_TYPE_F4) + cr_reg = FLASH_F4_CR; + else if (sl->flash_type == FLASH_TYPE_L4) + cr_reg = STM32L4_FLASH_CR; else - stlink_write_debug32(sl, FLASH_CR, n); + cr_reg = FLASH_CR; + + n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); + stlink_write_debug32(sl, cr_reg, n); } static void set_flash_cr_per(stlink_t *sl) { @@ -303,57 +310,60 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { } static void set_flash_cr_mer(stlink_t *sl) { - uint32_t val; - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { - stlink_read_debug32(sl, FLASH_F4_CR, &val); - val |= 1 << FLASH_CR_MER; - stlink_write_debug32(sl, FLASH_F4_CR, val); - } else if (sl->chip_id == STM32_CHIPID_L4) { - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val &=~ STM32L4_FLASH_CR_OPBITS; - val |= (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER2); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + uint32_t val, cr_reg, cr_mer; + + if (sl->flash_type == FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_mer = 1 << FLASH_CR_MER; + } else if (sl->flash_type == FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); } else { - stlink_read_debug32(sl, FLASH_CR, &val); - val |= 1 << FLASH_CR_MER; - stlink_write_debug32(sl, FLASH_CR, val); + cr_reg = FLASH_CR; + cr_mer = 1 << FLASH_CR_MER; } + + stlink_read_debug32(sl, cr_reg, &val); + val |= cr_mer; + stlink_write_debug32(sl, cr_reg, val); } static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { - uint32_t val; - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { - stlink_read_debug32(sl, FLASH_F4_CR, &val); - val &= ~(1 << FLASH_CR_MER); - stlink_write_debug32(sl, FLASH_F4_CR, val); + uint32_t val, cr_reg, cr_mer; + + if (sl->flash_type == FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_mer = 1 << FLASH_CR_MER; + } else if (sl->flash_type == FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); } else { - stlink_read_debug32(sl, FLASH_CR, &val); - val &= ~(1 << FLASH_CR_MER); - stlink_write_debug32(sl, FLASH_CR, val); + cr_reg = FLASH_CR; + cr_mer = 1 << FLASH_CR_MER; } + + stlink_read_debug32(sl, cr_reg, &val); + val &= ~cr_mer; + stlink_write_debug32(sl, cr_reg, val); } static void set_flash_cr_strt(stlink_t *sl) { - uint32_t val; - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { - val = read_flash_cr(sl); - val |= (1 << FLASH_F4_CR_STRT); - stlink_write_debug32(sl, FLASH_F4_CR, val); - } else if (sl->chip_id == STM32_CHIPID_L4) { - val = read_flash_cr(sl); - val |= (1lu << STM32L4_FLASH_CR_STRT); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + uint32_t val, cr_reg, cr_strt; + + if (sl->flash_type == FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_strt = 1 << FLASH_F4_CR_STRT; + } else if (sl->flash_type == FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_strt = 1 << STM32L4_FLASH_CR_STRT; } else { - stlink_read_debug32(sl, FLASH_CR, &val); - val |= 1 << FLASH_CR_STRT; - stlink_write_debug32(sl, FLASH_CR, val); + cr_reg = FLASH_CR; + cr_strt = 1 << FLASH_CR_STRT; } + + stlink_read_debug32(sl, cr_reg, &val); + val |= cr_strt; + stlink_write_debug32(sl, cr_reg, val); } static inline uint32_t read_flash_acr(stlink_t *sl) { @@ -363,28 +373,31 @@ static inline uint32_t read_flash_acr(stlink_t *sl) { } static inline uint32_t read_flash_sr(stlink_t *sl) { - uint32_t res; - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) - stlink_read_debug32(sl, FLASH_F4_SR, &res); - else if (sl->chip_id == STM32_CHIPID_L4) - stlink_read_debug32(sl, STM32L4_FLASH_SR, &res); + uint32_t res, sr_reg; + + if (sl->flash_type == FLASH_TYPE_F4) + sr_reg = FLASH_F4_SR; + else if (sl->flash_type == FLASH_TYPE_L4) + sr_reg = STM32L4_FLASH_SR; else - stlink_read_debug32(sl, FLASH_SR, &res); - //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf); + sr_reg = FLASH_SR; + + stlink_read_debug32(sl, sr_reg, &res); + return res; } static inline unsigned int is_flash_busy(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) - return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); - else if (sl->chip_id == STM32_CHIPID_L4) - return read_flash_sr(sl) & (1 << STM32L4_FLASH_SR_BSY); + uint32_t sr_busy_shift; + + if (sl->flash_type == FLASH_TYPE_F4) + sr_busy_shift = FLASH_F4_SR_BSY; + else if (sl->flash_type == FLASH_TYPE_L4) + sr_busy_shift = STM32L4_FLASH_SR_BSY; else - return read_flash_sr(sl) & (1 << FLASH_SR_BSY); + sr_busy_shift = FLASH_SR_BSY; + + return read_flash_sr(sl) & (1 << sr_busy_shift); } static void wait_flash_busy(stlink_t *sl) { @@ -600,6 +613,7 @@ int stlink_load_device_params(stlink_t *sl) { } else { sl->flash_size = flash_size * 1024; } + sl->flash_type = params->flash_type; sl->flash_pgsz = params->flash_pagesize; sl->sram_size = params->sram_size; sl->sys_base = params->bootrom_base; @@ -1216,9 +1230,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)|| (sl->chip_id == STM32_CHIPID_F4_DSI)) { + if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L4) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1262,9 +1274,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) #if DEBUG_FLASH fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif - } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 - || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH - || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { + } else if (sl->flash_type == FLASH_TYPE_L0) { uint32_t val; uint32_t flash_regs_base; @@ -1332,13 +1342,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->core_id == STM32VL_CORE_ID - || sl->core_id == STM32F0_CORE_ID - || sl->chip_id == STM32_CHIPID_F3 - || sl->chip_id == STM32_CHIPID_F3_SMALL - || sl->chip_id == STM32_CHIPID_F303_HIGH - || sl->chip_id == STM32_CHIPID_F37x - || sl->chip_id == STM32_CHIPID_F334) { + } else if (sl->flash_type == FLASH_TYPE_F0) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1370,9 +1374,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } int stlink_erase_flash_mass(stlink_t *sl) { - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 - || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH - || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { + if (sl->flash_type == FLASH_TYPE_L0) { /* erase each page */ int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -1838,16 +1840,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t if (eraseonly) return 0; - if ((sl->chip_id == STM32_CHIPID_F2) || - (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || - (sl->chip_id == STM32_CHIPID_F4_HD) || - (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || - (sl->chip_id == STM32_CHIPID_F7) || - (sl->chip_id == STM32_CHIPID_L4) || - (sl->chip_id == STM32_CHIPID_F4_DSI)) { + if ((sl->flash_type == FLASH_TYPE_F4) || (sl->flash_type == FLASH_TYPE_L4)) { /* todo: check write operation */ ILOG("Starting Flash write for F2/F4/L4\n"); @@ -1907,9 +1900,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } //STM32F4END - else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 - || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH - || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { + else if (sl->flash_type == FLASH_TYPE_L0) { /* use fast word write. todo: half page. */ uint32_t val; uint32_t flash_regs_base; @@ -1984,13 +1975,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->core_id == STM32VL_CORE_ID || - sl->core_id == STM32F0_CORE_ID || - sl->chip_id == STM32_CHIPID_F3 || - sl->chip_id == STM32_CHIPID_F3_SMALL || - sl->chip_id == STM32_CHIPID_F303_HIGH || - sl->chip_id == STM32_CHIPID_F334 || - sl->chip_id == STM32_CHIPID_F37x) { + } else if (sl->flash_type == FLASH_TYPE_F0) { ILOG("Starting Flash write for VL/F0/F3 core id\n"); /* flash loader initialization */ if (init_flash_loader(sl, &fl) == -1) { @@ -2040,14 +2025,19 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* write the file in flash at addr */ int err; unsigned int num_empty, index, val; - unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 - || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH - || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff; + unsigned char erased_pattern; mapped_file_t mf = MAPPED_FILE_INITIALIZER; + if (map_file(&mf, path) == -1) { ELOG("map_file() == -1\n"); return -1; } + + if (sl->flash_type == FLASH_TYPE_L0) + erased_pattern = 0x00; + else + erased_pattern = 0xff; + index = mf.len; for(num_empty = 0; num_empty != mf.len; ++num_empty) { if (mf.base[--index] != erased_pattern) { @@ -2083,9 +2073,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 - || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH - || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { + if (sl->flash_type == FLASH_TYPE_L0) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -2096,13 +2084,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, count, 2); /* count (32 bits words) */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - } else if (sl->core_id == STM32VL_CORE_ID || - sl->core_id == STM32F0_CORE_ID || - sl->chip_id == STM32_CHIPID_F3 || - sl->chip_id == STM32_CHIPID_F3_SMALL || - sl->chip_id == STM32_CHIPID_F303_HIGH || - sl->chip_id == STM32_CHIPID_F37x || - sl->chip_id == STM32_CHIPID_F334) { + } else if (sl->flash_type == FLASH_TYPE_F0) { size_t count = size / sizeof(uint16_t); if (size % sizeof(uint16_t)) ++count; @@ -2114,10 +2096,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || - sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { - + } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L4) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; if (sl->chip_id == STM32_CHIPID_L4) { @@ -2152,10 +2131,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } /* check written byte count */ - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 - || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH - || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { - + if (sl->flash_type == FLASH_TYPE_L0) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -2165,25 +2141,14 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - } else if (sl->core_id == STM32VL_CORE_ID || - sl->core_id == STM32F0_CORE_ID || - sl->chip_id == STM32_CHIPID_F3 || - sl->chip_id == STM32_CHIPID_F3_SMALL || - sl->chip_id == STM32_CHIPID_F303_HIGH || - sl->chip_id == STM32_CHIPID_F37x || - sl->chip_id == STM32_CHIPID_F334) { - + } else if (sl->flash_type == FLASH_TYPE_F0) { stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { fprintf(stderr, "write error, count == %u\n", rr.r[2]); return -1; } - } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || - sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4) || - (sl->chip_id == STM32_CHIPID_F4_DSI)) { - + } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L4) { stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { fprintf(stderr, "write error, count == %u\n", rr.r[2]); diff --git a/src/stlink-common.h b/src/stlink-common.h index e408864..e7be10f 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -166,9 +166,17 @@ extern "C" { /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ #define C_BUF_LEN 32 + enum flash_type { + FLASH_TYPE_F0, + FLASH_TYPE_L0, + FLASH_TYPE_F4, + FLASH_TYPE_L4, + }; + typedef struct chip_params_ { uint32_t chip_id; char* description; + enum flash_type flash_type; uint32_t flash_size_reg; uint32_t flash_pagesize; uint32_t sram_size; @@ -183,6 +191,7 @@ extern "C" { //RM0385 and DS10916 document was used to find these paramaters .chip_id = STM32_CHIPID_F7, .description = "F7 device", + .flash_type = FLASH_TYPE_F4, .flash_size_reg = 0x1ff0f442, // section 41.2 .flash_pagesize = 0x800, // No flash pages .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 @@ -192,6 +201,7 @@ extern "C" { { // table 2, PM0063 .chip_id = STM32_CHIPID_F1_MEDIUM, .description = "F1 Medium-density device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, .sram_size = 0x5000, @@ -201,6 +211,7 @@ extern "C" { { // table 1, PM0059 .chip_id = STM32_CHIPID_F2, .description = "F2 device", + .flash_type = FLASH_TYPE_F4, .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/ .flash_pagesize = 0x20000, .sram_size = 0x20000, @@ -210,6 +221,7 @@ extern "C" { { // PM0063 .chip_id = STM32_CHIPID_F1_LOW, .description = "F1 Low-density device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, .sram_size = 0x2800, @@ -219,6 +231,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F4, .description = "F4 device", + .flash_type = FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ .flash_pagesize = 0x4000, .sram_size = 0x30000, @@ -228,6 +241,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F4_DSI, .description = "F46x and F47x device", + .flash_type = FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ .flash_pagesize = 0x4000, .sram_size = 0x40000, @@ -237,6 +251,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F4_HD, .description = "F42x and F43x device", + .flash_type = FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ .flash_pagesize = 0x4000, .sram_size = 0x40000, @@ -246,6 +261,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F4_LP, .description = "F4 device (low power)", + .flash_type = FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x10000, @@ -255,6 +271,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F411RE, .description = "F4 device (low power) - stm32f411re", + .flash_type = FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x20000, @@ -264,6 +281,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F4_DE, .description = "F4 device (Dynamic Efficency)", + .flash_type = FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x18000, @@ -273,6 +291,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F1_HIGH, .description = "F1 High-density device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, .sram_size = 0x10000, @@ -284,6 +303,7 @@ extern "C" { // not the sector write protection...) .chip_id = STM32_CHIPID_L1_MEDIUM, .description = "L1 Med-density device", + .flash_type = FLASH_TYPE_L0, .flash_size_reg = 0x1ff8004c, .flash_pagesize = 0x100, .sram_size = 0x4000, @@ -293,6 +313,7 @@ extern "C" { { .chip_id = STM32_CHIPID_L1_CAT2, .description = "L1 Cat.2 device", + .flash_type = FLASH_TYPE_L0, .flash_size_reg = 0x1ff8004c, .flash_pagesize = 0x100, .sram_size = 0x8000, @@ -302,6 +323,7 @@ extern "C" { { .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS, .description = "L1 Medium-Plus-density device", + .flash_type = FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/ @@ -311,6 +333,7 @@ extern "C" { { .chip_id = STM32_CHIPID_L1_HIGH, .description = "L1 High-density device", + .flash_type = FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/ @@ -320,6 +343,7 @@ extern "C" { { .chip_id = STM32_CHIPID_L152_RE, .description = "L152RE", + .flash_type = FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/ @@ -329,6 +353,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F1_CONN, .description = "F1 Connectivity line device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, .sram_size = 0x10000, @@ -338,6 +363,7 @@ extern "C" { {//Low and Medium density VL have same chipid. RM0041 25.6.1 .chip_id = STM32_CHIPID_F1_VL_MEDIUM_LOW, .description = "F1 Medium/Low-density Value Line device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, .sram_size = 0x2000,//0x1000 for low density devices @@ -348,6 +374,7 @@ extern "C" { // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. .chip_id = STM32_CHIPID_F446, .description = "F446 device", + .flash_type = FLASH_TYPE_F4, .flash_size_reg = 0x1fff7a22, .flash_pagesize = 0x20000, .sram_size = 0x20000, @@ -359,6 +386,7 @@ extern "C" { // Support based on DM00043574.pdf (RM0316) document. .chip_id = STM32_CHIPID_F3, .description = "F3 device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, .sram_size = 0xa000, @@ -370,6 +398,7 @@ extern "C" { // Support based on 303 above (37x and 30x have same memory map) .chip_id = STM32_CHIPID_F37x, .description = "F3 device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, .sram_size = 0xa000, @@ -379,6 +408,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F1_VL_HIGH, .description = "F1 High-density value line device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, .sram_size = 0x8000, @@ -388,6 +418,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F1_XL, .description = "F1 XL-density device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, .sram_size = 0x18000, @@ -399,6 +430,7 @@ extern "C" { //RM0091 document was used to find these paramaters .chip_id = STM32_CHIPID_F0_CAN, .description = "F07x device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x800, // Page sizes listed in Table 4 .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 @@ -410,6 +442,7 @@ extern "C" { //RM0091 document was used to find these paramaters .chip_id = STM32_CHIPID_F0, .description = "F0 device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 @@ -419,6 +452,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F09X, .description = "F09X device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) @@ -430,6 +464,7 @@ extern "C" { //RM0091 document was used to find these paramaters .chip_id = STM32_CHIPID_F04, .description = "F04x device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 @@ -441,6 +476,7 @@ extern "C" { //RM0091 document was used to find these paramaters .chip_id = STM32_CHIPID_F0_SMALL, .description = "F0 small device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 @@ -451,6 +487,7 @@ extern "C" { // STM32F30x .chip_id = STM32_CHIPID_F3_SMALL, .description = "F3 small device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, .sram_size = 0xa000, @@ -462,6 +499,7 @@ extern "C" { // RM0367,RM0377 documents was used to find these parameters .chip_id = STM32_CHIPID_L0, .description = "L0x3 device", + .flash_type = FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, .sram_size = 0x2000, @@ -473,6 +511,7 @@ extern "C" { // RM0364 document was used to find these parameters .chip_id = STM32_CHIPID_F334, .description = "F334 device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, .sram_size = 0x3000, @@ -484,6 +523,7 @@ extern "C" { // Support based on DM00043574.pdf (RM0316) document rev 5. .chip_id = STM32_CHIPID_F303_HIGH, .description = "F303 high density device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register .flash_pagesize = 0x800, // 4.2.1 Flash memory organization .sram_size = 0x10000, // 3.3 Embedded SRAM @@ -495,6 +535,7 @@ extern "C" { // From RM0351. .chip_id = STM32_CHIPID_L4, .description = "L4 device", + .flash_type = FLASH_TYPE_L4, .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1671) .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81) // SRAM1 is "up to" 96k in the standard Cortex-M memory map; @@ -605,6 +646,7 @@ extern "C" { #define STM32F4_FLASH_PGSZ 16384 #define STM32F4_FLASH_SIZE (128 * 1024 * 8) + enum flash_type flash_type; stm32_addr_t flash_base; size_t flash_size; size_t flash_pgsz;