From: kbongers Date: Sat, 2 Feb 2002 06:46:19 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://git.gag.com/?a=commitdiff_plain;ds=sidebyside;h=598b42eac1d08810287fc5d39e47af9eb1a26632;p=fw%2Fsdcc *** empty log message *** git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@1889 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- diff --git a/sim/ucsim/xa.src/glob.cc b/sim/ucsim/xa.src/glob.cc index 517f644b..a139c5d7 100644 --- a/sim/ucsim/xa.src/glob.cc +++ b/sim/ucsim/xa.src/glob.cc @@ -37,55 +37,18 @@ char *op_mnemonic_str[] = { "BAD_OPCODE", "ADD", "ADDC", -"SUB", -"SUBB", -"CMP", -"AND", -"OR", -"XOR", "ADDS", -"NEG", -"SEXT", -"MUL", -"DIV.w", -"DIV.d", -"DIVU.b", -"DIVU.w", -"DIVU.d", -"DA", +"AND", +"ANL", "ASL", "ASR", -"LEA", -"CPL", -"LSR", -"NORM", -"RL", -"RLC", -"RR", -"RRC", -"MOVS", -"MOVC", -"MOVX", -"PUSH", -"PUSHU", -"POP", -"POPU", -"XCH", -"SETB", -"CLR", -"MOV", -"ANL", -"ORL", -"JMP", -"CALL", -"RET", -"RETI", "BCC", "BCS", "BEQ", "BG", "BGE", "BGT", +"BKPT", "BL", "BLE", "BLT", @@ -95,20 +58,58 @@ char *op_mnemonic_str[] = { "BOV", "BPL", "BR", +"CALL", +"CJNE", +"CLR", +"CMP", +"CPL", +"DA", +"DIV_w", +"DIV_d", +"DIVU_b", +"DIVU_w", +"DIVU_d", +"DJNZ", +"FCALL", +"FJMP", "JB", "JBC", +"JMP", "JNB", -"CJNE", -"DJNZ", -"JZ", "JNZ", +"JZ", +"LEA", +"LSR", +"MOV", +"MOVC", +"MOVS", +"MOVX", +"MUL_w", +"MULU_b", +"MULU_w", +"NEG", "NOP", -"BKPT", -"TRAP", +"NORM", +"OR", +"ORL", +"POP", +"POPU", +"PUSH", +"PUSHU", "RESET", -"FCALL", -"FJMP", -"IREG", +"RET", +"RETI", +"RL", +"RLC", +"RR", +"RRC", +"SETB", +"SEXT", +"SUB", +"SUBB", +"TRAP", +"XCH", +"XOR", }; /* this is junk, but we need to keep it until main ucSim code @@ -203,8 +204,10 @@ struct xa_dis_entry disass_xa[]= { {0x0840,0xfffc,' ',3,ANL, C_BIT }, // ANL C, bit 0 0 0 0 1 0 0 0 0 1 0 0 0 0 b b {0x0850,0xfffc,' ',3,ANL, C_NOTBIT }, // ANL C, /bit 0 0 0 0 1 0 0 0 0 1 0 1 0 0 b b - {0x0850,0xfffc,' ',3,ASL, REG_REG }, // ASL Rd, Rs 1 1 0 0 S S 0 1 d d d d s s s s - /* ASR(3) */ + {0xc150,0xf300,' ',3,ASL, REG_REG }, // ASL Rd, Rs 1 1 0 0 S S 0 1 d d d d s s s s + /* 2 more ASL cases */ + {0xc250,0xf300,' ',3,ASR, REG_REG }, // ASR Rd, Rs 1 1 0 0 S S 1 0 d d d d s s s s + /* 2 more ASR cases */ {0xf000,0xff00,' ',2,BCC, REL8 }, // BCC rel8 1 1 1 1 0 0 0 0 rel8 {0xf100,0xff00,' ',2,BCS, REL8 }, // BCS rel8 1 1 1 1 0 0 0 1 rel8 {0xf300,0xff00,' ',2,BEQ, REL8 }, // BEQ rel8 1 1 1 1 0 0 1 1 rel8 @@ -225,7 +228,7 @@ struct xa_dis_entry disass_xa[]= { {0xfe00,0xff00,' ',2,BR, REL8 }, // BR rel8 1 1 1 1 1 1 1 0 rel8 {0xc500,0xff00,' ',3,CALL, REL16 }, // CALL rel16 1 1 0 0 0 1 0 1 rel16 - {0xc600,0xfff8,' ',2,CALL, IREG_ALONE }, // CALL [Rs] 1 1 0 0 0 1 1 0 0 0 0 0 0 s s s + {0xc600,0xfff8,' ',2,CALL, IREG }, // CALL [Rs] 1 1 0 0 0 1 1 0 0 0 0 0 0 s s s {0xe200,0xf708,' ',4,CJNE, REG_DIRECT_REL8}, // CJNE Rd, direct, rel8 1 1 1 0 S 0 1 0 d d d d 0 x x x {0xe300,0xff0f,' ',4,CJNE, REG_DATA8_REL8}, // CJNE Rd, data8, rel8 1 1 1 0 0 0 1 1 d d d d 0 0 0 0 @@ -233,7 +236,7 @@ struct xa_dis_entry disass_xa[]= { {0xe308,0xff8f,' ',4,CJNE, IREG_DATA8_REL8}, // CJNE [Rd], data8, rel8 1 1 1 0 0 0 1 1 0 d d d 1 0 0 0 {0xeb08,0xff8f,' ',5,CJNE, IREG_DATA16_REL8},// CJNE [Rd], data16, rel8 1 1 1 0 1 0 1 1 0 d d d 1 0 0 0 - {0x0800,0xfffc,' ',3,CLR, BIT_ALONE }, // CLR bit 0 0 0 0 1 0 0 0 0 0 0 0 0 0 b b + {0x0800,0xfffc,' ',3,CLR, BIT_ALONE }, // CLR bit 0 0 0 0 1 0 0 0 0 0 0 0 0 0 b b {0x4100,0xf700,' ',2,CMP, REG_REG }, // CMP Rd, Rs 0 1 0 0 S 0 0 1 d d d d s s s s {0x4200,0xf708,' ',2,CMP, REG_IREG }, // CMP Rd, [Rs] 0 1 0 0 S 0 1 0 d d d d 0 s s s {0x4208,0xf708,' ',2,CMP, IREG_REG }, // CMP [Rd], Rs 0 1 0 0 S 0 1 0 s s s s 1 d d d @@ -257,11 +260,8 @@ struct xa_dis_entry disass_xa[]= { {0x9d04,0xff8f,' ',6,CMP, IREGOFF16_DATA16}, // CMP [Rd+offset16], #data16 1 0 0 1 1 1 0 1 0 d d d 0 1 0 0 {0x9604,0xff8f,' ',4,CMP, DIRECT_DATA8 }, // CMP direct, #data8 1 0 0 1 0 1 1 0 0 b b b 0 1 0 0 {0x9e04,0xff8f,' ',5,CMP, DIRECT_DATA16 }, // CMP direct, #data16 1 0 0 1 0 1 1 0 0 b b b 0 1 0 0 - - {0x900c,0xf70f,' ',2,CPL, REG_ALONE }, // CPL Rd 1 0 0 1 S 0 0 0 d d d d 1 0 1 0 - - {0x9008,0xff0f,' ',2,DA, REG_ALONE }, // DA Rd 1 0 0 1 0 0 0 0 d d d d 1 0 0 0 - + {0x900c,0xf70f,' ',2,CPL, REG }, // CPL Rd 1 0 0 1 S 0 0 0 d d d d 1 0 1 0 + {0x9008,0xff0f,' ',2,DA, REG }, // DA Rd 1 0 0 1 0 0 0 0 d d d d 1 0 0 0 {0xe708,0xff00,' ',2,DIV_w, REG_REG }, // DIV.w Rd, Rs 1 1 1 0 0 1 1 1 d d d d s s s s {0xe80b,0xff0f,' ',3,DIV_w, REG_DATA8 }, // DIV.w Rd, #data8 1 1 1 0 1 0 0 0 d d d d 1 0 1 1 {0xef00,0xff10,' ',2,DIV_d, REG_REG }, // DIV.d Rd, Rs 1 1 1 0 1 1 1 1 d d d 0 s s s s @@ -340,14 +340,15 @@ struct xa_dis_entry disass_xa[]= { {0x9d06,0xff8f,' ',6, OR, IREGOFF16_DATA16}, // OR [Rd+offset16], #data16 1 0 0 1 1 1 0 1 0 d d d 0 1 1 0 {0x9606,0xff8f,' ',4, OR, DIRECT_DATA8 }, // OR direct, #data8 1 0 0 1 0 1 1 0 0 b b b 0 1 1 0 {0x9e06,0xff8f,' ',5, OR, DIRECT_DATA16 }, // OR direct, #data16 1 0 0 1 0 1 1 0 0 b b b 0 1 1 0 - /* ORL(2) */ - {0x8710,0xf7f8,' ',3, POP, DIRECT_ALONE }, // POP direct 1 0 0 0 S 1 1 1 0 0 0 1 0 d d d + {0x0860,0xfffc,' ',3, ORL, C_BIT }, // ORL C, bit 0 0 0 0 1 0 0 0 0 1 1 0 0 0 b b + {0x0870,0xfffc,' ',3, ORL, C_NOTBIT }, // ORL C, /bit 0 0 0 0 1 0 0 0 0 1 1 1 0 0 b b + {0x8710,0xf7f8,' ',3, POP, DIRECT }, // POP direct 1 0 0 0 S 1 1 1 0 0 0 1 0 d d d {0x2700,0xb700,' ',2, POP, RLIST }, // POP Rlist 0 H 1 0 S 1 1 1 rlist - {0x8700,0xf7f8,' ',3, POPU, DIRECT_ALONE }, // POPU direct 1 0 0 0 S 1 1 1 0 0 0 0 0 d d d + {0x8700,0xf7f8,' ',3, POPU, DIRECT }, // POPU direct 1 0 0 0 S 1 1 1 0 0 0 0 0 d d d {0x3700,0xb700,' ',2, POPU, RLIST }, // POPU Rlist 0 H 1 1 S 1 1 1 rlist - {0x8730,0xf7f8,' ',3, PUSH, DIRECT_ALONE }, // PUSH direct 1 0 0 0 S 1 1 1 0 0 1 1 0 d d d + {0x8730,0xf7f8,' ',3, PUSH, DIRECT }, // PUSH direct 1 0 0 0 S 1 1 1 0 0 1 1 0 d d d {0x0700,0xb700,' ',2, PUSH, RLIST }, // PUSH Rlist 0 H 0 0 S 1 1 1 rlist - {0x8720,0xf7f8,' ',3, PUSHU, DIRECT_ALONE }, // PUSHU direct 1 0 0 0 S 1 1 1 0 0 1 0 0 d d d + {0x8720,0xf7f8,' ',3, PUSHU, DIRECT }, // PUSHU direct 1 0 0 0 S 1 1 1 0 0 1 0 0 d d d {0x1700,0xb700,' ',2, PUSHU, RLIST }, // PUSHU Rlist 0 H 0 1 S 1 1 1 rlist {0xd610,0xffff,' ',2, RESET, NO_OPERANDS }, // RESET 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 0 diff --git a/sim/ucsim/xa.src/glob.h b/sim/ucsim/xa.src/glob.h index 49bb834c..d2215369 100644 --- a/sim/ucsim/xa.src/glob.h +++ b/sim/ucsim/xa.src/glob.h @@ -38,55 +38,18 @@ enum { BAD_OPCODE=0, ADD, ADDC, -SUB, -SUBB, -CMP, -AND, -OR, -XOR, ADDS, -NEG, -SEXT, -MUL, -DIV_w, -DIV_d, -DIVU_b, -DIVU_w, -DIVU_d, -DA, +AND, +ANL, ASL, ASR, -LEA, -CPL, -LSR, -NORM, -RL, -RLC, -RR, -RRC, -MOVS, -MOVC, -MOVX, -PUSH, -PUSHU, -POP, -POPU, -XCH, -SETB, -CLR, -MOV, -ANL, -ORL, -JMP, -CALL, -RET, -RETI, BCC, BCS, BEQ, BG, BGE, BGT, +BKPT, BL, BLE, BLT, @@ -96,20 +59,58 @@ BNV, BOV, BPL, BR, +CALL, +CJNE, +CLR, +CMP, +CPL, +DA, +DIV_w, +DIV_d, +DIVU_b, +DIVU_w, +DIVU_d, +DJNZ, +FCALL, +FJMP, JB, JBC, +JMP, JNB, -CJNE, -DJNZ, -JZ, JNZ, +JZ, +LEA, +LSR, +MOV, +MOVC, +MOVS, +MOVX, +MUL_w, +MULU_b, +MULU_w, +NEG, NOP, -BKPT, -TRAP, +NORM, +OR, +ORL, +POP, +POPU, +PUSH, +PUSHU, RESET, -FCALL, -FJMP, -IREG, +RET, +RETI, +RL, +RLC, +RR, +RRC, +SETB, +SEXT, +SUB, +SUBB, +TRAP, +XCH, +XOR, }; extern char *op_mnemonic_str[]; @@ -155,13 +156,13 @@ enum op_operands { IREGOFF16_DATA4, DIRECT_DATA4, - REG_ALONE, - IREG_ALONE, + REG, + IREG, BIT_ALONE, - BIT_REL8, - DIRECT_ALONE, + DIRECT, RLIST, ADDR24, + BIT_REL8, REG_REL8, DIRECT_REL8, diff --git a/sim/ucsim/xa.src/inst.cc b/sim/ucsim/xa.src/inst.cc index ed6f1f90..47920fdf 100644 --- a/sim/ucsim/xa.src/inst.cc +++ b/sim/ucsim/xa.src/inst.cc @@ -35,8 +35,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA #include "xacl.h" #include "regsxa.h" -int -cl_xa::get_reg(int word_flag, unsigned int index) +int cl_xa::get_reg(int word_flag, unsigned int index) { //if (index < 3) { /* banked */ // if (word_flag) @@ -51,19 +50,12 @@ cl_xa::get_reg(int word_flag, unsigned int index) //} } -int -cl_xa::inst_NOP(uint code, int operands) -{ - return(resGO); -} - #define RI_F0 ((code >> 4) & 0xf) #define RI_70 ((code >> 4) & 0x7) #define RI_0F (code & 0xf) #define RI_07 (code & 0x7) -int -cl_xa::inst_ADD(uint code, int operands) +int cl_xa::inst_ADD(uint code, int operands) { #undef FUNC1 #define FUNC1 add1 @@ -74,8 +66,7 @@ cl_xa::inst_ADD(uint code, int operands) return(resGO); } -int -cl_xa::inst_ADDC(uint code, int operands) +int cl_xa::inst_ADDC(uint code, int operands) { #undef FUNC1 #define FUNC1 addc1 @@ -86,40 +77,12 @@ cl_xa::inst_ADDC(uint code, int operands) return(resGO); } -int -cl_xa::inst_SUB(uint code, int operands) +int cl_xa::inst_ADDS(uint code, int operands) { -#undef FUNC1 -#define FUNC1 sub1 -#undef FUNC2 -#define FUNC2 sub2 -#include "inst_gen.cc" return(resGO); } -int -cl_xa::inst_SUBB(uint code, int operands) -{ -#undef FUNC1 -#define FUNC1 subb1 -#undef FUNC2 -#define FUNC2 subb2 -#include "inst_gen.cc" - return(resGO); -} - -int -cl_xa::inst_CMP(uint code, int operands) -{ -#undef FUNC1 -#define FUNC1 cmp1 -#undef FUNC2 -#define FUNC2 cmp2 -#include "inst_gen.cc" - return(resGO); -} -int -cl_xa::inst_AND(uint code, int operands) +int cl_xa::inst_AND(uint code, int operands) { #undef FUNC1 #define FUNC1 and1 @@ -128,279 +91,98 @@ cl_xa::inst_AND(uint code, int operands) #include "inst_gen.cc" return(resGO); } -int -cl_xa::inst_OR(uint code, int operands) -{ -#undef FUNC1 -#define FUNC1 or1 -#undef FUNC2 -#define FUNC2 or2 -#include "inst_gen.cc" - return(resGO); -} -int -cl_xa::inst_XOR(uint code, int operands) + +int cl_xa::inst_ANL(uint code, int operands) { -#undef FUNC1 -#define FUNC1 xor1 -#undef FUNC2 -#define FUNC2 xor2 -#include "inst_gen.cc" return(resGO); } -int -cl_xa::inst_ADDS(uint code, int operands) + +int cl_xa::inst_ASL(uint code, int operands) { return(resGO); } -int -cl_xa::inst_NEG(uint code, int operands) + +int cl_xa::inst_ASR(uint code, int operands) { return(resGO); } -int -cl_xa::inst_SEXT(uint code, int operands) + +int cl_xa::inst_BCC(uint code, int operands) { return(resGO); } -int -cl_xa::inst_MUL(uint code, int operands) + +int cl_xa::inst_BCS(uint code, int operands) { return(resGO); } -int -cl_xa::inst_DIV(uint code, int operands) + +int cl_xa::inst_BEQ(uint code, int operands) { + short jmpAddr = fetch1()*2; + if (get_psw() & BIT_Z) { + PC=(PC+jmpAddr)&0xfffffffe; + } return(resGO); } -int -cl_xa::inst_DA(uint code, int operands) + +int cl_xa::inst_BG(uint code, int operands) { return(resGO); } -int -cl_xa::inst_ASL(uint code, int operands) +int cl_xa::inst_BGE(uint code, int operands) { return(resGO); } -int -cl_xa::inst_ASR(uint code, int operands) +int cl_xa::inst_BGT(uint code, int operands) { return(resGO); } -int -cl_xa::inst_LEA(uint code, int operands) +int cl_xa::inst_BKPT(uint code, int operands) { return(resGO); } -int -cl_xa::inst_CPL(uint code, int operands) +int cl_xa::inst_BL(uint code, int operands) { return(resGO); } -int -cl_xa::inst_LSR(uint code, int operands) +int cl_xa::inst_BLE(uint code, int operands) { return(resGO); } -int -cl_xa::inst_NORM(uint code, int operands) +int cl_xa::inst_BLT(uint code, int operands) { return(resGO); } -int -cl_xa::inst_RL(uint code, int operands) +int cl_xa::inst_BMI(uint code, int operands) { return(resGO); } -int -cl_xa::inst_RLC(uint code, int operands) +int cl_xa::inst_BNE(uint code, int operands) { return(resGO); } -int -cl_xa::inst_RR(uint code, int operands) +int cl_xa::inst_BNV(uint code, int operands) { return(resGO); } -int -cl_xa::inst_RRC(uint code, int operands) +int cl_xa::inst_BOV(uint code, int operands) { return(resGO); } -int -cl_xa::inst_MOVS(uint code, int operands) +int cl_xa::inst_BPL(uint code, int operands) { return(resGO); } -int -cl_xa::inst_MOVC(uint code, int operands) -{ - switch (operands) { - case REG_IREGINC: - { - short srcreg = reg2(RI_07); - if (code & 0x0800) { /* word op */ - set_reg2( RI_F0, - mov2( reg2(RI_F0), - getcode2(srcreg) - ) - ); - } else { - set_reg1( RI_F0, - mov1( reg1(RI_F0), - getcode1(srcreg) - ) - ); - } - if (operands == REG_IREGINC) { - set_reg2(RI_07, srcreg+1); - } - } - break; - // fixme, 2 more - } - return(resGO); -} -int -cl_xa::inst_MOVX(uint code, int operands) -{ - return(resGO); -} -int -cl_xa::inst_PUSH(uint code, int operands) -{ - switch(operands) { - case DIRECT_ALONE: - { - unsigned short sp; - unsigned short direct_addr = ((operands & 0x7) << 8) | fetch(); - - sp = get_sp()-2; - set_sp(sp); - if (code & 0x0800) { /* word op */ - store2( sp, get_word_direct(direct_addr)); - } else { - store2( sp, get_byte_direct(direct_addr)); - } - } - break; - case RLIST: - // fixme: implement - unsigned char rlist = fetch(); - rlist = rlist; //shutup compiler - break; - } - - return(resGO); -} -int -cl_xa::inst_POP(uint code, int operands) -{ - switch(operands) { - case DIRECT_ALONE: - { - unsigned short sp; - unsigned short direct_addr = ((operands & 0x7) << 8) | fetch(); - - sp = get_sp(); - if (code & 0x0800) { /* word op */ - set_word_direct(direct_addr, get2(sp) ); - } else { - set_byte_direct(direct_addr, get2(sp) & 0xff ); - } - set_sp(sp+2); - } - break; - - case RLIST: - // fixme: implement - unsigned char rlist = fetch(); - rlist = rlist; //shutup compiler - break; - } - return(resGO); -} -int -cl_xa::inst_XCH(uint code, int operands) -{ - return(resGO); -} -int -cl_xa::inst_SETB(uint code, int operands) -{ - unsigned short bitAddr = (code&0x03 << 8) + fetch(); - // fixme: implement - bitAddr=bitAddr; - return(resGO); -} -int -cl_xa::inst_CLR(uint code, int operands) -{ - unsigned short bitAddr = (code&0x03 << 8) + fetch(); - // fixme: implement - bitAddr=bitAddr; - return(resGO); -} -int -cl_xa::inst_MOV(uint code, int operands) -{ -#undef FUNC1 -#define FUNC1 mov1 -#undef FUNC2 -#define FUNC2 mov2 -#include "inst_gen.cc" - return(resGO); -} -int -cl_xa::inst_ANL(uint code, int operands) -{ - return(resGO); -} -int -cl_xa::inst_ORL(uint code, int operands) -{ - return(resGO); -} -int -cl_xa::inst_BEQ(uint code, int operands) -{ - short jmpAddr = fetch1()*2; - if (get_psw() & BIT_Z) { - PC=(PC+jmpAddr)&0xfffffffe; - } - return(resGO); -} -int -cl_xa::inst_BR(uint code, int operands) +int cl_xa::inst_BR(uint code, int operands) { short jmpAddr = fetch1()*2; PC=(PC+jmpAddr)&0xfffffffe; return(resGO); } -int -cl_xa::inst_JMP(uint code, int operands) -{ - int jmpAddr; - switch(operands) { - case REL16: - { - jmpAddr = (signed short)fetch2()*2; - PC = (PC + jmpAddr) & 0xfffffffe; - } - break; - case IREG: - PC &= 0xff0000; - PC |= (reg2(RI_07) & 0xfffe); /* word aligned */ - break; - /* fixme 2 more... */ - } - return(resGO); -} -int -cl_xa::inst_CALL(uint code, int operands) +int cl_xa::inst_CALL(uint code, int operands) { int jmpaddr; unsigned int sp; @@ -434,48 +216,8 @@ cl_xa::inst_CALL(uint code, int operands) } return(resGO); } -int -cl_xa::inst_RET(uint code, int operands) -{ - unsigned int retaddr; - unsigned short sp; - sp = get_sp(); - retaddr = get2(sp); -#if 0 // only in huge model - retaddr |= get2(sp+2) << 16; -#endif - set_sp(sp+2); - PC = retaddr; - return(resGO); -} -int -cl_xa::inst_Bcc(uint code, int operands) -{ - return(resGO); -} -int -cl_xa::inst_JB(uint code, int operands) -{ - short bitAddr=((code&0x3)<<8) + fetch1(); - short jmpAddr = (fetch1() * 2); - if (get_bit(bitAddr)) { - PC = (PC+jmpAddr)&0xfffffe; - } - return(resGO); -} -int -cl_xa::inst_JNB(uint code, int operands) -{ - short bitAddr=((code&0x3)<<8) + fetch1(); - short jmpAddr = (fetch1() * 2); - if (!get_bit(bitAddr)) { - PC = (PC+jmpAddr)&0xfffffe; - } - return(resGO); - return(resGO); -} -int -cl_xa::inst_CJNE(uint code, int operands) + +int cl_xa::inst_CJNE(uint code, int operands) { switch(operands) { case REG_DIRECT_REL8: @@ -536,23 +278,54 @@ cl_xa::inst_CJNE(uint code, int operands) } return(resGO); } -int -cl_xa::inst_DJNZ(uint code, int operands) + +int cl_xa::inst_CLR(uint code, int operands) +{ + unsigned short bitAddr = (code&0x03 << 8) + fetch(); + // fixme: implement + bitAddr=bitAddr; + return(resGO); +} + +int cl_xa::inst_CMP(uint code, int operands) +{ +#undef FUNC1 +#define FUNC1 cmp1 +#undef FUNC2 +#define FUNC2 cmp2 +#include "inst_gen.cc" + return(resGO); +} +int cl_xa::inst_CPL(uint code, int operands) { + return(resGO); +} +int cl_xa::inst_DA(uint code, int operands) +{ + return(resGO); +} +int cl_xa::inst_DIV(uint code, int operands) +{ + return(resGO); +} + +int cl_xa::inst_DJNZ(uint code, int operands) +{ + // update N Z flags. switch(operands) { case REG_REL8: { - int addr = (fetch1() * 2); + int addr = ( ((char)fetch1()) * 2); if (code & 0x800) { // word op unsigned short tmp = mov2(0, reg2(RI_F0)-1); set_reg2(RI_F0, tmp); if (tmp != 0) - PC += addr; + PC = (PC + addr) & 0xfffffffe; } else { unsigned char tmp = mov1(0, reg1(RI_F0)-1); set_reg1(RI_F0, tmp); if (tmp != 0) - PC += addr; + PC = (PC + addr) & 0xfffffffe; } } break; @@ -579,18 +352,60 @@ cl_xa::inst_DJNZ(uint code, int operands) return(resGO); } -int -cl_xa::inst_JZ(uint code, int operands) + +int cl_xa::inst_FCALL(uint code, int operands) { - /* reg1(8) = R4L, is ACC for MCS51 compatiblility */ - short saddr = (fetch1() * 2); - if (reg1(8)==0) { - PC += saddr; + return(resGO); +} + +int cl_xa::inst_FJMP(uint code, int operands) +{ + return(resGO); +} + +int cl_xa::inst_JB(uint code, int operands) +{ + short bitAddr=((code&0x3)<<8) + fetch1(); + short jmpAddr = (fetch1() * 2); + if (get_bit(bitAddr)) { + PC = (PC+jmpAddr)&0xfffffe; + } + return(resGO); +} +int cl_xa::inst_JBC(uint code, int operands) +{ + return(resGO); +} +int cl_xa::inst_JNB(uint code, int operands) +{ + short bitAddr=((code&0x3)<<8) + fetch1(); + short jmpAddr = (fetch1() * 2); + if (!get_bit(bitAddr)) { + PC = (PC+jmpAddr)&0xfffffe; + } + return(resGO); + return(resGO); +} +int cl_xa::inst_JMP(uint code, int operands) +{ + int jmpAddr; + + switch(operands) { + case REL16: + { + jmpAddr = (signed short)fetch2()*2; + PC = (PC + jmpAddr) & 0xfffffffe; + } + break; + case IREG: + PC &= 0xff0000; + PC |= (reg2(RI_07) & 0xfffe); /* word aligned */ + break; + /* fixme 2 more... */ } return(resGO); } -int -cl_xa::inst_JNZ(uint code, int operands) +int cl_xa::inst_JNZ(uint code, int operands) { short saddr = (fetch1() * 2); /* reg1(8) = R4L, is ACC for MCS51 compatiblility */ @@ -599,21 +414,238 @@ cl_xa::inst_JNZ(uint code, int operands) } return(resGO); } -int -cl_xa::inst_BKPT(uint code, int operands) +int cl_xa::inst_JZ(uint code, int operands) +{ + /* reg1(8) = R4L, is ACC for MCS51 compatiblility */ + short saddr = (fetch1() * 2); + if (reg1(8)==0) { + PC += saddr; + } + return(resGO); +} +int cl_xa::inst_LEA(uint code, int operands) +{ + return(resGO); +} +int cl_xa::inst_LSR(uint code, int operands) +{ + return(resGO); +} +int cl_xa::inst_MOV(uint code, int operands) +{ +#undef FUNC1 +#define FUNC1 mov1 +#undef FUNC2 +#define FUNC2 mov2 +#include "inst_gen.cc" + return(resGO); +} +int cl_xa::inst_MOVC(uint code, int operands) +{ + switch (operands) { + case REG_IREGINC: + { + short srcreg = reg2(RI_07); + if (code & 0x0800) { /* word op */ + set_reg2( RI_F0, + mov2( reg2(RI_F0), + getcode2(srcreg) + ) + ); + } else { + set_reg1( RI_F0, + mov1( reg1(RI_F0), + getcode1(srcreg) + ) + ); + } + if (operands == REG_IREGINC) { + set_reg2(RI_07, srcreg+1); + } + } + break; + // fixme, 2 more + } + return(resGO); +} +int cl_xa::inst_MOVS(uint code, int operands) +{ + return(resGO); +} +int cl_xa::inst_MOVX(uint code, int operands) +{ + return(resGO); +} +int cl_xa::inst_MUL(uint code, int operands) +{ + return(resGO); +} +int cl_xa::inst_NEG(uint code, int operands) +{ + return(resGO); +} +int cl_xa::inst_NOP(uint code, int operands) +{ + return(resGO); +} +int cl_xa::inst_NORM(uint code, int operands) +{ + return(resGO); +} +int cl_xa::inst_OR(uint code, int operands) +{ +#undef FUNC1 +#define FUNC1 or1 +#undef FUNC2 +#define FUNC2 or2 +#include "inst_gen.cc" + return(resGO); +} + +int cl_xa::inst_ORL(uint code, int operands) +{ + return(resGO); +} + +int cl_xa::inst_POP(uint code, int operands) +{ + switch(operands) { + case DIRECT: + { + unsigned short sp; + unsigned short direct_addr = ((operands & 0x7) << 8) | fetch(); + + sp = get_sp(); + if (code & 0x0800) { /* word op */ + set_word_direct(direct_addr, get2(sp) ); + } else { + set_byte_direct(direct_addr, get2(sp) & 0xff ); + } + set_sp(sp+2); + } + break; + + case RLIST: + // fixme: implement + unsigned char rlist = fetch(); + rlist = rlist; //shutup compiler + break; + } + return(resGO); +} + +int cl_xa::inst_PUSH(uint code, int operands) +{ + switch(operands) { + case DIRECT: + { + unsigned short sp; + unsigned short direct_addr = ((operands & 0x7) << 8) | fetch(); + + sp = get_sp()-2; + set_sp(sp); + if (code & 0x0800) { /* word op */ + store2( sp, get_word_direct(direct_addr)); + } else { + store2( sp, get_byte_direct(direct_addr)); + } + } + break; + + case RLIST: + // fixme: implement + unsigned char rlist = fetch(); + rlist = rlist; //shutup compiler + break; + } + + return(resGO); +} +int cl_xa::inst_RESET(uint code, int operands) +{ + return(resGO); +} +int cl_xa::inst_RET(uint code, int operands) +{ + unsigned int retaddr; + unsigned short sp; + sp = get_sp(); + retaddr = get2(sp); +#if 0 // only in huge model + retaddr |= get2(sp+2) << 16; +#endif + set_sp(sp+2); + PC = retaddr; + return(resGO); +} +int cl_xa::inst_RETI(uint code, int operands) +{ + return(resGO); +} +int cl_xa::inst_RL(uint code, int operands) +{ + return(resGO); +} +int cl_xa::inst_RLC(uint code, int operands) { return(resGO); } -int -cl_xa::inst_TRAP(uint code, int operands) +int cl_xa::inst_RR(uint code, int operands) +{ + return(resGO); +} +int cl_xa::inst_RRC(uint code, int operands) +{ + return(resGO); +} +int cl_xa::inst_SETB(uint code, int operands) +{ + unsigned short bitAddr = (code&0x03 << 8) + fetch(); + // fixme: implement + bitAddr=bitAddr; + return(resGO); +} + +int cl_xa::inst_SEXT(uint code, int operands) { return(resGO); } -int -cl_xa::inst_RESET(uint code, int operands) + +int cl_xa::inst_SUB(uint code, int operands) { +#undef FUNC1 +#define FUNC1 sub1 +#undef FUNC2 +#define FUNC2 sub2 +#include "inst_gen.cc" return(resGO); } +int cl_xa::inst_SUBB(uint code, int operands) +{ +#undef FUNC1 +#define FUNC1 subb1 +#undef FUNC2 +#define FUNC2 subb2 +#include "inst_gen.cc" + return(resGO); +} +int cl_xa::inst_TRAP(uint code, int operands) +{ + return(resGO); +} +int cl_xa::inst_XCH(uint code, int operands) +{ + return(resGO); +} +int cl_xa::inst_XOR(uint code, int operands) +{ +#undef FUNC1 +#define FUNC1 xor1 +#undef FUNC2 +#define FUNC2 xor2 +#include "inst_gen.cc" + return(resGO); +} /* End of xa.src/inst.cc */ diff --git a/sim/ucsim/xa.src/inst_gen.cc b/sim/ucsim/xa.src/inst_gen.cc index cd7f2352..294a184c 100644 --- a/sim/ucsim/xa.src/inst_gen.cc +++ b/sim/ucsim/xa.src/inst_gen.cc @@ -177,7 +177,14 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA break; case REG_DATA16 : - set_reg2( RI_F0, FUNC2( reg2(RI_F0), fetch2()) ); + { + unsigned short dat = fetch2(); + //unsigned short res; + //res = FUNC2( reg2(RI_F0), dat); + //set_reg2( RI_F0, res ); +//printf("reg_data16 code=%x dat=%x, res=%x\n", code, dat, res); + set_reg2( RI_F0, FUNC2( reg2(RI_F0), dat) ); + } break; case IREGINC_DATA8 : diff --git a/sim/ucsim/xa.src/instcl.h b/sim/ucsim/xa.src/instcl.h index 5bc5f022..a6a8267e 100644 --- a/sim/ucsim/xa.src/instcl.h +++ b/sim/ucsim/xa.src/instcl.h @@ -1,55 +1,71 @@ /* xa.src/instcl.h */ - virtual int inst_NOP(uint code, int operands); virtual int inst_ADD(uint code, int operands); virtual int inst_ADDC(uint code, int operands); - virtual int inst_SUB(uint code, int operands); - virtual int inst_SUBB(uint code, int operands); - virtual int inst_CMP(uint code, int operands); - virtual int inst_AND(uint code, int operands); - virtual int inst_OR(uint code, int operands); - virtual int inst_XOR(uint code, int operands); virtual int inst_ADDS(uint code, int operands); - virtual int inst_NEG(uint code, int operands); - virtual int inst_SEXT(uint code, int operands); - virtual int inst_MUL(uint code, int operands); - virtual int inst_DIV(uint code, int operands); - virtual int inst_DA(uint code, int operands); + virtual int inst_AND(uint code, int operands); + virtual int inst_ANL(uint code, int operands); virtual int inst_ASL(uint code, int operands); virtual int inst_ASR(uint code, int operands); - virtual int inst_LEA(uint code, int operands); + virtual int inst_BCC(uint code, int operands); + virtual int inst_BCS(uint code, int operands); + virtual int inst_BEQ(uint code, int operands); + virtual int inst_BG(uint code, int operands); + virtual int inst_BGE(uint code, int operands); + virtual int inst_BGT(uint code, int operands); + virtual int inst_BKPT(uint code, int operands); + virtual int inst_BL(uint code, int operands); + virtual int inst_BLE(uint code, int operands); + virtual int inst_BLT(uint code, int operands); + virtual int inst_BMI(uint code, int operands); + virtual int inst_BNE(uint code, int operands); + virtual int inst_BNV(uint code, int operands); + virtual int inst_BOV(uint code, int operands); + virtual int inst_BPL(uint code, int operands); + virtual int inst_BR(uint code, int operands); + virtual int inst_CALL(uint code, int operands); + virtual int inst_CJNE(uint code, int operands); + virtual int inst_CLR(uint code, int operands); + virtual int inst_CMP(uint code, int operands); virtual int inst_CPL(uint code, int operands); + virtual int inst_DA(uint code, int operands); + virtual int inst_DIV(uint code, int operands); + virtual int inst_DJNZ(uint code, int operands); + virtual int inst_FCALL(uint code, int operands); + virtual int inst_FJMP(uint code, int operands); + virtual int inst_JB(uint code, int operands); + virtual int inst_JBC(uint code, int operands); + virtual int inst_JNB(uint code, int operands); + virtual int inst_JMP(uint code, int operands); + virtual int inst_JNZ(uint code, int operands); + virtual int inst_JZ(uint code, int operands); + virtual int inst_LEA(uint code, int operands); virtual int inst_LSR(uint code, int operands); + virtual int inst_MOV(uint code, int operands); + virtual int inst_MOVC(uint code, int operands); + virtual int inst_MOVS(uint code, int operands); + virtual int inst_MOVX(uint code, int operands); + virtual int inst_MUL(uint code, int operands); + virtual int inst_NEG(uint code, int operands); + virtual int inst_NOP(uint code, int operands); virtual int inst_NORM(uint code, int operands); + virtual int inst_OR(uint code, int operands); + virtual int inst_ORL(uint code, int operands); + virtual int inst_POP(uint code, int operands); + virtual int inst_PUSH(uint code, int operands); + virtual int inst_RET(uint code, int operands); + virtual int inst_RETI(uint code, int operands); + virtual int inst_RESET(uint code, int operands); virtual int inst_RL(uint code, int operands); virtual int inst_RLC(uint code, int operands); virtual int inst_RR(uint code, int operands); virtual int inst_RRC(uint code, int operands); - virtual int inst_MOVS(uint code, int operands); - virtual int inst_MOVC(uint code, int operands); - virtual int inst_MOVX(uint code, int operands); - virtual int inst_PUSH(uint code, int operands); - virtual int inst_POP(uint code, int operands); - virtual int inst_XCH(uint code, int operands); virtual int inst_SETB(uint code, int operands); - virtual int inst_CLR(uint code, int operands); - virtual int inst_MOV(uint code, int operands); - virtual int inst_ANL(uint code, int operands); - virtual int inst_ORL(uint code, int operands); - virtual int inst_BEQ(uint code, int operands); - virtual int inst_BR(uint code, int operands); - virtual int inst_JMP(uint code, int operands); - virtual int inst_CALL(uint code, int operands); - virtual int inst_RET(uint code, int operands); - virtual int inst_Bcc(uint code, int operands); - virtual int inst_JB(uint code, int operands); - virtual int inst_JNB(uint code, int operands); - virtual int inst_CJNE(uint code, int operands); - virtual int inst_DJNZ(uint code, int operands); - virtual int inst_JZ(uint code, int operands); - virtual int inst_JNZ(uint code, int operands); - virtual int inst_BKPT(uint code, int operands); + virtual int inst_SEXT(uint code, int operands); + virtual int inst_SUB(uint code, int operands); + virtual int inst_SUBB(uint code, int operands); virtual int inst_TRAP(uint code, int operands); - virtual int inst_RESET(uint code, int operands); + virtual int inst_XCH(uint code, int operands); + virtual int inst_XOR(uint code, int operands); /* End of xa.src/instcl.h */ diff --git a/sim/ucsim/xa.src/regsxa.h b/sim/ucsim/xa.src/regsxa.h index 160e1cb1..96b9281b 100644 --- a/sim/ucsim/xa.src/regsxa.h +++ b/sim/ucsim/xa.src/regsxa.h @@ -76,7 +76,7 @@ struct t_regs #define fetch1() fetch() /* get a 1 or 2 byte register */ -#define reg2(_index) get_reg(1, (_index)) +#define reg2(_index) get_reg(1, (_index<<1)) /* function in inst.cc */ #define reg1(_index) (unsigned char)get_reg(0, (_index)) #define set_byte_direct(_index, _value) { \ @@ -93,9 +93,9 @@ struct t_regs #define set_reg2(_index, _value) { \ if ((_index) < 3) { /* banked */ \ - set_word_direct((0x400+_index), _value); \ + set_word_direct((0x400+(_index<<1)), _value); \ } else { /* non-banked */ \ - set_word_direct((0x400+_index), _value); \ + set_word_direct((0x400+(_index<<1)), _value); \ } \ } @@ -121,10 +121,23 @@ struct t_regs #define get_psw() ((TYPE_UWORD)(get_word_direct(0x400+(0x80*2)))) #define set_psw(_flags) set_word_direct(0x400+(0x80*2), _flags) +// PSW bits... +#define BIT_C 0x80 +#define BIT_AC 0x40 +#define BIT_V 0x04 +#define BIT_N 0x02 +#define BIT_Z 0x01 +#define BIT_ALL (BIT_C | BIT_AC | BIT_V | BIT_N | BIT_Z) + + #if 0 -------------------------------------------------------------------- -Notes: - Register layout: +Developer Notes. + +This user guide has got the detailed information on the XA chip. + +http://www.semiconductors.philips.com/acrobat/various/XA_USER_GUIDE_1.pdf + f: {unused slot(word accessable only) for R8-R15} e: R7h,R7l Stack pointer, ptr to USP(PSW.SM=0), or SSP(PSW.SM=1) @@ -133,7 +146,7 @@ a: R5h,R5l 8: R4h,R4l below are the banked registers which mirror(B0..B3) depending on PSW.(RS0,RS1) -6: R3h,R3l  +6: R3h,R3l 4: R2h,R2l 2: R1h,R1l 0: R0h,R0l @@ -184,17 +197,9 @@ PSW Flags: Carry(C), Aux Carry(AC), Overflow(V), Negative(N), Zero(Z). Stack ptr is pre-decremented, followed by load(word operation), default SPs are set to 100H. So first PUSH would go to FEH-FFH. - +-------------------------------------------------------------------- #endif -// PSW bits... -#define BIT_C 0x80 -#define BIT_AC 0x40 -#define BIT_V 0x04 -#define BIT_N 0x02 -#define BIT_Z 0x01 -#define BIT_ALL (BIT_C | BIT_AC | BIT_V | BIT_N | BIT_Z) - #endif /* End of xa.src/regsxa.h */ diff --git a/sim/ucsim/xa.src/xa.cc b/sim/ucsim/xa.src/xa.cc index 9e65740f..75db1369 100644 --- a/sim/ucsim/xa.src/xa.cc +++ b/sim/ucsim/xa.src/xa.cc @@ -66,7 +66,7 @@ cl_xa::init(void) wmem_direct = (TYPE_UWORD *) &mem_direct[0]; /* initialize SP to 100H */ - set_reg2(7*2, 0x100); + set_reg2(7, 0x100); printf("The XA Simulator is in development, UNSTABLE, DEVELOPERS ONLY!\n"); @@ -157,7 +157,25 @@ cl_xa::longest_inst(void) } /*-------------------------------------------------------------------- -get_disasm_info - +get_disasm_info - Given an address, return information about the opcode + which resides there. + addr - address of opcode we want information on. + ret_len - return length of opcode. + ret_branch - return a character which indicates if we are + a branching opcode. Used by main app to implement "Next" + function which steps over functions. + immed_offset - return a number which represents the number of bytes + offset to where any immediate data is(tail end of opcode). Used + for printing disassembly. + operands - return a key indicating the form of the operands, + used for printing the disassembly. + mnemonic - return a key indicating the mnemonic of the instruction. + + Return value: Return the operand code formed by either the single + byte opcode or 2 bytes of the opcode for multi-byte opcodes. + + Note: Any of the return pointer parameters can be set to NULL to + indicate the caller does not want the information. |--------------------------------------------------------------------*/ int cl_xa::get_disasm_info(t_addr addr, @@ -227,7 +245,9 @@ static char *b_reg_strs[] = { "R7l", "R7h"}; /*-------------------------------------------------------------------- -disass - +disass - Disassemble an opcode. + addr - address of opcode to disassemble/print. + sep - optionally points to string(tab) to use as separator. |--------------------------------------------------------------------*/ char * cl_xa::disass(t_addr addr, char *sep) @@ -440,15 +460,15 @@ cl_xa::disass(t_addr addr, char *sep) case DIRECT_DATA4 : strcpy(parm_str, "DIRECT_DATA4"); break; - case DIRECT_ALONE : + case DIRECT : sprintf(parm_str, "0x%03x", ((code & 0x007) << 4) + get_mem(MEM_ROM, addr+2)); break; - case REG_ALONE : + case REG : sprintf(parm_str, "%s", reg_strs[((code >> 4) & 0xf)] ); break; - case IREG_ALONE : + case IREG : sprintf(parm_str, "[%s]", reg_strs[((code >> 4) & 0xf)] ); break; @@ -557,7 +577,8 @@ cl_xa::disass(t_addr addr, char *sep) } /*-------------------------------------------------------------------- - print_regs - + print_regs - Print the registers, flags and other useful information. + Used to print a status line while stepping through the code. |--------------------------------------------------------------------*/ void cl_xa::print_regs(class cl_console *con) @@ -567,7 +588,7 @@ cl_xa::print_regs(class cl_console *con) flags = get_psw(); con->dd_printf("CA---VNZ Flags: %02x ", flags); con->dd_printf("R0:%04x R1:%04x R2:%04x R3:%04x\n", - get_reg(1,0), get_reg(1,2), get_reg(1,4), get_reg(1,6)); + reg2(0), reg2(1), reg2(2), reg2(3)); con->dd_printf("%c%c---%c%c%c ", (flags & BIT_C)?'1':'0', @@ -577,18 +598,17 @@ cl_xa::print_regs(class cl_console *con) (flags & BIT_Z)?'1':'0'); con->dd_printf("R4:%04x R5:%04x R6:%04x R7(SP):%04x ES:%04x DS:%04x\n", - get_reg(1,8), get_reg(1,10), get_reg(1,12), get_reg(1,14), 0, 0); + reg2(4), reg2(5), reg2(6), reg2(7), 0, 0); print_disass(PC, con); } -/* - * Execution - */ - -int -cl_xa::exec_inst(void) +/*-------------------------------------------------------------------- + exec_inst - Called to implement simulator execution of 1 instruction + at the current PC(program counter) address. +|--------------------------------------------------------------------*/ +int cl_xa::exec_inst(void) { t_mem code1; uint code; @@ -632,46 +652,122 @@ cl_xa::exec_inst(void) return inst_ADD(code, operands); case ADDC: return inst_ADDC(code, operands); - case SUB: - return inst_SUB(code, operands); - case SUBB: - return inst_SUBB(code, operands); - case CMP: - return inst_CMP(code, operands); - case AND: - return inst_AND(code, operands); - case OR: - return inst_OR(code, operands); - case XOR: - return inst_XOR(code, operands); case ADDS: return inst_ADDS(code, operands); - case NEG: - return inst_NEG(code, operands); - case SEXT: - return inst_SEXT(code, operands); - case MUL: - return inst_MUL(code, operands); + case AND: + return inst_AND(code, operands); + case ANL: + return inst_ANL(code, operands); + case ASL: + return inst_ASL(code, operands); + case ASR: + return inst_ASR(code, operands); + case BCC: + return inst_BCC(code, operands); + case BCS: + return inst_BCS(code, operands); + case BEQ: + return inst_BEQ(code, operands); + case BG: + return inst_BG(code, operands); + case BGE: + return inst_BGE(code, operands); + case BGT: + return inst_BGT(code, operands); + case BKPT: + return inst_BKPT(code, operands); + case BL: + return inst_BL(code, operands); + case BLE: + return inst_BLE(code, operands); + case BLT: + return inst_BLT(code, operands); + case BMI: + return inst_BMI(code, operands); + case BNE: + return inst_BNE(code, operands); + case BNV: + return inst_BNV(code, operands); + case BOV: + return inst_BOV(code, operands); + case BPL: + return inst_BPL(code, operands); + case BR: + return inst_BR(code, operands); + case CALL: + return inst_CALL(code, operands); + case CJNE: + return inst_CJNE(code, operands); + case CLR: + return inst_CLR(code, operands); + case CMP: + return inst_CMP(code, operands); + case CPL: + return inst_CPL(code, operands); + case DA: + return inst_DA(code, operands); case DIV_w : case DIV_d : case DIVU_b: case DIVU_w: case DIVU_d: return inst_DIV(code, operands); - case DA: - return inst_DA(code, operands); - case ASL: - return inst_ASL(code, operands); - case ASR: - return inst_ASR(code, operands); + case DJNZ: + return inst_DJNZ(code, operands); + case FCALL: + return inst_FCALL(code, operands); + case FJMP: + return inst_FJMP(code, operands); + case JB: + return inst_JB(code, operands); + case JBC: + return inst_JBC(code, operands); + case JMP: + return inst_JMP(code, operands); + case JNB: + return inst_JNB(code, operands); + case JNZ: + return inst_JNZ(code, operands); + case JZ: + return inst_JZ(code, operands); case LEA: return inst_LEA(code, operands); - case CPL: - return inst_CPL(code, operands); case LSR: return inst_LSR(code, operands); + case MOV: + return inst_MOV(code, operands); + case MOVC: + return inst_MOVC(code, operands); + case MOVS: + return inst_MOVS(code, operands); + case MOVX: + return inst_MOVX(code, operands); + case MUL_w: + case MULU_b: + case MULU_w: + return inst_MUL(code, operands); + case NEG: + return inst_NEG(code, operands); + case NOP: + return inst_NOP(code, operands); case NORM: return inst_NORM(code, operands); + case OR: + return inst_OR(code, operands); + case ORL: + return inst_ORL(code, operands); + case POP: + case POPU: + return inst_POP(code, operands); + case PUSH: + case PUSHU: + return inst_PUSH(code, operands); + case RESET: + return inst_RESET(code, operands); + case RET: + return inst_RET(code, operands); + case RETI: + return inst_RETI(code, operands); case RL: return inst_RL(code, operands); case RLC: @@ -680,60 +776,21 @@ cl_xa::exec_inst(void) return inst_RR(code, operands); case RRC: return inst_RRC(code, operands); - case MOVS: - return inst_MOVS(code, operands); - case MOVC: - return inst_MOVC(code, operands); - case MOVX: - return inst_MOVX(code, operands); - case PUSH: - return inst_PUSH(code, operands); - case POP: - return inst_POP(code, operands); - case XCH: - return inst_XCH(code, operands); case SETB: return inst_SETB(code, operands); - case CLR: - return inst_CLR(code, operands); - case MOV: - return inst_MOV(code, operands); - case ANL: - return inst_ANL(code, operands); - case ORL: - return inst_ORL(code, operands); - case BEQ: - return inst_BEQ(code, operands); - case BR: - return inst_BR(code, operands); - case JMP: - return inst_JMP(code, operands); - case CALL: - return inst_CALL(code, operands); - case RET: - return inst_RET(code, operands); - case BCC: - return inst_Bcc(code, operands); - case JB: - return inst_JB(code, operands); - case JNB: - return inst_JNB(code, operands); - case CJNE: - return inst_CJNE(code, operands); - case DJNZ: - return inst_DJNZ(code, operands); - case JZ: - return inst_JZ(code, operands); - case JNZ: - return inst_JNZ(code, operands); - case NOP: - return inst_NOP(code, operands); - case BKPT: - return inst_BKPT(code, operands); + case SEXT: + return inst_SEXT(code, operands); + case SUB: + return inst_SUB(code, operands); + case SUBB: + return inst_SUBB(code, operands); case TRAP: return inst_TRAP(code, operands); - case RESET: - return inst_RESET(code, operands); + case XCH: + return inst_XCH(code, operands); + case XOR: + return inst_XOR(code, operands); + case BAD_OPCODE: default: break;