if (res != ERROR_OK)
return res;
+ usleep(100000);
+
/* Check to see if the NVM command resulted in an error condition. */
return samd_check_error(target);
}
assert(pg_offset + 4 * nw <= chip->page_size);
/* Word aligned data, use direct write from buffer */
+
+ uint32_t n;
+ for (n = 0; n < nw; n++) {
+ uint32_t value;
+
+ memcpy(&value, buffer + n * 4, 4);
+ res = target_write_u32(bank->target, address + n * 4, value);
+
+ if (res != ERROR_OK)
+ LOG_ERROR("%s: %d", __func__, __LINE__);
+ usleep(1000);
+ }
+
res = target_write_memory(bank->target, address, 4, nw, buffer);
}
if (res != ERROR_OK) {
/* Access through AHB is stalled while flash is being programmed */
usleep(100000);
+ /* Verify write */
+
+ {
+ uint32_t n;
+
+ for (n = 0; n < nb; n += 4) {
+ uint32_t got, should;
+
+ memcpy(&should, buffer + n, 4);
+ res = target_read_u32(bank->target, address + n, &got);
+
+ if (res != ERROR_OK)
+ LOG_ERROR("%s: %d", __func__, __LINE__);
+
+ if (got != should) {
+ LOG_ERROR("address 0x%08" PRIx32 " wrote 0x%08" PRIx32 " got 0x%08x" PRIx32,
+ address + n, should, got);
+ }
+ }
+ }
+
/* We're done with the page contents */
count -= nb;
offset += nb;