Merge branch 'wip/wbxng' of git@gnuradio.org:jcorgan

* 'wip/wbxng' of git@gnuradio.org:jcorgan:
  Clean up for work-in-progress
  Integrated gain control for TX and RX of wbxng
  Enabled RX Baseband
  First Functional TX modulator
  Locking, controllable synthesizer on TX and RX
  Able to tune RX VCO, observe R and N divider output on MUXOUT
  twiddling gpio successfully
  Clean build
  Initial compile of wbxng, properly sets db IDs

diff --git a/usrp/host/include/usrp/db_wbxng.h b/usrp/host/include/usrp/db_wbxng.h
index 2158face2e77eb15077ccaf0f61254f3938b4bfb..8611d4787debec97b1c56d03310d01bce1189cf5 100644 (file)
--- a/usrp/host/include/usrp/db_wbxng.h
+++ b/usrp/host/include/usrp/db_wbxng.h
@@ -41,12 +41,6 @@ public:
 
 protected:
   bool _lock_detect();
-
-  //virtual bool _compute_regs(double freq, int &retR, int &retcontrol, int &retN, double &retfreq);
-  int  _compute_control_reg();
-  int _refclk_divisor();
-  double _refclk_freq();
-
   bool _set_pga(float pga_gain);
 
   int power_on() { return d_power_on; }

diff --git a/usrp/host/lib/db_wbxng.cc b/usrp/host/lib/db_wbxng.cc
index c23fc47edf290b2310b862cd37b4cf2aaa6b4bfc..38c3a28860b7652b777353d5a185622c486eb1c3 100644 (file)
--- a/usrp/host/lib/db_wbxng.cc
+++ b/usrp/host/lib/db_wbxng.cc
@@ -86,7 +86,7 @@ wbxng_base::set_freq(double freq)
   nanosleep(&t, NULL);
 
   fprintf(stderr,"Setting WBXNG frequency, requested %d, obtained %f, lock_detect %d\n",
-          int_freq, freq_result, _lock_detect());
+          int_freq, freq_result, d_common->_get_locked());
 
   // FIXME
   // Offsetting the LO helps get the Tx carrier leakage out of the way.

diff --git a/usrp2/fpga/control_lib/newfifo/fifo_2clock.v b/usrp2/fpga/control_lib/newfifo/fifo_2clock.v
index 07ae090f2648b1598adc5db29f530287d14a8350..34c85ccb4dc71410d0c9cffd3b0a6acbcb1998da 100644 (file)
--- a/usrp2/fpga/control_lib/newfifo/fifo_2clock.v
+++ b/usrp2/fpga/control_lib/newfifo/fifo_2clock.v
@@ -19,28 +19,28 @@ module fifo_2clock
       if(WIDTH==36)
        if(SIZE==9)
          fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
-              (.rst(rst),
+              (.rst(arst),
                .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
                .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
        else if(SIZE==11)
          fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk 
-                    (.rst(rst),
+                    (.rst(arst),
                      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
                      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
        else if(SIZE==6)
          fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk 
-                    (.rst(rst),
+                    (.rst(arst),
                      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
                      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
        else
          fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
-              (.rst(rst),
+              (.rst(arst),
                .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
                .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
       else if((WIDTH==19)|(WIDTH==18))
        if(SIZE==4)
          fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk
-                    (.rst(rst),
+                    (.rst(arst),
                      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
                      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
    endgenerate