+2005-04-01 Erik Petrich <epetrich AT ivorytower.norman.ok.us>
+
+ * device/include/Makefile.in: add support for hc08 subdirectory
+ * device/include/hc08/: new subdirectory
+ * device/include/hc08/mc68hc908jkjl.h: new header contributed by
+ Lucas Loizaga, thanks!
+ * device/include/hc08/mc68hc908qy.h,
+ * device/include/hc08/mc68hc908gp32.h,
+ * device/include/hc08/mc68hc908jb8.h: moved hc08 register defs to
+ their own directory. Changed internal macro names to use the compiler
+ reserved namespace. Changed SDCC specific keywords to double
+ underlined form.
+ * device/include/math.h,
+ * device/include/malloc.h,
+ * device/include/stdarg.h,
+ * device/include/stdbool.h
+ * device/include/string.h,
+ * device/include/tinibios.h,
+ * device/include/ds400rom.h,
+ * device/include/8051.h,
+ * device/include/8052.h,
+ * device/include/80c51xa.h,
+ * device/include/at89c55.h,
+ * device/include/at89S8252.h,
+ * device/include/at89x51.h,
+ * device/include/at89x52.h,
+ * device/include/ds80c390.h,
+ * device/include/reg764.h,
+ * device/include/regc515c.h,
+ * device/include/sab80515.h,
+ * device/include/mcs51/c8051f000.h,
+ * device/include/mcs51/c8051f018.h,
+ * device/include/mcs51/c8051f020.h,
+ * device/include/mcs51/c8051f040.h,
+ * device/include/mcs51/c8051f060.h,
+ * device/include/mcs51/c8051f120.h,
+ * device/include/mcs51/c8051f300.h,
+ * device/include/mcs51/c8051f310.h,
+ * device/include/mcs51/c8051f320.h,
+ * device/include/mcs51/c8051f330.h,
+ * device/include/mcs51/c8051f350.h,
+ * device/include/z180.h: Changed SDCC specific keywords to double
+ underlined form.
+
2005-03-31 Vangelis Rokas <vrokas AT users.sourceforge.net>
* src/pic16/device.c (Pics16[]): added devices 18F2550, 18F4331,
#define REG8051_H
/* BYTE Register */
-sfr at 0x80 P0 ;
-sfr at 0x81 SP ;
-sfr at 0x82 DPL ;
-sfr at 0x83 DPH ;
-sfr at 0x87 PCON ;
-sfr at 0x88 TCON ;
-sfr at 0x89 TMOD ;
-sfr at 0x8A TL0 ;
-sfr at 0x8B TL1 ;
-sfr at 0x8C TH0 ;
-sfr at 0x8D TH1 ;
-sfr at 0x90 P1 ;
-sfr at 0x98 SCON ;
-sfr at 0x99 SBUF ;
-sfr at 0xA0 P2 ;
-sfr at 0xA8 IE ;
-sfr at 0xB0 P3 ;
-sfr at 0xB8 IP ;
-sfr at 0xD0 PSW ;
-sfr at 0xE0 ACC ;
-sfr at 0xF0 B ;
+__sfr __at 0x80 P0 ;
+__sfr __at 0x81 SP ;
+__sfr __at 0x82 DPL ;
+__sfr __at 0x83 DPH ;
+__sfr __at 0x87 PCON ;
+__sfr __at 0x88 TCON ;
+__sfr __at 0x89 TMOD ;
+__sfr __at 0x8A TL0 ;
+__sfr __at 0x8B TL1 ;
+__sfr __at 0x8C TH0 ;
+__sfr __at 0x8D TH1 ;
+__sfr __at 0x90 P1 ;
+__sfr __at 0x98 SCON ;
+__sfr __at 0x99 SBUF ;
+__sfr __at 0xA0 P2 ;
+__sfr __at 0xA8 IE ;
+__sfr __at 0xB0 P3 ;
+__sfr __at 0xB8 IP ;
+__sfr __at 0xD0 PSW ;
+__sfr __at 0xE0 ACC ;
+__sfr __at 0xF0 B ;
/* BIT Register */
/* P0 */
-sbit at 0x80 P0_0 ;
-sbit at 0x81 P0_1 ;
-sbit at 0x82 P0_2 ;
-sbit at 0x83 P0_3 ;
-sbit at 0x84 P0_4 ;
-sbit at 0x85 P0_5 ;
-sbit at 0x86 P0_6 ;
-sbit at 0x87 P0_7 ;
+__sbit __at 0x80 P0_0 ;
+__sbit __at 0x81 P0_1 ;
+__sbit __at 0x82 P0_2 ;
+__sbit __at 0x83 P0_3 ;
+__sbit __at 0x84 P0_4 ;
+__sbit __at 0x85 P0_5 ;
+__sbit __at 0x86 P0_6 ;
+__sbit __at 0x87 P0_7 ;
/* TCON */
-sbit at 0x88 IT0 ;
-sbit at 0x89 IE0 ;
-sbit at 0x8A IT1 ;
-sbit at 0x8B IE1 ;
-sbit at 0x8C TR0 ;
-sbit at 0x8D TF0 ;
-sbit at 0x8E TR1 ;
-sbit at 0x8F TF1 ;
+__sbit __at 0x88 IT0 ;
+__sbit __at 0x89 IE0 ;
+__sbit __at 0x8A IT1 ;
+__sbit __at 0x8B IE1 ;
+__sbit __at 0x8C TR0 ;
+__sbit __at 0x8D TF0 ;
+__sbit __at 0x8E TR1 ;
+__sbit __at 0x8F TF1 ;
/* P1 */
-sbit at 0x90 P1_0 ;
-sbit at 0x91 P1_1 ;
-sbit at 0x92 P1_2 ;
-sbit at 0x93 P1_3 ;
-sbit at 0x94 P1_4 ;
-sbit at 0x95 P1_5 ;
-sbit at 0x96 P1_6 ;
-sbit at 0x97 P1_7 ;
+__sbit __at 0x90 P1_0 ;
+__sbit __at 0x91 P1_1 ;
+__sbit __at 0x92 P1_2 ;
+__sbit __at 0x93 P1_3 ;
+__sbit __at 0x94 P1_4 ;
+__sbit __at 0x95 P1_5 ;
+__sbit __at 0x96 P1_6 ;
+__sbit __at 0x97 P1_7 ;
/* SCON */
-sbit at 0x98 RI ;
-sbit at 0x99 TI ;
-sbit at 0x9A RB8 ;
-sbit at 0x9B TB8 ;
-sbit at 0x9C REN ;
-sbit at 0x9D SM2 ;
-sbit at 0x9E SM1 ;
-sbit at 0x9F SM0 ;
+__sbit __at 0x98 RI ;
+__sbit __at 0x99 TI ;
+__sbit __at 0x9A RB8 ;
+__sbit __at 0x9B TB8 ;
+__sbit __at 0x9C REN ;
+__sbit __at 0x9D SM2 ;
+__sbit __at 0x9E SM1 ;
+__sbit __at 0x9F SM0 ;
/* P2 */
-sbit at 0xA0 P2_0 ;
-sbit at 0xA1 P2_1 ;
-sbit at 0xA2 P2_2 ;
-sbit at 0xA3 P2_3 ;
-sbit at 0xA4 P2_4 ;
-sbit at 0xA5 P2_5 ;
-sbit at 0xA6 P2_6 ;
-sbit at 0xA7 P2_7 ;
+__sbit __at 0xA0 P2_0 ;
+__sbit __at 0xA1 P2_1 ;
+__sbit __at 0xA2 P2_2 ;
+__sbit __at 0xA3 P2_3 ;
+__sbit __at 0xA4 P2_4 ;
+__sbit __at 0xA5 P2_5 ;
+__sbit __at 0xA6 P2_6 ;
+__sbit __at 0xA7 P2_7 ;
/* IE */
-sbit at 0xA8 EX0 ;
-sbit at 0xA9 ET0 ;
-sbit at 0xAA EX1 ;
-sbit at 0xAB ET1 ;
-sbit at 0xAC ES ;
-sbit at 0xAF EA ;
+__sbit __at 0xA8 EX0 ;
+__sbit __at 0xA9 ET0 ;
+__sbit __at 0xAA EX1 ;
+__sbit __at 0xAB ET1 ;
+__sbit __at 0xAC ES ;
+__sbit __at 0xAF EA ;
/* P3 */
-sbit at 0xB0 P3_0 ;
-sbit at 0xB1 P3_1 ;
-sbit at 0xB2 P3_2 ;
-sbit at 0xB3 P3_3 ;
-sbit at 0xB4 P3_4 ;
-sbit at 0xB5 P3_5 ;
-sbit at 0xB6 P3_6 ;
-sbit at 0xB7 P3_7 ;
-
-sbit at 0xB0 RXD ;
-sbit at 0xB1 TXD ;
-sbit at 0xB2 INT0 ;
-sbit at 0xB3 INT1 ;
-sbit at 0xB4 T0 ;
-sbit at 0xB5 T1 ;
-sbit at 0xB6 WR ;
-sbit at 0xB7 RD ;
+__sbit __at 0xB0 P3_0 ;
+__sbit __at 0xB1 P3_1 ;
+__sbit __at 0xB2 P3_2 ;
+__sbit __at 0xB3 P3_3 ;
+__sbit __at 0xB4 P3_4 ;
+__sbit __at 0xB5 P3_5 ;
+__sbit __at 0xB6 P3_6 ;
+__sbit __at 0xB7 P3_7 ;
+
+__sbit __at 0xB0 RXD ;
+__sbit __at 0xB1 TXD ;
+__sbit __at 0xB2 INT0 ;
+__sbit __at 0xB3 INT1 ;
+__sbit __at 0xB4 T0 ;
+__sbit __at 0xB5 T1 ;
+__sbit __at 0xB6 WR ;
+__sbit __at 0xB7 RD ;
/* IP */
-sbit at 0xB8 PX0 ;
-sbit at 0xB9 PT0 ;
-sbit at 0xBA PX1 ;
-sbit at 0xBB PT1 ;
-sbit at 0xBC PS ;
+__sbit __at 0xB8 PX0 ;
+__sbit __at 0xB9 PT0 ;
+__sbit __at 0xBA PX1 ;
+__sbit __at 0xBB PT1 ;
+__sbit __at 0xBC PS ;
/* PSW */
-sbit at 0xD0 P ;
-sbit at 0xD1 F1 ;
-sbit at 0xD2 OV ;
-sbit at 0xD3 RS0 ;
-sbit at 0xD4 RS1 ;
-sbit at 0xD5 F0 ;
-sbit at 0xD6 AC ;
-sbit at 0xD7 CY ;
+__sbit __at 0xD0 P ;
+__sbit __at 0xD1 F1 ;
+__sbit __at 0xD2 OV ;
+__sbit __at 0xD3 RS0 ;
+__sbit __at 0xD4 RS1 ;
+__sbit __at 0xD5 F0 ;
+__sbit __at 0xD6 AC ;
+__sbit __at 0xD7 CY ;
/* BIT definitions for bits that are not directly accessible */
/* PCON bits */
/* define 8052 specific registers only */
/* T2CON */
-sfr at 0xC8 T2CON ;
+__sfr __at 0xC8 T2CON ;
/* RCAP2 L & H */
-sfr at 0xCA RCAP2L ;
-sfr at 0xCB RCAP2H ;
-sfr at 0xCC TL2 ;
-sfr at 0xCD TH2 ;
+__sfr __at 0xCA RCAP2L ;
+__sfr __at 0xCB RCAP2H ;
+__sfr __at 0xCC TL2 ;
+__sfr __at 0xCD TH2 ;
/* IE */
-sbit at 0xAD ET2 ; /* Enable timer2 interrupt */
+__sbit __at 0xAD ET2 ; /* Enable timer2 interrupt */
/* T2CON bits */
-sbit at 0xC8 T2CON_0 ;
-sbit at 0xC9 T2CON_1 ;
-sbit at 0xCA T2CON_2 ;
-sbit at 0xCB T2CON_3 ;
-sbit at 0xCC T2CON_4 ;
-sbit at 0xCD T2CON_5 ;
-sbit at 0xCE T2CON_6 ;
-sbit at 0xCF T2CON_7 ;
+__sbit __at 0xC8 T2CON_0 ;
+__sbit __at 0xC9 T2CON_1 ;
+__sbit __at 0xCA T2CON_2 ;
+__sbit __at 0xCB T2CON_3 ;
+__sbit __at 0xCC T2CON_4 ;
+__sbit __at 0xCD T2CON_5 ;
+__sbit __at 0xCE T2CON_6 ;
+__sbit __at 0xCF T2CON_7 ;
-sbit at 0xC8 CP_RL2 ;
-sbit at 0xC9 C_T2 ;
-sbit at 0xCA TR2 ;
-sbit at 0xCB EXEN2 ;
-sbit at 0xCC TCLK ;
-sbit at 0xCD RCLK ;
-sbit at 0xCE EXF2 ;
-sbit at 0xCF TF2 ;
+__sbit __at 0xC8 CP_RL2 ;
+__sbit __at 0xC9 C_T2 ;
+__sbit __at 0xCA TR2 ;
+__sbit __at 0xCB EXEN2 ;
+__sbit __at 0xCC TCLK ;
+__sbit __at 0xCD RCLK ;
+__sbit __at 0xCE EXF2 ;
+__sbit __at 0xCF TF2 ;
#endif
#ifndef XA_H
#define XA_H
-sfr at 0x400 /*unsigned short*/ PSW; /* Program status word */
-sfr at 0x400 PSWL; /* Program status word (low byte) */
-sfr at 0x401 PSWH; /* Program status word (high byte) */
-sfr at 0x402 PSW51; /* 80C51 compatible PSW */
-sfr at 0x403 SSEL; /* Segment selection register */
-sfr at 0x404 PCON; /* Power control register */
-sfr at 0x410 TCON; /* Timer 0 and 1 control register */
-sfr at 0x411 TSTAT; /* Timer 0 and 1 extended status */
-sfr at 0x418 T2CON; /* Timer 2 control register */
-sfr at 0x419 T2MOD; /* Timer 2 mode control */
-sfr at 0x41F WDCON; /* Watchdog control register */
-sfr at 0x420 S0CON; /* Serial port 0 control register */
-sfr at 0x421 S0STAT; /* Serial port 0 extended status */
-sfr at 0x424 S1CON; /* Serial port 1 control register */
-sfr at 0x425 S1STAT; /* Serial port 1 extended status */
-sfr at 0x426 IEL; /* Interrupt enable low byte */
-sfr at 0x427 IEH; /* Interrupt enable high byte */
-sfr at 0x42A SWR; /* Software Interrupt Request */
-sfr at 0x430 P0; /* Port 0 */
-sfr at 0x431 P1; /* Port 1 */
-sfr at 0x432 P2; /* Port 2 */
-sfr at 0x433 P3; /* Port3 */
-sfr at 0x440 SCR; /* System configuration register */
-sfr at 0x441 DS; /* Data segment */
-sfr at 0x442 ES; /* Extra segment */
-sfr at 0x443 CS; /* Code segment */
-sfr at 0x450 TL0; /* Timer 0 low byte */
-sfr at 0x451 TH0; /* Timer 0 high byte */
-sfr at 0x452 TL1; /* Timer 1 low byte */
-sfr at 0x453 TH1; /* Timer 1 high byte */
-sfr at 0x454 RTL0; /* Timer 0 extended reload, low byte */
-sfr at 0x455 RTH0; /* Timer 0 extended reload, high byte */
-sfr at 0x456 RTL1; /* Timer 1 extended reload, low byte */
-sfr at 0x457 RTH1; /* Timer 1 extended reload, high byte */
-sfr at 0x458 TL2; /* Timer 2 low byte */
-sfr at 0x459 TH2; /* Timer 2 high byte */
-sfr at 0x45A T2CAPL; /* Timer 2 capture register, low byte */
-sfr at 0x45B T2CAPH; /* Timer 2 capture register, high byte */
-sfr at 0x45C TMOD; /* Timer 0 and 1 mode register */
-sfr at 0x45D WFEED1; /* Watchdog feed 1 */
-sfr at 0x45E WFEED2; /* Watchdog feed 2 */
-sfr at 0x45F WDL; /* Watchdog timer reload */
-sfr at 0x460 S0BUF; /* Serial port 0 buffer register */
-sfr at 0x461 S0ADDR; /* Serial port 0 address register */
-sfr at 0x462 S0ADEN; /* Serial port 0 address enable register */
-sfr at 0x464 S1BUF; /* Serial port 1 buffer register */
-sfr at 0x465 S1ADDR; /* Serial port 1 address register */
-sfr at 0x466 S1ADEN; /* Serial port 1 address enable register */
-sfr at 0x468 BTRL; /* Bus timing register high byte */
-sfr at 0x469 BTRH; /* Bus timing register low byte */
-sfr at 0x46A BCR; /* Bus configuration register */
-sfr at 0x470 P0CFGA; /* Port 0 configuration A */
-sfr at 0x471 P1CFGA; /* Port 1 configuration A */
-sfr at 0x472 P2CFGA; /* Port 2 configuration A */
-sfr at 0x473 P3CFGA; /* Port 3 configuration A */
-sfr at 0x47A SWE; /* Software Interrupt Enable */
-sfr at 0x4A0 IPA0; /* Interrupt priority 0 */
-sfr at 0x4A1 IPA1; /* Interrupt priority 1 */
-sfr at 0x4A2 IPA2; /* Interrupt priority 2 */
-sfr at 0x4A4 IPA4; /* Interrupt priority 4 */
-sfr at 0x4A5 IPA5; /* Interrupt priority 5 */
-sfr at 0x4F0 P0CFGB; /* Port 0 configuration B */
-sfr at 0x4F1 P1CFGB; /* Port 1 configuration B */
-sfr at 0x4F2 P2CFGB; /* Port 2 configuration B */
-sfr at 0x4F3 P3CFGB; /* Port 3 configuration B */
+__sfr __at 0x400 /*unsigned short*/ PSW; /* Program status word */
+__sfr __at 0x400 PSWL; /* Program status word (low byte) */
+__sfr __at 0x401 PSWH; /* Program status word (high byte) */
+__sfr __at 0x402 PSW51; /* 80C51 compatible PSW */
+__sfr __at 0x403 SSEL; /* Segment selection register */
+__sfr __at 0x404 PCON; /* Power control register */
+__sfr __at 0x410 TCON; /* Timer 0 and 1 control register */
+__sfr __at 0x411 TSTAT; /* Timer 0 and 1 extended status */
+__sfr __at 0x418 T2CON; /* Timer 2 control register */
+__sfr __at 0x419 T2MOD; /* Timer 2 mode control */
+__sfr __at 0x41F WDCON; /* Watchdog control register */
+__sfr __at 0x420 S0CON; /* Serial port 0 control register */
+__sfr __at 0x421 S0STAT; /* Serial port 0 extended status */
+__sfr __at 0x424 S1CON; /* Serial port 1 control register */
+__sfr __at 0x425 S1STAT; /* Serial port 1 extended status */
+__sfr __at 0x426 IEL; /* Interrupt enable low byte */
+__sfr __at 0x427 IEH; /* Interrupt enable high byte */
+__sfr __at 0x42A SWR; /* Software Interrupt Request */
+__sfr __at 0x430 P0; /* Port 0 */
+__sfr __at 0x431 P1; /* Port 1 */
+__sfr __at 0x432 P2; /* Port 2 */
+__sfr __at 0x433 P3; /* Port3 */
+__sfr __at 0x440 SCR; /* System configuration register */
+__sfr __at 0x441 DS; /* Data segment */
+__sfr __at 0x442 ES; /* Extra segment */
+__sfr __at 0x443 CS; /* Code segment */
+__sfr __at 0x450 TL0; /* Timer 0 low byte */
+__sfr __at 0x451 TH0; /* Timer 0 high byte */
+__sfr __at 0x452 TL1; /* Timer 1 low byte */
+__sfr __at 0x453 TH1; /* Timer 1 high byte */
+__sfr __at 0x454 RTL0; /* Timer 0 extended reload, low byte */
+__sfr __at 0x455 RTH0; /* Timer 0 extended reload, high byte */
+__sfr __at 0x456 RTL1; /* Timer 1 extended reload, low byte */
+__sfr __at 0x457 RTH1; /* Timer 1 extended reload, high byte */
+__sfr __at 0x458 TL2; /* Timer 2 low byte */
+__sfr __at 0x459 TH2; /* Timer 2 high byte */
+__sfr __at 0x45A T2CAPL; /* Timer 2 capture register, low byte */
+__sfr __at 0x45B T2CAPH; /* Timer 2 capture register, high byte */
+__sfr __at 0x45C TMOD; /* Timer 0 and 1 mode register */
+__sfr __at 0x45D WFEED1; /* Watchdog feed 1 */
+__sfr __at 0x45E WFEED2; /* Watchdog feed 2 */
+__sfr __at 0x45F WDL; /* Watchdog timer reload */
+__sfr __at 0x460 S0BUF; /* Serial port 0 buffer register */
+__sfr __at 0x461 S0ADDR; /* Serial port 0 address register */
+__sfr __at 0x462 S0ADEN; /* Serial port 0 address enable register */
+__sfr __at 0x464 S1BUF; /* Serial port 1 buffer register */
+__sfr __at 0x465 S1ADDR; /* Serial port 1 address register */
+__sfr __at 0x466 S1ADEN; /* Serial port 1 address enable register */
+__sfr __at 0x468 BTRL; /* Bus timing register high byte */
+__sfr __at 0x469 BTRH; /* Bus timing register low byte */
+__sfr __at 0x46A BCR; /* Bus configuration register */
+__sfr __at 0x470 P0CFGA; /* Port 0 configuration A */
+__sfr __at 0x471 P1CFGA; /* Port 1 configuration A */
+__sfr __at 0x472 P2CFGA; /* Port 2 configuration A */
+__sfr __at 0x473 P3CFGA; /* Port 3 configuration A */
+__sfr __at 0x47A SWE; /* Software Interrupt Enable */
+__sfr __at 0x4A0 IPA0; /* Interrupt priority 0 */
+__sfr __at 0x4A1 IPA1; /* Interrupt priority 1 */
+__sfr __at 0x4A2 IPA2; /* Interrupt priority 2 */
+__sfr __at 0x4A4 IPA4; /* Interrupt priority 4 */
+__sfr __at 0x4A5 IPA5; /* Interrupt priority 5 */
+__sfr __at 0x4F0 P0CFGB; /* Port 0 configuration B */
+__sfr __at 0x4F1 P1CFGB; /* Port 1 configuration B */
+__sfr __at 0x4F2 P2CFGB; /* Port 2 configuration B */
+__sfr __at 0x4F3 P3CFGB; /* Port 3 configuration B */
-sbit at 0x33B ETI1; /* TX interrupt enable 1 */
-sbit at 0x33A ERI1; /* RX interrupt enable 1 */
-sbit at 0x339 ETI0; /* TX interrupt enable 0 */
-sbit at 0x338 ERI0; /* RX interrupt enable 0 */
-sbit at 0x337 EA; /* global int. enable */
-sbit at 0x334 ET2; /* timer 2 interrupt */
-sbit at 0x333 ET1; /* timer 1 interrupt */
-sbit at 0x332 EX1; /* external interrupt 1 */
-sbit at 0x331 ET0; /* timer 0 interrupt */
-sbit at 0x330 EX0; /* external interrupt 0 */
-sbit at 0x221 PD; /* power down */
-sbit at 0x220 IDL;
-sbit at 0x20F SM;
-sbit at 0x20E TM;
-sbit at 0x20D RS1;
-sbit at 0x20C RS0;
-sbit at 0x20B IM3;
-sbit at 0x20A IM2;
-sbit at 0x209 IM1;
-sbit at 0x208 IM0;
-sbit at 0x307 S0M0;
-sbit at 0x306 S0M1;
-sbit at 0x305 S0M2;
-sbit at 0x304 R0EN;
-sbit at 0x303 T0B8;
-sbit at 0x302 R0B8;
-sbit at 0x301 TI0; /* serial port 0 tx ready */
-sbit at 0x300 RI0; /* serial port 0 rx ready */
-sbit at 0x30B FE0;
-sbit at 0x30A BR0;
-sbit at 0x309 OE0;
-sbit at 0x308 STINT0;
-sbit at 0x327 S1M0;
-sbit at 0x326 S1M1;
-sbit at 0x325 S1M2;
-sbit at 0x324 R1EN;
-sbit at 0x323 T1B8;
-sbit at 0x322 R1B8;
-sbit at 0x321 TI1; /* serial port 0 tx ready */
-sbit at 0x320 RI1; /* serial port 0 rx ready */
-sbit at 0x32B FE1;
-sbit at 0x32A BR1;
-sbit at 0x329 OE1;
-sbit at 0x328 STINT1;
-sbit at 0x356 SWR7;
-sbit at 0x355 SWR6;
-sbit at 0x354 SWR5;
-sbit at 0x353 SWR4;
-sbit at 0x352 SWR3;
-sbit at 0x351 SWR2;
-sbit at 0x350 SWR1;
-sbit at 0x2C7 TF2;
-sbit at 0x2C6 EXF2;
-sbit at 0x2C5 RCLK0;
-sbit at 0x2C4 TCLK0;
-sbit at 0x2CD RCLK1;
-sbit at 0x2CC TCLK1;
-sbit at 0x2C3 EXEN2;
-sbit at 0x2C2 TR2;
-sbit at 0x2C1 CT2;
-sbit at 0x2C0 CPRL2;
-sbit at 0x2C9 T2OE;
-sbit at 0x2C8 DCEN;
-sbit at 0x287 TF1;
-sbit at 0x286 TR1;
-sbit at 0x285 TF0;
-sbit at 0x284 TR0;
-sbit at 0x283 IE1;
-sbit at 0x282 IT1;
-sbit at 0x281 IE0;
-sbit at 0x280 IT0;
-sbit at 0x28A T1OE;
-sbit at 0x288 T0OE;
-sbit at 0x2FF PRE2;
-sbit at 0x2FE PRE1;
-sbit at 0x2FD PRE0;
-sbit at 0x2FA WDRUN;
-sbit at 0x2F9 WDTOF;
-sbit at 0x2F8 WDMOD;
-sbit at 0x388 WR1;
-sbit at 0x38F T2EX;
-sbit at 0x38C RXD1;
-sbit at 0x38D TXD1;
-sbit at 0x398 RXD0;
-sbit at 0x399 TXD0;
-sbit at 0x39A INT0;
-sbit at 0x39B INT1;
-sbit at 0x39C T0;
-sbit at 0x39D T1;
-sbit at 0x39E WR;
-sbit at 0x39F RD;
+__sbit __at 0x33B ETI1; /* TX interrupt enable 1 */
+__sbit __at 0x33A ERI1; /* RX interrupt enable 1 */
+__sbit __at 0x339 ETI0; /* TX interrupt enable 0 */
+__sbit __at 0x338 ERI0; /* RX interrupt enable 0 */
+__sbit __at 0x337 EA; /* global int. enable */
+__sbit __at 0x334 ET2; /* timer 2 interrupt */
+__sbit __at 0x333 ET1; /* timer 1 interrupt */
+__sbit __at 0x332 EX1; /* external interrupt 1 */
+__sbit __at 0x331 ET0; /* timer 0 interrupt */
+__sbit __at 0x330 EX0; /* external interrupt 0 */
+__sbit __at 0x221 PD; /* power down */
+__sbit __at 0x220 IDL;
+__sbit __at 0x20F SM;
+__sbit __at 0x20E TM;
+__sbit __at 0x20D RS1;
+__sbit __at 0x20C RS0;
+__sbit __at 0x20B IM3;
+__sbit __at 0x20A IM2;
+__sbit __at 0x209 IM1;
+__sbit __at 0x208 IM0;
+__sbit __at 0x307 S0M0;
+__sbit __at 0x306 S0M1;
+__sbit __at 0x305 S0M2;
+__sbit __at 0x304 R0EN;
+__sbit __at 0x303 T0B8;
+__sbit __at 0x302 R0B8;
+__sbit __at 0x301 TI0; /* serial port 0 tx ready */
+__sbit __at 0x300 RI0; /* serial port 0 rx ready */
+__sbit __at 0x30B FE0;
+__sbit __at 0x30A BR0;
+__sbit __at 0x309 OE0;
+__sbit __at 0x308 STINT0;
+__sbit __at 0x327 S1M0;
+__sbit __at 0x326 S1M1;
+__sbit __at 0x325 S1M2;
+__sbit __at 0x324 R1EN;
+__sbit __at 0x323 T1B8;
+__sbit __at 0x322 R1B8;
+__sbit __at 0x321 TI1; /* serial port 0 tx ready */
+__sbit __at 0x320 RI1; /* serial port 0 rx ready */
+__sbit __at 0x32B FE1;
+__sbit __at 0x32A BR1;
+__sbit __at 0x329 OE1;
+__sbit __at 0x328 STINT1;
+__sbit __at 0x356 SWR7;
+__sbit __at 0x355 SWR6;
+__sbit __at 0x354 SWR5;
+__sbit __at 0x353 SWR4;
+__sbit __at 0x352 SWR3;
+__sbit __at 0x351 SWR2;
+__sbit __at 0x350 SWR1;
+__sbit __at 0x2C7 TF2;
+__sbit __at 0x2C6 EXF2;
+__sbit __at 0x2C5 RCLK0;
+__sbit __at 0x2C4 TCLK0;
+__sbit __at 0x2CD RCLK1;
+__sbit __at 0x2CC TCLK1;
+__sbit __at 0x2C3 EXEN2;
+__sbit __at 0x2C2 TR2;
+__sbit __at 0x2C1 CT2;
+__sbit __at 0x2C0 CPRL2;
+__sbit __at 0x2C9 T2OE;
+__sbit __at 0x2C8 DCEN;
+__sbit __at 0x287 TF1;
+__sbit __at 0x286 TR1;
+__sbit __at 0x285 TF0;
+__sbit __at 0x284 TR0;
+__sbit __at 0x283 IE1;
+__sbit __at 0x282 IT1;
+__sbit __at 0x281 IE0;
+__sbit __at 0x280 IT0;
+__sbit __at 0x28A T1OE;
+__sbit __at 0x288 T0OE;
+__sbit __at 0x2FF PRE2;
+__sbit __at 0x2FE PRE1;
+__sbit __at 0x2FD PRE0;
+__sbit __at 0x2FA WDRUN;
+__sbit __at 0x2F9 WDTOF;
+__sbit __at 0x2F8 WDMOD;
+__sbit __at 0x388 WR1;
+__sbit __at 0x38F T2EX;
+__sbit __at 0x38C RXD1;
+__sbit __at 0x38D TXD1;
+__sbit __at 0x398 RXD0;
+__sbit __at 0x399 TXD0;
+__sbit __at 0x39A INT0;
+__sbit __at 0x39B INT1;
+__sbit __at 0x39C T0;
+__sbit __at 0x39D T1;
+__sbit __at 0x39E WR;
+__sbit __at 0x39F RD;
/*
* Interrupt stuff
if [ "`grep z80 ../../ports.build`" = z80 ]; then \
$(CP) z80/*.h $(sdcc_includedir)/z80 ; \
fi
+ if [ "`grep hc08 ../../ports.build`" = hc08 ]; then \
+ $(CP) hc08/*.h $(sdcc_includedir)/hc08 ; \
+ fi
rm -rf `find $(sdcc_includedir) -type d -name 'CVS'`
[ -d $(sdcc_includedir)/mcs51 ] || mkdir -p $(sdcc_includedir)/mcs51
[ -d $(sdcc_includedir)/pic16 ] || mkdir -p $(sdcc_includedir)/pic16
[ -d $(sdcc_includedir)/z80 ] || mkdir -p $(sdcc_includedir)/z80
+ [ -d $(sdcc_includedir)/hc08 ] || mkdir -p $(sdcc_includedir)/hc08
# Creating dependencies
#define AT89S8252_H
/* BYTE addressable registers */
-sfr at 0x80 P0 ;
-sfr at 0x81 SP ;
-sfr at 0x82 DPL ;
-sfr at 0x82 DP0L ; /* as called by Atmel */
-sfr at 0x83 DPH ;
-sfr at 0x83 DP0H ; /* as called by Atmel */
-sfr at 0x84 DP1L ; /* at89S8252 specific register */
-sfr at 0x85 DP1H ; /* at89S8252 specific register */
-sfr at 0x86 SPDR ; /* at89S8252 specific register */
-sfr at 0x87 PCON ;
-sfr at 0x88 TCON ;
-sfr at 0x89 TMOD ;
-sfr at 0x8A TL0 ;
-sfr at 0x8B TL1 ;
-sfr at 0x8C TH0 ;
-sfr at 0x8D TH1 ;
-sfr at 0x90 P1 ;
-sfr at 0x96 WMCON ; /* at89S8252 specific register */
-sfr at 0x98 SCON ;
-sfr at 0x99 SBUF ;
-sfr at 0xA0 P2 ;
-sfr at 0xA8 IE ;
-sfr at 0xAA SPSR ; /* at89S8252 specific register */
-sfr at 0xB0 P3 ;
-sfr at 0xB8 IP ;
-sfr at 0xC8 T2CON ;
-sfr at 0xC9 T2MOD ;
-sfr at 0xCA RCAP2L ;
-sfr at 0xCB RCAP2H ;
-sfr at 0xCC TL2 ;
-sfr at 0xCD TH2 ;
-sfr at 0xD0 PSW ;
-sfr at 0xD5 SPCR ; /* at89S8252 specific register */
-sfr at 0xE0 ACC ;
-sfr at 0xE0 A ;
-sfr at 0xF0 B ;
+__sfr __at 0x80 P0 ;
+__sfr __at 0x81 SP ;
+__sfr __at 0x82 DPL ;
+__sfr __at 0x82 DP0L ; /* as called by Atmel */
+__sfr __at 0x83 DPH ;
+__sfr __at 0x83 DP0H ; /* as called by Atmel */
+__sfr __at 0x84 DP1L ; /* at89S8252 specific register */
+__sfr __at 0x85 DP1H ; /* at89S8252 specific register */
+__sfr __at 0x86 SPDR ; /* at89S8252 specific register */
+__sfr __at 0x87 PCON ;
+__sfr __at 0x88 TCON ;
+__sfr __at 0x89 TMOD ;
+__sfr __at 0x8A TL0 ;
+__sfr __at 0x8B TL1 ;
+__sfr __at 0x8C TH0 ;
+__sfr __at 0x8D TH1 ;
+__sfr __at 0x90 P1 ;
+__sfr __at 0x96 WMCON ; /* at89S8252 specific register */
+__sfr __at 0x98 SCON ;
+__sfr __at 0x99 SBUF ;
+__sfr __at 0xA0 P2 ;
+__sfr __at 0xA8 IE ;
+__sfr __at 0xAA SPSR ; /* at89S8252 specific register */
+__sfr __at 0xB0 P3 ;
+__sfr __at 0xB8 IP ;
+__sfr __at 0xC8 T2CON ;
+__sfr __at 0xC9 T2MOD ;
+__sfr __at 0xCA RCAP2L ;
+__sfr __at 0xCB RCAP2H ;
+__sfr __at 0xCC TL2 ;
+__sfr __at 0xCD TH2 ;
+__sfr __at 0xD0 PSW ;
+__sfr __at 0xD5 SPCR ; /* at89S8252 specific register */
+__sfr __at 0xE0 ACC ;
+__sfr __at 0xE0 A ;
+__sfr __at 0xF0 B ;
/* BIT addressable registers */
/* P0 */
-sbit at 0x80 P0_0 ;
-sbit at 0x81 P0_1 ;
-sbit at 0x82 P0_2 ;
-sbit at 0x83 P0_3 ;
-sbit at 0x84 P0_4 ;
-sbit at 0x85 P0_5 ;
-sbit at 0x86 P0_6 ;
-sbit at 0x87 P0_7 ;
+__sbit __at 0x80 P0_0 ;
+__sbit __at 0x81 P0_1 ;
+__sbit __at 0x82 P0_2 ;
+__sbit __at 0x83 P0_3 ;
+__sbit __at 0x84 P0_4 ;
+__sbit __at 0x85 P0_5 ;
+__sbit __at 0x86 P0_6 ;
+__sbit __at 0x87 P0_7 ;
/* TCON */
-sbit at 0x88 IT0 ;
-sbit at 0x89 IE0 ;
-sbit at 0x8A IT1 ;
-sbit at 0x8B IE1 ;
-sbit at 0x8C TR0 ;
-sbit at 0x8D TF0 ;
-sbit at 0x8E TR1 ;
-sbit at 0x8F TF1 ;
+__sbit __at 0x88 IT0 ;
+__sbit __at 0x89 IE0 ;
+__sbit __at 0x8A IT1 ;
+__sbit __at 0x8B IE1 ;
+__sbit __at 0x8C TR0 ;
+__sbit __at 0x8D TF0 ;
+__sbit __at 0x8E TR1 ;
+__sbit __at 0x8F TF1 ;
/* P1 */
-sbit at 0x90 P1_0 ;
-sbit at 0x91 P1_1 ;
-sbit at 0x92 P1_2 ;
-sbit at 0x93 P1_3 ;
-sbit at 0x94 P1_4 ;
-sbit at 0x95 P1_5 ;
-sbit at 0x96 P1_6 ;
-sbit at 0x97 P1_7 ;
-
-sbit at 0x90 T2 ;
-sbit at 0x91 T2EX ;
+__sbit __at 0x90 P1_0 ;
+__sbit __at 0x91 P1_1 ;
+__sbit __at 0x92 P1_2 ;
+__sbit __at 0x93 P1_3 ;
+__sbit __at 0x94 P1_4 ;
+__sbit __at 0x95 P1_5 ;
+__sbit __at 0x96 P1_6 ;
+__sbit __at 0x97 P1_7 ;
+
+__sbit __at 0x90 T2 ;
+__sbit __at 0x91 T2EX ;
/* P1 SPI portpins */
-sbit at 0x94 SS; /* SPI: SS - Slave port select input */
-sbit at 0x95 MOSI; /* SPI: MOSI - Master data output, slave data input */
-sbit at 0x96 MISO; /* SPI: MISO - Master data input, slave data output */
-sbit at 0x97 SCK; /* SPI: SCK - Master clock output, slave clock input */
+__sbit __at 0x94 SS; /* SPI: SS - Slave port select input */
+__sbit __at 0x95 MOSI; /* SPI: MOSI - Master data output, slave data input */
+__sbit __at 0x96 MISO; /* SPI: MISO - Master data input, slave data output */
+__sbit __at 0x97 SCK; /* SPI: SCK - Master clock output, slave clock input */
/* SCON */
-sbit at 0x98 RI ;
-sbit at 0x99 TI ;
-sbit at 0x9A RB8 ;
-sbit at 0x9B TB8 ;
-sbit at 0x9C REN ;
-sbit at 0x9D SM2 ;
-sbit at 0x9E SM1 ;
-sbit at 0x9F SM0 ;
+__sbit __at 0x98 RI ;
+__sbit __at 0x99 TI ;
+__sbit __at 0x9A RB8 ;
+__sbit __at 0x9B TB8 ;
+__sbit __at 0x9C REN ;
+__sbit __at 0x9D SM2 ;
+__sbit __at 0x9E SM1 ;
+__sbit __at 0x9F SM0 ;
/* P2 */
-sbit at 0xA0 P2_0 ;
-sbit at 0xA1 P2_1 ;
-sbit at 0xA2 P2_2 ;
-sbit at 0xA3 P2_3 ;
-sbit at 0xA4 P2_4 ;
-sbit at 0xA5 P2_5 ;
-sbit at 0xA6 P2_6 ;
-sbit at 0xA7 P2_7 ;
+__sbit __at 0xA0 P2_0 ;
+__sbit __at 0xA1 P2_1 ;
+__sbit __at 0xA2 P2_2 ;
+__sbit __at 0xA3 P2_3 ;
+__sbit __at 0xA4 P2_4 ;
+__sbit __at 0xA5 P2_5 ;
+__sbit __at 0xA6 P2_6 ;
+__sbit __at 0xA7 P2_7 ;
/* IE */
-sbit at 0xA8 EX0 ;
-sbit at 0xA9 ET0 ;
-sbit at 0xAA EX1 ;
-sbit at 0xAB ET1 ;
-sbit at 0xAC ES ;
-sbit at 0xAD ET2 ;
-sbit at 0xAF EA ;
+__sbit __at 0xA8 EX0 ;
+__sbit __at 0xA9 ET0 ;
+__sbit __at 0xAA EX1 ;
+__sbit __at 0xAB ET1 ;
+__sbit __at 0xAC ES ;
+__sbit __at 0xAD ET2 ;
+__sbit __at 0xAF EA ;
/* P3 */
-sbit at 0xB0 P3_0 ;
-sbit at 0xB1 P3_1 ;
-sbit at 0xB2 P3_2 ;
-sbit at 0xB3 P3_3 ;
-sbit at 0xB4 P3_4 ;
-sbit at 0xB5 P3_5 ;
-sbit at 0xB6 P3_6 ;
-sbit at 0xB7 P3_7 ;
-
-sbit at 0xB0 RXD ;
-sbit at 0xB1 TXD ;
-sbit at 0xB2 INT0 ;
-sbit at 0xB3 INT1 ;
-sbit at 0xB4 T0 ;
-sbit at 0xB5 T1 ;
-sbit at 0xB6 WR ;
-sbit at 0xB7 RD ;
+__sbit __at 0xB0 P3_0 ;
+__sbit __at 0xB1 P3_1 ;
+__sbit __at 0xB2 P3_2 ;
+__sbit __at 0xB3 P3_3 ;
+__sbit __at 0xB4 P3_4 ;
+__sbit __at 0xB5 P3_5 ;
+__sbit __at 0xB6 P3_6 ;
+__sbit __at 0xB7 P3_7 ;
+
+__sbit __at 0xB0 RXD ;
+__sbit __at 0xB1 TXD ;
+__sbit __at 0xB2 INT0 ;
+__sbit __at 0xB3 INT1 ;
+__sbit __at 0xB4 T0 ;
+__sbit __at 0xB5 T1 ;
+__sbit __at 0xB6 WR ;
+__sbit __at 0xB7 RD ;
/* IP */
-sbit at 0xB8 PX0 ;
-sbit at 0xB9 PT0 ;
-sbit at 0xBA PX1 ;
-sbit at 0xBB PT1 ;
-sbit at 0xBC PS ;
-sbit at 0xBD PT2 ;
+__sbit __at 0xB8 PX0 ;
+__sbit __at 0xB9 PT0 ;
+__sbit __at 0xBA PX1 ;
+__sbit __at 0xBB PT1 ;
+__sbit __at 0xBC PS ;
+__sbit __at 0xBD PT2 ;
/* T2CON */
-sbit at 0xC8 T2CON_0 ;
-sbit at 0xC9 T2CON_1 ;
-sbit at 0xCA T2CON_2 ;
-sbit at 0xCB T2CON_3 ;
-sbit at 0xCC T2CON_4 ;
-sbit at 0xCD T2CON_5 ;
-sbit at 0xCE T2CON_6 ;
-sbit at 0xCF T2CON_7 ;
-
-sbit at 0xC8 CP_RL2 ;
-sbit at 0xC9 C_T2 ;
-sbit at 0xCA TR2 ;
-sbit at 0xCB EXEN2 ;
-sbit at 0xCC TCLK ;
-sbit at 0xCD RCLK ;
-sbit at 0xCE EXF2 ;
-sbit at 0xCF TF2 ;
+__sbit __at 0xC8 T2CON_0 ;
+__sbit __at 0xC9 T2CON_1 ;
+__sbit __at 0xCA T2CON_2 ;
+__sbit __at 0xCB T2CON_3 ;
+__sbit __at 0xCC T2CON_4 ;
+__sbit __at 0xCD T2CON_5 ;
+__sbit __at 0xCE T2CON_6 ;
+__sbit __at 0xCF T2CON_7 ;
+
+__sbit __at 0xC8 CP_RL2 ;
+__sbit __at 0xC9 C_T2 ;
+__sbit __at 0xCA TR2 ;
+__sbit __at 0xCB EXEN2 ;
+__sbit __at 0xCC TCLK ;
+__sbit __at 0xCD RCLK ;
+__sbit __at 0xCE EXF2 ;
+__sbit __at 0xCF TF2 ;
/* PSW */
-sbit at 0xD0 P ;
-sbit at 0xD1 FL ;
-sbit at 0xD2 OV ;
-sbit at 0xD3 RS0 ;
-sbit at 0xD4 RS1 ;
-sbit at 0xD5 F0 ;
-sbit at 0xD6 AC ;
-sbit at 0xD7 CY ;
+__sbit __at 0xD0 P ;
+__sbit __at 0xD1 FL ;
+__sbit __at 0xD2 OV ;
+__sbit __at 0xD3 RS0 ;
+__sbit __at 0xD4 RS1 ;
+__sbit __at 0xD5 F0 ;
+__sbit __at 0xD6 AC ;
+__sbit __at 0xD7 CY ;
/* B */
-sbit at 0xF0 BREG_F0 ;
-sbit at 0xF1 BREG_F1 ;
-sbit at 0xF2 BREG_F2 ;
-sbit at 0xF3 BREG_F3 ;
-sbit at 0xF4 BREG_F4 ;
-sbit at 0xF5 BREG_F5 ;
-sbit at 0xF6 BREG_F6 ;
-sbit at 0xF7 BREG_F7 ;
+__sbit __at 0xF0 BREG_F0 ;
+__sbit __at 0xF1 BREG_F1 ;
+__sbit __at 0xF2 BREG_F2 ;
+__sbit __at 0xF3 BREG_F3 ;
+__sbit __at 0xF4 BREG_F4 ;
+__sbit __at 0xF5 BREG_F5 ;
+__sbit __at 0xF6 BREG_F6 ;
+__sbit __at 0xF7 BREG_F7 ;
/* BIT definitions for bits that are not directly accessible */
/* This is one of the addons comming from Bernd Krueger-Knauber */
/* ALE (0x8E) Bit Values */
-sfr at 0x8E ALE; /* at89S8252 specific register */
+__sfr __at 0x8E ALE; /* at89S8252 specific register */
/* Macro to enable and disable the toggling of the ALE-pin (EMV) */
#define AT89x55_H
/* BYTE addressable registers */
-sfr at 0x80 P0 ;
-sfr at 0x81 SP ;
-sfr at 0x82 DPL ;
-sfr at 0x83 DPH ;
-sfr at 0x87 PCON ;
-sfr at 0x88 TCON ;
-sfr at 0x89 TMOD ;
-sfr at 0x8A TL0 ;
-sfr at 0x8B TL1 ;
-sfr at 0x8C TH0 ;
-sfr at 0x8D TH1 ;
-sfr at 0x90 P1 ;
-sfr at 0x98 SCON ;
-sfr at 0x99 SBUF ;
-sfr at 0xA0 P2 ;
-sfr at 0xA8 IE ;
-sfr at 0xB0 P3 ;
-sfr at 0xB8 IP ;
-sfr at 0xC8 T2CON ;
-sfr at 0xC9 T2MOD ;
-sfr at 0xCA RCAP2L ;
-sfr at 0xCB RCAP2H ;
-sfr at 0xCC TL2 ;
-sfr at 0xCD TH2 ;
-sfr at 0xD0 PSW ;
-sfr at 0xE0 ACC ;
-sfr at 0xE0 A ;
-sfr at 0xF0 B ;
+__sfr __at 0x80 P0 ;
+__sfr __at 0x81 SP ;
+__sfr __at 0x82 DPL ;
+__sfr __at 0x83 DPH ;
+__sfr __at 0x87 PCON ;
+__sfr __at 0x88 TCON ;
+__sfr __at 0x89 TMOD ;
+__sfr __at 0x8A TL0 ;
+__sfr __at 0x8B TL1 ;
+__sfr __at 0x8C TH0 ;
+__sfr __at 0x8D TH1 ;
+__sfr __at 0x90 P1 ;
+__sfr __at 0x98 SCON ;
+__sfr __at 0x99 SBUF ;
+__sfr __at 0xA0 P2 ;
+__sfr __at 0xA8 IE ;
+__sfr __at 0xB0 P3 ;
+__sfr __at 0xB8 IP ;
+__sfr __at 0xC8 T2CON ;
+__sfr __at 0xC9 T2MOD ;
+__sfr __at 0xCA RCAP2L ;
+__sfr __at 0xCB RCAP2H ;
+__sfr __at 0xCC TL2 ;
+__sfr __at 0xCD TH2 ;
+__sfr __at 0xD0 PSW ;
+__sfr __at 0xE0 ACC ;
+__sfr __at 0xE0 A ;
+__sfr __at 0xF0 B ;
/* BIT addressable registers */
/* P0 */
-sbit at 0x80 P0_0 ;
-sbit at 0x81 P0_1 ;
-sbit at 0x82 P0_2 ;
-sbit at 0x83 P0_3 ;
-sbit at 0x84 P0_4 ;
-sbit at 0x85 P0_5 ;
-sbit at 0x86 P0_6 ;
-sbit at 0x87 P0_7 ;
+__sbit __at 0x80 P0_0 ;
+__sbit __at 0x81 P0_1 ;
+__sbit __at 0x82 P0_2 ;
+__sbit __at 0x83 P0_3 ;
+__sbit __at 0x84 P0_4 ;
+__sbit __at 0x85 P0_5 ;
+__sbit __at 0x86 P0_6 ;
+__sbit __at 0x87 P0_7 ;
/* TCON */
-sbit at 0x88 IT0 ;
-sbit at 0x89 IE0 ;
-sbit at 0x8A IT1 ;
-sbit at 0x8B IE1 ;
-sbit at 0x8C TR0 ;
-sbit at 0x8D TF0 ;
-sbit at 0x8E TR1 ;
-sbit at 0x8F TF1 ;
+__sbit __at 0x88 IT0 ;
+__sbit __at 0x89 IE0 ;
+__sbit __at 0x8A IT1 ;
+__sbit __at 0x8B IE1 ;
+__sbit __at 0x8C TR0 ;
+__sbit __at 0x8D TF0 ;
+__sbit __at 0x8E TR1 ;
+__sbit __at 0x8F TF1 ;
/* P1 */
-sbit at 0x90 P1_0 ;
-sbit at 0x91 P1_1 ;
-sbit at 0x92 P1_2 ;
-sbit at 0x93 P1_3 ;
-sbit at 0x94 P1_4 ;
-sbit at 0x95 P1_5 ;
-sbit at 0x96 P1_6 ;
-sbit at 0x97 P1_7 ;
-
-sbit at 0x90 T2 ;
-sbit at 0x91 T2EX ;
+__sbit __at 0x90 P1_0 ;
+__sbit __at 0x91 P1_1 ;
+__sbit __at 0x92 P1_2 ;
+__sbit __at 0x93 P1_3 ;
+__sbit __at 0x94 P1_4 ;
+__sbit __at 0x95 P1_5 ;
+__sbit __at 0x96 P1_6 ;
+__sbit __at 0x97 P1_7 ;
+
+__sbit __at 0x90 T2 ;
+__sbit __at 0x91 T2EX ;
/* SCON */
-sbit at 0x98 RI ;
-sbit at 0x99 TI ;
-sbit at 0x9A RB8 ;
-sbit at 0x9B TB8 ;
-sbit at 0x9C REN ;
-sbit at 0x9D SM2 ;
-sbit at 0x9E SM1 ;
-sbit at 0x9F SM0 ;
+__sbit __at 0x98 RI ;
+__sbit __at 0x99 TI ;
+__sbit __at 0x9A RB8 ;
+__sbit __at 0x9B TB8 ;
+__sbit __at 0x9C REN ;
+__sbit __at 0x9D SM2 ;
+__sbit __at 0x9E SM1 ;
+__sbit __at 0x9F SM0 ;
/* P2 */
-sbit at 0xA0 P2_0 ;
-sbit at 0xA1 P2_1 ;
-sbit at 0xA2 P2_2 ;
-sbit at 0xA3 P2_3 ;
-sbit at 0xA4 P2_4 ;
-sbit at 0xA5 P2_5 ;
-sbit at 0xA6 P2_6 ;
-sbit at 0xA7 P2_7 ;
+__sbit __at 0xA0 P2_0 ;
+__sbit __at 0xA1 P2_1 ;
+__sbit __at 0xA2 P2_2 ;
+__sbit __at 0xA3 P2_3 ;
+__sbit __at 0xA4 P2_4 ;
+__sbit __at 0xA5 P2_5 ;
+__sbit __at 0xA6 P2_6 ;
+__sbit __at 0xA7 P2_7 ;
/* IE */
-sbit at 0xA8 EX0 ;
-sbit at 0xA9 ET0 ;
-sbit at 0xAA EX1 ;
-sbit at 0xAB ET1 ;
-sbit at 0xAC ES ;
-sbit at 0xAD ET2 ;
-sbit at 0xAF EA ;
+__sbit __at 0xA8 EX0 ;
+__sbit __at 0xA9 ET0 ;
+__sbit __at 0xAA EX1 ;
+__sbit __at 0xAB ET1 ;
+__sbit __at 0xAC ES ;
+__sbit __at 0xAD ET2 ;
+__sbit __at 0xAF EA ;
/* P3 */
-sbit at 0xB0 P3_0 ;
-sbit at 0xB1 P3_1 ;
-sbit at 0xB2 P3_2 ;
-sbit at 0xB3 P3_3 ;
-sbit at 0xB4 P3_4 ;
-sbit at 0xB5 P3_5 ;
-sbit at 0xB6 P3_6 ;
-sbit at 0xB7 P3_7 ;
-
-sbit at 0xB0 RXD ;
-sbit at 0xB1 TXD ;
-sbit at 0xB2 INT0 ;
-sbit at 0xB3 INT1 ;
-sbit at 0xB4 T0 ;
-sbit at 0xB5 T1 ;
-sbit at 0xB6 WR ;
-sbit at 0xB7 RD ;
+__sbit __at 0xB0 P3_0 ;
+__sbit __at 0xB1 P3_1 ;
+__sbit __at 0xB2 P3_2 ;
+__sbit __at 0xB3 P3_3 ;
+__sbit __at 0xB4 P3_4 ;
+__sbit __at 0xB5 P3_5 ;
+__sbit __at 0xB6 P3_6 ;
+__sbit __at 0xB7 P3_7 ;
+
+__sbit __at 0xB0 RXD ;
+__sbit __at 0xB1 TXD ;
+__sbit __at 0xB2 INT0 ;
+__sbit __at 0xB3 INT1 ;
+__sbit __at 0xB4 T0 ;
+__sbit __at 0xB5 T1 ;
+__sbit __at 0xB6 WR ;
+__sbit __at 0xB7 RD ;
/* IP */
-sbit at 0xB8 PX0 ;
-sbit at 0xB9 PT0 ;
-sbit at 0xBA PX1 ;
-sbit at 0xBB PT1 ;
-sbit at 0xBC PS ;
-sbit at 0xBD PT2 ;
+__sbit __at 0xB8 PX0 ;
+__sbit __at 0xB9 PT0 ;
+__sbit __at 0xBA PX1 ;
+__sbit __at 0xBB PT1 ;
+__sbit __at 0xBC PS ;
+__sbit __at 0xBD PT2 ;
/* T2CON */
-sbit at 0xC8 T2CON_0 ;
-sbit at 0xC9 T2CON_1 ;
-sbit at 0xCA T2CON_2 ;
-sbit at 0xCB T2CON_3 ;
-sbit at 0xCC T2CON_4 ;
-sbit at 0xCD T2CON_5 ;
-sbit at 0xCE T2CON_6 ;
-sbit at 0xCF T2CON_7 ;
-
-sbit at 0xC8 CP_RL2 ;
-sbit at 0xC9 C_T2 ;
-sbit at 0xCA TR2 ;
-sbit at 0xCB EXEN2 ;
-sbit at 0xCC TCLK ;
-sbit at 0xCD RCLK ;
-sbit at 0xCE EXF2 ;
-sbit at 0xCF TF2 ;
+__sbit __at 0xC8 T2CON_0 ;
+__sbit __at 0xC9 T2CON_1 ;
+__sbit __at 0xCA T2CON_2 ;
+__sbit __at 0xCB T2CON_3 ;
+__sbit __at 0xCC T2CON_4 ;
+__sbit __at 0xCD T2CON_5 ;
+__sbit __at 0xCE T2CON_6 ;
+__sbit __at 0xCF T2CON_7 ;
+
+__sbit __at 0xC8 CP_RL2 ;
+__sbit __at 0xC9 C_T2 ;
+__sbit __at 0xCA TR2 ;
+__sbit __at 0xCB EXEN2 ;
+__sbit __at 0xCC TCLK ;
+__sbit __at 0xCD RCLK ;
+__sbit __at 0xCE EXF2 ;
+__sbit __at 0xCF TF2 ;
/* PSW */
-sbit at 0xD0 P ;
-sbit at 0xD1 FL ;
-sbit at 0xD2 OV ;
-sbit at 0xD3 RS0 ;
-sbit at 0xD4 RS1 ;
-sbit at 0xD5 F0 ;
-sbit at 0xD6 AC ;
-sbit at 0xD7 CY ;
+__sbit __at 0xD0 P ;
+__sbit __at 0xD1 FL ;
+__sbit __at 0xD2 OV ;
+__sbit __at 0xD3 RS0 ;
+__sbit __at 0xD4 RS1 ;
+__sbit __at 0xD5 F0 ;
+__sbit __at 0xD6 AC ;
+__sbit __at 0xD7 CY ;
/* BIT definitions for bits that are not directly accessible */
#define AT89x51_H
/* BYTE addressable registers */
-sfr at 0x80 P0 ;
-sfr at 0x81 SP ;
-sfr at 0x82 DPL ;
-sfr at 0x83 DPH ;
-sfr at 0x87 PCON ;
-sfr at 0x88 TCON ;
-sfr at 0x89 TMOD ;
-sfr at 0x8A TL0 ;
-sfr at 0x8B TL1 ;
-sfr at 0x8C TH0 ;
-sfr at 0x8D TH1 ;
-sfr at 0x90 P1 ;
-sfr at 0x98 SCON ;
-sfr at 0x99 SBUF ;
-sfr at 0xA0 P2 ;
-sfr at 0xA8 IE ;
-sfr at 0xB0 P3 ;
-sfr at 0xB8 IP ;
-sfr at 0xD0 PSW ;
-sfr at 0xE0 ACC ;
-sfr at 0xE0 A ;
-sfr at 0xF0 B ;
+__sfr __at 0x80 P0 ;
+__sfr __at 0x81 SP ;
+__sfr __at 0x82 DPL ;
+__sfr __at 0x83 DPH ;
+__sfr __at 0x87 PCON ;
+__sfr __at 0x88 TCON ;
+__sfr __at 0x89 TMOD ;
+__sfr __at 0x8A TL0 ;
+__sfr __at 0x8B TL1 ;
+__sfr __at 0x8C TH0 ;
+__sfr __at 0x8D TH1 ;
+__sfr __at 0x90 P1 ;
+__sfr __at 0x98 SCON ;
+__sfr __at 0x99 SBUF ;
+__sfr __at 0xA0 P2 ;
+__sfr __at 0xA8 IE ;
+__sfr __at 0xB0 P3 ;
+__sfr __at 0xB8 IP ;
+__sfr __at 0xD0 PSW ;
+__sfr __at 0xE0 ACC ;
+__sfr __at 0xE0 A ;
+__sfr __at 0xF0 B ;
/* BIT addressable registers */
/* P0 */
-sbit at 0x80 P0_0 ;
-sbit at 0x81 P0_1 ;
-sbit at 0x82 P0_2 ;
-sbit at 0x83 P0_3 ;
-sbit at 0x84 P0_4 ;
-sbit at 0x85 P0_5 ;
-sbit at 0x86 P0_6 ;
-sbit at 0x87 P0_7 ;
+__sbit __at 0x80 P0_0 ;
+__sbit __at 0x81 P0_1 ;
+__sbit __at 0x82 P0_2 ;
+__sbit __at 0x83 P0_3 ;
+__sbit __at 0x84 P0_4 ;
+__sbit __at 0x85 P0_5 ;
+__sbit __at 0x86 P0_6 ;
+__sbit __at 0x87 P0_7 ;
/* TCON */
-sbit at 0x88 IT0 ;
-sbit at 0x89 IE0 ;
-sbit at 0x8A IT1 ;
-sbit at 0x8B IE1 ;
-sbit at 0x8C TR0 ;
-sbit at 0x8D TF0 ;
-sbit at 0x8E TR1 ;
-sbit at 0x8F TF1 ;
+__sbit __at 0x88 IT0 ;
+__sbit __at 0x89 IE0 ;
+__sbit __at 0x8A IT1 ;
+__sbit __at 0x8B IE1 ;
+__sbit __at 0x8C TR0 ;
+__sbit __at 0x8D TF0 ;
+__sbit __at 0x8E TR1 ;
+__sbit __at 0x8F TF1 ;
/* P1 */
-sbit at 0x90 P1_0 ;
-sbit at 0x91 P1_1 ;
-sbit at 0x92 P1_2 ;
-sbit at 0x93 P1_3 ;
-sbit at 0x94 P1_4 ;
-sbit at 0x95 P1_5 ;
-sbit at 0x96 P1_6 ;
-sbit at 0x97 P1_7 ;
+__sbit __at 0x90 P1_0 ;
+__sbit __at 0x91 P1_1 ;
+__sbit __at 0x92 P1_2 ;
+__sbit __at 0x93 P1_3 ;
+__sbit __at 0x94 P1_4 ;
+__sbit __at 0x95 P1_5 ;
+__sbit __at 0x96 P1_6 ;
+__sbit __at 0x97 P1_7 ;
/* SCON */
-sbit at 0x98 RI ;
-sbit at 0x99 TI ;
-sbit at 0x9A RB8 ;
-sbit at 0x9B TB8 ;
-sbit at 0x9C REN ;
-sbit at 0x9D SM2 ;
-sbit at 0x9E SM1 ;
-sbit at 0x9F SM0 ;
+__sbit __at 0x98 RI ;
+__sbit __at 0x99 TI ;
+__sbit __at 0x9A RB8 ;
+__sbit __at 0x9B TB8 ;
+__sbit __at 0x9C REN ;
+__sbit __at 0x9D SM2 ;
+__sbit __at 0x9E SM1 ;
+__sbit __at 0x9F SM0 ;
/* P2 */
-sbit at 0xA0 P2_0 ;
-sbit at 0xA1 P2_1 ;
-sbit at 0xA2 P2_2 ;
-sbit at 0xA3 P2_3 ;
-sbit at 0xA4 P2_4 ;
-sbit at 0xA5 P2_5 ;
-sbit at 0xA6 P2_6 ;
-sbit at 0xA7 P2_7 ;
+__sbit __at 0xA0 P2_0 ;
+__sbit __at 0xA1 P2_1 ;
+__sbit __at 0xA2 P2_2 ;
+__sbit __at 0xA3 P2_3 ;
+__sbit __at 0xA4 P2_4 ;
+__sbit __at 0xA5 P2_5 ;
+__sbit __at 0xA6 P2_6 ;
+__sbit __at 0xA7 P2_7 ;
/* IE */
-sbit at 0xA8 EX0 ;
-sbit at 0xA9 ET0 ;
-sbit at 0xAA EX1 ;
-sbit at 0xAB ET1 ;
-sbit at 0xAC ES ;
-sbit at 0xAF EA ;
+__sbit __at 0xA8 EX0 ;
+__sbit __at 0xA9 ET0 ;
+__sbit __at 0xAA EX1 ;
+__sbit __at 0xAB ET1 ;
+__sbit __at 0xAC ES ;
+__sbit __at 0xAF EA ;
/* P3 */
-sbit at 0xB0 P3_0 ;
-sbit at 0xB1 P3_1 ;
-sbit at 0xB2 P3_2 ;
-sbit at 0xB3 P3_3 ;
-sbit at 0xB4 P3_4 ;
-sbit at 0xB5 P3_5 ;
-sbit at 0xB6 P3_6 ;
-sbit at 0xB7 P3_7 ;
-
-sbit at 0xB0 RXD ;
-sbit at 0xB1 TXD ;
-sbit at 0xB2 INT0 ;
-sbit at 0xB3 INT1 ;
-sbit at 0xB4 T0 ;
-sbit at 0xB5 T1 ;
-sbit at 0xB6 WR ;
-sbit at 0xB7 RD ;
+__sbit __at 0xB0 P3_0 ;
+__sbit __at 0xB1 P3_1 ;
+__sbit __at 0xB2 P3_2 ;
+__sbit __at 0xB3 P3_3 ;
+__sbit __at 0xB4 P3_4 ;
+__sbit __at 0xB5 P3_5 ;
+__sbit __at 0xB6 P3_6 ;
+__sbit __at 0xB7 P3_7 ;
+
+__sbit __at 0xB0 RXD ;
+__sbit __at 0xB1 TXD ;
+__sbit __at 0xB2 INT0 ;
+__sbit __at 0xB3 INT1 ;
+__sbit __at 0xB4 T0 ;
+__sbit __at 0xB5 T1 ;
+__sbit __at 0xB6 WR ;
+__sbit __at 0xB7 RD ;
/* IP */
-sbit at 0xB8 PX0 ;
-sbit at 0xB9 PT0 ;
-sbit at 0xBA PX1 ;
-sbit at 0xBB PT1 ;
-sbit at 0xBC PS ;
+__sbit __at 0xB8 PX0 ;
+__sbit __at 0xB9 PT0 ;
+__sbit __at 0xBA PX1 ;
+__sbit __at 0xBB PT1 ;
+__sbit __at 0xBC PS ;
/* PSW */
-sbit at 0xD0 P ;
-sbit at 0xD1 FL ;
-sbit at 0xD2 OV ;
-sbit at 0xD3 RS0 ;
-sbit at 0xD4 RS1 ;
-sbit at 0xD5 F0 ;
-sbit at 0xD6 AC ;
-sbit at 0xD7 CY ;
+__sbit __at 0xD0 P ;
+__sbit __at 0xD1 FL ;
+__sbit __at 0xD2 OV ;
+__sbit __at 0xD3 RS0 ;
+__sbit __at 0xD4 RS1 ;
+__sbit __at 0xD5 F0 ;
+__sbit __at 0xD6 AC ;
+__sbit __at 0xD7 CY ;
/* BIT definitions for bits that are not directly accessible */
#define AT89x52_H
/* BYTE addressable registers */
-sfr at 0x80 P0 ;
-sfr at 0x81 SP ;
-sfr at 0x82 DPL ;
-sfr at 0x83 DPH ;
-sfr at 0x87 PCON ;
-sfr at 0x88 TCON ;
-sfr at 0x89 TMOD ;
-sfr at 0x8A TL0 ;
-sfr at 0x8B TL1 ;
-sfr at 0x8C TH0 ;
-sfr at 0x8D TH1 ;
-sfr at 0x90 P1 ;
-sfr at 0x98 SCON ;
-sfr at 0x99 SBUF ;
-sfr at 0xA0 P2 ;
-sfr at 0xA8 IE ;
-sfr at 0xB0 P3 ;
-sfr at 0xB8 IP ;
-sfr at 0xC8 T2CON ;
-sfr at 0xC9 T2MOD ;
-sfr at 0xCA RCAP2L ;
-sfr at 0xCB RCAP2H ;
-sfr at 0xCC TL2 ;
-sfr at 0xCD TH2 ;
-sfr at 0xD0 PSW ;
-sfr at 0xE0 ACC ;
-sfr at 0xE0 A ;
-sfr at 0xF0 B ;
+__sfr __at 0x80 P0 ;
+__sfr __at 0x81 SP ;
+__sfr __at 0x82 DPL ;
+__sfr __at 0x83 DPH ;
+__sfr __at 0x87 PCON ;
+__sfr __at 0x88 TCON ;
+__sfr __at 0x89 TMOD ;
+__sfr __at 0x8A TL0 ;
+__sfr __at 0x8B TL1 ;
+__sfr __at 0x8C TH0 ;
+__sfr __at 0x8D TH1 ;
+__sfr __at 0x90 P1 ;
+__sfr __at 0x98 SCON ;
+__sfr __at 0x99 SBUF ;
+__sfr __at 0xA0 P2 ;
+__sfr __at 0xA8 IE ;
+__sfr __at 0xB0 P3 ;
+__sfr __at 0xB8 IP ;
+__sfr __at 0xC8 T2CON ;
+__sfr __at 0xC9 T2MOD ;
+__sfr __at 0xCA RCAP2L ;
+__sfr __at 0xCB RCAP2H ;
+__sfr __at 0xCC TL2 ;
+__sfr __at 0xCD TH2 ;
+__sfr __at 0xD0 PSW ;
+__sfr __at 0xE0 ACC ;
+__sfr __at 0xE0 A ;
+__sfr __at 0xF0 B ;
/* BIT addressable registers */
/* P0 */
-sbit at 0x80 P0_0 ;
-sbit at 0x81 P0_1 ;
-sbit at 0x82 P0_2 ;
-sbit at 0x83 P0_3 ;
-sbit at 0x84 P0_4 ;
-sbit at 0x85 P0_5 ;
-sbit at 0x86 P0_6 ;
-sbit at 0x87 P0_7 ;
+__sbit __at 0x80 P0_0 ;
+__sbit __at 0x81 P0_1 ;
+__sbit __at 0x82 P0_2 ;
+__sbit __at 0x83 P0_3 ;
+__sbit __at 0x84 P0_4 ;
+__sbit __at 0x85 P0_5 ;
+__sbit __at 0x86 P0_6 ;
+__sbit __at 0x87 P0_7 ;
/* TCON */
-sbit at 0x88 IT0 ;
-sbit at 0x89 IE0 ;
-sbit at 0x8A IT1 ;
-sbit at 0x8B IE1 ;
-sbit at 0x8C TR0 ;
-sbit at 0x8D TF0 ;
-sbit at 0x8E TR1 ;
-sbit at 0x8F TF1 ;
+__sbit __at 0x88 IT0 ;
+__sbit __at 0x89 IE0 ;
+__sbit __at 0x8A IT1 ;
+__sbit __at 0x8B IE1 ;
+__sbit __at 0x8C TR0 ;
+__sbit __at 0x8D TF0 ;
+__sbit __at 0x8E TR1 ;
+__sbit __at 0x8F TF1 ;
/* P1 */
-sbit at 0x90 P1_0 ;
-sbit at 0x91 P1_1 ;
-sbit at 0x92 P1_2 ;
-sbit at 0x93 P1_3 ;
-sbit at 0x94 P1_4 ;
-sbit at 0x95 P1_5 ;
-sbit at 0x96 P1_6 ;
-sbit at 0x97 P1_7 ;
+__sbit __at 0x90 P1_0 ;
+__sbit __at 0x91 P1_1 ;
+__sbit __at 0x92 P1_2 ;
+__sbit __at 0x93 P1_3 ;
+__sbit __at 0x94 P1_4 ;
+__sbit __at 0x95 P1_5 ;
+__sbit __at 0x96 P1_6 ;
+__sbit __at 0x97 P1_7 ;
-sbit at 0x90 T2 ;
-sbit at 0x91 T2EX ;
+__sbit __at 0x90 T2 ;
+__sbit __at 0x91 T2EX ;
/* SCON */
-sbit at 0x98 RI ;
-sbit at 0x99 TI ;
-sbit at 0x9A RB8 ;
-sbit at 0x9B TB8 ;
-sbit at 0x9C REN ;
-sbit at 0x9D SM2 ;
-sbit at 0x9E SM1 ;
-sbit at 0x9F SM0 ;
+__sbit __at 0x98 RI ;
+__sbit __at 0x99 TI ;
+__sbit __at 0x9A RB8 ;
+__sbit __at 0x9B TB8 ;
+__sbit __at 0x9C REN ;
+__sbit __at 0x9D SM2 ;
+__sbit __at 0x9E SM1 ;
+__sbit __at 0x9F SM0 ;
/* P2 */
-sbit at 0xA0 P2_0 ;
-sbit at 0xA1 P2_1 ;
-sbit at 0xA2 P2_2 ;
-sbit at 0xA3 P2_3 ;
-sbit at 0xA4 P2_4 ;
-sbit at 0xA5 P2_5 ;
-sbit at 0xA6 P2_6 ;
-sbit at 0xA7 P2_7 ;
+__sbit __at 0xA0 P2_0 ;
+__sbit __at 0xA1 P2_1 ;
+__sbit __at 0xA2 P2_2 ;
+__sbit __at 0xA3 P2_3 ;
+__sbit __at 0xA4 P2_4 ;
+__sbit __at 0xA5 P2_5 ;
+__sbit __at 0xA6 P2_6 ;
+__sbit __at 0xA7 P2_7 ;
/* IE */
-sbit at 0xA8 EX0 ;
-sbit at 0xA9 ET0 ;
-sbit at 0xAA EX1 ;
-sbit at 0xAB ET1 ;
-sbit at 0xAC ES ;
-sbit at 0xAD ET2 ;
-sbit at 0xAF EA ;
+__sbit __at 0xA8 EX0 ;
+__sbit __at 0xA9 ET0 ;
+__sbit __at 0xAA EX1 ;
+__sbit __at 0xAB ET1 ;
+__sbit __at 0xAC ES ;
+__sbit __at 0xAD ET2 ;
+__sbit __at 0xAF EA ;
/* P3 */
-sbit at 0xB0 P3_0 ;
-sbit at 0xB1 P3_1 ;
-sbit at 0xB2 P3_2 ;
-sbit at 0xB3 P3_3 ;
-sbit at 0xB4 P3_4 ;
-sbit at 0xB5 P3_5 ;
-sbit at 0xB6 P3_6 ;
-sbit at 0xB7 P3_7 ;
+__sbit __at 0xB0 P3_0 ;
+__sbit __at 0xB1 P3_1 ;
+__sbit __at 0xB2 P3_2 ;
+__sbit __at 0xB3 P3_3 ;
+__sbit __at 0xB4 P3_4 ;
+__sbit __at 0xB5 P3_5 ;
+__sbit __at 0xB6 P3_6 ;
+__sbit __at 0xB7 P3_7 ;
-sbit at 0xB0 RXD ;
-sbit at 0xB1 TXD ;
-sbit at 0xB2 INT0 ;
-sbit at 0xB3 INT1 ;
-sbit at 0xB4 T0 ;
-sbit at 0xB5 T1 ;
-sbit at 0xB6 WR ;
-sbit at 0xB7 RD ;
+__sbit __at 0xB0 RXD ;
+__sbit __at 0xB1 TXD ;
+__sbit __at 0xB2 INT0 ;
+__sbit __at 0xB3 INT1 ;
+__sbit __at 0xB4 T0 ;
+__sbit __at 0xB5 T1 ;
+__sbit __at 0xB6 WR ;
+__sbit __at 0xB7 RD ;
/* IP */
-sbit at 0xB8 PX0 ;
-sbit at 0xB9 PT0 ;
-sbit at 0xBA PX1 ;
-sbit at 0xBB PT1 ;
-sbit at 0xBC PS ;
-sbit at 0xBD PT2 ;
+__sbit __at 0xB8 PX0 ;
+__sbit __at 0xB9 PT0 ;
+__sbit __at 0xBA PX1 ;
+__sbit __at 0xBB PT1 ;
+__sbit __at 0xBC PS ;
+__sbit __at 0xBD PT2 ;
/* T2CON */
-sbit at 0xC8 T2CON_0 ;
-sbit at 0xC9 T2CON_1 ;
-sbit at 0xCA T2CON_2 ;
-sbit at 0xCB T2CON_3 ;
-sbit at 0xCC T2CON_4 ;
-sbit at 0xCD T2CON_5 ;
-sbit at 0xCE T2CON_6 ;
-sbit at 0xCF T2CON_7 ;
+__sbit __at 0xC8 T2CON_0 ;
+__sbit __at 0xC9 T2CON_1 ;
+__sbit __at 0xCA T2CON_2 ;
+__sbit __at 0xCB T2CON_3 ;
+__sbit __at 0xCC T2CON_4 ;
+__sbit __at 0xCD T2CON_5 ;
+__sbit __at 0xCE T2CON_6 ;
+__sbit __at 0xCF T2CON_7 ;
-sbit at 0xC8 CP_RL2 ;
-sbit at 0xC9 C_T2 ;
-sbit at 0xCA TR2 ;
-sbit at 0xCB EXEN2 ;
-sbit at 0xCC TCLK ;
-sbit at 0xCD RCLK ;
-sbit at 0xCE EXF2 ;
-sbit at 0xCF TF2 ;
+__sbit __at 0xC8 CP_RL2 ;
+__sbit __at 0xC9 C_T2 ;
+__sbit __at 0xCA TR2 ;
+__sbit __at 0xCB EXEN2 ;
+__sbit __at 0xCC TCLK ;
+__sbit __at 0xCD RCLK ;
+__sbit __at 0xCE EXF2 ;
+__sbit __at 0xCF TF2 ;
/* PSW */
-sbit at 0xD0 P ;
-sbit at 0xD1 FL ;
-sbit at 0xD2 OV ;
-sbit at 0xD3 RS0 ;
-sbit at 0xD4 RS1 ;
-sbit at 0xD5 F0 ;
-sbit at 0xD6 AC ;
-sbit at 0xD7 CY ;
+__sbit __at 0xD0 P ;
+__sbit __at 0xD1 FL ;
+__sbit __at 0xD2 OV ;
+__sbit __at 0xD3 RS0 ;
+__sbit __at 0xD4 RS1 ;
+__sbit __at 0xD5 F0 ;
+__sbit __at 0xD6 AC ;
+__sbit __at 0xD7 CY ;
/* BIT definitions for bits that are not directly accessible */
#ifndef DS400ROM_H_
#define DS400ROM_H_
-extern unsigned char init_rom(void xdata *loMem,
- void xdata *hiMem) _naked;
+extern unsigned char init_rom(void __xdata *loMem,
+ void __xdata *hiMem) __naked;
-extern unsigned long task_gettimemillis_long(void) _naked;
+extern unsigned long task_gettimemillis_long(void) __naked;
extern unsigned char task_getthreadID(void) _naked;
#ifndef DS80C390_H
#define DS80C390_H
-sfr at 0x80 P4; // ce3..ce0, a19..a16
-sfr at 0x81 SP; // stack pointer
-sfr at 0x82 DPL; // data pointer 0 lsb
-sfr at 0x83 DPH; // data pointer 0 msb
-sfr at 0x84 DPL1; // data pointer 1 lsb
-sfr at 0x85 DPH1; // data pointer 1 msb
-sfr at 0x86 DPS; // data pointer select
-sfr at 0x87 PCON; // power control
-sfr at 0x88 TCON; // timer/counter control
- sbit at 0x88 IT0;
- sbit at 0x89 IE0;
- sbit at 0x8a IT1;
- sbit at 0x8b IE1;
- sbit at 0x8c TR0;
- sbit at 0x8d TF0;
- sbit at 0x8e TR1;
- sbit at 0x8f TF1;
-sfr at 0x89 TMOD; // timer mode control
-sfr at 0x8a TL0; // timer 0 lsb
-sfr at 0x8b TL1; // timer 1 msb
-sfr at 0x8c TH0; // timer 0 msb
-sfr at 0x8d TH1; // timer 1 msb
-sfr at 0x8e CKCON; // clock control
-sfr at 0x90 P1;
- sbit at 0x90 T2;
- sbit at 0x91 T2EX;
- sbit at 0x92 RXD1;
- sbit at 0x93 TXD1;
- sbit at 0x94 INT2;
- sbit at 0x95 INT3;
- sbit at 0x96 INT4;
- sbit at 0x97 INT5;
-sfr at 0x91 EXIF; // external interrupt flag
-sfr at 0x92 P4CNT;
-sfr at 0x93 DPX; // extended datapointer 0
-sfr at 0x95 DPX1; // extended datapointer 1
-sfr at 0x98 SCON0; // serial 0 control
- sbit at 0x98 RI_0;
- sbit at 0x99 TI_0;
- sbit at 0x9a RB8_0;
- sbit at 0x9b TB8_0;
- sbit at 0x9c REN_0;
- sbit at 0x9d SM2_0;
- sbit at 0x9e SM1_0;
- sbit at 0x9f SM0_0;
- sbit at 0x9f FE_0; // depending on SMOD0
-sfr at 0x99 SBUF0; // serial 0 data buffer
-sfr at 0x9b ESP; // extended stack pointer
-sfr at 0x9c AP; // address page
-sfr at 0x9d ACON; // address control
-sfr at 0xa0 P2; // never mind the sbits
-sfr at 0xa1 P5;
-sfr at 0xa2 P5CNT;
-sfr at 0xa8 IE; // interrupt enable
- sbit at 0xa8 EX0;
- sbit at 0xa9 ET0;
- sbit at 0xaa EX1;
- sbit at 0xab ET1;
- sbit at 0xac ES0;
- sbit at 0xad ET2;
- sbit at 0xae ES1;
- sbit at 0xaf EA;
-sfr at 0xb0 P3;
- sbit at 0xb0 RXD0;
- sbit at 0xb1 TXD0;
- sbit at 0xb2 INT0;
- sbit at 0xb3 INT1;
- sbit at 0xb4 T0;
- sbit at 0xb5 T1;
- sbit at 0xb6 WR;
- sbit at 0xb7 RD;
-sfr at 0xb8 IP; // interupt priority
- sbit at 0xb8 PX0; // external 0
- sbit at 0xb9 PT0; // timer 0
- sbit at 0xba PX1; // external 1
- sbit at 0xbb PT1; // timer 1
- sbit at 0xbc PS0; // serial port 0
- sbit at 0xbd PT2; // timer 2
- sbit at 0xbe PS1; // serial port 1
-sfr at 0xc0 SCON1; // serial 1 control
- sbit at 0xc0 RI_1;
- sbit at 0xc1 TI_1;
- sbit at 0xc2 RB8_1;
- sbit at 0xc3 TB8_1;
- sbit at 0xc4 REN_1;
- sbit at 0xc5 SM2_1;
- sbit at 0xc6 SM1_1;
- sbit at 0xc7 SM0_1;
- sbit at 0xc7 FE_1; // depending on SMOD0
-sfr at 0xc1 SBUF1; // serial 1 data buffer
-sfr at 0xc4 PMR; // power managment
-sfr at 0xc6 MCON; // memory control register
-sfr at 0xc7 TA; // timed access register
-sfr at 0xc8 T2CON; // timer 2 control
- sbit at 0xc8 CP_RL; // capture/reload
- sbit at 0xc9 C_T; // count/timer
- sbit at 0xca TR2; // stop/run
- sbit at 0xcb EXEN2;
- sbit at 0xcc TCLK;
- sbit at 0xcd RCLK;
- sbit at 0xce EXF2;
- sbit at 0xcf TF2; // overflow flag
-sfr at 0xc9 T2MOD; // timer 2 mode
-sfr at 0xca RCAP2L; // timer 2 capture/reload
-sfr at 0xca RTL2; // depends on CP_RL
-sfr at 0xcb RCAP2H;
-sfr at 0xcb RTH2;
-sfr at 0xcc TL2; // timer 2 lsb
-sfr at 0xcd TH2; // timer 2 msb
-sfr at 0xd0 PSW; // program status word (byte actually)
- sbit at 0xd0 P; // parity
- sbit at 0xd1 F1; // user flag 1
- sbit at 0xd2 OV; // overflow flag
- sbit at 0xd3 RS0; // register select l
- sbit at 0xd4 RS1; // register select h
- sbit at 0xd5 F0; // user flag 0
- sbit at 0xd6 AC; // auxiliary carry flag
- sbit at 0xd7 CY; // carry flag
-sfr at 0xd1 MCNT0; // arithmetic accellerator
-sfr at 0xd2 MCNT1;
-sfr at 0xd3 MA;
-sfr at 0xd4 MB;
-sfr at 0xd5 MC;
-sfr at 0xd8 WDCON; // watch dog
- sbit at 0xd8 RWT;
- sbit at 0xd9 EWT;
- sbit at 0xda WDRF;
- sbit at 0xdb WDIF;
- sbit at 0xdc PFI;
- sbit at 0xdd EPFI;
- sbit at 0xde POR;
- sbit at 0xdf SMOD_1;
-sfr at 0xe0 ACC; // accumulator
-sfr at 0xe8 EIE; // extended interrupt enable
- sbit at 0xe8 EX2;
- sbit at 0xe9 EX3;
- sbit at 0xea EX4;
- sbit at 0xeb EX5;
- sbit at 0xec EWDI;
- sbit at 0xed C1IE;
- sbit at 0xee C0IE;
- sbit at 0xef CANBIE;
-sfr at 0xea MXAX; // extended address register
-sfr at 0xf0 B; // aux accumulator
-sfr at 0xf8 EIP; // extended interrupt priority
- sbit at 0xf8 PX2;
- sbit at 0xf9 PX3;
- sbit at 0xfa PX4;
- sbit at 0xfb PX5;
- sbit at 0xfc PWDI;
- sbit at 0xfd C1IP;
- sbit at 0xfe C0IP;
- sbit at 0xff CANBIP;
+__sfr __at 0x80 P4; // ce3..ce0, a19..a16
+__sfr __at 0x81 SP; // stack pointer
+__sfr __at 0x82 DPL; // data pointer 0 lsb
+__sfr __at 0x83 DPH; // data pointer 0 msb
+__sfr __at 0x84 DPL1; // data pointer 1 lsb
+__sfr __at 0x85 DPH1; // data pointer 1 msb
+__sfr __at 0x86 DPS; // data pointer select
+__sfr __at 0x87 PCON; // power control
+__sfr __at 0x88 TCON; // timer/counter control
+ __sbit __at 0x88 IT0;
+ __sbit __at 0x89 IE0;
+ __sbit __at 0x8a IT1;
+ __sbit __at 0x8b IE1;
+ __sbit __at 0x8c TR0;
+ __sbit __at 0x8d TF0;
+ __sbit __at 0x8e TR1;
+ __sbit __at 0x8f TF1;
+__sfr __at 0x89 TMOD; // timer mode control
+__sfr __at 0x8a TL0; // timer 0 lsb
+__sfr __at 0x8b TL1; // timer 1 msb
+__sfr __at 0x8c TH0; // timer 0 msb
+__sfr __at 0x8d TH1; // timer 1 msb
+__sfr __at 0x8e CKCON; // clock control
+__sfr __at 0x90 P1;
+ __sbit __at 0x90 T2;
+ __sbit __at 0x91 T2EX;
+ __sbit __at 0x92 RXD1;
+ __sbit __at 0x93 TXD1;
+ __sbit __at 0x94 INT2;
+ __sbit __at 0x95 INT3;
+ __sbit __at 0x96 INT4;
+ __sbit __at 0x97 INT5;
+__sfr __at 0x91 EXIF; // external interrupt flag
+__sfr __at 0x92 P4CNT;
+__sfr __at 0x93 DPX; // extended datapointer 0
+__sfr __at 0x95 DPX1; // extended datapointer 1
+__sfr __at 0x98 SCON0; // serial 0 control
+ __sbit __at 0x98 RI_0;
+ __sbit __at 0x99 TI_0;
+ __sbit __at 0x9a RB8_0;
+ __sbit __at 0x9b TB8_0;
+ __sbit __at 0x9c REN_0;
+ __sbit __at 0x9d SM2_0;
+ __sbit __at 0x9e SM1_0;
+ __sbit __at 0x9f SM0_0;
+ __sbit __at 0x9f FE_0; // depending on SMOD0
+__sfr __at 0x99 SBUF0; // serial 0 data buffer
+__sfr __at 0x9b ESP; // extended stack pointer
+__sfr __at 0x9c AP; // address page
+__sfr __at 0x9d ACON; // address control
+__sfr __at 0xa0 P2; // never mind the sbits
+__sfr __at 0xa1 P5;
+__sfr __at 0xa2 P5CNT;
+__sfr __at 0xa8 IE; // interrupt enable
+ __sbit __at 0xa8 EX0;
+ __sbit __at 0xa9 ET0;
+ __sbit __at 0xaa EX1;
+ __sbit __at 0xab ET1;
+ __sbit __at 0xac ES0;
+ __sbit __at 0xad ET2;
+ __sbit __at 0xae ES1;
+ __sbit __at 0xaf EA;
+__sfr __at 0xb0 P3;
+ __sbit __at 0xb0 RXD0;
+ __sbit __at 0xb1 TXD0;
+ __sbit __at 0xb2 INT0;
+ __sbit __at 0xb3 INT1;
+ __sbit __at 0xb4 T0;
+ __sbit __at 0xb5 T1;
+ __sbit __at 0xb6 WR;
+ __sbit __at 0xb7 RD;
+__sfr __at 0xb8 IP; // interupt priority
+ __sbit __at 0xb8 PX0; // external 0
+ __sbit __at 0xb9 PT0; // timer 0
+ __sbit __at 0xba PX1; // external 1
+ __sbit __at 0xbb PT1; // timer 1
+ __sbit __at 0xbc PS0; // serial port 0
+ __sbit __at 0xbd PT2; // timer 2
+ __sbit __at 0xbe PS1; // serial port 1
+__sfr __at 0xc0 SCON1; // serial 1 control
+ __sbit __at 0xc0 RI_1;
+ __sbit __at 0xc1 TI_1;
+ __sbit __at 0xc2 RB8_1;
+ __sbit __at 0xc3 TB8_1;
+ __sbit __at 0xc4 REN_1;
+ __sbit __at 0xc5 SM2_1;
+ __sbit __at 0xc6 SM1_1;
+ __sbit __at 0xc7 SM0_1;
+ __sbit __at 0xc7 FE_1; // depending on SMOD0
+__sfr __at 0xc1 SBUF1; // serial 1 data buffer
+__sfr __at 0xc4 PMR; // power managment
+__sfr __at 0xc6 MCON; // memory control register
+__sfr __at 0xc7 TA; // timed access register
+__sfr __at 0xc8 T2CON; // timer 2 control
+ __sbit __at 0xc8 CP_RL; // capture/reload
+ __sbit __at 0xc9 C_T; // count/timer
+ __sbit __at 0xca TR2; // stop/run
+ __sbit __at 0xcb EXEN2;
+ __sbit __at 0xcc TCLK;
+ __sbit __at 0xcd RCLK;
+ __sbit __at 0xce EXF2;
+ __sbit __at 0xcf TF2; // overflow flag
+__sfr __at 0xc9 T2MOD; // timer 2 mode
+__sfr __at 0xca RCAP2L; // timer 2 capture/reload
+__sfr __at 0xca RTL2; // depends on CP_RL
+__sfr __at 0xcb RCAP2H;
+__sfr __at 0xcb RTH2;
+__sfr __at 0xcc TL2; // timer 2 lsb
+__sfr __at 0xcd TH2; // timer 2 msb
+__sfr __at 0xd0 PSW; // program status word (byte actually)
+ __sbit __at 0xd0 P; // parity
+ __sbit __at 0xd1 F1; // user flag 1
+ __sbit __at 0xd2 OV; // overflow flag
+ __sbit __at 0xd3 RS0; // register select l
+ __sbit __at 0xd4 RS1; // register select h
+ __sbit __at 0xd5 F0; // user flag 0
+ __sbit __at 0xd6 AC; // auxiliary carry flag
+ __sbit __at 0xd7 CY; // carry flag
+__sfr __at 0xd1 MCNT0; // arithmetic accellerator
+__sfr __at 0xd2 MCNT1;
+__sfr __at 0xd3 MA;
+__sfr __at 0xd4 MB;
+__sfr __at 0xd5 MC;
+__sfr __at 0xd8 WDCON; // watch dog
+ __sbit __at 0xd8 RWT;
+ __sbit __at 0xd9 EWT;
+ __sbit __at 0xda WDRF;
+ __sbit __at 0xdb WDIF;
+ __sbit __at 0xdc PFI;
+ __sbit __at 0xdd EPFI;
+ __sbit __at 0xde POR;
+ __sbit __at 0xdf SMOD_1;
+__sfr __at 0xe0 ACC; // accumulator
+__sfr __at 0xe8 EIE; // extended interrupt enable
+ __sbit __at 0xe8 EX2;
+ __sbit __at 0xe9 EX3;
+ __sbit __at 0xea EX4;
+ __sbit __at 0xeb EX5;
+ __sbit __at 0xec EWDI;
+ __sbit __at 0xed C1IE;
+ __sbit __at 0xee C0IE;
+ __sbit __at 0xef CANBIE;
+__sfr __at 0xea MXAX; // extended address register
+__sfr __at 0xf0 B; // aux accumulator
+__sfr __at 0xf8 EIP; // extended interrupt priority
+ __sbit __at 0xf8 PX2;
+ __sbit __at 0xf9 PX3;
+ __sbit __at 0xfa PX4;
+ __sbit __at 0xfb PX5;
+ __sbit __at 0xfc PWDI;
+ __sbit __at 0xfd C1IP;
+ __sbit __at 0xfe C0IP;
+ __sbit __at 0xff CANBIP;
#endif /* DS80C390_H */
--- /dev/null
+/*-------------------------------------------------------------------------
+ Register Declarations for Motorola MC68HC908GP32
+
+ Copyright (c) 2004, Juan Gonzalez <juan@iearobotics.com>
+
+ Based on mc68hc908qy.h,
+ Written By - Erik Petrich
+ epetrich@users.sourceforge.net (2003)
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2, or (__at your option) any
+ later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+ In other words, you are welcome to use, share and improve this program.
+ You are forbidden to forbid anyone else to use, share and improve
+ what you give them. Help stamp out software-hoarding!
+-------------------------------------------------------------------------*/
+
+#ifndef _MC68HC908GP32_H
+#define _MC68HC908GP32_H
+
+#ifndef _UINT8
+ #define _UINT8 unsigned char
+#endif
+#ifndef _UINT16
+ #define _UINT16 unsigned int
+#endif
+#ifndef _VOLDATA
+ #define _VOLDATA volatile __data
+#endif
+#ifndef _VOLXDATA
+ #define _VOLXDATA volatile __xdata
+#endif
+
+struct __hc08_bits
+{
+ unsigned int bit0:1;
+ unsigned int bit1:1;
+ unsigned int bit2:1;
+ unsigned int bit3:1;
+ unsigned int bit4:1;
+ unsigned int bit5:1;
+ unsigned int bit6:1;
+ unsigned int bit7:1;
+};
+
+
+_VOLDATA _UINT8 __at 0x00 PTA; /* Port A Data Register */
+#define PORTA PTA /* Alias for PTA */
+ #define PTA0 ((struct __hc08_bits *)(&PTA))->bit0
+ #define PTA1 ((struct __hc08_bits *)(&PTA))->bit1
+ #define PTA2 ((struct __hc08_bits *)(&PTA))->bit2
+ #define PTA3 ((struct __hc08_bits *)(&PTA))->bit3
+ #define PTA4 ((struct __hc08_bits *)(&PTA))->bit4
+ #define PTA5 ((struct __hc08_bits *)(&PTA))->bit5
+ #define AWUL ((struct __hc08_bits *)(&PTA))->bit6
+
+_VOLDATA _UINT8 __at 0x01 PTB; /* Port B Data Register */
+#define PORTB PTB /* Alias for PTB */
+ #define PTB0 ((struct __hc08_bits *)(&PTB))->bit0
+ #define PTB1 ((struct __hc08_bits *)(&PTB))->bit1
+ #define PTB2 ((struct __hc08_bits *)(&PTB))->bit2
+ #define PTB3 ((struct __hc08_bits *)(&PTB))->bit3
+ #define PTB4 ((struct __hc08_bits *)(&PTB))->bit4
+ #define PTB5 ((struct __hc08_bits *)(&PTB))->bit5
+ #define PTB6 ((struct __hc08_bits *)(&PTB))->bit6
+ #define PTB7 ((struct __hc08_bits *)(&PTB))->bit7
+
+_VOLDATA _UINT8 __at 0x02 PTC; /* Port C Data Register */
+#define PORTC PTC /* Alias for PTC */
+ #define PTC0 ((struct __hc08_bits *)(&PTC))->bit0
+ #define PTC1 ((struct __hc08_bits *)(&PTC))->bit1
+ #define PTC2 ((struct __hc08_bits *)(&PTC))->bit2
+ #define PTC3 ((struct __hc08_bits *)(&PTC))->bit3
+ #define PTC4 ((struct __hc08_bits *)(&PTC))->bit4
+ #define PTC5 ((struct __hc08_bits *)(&PTC))->bit5
+ #define PTC6 ((struct __hc08_bits *)(&PTC))->bit6
+ #define PTC7 ((struct __hc08_bits *)(&PTC))->bit7
+
+_VOLDATA _UINT8 __at 0x03 PTD; /* Port D Data Register */
+#define PORTD PTD /* Alias for PTD */
+ #define PTD0 ((struct __hc08_bits *)(&PTD))->bit0
+ #define PTD1 ((struct __hc08_bits *)(&PTD))->bit1
+ #define PTD2 ((struct __hc08_bits *)(&PTD))->bit2
+ #define PTD3 ((struct __hc08_bits *)(&PTD))->bit3
+ #define PTD4 ((struct __hc08_bits *)(&PTD))->bit4
+ #define PTD5 ((struct __hc08_bits *)(&PTD))->bit5
+ #define PTD6 ((struct __hc08_bits *)(&PTD))->bit6
+ #define PTD7 ((struct __hc08_bits *)(&PTD))->bit7
+
+_VOLDATA _UINT8 __at 0x04 DDRA; /* Data Direction Register A */
+ #define DDRA0 ((struct __hc08_bits *)(&DDRA))->bit0
+ #define DDRA1 ((struct __hc08_bits *)(&DDRA))->bit1
+ #define DDRA2 ((struct __hc08_bits *)(&DDRA))->bit2
+ #define DDRA3 ((struct __hc08_bits *)(&DDRA))->bit3
+ #define DDRA4 ((struct __hc08_bits *)(&DDRA))->bit4
+ #define DDRA5 ((struct __hc08_bits *)(&DDRA))->bit5
+ #define DDRA6 ((struct __hc08_bits *)(&DDRA))->bit6
+ #define DDRA7 ((struct __hc08_bits *)(&DDRA))->bit7
+
+_VOLDATA _UINT8 __at 0x05 DDRB; /* Data Direction Register B */
+ #define DDRB0 ((struct __hc08_bits *)(&DDRB))->bit0
+ #define DDRB1 ((struct __hc08_bits *)(&DDRB))->bit1
+ #define DDRB2 ((struct __hc08_bits *)(&DDRB))->bit2
+ #define DDRB3 ((struct __hc08_bits *)(&DDRB))->bit3
+ #define DDRB4 ((struct __hc08_bits *)(&DDRB))->bit4
+ #define DDRB5 ((struct __hc08_bits *)(&DDRB))->bit5
+ #define DDRB6 ((struct __hc08_bits *)(&DDRB))->bit6
+ #define DDRB7 ((struct __hc08_bits *)(&DDRB))->bit7
+
+_VOLDATA _UINT8 __at 0x06 DDRC; /* Data Direction Register C */
+ #define DDRC0 ((struct __hc08_bits *)(&DDRC))->bit0
+ #define DDRC1 ((struct __hc08_bits *)(&DDRC))->bit1
+ #define DDRC2 ((struct __hc08_bits *)(&DDRC))->bit2
+ #define DDRC3 ((struct __hc08_bits *)(&DDRC))->bit3
+ #define DDRC4 ((struct __hc08_bits *)(&DDRC))->bit4
+ #define DDRC5 ((struct __hc08_bits *)(&DDRC))->bit5
+ #define DDRC6 ((struct __hc08_bits *)(&DDRC))->bit6
+ #define DDRC7 ((struct __hc08_bits *)(&DDRC))->bit7
+
+_VOLDATA _UINT8 __at 0x07 DDRD; /* Data Direction Register D */
+ #define DDRD0 ((struct __hc08_bits *)(&DDRD))->bit0
+ #define DDRD1 ((struct __hc08_bits *)(&DDRD))->bit1
+ #define DDRD2 ((struct __hc08_bits *)(&DDRD))->bit2
+ #define DDRD3 ((struct __hc08_bits *)(&DDRD))->bit3
+ #define DDRD4 ((struct __hc08_bits *)(&DDRD))->bit4
+ #define DDRD5 ((struct __hc08_bits *)(&DDRD))->bit5
+ #define DDRD6 ((struct __hc08_bits *)(&DDRD))->bit6
+ #define DDRD7 ((struct __hc08_bits *)(&DDRD))->bit7
+
+_VOLDATA _UINT8 __at 0x08 PTE; /* Port E Data Register */
+#define PORTE PTE /* Alias for PTE */
+ #define PTE0 ((struct __hc08_bits *)(&PTE))->bit0
+ #define PTE1 ((struct __hc08_bits *)(&PTE))->bit1
+ #define PTE2 ((struct __hc08_bits *)(&PTE))->bit2
+ #define PTE3 ((struct __hc08_bits *)(&PTE))->bit3
+ #define PTE4 ((struct __hc08_bits *)(&PTE))->bit4
+ #define PTE5 ((struct __hc08_bits *)(&PTE))->bit5
+ #define PTE6 ((struct __hc08_bits *)(&PTE))->bit6
+ #define PTE7 ((struct __hc08_bits *)(&PTE))->bit7
+
+_VOLDATA _UINT8 __at 0x0C DDRE; /* Data Direction Register E */
+ #define DDRE0 ((struct __hc08_bits *)(&DDRE))->bit0
+ #define DDRE1 ((struct __hc08_bits *)(&DDRE))->bit1
+ #define DDRE2 ((struct __hc08_bits *)(&DDRE))->bit2
+ #define DDRE3 ((struct __hc08_bits *)(&DDRE))->bit3
+ #define DDRE4 ((struct __hc08_bits *)(&DDRE))->bit4
+ #define DDRE5 ((struct __hc08_bits *)(&DDRE))->bit5
+ #define DDRE6 ((struct __hc08_bits *)(&DDRE))->bit6
+ #define DDRE7 ((struct __hc08_bits *)(&DDRE))->bit7
+
+_VOLDATA _UINT8 __at 0x0D PTAPUE; /* Port A pull-up enables */
+ #define PTAPUE0 ((struct __hc08_bits *)(&PTAPUE))->bit0
+ #define PTAPUE1 ((struct __hc08_bits *)(&PTAPUE))->bit1
+ #define PTAPUE2 ((struct __hc08_bits *)(&PTAPUE))->bit2
+ #define PTAPUE3 ((struct __hc08_bits *)(&PTAPUE))->bit3
+ #define PTAPUE4 ((struct __hc08_bits *)(&PTAPUE))->bit4
+ #define PTAPUE5 ((struct __hc08_bits *)(&PTAPUE))->bit5
+ #define PTAPUE6 ((struct __hc08_bits *)(&PTAPUE))->bit6
+ #define PTAPUE7 ((struct __hc08_bits *)(&PTAPUE))->bit7
+
+_VOLDATA _UINT8 __at 0x0E PTCPUE; /* Port C pull-up enables */
+ #define PTCPUE0 ((struct __hc08_bits *)(&PTCPUE))->bit0
+ #define PTCPUE1 ((struct __hc08_bits *)(&PTCPUE))->bit1
+ #define PTCPUE2 ((struct __hc08_bits *)(&PTCPUE))->bit2
+ #define PTCPUE3 ((struct __hc08_bits *)(&PTCPUE))->bit3
+ #define PTCPUE4 ((struct __hc08_bits *)(&PTCPUE))->bit4
+ #define PTCPUE5 ((struct __hc08_bits *)(&PTCPUE))->bit5
+ #define PTCPUE6 ((struct __hc08_bits *)(&PTCPUE))->bit6
+ /* PTCPUE7 does not exit! */
+
+_VOLDATA _UINT8 __at 0x0F PTDPUE; /* port D pull-up enables */
+ #define PTDPUE0 ((struct __hc08_bits *)(&PTDPUE))->bit0
+ #define PTDPUE1 ((struct __hc08_bits *)(&PTDPUE))->bit1
+ #define PTDPUE2 ((struct __hc08_bits *)(&PTDPUE))->bit2
+ #define PTDPUE3 ((struct __hc08_bits *)(&PTDPUE))->bit3
+ #define PTDPUE4 ((struct __hc08_bits *)(&PTDPUE))->bit4
+ #define PTDPUE5 ((struct __hc08_bits *)(&PTDPUE))->bit5
+ #define PTDPUE6 ((struct __hc08_bits *)(&PTDPUE))->bit6
+ #define PTDPUE7 ((struct __hc08_bits *)(&PTDPUE))->bit7
+
+_VOLDATA _UINT8 __at 0x10 SPCR; /* SPI Control Register */
+ #define SPRIE ((struct __hc08_bits *)(&SPCR))->bit7
+ #define DMAS ((struct __hc08_bits *)(&SPCR))->bit6
+ #define SPMSTR ((struct __hc08_bits *)(&SPCR))->bit5
+ #define CPOL ((struct __hc08_bits *)(&SPCR))->bit4
+ #define CPHA ((struct __hc08_bits *)(&SPCR))->bit3
+ #define SPWOM ((struct __hc08_bits *)(&SPCR))->bit2
+ #define SPE ((struct __hc08_bits *)(&SPCR))->bit1
+ #define SPTIE ((struct __hc08_bits *)(&SPCR))->bit0
+
+_VOLDATA _UINT8 __at 0x11 SPSCR; /* SPI Status and Control Register */
+ #define SPRF ((struct __hc08_bits *)(&SPSCR))->bit7
+ #define ERRIE ((struct __hc08_bits *)(&SPSCR))->bit6
+ #define OVRF ((struct __hc08_bits *)(&SPSCR))->bit5
+ #define MODF ((struct __hc08_bits *)(&SPSCR))->bit4
+ #define SPTE ((struct __hc08_bits *)(&SPSCR))->bit3
+ #define MODFEN ((struct __hc08_bits *)(&SPSCR))->bit2
+ #define SPR1 ((struct __hc08_bits *)(&SPSCR))->bit1
+ #define SPR0 ((struct __hc08_bits *)(&SPSCR))->bit0
+
+_VOLDATA _UINT8 __at 0x12 SPDR; /* SPI Data Register */
+
+_VOLDATA _UINT8 __at 0x13 SCC1; /* SCI Control Register 1 */
+ #define LOOPS ((struct __hc08_bits *)(&SCC1))->bit7
+ #define ENSCI ((struct __hc08_bits *)(&SCC1))->bit6
+ #define TXINV ((struct __hc08_bits *)(&SCC1))->bit5
+ #define M ((struct __hc08_bits *)(&SCC1))->bit4
+ #define WAKE ((struct __hc08_bits *)(&SCC1))->bit3
+ #define ILTY ((struct __hc08_bits *)(&SCC1))->bit2
+ #define PEN ((struct __hc08_bits *)(&SCC1))->bit1
+ #define PTY ((struct __hc08_bits *)(&SCC1))->bit0
+
+
+_VOLDATA _UINT8 __at 0x14 SCC2; /* SCI Control Register 2 */
+ #define SCTIE ((struct __hc08_bits *)(&SCC2))->bit7
+ #define TCIE ((struct __hc08_bits *)(&SCC2))->bit6
+ #define SCRIE ((struct __hc08_bits *)(&SCC2))->bit5
+ #define ILIE ((struct __hc08_bits *)(&SCC2))->bit4
+ #define TE ((struct __hc08_bits *)(&SCC2))->bit3
+ #define RE ((struct __hc08_bits *)(&SCC2))->bit2
+ #define WRU ((struct __hc08_bits *)(&SCC2))->bit1
+ #define SBK ((struct __hc08_bits *)(&SCC2))->bit0
+
+_VOLDATA _UINT8 __at 0x15 SCC3; /* SCI Control Register 3 */
+ #define SCC3_R8 ((struct __hc08_bits *)(&SCC3))->bit7
+ #define SCC3_TB ((struct __hc08_bits *)(&SCC3))->bit6
+ #define DMARE ((struct __hc08_bits *)(&SCC3))->bit5
+ #define DMATE ((struct __hc08_bits *)(&SCC3))->bit4
+ #define ORIE ((struct __hc08_bits *)(&SCC3))->bit3
+ #define NEIE ((struct __hc08_bits *)(&SCC3))->bit2
+ #define FEIE ((struct __hc08_bits *)(&SCC3))->bit1
+ #define PEIE ((struct __hc08_bits *)(&SCC3))->bit0
+
+_VOLDATA _UINT8 __at 0x16 SCS1; /* SCI Status Register 1 */
+ #define SCTE ((struct __hc08_bits *)(&SCS1))->bit7
+ #define TC ((struct __hc08_bits *)(&SCS1))->bit6
+ #define SCRF ((struct __hc08_bits *)(&SCS1))->bit5
+ #define IDLE ((struct __hc08_bits *)(&SCS1))->bit4
+ #define OR ((struct __hc08_bits *)(&SCS1))->bit3
+ #define NF ((struct __hc08_bits *)(&SCS1))->bit2
+ #define FE ((struct __hc08_bits *)(&SCS1))->bit1
+ #define PE ((struct __hc08_bits *)(&SCS1))->bit0
+
+_VOLDATA _UINT8 __at 0x17 SCS2; /* SCI Status Register 2 */
+ #define RPF ((struct __hc08_bits *)(&SCS2))->bit0
+ #define BKF ((struct __hc08_bits *)(&SCS2))->bit1
+ /* Bits 2-7 not implemented */
+
+_VOLDATA _UINT8 __at 0x18 SCDR; /* SCI Data Register */
+
+_VOLDATA _UINT8 __at 0x19 SCBR; /* SCI Baud Rate Register */
+ #define SCP1 ((struct __hc08_bits *)(&SCBR))->bit5
+ #define SCP0 ((struct __hc08_bits *)(&SCBR))->bit4
+ #define R ((struct __hc08_bits *)(&SCBR))->bit3
+ #define SCR2 ((struct __hc08_bits *)(&SCBR))->bit2
+ #define SCR1 ((struct __hc08_bits *)(&SCBR))->bit1
+ #define SCR0 ((struct __hc08_bits *)(&SCBR))->bit0
+ /*-- Bits 6 and 7 do not exist */
+
+_VOLDATA _UINT8 __at 0x1a INTKBSCR; /* Keyboard Status and Control Register */
+ #define KEYF ((struct __hc08_bits *)(&INTKBSCR))->bit3
+ #define ACKK ((struct __hc08_bits *)(&INTKBSCR))->bit2
+ #define IMASKK ((struct __hc08_bits *)(&INTKBSCR))->bit1
+ #define MODEK ((struct __hc08_bits *)(&INTKBSCR))->bit0
+ /*-- Bits 4-7 do not exist */
+
+_VOLDATA _UINT8 __at 0x1b INTKBIER; /* Keyboard Interrupt Enable Register */
+ #define KBIE7 ((struct __hc08_bits *)(&INTKBIER))->bit7
+ #define KBIE6 ((struct __hc08_bits *)(&INTKBIER))->bit6
+ #define KBIE5 ((struct __hc08_bits *)(&INTKBIER))->bit5
+ #define KBIE4 ((struct __hc08_bits *)(&INTKBIER))->bit4
+ #define KBIE3 ((struct __hc08_bits *)(&INTKBIER))->bit3
+ #define KBIE2 ((struct __hc08_bits *)(&INTKBIER))->bit2
+ #define KBIE1 ((struct __hc08_bits *)(&INTKBIER))->bit1
+ #define KBIE0 ((struct __hc08_bits *)(&INTKBIER))->bit0
+
+_VOLDATA _UINT8 __at 0x1C TBCR; /* Time Base Module Control */
+ #define TBIF ((struct __hc08_bits *)(&TBCR))->bit7
+ #define TBR2 ((struct __hc08_bits *)(&TBCR))->bit6
+ #define TBR1 ((struct __hc08_bits *)(&TBCR))->bit5
+ #define TBR0 ((struct __hc08_bits *)(&TBCR))->bit4
+ #define TACK ((struct __hc08_bits *)(&TBCR))->bit3
+ #define TBIE ((struct __hc08_bits *)(&TBCR))->bit2
+ #define TBON ((struct __hc08_bits *)(&TBCR))->bit1
+ /* Bit 0 Reserved */
+
+_VOLDATA _UINT8 __at 0x1D INTSCR; /* IRQ status/control */
+ #define IRQF1 ((struct __hc08_bits *)(&INTSCR))->bit3
+ #define ACK1 ((struct __hc08_bits *)(&INTSCR))->bit2
+ #define IMASK1 ((struct __hc08_bits *)(&INTSCR))->bit1
+ #define MODE1 ((struct __hc08_bits *)(&INTSCR))->bit0
+ /* Bits 4-7 unimplemented */
+
+_VOLDATA _UINT8 __at 0x1e CONFIG2; /* Configuration Register 2 */
+/* CONFIG2 is one-time writeble, so can't use bitfields */
+
+_VOLDATA _UINT8 __at 0x1f CONFIG1; /* Configuration Register 1 */
+/* CONFIG1 is one-time writeable, so can't use bitfields */
+
+_VOLDATA _UINT8 __at 0x20 T1SC; /* TIM 1 Status and Control */
+ #define PS0 ((struct __hc08_bits *)(&T1SC))->bit0
+ #define PS1 ((struct __hc08_bits *)(&T1SC))->bit1
+ #define PS2 ((struct __hc08_bits *)(&T1SC))->bit2
+ #define TRST ((struct __hc08_bits *)(&T1SC))->bit4
+ #define TSTOP ((struct __hc08_bits *)(&T1SC))->bit5
+ #define TOIE ((struct __hc08_bits *)(&T1SC))->bit6
+ #define TOF ((struct __hc08_bits *)(&T1SC))->bit7
+
+_VOLDATA _UINT16 __at 0x21 T1CNT; /* TIM1 Counter High & Low Registers */
+_VOLDATA _UINT8 __at 0x21 T1CNTH; /* TIM1 Counter Register High */
+_VOLDATA _UINT8 __at 0x22 T1CNTL; /* TIM1 Counter Register Low */
+
+_VOLDATA _UINT16 __at 0x23 T1MOD; /* TIM1 Counter Modulo High & Low Registers */
+_VOLDATA _UINT8 __at 0x23 T1MODH; /* TIM1 Counter Modulo Register High */
+_VOLDATA _UINT8 __at 0x24 T1MODL; /* TIM1 Counter Modulo Register Low */
+
+_VOLDATA _UINT8 __at 0x25 T1SC0; /* TIM1 Channel 0 Status and Control Register */
+ #define CH0MAX ((struct __hc08_bits *)(&T1SC0))->bit0
+ #define TOV0 ((struct __hc08_bits *)(&T1SC0))->bit1
+ #define ELS0A ((struct __hc08_bits *)(&T1SC0))->bit2
+ #define ELS0B ((struct __hc08_bits *)(&T1SC0))->bit3
+ #define MS0A ((struct __hc08_bits *)(&T1SC0))->bit4
+ #define MS0B ((struct __hc08_bits *)(&T1SC0))->bit5
+ #define CH0IE ((struct __hc08_bits *)(&T1SC0))->bit6
+ #define CH0F ((struct __hc08_bits *)(&T1SC0))->bit7
+
+_VOLDATA _UINT16 __at 0x26 T1CH0; /* TIM1 Channel 0 High & Low Registers */
+_VOLDATA _UINT8 __at 0x26 T1CH0H; /* TIM1 Channel 0 Register High */
+_VOLDATA _UINT8 __at 0x27 T1CH0L; /* TIM1 Channel 0 Register Low */
+
+_VOLDATA _UINT8 __at 0x28 T1SC1; /* TIM1 Channel 1 Status and Control Register */
+ #define CH1MAX ((struct __hc08_bits *)(&T1SC1))->bit0
+ #define TOV1 ((struct __hc08_bits *)(&T1SC1))->bit1
+ #define ELS1A ((struct __hc08_bits *)(&T1SC1))->bit2
+ #define ELS1B ((struct __hc08_bits *)(&T1SC1))->bit3
+ #define MS1A ((struct __hc08_bits *)(&T1SC1))->bit4
+ #define CH1IE ((struct __hc08_bits *)(&T1SC1))->bit6
+ #define CH1F ((struct __hc08_bits *)(&T1SC1))->bit7
+
+_VOLDATA _UINT16 __at 0x29 T1CH1; /* TIM1 Channel 1 High & Low Registers */
+_VOLDATA _UINT8 __at 0x29 T1CH1H; /* TIM1 Channel 1 Register High */
+_VOLDATA _UINT8 __at 0x2A T1CH1L; /* TIM1 Channel 1 Register Low */
+
+/*------------------*/
+/* TIM 2 REGISTERS */
+/*------------------*/
+
+_VOLDATA _UINT8 __at 0x2B T2SC; /* TIM 2 Status and Control */
+ #define PS0_2 ((struct __hc08_bits *)(&T2SC))->bit0
+ #define PS1_2 ((struct __hc08_bits *)(&T2SC))->bit1
+ #define PS2_2 ((struct __hc08_bits *)(&T2SC))->bit2
+ #define TRST_2 ((struct __hc08_bits *)(&T2SC))->bit4
+ #define TSTOP_2 ((struct __hc08_bits *)(&T2SC))->bit5
+ #define TOIE_2 ((struct __hc08_bits *)(&T2SC))->bit6
+ #define TOF_2 ((struct __hc08_bits *)(&T2SC))->bit7
+
+_VOLDATA _UINT16 __at 0x2C T2CNT; /* TIM2 Counter High & Low Registers */
+_VOLDATA _UINT8 __at 0x2C T2CNTH; /* TIM2 Counter Register High */
+_VOLDATA _UINT8 __at 0x2D T2CNTL; /* TIM2 Counter Register Low */
+
+_VOLDATA _UINT16 __at 0x2E T2MOD; /* TIM2 Counter Modulo High & Low Registers */
+_VOLDATA _UINT8 __at 0x2E T2MODH; /* TIM2 Counter Modulo Register High */
+_VOLDATA _UINT8 __at 0x2F T2MODL; /* TIM2 Counter Modulo Register Low */
+
+_VOLDATA _UINT8 __at 0x30 T2SC0; /* TIM2 Channel 0 Status and Control Register */
+ #define CH0MAX_2 ((struct __hc08_bits *)(&T2SC0))->bit0
+ #define TOV0_2 ((struct __hc08_bits *)(&T2SC0))->bit1
+ #define ELS0A_2 ((struct __hc08_bits *)(&T2SC0))->bit2
+ #define ELS0B_2 ((struct __hc08_bits *)(&T2SC0))->bit3
+ #define MS0A_2 ((struct __hc08_bits *)(&T2SC0))->bit4
+ #define MS0B_2 ((struct __hc08_bits *)(&T2SC0))->bit5
+ #define CH0IE_2 ((struct __hc08_bits *)(&T2SC0))->bit6
+ #define CH0F_2 ((struct __hc08_bits *)(&T2SC0))->bit7
+
+_VOLDATA _UINT16 __at 0x31 T2CH0; /* TIM2 Channel 0 High & Low Registers */
+_VOLDATA _UINT8 __at 0x31 T2CH0H; /* TIM2 Channel 0 Register High */
+_VOLDATA _UINT8 __at 0x32 T2CH0L; /* TIM2 Channel 0 Register Low */
+
+_VOLDATA _UINT8 __at 0x33 T2SC1; /* TIM2 Channel 1 Status and Control Register */
+ #define CH1MAX_2 ((struct __hc08_bits *)(&T2SC1))->bit0
+ #define TOV1_2 ((struct __hc08_bits *)(&T2SC1))->bit1
+ #define ELS1A_2 ((struct __hc08_bits *)(&T2SC1))->bit2
+ #define ELS1B_2 ((struct __hc08_bits *)(&T2SC1))->bit3
+ #define MS1A_2 ((struct __hc08_bits *)(&T2SC1))->bit4
+ #define CH1IE_2 ((struct __hc08_bits *)(&T2SC1))->bit6
+ #define CH1F_2 ((struct __hc08_bits *)(&T2SC1))->bit7
+
+_VOLDATA _UINT16 __at 0x34 T2CH1; /* TIM2 Channel 1 High & Low Registers */
+_VOLDATA _UINT8 __at 0x34 T2CH1H; /* TIM2 Channel 1 Register High */
+_VOLDATA _UINT8 __at 0x35 T2CH1L; /* TIM2 Channel 1 Register Low */
+
+_VOLDATA _UINT8 __at 0x36 PCTL; /* PLL Control Register */
+ #define PLLIE ((struct __hc08_bits *)(&PCTL))->bit7
+ #define PLLF ((struct __hc08_bits *)(&PCTL))->bit6
+ #define PLLON ((struct __hc08_bits *)(&PCTL))->bit5
+ #define BCS ((struct __hc08_bits *)(&PCTL))->bit4
+ #define PRE1 ((struct __hc08_bits *)(&PCTL))->bit3
+ #define PRE0 ((struct __hc08_bits *)(&PCTL))->bit2
+ #define VPR1 ((struct __hc08_bits *)(&PCTL))->bit1
+ #define VPR0 ((struct __hc08_bits *)(&PCTL))->bit0
+
+_VOLDATA _UINT8 __at 0x37 PBWC; /* PLL Bandwidth Control Register */
+ #define AUTO ((struct __hc08_bits *)(&PBWC))->bit7
+ #define LOCK ((struct __hc08_bits *)(&PBWC))->bit6
+ #define ACQ ((struct __hc08_bits *)(&PBWC))->bit5
+ /* Bits 1-4, Unimplemented */
+ /* Bit 0, Reserved */
+
+_VOLDATA _UINT8 __at 0x38 PMSH; /* PLL Multiplier Select High */
+ #define MUL11 ((struct __hc08_bits *)(&PMSH))->bit3
+ #define MUL10 ((struct __hc08_bits *)(&PMSH))->bit2
+ #define MUL9 ((struct __hc08_bits *)(&PMSH))->bit1
+ #define MUL8 ((struct __hc08_bits *)(&PMSH))->bit0
+ /* Bits 4-7 unimplemented */
+
+_VOLDATA _UINT8 __at 0x39 PMSL; /* PLL Multiplir Select Low */
+ #define MUL7 ((struct __hc08_bits *)(&PMSL))->bit7
+ #define MUL6 ((struct __hc08_bits *)(&PMSL))->bit6
+ #define MUL5 ((struct __hc08_bits *)(&PMSL))->bit5
+ #define MUL4 ((struct __hc08_bits *)(&PMSL))->bit4
+ #define MUL3 ((struct __hc08_bits *)(&PMSL))->bit3
+ #define MUL2 ((struct __hc08_bits *)(&PMSL))->bit2
+ #define MUL1 ((struct __hc08_bits *)(&PMSL))->bit1
+ #define MUL0 ((struct __hc08_bits *)(&PMSL))->bit0
+
+_VOLDATA _UINT8 __at 0x3a PMRS; /* PLL VCO Select Range */
+ #define VRS7 ((struct __hc08_bits *)(&PMRS))->bit7
+ #define VRS6 ((struct __hc08_bits *)(&PMRS))->bit6
+ #define VRS5 ((struct __hc08_bits *)(&PMRS))->bit5
+ #define VRS4 ((struct __hc08_bits *)(&PMRS))->bit4
+ #define VRS3 ((struct __hc08_bits *)(&PMRS))->bit3
+ #define VRS2 ((struct __hc08_bits *)(&PMRS))->bit2
+ #define VRS1 ((struct __hc08_bits *)(&PMRS))->bit1
+ #define VRS0 ((struct __hc08_bits *)(&PMRS))->bit0
+
+_VOLDATA _UINT8 __at 0x3b PMDS; /* PLL Reference Divider Select Register */
+ #define RDS3 ((struct __hc08_bits *)(&PMDS))->bit3
+ #define RDS2 ((struct __hc08_bits *)(&PMDS))->bit2
+ #define RDS1 ((struct __hc08_bits *)(&PMDS))->bit1
+ #define RDS0 ((struct __hc08_bits *)(&PMDS))->bit0
+ /* Bits 4-7 unimplemented */
+
+_VOLDATA _UINT8 __at 0x3c ADSCR; /* Analog-to-Digital Status and Control Reg. */
+ #define COCO ((struct __hc08_bits *)(&ADSCR))->bit7
+ #define AIEN ((struct __hc08_bits *)(&ADSCR))->bit6
+ #define ADCO ((struct __hc08_bits *)(&ADSCR))->bit5
+ #define ADCH4 ((struct __hc08_bits *)(&ADSCR))->bit4
+ #define ADCH3 ((struct __hc08_bits *)(&ADSCR))->bit3
+ #define ADCH2 ((struct __hc08_bits *)(&ADSCR))->bit2
+ #define ADCH1 ((struct __hc08_bits *)(&ADSCR))->bit1
+ #define ADCH0 ((struct __hc08_bits *)(&ADSCR))->bit0
+
+_VOLDATA _UINT8 __at 0x3d ADR; /* Analog-to-Digital Data Register */
+
+_VOLDATA _UINT8 __at 0x3e ADCLK; /* Analog-to-Digital Clock */
+ #define ADIV2 ((struct __hc08_bits *)(&ADCLK))->bit7
+ #define ADIV1 ((struct __hc08_bits *)(&ADCLK))->bit6
+ #define ADIV0 ((struct __hc08_bits *)(&ADCLK))->bit5
+ #define ADICLK ((struct __hc08_bits *)(&ADCLK))->bit4
+ /* Bits 0-3 unimplemented */
+
+_VOLXDATA _UINT8 __at 0xfe00 SBSR; /* SIM Break Status Register */
+ #define SBSW ((struct __hc08_bits *)(&SBSR))->bit1
+
+_VOLXDATA _UINT8 __at 0xfe01 SRSR; /* SIM Reset Status Register */
+ #define LVI ((struct __hc08_bits *)(&SRSR))->bit1
+ #define MODRST ((struct __hc08_bits *)(&SRSR))->bit2
+ #define ILAD ((struct __hc08_bits *)(&SRSR))->bit3
+ #define ILOP ((struct __hc08_bits *)(&SRSR))->bit4
+ #define COP ((struct __hc08_bits *)(&SRSR))->bit5
+ #define PIN ((struct __hc08_bits *)(&SRSR))->bit6
+ #define POR ((struct __hc08_bits *)(&SRSR))->bit7
+ /* Bit 0 unimplemented */
+
+_VOLXDATA _UINT8 __at 0xfe02 SUBAR; /* SIM Upper Byte Address */
+
+_VOLXDATA _UINT8 __at 0xfe03 SBFCR; /* SIM Break Flag Control Register */
+ #define BFCE ((struct __hc08_bits *)(&BFCR))->bit7
+
+_VOLXDATA _UINT8 __at 0xfe04 INT1; /* Interrupt Status Register 1 */
+ #define IF1 ((struct __hc08_bits *)(&INT1))->bit2
+ #define IF2 ((struct __hc08_bits *)(&INT1))->bit3
+ #define IF3 ((struct __hc08_bits *)(&INT1))->bit4
+ #define IF4 ((struct __hc08_bits *)(&INT1))->bit5
+ #define IF5 ((struct __hc08_bits *)(&INT1))->bit6
+ #define IF6 ((struct __hc08_bits *)(&INT1))->bit7
+ /* Bits 0-1 Reserved */
+
+_VOLXDATA _UINT8 __at 0xfe05 INT2; /* Interrupt Status Register 2 */
+ #define IF14 ((struct __hc08_bits *)(&INT2))->bit7
+ #define IF13 ((struct __hc08_bits *)(&INT2))->bit6
+ #define IF12 ((struct __hc08_bits *)(&INT2))->bit5
+ #define IF11 ((struct __hc08_bits *)(&INT2))->bit4
+ #define IF10 ((struct __hc08_bits *)(&INT2))->bit3
+ #define IF9 ((struct __hc08_bits *)(&INT2))->bit2
+ #define IF8 ((struct __hc08_bits *)(&INT2))->bit1
+ #define IF7 ((struct __hc08_bits *)(&INT2))->bit0
+
+_VOLXDATA _UINT8 __at 0xfe06 INT3; /* Interrupt Status Register 3 */
+ #define IF16 ((struct __hc08_bits *)(&INT3))->bit1
+ #define IF15 ((struct __hc08_bits *)(&INT3))->bit0
+
+_VOLXDATA _UINT8 __at 0xfe07 FLCTR; /* Flash test/programming */
+
+_VOLXDATA _UINT8 __at 0xfe08 FLCR; /* FLASH Control Register */
+ #define PGM ((struct __hc08_bits *)(&FLCR))->bit0
+ #define ERASE ((struct __hc08_bits *)(&FLCR))->bit1
+ #define MASS ((struct __hc08_bits *)(&FLCR))->bit2
+ #define HVEN ((struct __hc08_bits *)(&FLCR))->bit3
+
+_VOLXDATA _UINT16 __at 0xfe09 BRK; /* Break Address High & Low Registers */
+_VOLXDATA _UINT8 __at 0xfe09 BRKH; /* Break Address High Register */
+_VOLXDATA _UINT8 __at 0xfe0a BRKL; /* Break Address Low Register */
+
+_VOLXDATA _UINT8 __at 0xfe0b BRKSCR; /* Break Status and Control Register */
+ #define BRKA ((struct __hc08_bits *)(&BRKSCR))->bit6
+ #define BRKE ((struct __hc08_bits *)(&BRKSCR))->bit7
+
+_VOLXDATA _UINT8 __at 0xfe0c LVISR; /* Low voltage detect */
+ #define LVIOUT ((struct __hc08_bits *)(&LVISR))->bit7
+
+
+_VOLXDATA _UINT8 __at 0xfe7e FLBPR; /* FLASH Block Protect Register */
+ #define BPR0 ((struct __hc08_bits *)(&FLBPR))->bit0
+ #define BPR1 ((struct __hc08_bits *)(&FLBPR))->bit1
+ #define BPR2 ((struct __hc08_bits *)(&FLBPR))->bit2
+ #define BPR3 ((struct __hc08_bits *)(&FLBPR))->bit3
+ #define BPR4 ((struct __hc08_bits *)(&FLBPR))->bit4
+ #define BPR5 ((struct __hc08_bits *)(&FLBPR))->bit5
+ #define BPR6 ((struct __hc08_bits *)(&FLBPR))->bit6
+ #define BPR7 ((struct __hc08_bits *)(&FLBPR))->bit7
+
+_VOLXDATA _UINT8 __at 0xffff COPCTL; /* COP Control Register */
+
+#endif
--- /dev/null
+/*-------------------------------------------------------------------------
+ Register Declarations for Motorola MC68HC908JB8
+
+ Copyright (c) 2004, Bjorn Bringert <bjorn@bringert.net>
+
+ Based on mc68hc908qy.h,
+ Written By - Erik Petrich
+ epetrich@users.sourceforge.net (2003)
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2, or (__at your option) any
+ later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+ In other words, you are welcome to use, share and improve this program.
+ You are forbidden to forbid anyone else to use, share and improve
+ what you give them. Help stamp out software-hoarding!
+-------------------------------------------------------------------------*/
+
+#ifndef _MC68HC908JB8_H
+#define _MC68HC908JB8_H
+
+#ifndef _UINT8
+ #define _UINT8 unsigned char
+#endif
+#ifndef _UINT16
+ #define _UINT16 unsigned int
+#endif
+#ifndef _VOLDATA
+ #define _VOLDATA volatile __data
+#endif
+#ifndef _VOLXDATA
+ #define _VOLXDATA volatile __xdata
+#endif
+
+struct __hc08_bits
+{
+ unsigned int bit0:1;
+ unsigned int bit1:1;
+ unsigned int bit2:1;
+ unsigned int bit3:1;
+ unsigned int bit4:1;
+ unsigned int bit5:1;
+ unsigned int bit6:1;
+ unsigned int bit7:1;
+};
+
+
+_VOLDATA _UINT8 __at 0x00 PTA; /* Port A Data Register */
+ #define PTA0 ((struct __hc08_bits *)(&PTA))->bit0
+ #define PTA1 ((struct __hc08_bits *)(&PTA))->bit1
+ #define PTA2 ((struct __hc08_bits *)(&PTA))->bit2
+ #define PTA3 ((struct __hc08_bits *)(&PTA))->bit3
+ #define PTA4 ((struct __hc08_bits *)(&PTA))->bit4
+ #define PTA5 ((struct __hc08_bits *)(&PTA))->bit5
+ #define AWUL ((struct __hc08_bits *)(&PTA))->bit6
+
+_VOLDATA _UINT8 __at 0x01 PTB; /* Port B Data Register */
+ #define PTB0 ((struct __hc08_bits *)(&PTB))->bit0
+ #define PTB1 ((struct __hc08_bits *)(&PTB))->bit1
+ #define PTB2 ((struct __hc08_bits *)(&PTB))->bit2
+ #define PTB3 ((struct __hc08_bits *)(&PTB))->bit3
+ #define PTB4 ((struct __hc08_bits *)(&PTB))->bit4
+ #define PTB5 ((struct __hc08_bits *)(&PTB))->bit5
+ #define PTB6 ((struct __hc08_bits *)(&PTB))->bit6
+ #define PTB7 ((struct __hc08_bits *)(&PTB))->bit7
+
+_VOLDATA _UINT8 __at 0x02 PTC; /* Port C Data Register */
+ #define PTC0 ((struct __hc08_bits *)(&PTC))->bit0
+ #define PTC1 ((struct __hc08_bits *)(&PTC))->bit1
+ #define PTC2 ((struct __hc08_bits *)(&PTC))->bit2
+ #define PTC3 ((struct __hc08_bits *)(&PTC))->bit3
+ #define PTC4 ((struct __hc08_bits *)(&PTC))->bit4
+ #define PTC5 ((struct __hc08_bits *)(&PTC))->bit5
+ #define PTC6 ((struct __hc08_bits *)(&PTC))->bit6
+ #define PTC7 ((struct __hc08_bits *)(&PTC))->bit7
+
+_VOLDATA _UINT8 __at 0x03 PTD; /* Port D Data Register */
+ #define PTD0 ((struct __hc08_bits *)(&PTD))->bit0
+ #define PTD1 ((struct __hc08_bits *)(&PTD))->bit1
+ #define PTD2 ((struct __hc08_bits *)(&PTD))->bit2
+ #define PTD3 ((struct __hc08_bits *)(&PTD))->bit3
+ #define PTD4 ((struct __hc08_bits *)(&PTD))->bit4
+ #define PTD5 ((struct __hc08_bits *)(&PTD))->bit5
+ #define PTD6 ((struct __hc08_bits *)(&PTD))->bit6
+ #define PTD7 ((struct __hc08_bits *)(&PTD))->bit7
+
+_VOLDATA _UINT8 __at 0x04 DDRA; /* Data Direction Register A */
+ #define DDRA0 ((struct __hc08_bits *)(&DDRA))->bit0
+ #define DDRA1 ((struct __hc08_bits *)(&DDRA))->bit1
+ #define DDRA2 ((struct __hc08_bits *)(&DDRA))->bit2
+ #define DDRA3 ((struct __hc08_bits *)(&DDRA))->bit3
+ #define DDRA4 ((struct __hc08_bits *)(&DDRA))->bit4
+ #define DDRA5 ((struct __hc08_bits *)(&DDRA))->bit5
+ #define DDRA6 ((struct __hc08_bits *)(&DDRA))->bit6
+ #define DDRA7 ((struct __hc08_bits *)(&DDRA))->bit7
+
+_VOLDATA _UINT8 __at 0x05 DDRB; /* Data Direction Register B */
+ #define DDRB0 ((struct __hc08_bits *)(&DDRB))->bit0
+ #define DDRB1 ((struct __hc08_bits *)(&DDRB))->bit1
+ #define DDRB2 ((struct __hc08_bits *)(&DDRB))->bit2
+ #define DDRB3 ((struct __hc08_bits *)(&DDRB))->bit3
+ #define DDRB4 ((struct __hc08_bits *)(&DDRB))->bit4
+ #define DDRB5 ((struct __hc08_bits *)(&DDRB))->bit5
+ #define DDRB6 ((struct __hc08_bits *)(&DDRB))->bit6
+ #define DDRB7 ((struct __hc08_bits *)(&DDRB))->bit7
+
+_VOLDATA _UINT8 __at 0x06 DDRC; /* Data Direction Register C */
+ #define DDRC0 ((struct __hc08_bits *)(&DDRC))->bit0
+ #define DDRC1 ((struct __hc08_bits *)(&DDRC))->bit1
+ #define DDRC2 ((struct __hc08_bits *)(&DDRC))->bit2
+ #define DDRC3 ((struct __hc08_bits *)(&DDRC))->bit3
+ #define DDRC4 ((struct __hc08_bits *)(&DDRC))->bit4
+ #define DDRC5 ((struct __hc08_bits *)(&DDRC))->bit5
+ #define DDRC6 ((struct __hc08_bits *)(&DDRC))->bit6
+ #define DDRC7 ((struct __hc08_bits *)(&DDRC))->bit7
+
+_VOLDATA _UINT8 __at 0x07 DDRD; /* Data Direction Register D */
+ #define DDRD0 ((struct __hc08_bits *)(&DDRD))->bit0
+ #define DDRD1 ((struct __hc08_bits *)(&DDRD))->bit1
+ #define DDRD2 ((struct __hc08_bits *)(&DDRD))->bit2
+ #define DDRD3 ((struct __hc08_bits *)(&DDRD))->bit3
+ #define DDRD4 ((struct __hc08_bits *)(&DDRD))->bit4
+ #define DDRD5 ((struct __hc08_bits *)(&DDRD))->bit5
+ #define DDRD6 ((struct __hc08_bits *)(&DDRD))->bit6
+ #define DDRD7 ((struct __hc08_bits *)(&DDRD))->bit7
+
+_VOLDATA _UINT8 __at 0x08 PTE; /* Port E Data Register */
+ #define PTE0 ((struct __hc08_bits *)(&PTE))->bit0
+ #define PTE1 ((struct __hc08_bits *)(&PTE))->bit1
+ #define PTE2 ((struct __hc08_bits *)(&PTE))->bit2
+ #define PTE3 ((struct __hc08_bits *)(&PTE))->bit3
+ #define PTE4 ((struct __hc08_bits *)(&PTE))->bit4
+ #define PTE5 ((struct __hc08_bits *)(&PTE))->bit5
+ #define PTE6 ((struct __hc08_bits *)(&PTE))->bit6
+ #define PTE7 ((struct __hc08_bits *)(&PTE))->bit7
+
+_VOLDATA _UINT8 __at 0x09 DDRE; /* Data Direction Register E */
+ #define DDRE0 ((struct __hc08_bits *)(&DDRE))->bit0
+ #define DDRE1 ((struct __hc08_bits *)(&DDRE))->bit1
+ #define DDRE2 ((struct __hc08_bits *)(&DDRE))->bit2
+ #define DDRE3 ((struct __hc08_bits *)(&DDRE))->bit3
+ #define DDRE4 ((struct __hc08_bits *)(&DDRE))->bit4
+ #define DDRE5 ((struct __hc08_bits *)(&DDRE))->bit5
+ #define DDRE6 ((struct __hc08_bits *)(&DDRE))->bit6
+ #define DDRE7 ((struct __hc08_bits *)(&DDRE))->bit7
+
+_VOLDATA _UINT8 __at 0x0a TSC; /* TIM Status and Control */
+ #define PS0 ((struct __hc08_bits *)(&TSC))->bit0
+ #define PS1 ((struct __hc08_bits *)(&TSC))->bit1
+ #define PS2 ((struct __hc08_bits *)(&TSC))->bit2
+ #define TRST ((struct __hc08_bits *)(&TSC))->bit4
+ #define TSTOP ((struct __hc08_bits *)(&TSC))->bit5
+ #define TOIE ((struct __hc08_bits *)(&TSC))->bit6
+ #define TOF ((struct __hc08_bits *)(&TSC))->bit7
+
+_VOLDATA _UINT16 __at 0x0c TCNT; /* TIM Counter High & Low Registers */
+_VOLDATA _UINT8 __at 0x0c TCNTH; /* TIM Counter Register High */
+_VOLDATA _UINT8 __at 0x0d TCNTL; /* TIM Counter Register Low */
+
+_VOLDATA _UINT16 __at 0x0e TMOD; /* TIM Counter Modulo High & Low Registers */
+_VOLDATA _UINT8 __at 0x0e TMODH; /* TIM Counter Modulo Register High */
+_VOLDATA _UINT8 __at 0x0f TMODL; /* TIM Counter Modulo Register Low */
+
+_VOLDATA _UINT8 __at 0x10 TSC0; /* TIM Channel 0 Status and Control Register */
+ #define CH0MAX ((struct __hc08_bits *)(&TSC0))->bit0
+ #define TOV0 ((struct __hc08_bits *)(&TSC0))->bit1
+ #define ELS0A ((struct __hc08_bits *)(&TSC0))->bit2
+ #define ELS0B ((struct __hc08_bits *)(&TSC0))->bit3
+ #define MS0A ((struct __hc08_bits *)(&TSC0))->bit4
+ #define MS0B ((struct __hc08_bits *)(&TSC0))->bit5
+ #define CH0IE ((struct __hc08_bits *)(&TSC0))->bit6
+ #define CH0F ((struct __hc08_bits *)(&TSC0))->bit7
+
+_VOLDATA _UINT16 __at 0x11 TCH0; /* TIM Channel 0 High & Low Registers */
+_VOLDATA _UINT8 __at 0x11 TCH0H; /* TIM Channel 0 Register High */
+_VOLDATA _UINT8 __at 0x12 TCH0L; /* TIM Channel 0 Register Low */
+
+_VOLDATA _UINT8 __at 0x13 TSC1; /* TIM Channel 1 Status and Control Register */
+ #define CH1MAX ((struct __hc08_bits *)(&TSC1))->bit0
+ #define TOV1 ((struct __hc08_bits *)(&TSC1))->bit1
+ #define ELS1A ((struct __hc08_bits *)(&TSC1))->bit2
+ #define ELS1B ((struct __hc08_bits *)(&TSC1))->bit3
+ #define MS1A ((struct __hc08_bits *)(&TSC1))->bit4
+ #define CH1IE ((struct __hc08_bits *)(&TSC1))->bit6
+ #define CH1F ((struct __hc08_bits *)(&TSC1))->bit7
+
+_VOLDATA _UINT16 __at 0x14 TCH1; /* TIM Channel 1 High & Low Registers */
+_VOLDATA _UINT8 __at 0x14 TCH1H; /* TIM Channel 1 Register High */
+_VOLDATA _UINT8 __at 0x15 TCH1L; /* TIM Channel 1 Register Low */
+
+_VOLDATA _UINT8 __at 0x16 KBSCR; /* Keyboard Status and Control Register */
+ #define MODEK ((struct __hc08_bits *)(&KBSCR))->bit0
+ #define IMASKK ((struct __hc08_bits *)(&KBSCR))->bit1
+ #define ACKK ((struct __hc08_bits *)(&KBSCR))->bit2
+ #define KEYF ((struct __hc08_bits *)(&KBSCR))->bit3
+
+_VOLDATA _UINT8 __at 0x17 KBIER; /* Keyboard Interrupt Enable Register */
+ #define KBIE0 ((struct __hc08_bits *)(&KBIER))->bit0
+ #define KBIE1 ((struct __hc08_bits *)(&KBIER))->bit1
+ #define KBIE2 ((struct __hc08_bits *)(&KBIER))->bit2
+ #define KBIE3 ((struct __hc08_bits *)(&KBIER))->bit3
+ #define KBIE4 ((struct __hc08_bits *)(&KBIER))->bit4
+ #define KBIE5 ((struct __hc08_bits *)(&KBIER))->bit5
+ #define KBIE6 ((struct __hc08_bits *)(&KBIER))->bit6
+ #define KBIE7 ((struct __hc08_bits *)(&KBIER))->bit7
+
+_VOLDATA _UINT8 __at 0x18 UIR2; /* USB Interrupt Register 2 */
+ #define RXD0FR ((struct __hc08_bits *)(&UIR2))->bit0
+ #define TXD0FR ((struct __hc08_bits *)(&UIR2))->bit1
+ #define RESUMFR ((struct __hc08_bits *)(&UIR2))->bit2
+ #define TXD1FR ((struct __hc08_bits *)(&UIR2))->bit3
+ #define RXD2FR ((struct __hc08_bits *)(&UIR2))->bit4
+ #define TXD2FR ((struct __hc08_bits *)(&UIR2))->bit5
+ #define RSTFR ((struct __hc08_bits *)(&UIR2))->bit6
+ #define EOPFR ((struct __hc08_bits *)(&UIR2))->bit7
+
+_VOLDATA _UINT8 __at 0x19 UCR2; /* USB Control Register 2 */
+ #define TP2SIZ0 ((struct __hc08_bits *)(&UCR2))->bit0
+ #define TP2SIZ1 ((struct __hc08_bits *)(&UCR2))->bit1
+ #define TP2SIZ2 ((struct __hc08_bits *)(&UCR2))->bit2
+ #define TP2SIZ3 ((struct __hc08_bits *)(&UCR2))->bit3
+ #define RX2E ((struct __hc08_bits *)(&UCR2))->bit4
+ #define TX2E ((struct __hc08_bits *)(&UCR2))->bit5
+ #define STALL2 ((struct __hc08_bits *)(&UCR2))->bit6
+ #define T2SEQ ((struct __hc08_bits *)(&UCR2))->bit7
+
+_VOLDATA _UINT8 __at 0x1a UCR3; /* USB Control Register 3 */
+ #define ENABLE1 ((struct __hc08_bits *)(&UCR3))->bit0
+ #define ENABLE2 ((struct __hc08_bits *)(&UCR3))->bit1
+ #define PULLEN ((struct __hc08_bits *)(&UCR3))->bit2
+ #define ISTALL0 ((struct __hc08_bits *)(&UCR3))->bit4
+ #define OSTALL0 ((struct __hc08_bits *)(&UCR3))->bit5
+ #define TX1STR ((struct __hc08_bits *)(&UCR3))->bit6
+ #define TX1ST ((struct __hc08_bits *)(&UCR3))->bit7
+
+_VOLDATA _UINT8 __at 0x1b UCR4; /* USB Control Register 4 */
+ #define FDM ((struct __hc08_bits *)(&UCR4))->bit0
+ #define FDP ((struct __hc08_bits *)(&UCR4))->bit1
+ #define FUSB0 ((struct __hc08_bits *)(&UCR4))->bit2
+
+_VOLDATA _UINT8 __at 0x1c IOCR; /* IRQ Option Control Register */
+ #define IRQPD ((struct __hc08_bits *)(&IOCR))->bit0
+ #define PTE4IE ((struct __hc08_bits *)(&IOCR))->bit1
+ #define PTE4IF ((struct __hc08_bits *)(&IOCR))->bit2
+
+_VOLDATA _UINT8 __at 0x1d POCR; /* Port Option Control Register */
+ #define PAP ((struct __hc08_bits *)(&POCR))->bit0
+ #define PBP ((struct __hc08_bits *)(&POCR))->bit1
+ #define PCP ((struct __hc08_bits *)(&POCR))->bit2
+ #define PTE3P ((struct __hc08_bits *)(&POCR))->bit3
+ #define PTE4P ((struct __hc08_bits *)(&POCR))->bit4
+ #define PTDILDD ((struct __hc08_bits *)(&POCR))->bit5
+ #define PTDLDD ((struct __hc08_bits *)(&POCR))->bit6
+ #define PTE20P ((struct __hc08_bits *)(&POCR))->bit7
+
+_VOLDATA _UINT8 __at 0x1e ISCR; /* IRQ Status and Control Register */
+ #define MODE ((struct __hc08_bits *)(&ISCR))->bit0
+ #define IMASK ((struct __hc08_bits *)(&ISCR))->bit1
+ #define ACK ((struct __hc08_bits *)(&ISCR))->bit2
+ #define IRQF ((struct __hc08_bits *)(&ISCR))->bit3
+
+_VOLDATA _UINT8 __at 0x1f CONFIG; /* Configuration Register 1 */
+/* CONFIG1 is one-time writeable, so can't use bitfields */
+
+_VOLDATA _UINT8 __at 0x20 UE0D0; /* USB Endpoint 0 Data Register 0 */
+_VOLDATA _UINT8 __at 0x21 UE0D1; /* USB Endpoint 0 Data Register 1 */
+_VOLDATA _UINT8 __at 0x22 UE0D2; /* USB Endpoint 0 Data Register 2 */
+_VOLDATA _UINT8 __at 0x23 UE0D3; /* USB Endpoint 0 Data Register 3 */
+_VOLDATA _UINT8 __at 0x24 UE0D4; /* USB Endpoint 0 Data Register 4 */
+_VOLDATA _UINT8 __at 0x25 UE0D5; /* USB Endpoint 0 Data Register 5 */
+_VOLDATA _UINT8 __at 0x26 UE0D6; /* USB Endpoint 0 Data Register 6 */
+_VOLDATA _UINT8 __at 0x27 UE0D7; /* USB Endpoint 0 Data Register 7 */
+
+_VOLDATA _UINT8 __at 0x28 UE1D0; /* USB Endpoint 1 Data Register 0 */
+_VOLDATA _UINT8 __at 0x29 UE1D1; /* USB Endpoint 1 Data Register 1 */
+_VOLDATA _UINT8 __at 0x2a UE1D2; /* USB Endpoint 1 Data Register 2 */
+_VOLDATA _UINT8 __at 0x2b UE1D3; /* USB Endpoint 1 Data Register 3 */
+_VOLDATA _UINT8 __at 0x2c UE1D4; /* USB Endpoint 1 Data Register 4 */
+_VOLDATA _UINT8 __at 0x2d UE1D5; /* USB Endpoint 1 Data Register 5 */
+_VOLDATA _UINT8 __at 0x2e UE1D6; /* USB Endpoint 1 Data Register 6 */
+_VOLDATA _UINT8 __at 0x2f UE1D7; /* USB Endpoint 1 Data Register 7 */
+
+_VOLDATA _UINT8 __at 0x30 UE2D0; /* USB Endpoint 2 Data Register 0 */
+_VOLDATA _UINT8 __at 0x31 UE2D1; /* USB Endpoint 2 Data Register 1 */
+_VOLDATA _UINT8 __at 0x32 UE2D2; /* USB Endpoint 2 Data Register 2 */
+_VOLDATA _UINT8 __at 0x33 UE2D3; /* USB Endpoint 2 Data Register 3 */
+_VOLDATA _UINT8 __at 0x34 UE2D4; /* USB Endpoint 2 Data Register 4 */
+_VOLDATA _UINT8 __at 0x35 UE2D5; /* USB Endpoint 2 Data Register 5 */
+_VOLDATA _UINT8 __at 0x36 UE2D6; /* USB Endpoint 2 Data Register 6 */
+_VOLDATA _UINT8 __at 0x37 UE2D7; /* USB Endpoint 2 Data Register 7 */
+
+_VOLDATA _UINT8 __at 0x38 UADDR; /* USB Address Register */
+ #define USBEN ((struct __hc08_bits *)(&UADDR))->bit7
+
+_VOLDATA _UINT8 __at 0x39 UIR0; /* USB Interrupt Register 0 */
+ #define RXD0IE ((struct __hc08_bits *)(&UIR0))->bit0
+ #define TXD0IE ((struct __hc08_bits *)(&UIR0))->bit1
+ #define TXD1IE ((struct __hc08_bits *)(&UIR0))->bit3
+ #define RXD2IE ((struct __hc08_bits *)(&UIR0))->bit4
+ #define TXD2IE ((struct __hc08_bits *)(&UIR0))->bit5
+ #define SUSPND ((struct __hc08_bits *)(&UIR0))->bit6
+ #define EOPIE ((struct __hc08_bits *)(&UIR0))->bit7
+
+_VOLDATA _UINT8 __at 0x3a UIR1; /* USB Interrupt Register 1 */
+ #define RXD0F ((struct __hc08_bits *)(&UIR1))->bit0
+ #define TXD0F ((struct __hc08_bits *)(&UIR1))->bit1
+ #define RESUMF ((struct __hc08_bits *)(&UIR1))->bit2
+ #define TXD1F ((struct __hc08_bits *)(&UIR1))->bit3
+ #define RXD2F ((struct __hc08_bits *)(&UIR1))->bit4
+ #define TXD2F ((struct __hc08_bits *)(&UIR1))->bit5
+ #define RSTF ((struct __hc08_bits *)(&UIR1))->bit6
+ #define EOPF ((struct __hc08_bits *)(&UIR1))->bit7
+
+_VOLDATA _UINT8 __at 0x3b UCR0; /* USB Control Register 0 */
+ #define TP0SIZ0 ((struct __hc08_bits *)(&UCR0))->bit0
+ #define TP0SIZ1 ((struct __hc08_bits *)(&UCR0))->bit1
+ #define TP0SIZ2 ((struct __hc08_bits *)(&UCR0))->bit2
+ #define TP0SIZ3 ((struct __hc08_bits *)(&UCR0))->bit3
+ #define RX0E ((struct __hc08_bits *)(&UCR0))->bit4
+ #define TX0E ((struct __hc08_bits *)(&UCR0))->bit5
+ #define T0SEQ ((struct __hc08_bits *)(&UCR0))->bit7
+
+_VOLDATA _UINT8 __at 0x3c UCR1; /* USB Control Register 1 */
+ #define TP1SIZ0 ((struct __hc08_bits *)(&UCR1))->bit0
+ #define TP1SIZ1 ((struct __hc08_bits *)(&UCR1))->bit1
+ #define TP1SIZ2 ((struct __hc08_bits *)(&UCR1))->bit2
+ #define TP1SIZ3 ((struct __hc08_bits *)(&UCR1))->bit3
+ #define FRESUM ((struct __hc08_bits *)(&UCR1))->bit4
+ #define TX1E ((struct __hc08_bits *)(&UCR1))->bit5
+ #define STALL1 ((struct __hc08_bits *)(&UCR1))->bit6
+ #define T1SEQ ((struct __hc08_bits *)(&UCR1))->bit7
+
+_VOLDATA _UINT8 __at 0x3d USR0; /* USB Status Register 0 */
+ #define RP0SIZ0 ((struct __hc08_bits *)(&USR0))->bit0
+ #define RP0SIZ1 ((struct __hc08_bits *)(&USR0))->bit1
+ #define RP0SIZ2 ((struct __hc08_bits *)(&USR0))->bit2
+ #define RP0SIZ3 ((struct __hc08_bits *)(&USR0))->bit3
+ #define SETUP ((struct __hc08_bits *)(&USR0))->bit6
+ #define R0SEQ ((struct __hc08_bits *)(&USR0))->bit7
+
+_VOLDATA _UINT8 __at 0x3e USR1; /* USB Status Register 1 */
+ #define RP2SIZ0 ((struct __hc08_bits *)(&USR1))->bit0
+ #define RP2SIZ1 ((struct __hc08_bits *)(&USR1))->bit1
+ #define RP2SIZ2 ((struct __hc08_bits *)(&USR1))->bit2
+ #define RP2SIZ3 ((struct __hc08_bits *)(&USR1))->bit3
+ #define TXSTL ((struct __hc08_bits *)(&USR1))->bit4
+ #define TXNAK ((struct __hc08_bits *)(&USR1))->bit5
+ #define TXACK ((struct __hc08_bits *)(&USR1))->bit6
+ #define R2SEQ ((struct __hc08_bits *)(&USR1))->bit7
+
+_VOLXDATA _UINT8 __at 0xfe00 BSR; /* Break Status Register */
+ #define SBSW ((struct __hc08_bits *)(&BSR))->bit1
+
+_VOLXDATA _UINT8 __at 0xfe01 RSR; /* Reset Status Register */
+ #define LVI ((struct __hc08_bits *)(&RSR))->bit1
+ #define USB ((struct __hc08_bits *)(&RSR))->bit2
+ #define ILAD ((struct __hc08_bits *)(&RSR))->bit3
+ #define ILOP ((struct __hc08_bits *)(&RSR))->bit4
+ #define COP ((struct __hc08_bits *)(&RSR))->bit5
+ #define PIN ((struct __hc08_bits *)(&RSR))->bit6
+ #define POR ((struct __hc08_bits *)(&RSR))->bit7
+
+_VOLXDATA _UINT8 __at 0xfe03 BFCR; /* Break Flag Control Register */
+ #define BFCE ((struct __hc08_bits *)(&BFCR))->bit7
+
+_VOLXDATA _UINT8 __at 0xfe04 INT1; /* Interrupt Status Register 1 */
+ #define IF1 ((struct __hc08_bits *)(&INT1))->bit2
+ #define IF2 ((struct __hc08_bits *)(&INT1))->bit3
+ #define IF3 ((struct __hc08_bits *)(&INT1))->bit4
+ #define IF4 ((struct __hc08_bits *)(&INT1))->bit5
+ #define IF5 ((struct __hc08_bits *)(&INT1))->bit6
+ #define IF6 ((struct __hc08_bits *)(&INT1))->bit7
+
+_VOLXDATA _UINT8 __at 0xfe08 FLCR; /* FLASH Control Register */
+ #define PGM ((struct __hc08_bits *)(&FLCR))->bit0
+ #define ERASE ((struct __hc08_bits *)(&FLCR))->bit1
+ #define MASS ((struct __hc08_bits *)(&FLCR))->bit2
+ #define HVEN ((struct __hc08_bits *)(&FLCR))->bit3
+
+_VOLXDATA _UINT8 __at 0xfe09 FLBPR; /* FLASH Block Protect Register */
+ #define BPR0 ((struct __hc08_bits *)(&FLBPR))->bit0
+ #define BPR1 ((struct __hc08_bits *)(&FLBPR))->bit1
+ #define BPR2 ((struct __hc08_bits *)(&FLBPR))->bit2
+ #define BPR3 ((struct __hc08_bits *)(&FLBPR))->bit3
+ #define BPR4 ((struct __hc08_bits *)(&FLBPR))->bit4
+ #define BPR5 ((struct __hc08_bits *)(&FLBPR))->bit5
+ #define BPR6 ((struct __hc08_bits *)(&FLBPR))->bit6
+ #define BPR7 ((struct __hc08_bits *)(&FLBPR))->bit7
+
+_VOLXDATA _UINT16 __at 0xfe0c BRK; /* Break Address High & Low Registers */
+_VOLXDATA _UINT8 __at 0xfe0c BRKH; /* Break Address High Register */
+_VOLXDATA _UINT8 __at 0xfe0d BRKL; /* Break Address Low Register */
+
+_VOLXDATA _UINT8 __at 0xfe0e BRKSCR; /* Break Status and Control Register */
+ #define BRKA ((struct __hc08_bits *)(&BRKSCR))->bit6
+ #define BRKE ((struct __hc08_bits *)(&BRKSCR))->bit7
+
+_VOLXDATA _UINT8 __at 0xffff COPCTL; /* COP Control Register */
+
+#endif
+
--- /dev/null
+/*-------------------------------------------------------------------------
+ Register Declarations for Motorola MC68HC908JK1/JK3/JL3/JK8/JL8
+
+ Copyright (c) 2004, Lucas Loizaga <lucas.loizaga@ingenieria-inversa.com.ar>
+
+ Based on mc68hc908qy.h,
+ Written By - Erik Petrich
+ epetrich@users.sourceforge.net (2003)
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2, or (__at your option) any
+ later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+ In other words, you are welcome to use, share and improve this program.
+ You are forbidden to forbid anyone else to use, share and improve
+ what you give them. Help stamp out software-hoarding!
+-------------------------------------------------------------------------*/
+
+#ifndef _MC68HC908JKJL_H
+#define _MC68HC908JKJL_H
+
+#ifndef _UINT8
+ #define _UINT8 unsigned char
+#endif
+#ifndef _UINT16
+ #define _UINT16 unsigned int
+#endif
+#ifndef _VOLDATA
+ #define _VOLDATA volatile __data
+#endif
+#ifndef _VOLXDATA
+ #define _VOLXDATA volatile __xdata
+#endif
+
+struct __hc08_bits
+{
+ unsigned int bit0:1;
+ unsigned int bit1:1;
+ unsigned int bit2:1;
+ unsigned int bit3:1;
+ unsigned int bit4:1;
+ unsigned int bit5:1;
+ unsigned int bit6:1;
+ unsigned int bit7:1;
+};
+
+
+_VOLDATA _UINT8 __at 0x00 PTA; /* Port A Data Register */
+#define PORTA PTA /* Alias for PTA */
+ #define PTA0 ((struct __hc08_bits *)(&PTA))->bit0
+ #define PTA1 ((struct __hc08_bits *)(&PTA))->bit1
+ #define PTA2 ((struct __hc08_bits *)(&PTA))->bit2
+ #define PTA3 ((struct __hc08_bits *)(&PTA))->bit3
+ #define PTA4 ((struct __hc08_bits *)(&PTA))->bit4
+ #define PTA5 ((struct __hc08_bits *)(&PTA))->bit5
+ #define PTA6 ((struct __hc08_bits *)(&PTA))->bit6
+ #define PTA7 ((struct __hc08_bits *)(&PTA))->bit7
+
+_VOLDATA _UINT8 __at 0x01 PTB; /* Port B Data Register */
+#define PORTB PTB /* Alias for PTB */
+ #define PTB0 ((struct __hc08_bits *)(&PTB))->bit0
+ #define PTB1 ((struct __hc08_bits *)(&PTB))->bit1
+ #define PTB2 ((struct __hc08_bits *)(&PTB))->bit2
+ #define PTB3 ((struct __hc08_bits *)(&PTB))->bit3
+ #define PTB4 ((struct __hc08_bits *)(&PTB))->bit4
+ #define PTB5 ((struct __hc08_bits *)(&PTB))->bit5
+ #define PTB6 ((struct __hc08_bits *)(&PTB))->bit6
+ #define PTB7 ((struct __hc08_bits *)(&PTB))->bit7
+
+_VOLDATA _UINT8 __at 0x03 PTD; /* Port D Data Register */
+#define PORTD PTD /* Alias for PTD */
+ #define PTD0 ((struct __hc08_bits *)(&PTD))->bit0
+ #define PTD1 ((struct __hc08_bits *)(&PTD))->bit1
+ #define PTD2 ((struct __hc08_bits *)(&PTD))->bit2
+ #define PTD3 ((struct __hc08_bits *)(&PTD))->bit3
+ #define PTD4 ((struct __hc08_bits *)(&PTD))->bit4
+ #define PTD5 ((struct __hc08_bits *)(&PTD))->bit5
+ #define PTD6 ((struct __hc08_bits *)(&PTD))->bit6
+ #define PTD7 ((struct __hc08_bits *)(&PTD))->bit7
+
+_VOLDATA _UINT8 __at 0x04 DDRA; /* Data Direction Register A */
+ #define DDRA0 ((struct __hc08_bits *)(&DDRA))->bit0
+ #define DDRA1 ((struct __hc08_bits *)(&DDRA))->bit1
+ #define DDRA2 ((struct __hc08_bits *)(&DDRA))->bit2
+ #define DDRA3 ((struct __hc08_bits *)(&DDRA))->bit3
+ #define DDRA4 ((struct __hc08_bits *)(&DDRA))->bit4
+ #define DDRA5 ((struct __hc08_bits *)(&DDRA))->bit5
+ #define DDRA6 ((struct __hc08_bits *)(&DDRA))->bit6
+ #define DDRA7 ((struct __hc08_bits *)(&DDRA))->bit7
+
+_VOLDATA _UINT8 __at 0x05 DDRB; /* Data Direction Register B */
+ #define DDRB0 ((struct __hc08_bits *)(&DDRB))->bit0
+ #define DDRB1 ((struct __hc08_bits *)(&DDRB))->bit1
+ #define DDRB2 ((struct __hc08_bits *)(&DDRB))->bit2
+ #define DDRB3 ((struct __hc08_bits *)(&DDRB))->bit3
+ #define DDRB4 ((struct __hc08_bits *)(&DDRB))->bit4
+ #define DDRB5 ((struct __hc08_bits *)(&DDRB))->bit5
+ #define DDRB6 ((struct __hc08_bits *)(&DDRB))->bit6
+ #define DDRB7 ((struct __hc08_bits *)(&DDRB))->bit7
+
+_VOLDATA _UINT8 __at 0x07 DDRD; /* Data Direction Register D */
+ #define DDRD0 ((struct __hc08_bits *)(&DDRD))->bit0
+ #define DDRD1 ((struct __hc08_bits *)(&DDRD))->bit1
+ #define DDRD2 ((struct __hc08_bits *)(&DDRD))->bit2
+ #define DDRD3 ((struct __hc08_bits *)(&DDRD))->bit3
+ #define DDRD4 ((struct __hc08_bits *)(&DDRD))->bit4
+ #define DDRD5 ((struct __hc08_bits *)(&DDRD))->bit5
+ #define DDRD6 ((struct __hc08_bits *)(&DDRD))->bit6
+ #define DDRD7 ((struct __hc08_bits *)(&DDRD))->bit7
+
+_VOLDATA _UINT8 __at 0x08 PTE; /* Port E Data Register */
+#define PORTE PTE /* Alias for PTE */
+ #define PTE0 ((struct __hc08_bits *)(&PTE))->bit0
+ #define PTE1 ((struct __hc08_bits *)(&PTE))->bit1
+
+
+_VOLDATA _UINT8 __at 0x0A PTE; /* Port D Control Register */
+#define PORTE PTE /* Alias for PDCR */
+ #define PTDPU6 ((struct __hc08_bits *)(&PTE))->bit0
+ #define PTDPU7 ((struct __hc08_bits *)(&PTE))->bit1
+ #define SLOWD6 ((struct __hc08_bits *)(&PTE))->bit2
+ #define SLOWD7 ((struct __hc08_bits *)(&PTE))->bit3
+
+_VOLDATA _UINT8 __at 0x0C DDRE; /* Data Direction Register E */
+ #define DDRE0 ((struct __hc08_bits *)(&DDRE))->bit0
+ #define DDRE1 ((struct __hc08_bits *)(&DDRE))->bit1
+
+
+_VOLDATA _UINT8 __at 0x0D PTAPUE; /* Port A pull-up enables */
+ #define PTAPUE0 ((struct __hc08_bits *)(&PTAPUE))->bit0
+ #define PTAPUE1 ((struct __hc08_bits *)(&PTAPUE))->bit1
+ #define PTAPUE2 ((struct __hc08_bits *)(&PTAPUE))->bit2
+ #define PTAPUE3 ((struct __hc08_bits *)(&PTAPUE))->bit3
+ #define PTAPUE4 ((struct __hc08_bits *)(&PTAPUE))->bit4
+ #define PTAPUE5 ((struct __hc08_bits *)(&PTAPUE))->bit5
+ #define PTAPUE6 ((struct __hc08_bits *)(&PTAPUE))->bit6
+ #define PTA6EN ((struct __hc08_bits *)(&PTAPUE))->bit7
+
+_VOLDATA _UINT8 __at 0x0E PTA7PUE; /* Port A pull-up enables */
+ #define PTAPUE7 ((struct __hc08_bits *)(&PTA7PUE))->bit7
+
+_VOLDATA _UINT8 __at 0x13 SCC1; /* SCI Control Register 1 */
+ #define LOOPS ((struct __hc08_bits *)(&SCC1))->bit7
+ #define ENSCI ((struct __hc08_bits *)(&SCC1))->bit6
+ #define TXINV ((struct __hc08_bits *)(&SCC1))->bit5
+ #define M ((struct __hc08_bits *)(&SCC1))->bit4
+ #define WAKE ((struct __hc08_bits *)(&SCC1))->bit3
+ #define ILTY ((struct __hc08_bits *)(&SCC1))->bit2
+ #define PEN ((struct __hc08_bits *)(&SCC1))->bit1
+ #define PTY ((struct __hc08_bits *)(&SCC1))->bit0
+
+
+_VOLDATA _UINT8 __at 0x14 SCC2; /* SCI Control Register 2 */
+ #define SCTIE ((struct __hc08_bits *)(&SCC2))->bit7
+ #define TCIE ((struct __hc08_bits *)(&SCC2))->bit6
+ #define SCRIE ((struct __hc08_bits *)(&SCC2))->bit5
+ #define ILIE ((struct __hc08_bits *)(&SCC2))->bit4
+ #define TE ((struct __hc08_bits *)(&SCC2))->bit3
+ #define RE ((struct __hc08_bits *)(&SCC2))->bit2
+ #define WRU ((struct __hc08_bits *)(&SCC2))->bit1
+ #define SBK ((struct __hc08_bits *)(&SCC2))->bit0
+
+_VOLDATA _UINT8 __at 0x15 SCC3; /* SCI Control Register 3 */
+ #define SCC3_R8 ((struct __hc08_bits *)(&SCC3))->bit7
+ #define SCC3_TB ((struct __hc08_bits *)(&SCC3))->bit6
+ #define DMARE ((struct __hc08_bits *)(&SCC3))->bit5
+ #define DMATE ((struct __hc08_bits *)(&SCC3))->bit4
+ #define ORIE ((struct __hc08_bits *)(&SCC3))->bit3
+ #define NEIE ((struct __hc08_bits *)(&SCC3))->bit2
+ #define FEIE ((struct __hc08_bits *)(&SCC3))->bit1
+ #define PEIE ((struct __hc08_bits *)(&SCC3))->bit0
+
+_VOLDATA _UINT8 __at 0x16 SCS1; /* SCI Status Register 1 */
+ #define SCTE ((struct __hc08_bits *)(&SCS1))->bit7
+ #define TC ((struct __hc08_bits *)(&SCS1))->bit6
+ #define SCRF ((struct __hc08_bits *)(&SCS1))->bit5
+ #define IDLE ((struct __hc08_bits *)(&SCS1))->bit4
+ #define OR ((struct __hc08_bits *)(&SCS1))->bit3
+ #define NF ((struct __hc08_bits *)(&SCS1))->bit2
+ #define FE ((struct __hc08_bits *)(&SCS1))->bit1
+ #define PE ((struct __hc08_bits *)(&SCS1))->bit0
+
+_VOLDATA _UINT8 __at 0x17 SCS2; /* SCI Status Register 2 */
+ #define RPF ((struct __hc08_bits *)(&SCS2))->bit0
+ #define BKF ((struct __hc08_bits *)(&SCS2))->bit1
+ /* Bits 2-7 not implemented */
+
+_VOLDATA _UINT8 __at 0x18 SCDR; /* SCI Data Register */
+
+_VOLDATA _UINT8 __at 0x19 SCBR; /* SCI Baud Rate Register */
+ #define SCP1 ((struct __hc08_bits *)(&SCBR))->bit5
+ #define SCP0 ((struct __hc08_bits *)(&SCBR))->bit4
+ #define R ((struct __hc08_bits *)(&SCBR))->bit3
+ #define SCR2 ((struct __hc08_bits *)(&SCBR))->bit2
+ #define SCR1 ((struct __hc08_bits *)(&SCBR))->bit1
+ #define SCR0 ((struct __hc08_bits *)(&SCBR))->bit0
+ /*-- Bits 6 and 7 do not exist */
+
+
+_VOLDATA _UINT8 __at 0x1a KBSCR; /* Keyboard Status and Control Register */
+ #define MODEK ((struct __hc08_bits *)(&KBSCR))->bit0
+ #define IMASKK ((struct __hc08_bits *)(&KBSCR))->bit1
+ #define ACKK ((struct __hc08_bits *)(&KBSCR))->bit2
+ #define KEYF ((struct __hc08_bits *)(&KBSCR))->bit3
+ /*-- Bits 4-7 do not exist */
+
+_VOLDATA _UINT8 __at 0x1b KBIER; /* Keyboard Interrupt Enable Register */
+ #define KBIE0 ((struct __hc08_bits *)(&KBIER))->bit0
+ #define KBIE1 ((struct __hc08_bits *)(&KBIER))->bit1
+ #define KBIE3 ((struct __hc08_bits *)(&KBIER))->bit3
+ #define KBIE2 ((struct __hc08_bits *)(&KBIER))->bit2
+ #define KBIE4 ((struct __hc08_bits *)(&KBIER))->bit4
+ #define KBIE5 ((struct __hc08_bits *)(&KBIER))->bit5
+ #define KBIE6 ((struct __hc08_bits *)(&KBIER))->bit6
+ #define KBIE7 ((struct __hc08_bits *)(&KBIER))->bit7
+
+_VOLDATA _UINT8 __at 0x1D INTSCR; /* IRQ status/control */
+ #define IRQF1 ((struct __hc08_bits *)(&INTSCR))->bit3
+ #define ACK1 ((struct __hc08_bits *)(&INTSCR))->bit2
+ #define IMASK1 ((struct __hc08_bits *)(&INTSCR))->bit1
+ #define MODE1 ((struct __hc08_bits *)(&INTSCR))->bit0
+ /* Bits 4-7 unimplemented */
+
+_VOLDATA _UINT8 __at 0x1e CONFIG2; /* Configuration Register 2 */
+/* CONFIG2 is one-time writeble, so can't use bitfields */
+
+_VOLDATA _UINT8 __at 0x1f CONFIG1; /* Configuration Register 1 */
+/* CONFIG1 is one-time writeable, so can't use bitfields */
+
+_VOLDATA _UINT8 __at 0x20 T1SC; /* TIM 1 Status and Control */
+ #define PS0 ((struct __hc08_bits *)(&T1SC))->bit0
+ #define PS1 ((struct __hc08_bits *)(&T1SC))->bit1
+ #define PS2 ((struct __hc08_bits *)(&T1SC))->bit2
+ #define TRST ((struct __hc08_bits *)(&T1SC))->bit4
+ #define TSTOP ((struct __hc08_bits *)(&T1SC))->bit5
+ #define TOIE ((struct __hc08_bits *)(&T1SC))->bit6
+ #define TOF ((struct __hc08_bits *)(&T1SC))->bit7
+
+_VOLDATA _UINT16 __at 0x21 T1CNT; /* TIM1 Counter High & Low Registers */
+_VOLDATA _UINT8 __at 0x21 T1CNTH; /* TIM1 Counter Register High */
+_VOLDATA _UINT8 __at 0x22 T1CNTL; /* TIM1 Counter Register Low */
+
+_VOLDATA _UINT16 __at 0x23 T1MOD; /* TIM1 Counter Modulo High & Low Registers */
+_VOLDATA _UINT8 __at 0x23 T1MODH; /* TIM1 Counter Modulo Register High */
+_VOLDATA _UINT8 __at 0x24 T1MODL; /* TIM1 Counter Modulo Register Low */
+
+_VOLDATA _UINT8 __at 0x25 T1SC0; /* TIM1 Channel 0 Status and Control Register */
+ #define CH0MAX ((struct __hc08_bits *)(&T1SC0))->bit0
+ #define TOV0 ((struct __hc08_bits *)(&T1SC0))->bit1
+ #define ELS0A ((struct __hc08_bits *)(&T1SC0))->bit2
+ #define ELS0B ((struct __hc08_bits *)(&T1SC0))->bit3
+ #define MS0A ((struct __hc08_bits *)(&T1SC0))->bit4
+ #define MS0B ((struct __hc08_bits *)(&T1SC0))->bit5
+ #define CH0IE ((struct __hc08_bits *)(&T1SC0))->bit6
+ #define CH0F ((struct __hc08_bits *)(&T1SC0))->bit7
+
+_VOLDATA _UINT16 __at 0x26 T1CH0; /* TIM1 Channel 0 High & Low Registers */
+_VOLDATA _UINT8 __at 0x26 T1CH0H; /* TIM1 Channel 0 Register High */
+_VOLDATA _UINT8 __at 0x27 T1CH0L; /* TIM1 Channel 0 Register Low */
+
+_VOLDATA _UINT8 __at 0x28 T1SC1; /* TIM1 Channel 1 Status and Control Register */
+ #define CH1MAX ((struct __hc08_bits *)(&T1SC1))->bit0
+ #define TOV1 ((struct __hc08_bits *)(&T1SC1))->bit1
+ #define ELS1A ((struct __hc08_bits *)(&T1SC1))->bit2
+ #define ELS1B ((struct __hc08_bits *)(&T1SC1))->bit3
+ #define MS1A ((struct __hc08_bits *)(&T1SC1))->bit4
+ #define CH1IE ((struct __hc08_bits *)(&T1SC1))->bit6
+ #define CH1F ((struct __hc08_bits *)(&T1SC1))->bit7
+
+_VOLDATA _UINT16 __at 0x29 T1CH1; /* TIM1 Channel 1 High & Low Registers */
+_VOLDATA _UINT8 __at 0x29 T1CH1H; /* TIM1 Channel 1 Register High */
+_VOLDATA _UINT8 __at 0x2A T1CH1L; /* TIM1 Channel 1 Register Low */
+
+_VOLDATA _UINT8 __at 0x30 T2SC; /* TIM2 Status and Control Register */
+ #define PS0_2 ((struct __hc08_bits *)(&T2SC))->bit0
+ #define PS1_2 ((struct __hc08_bits *)(&T2SC0))->bit1
+ #define PS2_2 ((struct __hc08_bits *)(&T2SC0))->bit2
+ #define TRST_2 ((struct __hc08_bits *)(&T2SC0))->bit4
+ #define TSTOP_2 ((struct __hc08_bits *)(&T2SC0))->bit5
+ #define TOIE_2 ((struct __hc08_bits *)(&T2SC0))->bit6
+ #define TOF_2 ((struct __hc08_bits *)(&T2SC0))->bit7
+
+_VOLDATA _UINT16 __at 0x31 T2CNT; /* TIM2 Counter Registers */
+_VOLDATA _UINT8 __at 0x31 T2CNTH; /* TIM2 Counter Register High */
+_VOLDATA _UINT8 __at 0x32 T2CNTL; /* TIM2 Counter Register Low */
+
+
+_VOLDATA _UINT16 __at 0x33 T2MOD; /* TIM2 Counter Modulo Registers */
+_VOLDATA _UINT8 __at 0x33 T2MODH; /* TIM2 Counter Modulo Register High */
+_VOLDATA _UINT8 __at 0x34 T2MODL; /* TIM2 Counter Modulo Register Low */
+
+
+_VOLDATA _UINT8 __at 0x35 T2SC1; /* TIM2 Channel 0 Status and Control Register */
+ #define CH0MAX_2 ((struct __hc08_bits *)(&T2SC1))->bit0
+ #define TOV0_2 ((struct __hc08_bits *)(&T2SC1))->bit1
+ #define ELS0A_2 ((struct __hc08_bits *)(&T2SC1))->bit2
+ #define ELS0B_2 ((struct __hc08_bits *)(&T2SC1))->bit3
+ #define MS0A_2 ((struct __hc08_bits *)(&T2SC1))->bit4
+ #define CH0IE_2 ((struct __hc08_bits *)(&T2SC1))->bit6
+ #define CH0F_2 ((struct __hc08_bits *)(&T2SC1))->bit7
+
+_VOLDATA _UINT16 __at 0x36 T2CH0; /* TIM2 Channel 0 High & Low Registers */
+_VOLDATA _UINT8 __at 0x36 T2CH0H; /* TIM2 Channel 0 Register High */
+_VOLDATA _UINT8 __at 0x37 T2CH0L; /* TIM2 Channel 0 Register Low */
+
+_VOLDATA _UINT8 __at 0x38 T2SC1; /* TIM2 Channel 1 Status and Control Register */
+ #define CH1MAX_2 ((struct __hc08_bits *)(&T2SC1))->bit0
+ #define TOV1_2 ((struct __hc08_bits *)(&T2SC1))->bit1
+ #define ELS1A_2 ((struct __hc08_bits *)(&T2SC1))->bit2
+ #define ELS1B_2 ((struct __hc08_bits *)(&T2SC1))->bit3
+ #define MS1A_2 ((struct __hc08_bits *)(&T2SC1))->bit4
+ #define CH1IE_2 ((struct __hc08_bits *)(&T2SC1))->bit6
+ #define CH1F_2 ((struct __hc08_bits *)(&T2SC1))->bit7
+
+_VOLDATA _UINT16 __at 0x39 T2CH1; /* TIM2 Channel 1 High & Low Registers */
+_VOLDATA _UINT8 __at 0x39 T2CH1H; /* TIM2 Channel 1 Register High */
+_VOLDATA _UINT8 __at 0x3a T2CH1L; /* TIM2 Channel 1 Register Low */
+
+
+_VOLDATA _UINT8 __at 0x3c ADSCR; /* Analog-to-Digital Status and Control Reg. */
+ #define COCO ((struct __hc08_bits *)(&ADSCR))->bit7
+ #define AIEN ((struct __hc08_bits *)(&ADSCR))->bit6
+ #define ADCO ((struct __hc08_bits *)(&ADSCR))->bit5
+ #define ADCH4 ((struct __hc08_bits *)(&ADSCR))->bit4
+ #define ADCH3 ((struct __hc08_bits *)(&ADSCR))->bit3
+ #define ADCH2 ((struct __hc08_bits *)(&ADSCR))->bit2
+ #define ADCH1 ((struct __hc08_bits *)(&ADSCR))->bit1
+ #define ADCH0 ((struct __hc08_bits *)(&ADSCR))->bit0
+
+_VOLDATA _UINT8 __at 0x3d ADR; /* Analog-to-Digital Data Register */
+
+_VOLDATA _UINT8 __at 0x3e ADCLK; /* Analog-to-Digital Clock */
+ #define ADIV2 ((struct __hc08_bits *)(&ADCLK))->bit7
+ #define ADIV1 ((struct __hc08_bits *)(&ADCLK))->bit6
+ #define ADIV0 ((struct __hc08_bits *)(&ADCLK))->bit5
+ /* Bits 0-4 unimplemented */
+
+_VOLXDATA _UINT8 __at 0xfe00 BSR; /* SIM Break Status Register */
+ #define SBSW ((struct __hc08_bits *)(&BSR))->bit1
+
+_VOLXDATA _UINT8 __at 0xfe01 RSR; /* SIM Reset Status Register */
+ #define LVI ((struct __hc08_bits *)(&RSR))->bit1
+ #define MODRST ((struct __hc08_bits *)(&RSR))->bit2
+ #define ILAD ((struct __hc08_bits *)(&RSR))->bit3
+ #define ILOP ((struct __hc08_bits *)(&RSR))->bit4
+ #define COP ((struct __hc08_bits *)(&RSR))->bit5
+ #define PIN ((struct __hc08_bits *)(&RSR))->bit6
+ #define POR ((struct __hc08_bits *)(&RSR))->bit7
+ /* Bit 0 unimplemented */
+
+_VOLXDATA _UINT8 __at 0xfe02 SUBAR; /* SIM Upper Byte Address */
+
+_VOLXDATA _UINT8 __at 0xfe03 BFCR; /* SIM Break Flag Control Register */
+ #define BFCE ((struct __hc08_bits *)(&BFCR))->bit7
+
+_VOLXDATA _UINT8 __at 0xfe04 INT1; /* Interrupt Status Register 1 */
+ #define IF1 ((struct __hc08_bits *)(&INT1))->bit2
+ #define IF3 ((struct __hc08_bits *)(&INT1))->bit4
+ #define IF4 ((struct __hc08_bits *)(&INT1))->bit5
+ #define IF5 ((struct __hc08_bits *)(&INT1))->bit6
+
+
+_VOLXDATA _UINT8 __at 0xfe05 INT2; /* Interrupt Status Register 2 */
+ #define IF14 ((struct __hc08_bits *)(&INT2))->bit7
+
+_VOLXDATA _UINT8 __at 0xfe06 INT3; /* Interrupt Status Register 3 */
+ #define IF16 ((struct __hc08_bits *)(&INT3))->bit1
+ #define IF15 ((struct __hc08_bits *)(&INT3))->bit0
+
+_VOLXDATA _UINT8 __at 0xfe08 FLCR; /* FLASH Control Register */
+ #define PGM ((struct __hc08_bits *)(&FLCR))->bit0
+ #define ERASE ((struct __hc08_bits *)(&FLCR))->bit1
+ #define MASS ((struct __hc08_bits *)(&FLCR))->bit2
+ #define HVEN ((struct __hc08_bits *)(&FLCR))->bit3
+
+_VOLXDATA _UINT8 __at 0xfe09 FLBPR; /* Flash Block Protect Register */
+ #define BPR0 ((struct __hc08_bits *)(&FLBPR))->bit0
+ #define BPR1 ((struct __hc08_bits *)(&FLBPR))->bit1
+ #define BPR2 ((struct __hc08_bits *)(&FLBPR))->bit2
+ #define BPR3 ((struct __hc08_bits *)(&FLBPR))->bit3
+ #define BPR4 ((struct __hc08_bits *)(&FLBPR))->bit4
+ #define BPR5 ((struct __hc08_bits *)(&FLBPR))->bit5
+ #define BPR6 ((struct __hc08_bits *)(&FLBPR))->bit6
+ #define BPR7 ((struct __hc08_bits *)(&FLBPR))->bit7
+
+_VOLXDATA _UINT16 __at 0xfe0C BRK; /* Break Address High & Low Registers */
+_VOLXDATA _UINT8 __at 0xfe0C BRKH; /* Break Address High Register */
+_VOLXDATA _UINT8 __at 0xfe0D BRKL; /* Break Address Low Register */
+
+_VOLXDATA _UINT8 __at 0xfe0e BRKSCR; /* Break Status and Control Register */
+ #define BRKA ((struct __hc08_bits *)(&BRKSCR))->bit6
+ #define BRKE ((struct __hc08_bits *)(&BRKSCR))->bit7
+
+_VOLXDATA _UINT8 __at 0xffff COPCTL; /* COP Control Register */
+
+#endif
--- /dev/null
+/*-------------------------------------------------------------------------
+ Register Declarations for Motorola MC68HC908QY & MC68HC908QT
+
+ Written By - Erik Petrich
+ epetrich@users.sourceforge.net (2003)
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2, or (__at your option) any
+ later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+ In other words, you are welcome to use, share and improve this program.
+ You are forbidden to forbid anyone else to use, share and improve
+ what you give them. Help stamp out software-hoarding!
+-------------------------------------------------------------------------*/
+
+#ifndef _MC68HC908QY_H
+#define _MC68HC908QY_H
+
+#ifndef _UINT8
+ #define _UINT8 unsigned char
+#endif
+#ifndef _UINT16
+ #define _UINT16 unsigned int
+#endif
+#ifndef _VOLDATA
+ #define _VOLDATA volatile __data
+#endif
+#ifndef _VOLXDATA
+ #define _VOLXDATA volatile __xdata
+#endif
+
+struct __hc08_bits
+{
+ unsigned int bit0:1;
+ unsigned int bit1:1;
+ unsigned int bit2:1;
+ unsigned int bit3:1;
+ unsigned int bit4:1;
+ unsigned int bit5:1;
+ unsigned int bit6:1;
+ unsigned int bit7:1;
+};
+
+
+_VOLDATA _UINT8 __at 0x00 PTA; /* Port A Data Register */
+ #define PTA0 ((struct __hc08_bits *)(&PTA))->bit0
+ #define PTA1 ((struct __hc08_bits *)(&PTA))->bit1
+ #define PTA2 ((struct __hc08_bits *)(&PTA))->bit2
+ #define PTA3 ((struct __hc08_bits *)(&PTA))->bit3
+ #define PTA4 ((struct __hc08_bits *)(&PTA))->bit4
+ #define PTA5 ((struct __hc08_bits *)(&PTA))->bit5
+ #define AWUL ((struct __hc08_bits *)(&PTA))->bit6
+
+_VOLDATA _UINT8 __at 0x01 PTB; /* Port B Data Register */
+ #define PTB0 ((struct __hc08_bits *)(&PTB))->bit0
+ #define PTB1 ((struct __hc08_bits *)(&PTB))->bit1
+ #define PTB2 ((struct __hc08_bits *)(&PTB))->bit2
+ #define PTB3 ((struct __hc08_bits *)(&PTB))->bit3
+ #define PTB4 ((struct __hc08_bits *)(&PTB))->bit4
+ #define PTB5 ((struct __hc08_bits *)(&PTB))->bit5
+ #define PTB6 ((struct __hc08_bits *)(&PTB))->bit6
+ #define PTB7 ((struct __hc08_bits *)(&PTB))->bit7
+
+_VOLDATA _UINT8 __at 0x04 DDRA; /* Data Direction Register A */
+ #define DDRA0 ((struct __hc08_bits *)(&DDRA))->bit0
+ #define DDRA1 ((struct __hc08_bits *)(&DDRA))->bit1
+ #define DDRA3 ((struct __hc08_bits *)(&DDRA))->bit3
+ #define DDRA4 ((struct __hc08_bits *)(&DDRA))->bit4
+ #define DDRA5 ((struct __hc08_bits *)(&DDRA))->bit5
+
+_VOLDATA _UINT8 __at 0x05 DDRB; /* Data Direction Register B */
+ #define DDRB0 ((struct __hc08_bits *)(&DDRB))->bit0
+ #define DDRB1 ((struct __hc08_bits *)(&DDRB))->bit1
+ #define DDRB2 ((struct __hc08_bits *)(&DDRB))->bit2
+ #define DDRB3 ((struct __hc08_bits *)(&DDRB))->bit3
+ #define DDRB4 ((struct __hc08_bits *)(&DDRB))->bit4
+ #define DDRB5 ((struct __hc08_bits *)(&DDRB))->bit5
+ #define DDRB6 ((struct __hc08_bits *)(&DDRB))->bit6
+ #define DDRB7 ((struct __hc08_bits *)(&DDRB))->bit7
+
+_VOLDATA _UINT8 __at 0x0b PTAPUE; /* Port A Input Pullup Enable Register */
+ #define PTAPUE0 ((struct __hc08_bits *)(&PTAPUE))->bit0
+ #define PTAPUE1 ((struct __hc08_bits *)(&PTAPUE))->bit1
+ #define PTAPUE2 ((struct __hc08_bits *)(&PTAPUE))->bit2
+ #define PTAPUE3 ((struct __hc08_bits *)(&PTAPUE))->bit3
+ #define PTAPUE4 ((struct __hc08_bits *)(&PTAPUE))->bit4
+ #define PTAPUE5 ((struct __hc08_bits *)(&PTAPUE))->bit5
+ #define OSC2EN ((struct __hc08_bits *)(&PTAPUE))->bit7
+
+_VOLDATA _UINT8 __at 0x0c PTBPUE; /* Port B Input Pullup Enable Register */
+ #define PTBPUE0 ((struct __hc08_bits *)(&PTBPUE))->bit0
+ #define PTBPUE1 ((struct __hc08_bits *)(&PTBPUE))->bit1
+ #define PTBPUE2 ((struct __hc08_bits *)(&PTBPUE))->bit2
+ #define PTBPUE3 ((struct __hc08_bits *)(&PTBPUE))->bit3
+ #define PTBPUE4 ((struct __hc08_bits *)(&PTBPUE))->bit4
+ #define PTBPUE5 ((struct __hc08_bits *)(&PTBPUE))->bit5
+ #define PTBPUE6 ((struct __hc08_bits *)(&PTBPUE))->bit6
+ #define PTBPUE7 ((struct __hc08_bits *)(&PTBPUE))->bit7
+
+_VOLDATA _UINT8 __at 0x1a KBSCR; /* Keyboard Status and Control Register */
+ #define MODEK ((struct __hc08_bits *)(&KBSCR))->bit0
+ #define IMASKK ((struct __hc08_bits *)(&KBSCR))->bit1
+ #define ACKK ((struct __hc08_bits *)(&KBSCR))->bit2
+ #define KEYF ((struct __hc08_bits *)(&KBSCR))->bit3
+
+_VOLDATA _UINT8 __at 0x1b KBIER; /* Keyboard Interrupt Enable Register */
+ #define KBIE0 ((struct __hc08_bits *)(&KBIER))->bit0
+ #define KBIE1 ((struct __hc08_bits *)(&KBIER))->bit1
+ #define KBIE2 ((struct __hc08_bits *)(&KBIER))->bit2
+ #define KBIE3 ((struct __hc08_bits *)(&KBIER))->bit3
+ #define KBIE4 ((struct __hc08_bits *)(&KBIER))->bit4
+ #define KBIE5 ((struct __hc08_bits *)(&KBIER))->bit5
+ #define AWUIE ((struct __hc08_bits *)(&KBIER))->bit6
+
+_VOLDATA _UINT8 __at 0x1d INTSCR; /* IRQ Status and Control Register */
+ #define MODE1 ((struct __hc08_bits *)(&INTSCR))->bit0
+ #define IMASK1 ((struct __hc08_bits *)(&INTSCR))->bit1
+ #define ACK1 ((struct __hc08_bits *)(&INTSCR))->bit2
+ #define IRQF1 ((struct __hc08_bits *)(&INTSCR))->bit3
+
+_VOLDATA _UINT8 __at 0x1e CONFIG2; /* Configuration Register 2 */
+/* CONFIG2 is one-time writeable, so can't use bitfields */
+
+_VOLDATA _UINT8 __at 0x1f CONFIG1; /* Configuration Register 1 */
+/* CONFIG1 is one-time writeable, so can't use bitfields */
+
+_VOLDATA _UINT8 __at 0x20 TSC; /* TIM Status and Control */
+ #define PS0 ((struct __hc08_bits *)(&TSC))->bit0
+ #define PS1 ((struct __hc08_bits *)(&TSC))->bit1
+ #define PS2 ((struct __hc08_bits *)(&TSC))->bit2
+ #define TRST ((struct __hc08_bits *)(&TSC))->bit4
+ #define TSTOP ((struct __hc08_bits *)(&TSC))->bit5
+ #define TOIE ((struct __hc08_bits *)(&TSC))->bit6
+ #define TOF ((struct __hc08_bits *)(&TSC))->bit7
+
+_VOLDATA _UINT8 __at 0x21 TCNTH; /* TIM Counter Register High */
+_VOLDATA _UINT8 __at 0x22 TCNTL; /* TIM Counter Register Low */
+_VOLDATA _UINT16 __at 0x21 TCNT; /* TIM Counter High & Low Registers */
+
+_VOLDATA _UINT8 __at 0x23 TMODH; /* TIM Counter Modulo Register High */
+_VOLDATA _UINT8 __at 0x24 TMODL; /* TIM Counter Modulo Register Low */
+_VOLDATA _UINT16 __at 0x23 TMOD; /* TIM Counter Modulo High & Low Registers */
+
+_VOLDATA _UINT8 __at 0x25 TSC0; /* TIM Channel 0 Status and Control Register */
+ #define CH0MAX ((struct __hc08_bits *)(&TSC0))->bit0
+ #define TOV0 ((struct __hc08_bits *)(&TSC0))->bit1
+ #define ELS0A ((struct __hc08_bits *)(&TSC0))->bit2
+ #define ELS0B ((struct __hc08_bits *)(&TSC0))->bit3
+ #define MS0A ((struct __hc08_bits *)(&TSC0))->bit4
+ #define MS0B ((struct __hc08_bits *)(&TSC0))->bit5
+ #define CH0IE ((struct __hc08_bits *)(&TSC0))->bit6
+ #define CH0F ((struct __hc08_bits *)(&TSC0))->bit7
+
+_VOLDATA _UINT8 __at 0x26 TCH0H; /* TIM Channel 0 Register High */
+_VOLDATA _UINT8 __at 0x27 TCH0L; /* TIM Channel 0 Register Low */
+_VOLDATA _UINT16 __at 0x26 TCH0; /* TIM Channel 0 High & Low Registers */
+
+_VOLDATA _UINT8 __at 0x28 TSC1; /* TIM Channel 1 Status and Control Register */
+ #define CH1MAX ((struct __hc08_bits *)(&TSC1))->bit0
+ #define TOV1 ((struct __hc08_bits *)(&TSC1))->bit1
+ #define ELS1A ((struct __hc08_bits *)(&TSC1))->bit2
+ #define ELS1B ((struct __hc08_bits *)(&TSC1))->bit3
+ #define MS1A ((struct __hc08_bits *)(&TSC1))->bit4
+ #define MS1B ((struct __hc08_bits *)(&TSC1))->bit5
+ #define CH1IE ((struct __hc08_bits *)(&TSC1))->bit6
+ #define CH1F ((struct __hc08_bits *)(&TSC1))->bit7
+
+_VOLDATA _UINT8 __at 0x29 TCH1H; /* TIM Channel 1 Register High */
+_VOLDATA _UINT8 __at 0x2a TCH1L; /* TIM Channel 1 Register Low */
+_VOLDATA _UINT16 __at 0x29 TCH1; /* TIM Channel 1 High & Low Registers */
+
+_VOLDATA _UINT8 __at 0x36 OSCSTAT; /* Oscillator Status Register */
+ #define ECGST ((struct __hc08_bits *)(&OSCSTAT))->bit0
+ #define ECGON ((struct __hc08_bits *)(&OSCSTAT))->bit1
+
+_VOLDATA _UINT8 __at 0x38 OSCTRIM; /* Oscillator Trim Register */
+
+_VOLDATA _UINT8 __at 0x3c ADSCR; /* ADC Status and Control Register */
+ #define CH0 ((struct __hc08_bits *)(&ADSCR))->bit0
+ #define CH1 ((struct __hc08_bits *)(&ADSCR))->bit1
+ #define CH2 ((struct __hc08_bits *)(&ADSCR))->bit2
+ #define CH3 ((struct __hc08_bits *)(&ADSCR))->bit3
+ #define CH4 ((struct __hc08_bits *)(&ADSCR))->bit4
+ #define ADC0 ((struct __hc08_bits *)(&ADSCR))->bit5
+ #define AIEN ((struct __hc08_bits *)(&ADSCR))->bit6
+ #define COCO ((struct __hc08_bits *)(&ADSCR))->bit7
+
+_VOLDATA _UINT8 __at 0x3e ADR; /* ADC Data Register */
+
+_VOLDATA _UINT8 __at 0x3f ADICLK; /* ADS Input Clock Register */
+ #define ADIV0 ((struct __hc08_bits *)(&ADICLK))->bit5
+ #define ADIV1 ((struct __hc08_bits *)(&ADICLK))->bit6
+ #define ADIV2 ((struct __hc08_bits *)(&ADICLK))->bit7
+
+_VOLXDATA _UINT8 __at 0xfe00 BSR; /* Break Status Register */
+ #define SBSW ((struct __hc08_bits *)(&BSR))->bit1
+
+_VOLXDATA _UINT8 __at 0xfe01 SRSR; /* SIM Reset Status Register */
+ #define LVI ((struct __hc08_bits *)(&SRSR))->bit1
+ #define MODRST ((struct __hc08_bits *)(&SRSR))->bit2
+ #define ILAD ((struct __hc08_bits *)(&SRSR))->bit3
+ #define ILOP ((struct __hc08_bits *)(&SRSR))->bit4
+ #define COP ((struct __hc08_bits *)(&SRSR))->bit5
+ #define PIN ((struct __hc08_bits *)(&SRSR))->bit6
+ #define POR ((struct __hc08_bits *)(&SRSR))->bit7
+
+_VOLXDATA _UINT8 __at 0xfe02 BRKAR; /* Break Auxilliary Register */
+ #define BDCOP ((struct __hc08_bits *)(&BRKAR))->bit0
+
+_VOLXDATA _UINT8 __at 0xfe03 BFCF; /* Break Flag Control Register */
+ #define BFCF ((struct __hc08_bits *)(&BFCF))->bit7
+
+_VOLXDATA _UINT8 __at 0xfe04 INT1; /* Interrupt Status Register 1 */
+ #define IF1 ((struct __hc08_bits *)(&INT1))->bit2
+ #define IF3 ((struct __hc08_bits *)(&INT1))->bit4
+ #define IF4 ((struct __hc08_bits *)(&INT1))->bit5
+ #define IF5 ((struct __hc08_bits *)(&INT1))->bit6
+
+_VOLXDATA _UINT8 __at 0xfe05 INT2; /* Interrupt Status Register 2 */
+ #define IF14 ((struct __hc08_bits *)(&INT2))->bit7
+
+_VOLXDATA _UINT8 __at 0xfe06 INT3; /* Interrupt Status Register 3 */
+ #define IF15 ((struct __hc08_bits *)(&INT3))->bit0
+
+_VOLXDATA _UINT8 __at 0xfe08 FLCR; /* FLASH Control Register */
+ #define PGM ((struct __hc08_bits *)(&FLCR))->bit0
+ #define ERASE ((struct __hc08_bits *)(&FLCR))->bit1
+ #define MASS ((struct __hc08_bits *)(&FLCR))->bit2
+ #define HVEN ((struct __hc08_bits *)(&FLCR))->bit3
+
+_VOLXDATA _UINT8 __at 0xfe09 BRKH; /* Break Address High Register */
+_VOLXDATA _UINT8 __at 0xfe0a BRKL; /* Break Address Low Register */
+_VOLXDATA _UINT16 __at 0xfe09 BRK; /* Break Address High & Low Registers */
+
+_VOLXDATA _UINT8 __at 0xfe0b BRKSCR; /* Break Status and Control Register */
+ #define BRKA ((struct __hc08_bits *)(&BRKSCR))->bit6
+ #define BRKE ((struct __hc08_bits *)(&BRKSCR))->bit7
+
+_VOLXDATA _UINT8 __at 0xfe0c LVISR; /* LVI Status Register */
+ #define LVIOUT ((struct __hc08_bits *)(&LVISR))->bit7
+
+_VOLXDATA _UINT8 __at 0xffbe FLBPR; /* FLASH Block Protect Register */
+_VOLXDATA _UINT8 __at 0xffc0 OSCTRIMVAL; /* Oscillator Trim Value */
+_VOLXDATA _UINT8 __at 0xffff COPCTL; /* COP Control Register */
+
+
+#endif
+
MEMHEADER
{
- MEMHEADER xdata * next;
+ MEMHEADER __xdata * next;
unsigned int len;
unsigned char mem[];
};
#ifdef SDCC_STACK_AUTO
-extern void init_dynamic_memory(void xdata * heap, unsigned int size) reentrant;
-extern void xdata * calloc (size_t nmemb, size_t size) reentrant;
-extern void xdata * malloc (size_t size) reentrant;
-extern void xdata * realloc (void * ptr, size_t size) reentrant;
-extern void free (void * ptr) reentrant;
+extern void init_dynamic_memory(void __xdata * heap, unsigned int size) __reentrant;
+extern void __xdata * calloc (size_t nmemb, size_t size) __reentrant;
+extern void __xdata * malloc (size_t size) __reentrant;
+extern void __xdata * realloc (void * ptr, size_t size) __reentrant;
+extern void free (void * ptr) __reentrant;
#else
-extern void init_dynamic_memory(void xdata * heap, unsigned int size);
-extern void xdata * calloc (size_t nmemb, size_t size);
-extern void xdata * malloc (size_t size);
-extern void xdata * realloc (void * ptr, size_t size);
+extern void init_dynamic_memory(void __xdata * heap, unsigned int size);
+extern void __xdata * calloc (size_t nmemb, size_t size);
+extern void __xdata * malloc (size_t size);
+extern void __xdata * realloc (void * ptr, size_t size);
extern void free (void * ptr);
#endif
#if defined(SDCC_z80) || defined(SDCC_gbz80)
#define _FLOAT_FUNC_REENTRANT
#else
-#define _FLOAT_FUNC_REENTRANT reentrant
+#define _FLOAT_FUNC_REENTRANT __reentrant
#endif
/**********************************************
+++ /dev/null
-/*-------------------------------------------------------------------------
- Register Declarations for Motorola MC68HC908GP32
-
- Copyright (c) 2004, Juan Gonzalez <juan@iearobotics.com>
-
- Based on mc68hc908qy.h,
- Written By - Erik Petrich
- epetrich@users.sourceforge.net (2003)
-
- This program is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published by the
- Free Software Foundation; either version 2, or (at your option) any
- later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
- In other words, you are welcome to use, share and improve this program.
- You are forbidden to forbid anyone else to use, share and improve
- what you give them. Help stamp out software-hoarding!
--------------------------------------------------------------------------*/
-
-#ifndef MC68HC908GP32_H
-#define MC68HC908GP32_H
-
-#ifndef UINT8
- #define UINT8 unsigned char
-#endif
-#ifndef UINT16
- #define UINT16 unsigned int
-#endif
-#ifndef VOLDATA
- #define VOLDATA volatile data
-#endif
-#ifndef VOLXDATA
- #define VOLXDATA volatile xdata
-#endif
-
-struct _hc08_bits
-{
- unsigned int bit0:1;
- unsigned int bit1:1;
- unsigned int bit2:1;
- unsigned int bit3:1;
- unsigned int bit4:1;
- unsigned int bit5:1;
- unsigned int bit6:1;
- unsigned int bit7:1;
-};
-
-
-VOLDATA UINT8 at 0x00 PTA; /* Port A Data Register */
-#define PORTA PTA /* Alias for PTA */
- #define PTA0 ((struct _hc08_bits *)(&PTA))->bit0
- #define PTA1 ((struct _hc08_bits *)(&PTA))->bit1
- #define PTA2 ((struct _hc08_bits *)(&PTA))->bit2
- #define PTA3 ((struct _hc08_bits *)(&PTA))->bit3
- #define PTA4 ((struct _hc08_bits *)(&PTA))->bit4
- #define PTA5 ((struct _hc08_bits *)(&PTA))->bit5
- #define AWUL ((struct _hc08_bits *)(&PTA))->bit6
-
-VOLDATA UINT8 at 0x01 PTB; /* Port B Data Register */
-#define PORTB PTB /* Alias for PTB */
- #define PTB0 ((struct _hc08_bits *)(&PTB))->bit0
- #define PTB1 ((struct _hc08_bits *)(&PTB))->bit1
- #define PTB2 ((struct _hc08_bits *)(&PTB))->bit2
- #define PTB3 ((struct _hc08_bits *)(&PTB))->bit3
- #define PTB4 ((struct _hc08_bits *)(&PTB))->bit4
- #define PTB5 ((struct _hc08_bits *)(&PTB))->bit5
- #define PTB6 ((struct _hc08_bits *)(&PTB))->bit6
- #define PTB7 ((struct _hc08_bits *)(&PTB))->bit7
-
-VOLDATA UINT8 at 0x02 PTC; /* Port C Data Register */
-#define PORTC PTC /* Alias for PTC */
- #define PTC0 ((struct _hc08_bits *)(&PTC))->bit0
- #define PTC1 ((struct _hc08_bits *)(&PTC))->bit1
- #define PTC2 ((struct _hc08_bits *)(&PTC))->bit2
- #define PTC3 ((struct _hc08_bits *)(&PTC))->bit3
- #define PTC4 ((struct _hc08_bits *)(&PTC))->bit4
- #define PTC5 ((struct _hc08_bits *)(&PTC))->bit5
- #define PTC6 ((struct _hc08_bits *)(&PTC))->bit6
- #define PTC7 ((struct _hc08_bits *)(&PTC))->bit7
-
-VOLDATA UINT8 at 0x03 PTD; /* Port D Data Register */
-#define PORTD PTD /* Alias for PTD */
- #define PTD0 ((struct _hc08_bits *)(&PTD))->bit0
- #define PTD1 ((struct _hc08_bits *)(&PTD))->bit1
- #define PTD2 ((struct _hc08_bits *)(&PTD))->bit2
- #define PTD3 ((struct _hc08_bits *)(&PTD))->bit3
- #define PTD4 ((struct _hc08_bits *)(&PTD))->bit4
- #define PTD5 ((struct _hc08_bits *)(&PTD))->bit5
- #define PTD6 ((struct _hc08_bits *)(&PTD))->bit6
- #define PTD7 ((struct _hc08_bits *)(&PTD))->bit7
-
-VOLDATA UINT8 at 0x04 DDRA; /* Data Direction Register A */
- #define DDRA0 ((struct _hc08_bits *)(&DDRA))->bit0
- #define DDRA1 ((struct _hc08_bits *)(&DDRA))->bit1
- #define DDRA2 ((struct _hc08_bits *)(&DDRA))->bit2
- #define DDRA3 ((struct _hc08_bits *)(&DDRA))->bit3
- #define DDRA4 ((struct _hc08_bits *)(&DDRA))->bit4
- #define DDRA5 ((struct _hc08_bits *)(&DDRA))->bit5
- #define DDRA6 ((struct _hc08_bits *)(&DDRA))->bit6
- #define DDRA7 ((struct _hc08_bits *)(&DDRA))->bit7
-
-VOLDATA UINT8 at 0x05 DDRB; /* Data Direction Register B */
- #define DDRB0 ((struct _hc08_bits *)(&DDRB))->bit0
- #define DDRB1 ((struct _hc08_bits *)(&DDRB))->bit1
- #define DDRB2 ((struct _hc08_bits *)(&DDRB))->bit2
- #define DDRB3 ((struct _hc08_bits *)(&DDRB))->bit3
- #define DDRB4 ((struct _hc08_bits *)(&DDRB))->bit4
- #define DDRB5 ((struct _hc08_bits *)(&DDRB))->bit5
- #define DDRB6 ((struct _hc08_bits *)(&DDRB))->bit6
- #define DDRB7 ((struct _hc08_bits *)(&DDRB))->bit7
-
-VOLDATA UINT8 at 0x06 DDRC; /* Data Direction Register C */
- #define DDRC0 ((struct _hc08_bits *)(&DDRC))->bit0
- #define DDRC1 ((struct _hc08_bits *)(&DDRC))->bit1
- #define DDRC2 ((struct _hc08_bits *)(&DDRC))->bit2
- #define DDRC3 ((struct _hc08_bits *)(&DDRC))->bit3
- #define DDRC4 ((struct _hc08_bits *)(&DDRC))->bit4
- #define DDRC5 ((struct _hc08_bits *)(&DDRC))->bit5
- #define DDRC6 ((struct _hc08_bits *)(&DDRC))->bit6
- #define DDRC7 ((struct _hc08_bits *)(&DDRC))->bit7
-
-VOLDATA UINT8 at 0x07 DDRD; /* Data Direction Register D */
- #define DDRD0 ((struct _hc08_bits *)(&DDRD))->bit0
- #define DDRD1 ((struct _hc08_bits *)(&DDRD))->bit1
- #define DDRD2 ((struct _hc08_bits *)(&DDRD))->bit2
- #define DDRD3 ((struct _hc08_bits *)(&DDRD))->bit3
- #define DDRD4 ((struct _hc08_bits *)(&DDRD))->bit4
- #define DDRD5 ((struct _hc08_bits *)(&DDRD))->bit5
- #define DDRD6 ((struct _hc08_bits *)(&DDRD))->bit6
- #define DDRD7 ((struct _hc08_bits *)(&DDRD))->bit7
-
-VOLDATA UINT8 at 0x08 PTE; /* Port E Data Register */
-#define PORTE PTE /* Alias for PTE */
- #define PTE0 ((struct _hc08_bits *)(&PTE))->bit0
- #define PTE1 ((struct _hc08_bits *)(&PTE))->bit1
- #define PTE2 ((struct _hc08_bits *)(&PTE))->bit2
- #define PTE3 ((struct _hc08_bits *)(&PTE))->bit3
- #define PTE4 ((struct _hc08_bits *)(&PTE))->bit4
- #define PTE5 ((struct _hc08_bits *)(&PTE))->bit5
- #define PTE6 ((struct _hc08_bits *)(&PTE))->bit6
- #define PTE7 ((struct _hc08_bits *)(&PTE))->bit7
-
-VOLDATA UINT8 at 0x0C DDRE; /* Data Direction Register E */
- #define DDRE0 ((struct _hc08_bits *)(&DDRE))->bit0
- #define DDRE1 ((struct _hc08_bits *)(&DDRE))->bit1
- #define DDRE2 ((struct _hc08_bits *)(&DDRE))->bit2
- #define DDRE3 ((struct _hc08_bits *)(&DDRE))->bit3
- #define DDRE4 ((struct _hc08_bits *)(&DDRE))->bit4
- #define DDRE5 ((struct _hc08_bits *)(&DDRE))->bit5
- #define DDRE6 ((struct _hc08_bits *)(&DDRE))->bit6
- #define DDRE7 ((struct _hc08_bits *)(&DDRE))->bit7
-
-VOLDATA UINT8 at 0x0D PTAPUE; /* Port A pull-up enables */
- #define PTAPUE0 ((struct _hc08_bits *)(&PTAPUE))->bit0
- #define PTAPUE1 ((struct _hc08_bits *)(&PTAPUE))->bit1
- #define PTAPUE2 ((struct _hc08_bits *)(&PTAPUE))->bit2
- #define PTAPUE3 ((struct _hc08_bits *)(&PTAPUE))->bit3
- #define PTAPUE4 ((struct _hc08_bits *)(&PTAPUE))->bit4
- #define PTAPUE5 ((struct _hc08_bits *)(&PTAPUE))->bit5
- #define PTAPUE6 ((struct _hc08_bits *)(&PTAPUE))->bit6
- #define PTAPUE7 ((struct _hc08_bits *)(&PTAPUE))->bit7
-
-VOLDATA UINT8 at 0x0E PTCPUE; /* Port C pull-up enables */
- #define PTCPUE0 ((struct _hc08_bits *)(&PTCPUE))->bit0
- #define PTCPUE1 ((struct _hc08_bits *)(&PTCPUE))->bit1
- #define PTCPUE2 ((struct _hc08_bits *)(&PTCPUE))->bit2
- #define PTCPUE3 ((struct _hc08_bits *)(&PTCPUE))->bit3
- #define PTCPUE4 ((struct _hc08_bits *)(&PTCPUE))->bit4
- #define PTCPUE5 ((struct _hc08_bits *)(&PTCPUE))->bit5
- #define PTCPUE6 ((struct _hc08_bits *)(&PTCPUE))->bit6
- /* PTCPUE7 does not exit! */
-
-VOLDATA UINT8 at 0x0F PTDPUE; /* port D pull-up enables */
- #define PTDPUE0 ((struct _hc08_bits *)(&PTDPUE))->bit0
- #define PTDPUE1 ((struct _hc08_bits *)(&PTDPUE))->bit1
- #define PTDPUE2 ((struct _hc08_bits *)(&PTDPUE))->bit2
- #define PTDPUE3 ((struct _hc08_bits *)(&PTDPUE))->bit3
- #define PTDPUE4 ((struct _hc08_bits *)(&PTDPUE))->bit4
- #define PTDPUE5 ((struct _hc08_bits *)(&PTDPUE))->bit5
- #define PTDPUE6 ((struct _hc08_bits *)(&PTDPUE))->bit6
- #define PTDPUE7 ((struct _hc08_bits *)(&PTDPUE))->bit7
-
-VOLDATA UINT8 at 0x10 SPCR; /* SPI Control Register */
- #define SPRIE ((struct _hc08_bits *)(&SPCR))->bit7
- #define DMAS ((struct _hc08_bits *)(&SPCR))->bit6
- #define SPMSTR ((struct _hc08_bits *)(&SPCR))->bit5
- #define CPOL ((struct _hc08_bits *)(&SPCR))->bit4
- #define CPHA ((struct _hc08_bits *)(&SPCR))->bit3
- #define SPWOM ((struct _hc08_bits *)(&SPCR))->bit2
- #define SPE ((struct _hc08_bits *)(&SPCR))->bit1
- #define SPTIE ((struct _hc08_bits *)(&SPCR))->bit0
-
-VOLDATA UINT8 at 0x11 SPSCR; /* SPI Status and Control Register */
- #define SPRF ((struct _hc08_bits *)(&SPSCR))->bit7
- #define ERRIE ((struct _hc08_bits *)(&SPSCR))->bit6
- #define OVRF ((struct _hc08_bits *)(&SPSCR))->bit5
- #define MODF ((struct _hc08_bits *)(&SPSCR))->bit4
- #define SPTE ((struct _hc08_bits *)(&SPSCR))->bit3
- #define MODFEN ((struct _hc08_bits *)(&SPSCR))->bit2
- #define SPR1 ((struct _hc08_bits *)(&SPSCR))->bit1
- #define SPR0 ((struct _hc08_bits *)(&SPSCR))->bit0
-
-VOLDATA UINT8 at 0x12 SPDR; /* SPI Data Register */
-
-VOLDATA UINT8 at 0x13 SCC1; /* SCI Control Register 1 */
- #define LOOPS ((struct _hc08_bits *)(&SCC1))->bit7
- #define ENSCI ((struct _hc08_bits *)(&SCC1))->bit6
- #define TXINV ((struct _hc08_bits *)(&SCC1))->bit5
- #define M ((struct _hc08_bits *)(&SCC1))->bit4
- #define WAKE ((struct _hc08_bits *)(&SCC1))->bit3
- #define ILTY ((struct _hc08_bits *)(&SCC1))->bit2
- #define PEN ((struct _hc08_bits *)(&SCC1))->bit1
- #define PTY ((struct _hc08_bits *)(&SCC1))->bit0
-
-
-VOLDATA UINT8 at 0x14 SCC2; /* SCI Control Register 2 */
- #define SCTIE ((struct _hc08_bits *)(&SCC2))->bit7
- #define TCIE ((struct _hc08_bits *)(&SCC2))->bit6
- #define SCRIE ((struct _hc08_bits *)(&SCC2))->bit5
- #define ILIE ((struct _hc08_bits *)(&SCC2))->bit4
- #define TE ((struct _hc08_bits *)(&SCC2))->bit3
- #define RE ((struct _hc08_bits *)(&SCC2))->bit2
- #define WRU ((struct _hc08_bits *)(&SCC2))->bit1
- #define SBK ((struct _hc08_bits *)(&SCC2))->bit0
-
-VOLDATA UINT8 at 0x15 SCC3; /* SCI Control Register 3 */
- #define SCC3_R8 ((struct _hc08_bits *)(&SCC3))->bit7
- #define SCC3_TB ((struct _hc08_bits *)(&SCC3))->bit6
- #define DMARE ((struct _hc08_bits *)(&SCC3))->bit5
- #define DMATE ((struct _hc08_bits *)(&SCC3))->bit4
- #define ORIE ((struct _hc08_bits *)(&SCC3))->bit3
- #define NEIE ((struct _hc08_bits *)(&SCC3))->bit2
- #define FEIE ((struct _hc08_bits *)(&SCC3))->bit1
- #define PEIE ((struct _hc08_bits *)(&SCC3))->bit0
-
-VOLDATA UINT8 at 0x16 SCS1; /* SCI Status Register 1 */
- #define SCTE ((struct _hc08_bits *)(&SCS1))->bit7
- #define TC ((struct _hc08_bits *)(&SCS1))->bit6
- #define SCRF ((struct _hc08_bits *)(&SCS1))->bit5
- #define IDLE ((struct _hc08_bits *)(&SCS1))->bit4
- #define OR ((struct _hc08_bits *)(&SCS1))->bit3
- #define NF ((struct _hc08_bits *)(&SCS1))->bit2
- #define FE ((struct _hc08_bits *)(&SCS1))->bit1
- #define PE ((struct _hc08_bits *)(&SCS1))->bit0
-
-VOLDATA UINT8 at 0x17 SCS2; /* SCI Status Register 2 */
- #define RPF ((struct _hc08_bits *)(&SCS2))->bit0
- #define BKF ((struct _hc08_bits *)(&SCS2))->bit1
- /* Bits 2-7 not implemented */
-
-VOLDATA UINT8 at 0x18 SCDR; /* SCI Data Register */
-
-VOLDATA UINT8 at 0x19 SCBR; /* SCI Baud Rate Register */
- #define SCP1 ((struct _hc08_bits *)(&SCBR))->bit5
- #define SCP0 ((struct _hc08_bits *)(&SCBR))->bit4
- #define R ((struct _hc08_bits *)(&SCBR))->bit3
- #define SCR2 ((struct _hc08_bits *)(&SCBR))->bit2
- #define SCR1 ((struct _hc08_bits *)(&SCBR))->bit1
- #define SCR0 ((struct _hc08_bits *)(&SCBR))->bit0
- /*-- Bits 6 and 7 do not exist */
-
-VOLDATA UINT8 at 0x1a INTKBSCR; /* Keyboard Status and Control Register */
- #define KEYF ((struct _hc08_bits *)(&INTKBSCR))->bit3
- #define ACKK ((struct _hc08_bits *)(&INTKBSCR))->bit2
- #define IMASKK ((struct _hc08_bits *)(&INTKBSCR))->bit1
- #define MODEK ((struct _hc08_bits *)(&INTKBSCR))->bit0
- /*-- Bits 4-7 do not exist */
-
-VOLDATA UINT8 at 0x1b INTKBIER; /* Keyboard Interrupt Enable Register */
- #define KBIE7 ((struct _hc08_bits *)(&INTKBIER))->bit7
- #define KBIE6 ((struct _hc08_bits *)(&INTKBIER))->bit6
- #define KBIE5 ((struct _hc08_bits *)(&INTKBIER))->bit5
- #define KBIE4 ((struct _hc08_bits *)(&INTKBIER))->bit4
- #define KBIE3 ((struct _hc08_bits *)(&INTKBIER))->bit3
- #define KBIE2 ((struct _hc08_bits *)(&INTKBIER))->bit2
- #define KBIE1 ((struct _hc08_bits *)(&INTKBIER))->bit1
- #define KBIE0 ((struct _hc08_bits *)(&INTKBIER))->bit0
-
-VOLDATA UINT8 at 0x1C TBCR; /* Time Base Module Control */
- #define TBIF ((struct _hc08_bits *)(&TBCR))->bit7
- #define TBR2 ((struct _hc08_bits *)(&TBCR))->bit6
- #define TBR1 ((struct _hc08_bits *)(&TBCR))->bit5
- #define TBR0 ((struct _hc08_bits *)(&TBCR))->bit4
- #define TACK ((struct _hc08_bits *)(&TBCR))->bit3
- #define TBIE ((struct _hc08_bits *)(&TBCR))->bit2
- #define TBON ((struct _hc08_bits *)(&TBCR))->bit1
- /* Bit 0 Reserved */
-
-VOLDATA UINT8 at 0x1D INTSCR; /* IRQ status/control */
- #define IRQF1 ((struct _hc08_bits *)(&INTSCR))->bit3
- #define ACK1 ((struct _hc08_bits *)(&INTSCR))->bit2
- #define IMASK1 ((struct _hc08_bits *)(&INTSCR))->bit1
- #define MODE1 ((struct _hc08_bits *)(&INTSCR))->bit0
- /* Bits 4-7 unimplemented */
-
-VOLDATA UINT8 at 0x1e CONFIG2; /* Configuration Register 2 */
-/* CONFIG2 is one-time writeble, so can't use bitfields */
-
-VOLDATA UINT8 at 0x1f CONFIG1; /* Configuration Register 1 */
-/* CONFIG1 is one-time writeable, so can't use bitfields */
-
-VOLDATA UINT8 at 0x20 T1SC; /* TIM 1 Status and Control */
- #define PS0 ((struct _hc08_bits *)(&T1SC))->bit0
- #define PS1 ((struct _hc08_bits *)(&T1SC))->bit1
- #define PS2 ((struct _hc08_bits *)(&T1SC))->bit2
- #define TRST ((struct _hc08_bits *)(&T1SC))->bit4
- #define TSTOP ((struct _hc08_bits *)(&T1SC))->bit5
- #define TOIE ((struct _hc08_bits *)(&T1SC))->bit6
- #define TOF ((struct _hc08_bits *)(&T1SC))->bit7
-
-VOLDATA UINT16 at 0x21 T1CNT; /* TIM1 Counter High & Low Registers */
-VOLDATA UINT8 at 0x21 T1CNTH; /* TIM1 Counter Register High */
-VOLDATA UINT8 at 0x22 T1CNTL; /* TIM1 Counter Register Low */
-
-VOLDATA UINT16 at 0x23 T1MOD; /* TIM1 Counter Modulo High & Low Registers */
-VOLDATA UINT8 at 0x23 T1MODH; /* TIM1 Counter Modulo Register High */
-VOLDATA UINT8 at 0x24 T1MODL; /* TIM1 Counter Modulo Register Low */
-
-VOLDATA UINT8 at 0x25 T1SC0; /* TIM1 Channel 0 Status and Control Register */
- #define CH0MAX ((struct _hc08_bits *)(&T1SC0))->bit0
- #define TOV0 ((struct _hc08_bits *)(&T1SC0))->bit1
- #define ELS0A ((struct _hc08_bits *)(&T1SC0))->bit2
- #define ELS0B ((struct _hc08_bits *)(&T1SC0))->bit3
- #define MS0A ((struct _hc08_bits *)(&T1SC0))->bit4
- #define MS0B ((struct _hc08_bits *)(&T1SC0))->bit5
- #define CH0IE ((struct _hc08_bits *)(&T1SC0))->bit6
- #define CH0F ((struct _hc08_bits *)(&T1SC0))->bit7
-
-VOLDATA UINT16 at 0x26 T1CH0; /* TIM1 Channel 0 High & Low Registers */
-VOLDATA UINT8 at 0x26 T1CH0H; /* TIM1 Channel 0 Register High */
-VOLDATA UINT8 at 0x27 T1CH0L; /* TIM1 Channel 0 Register Low */
-
-VOLDATA UINT8 at 0x28 T1SC1; /* TIM1 Channel 1 Status and Control Register */
- #define CH1MAX ((struct _hc08_bits *)(&T1SC1))->bit0
- #define TOV1 ((struct _hc08_bits *)(&T1SC1))->bit1
- #define ELS1A ((struct _hc08_bits *)(&T1SC1))->bit2
- #define ELS1B ((struct _hc08_bits *)(&T1SC1))->bit3
- #define MS1A ((struct _hc08_bits *)(&T1SC1))->bit4
- #define CH1IE ((struct _hc08_bits *)(&T1SC1))->bit6
- #define CH1F ((struct _hc08_bits *)(&T1SC1))->bit7
-
-VOLDATA UINT16 at 0x29 T1CH1; /* TIM1 Channel 1 High & Low Registers */
-VOLDATA UINT8 at 0x29 T1CH1H; /* TIM1 Channel 1 Register High */
-VOLDATA UINT8 at 0x2A T1CH1L; /* TIM1 Channel 1 Register Low */
-
-/*------------------*/
-/* TIM 2 REGISTERS */
-/*------------------*/
-
-VOLDATA UINT8 at 0x2B T2SC; /* TIM 2 Status and Control */
- #define PS0_2 ((struct _hc08_bits *)(&T2SC))->bit0
- #define PS1_2 ((struct _hc08_bits *)(&T2SC))->bit1
- #define PS2_2 ((struct _hc08_bits *)(&T2SC))->bit2
- #define TRST_2 ((struct _hc08_bits *)(&T2SC))->bit4
- #define TSTOP_2 ((struct _hc08_bits *)(&T2SC))->bit5
- #define TOIE_2 ((struct _hc08_bits *)(&T2SC))->bit6
- #define TOF_2 ((struct _hc08_bits *)(&T2SC))->bit7
-
-VOLDATA UINT16 at 0x2C T2CNT; /* TIM2 Counter High & Low Registers */
-VOLDATA UINT8 at 0x2C T2CNTH; /* TIM2 Counter Register High */
-VOLDATA UINT8 at 0x2D T2CNTL; /* TIM2 Counter Register Low */
-
-VOLDATA UINT16 at 0x2E T2MOD; /* TIM2 Counter Modulo High & Low Registers */
-VOLDATA UINT8 at 0x2E T2MODH; /* TIM2 Counter Modulo Register High */
-VOLDATA UINT8 at 0x2F T2MODL; /* TIM2 Counter Modulo Register Low */
-
-VOLDATA UINT8 at 0x30 T2SC0; /* TIM2 Channel 0 Status and Control Register */
- #define CH0MAX_2 ((struct _hc08_bits *)(&T2SC0))->bit0
- #define TOV0_2 ((struct _hc08_bits *)(&T2SC0))->bit1
- #define ELS0A_2 ((struct _hc08_bits *)(&T2SC0))->bit2
- #define ELS0B_2 ((struct _hc08_bits *)(&T2SC0))->bit3
- #define MS0A_2 ((struct _hc08_bits *)(&T2SC0))->bit4
- #define MS0B_2 ((struct _hc08_bits *)(&T2SC0))->bit5
- #define CH0IE_2 ((struct _hc08_bits *)(&T2SC0))->bit6
- #define CH0F_2 ((struct _hc08_bits *)(&T2SC0))->bit7
-
-VOLDATA UINT16 at 0x31 T2CH0; /* TIM2 Channel 0 High & Low Registers */
-VOLDATA UINT8 at 0x31 T2CH0H; /* TIM2 Channel 0 Register High */
-VOLDATA UINT8 at 0x32 T2CH0L; /* TIM2 Channel 0 Register Low */
-
-VOLDATA UINT8 at 0x33 T2SC1; /* TIM2 Channel 1 Status and Control Register */
- #define CH1MAX_2 ((struct _hc08_bits *)(&T2SC1))->bit0
- #define TOV1_2 ((struct _hc08_bits *)(&T2SC1))->bit1
- #define ELS1A_2 ((struct _hc08_bits *)(&T2SC1))->bit2
- #define ELS1B_2 ((struct _hc08_bits *)(&T2SC1))->bit3
- #define MS1A_2 ((struct _hc08_bits *)(&T2SC1))->bit4
- #define CH1IE_2 ((struct _hc08_bits *)(&T2SC1))->bit6
- #define CH1F_2 ((struct _hc08_bits *)(&T2SC1))->bit7
-
-VOLDATA UINT16 at 0x34 T2CH1; /* TIM2 Channel 1 High & Low Registers */
-VOLDATA UINT8 at 0x34 T2CH1H; /* TIM2 Channel 1 Register High */
-VOLDATA UINT8 at 0x35 T2CH1L; /* TIM2 Channel 1 Register Low */
-
-VOLDATA UINT8 at 0x36 PCTL; /* PLL Control Register */
- #define PLLIE ((struct _hc08_bits *)(&PCTL))->bit7
- #define PLLF ((struct _hc08_bits *)(&PCTL))->bit6
- #define PLLON ((struct _hc08_bits *)(&PCTL))->bit5
- #define BCS ((struct _hc08_bits *)(&PCTL))->bit4
- #define PRE1 ((struct _hc08_bits *)(&PCTL))->bit3
- #define PRE0 ((struct _hc08_bits *)(&PCTL))->bit2
- #define VPR1 ((struct _hc08_bits *)(&PCTL))->bit1
- #define VPR0 ((struct _hc08_bits *)(&PCTL))->bit0
-
-VOLDATA UINT8 at 0x37 PBWC; /* PLL Bandwidth Control Register */
- #define AUTO ((struct _hc08_bits *)(&PBWC))->bit7
- #define LOCK ((struct _hc08_bits *)(&PBWC))->bit6
- #define ACQ ((struct _hc08_bits *)(&PBWC))->bit5
- /* Bits 1-4, Unimplemented */
- /* Bit 0, Reserved */
-
-VOLDATA UINT8 at 0x38 PMSH; /* PLL Multiplier Select High */
- #define MUL11 ((struct _hc08_bits *)(&PMSH))->bit3
- #define MUL10 ((struct _hc08_bits *)(&PMSH))->bit2
- #define MUL9 ((struct _hc08_bits *)(&PMSH))->bit1
- #define MUL8 ((struct _hc08_bits *)(&PMSH))->bit0
- /* Bits 4-7 unimplemented */
-
-VOLDATA UINT8 at 0x39 PMSL; /* PLL Multiplir Select Low */
- #define MUL7 ((struct _hc08_bits *)(&PMSL))->bit7
- #define MUL6 ((struct _hc08_bits *)(&PMSL))->bit6
- #define MUL5 ((struct _hc08_bits *)(&PMSL))->bit5
- #define MUL4 ((struct _hc08_bits *)(&PMSL))->bit4
- #define MUL3 ((struct _hc08_bits *)(&PMSL))->bit3
- #define MUL2 ((struct _hc08_bits *)(&PMSL))->bit2
- #define MUL1 ((struct _hc08_bits *)(&PMSL))->bit1
- #define MUL0 ((struct _hc08_bits *)(&PMSL))->bit0
-
-VOLDATA UINT8 at 0x3a PMRS; /* PLL VCO Select Range */
- #define VRS7 ((struct _hc08_bits *)(&PMRS))->bit7
- #define VRS6 ((struct _hc08_bits *)(&PMRS))->bit6
- #define VRS5 ((struct _hc08_bits *)(&PMRS))->bit5
- #define VRS4 ((struct _hc08_bits *)(&PMRS))->bit4
- #define VRS3 ((struct _hc08_bits *)(&PMRS))->bit3
- #define VRS2 ((struct _hc08_bits *)(&PMRS))->bit2
- #define VRS1 ((struct _hc08_bits *)(&PMRS))->bit1
- #define VRS0 ((struct _hc08_bits *)(&PMRS))->bit0
-
-VOLDATA UINT8 at 0x3b PMDS; /* PLL Reference Divider Select Register */
- #define RDS3 ((struct _hc08_bits *)(&PMDS))->bit3
- #define RDS2 ((struct _hc08_bits *)(&PMDS))->bit2
- #define RDS1 ((struct _hc08_bits *)(&PMDS))->bit1
- #define RDS0 ((struct _hc08_bits *)(&PMDS))->bit0
- /* Bits 4-7 unimplemented */
-
-VOLDATA UINT8 at 0x3c ADSCR; /* Analog-to-Digital Status and Control Reg. */
- #define COCO ((struct _hc08_bits *)(&ADSCR))->bit7
- #define AIEN ((struct _hc08_bits *)(&ADSCR))->bit6
- #define ADCO ((struct _hc08_bits *)(&ADSCR))->bit5
- #define ADCH4 ((struct _hc08_bits *)(&ADSCR))->bit4
- #define ADCH3 ((struct _hc08_bits *)(&ADSCR))->bit3
- #define ADCH2 ((struct _hc08_bits *)(&ADSCR))->bit2
- #define ADCH1 ((struct _hc08_bits *)(&ADSCR))->bit1
- #define ADCH0 ((struct _hc08_bits *)(&ADSCR))->bit0
-
-VOLDATA UINT8 at 0x3d ADR; /* Analog-to-Digital Data Register */
-
-VOLDATA UINT8 at 0x3e ADCLK; /* Analog-to-Digital Clock */
- #define ADIV2 ((struct _hc08_bits *)(&ADCLK))->bit7
- #define ADIV1 ((struct _hc08_bits *)(&ADCLK))->bit6
- #define ADIV0 ((struct _hc08_bits *)(&ADCLK))->bit5
- #define ADICLK ((struct _hc08_bits *)(&ADCLK))->bit4
- /* Bits 0-3 unimplemented */
-
-VOLXDATA UINT8 at 0xfe00 SBSR; /* SIM Break Status Register */
- #define SBSW ((struct _hc08_bits *)(&SBSR))->bit1
-
-VOLXDATA UINT8 at 0xfe01 SRSR; /* SIM Reset Status Register */
- #define LVI ((struct _hc08_bits *)(&SRSR))->bit1
- #define MODRST ((struct _hc08_bits *)(&SRSR))->bit2
- #define ILAD ((struct _hc08_bits *)(&SRSR))->bit3
- #define ILOP ((struct _hc08_bits *)(&SRSR))->bit4
- #define COP ((struct _hc08_bits *)(&SRSR))->bit5
- #define PIN ((struct _hc08_bits *)(&SRSR))->bit6
- #define POR ((struct _hc08_bits *)(&SRSR))->bit7
- /* Bit 0 unimplemented */
-
-VOLXDATA UINT8 at 0xfe02 SUBAR; /* SIM Upper Byte Address */
-
-VOLXDATA UINT8 at 0xfe03 SBFCR; /* SIM Break Flag Control Register */
- #define BFCE ((struct _hc08_bits *)(&BFCR))->bit7
-
-VOLXDATA UINT8 at 0xfe04 INT1; /* Interrupt Status Register 1 */
- #define IF1 ((struct _hc08_bits *)(&INT1))->bit2
- #define IF2 ((struct _hc08_bits *)(&INT1))->bit3
- #define IF3 ((struct _hc08_bits *)(&INT1))->bit4
- #define IF4 ((struct _hc08_bits *)(&INT1))->bit5
- #define IF5 ((struct _hc08_bits *)(&INT1))->bit6
- #define IF6 ((struct _hc08_bits *)(&INT1))->bit7
- /* Bits 0-1 Reserved */
-
-VOLXDATA UINT8 at 0xfe05 INT2; /* Interrupt Status Register 2 */
- #define IF14 ((struct _hc08_bits *)(&INT2))->bit7
- #define IF13 ((struct _hc08_bits *)(&INT2))->bit6
- #define IF12 ((struct _hc08_bits *)(&INT2))->bit5
- #define IF11 ((struct _hc08_bits *)(&INT2))->bit4
- #define IF10 ((struct _hc08_bits *)(&INT2))->bit3
- #define IF9 ((struct _hc08_bits *)(&INT2))->bit2
- #define IF8 ((struct _hc08_bits *)(&INT2))->bit1
- #define IF7 ((struct _hc08_bits *)(&INT2))->bit0
-
-VOLXDATA UINT8 at 0xfe06 INT3; /* Interrupt Status Register 3 */
- #define IF16 ((struct _hc08_bits *)(&INT3))->bit1
- #define IF15 ((struct _hc08_bits *)(&INT3))->bit0
-
-VOLXDATA UINT8 at 0xfe07 FLCTR; /* Flash test/programming */
-
-VOLXDATA UINT8 at 0xfe08 FLCR; /* FLASH Control Register */
- #define PGM ((struct _hc08_bits *)(&FLCR))->bit0
- #define ERASE ((struct _hc08_bits *)(&FLCR))->bit1
- #define MASS ((struct _hc08_bits *)(&FLCR))->bit2
- #define HVEN ((struct _hc08_bits *)(&FLCR))->bit3
-
-VOLXDATA UINT16 at 0xfe09 BRK; /* Break Address High & Low Registers */
-VOLXDATA UINT8 at 0xfe09 BRKH; /* Break Address High Register */
-VOLXDATA UINT8 at 0xfe0a BRKL; /* Break Address Low Register */
-
-VOLXDATA UINT8 at 0xfe0b BRKSCR; /* Break Status and Control Register */
- #define BRKA ((struct _hc08_bits *)(&BRKSCR))->bit6
- #define BRKE ((struct _hc08_bits *)(&BRKSCR))->bit7
-
-VOLXDATA UINT8 at 0xfe0c LVISR; /* Low voltage detect */
- #define LVIOUT ((struct _hc08_bits *)(&LVISR))->bit7
-
-
-VOLXDATA UINT8 at 0xfe7e FLBPR; /* FLASH Block Protect Register */
- #define BPR0 ((struct _hc08_bits *)(&FLBPR))->bit0
- #define BPR1 ((struct _hc08_bits *)(&FLBPR))->bit1
- #define BPR2 ((struct _hc08_bits *)(&FLBPR))->bit2
- #define BPR3 ((struct _hc08_bits *)(&FLBPR))->bit3
- #define BPR4 ((struct _hc08_bits *)(&FLBPR))->bit4
- #define BPR5 ((struct _hc08_bits *)(&FLBPR))->bit5
- #define BPR6 ((struct _hc08_bits *)(&FLBPR))->bit6
- #define BPR7 ((struct _hc08_bits *)(&FLBPR))->bit7
-
-VOLXDATA UINT8 at 0xffff COPCTL; /* COP Control Register */
-
-#endif
+++ /dev/null
-/*-------------------------------------------------------------------------
- Register Declarations for Motorola MC68HC908JB8
-
- Copyright (c) 2004, Bjorn Bringert <bjorn@bringert.net>
-
- Based on mc68hc908qy.h,
- Written By - Erik Petrich
- epetrich@users.sourceforge.net (2003)
-
- This program is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published by the
- Free Software Foundation; either version 2, or (at your option) any
- later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
- In other words, you are welcome to use, share and improve this program.
- You are forbidden to forbid anyone else to use, share and improve
- what you give them. Help stamp out software-hoarding!
--------------------------------------------------------------------------*/
-
-#ifndef MC68HC908JB8_H
-#define MC68HC908JB8_H
-
-#ifndef UINT8
- #define UINT8 unsigned char
-#endif
-#ifndef UINT16
- #define UINT16 unsigned int
-#endif
-#ifndef VOLDATA
- #define VOLDATA volatile data
-#endif
-#ifndef VOLXDATA
- #define VOLXDATA volatile xdata
-#endif
-
-struct _hc08_bits
-{
- unsigned int bit0:1;
- unsigned int bit1:1;
- unsigned int bit2:1;
- unsigned int bit3:1;
- unsigned int bit4:1;
- unsigned int bit5:1;
- unsigned int bit6:1;
- unsigned int bit7:1;
-};
-
-
-VOLDATA UINT8 at 0x00 PTA; /* Port A Data Register */
- #define PTA0 ((struct _hc08_bits *)(&PTA))->bit0
- #define PTA1 ((struct _hc08_bits *)(&PTA))->bit1
- #define PTA2 ((struct _hc08_bits *)(&PTA))->bit2
- #define PTA3 ((struct _hc08_bits *)(&PTA))->bit3
- #define PTA4 ((struct _hc08_bits *)(&PTA))->bit4
- #define PTA5 ((struct _hc08_bits *)(&PTA))->bit5
- #define AWUL ((struct _hc08_bits *)(&PTA))->bit6
-
-VOLDATA UINT8 at 0x01 PTB; /* Port B Data Register */
- #define PTB0 ((struct _hc08_bits *)(&PTB))->bit0
- #define PTB1 ((struct _hc08_bits *)(&PTB))->bit1
- #define PTB2 ((struct _hc08_bits *)(&PTB))->bit2
- #define PTB3 ((struct _hc08_bits *)(&PTB))->bit3
- #define PTB4 ((struct _hc08_bits *)(&PTB))->bit4
- #define PTB5 ((struct _hc08_bits *)(&PTB))->bit5
- #define PTB6 ((struct _hc08_bits *)(&PTB))->bit6
- #define PTB7 ((struct _hc08_bits *)(&PTB))->bit7
-
-VOLDATA UINT8 at 0x02 PTC; /* Port C Data Register */
- #define PTC0 ((struct _hc08_bits *)(&PTC))->bit0
- #define PTC1 ((struct _hc08_bits *)(&PTC))->bit1
- #define PTC2 ((struct _hc08_bits *)(&PTC))->bit2
- #define PTC3 ((struct _hc08_bits *)(&PTC))->bit3
- #define PTC4 ((struct _hc08_bits *)(&PTC))->bit4
- #define PTC5 ((struct _hc08_bits *)(&PTC))->bit5
- #define PTC6 ((struct _hc08_bits *)(&PTC))->bit6
- #define PTC7 ((struct _hc08_bits *)(&PTC))->bit7
-
-VOLDATA UINT8 at 0x03 PTD; /* Port D Data Register */
- #define PTD0 ((struct _hc08_bits *)(&PTD))->bit0
- #define PTD1 ((struct _hc08_bits *)(&PTD))->bit1
- #define PTD2 ((struct _hc08_bits *)(&PTD))->bit2
- #define PTD3 ((struct _hc08_bits *)(&PTD))->bit3
- #define PTD4 ((struct _hc08_bits *)(&PTD))->bit4
- #define PTD5 ((struct _hc08_bits *)(&PTD))->bit5
- #define PTD6 ((struct _hc08_bits *)(&PTD))->bit6
- #define PTD7 ((struct _hc08_bits *)(&PTD))->bit7
-
-VOLDATA UINT8 at 0x04 DDRA; /* Data Direction Register A */
- #define DDRA0 ((struct _hc08_bits *)(&DDRA))->bit0
- #define DDRA1 ((struct _hc08_bits *)(&DDRA))->bit1
- #define DDRA2 ((struct _hc08_bits *)(&DDRA))->bit2
- #define DDRA3 ((struct _hc08_bits *)(&DDRA))->bit3
- #define DDRA4 ((struct _hc08_bits *)(&DDRA))->bit4
- #define DDRA5 ((struct _hc08_bits *)(&DDRA))->bit5
- #define DDRA6 ((struct _hc08_bits *)(&DDRA))->bit6
- #define DDRA7 ((struct _hc08_bits *)(&DDRA))->bit7
-
-VOLDATA UINT8 at 0x05 DDRB; /* Data Direction Register B */
- #define DDRB0 ((struct _hc08_bits *)(&DDRB))->bit0
- #define DDRB1 ((struct _hc08_bits *)(&DDRB))->bit1
- #define DDRB2 ((struct _hc08_bits *)(&DDRB))->bit2
- #define DDRB3 ((struct _hc08_bits *)(&DDRB))->bit3
- #define DDRB4 ((struct _hc08_bits *)(&DDRB))->bit4
- #define DDRB5 ((struct _hc08_bits *)(&DDRB))->bit5
- #define DDRB6 ((struct _hc08_bits *)(&DDRB))->bit6
- #define DDRB7 ((struct _hc08_bits *)(&DDRB))->bit7
-
-VOLDATA UINT8 at 0x06 DDRC; /* Data Direction Register C */
- #define DDRC0 ((struct _hc08_bits *)(&DDRC))->bit0
- #define DDRC1 ((struct _hc08_bits *)(&DDRC))->bit1
- #define DDRC2 ((struct _hc08_bits *)(&DDRC))->bit2
- #define DDRC3 ((struct _hc08_bits *)(&DDRC))->bit3
- #define DDRC4 ((struct _hc08_bits *)(&DDRC))->bit4
- #define DDRC5 ((struct _hc08_bits *)(&DDRC))->bit5
- #define DDRC6 ((struct _hc08_bits *)(&DDRC))->bit6
- #define DDRC7 ((struct _hc08_bits *)(&DDRC))->bit7
-
-VOLDATA UINT8 at 0x07 DDRD; /* Data Direction Register D */
- #define DDRD0 ((struct _hc08_bits *)(&DDRD))->bit0
- #define DDRD1 ((struct _hc08_bits *)(&DDRD))->bit1
- #define DDRD2 ((struct _hc08_bits *)(&DDRD))->bit2
- #define DDRD3 ((struct _hc08_bits *)(&DDRD))->bit3
- #define DDRD4 ((struct _hc08_bits *)(&DDRD))->bit4
- #define DDRD5 ((struct _hc08_bits *)(&DDRD))->bit5
- #define DDRD6 ((struct _hc08_bits *)(&DDRD))->bit6
- #define DDRD7 ((struct _hc08_bits *)(&DDRD))->bit7
-
-VOLDATA UINT8 at 0x08 PTE; /* Port E Data Register */
- #define PTE0 ((struct _hc08_bits *)(&PTE))->bit0
- #define PTE1 ((struct _hc08_bits *)(&PTE))->bit1
- #define PTE2 ((struct _hc08_bits *)(&PTE))->bit2
- #define PTE3 ((struct _hc08_bits *)(&PTE))->bit3
- #define PTE4 ((struct _hc08_bits *)(&PTE))->bit4
- #define PTE5 ((struct _hc08_bits *)(&PTE))->bit5
- #define PTE6 ((struct _hc08_bits *)(&PTE))->bit6
- #define PTE7 ((struct _hc08_bits *)(&PTE))->bit7
-
-VOLDATA UINT8 at 0x09 DDRE; /* Data Direction Register E */
- #define DDRE0 ((struct _hc08_bits *)(&DDRE))->bit0
- #define DDRE1 ((struct _hc08_bits *)(&DDRE))->bit1
- #define DDRE2 ((struct _hc08_bits *)(&DDRE))->bit2
- #define DDRE3 ((struct _hc08_bits *)(&DDRE))->bit3
- #define DDRE4 ((struct _hc08_bits *)(&DDRE))->bit4
- #define DDRE5 ((struct _hc08_bits *)(&DDRE))->bit5
- #define DDRE6 ((struct _hc08_bits *)(&DDRE))->bit6
- #define DDRE7 ((struct _hc08_bits *)(&DDRE))->bit7
-
-VOLDATA UINT8 at 0x0a TSC; /* TIM Status and Control */
- #define PS0 ((struct _hc08_bits *)(&TSC))->bit0
- #define PS1 ((struct _hc08_bits *)(&TSC))->bit1
- #define PS2 ((struct _hc08_bits *)(&TSC))->bit2
- #define TRST ((struct _hc08_bits *)(&TSC))->bit4
- #define TSTOP ((struct _hc08_bits *)(&TSC))->bit5
- #define TOIE ((struct _hc08_bits *)(&TSC))->bit6
- #define TOF ((struct _hc08_bits *)(&TSC))->bit7
-
-VOLDATA UINT16 at 0x0c TCNT; /* TIM Counter High & Low Registers */
-VOLDATA UINT8 at 0x0c TCNTH; /* TIM Counter Register High */
-VOLDATA UINT8 at 0x0d TCNTL; /* TIM Counter Register Low */
-
-VOLDATA UINT16 at 0x0e TMOD; /* TIM Counter Modulo High & Low Registers */
-VOLDATA UINT8 at 0x0e TMODH; /* TIM Counter Modulo Register High */
-VOLDATA UINT8 at 0x0f TMODL; /* TIM Counter Modulo Register Low */
-
-VOLDATA UINT8 at 0x10 TSC0; /* TIM Channel 0 Status and Control Register */
- #define CH0MAX ((struct _hc08_bits *)(&TSC0))->bit0
- #define TOV0 ((struct _hc08_bits *)(&TSC0))->bit1
- #define ELS0A ((struct _hc08_bits *)(&TSC0))->bit2
- #define ELS0B ((struct _hc08_bits *)(&TSC0))->bit3
- #define MS0A ((struct _hc08_bits *)(&TSC0))->bit4
- #define MS0B ((struct _hc08_bits *)(&TSC0))->bit5
- #define CH0IE ((struct _hc08_bits *)(&TSC0))->bit6
- #define CH0F ((struct _hc08_bits *)(&TSC0))->bit7
-
-VOLDATA UINT16 at 0x11 TCH0; /* TIM Channel 0 High & Low Registers */
-VOLDATA UINT8 at 0x11 TCH0H; /* TIM Channel 0 Register High */
-VOLDATA UINT8 at 0x12 TCH0L; /* TIM Channel 0 Register Low */
-
-VOLDATA UINT8 at 0x13 TSC1; /* TIM Channel 1 Status and Control Register */
- #define CH1MAX ((struct _hc08_bits *)(&TSC1))->bit0
- #define TOV1 ((struct _hc08_bits *)(&TSC1))->bit1
- #define ELS1A ((struct _hc08_bits *)(&TSC1))->bit2
- #define ELS1B ((struct _hc08_bits *)(&TSC1))->bit3
- #define MS1A ((struct _hc08_bits *)(&TSC1))->bit4
- #define CH1IE ((struct _hc08_bits *)(&TSC1))->bit6
- #define CH1F ((struct _hc08_bits *)(&TSC1))->bit7
-
-VOLDATA UINT16 at 0x14 TCH1; /* TIM Channel 1 High & Low Registers */
-VOLDATA UINT8 at 0x14 TCH1H; /* TIM Channel 1 Register High */
-VOLDATA UINT8 at 0x15 TCH1L; /* TIM Channel 1 Register Low */
-
-VOLDATA UINT8 at 0x16 KBSCR; /* Keyboard Status and Control Register */
- #define MODEK ((struct _hc08_bits *)(&KBSCR))->bit0
- #define IMASKK ((struct _hc08_bits *)(&KBSCR))->bit1
- #define ACKK ((struct _hc08_bits *)(&KBSCR))->bit2
- #define KEYF ((struct _hc08_bits *)(&KBSCR))->bit3
-
-VOLDATA UINT8 at 0x17 KBIER; /* Keyboard Interrupt Enable Register */
- #define KBIE0 ((struct _hc08_bits *)(&KBIER))->bit0
- #define KBIE1 ((struct _hc08_bits *)(&KBIER))->bit1
- #define KBIE2 ((struct _hc08_bits *)(&KBIER))->bit2
- #define KBIE3 ((struct _hc08_bits *)(&KBIER))->bit3
- #define KBIE4 ((struct _hc08_bits *)(&KBIER))->bit4
- #define KBIE5 ((struct _hc08_bits *)(&KBIER))->bit5
- #define KBIE6 ((struct _hc08_bits *)(&KBIER))->bit6
- #define KBIE7 ((struct _hc08_bits *)(&KBIER))->bit7
-
-VOLDATA UINT8 at 0x18 UIR2; /* USB Interrupt Register 2 */
- #define RXD0FR ((struct _hc08_bits *)(&UIR2))->bit0
- #define TXD0FR ((struct _hc08_bits *)(&UIR2))->bit1
- #define RESUMFR ((struct _hc08_bits *)(&UIR2))->bit2
- #define TXD1FR ((struct _hc08_bits *)(&UIR2))->bit3
- #define RXD2FR ((struct _hc08_bits *)(&UIR2))->bit4
- #define TXD2FR ((struct _hc08_bits *)(&UIR2))->bit5
- #define RSTFR ((struct _hc08_bits *)(&UIR2))->bit6
- #define EOPFR ((struct _hc08_bits *)(&UIR2))->bit7
-
-VOLDATA UINT8 at 0x19 UCR2; /* USB Control Register 2 */
- #define TP2SIZ0 ((struct _hc08_bits *)(&UCR2))->bit0
- #define TP2SIZ1 ((struct _hc08_bits *)(&UCR2))->bit1
- #define TP2SIZ2 ((struct _hc08_bits *)(&UCR2))->bit2
- #define TP2SIZ3 ((struct _hc08_bits *)(&UCR2))->bit3
- #define RX2E ((struct _hc08_bits *)(&UCR2))->bit4
- #define TX2E ((struct _hc08_bits *)(&UCR2))->bit5
- #define STALL2 ((struct _hc08_bits *)(&UCR2))->bit6
- #define T2SEQ ((struct _hc08_bits *)(&UCR2))->bit7
-
-VOLDATA UINT8 at 0x1a UCR3; /* USB Control Register 3 */
- #define ENABLE1 ((struct _hc08_bits *)(&UCR3))->bit0
- #define ENABLE2 ((struct _hc08_bits *)(&UCR3))->bit1
- #define PULLEN ((struct _hc08_bits *)(&UCR3))->bit2
- #define ISTALL0 ((struct _hc08_bits *)(&UCR3))->bit4
- #define OSTALL0 ((struct _hc08_bits *)(&UCR3))->bit5
- #define TX1STR ((struct _hc08_bits *)(&UCR3))->bit6
- #define TX1ST ((struct _hc08_bits *)(&UCR3))->bit7
-
-VOLDATA UINT8 at 0x1b UCR4; /* USB Control Register 4 */
- #define FDM ((struct _hc08_bits *)(&UCR4))->bit0
- #define FDP ((struct _hc08_bits *)(&UCR4))->bit1
- #define FUSB0 ((struct _hc08_bits *)(&UCR4))->bit2
-
-VOLDATA UINT8 at 0x1c IOCR; /* IRQ Option Control Register */
- #define IRQPD ((struct _hc08_bits *)(&IOCR))->bit0
- #define PTE4IE ((struct _hc08_bits *)(&IOCR))->bit1
- #define PTE4IF ((struct _hc08_bits *)(&IOCR))->bit2
-
-VOLDATA UINT8 at 0x1d POCR; /* Port Option Control Register */
- #define PAP ((struct _hc08_bits *)(&POCR))->bit0
- #define PBP ((struct _hc08_bits *)(&POCR))->bit1
- #define PCP ((struct _hc08_bits *)(&POCR))->bit2
- #define PTE3P ((struct _hc08_bits *)(&POCR))->bit3
- #define PTE4P ((struct _hc08_bits *)(&POCR))->bit4
- #define PTDILDD ((struct _hc08_bits *)(&POCR))->bit5
- #define PTDLDD ((struct _hc08_bits *)(&POCR))->bit6
- #define PTE20P ((struct _hc08_bits *)(&POCR))->bit7
-
-VOLDATA UINT8 at 0x1e ISCR; /* IRQ Status and Control Register */
- #define MODE ((struct _hc08_bits *)(&ISCR))->bit0
- #define IMASK ((struct _hc08_bits *)(&ISCR))->bit1
- #define ACK ((struct _hc08_bits *)(&ISCR))->bit2
- #define IRQF ((struct _hc08_bits *)(&ISCR))->bit3
-
-VOLDATA UINT8 at 0x1f CONFIG; /* Configuration Register 1 */
-/* CONFIG1 is one-time writeable, so can't use bitfields */
-
-VOLDATA UINT8 at 0x20 UE0D0; /* USB Endpoint 0 Data Register 0 */
-VOLDATA UINT8 at 0x21 UE0D1; /* USB Endpoint 0 Data Register 1 */
-VOLDATA UINT8 at 0x22 UE0D2; /* USB Endpoint 0 Data Register 2 */
-VOLDATA UINT8 at 0x23 UE0D3; /* USB Endpoint 0 Data Register 3 */
-VOLDATA UINT8 at 0x24 UE0D4; /* USB Endpoint 0 Data Register 4 */
-VOLDATA UINT8 at 0x25 UE0D5; /* USB Endpoint 0 Data Register 5 */
-VOLDATA UINT8 at 0x26 UE0D6; /* USB Endpoint 0 Data Register 6 */
-VOLDATA UINT8 at 0x27 UE0D7; /* USB Endpoint 0 Data Register 7 */
-
-VOLDATA UINT8 at 0x28 UE1D0; /* USB Endpoint 1 Data Register 0 */
-VOLDATA UINT8 at 0x29 UE1D1; /* USB Endpoint 1 Data Register 1 */
-VOLDATA UINT8 at 0x2a UE1D2; /* USB Endpoint 1 Data Register 2 */
-VOLDATA UINT8 at 0x2b UE1D3; /* USB Endpoint 1 Data Register 3 */
-VOLDATA UINT8 at 0x2c UE1D4; /* USB Endpoint 1 Data Register 4 */
-VOLDATA UINT8 at 0x2d UE1D5; /* USB Endpoint 1 Data Register 5 */
-VOLDATA UINT8 at 0x2e UE1D6; /* USB Endpoint 1 Data Register 6 */
-VOLDATA UINT8 at 0x2f UE1D7; /* USB Endpoint 1 Data Register 7 */
-
-VOLDATA UINT8 at 0x30 UE2D0; /* USB Endpoint 2 Data Register 0 */
-VOLDATA UINT8 at 0x31 UE2D1; /* USB Endpoint 2 Data Register 1 */
-VOLDATA UINT8 at 0x32 UE2D2; /* USB Endpoint 2 Data Register 2 */
-VOLDATA UINT8 at 0x33 UE2D3; /* USB Endpoint 2 Data Register 3 */
-VOLDATA UINT8 at 0x34 UE2D4; /* USB Endpoint 2 Data Register 4 */
-VOLDATA UINT8 at 0x35 UE2D5; /* USB Endpoint 2 Data Register 5 */
-VOLDATA UINT8 at 0x36 UE2D6; /* USB Endpoint 2 Data Register 6 */
-VOLDATA UINT8 at 0x37 UE2D7; /* USB Endpoint 2 Data Register 7 */
-
-VOLDATA UINT8 at 0x38 UADDR; /* USB Address Register */
- #define USBEN ((struct _hc08_bits *)(&UADDR))->bit7
-
-VOLDATA UINT8 at 0x39 UIR0; /* USB Interrupt Register 0 */
- #define RXD0IE ((struct _hc08_bits *)(&UIR0))->bit0
- #define TXD0IE ((struct _hc08_bits *)(&UIR0))->bit1
- #define TXD1IE ((struct _hc08_bits *)(&UIR0))->bit3
- #define RXD2IE ((struct _hc08_bits *)(&UIR0))->bit4
- #define TXD2IE ((struct _hc08_bits *)(&UIR0))->bit5
- #define SUSPND ((struct _hc08_bits *)(&UIR0))->bit6
- #define EOPIE ((struct _hc08_bits *)(&UIR0))->bit7
-
-VOLDATA UINT8 at 0x3a UIR1; /* USB Interrupt Register 1 */
- #define RXD0F ((struct _hc08_bits *)(&UIR1))->bit0
- #define TXD0F ((struct _hc08_bits *)(&UIR1))->bit1
- #define RESUMF ((struct _hc08_bits *)(&UIR1))->bit2
- #define TXD1F ((struct _hc08_bits *)(&UIR1))->bit3
- #define RXD2F ((struct _hc08_bits *)(&UIR1))->bit4
- #define TXD2F ((struct _hc08_bits *)(&UIR1))->bit5
- #define RSTF ((struct _hc08_bits *)(&UIR1))->bit6
- #define EOPF ((struct _hc08_bits *)(&UIR1))->bit7
-
-VOLDATA UINT8 at 0x3b UCR0; /* USB Control Register 0 */
- #define TP0SIZ0 ((struct _hc08_bits *)(&UCR0))->bit0
- #define TP0SIZ1 ((struct _hc08_bits *)(&UCR0))->bit1
- #define TP0SIZ2 ((struct _hc08_bits *)(&UCR0))->bit2
- #define TP0SIZ3 ((struct _hc08_bits *)(&UCR0))->bit3
- #define RX0E ((struct _hc08_bits *)(&UCR0))->bit4
- #define TX0E ((struct _hc08_bits *)(&UCR0))->bit5
- #define T0SEQ ((struct _hc08_bits *)(&UCR0))->bit7
-
-VOLDATA UINT8 at 0x3c UCR1; /* USB Control Register 1 */
- #define TP1SIZ0 ((struct _hc08_bits *)(&UCR1))->bit0
- #define TP1SIZ1 ((struct _hc08_bits *)(&UCR1))->bit1
- #define TP1SIZ2 ((struct _hc08_bits *)(&UCR1))->bit2
- #define TP1SIZ3 ((struct _hc08_bits *)(&UCR1))->bit3
- #define FRESUM ((struct _hc08_bits *)(&UCR1))->bit4
- #define TX1E ((struct _hc08_bits *)(&UCR1))->bit5
- #define STALL1 ((struct _hc08_bits *)(&UCR1))->bit6
- #define T1SEQ ((struct _hc08_bits *)(&UCR1))->bit7
-
-VOLDATA UINT8 at 0x3d USR0; /* USB Status Register 0 */
- #define RP0SIZ0 ((struct _hc08_bits *)(&USR0))->bit0
- #define RP0SIZ1 ((struct _hc08_bits *)(&USR0))->bit1
- #define RP0SIZ2 ((struct _hc08_bits *)(&USR0))->bit2
- #define RP0SIZ3 ((struct _hc08_bits *)(&USR0))->bit3
- #define SETUP ((struct _hc08_bits *)(&USR0))->bit6
- #define R0SEQ ((struct _hc08_bits *)(&USR0))->bit7
-
-VOLDATA UINT8 at 0x3e USR1; /* USB Status Register 1 */
- #define RP2SIZ0 ((struct _hc08_bits *)(&USR1))->bit0
- #define RP2SIZ1 ((struct _hc08_bits *)(&USR1))->bit1
- #define RP2SIZ2 ((struct _hc08_bits *)(&USR1))->bit2
- #define RP2SIZ3 ((struct _hc08_bits *)(&USR1))->bit3
- #define TXSTL ((struct _hc08_bits *)(&USR1))->bit4
- #define TXNAK ((struct _hc08_bits *)(&USR1))->bit5
- #define TXACK ((struct _hc08_bits *)(&USR1))->bit6
- #define R2SEQ ((struct _hc08_bits *)(&USR1))->bit7
-
-VOLXDATA UINT8 at 0xfe00 BSR; /* Break Status Register */
- #define SBSW ((struct _hc08_bits *)(&BSR))->bit1
-
-VOLXDATA UINT8 at 0xfe01 RSR; /* Reset Status Register */
- #define LVI ((struct _hc08_bits *)(&RSR))->bit1
- #define USB ((struct _hc08_bits *)(&RSR))->bit2
- #define ILAD ((struct _hc08_bits *)(&RSR))->bit3
- #define ILOP ((struct _hc08_bits *)(&RSR))->bit4
- #define COP ((struct _hc08_bits *)(&RSR))->bit5
- #define PIN ((struct _hc08_bits *)(&RSR))->bit6
- #define POR ((struct _hc08_bits *)(&RSR))->bit7
-
-VOLXDATA UINT8 at 0xfe03 BFCR; /* Break Flag Control Register */
- #define BFCE ((struct _hc08_bits *)(&BFCR))->bit7
-
-VOLXDATA UINT8 at 0xfe04 INT1; /* Interrupt Status Register 1 */
- #define IF1 ((struct _hc08_bits *)(&INT1))->bit2
- #define IF2 ((struct _hc08_bits *)(&INT1))->bit3
- #define IF3 ((struct _hc08_bits *)(&INT1))->bit4
- #define IF4 ((struct _hc08_bits *)(&INT1))->bit5
- #define IF5 ((struct _hc08_bits *)(&INT1))->bit6
- #define IF6 ((struct _hc08_bits *)(&INT1))->bit7
-
-VOLXDATA UINT8 at 0xfe08 FLCR; /* FLASH Control Register */
- #define PGM ((struct _hc08_bits *)(&FLCR))->bit0
- #define ERASE ((struct _hc08_bits *)(&FLCR))->bit1
- #define MASS ((struct _hc08_bits *)(&FLCR))->bit2
- #define HVEN ((struct _hc08_bits *)(&FLCR))->bit3
-
-VOLXDATA UINT8 at 0xfe09 FLBPR; /* FLASH Block Protect Register */
- #define BPR0 ((struct _hc08_bits *)(&FLBPR))->bit0
- #define BPR1 ((struct _hc08_bits *)(&FLBPR))->bit1
- #define BPR2 ((struct _hc08_bits *)(&FLBPR))->bit2
- #define BPR3 ((struct _hc08_bits *)(&FLBPR))->bit3
- #define BPR4 ((struct _hc08_bits *)(&FLBPR))->bit4
- #define BPR5 ((struct _hc08_bits *)(&FLBPR))->bit5
- #define BPR6 ((struct _hc08_bits *)(&FLBPR))->bit6
- #define BPR7 ((struct _hc08_bits *)(&FLBPR))->bit7
-
-VOLXDATA UINT16 at 0xfe0c BRK; /* Break Address High & Low Registers */
-VOLXDATA UINT8 at 0xfe0c BRKH; /* Break Address High Register */
-VOLXDATA UINT8 at 0xfe0d BRKL; /* Break Address Low Register */
-
-VOLXDATA UINT8 at 0xfe0e BRKSCR; /* Break Status and Control Register */
- #define BRKA ((struct _hc08_bits *)(&BRKSCR))->bit6
- #define BRKE ((struct _hc08_bits *)(&BRKSCR))->bit7
-
-VOLXDATA UINT8 at 0xffff COPCTL; /* COP Control Register */
-
-#endif
-
+++ /dev/null
-/*-------------------------------------------------------------------------
- Register Declarations for Motorola MC68HC908QY & MC68HC908QT
-
- Written By - Erik Petrich
- epetrich@users.sourceforge.net (2003)
-
- This program is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published by the
- Free Software Foundation; either version 2, or (at your option) any
- later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
- In other words, you are welcome to use, share and improve this program.
- You are forbidden to forbid anyone else to use, share and improve
- what you give them. Help stamp out software-hoarding!
--------------------------------------------------------------------------*/
-
-#ifndef MC68HC908QY_H
-#define MC68HC908QY_H
-
-#ifndef UINT8
- #define UINT8 unsigned char
-#endif
-#ifndef UINT16
- #define UINT16 unsigned int
-#endif
-#ifndef VOLDATA
- #define VOLDATA volatile data
-#endif
-#ifndef VOLXDATA
- #define VOLXDATA volatile xdata
-#endif
-
-struct _hc08_bits
-{
- unsigned int bit0:1;
- unsigned int bit1:1;
- unsigned int bit2:1;
- unsigned int bit3:1;
- unsigned int bit4:1;
- unsigned int bit5:1;
- unsigned int bit6:1;
- unsigned int bit7:1;
-};
-
-
-VOLDATA UINT8 at 0x00 PTA; /* Port A Data Register */
- #define PTA0 ((struct _hc08_bits *)(&PTA))->bit0
- #define PTA1 ((struct _hc08_bits *)(&PTA))->bit1
- #define PTA2 ((struct _hc08_bits *)(&PTA))->bit2
- #define PTA3 ((struct _hc08_bits *)(&PTA))->bit3
- #define PTA4 ((struct _hc08_bits *)(&PTA))->bit4
- #define PTA5 ((struct _hc08_bits *)(&PTA))->bit5
- #define AWUL ((struct _hc08_bits *)(&PTA))->bit6
-
-VOLDATA UINT8 at 0x01 PTB; /* Port B Data Register */
- #define PTB0 ((struct _hc08_bits *)(&PTB))->bit0
- #define PTB1 ((struct _hc08_bits *)(&PTB))->bit1
- #define PTB2 ((struct _hc08_bits *)(&PTB))->bit2
- #define PTB3 ((struct _hc08_bits *)(&PTB))->bit3
- #define PTB4 ((struct _hc08_bits *)(&PTB))->bit4
- #define PTB5 ((struct _hc08_bits *)(&PTB))->bit5
- #define PTB6 ((struct _hc08_bits *)(&PTB))->bit6
- #define PTB7 ((struct _hc08_bits *)(&PTB))->bit7
-
-VOLDATA UINT8 at 0x04 DDRA; /* Data Direction Register A */
- #define DDRA0 ((struct _hc08_bits *)(&DDRA))->bit0
- #define DDRA1 ((struct _hc08_bits *)(&DDRA))->bit1
- #define DDRA3 ((struct _hc08_bits *)(&DDRA))->bit3
- #define DDRA4 ((struct _hc08_bits *)(&DDRA))->bit4
- #define DDRA5 ((struct _hc08_bits *)(&DDRA))->bit5
-
-VOLDATA UINT8 at 0x05 DDRB; /* Data Direction Register B */
- #define DDRB0 ((struct _hc08_bits *)(&DDRB))->bit0
- #define DDRB1 ((struct _hc08_bits *)(&DDRB))->bit1
- #define DDRB2 ((struct _hc08_bits *)(&DDRB))->bit2
- #define DDRB3 ((struct _hc08_bits *)(&DDRB))->bit3
- #define DDRB4 ((struct _hc08_bits *)(&DDRB))->bit4
- #define DDRB5 ((struct _hc08_bits *)(&DDRB))->bit5
- #define DDRB6 ((struct _hc08_bits *)(&DDRB))->bit6
- #define DDRB7 ((struct _hc08_bits *)(&DDRB))->bit7
-
-VOLDATA UINT8 at 0x0b PTAPUE; /* Port A Input Pullup Enable Register */
- #define PTAPUE0 ((struct _hc08_bits *)(&PTAPUE))->bit0
- #define PTAPUE1 ((struct _hc08_bits *)(&PTAPUE))->bit1
- #define PTAPUE2 ((struct _hc08_bits *)(&PTAPUE))->bit2
- #define PTAPUE3 ((struct _hc08_bits *)(&PTAPUE))->bit3
- #define PTAPUE4 ((struct _hc08_bits *)(&PTAPUE))->bit4
- #define PTAPUE5 ((struct _hc08_bits *)(&PTAPUE))->bit5
- #define OSC2EN ((struct _hc08_bits *)(&PTAPUE))->bit7
-
-VOLDATA UINT8 at 0x0c PTBPUE; /* Port B Input Pullup Enable Register */
- #define PTBPUE0 ((struct _hc08_bits *)(&PTBPUE))->bit0
- #define PTBPUE1 ((struct _hc08_bits *)(&PTBPUE))->bit1
- #define PTBPUE2 ((struct _hc08_bits *)(&PTBPUE))->bit2
- #define PTBPUE3 ((struct _hc08_bits *)(&PTBPUE))->bit3
- #define PTBPUE4 ((struct _hc08_bits *)(&PTBPUE))->bit4
- #define PTBPUE5 ((struct _hc08_bits *)(&PTBPUE))->bit5
- #define PTBPUE6 ((struct _hc08_bits *)(&PTBPUE))->bit6
- #define PTBPUE7 ((struct _hc08_bits *)(&PTBPUE))->bit7
-
-VOLDATA UINT8 at 0x1a KBSCR; /* Keyboard Status and Control Register */
- #define MODEK ((struct _hc08_bits *)(&KBSCR))->bit0
- #define IMASKK ((struct _hc08_bits *)(&KBSCR))->bit1
- #define ACKK ((struct _hc08_bits *)(&KBSCR))->bit2
- #define KEYF ((struct _hc08_bits *)(&KBSCR))->bit3
-
-VOLDATA UINT8 at 0x1b KBIER; /* Keyboard Interrupt Enable Register */
- #define KBIE0 ((struct _hc08_bits *)(&KBIER))->bit0
- #define KBIE1 ((struct _hc08_bits *)(&KBIER))->bit1
- #define KBIE2 ((struct _hc08_bits *)(&KBIER))->bit2
- #define KBIE3 ((struct _hc08_bits *)(&KBIER))->bit3
- #define KBIE4 ((struct _hc08_bits *)(&KBIER))->bit4
- #define KBIE5 ((struct _hc08_bits *)(&KBIER))->bit5
- #define AWUIE ((struct _hc08_bits *)(&KBIER))->bit6
-
-VOLDATA UINT8 at 0x1d INTSCR; /* IRQ Status and Control Register */
- #define MODE1 ((struct _hc08_bits *)(&INTSCR))->bit0
- #define IMASK1 ((struct _hc08_bits *)(&INTSCR))->bit1
- #define ACK1 ((struct _hc08_bits *)(&INTSCR))->bit2
- #define IRQF1 ((struct _hc08_bits *)(&INTSCR))->bit3
-
-VOLDATA UINT8 at 0x1e CONFIG2; /* Configuration Register 2 */
-/* CONFIG2 is one-time writeable, so can't use bitfields */
-
-VOLDATA UINT8 at 0x1f CONFIG1; /* Configuration Register 1 */
-/* CONFIG1 is one-time writeable, so can't use bitfields */
-
-VOLDATA UINT8 at 0x20 TSC; /* TIM Status and Control */
- #define PS0 ((struct _hc08_bits *)(&TSC))->bit0
- #define PS1 ((struct _hc08_bits *)(&TSC))->bit1
- #define PS2 ((struct _hc08_bits *)(&TSC))->bit2
- #define TRST ((struct _hc08_bits *)(&TSC))->bit4
- #define TSTOP ((struct _hc08_bits *)(&TSC))->bit5
- #define TOIE ((struct _hc08_bits *)(&TSC))->bit6
- #define TOF ((struct _hc08_bits *)(&TSC))->bit7
-
-VOLDATA UINT8 at 0x21 TCNTH; /* TIM Counter Register High */
-VOLDATA UINT8 at 0x22 TCNTL; /* TIM Counter Register Low */
-VOLDATA UINT16 at 0x21 TCNT; /* TIM Counter High & Low Registers */
-
-VOLDATA UINT8 at 0x23 TMODH; /* TIM Counter Modulo Register High */
-VOLDATA UINT8 at 0x24 TMODL; /* TIM Counter Modulo Register Low */
-VOLDATA UINT16 at 0x23 TMOD; /* TIM Counter Modulo High & Low Registers */
-
-VOLDATA UINT8 at 0x25 TSC0; /* TIM Channel 0 Status and Control Register */
- #define CH0MAX ((struct _hc08_bits *)(&TSC0))->bit0
- #define TOV0 ((struct _hc08_bits *)(&TSC0))->bit1
- #define ELS0A ((struct _hc08_bits *)(&TSC0))->bit2
- #define ELS0B ((struct _hc08_bits *)(&TSC0))->bit3
- #define MS0A ((struct _hc08_bits *)(&TSC0))->bit4
- #define MS0B ((struct _hc08_bits *)(&TSC0))->bit5
- #define CH0IE ((struct _hc08_bits *)(&TSC0))->bit6
- #define CH0F ((struct _hc08_bits *)(&TSC0))->bit7
-
-VOLDATA UINT8 at 0x26 TCH0H; /* TIM Channel 0 Register High */
-VOLDATA UINT8 at 0x27 TCH0L; /* TIM Channel 0 Register Low */
-VOLDATA UINT16 at 0x26 TCH0; /* TIM Channel 0 High & Low Registers */
-
-VOLDATA UINT8 at 0x28 TSC1; /* TIM Channel 1 Status and Control Register */
- #define CH1MAX ((struct _hc08_bits *)(&TSC1))->bit0
- #define TOV1 ((struct _hc08_bits *)(&TSC1))->bit1
- #define ELS1A ((struct _hc08_bits *)(&TSC1))->bit2
- #define ELS1B ((struct _hc08_bits *)(&TSC1))->bit3
- #define MS1A ((struct _hc08_bits *)(&TSC1))->bit4
- #define MS1B ((struct _hc08_bits *)(&TSC1))->bit5
- #define CH1IE ((struct _hc08_bits *)(&TSC1))->bit6
- #define CH1F ((struct _hc08_bits *)(&TSC1))->bit7
-
-VOLDATA UINT8 at 0x29 TCH1H; /* TIM Channel 1 Register High */
-VOLDATA UINT8 at 0x2a TCH1L; /* TIM Channel 1 Register Low */
-VOLDATA UINT16 at 0x29 TCH1; /* TIM Channel 1 High & Low Registers */
-
-VOLDATA UINT8 at 0x36 OSCSTAT; /* Oscillator Status Register */
- #define ECGST ((struct _hc08_bits *)(&OSCSTAT))->bit0
- #define ECGON ((struct _hc08_bits *)(&OSCSTAT))->bit1
-
-VOLDATA UINT8 at 0x38 OSCTRIM; /* Oscillator Trim Register */
-
-VOLDATA UINT8 at 0x3c ADSCR; /* ADC Status and Control Register */
- #define CH0 ((struct _hc08_bits *)(&ADSCR))->bit0
- #define CH1 ((struct _hc08_bits *)(&ADSCR))->bit1
- #define CH2 ((struct _hc08_bits *)(&ADSCR))->bit2
- #define CH3 ((struct _hc08_bits *)(&ADSCR))->bit3
- #define CH4 ((struct _hc08_bits *)(&ADSCR))->bit4
- #define ADC0 ((struct _hc08_bits *)(&ADSCR))->bit5
- #define AIEN ((struct _hc08_bits *)(&ADSCR))->bit6
- #define COCO ((struct _hc08_bits *)(&ADSCR))->bit7
-
-VOLDATA UINT8 at 0x3e ADR; /* ADC Data Register */
-
-VOLDATA UINT8 at 0x3f ADICLK; /* ADS Input Clock Register */
- #define ADIV0 ((struct _hc08_bits *)(&ADICLK))->bit5
- #define ADIV1 ((struct _hc08_bits *)(&ADICLK))->bit6
- #define ADIV2 ((struct _hc08_bits *)(&ADICLK))->bit7
-
-VOLXDATA UINT8 at 0xfe00 BSR; /* Break Status Register */
- #define SBSW ((struct _hc08_bits *)(&BSR))->bit1
-
-VOLXDATA UINT8 at 0xfe01 SRSR; /* SIM Reset Status Register */
- #define LVI ((struct _hc08_bits *)(&SRSR))->bit1
- #define MODRST ((struct _hc08_bits *)(&SRSR))->bit2
- #define ILAD ((struct _hc08_bits *)(&SRSR))->bit3
- #define ILOP ((struct _hc08_bits *)(&SRSR))->bit4
- #define COP ((struct _hc08_bits *)(&SRSR))->bit5
- #define PIN ((struct _hc08_bits *)(&SRSR))->bit6
- #define POR ((struct _hc08_bits *)(&SRSR))->bit7
-
-VOLXDATA UINT8 at 0xfe02 BRKAR; /* Break Auxilliary Register */
- #define BDCOP ((struct _hc08_bits *)(&BRKAR))->bit0
-
-VOLXDATA UINT8 at 0xfe03 BFCF; /* Break Flag Control Register */
- #define BFCF ((struct _hc08_bits *)(&BFCF))->bit7
-
-VOLXDATA UINT8 at 0xfe04 INT1; /* Interrupt Status Register 1 */
- #define IF1 ((struct _hc08_bits *)(&INT1))->bit2
- #define IF3 ((struct _hc08_bits *)(&INT1))->bit4
- #define IF4 ((struct _hc08_bits *)(&INT1))->bit5
- #define IF5 ((struct _hc08_bits *)(&INT1))->bit6
-
-VOLXDATA UINT8 at 0xfe05 INT2; /* Interrupt Status Register 2 */
- #define IF14 ((struct _hc08_bits *)(&INT2))->bit7
-
-VOLXDATA UINT8 at 0xfe06 INT3; /* Interrupt Status Register 3 */
- #define IF15 ((struct _hc08_bits *)(&INT3))->bit0
-
-VOLXDATA UINT8 at 0xfe08 FLCR; /* FLASH Control Register */
- #define PGM ((struct _hc08_bits *)(&FLCR))->bit0
- #define ERASE ((struct _hc08_bits *)(&FLCR))->bit1
- #define MASS ((struct _hc08_bits *)(&FLCR))->bit2
- #define HVEN ((struct _hc08_bits *)(&FLCR))->bit3
-
-VOLXDATA UINT8 at 0xfe09 BRKH; /* Break Address High Register */
-VOLXDATA UINT8 at 0xfe0a BRKL; /* Break Address Low Register */
-VOLXDATA UINT16 at 0xfe09 BRK; /* Break Address High & Low Registers */
-
-VOLXDATA UINT8 at 0xfe0b BRKSCR; /* Break Status and Control Register */
- #define BRKA ((struct _hc08_bits *)(&BRKSCR))->bit6
- #define BRKE ((struct _hc08_bits *)(&BRKSCR))->bit7
-
-VOLXDATA UINT8 at 0xfe0c LVISR; /* LVI Status Register */
- #define LVIOUT ((struct _hc08_bits *)(&LVISR))->bit7
-
-VOLXDATA UINT8 at 0xffbe FLBPR; /* FLASH Block Protect Register */
-VOLXDATA UINT8 at 0xffc0 OSCTRIMVAL; /* Oscillator Trim Value */
-VOLXDATA UINT8 at 0xffff COPCTL; /* COP Control Register */
-
-
-#endif
-
/* BYTE Registers */
-sfr at 0x80 P0 ; /* PORT 0 */
-sfr at 0x81 SP ; /* STACK POINTER */
-sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
-sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
-sfr at 0x87 PCON ; /* POWER CONTROL */
-sfr at 0x88 TCON ; /* TIMER CONTROL */
-sfr at 0x89 TMOD ; /* TIMER MODE */
-sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
-sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
-sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
-sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
-sfr at 0x8E CKCON ; /* CLOCK CONTROL */
-sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
-sfr at 0x90 P1 ; /* PORT 1 */
-sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */
-sfr at 0x92 TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
-sfr at 0x93 TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
-sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */
-sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */
-sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */
-sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */
-sfr at 0x9A SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
-sfr at 0x9B SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
-sfr at 0x9D SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
-sfr at 0x9E CPT0CN ; /* COMPARATOR 0 CONTROL */
-sfr at 0x9F CPT1CN ; /* COMPARATOR 1 CONTROL */
-sfr at 0xA0 P2 ; /* PORT 2 */
-sfr at 0xA4 PRT0CF ; /* PORT 0 CONFIGURATION */
-sfr at 0xA5 PRT1CF ; /* PORT 1 CONFIGURATION */
-sfr at 0xA6 PRT2CF ; /* PORT 2 CONFIGURATION */
-sfr at 0xA7 PRT3CF ; /* PORT 3 CONFIGURATION */
-sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
-sfr at 0xAD PRT1IF ; /* PORT 1 EXTERNAL INTERRUPT FLAGS */
-sfr at 0xAF EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
-sfr at 0xAF _XPAGE ; /* XDATA/PDATA PAGE */
-sfr at 0xB0 P3 ; /* PORT 3 */
-sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
-sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
-sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
-sfr at 0xB7 FLACL ; /* FLASH ACESS LIMIT */
-sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
-sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
-sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
-sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
-sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
-sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
-sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
-sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
-sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
-sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
-sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
-sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
-sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
-sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
-sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */
-sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
-sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
-sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
-sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
-sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
-sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
-sfr at 0xD5 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
-sfr at 0xD6 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
-sfr at 0xD7 DAC1CN ; /* DAC 1 CONTROL */
-sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
-sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
-sfr at 0xDA PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
-sfr at 0xDB PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
-sfr at 0xDC PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
-sfr at 0xDD PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
-sfr at 0xDE PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
-sfr at 0xE0 ACC ; /* ACCUMULATOR */
-sfr at 0xE1 XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
-sfr at 0xE2 XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
-sfr at 0xE3 XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
-sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
-sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
-sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
-sfr at 0xE9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
-sfr at 0xEA PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
-sfr at 0xEB PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
-sfr at 0xEC PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
-sfr at 0xED PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
-sfr at 0xEE PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
-sfr at 0xEF RSTSRC ; /* RESET SOURCE */
-sfr at 0xF0 B ; /* B REGISTER */
-sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
-sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
-sfr at 0xF8 SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
-sfr at 0xF9 PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
-sfr at 0xFA PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
-sfr at 0xFB PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
-sfr at 0xFC PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
-sfr at 0xFD PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
-sfr at 0xFE PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
-sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
+__sfr __at 0x80 P0 ; /* PORT 0 */
+__sfr __at 0x81 SP ; /* STACK POINTER */
+__sfr __at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
+__sfr __at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
+__sfr __at 0x87 PCON ; /* POWER CONTROL */
+__sfr __at 0x88 TCON ; /* TIMER CONTROL */
+__sfr __at 0x89 TMOD ; /* TIMER MODE */
+__sfr __at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
+__sfr __at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
+__sfr __at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
+__sfr __at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
+__sfr __at 0x8E CKCON ; /* CLOCK CONTROL */
+__sfr __at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
+__sfr __at 0x90 P1 ; /* PORT 1 */
+__sfr __at 0x91 TMR3CN ; /* TIMER 3 CONTROL */
+__sfr __at 0x92 TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
+__sfr __at 0x93 TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
+__sfr __at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */
+__sfr __at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */
+__sfr __at 0x98 SCON ; /* SERIAL PORT CONTROL */
+__sfr __at 0x99 SBUF ; /* SERIAL PORT BUFFER */
+__sfr __at 0x9A SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
+__sfr __at 0x9B SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
+__sfr __at 0x9D SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
+__sfr __at 0x9E CPT0CN ; /* COMPARATOR 0 CONTROL */
+__sfr __at 0x9F CPT1CN ; /* COMPARATOR 1 CONTROL */
+__sfr __at 0xA0 P2 ; /* PORT 2 */
+__sfr __at 0xA4 PRT0CF ; /* PORT 0 CONFIGURATION */
+__sfr __at 0xA5 PRT1CF ; /* PORT 1 CONFIGURATION */
+__sfr __at 0xA6 PRT2CF ; /* PORT 2 CONFIGURATION */
+__sfr __at 0xA7 PRT3CF ; /* PORT 3 CONFIGURATION */
+__sfr __at 0xA8 IE ; /* INTERRUPT ENABLE */
+__sfr __at 0xAD PRT1IF ; /* PORT 1 EXTERNAL INTERRUPT FLAGS */
+__sfr __at 0xAF EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
+__sfr __at 0xAF _XPAGE ; /* XDATA/PDATA PAGE */
+__sfr __at 0xB0 P3 ; /* PORT 3 */
+__sfr __at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
+__sfr __at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
+__sfr __at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
+__sfr __at 0xB7 FLACL ; /* FLASH ACESS LIMIT */
+__sfr __at 0xB8 IP ; /* INTERRUPT PRIORITY */
+__sfr __at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
+__sfr __at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
+__sfr __at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
+__sfr __at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
+__sfr __at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
+__sfr __at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
+__sfr __at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
+__sfr __at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
+__sfr __at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
+__sfr __at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
+__sfr __at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
+__sfr __at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
+__sfr __at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
+__sfr __at 0xC8 T2CON ; /* TIMER 2 CONTROL */
+__sfr __at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
+__sfr __at 0xD0 PSW ; /* PROGRAM STATUS WORD */
+__sfr __at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
+__sfr __at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
+__sfr __at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
+__sfr __at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
+__sfr __at 0xD5 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
+__sfr __at 0xD6 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
+__sfr __at 0xD7 DAC1CN ; /* DAC 1 CONTROL */
+__sfr __at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
+__sfr __at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
+__sfr __at 0xDA PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
+__sfr __at 0xDB PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
+__sfr __at 0xDC PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
+__sfr __at 0xDD PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
+__sfr __at 0xDE PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
+__sfr __at 0xE0 ACC ; /* ACCUMULATOR */
+__sfr __at 0xE1 XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
+__sfr __at 0xE2 XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
+__sfr __at 0xE3 XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
+__sfr __at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
+__sfr __at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
+__sfr __at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
+__sfr __at 0xE9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
+__sfr __at 0xEA PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
+__sfr __at 0xEB PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
+__sfr __at 0xEC PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
+__sfr __at 0xED PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
+__sfr __at 0xEE PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
+__sfr __at 0xEF RSTSRC ; /* RESET SOURCE */
+__sfr __at 0xF0 B ; /* B REGISTER */
+__sfr __at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
+__sfr __at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
+__sfr __at 0xF8 SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
+__sfr __at 0xF9 PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
+__sfr __at 0xFA PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
+__sfr __at 0xFB PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
+__sfr __at 0xFC PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
+__sfr __at 0xFD PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
+__sfr __at 0xFE PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
+__sfr __at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
/* BIT Registers */
/* P0 0x80 */
-sbit at 0x87 P0_7 ;
-sbit at 0x86 P0_6 ;
-sbit at 0x85 P0_5 ;
-sbit at 0x84 P0_4 ;
-sbit at 0x83 P0_3 ;
-sbit at 0x82 P0_2 ;
-sbit at 0x81 P0_1 ;
-sbit at 0x80 P0_0 ;
+__sbit __at 0x87 P0_7 ;
+__sbit __at 0x86 P0_6 ;
+__sbit __at 0x85 P0_5 ;
+__sbit __at 0x84 P0_4 ;
+__sbit __at 0x83 P0_3 ;
+__sbit __at 0x82 P0_2 ;
+__sbit __at 0x81 P0_1 ;
+__sbit __at 0x80 P0_0 ;
/* TCON 0x88 */
-sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
-sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
-sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
-sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
-sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
-sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
-sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
-sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
+__sbit __at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
+__sbit __at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
+__sbit __at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
+__sbit __at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
+__sbit __at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
+__sbit __at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
+__sbit __at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
+__sbit __at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
/* P1 0x90 */
-sbit at 0x97 P1_7 ;
-sbit at 0x96 P1_6 ;
-sbit at 0x95 P1_5 ;
-sbit at 0x94 P1_4 ;
-sbit at 0x93 P1_3 ;
-sbit at 0x92 P1_2 ;
-sbit at 0x91 P1_1 ;
-sbit at 0x90 P1_0 ;
+__sbit __at 0x97 P1_7 ;
+__sbit __at 0x96 P1_6 ;
+__sbit __at 0x95 P1_5 ;
+__sbit __at 0x94 P1_4 ;
+__sbit __at 0x93 P1_3 ;
+__sbit __at 0x92 P1_2 ;
+__sbit __at 0x91 P1_1 ;
+__sbit __at 0x90 P1_0 ;
/* SCON 0x98 */
-sbit at 0x9F SM0 ; /* SERIAL MODE CONTROL BIT 0 */
-sbit at 0x9E SM1 ; /* SERIAL MODE CONTROL BIT 1 */
-sbit at 0x9D SM2 ; /* MULTIPROCESSOR COMMUNICATION ENABLE */
-sbit at 0x9C REN ; /* RECEIVE ENABLE */
-sbit at 0x9B TB8 ; /* TRANSMIT BIT 8 */
-sbit at 0x9A RB8 ; /* RECEIVE BIT 8 */
-sbit at 0x99 TI ; /* TRANSMIT INTERRUPT FLAG */
-sbit at 0x98 RI ; /* RECEIVE INTERRUPT FLAG */
+__sbit __at 0x9F SM0 ; /* SERIAL MODE CONTROL BIT 0 */
+__sbit __at 0x9E SM1 ; /* SERIAL MODE CONTROL BIT 1 */
+__sbit __at 0x9D SM2 ; /* MULTIPROCESSOR COMMUNICATION ENABLE */
+__sbit __at 0x9C REN ; /* RECEIVE ENABLE */
+__sbit __at 0x9B TB8 ; /* TRANSMIT BIT 8 */
+__sbit __at 0x9A RB8 ; /* RECEIVE BIT 8 */
+__sbit __at 0x99 TI ; /* TRANSMIT INTERRUPT FLAG */
+__sbit __at 0x98 RI ; /* RECEIVE INTERRUPT FLAG */
/* P2 0xA0 */
-sbit at 0xA7 P2_7 ;
-sbit at 0xA6 P2_6 ;
-sbit at 0xA5 P2_5 ;
-sbit at 0xA4 P2_4 ;
-sbit at 0xA3 P2_3 ;
-sbit at 0xA2 P2_2 ;
-sbit at 0xA1 P2_1 ;
-sbit at 0xA0 P2_0 ;
+__sbit __at 0xA7 P2_7 ;
+__sbit __at 0xA6 P2_6 ;
+__sbit __at 0xA5 P2_5 ;
+__sbit __at 0xA4 P2_4 ;
+__sbit __at 0xA3 P2_3 ;
+__sbit __at 0xA2 P2_2 ;
+__sbit __at 0xA1 P2_1 ;
+__sbit __at 0xA0 P2_0 ;
/* IE 0xA8 */
-sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
-sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
-sbit at 0xAC ES ; /* SERIAL PORT INTERRUPT ENABLE */
-sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
-sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
-sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
-sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
+__sbit __at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
+__sbit __at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
+__sbit __at 0xAC ES ; /* SERIAL PORT INTERRUPT ENABLE */
+__sbit __at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
+__sbit __at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
+__sbit __at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
+__sbit __at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
/* P3 0xB0 */
-sbit at 0xB7 P3_7 ;
-sbit at 0xB6 P3_6 ;
-sbit at 0xB5 P3_5 ;
-sbit at 0xB4 P3_4 ;
-sbit at 0xB3 P3_3 ;
-sbit at 0xB2 P3_2 ;
-sbit at 0xB1 P3_1 ;
-sbit at 0xB0 P3_0 ;
+__sbit __at 0xB7 P3_7 ;
+__sbit __at 0xB6 P3_6 ;
+__sbit __at 0xB5 P3_5 ;
+__sbit __at 0xB4 P3_4 ;
+__sbit __at 0xB3 P3_3 ;
+__sbit __at 0xB2 P3_2 ;
+__sbit __at 0xB1 P3_1 ;
+__sbit __at 0xB0 P3_0 ;
/* IP 0xB8 */
-sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */
-sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */
-sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */
-sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
-sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
-sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
+__sbit __at 0xBD PT2 ; /* TIMER 2 PRIORITY */
+__sbit __at 0xBC PS ; /* SERIAL PORT PRIORITY */
+__sbit __at 0xBB PT1 ; /* TIMER 1 PRIORITY */
+__sbit __at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
+__sbit __at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
+__sbit __at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
/* SMB0CN 0xC0 */
-sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */
-sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
-sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */
-sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
-sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
-sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
-sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
-sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
+__sbit __at 0xC7 BUSY ; /* SMBUS 0 BUSY */
+__sbit __at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
+__sbit __at 0xC5 STA ; /* SMBUS 0 START FLAG */
+__sbit __at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
+__sbit __at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
+__sbit __at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
+__sbit __at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
+__sbit __at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
/* T2CON 0xC8 */
-sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
-sbit at 0xCE EXF2 ; /* EXTERNAL FLAG */
-sbit at 0xCD RCLK ; /* RECEIVE CLOCK FLAG */
-sbit at 0xCC TCLK ; /* TRANSMIT CLOCK FLAG */
-sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
-sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
-sbit at 0xC9 CT2 ; /* TIMER OR COUNTER SELECT */
-sbit at 0xC8 CPRL2 ; /* CAPTURE OR RELOAD SELECT */
+__sbit __at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
+__sbit __at 0xCE EXF2 ; /* EXTERNAL FLAG */
+__sbit __at 0xCD RCLK ; /* RECEIVE CLOCK FLAG */
+__sbit __at 0xCC TCLK ; /* TRANSMIT CLOCK FLAG */
+__sbit __at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
+__sbit __at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
+__sbit __at 0xC9 CT2 ; /* TIMER OR COUNTER SELECT */
+__sbit __at 0xC8 CPRL2 ; /* CAPTURE OR RELOAD SELECT */
/* PSW 0xD0 */
-sbit at 0xD7 CY ; /* CARRY FLAG */
-sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
-sbit at 0xD5 F0 ; /* USER FLAG 0 */
-sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
-sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
-sbit at 0xD2 OV ; /* OVERFLOW FLAG */
-sbit at 0xD1 F1 ; /* USER FLAG 1 */
-sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
+__sbit __at 0xD7 CY ; /* CARRY FLAG */
+__sbit __at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
+__sbit __at 0xD5 F0 ; /* USER FLAG 0 */
+__sbit __at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
+__sbit __at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
+__sbit __at 0xD2 OV ; /* OVERFLOW FLAG */
+__sbit __at 0xD1 F1 ; /* USER FLAG 1 */
+__sbit __at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
/* PCA0CN 0xD8H */
-sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
-sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
-sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
-sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
-sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
-sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
-sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
+__sbit __at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
+__sbit __at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
+__sbit __at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
+__sbit __at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
+__sbit __at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
+__sbit __at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
+__sbit __at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
/* ADC0CN 0xE8H */
-sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */
-sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
-sbit at 0xED AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
-sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
-sbit at 0xEB ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
-sbit at 0xEA ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
-sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
-sbit at 0xE8 ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
+__sbit __at 0xEF AD0EN ; /* ADC 0 ENABLE */
+__sbit __at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
+__sbit __at 0xED AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
+__sbit __at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
+__sbit __at 0xEB ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
+__sbit __at 0xEA ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
+__sbit __at 0xE9 AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
+__sbit __at 0xE8 ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
/* SPI0CN 0xF8H */
-sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
-sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
-sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
-sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
-sbit at 0xFB TXBSY ; /* SPI 0 TX BUSY FLAG */
-sbit at 0xFA SLVSEL ; /* SPI 0 SLAVE SELECT */
-sbit at 0xF9 MSTEN ; /* SPI 0 MASTER ENABLE */
-sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
+__sbit __at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
+__sbit __at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
+__sbit __at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
+__sbit __at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
+__sbit __at 0xFB TXBSY ; /* SPI 0 TX BUSY FLAG */
+__sbit __at 0xFA SLVSEL ; /* SPI 0 SLAVE SELECT */
+__sbit __at 0xF9 MSTEN ; /* SPI 0 MASTER ENABLE */
+__sbit __at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
/* Predefined SFR Bit Masks */
/* BYTE Registers */
-sfr at 0x80 P0 ; /* PORT 0 */
-sfr at 0x81 SP ; /* STACK POINTER */
-sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
-sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
-sfr at 0x87 PCON ; /* POWER CONTROL */
-sfr at 0x88 TCON ; /* TIMER CONTROL */
-sfr at 0x89 TMOD ; /* TIMER MODE */
-sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
-sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
-sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
-sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
-sfr at 0x8E CKCON ; /* CLOCK CONTROL */
-sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
-sfr at 0x90 P1 ; /* PORT 1 */
-sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */
-sfr at 0x92 TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
-sfr at 0x93 TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
-sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */
-sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */
-sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */
-sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */
-sfr at 0x9A SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
-sfr at 0x9B SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
-sfr at 0x9D SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
-sfr at 0x9E CPT0CN ; /* COMPARATOR 0 CONTROL */
-sfr at 0x9F CPT1CN ; /* COMPARATOR 1 CONTROL */
-sfr at 0xA0 P2 ; /* PORT 2 */
-sfr at 0xA4 PRT0CF ; /* PORT 0 CONFIGURATION */
-sfr at 0xA5 PRT1CF ; /* PORT 1 CONFIGURATION */
-sfr at 0xA6 PRT2CF ; /* PORT 2 CONFIGURATION */
-sfr at 0xA7 PRT3CF ; /* PORT 3 CONFIGURATION */
-sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
-sfr at 0xAD PRT1IF ; /* PORT 1 EXTERNAL INTERRUPT FLAGS */
-sfr at 0xAF EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
-sfr at 0xAF _XPAGE ; /* XDATA/PDATA PAGE */
-sfr at 0xB0 P3 ; /* PORT 3 */
-sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
-sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
-sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
-sfr at 0xB7 FLACL ; /* FLASH ACESS LIMIT */
-sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
-sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
-sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
-sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
-sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
-sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
-sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
-sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
-sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
-sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
-sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
-sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
-sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
-sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
-sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */
-sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
-sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
-sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
-sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
-sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
-sfr at 0xDA PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
-sfr at 0xDB PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
-sfr at 0xDC PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
-sfr at 0xDD PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
-sfr at 0xDE PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
-sfr at 0xE0 ACC ; /* ACCUMULATOR */
-sfr at 0xE1 XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
-sfr at 0xE2 XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
-sfr at 0xE3 XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
-sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
-sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
-sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
-sfr at 0xE9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
-sfr at 0xEA PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
-sfr at 0xEB PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
-sfr at 0xEC PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
-sfr at 0xED PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
-sfr at 0xEE PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
-sfr at 0xEF RSTSRC ; /* RESET SOURCE */
-sfr at 0xF0 B ; /* B REGISTER */
-sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
-sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
-sfr at 0xF8 SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
-sfr at 0xF9 PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
-sfr at 0xFA PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
-sfr at 0xFB PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
-sfr at 0xFC PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
-sfr at 0xFD PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
-sfr at 0xFE PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
-sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
+__sfr __at 0x80 P0 ; /* PORT 0 */
+__sfr __at 0x81 SP ; /* STACK POINTER */
+__sfr __at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
+__sfr __at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
+__sfr __at 0x87 PCON ; /* POWER CONTROL */
+__sfr __at 0x88 TCON ; /* TIMER CONTROL */
+__sfr __at 0x89 TMOD ; /* TIMER MODE */
+__sfr __at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
+__sfr __at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
+__sfr __at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
+__sfr __at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
+__sfr __at 0x8E CKCON ; /* CLOCK CONTROL */
+__sfr __at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
+__sfr __at 0x90 P1 ; /* PORT 1 */
+__sfr __at 0x91 TMR3CN ; /* TIMER 3 CONTROL */
+__sfr __at 0x92 TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
+__sfr __at 0x93 TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
+__sfr __at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */
+__sfr __at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */
+__sfr __at 0x98 SCON ; /* SERIAL PORT CONTROL */
+__sfr __at 0x99 SBUF ; /* SERIAL PORT BUFFER */
+__sfr __at 0x9A SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
+__sfr __at 0x9B SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
+__sfr __at 0x9D SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
+__sfr __at 0x9E CPT0CN ; /* COMPARATOR 0 CONTROL */
+__sfr __at 0x9F CPT1CN ; /* COMPARATOR 1 CONTROL */
+__sfr __at 0xA0 P2 ; /* PORT 2 */
+__sfr __at 0xA4 PRT0CF ; /* PORT 0 CONFIGURATION */
+__sfr __at 0xA5 PRT1CF ; /* PORT 1 CONFIGURATION */
+__sfr __at 0xA6 PRT2CF ; /* PORT 2 CONFIGURATION */
+__sfr __at 0xA7 PRT3CF ; /* PORT 3 CONFIGURATION */
+__sfr __at 0xA8 IE ; /* INTERRUPT ENABLE */
+__sfr __at 0xAD PRT1IF ; /* PORT 1 EXTERNAL INTERRUPT FLAGS */
+__sfr __at 0xAF EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
+__sfr __at 0xAF _XPAGE ; /* XDATA/PDATA PAGE */
+__sfr __at 0xB0 P3 ; /* PORT 3 */
+__sfr __at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
+__sfr __at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
+__sfr __at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
+__sfr __at 0xB7 FLACL ; /* FLASH ACESS LIMIT */
+__sfr __at 0xB8 IP ; /* INTERRUPT PRIORITY */
+__sfr __at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
+__sfr __at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
+__sfr __at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
+__sfr __at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
+__sfr __at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
+__sfr __at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
+__sfr __at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
+__sfr __at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
+__sfr __at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
+__sfr __at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
+__sfr __at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
+__sfr __at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
+__sfr __at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
+__sfr __at 0xC8 T2CON ; /* TIMER 2 CONTROL */
+__sfr __at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
+__sfr __at 0xD0 PSW ; /* PROGRAM STATUS WORD */
+__sfr __at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
+__sfr __at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
+__sfr __at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
+__sfr __at 0xDA PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
+__sfr __at 0xDB PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
+__sfr __at 0xDC PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
+__sfr __at 0xDD PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
+__sfr __at 0xDE PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
+__sfr __at 0xE0 ACC ; /* ACCUMULATOR */
+__sfr __at 0xE1 XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
+__sfr __at 0xE2 XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
+__sfr __at 0xE3 XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
+__sfr __at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
+__sfr __at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
+__sfr __at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
+__sfr __at 0xE9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
+__sfr __at 0xEA PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
+__sfr __at 0xEB PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
+__sfr __at 0xEC PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
+__sfr __at 0xED PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
+__sfr __at 0xEE PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
+__sfr __at 0xEF RSTSRC ; /* RESET SOURCE */
+__sfr __at 0xF0 B ; /* B REGISTER */
+__sfr __at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
+__sfr __at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
+__sfr __at 0xF8 SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
+__sfr __at 0xF9 PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
+__sfr __at 0xFA PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
+__sfr __at 0xFB PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
+__sfr __at 0xFC PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
+__sfr __at 0xFD PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
+__sfr __at 0xFE PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
+__sfr __at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
/* BIT Registers */
/* P0 0x80 */
-sbit at 0x87 P0_7 ;
-sbit at 0x86 P0_6 ;
-sbit at 0x85 P0_5 ;
-sbit at 0x84 P0_4 ;
-sbit at 0x83 P0_3 ;
-sbit at 0x82 P0_2 ;
-sbit at 0x81 P0_1 ;
-sbit at 0x80 P0_0 ;
+__sbit __at 0x87 P0_7 ;
+__sbit __at 0x86 P0_6 ;
+__sbit __at 0x85 P0_5 ;
+__sbit __at 0x84 P0_4 ;
+__sbit __at 0x83 P0_3 ;
+__sbit __at 0x82 P0_2 ;
+__sbit __at 0x81 P0_1 ;
+__sbit __at 0x80 P0_0 ;
/* TCON 0x88 */
-sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
-sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
-sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
-sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
-sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
-sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
-sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
-sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
+__sbit __at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
+__sbit __at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
+__sbit __at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
+__sbit __at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
+__sbit __at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
+__sbit __at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
+__sbit __at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
+__sbit __at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
/* P1 0x90 */
-sbit at 0x97 P1_7 ;
-sbit at 0x96 P1_6 ;
-sbit at 0x95 P1_5 ;
-sbit at 0x94 P1_4 ;
-sbit at 0x93 P1_3 ;
-sbit at 0x92 P1_2 ;
-sbit at 0x91 P1_1 ;
-sbit at 0x90 P1_0 ;
+__sbit __at 0x97 P1_7 ;
+__sbit __at 0x96 P1_6 ;
+__sbit __at 0x95 P1_5 ;
+__sbit __at 0x94 P1_4 ;
+__sbit __at 0x93 P1_3 ;
+__sbit __at 0x92 P1_2 ;
+__sbit __at 0x91 P1_1 ;
+__sbit __at 0x90 P1_0 ;
/* SCON 0x98 */
-sbit at 0x9F SM0 ; /* SERIAL MODE CONTROL BIT 0 */
-sbit at 0x9E SM1 ; /* SERIAL MODE CONTROL BIT 1 */
-sbit at 0x9D SM2 ; /* MULTIPROCESSOR COMMUNICATION ENABLE */
-sbit at 0x9C REN ; /* RECEIVE ENABLE */
-sbit at 0x9B TB8 ; /* TRANSMIT BIT 8 */
-sbit at 0x9A RB8 ; /* RECEIVE BIT 8 */
-sbit at 0x99 TI ; /* TRANSMIT INTERRUPT FLAG */
-sbit at 0x98 RI ; /* RECEIVE INTERRUPT FLAG */
+__sbit __at 0x9F SM0 ; /* SERIAL MODE CONTROL BIT 0 */
+__sbit __at 0x9E SM1 ; /* SERIAL MODE CONTROL BIT 1 */
+__sbit __at 0x9D SM2 ; /* MULTIPROCESSOR COMMUNICATION ENABLE */
+__sbit __at 0x9C REN ; /* RECEIVE ENABLE */
+__sbit __at 0x9B TB8 ; /* TRANSMIT BIT 8 */
+__sbit __at 0x9A RB8 ; /* RECEIVE BIT 8 */
+__sbit __at 0x99 TI ; /* TRANSMIT INTERRUPT FLAG */
+__sbit __at 0x98 RI ; /* RECEIVE INTERRUPT FLAG */
/* P2 0xA0 */
-sbit at 0xA7 P2_7 ;
-sbit at 0xA6 P2_6 ;
-sbit at 0xA5 P2_5 ;
-sbit at 0xA4 P2_4 ;
-sbit at 0xA3 P2_3 ;
-sbit at 0xA2 P2_2 ;
-sbit at 0xA1 P2_1 ;
-sbit at 0xA0 P2_0 ;
+__sbit __at 0xA7 P2_7 ;
+__sbit __at 0xA6 P2_6 ;
+__sbit __at 0xA5 P2_5 ;
+__sbit __at 0xA4 P2_4 ;
+__sbit __at 0xA3 P2_3 ;
+__sbit __at 0xA2 P2_2 ;
+__sbit __at 0xA1 P2_1 ;
+__sbit __at 0xA0 P2_0 ;
/* IE 0xA8 */
-sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
-sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
-sbit at 0xAC ES ; /* SERIAL PORT INTERRUPT ENABLE */
-sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
-sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
-sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
-sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
+__sbit __at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
+__sbit __at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
+__sbit __at 0xAC ES ; /* SERIAL PORT INTERRUPT ENABLE */
+__sbit __at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
+__sbit __at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
+__sbit __at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
+__sbit __at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
/* P3 0xB0 */
-sbit at 0xB7 P3_7 ;
-sbit at 0xB6 P3_6 ;
-sbit at 0xB5 P3_5 ;
-sbit at 0xB4 P3_4 ;
-sbit at 0xB3 P3_3 ;
-sbit at 0xB2 P3_2 ;
-sbit at 0xB1 P3_1 ;
-sbit at 0xB0 P3_0 ;
+__sbit __at 0xB7 P3_7 ;
+__sbit __at 0xB6 P3_6 ;
+__sbit __at 0xB5 P3_5 ;
+__sbit __at 0xB4 P3_4 ;
+__sbit __at 0xB3 P3_3 ;
+__sbit __at 0xB2 P3_2 ;
+__sbit __at 0xB1 P3_1 ;
+__sbit __at 0xB0 P3_0 ;
/* IP 0xB8 */
-sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */
-sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */
-sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */
-sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
-sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
-sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
+__sbit __at 0xBD PT2 ; /* TIMER 2 PRIORITY */
+__sbit __at 0xBC PS ; /* SERIAL PORT PRIORITY */
+__sbit __at 0xBB PT1 ; /* TIMER 1 PRIORITY */
+__sbit __at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
+__sbit __at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
+__sbit __at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
/* SMB0CN 0xC0 */
-sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */
-sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
-sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */
-sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
-sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
-sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
-sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
-sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
+__sbit __at 0xC7 BUSY ; /* SMBUS 0 BUSY */
+__sbit __at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
+__sbit __at 0xC5 STA ; /* SMBUS 0 START FLAG */
+__sbit __at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
+__sbit __at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
+__sbit __at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
+__sbit __at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
+__sbit __at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
/* T2CON 0xC8 */
-sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
-sbit at 0xCE EXF2 ; /* EXTERNAL FLAG */
-sbit at 0xCD RCLK ; /* RECEIVE CLOCK FLAG */
-sbit at 0xCC TCLK ; /* TRANSMIT CLOCK FLAG */
-sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
-sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
-sbit at 0xC9 CT2 ; /* TIMER OR COUNTER SELECT */
-sbit at 0xC8 CPRL2 ; /* CAPTURE OR RELOAD SELECT */
+__sbit __at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
+__sbit __at 0xCE EXF2 ; /* EXTERNAL FLAG */
+__sbit __at 0xCD RCLK ; /* RECEIVE CLOCK FLAG */
+__sbit __at 0xCC TCLK ; /* TRANSMIT CLOCK FLAG */
+__sbit __at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
+__sbit __at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
+__sbit __at 0xC9 CT2 ; /* TIMER OR COUNTER SELECT */
+__sbit __at 0xC8 CPRL2 ; /* CAPTURE OR RELOAD SELECT */
/* PSW 0xD0 */
-sbit at 0xD7 CY ; /* CARRY FLAG */
-sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
-sbit at 0xD5 F0 ; /* USER FLAG 0 */
-sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
-sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
-sbit at 0xD2 OV ; /* OVERFLOW FLAG */
-sbit at 0xD1 F1 ; /* USER FLAG 1 */
-sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
+__sbit __at 0xD7 CY ; /* CARRY FLAG */
+__sbit __at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
+__sbit __at 0xD5 F0 ; /* USER FLAG 0 */
+__sbit __at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
+__sbit __at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
+__sbit __at 0xD2 OV ; /* OVERFLOW FLAG */
+__sbit __at 0xD1 F1 ; /* USER FLAG 1 */
+__sbit __at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
/* PCA0CN 0xD8H */
-sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
-sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
-sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
-sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
-sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
-sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
-sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
+__sbit __at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
+__sbit __at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
+__sbit __at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
+__sbit __at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
+__sbit __at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
+__sbit __at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
+__sbit __at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
/* ADC0CN 0xE8H */
-sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */
-sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
-sbit at 0xED AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
-sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
-sbit at 0xEB ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
-sbit at 0xEA ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
-sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
-sbit at 0xE8 ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
+__sbit __at 0xEF AD0EN ; /* ADC 0 ENABLE */
+__sbit __at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
+__sbit __at 0xED AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
+__sbit __at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
+__sbit __at 0xEB ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
+__sbit __at 0xEA ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
+__sbit __at 0xE9 AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
+__sbit __at 0xE8 ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
/* SPI0CN 0xF8H */
-sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
-sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
-sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
-sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
-sbit at 0xFB TXBSY ; /* SPI 0 TX BUSY FLAG */
-sbit at 0xFA SLVSEL ; /* SPI 0 SLAVE SELECT */
-sbit at 0xF9 MSTEN ; /* SPI 0 MASTER ENABLE */
-sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
+__sbit __at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
+__sbit __at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
+__sbit __at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
+__sbit __at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
+__sbit __at 0xFB TXBSY ; /* SPI 0 TX BUSY FLAG */
+__sbit __at 0xFA SLVSEL ; /* SPI 0 SLAVE SELECT */
+__sbit __at 0xF9 MSTEN ; /* SPI 0 MASTER ENABLE */
+__sbit __at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
/* Predefined SFR Bit Masks */
/* BYTE Registers */
-sfr at 0x80 P0 ; /* PORT 0 */
-sfr at 0x81 SP ; /* STACK POINTER */
-sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
-sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
-sfr at 0x84 P4 ; /* PORT 4 */
-sfr at 0x85 P5 ; /* PORT 5 */
-sfr at 0x86 P6 ; /* PORT 6 */
-sfr at 0x87 PCON ; /* POWER CONTROL */
-sfr at 0x88 TCON ; /* TIMER CONTROL */
-sfr at 0x89 TMOD ; /* TIMER MODE */
-sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
-sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
-sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
-sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
-sfr at 0x8E CKCON ; /* CLOCK CONTROL */
-sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
-sfr at 0x90 P1 ; /* PORT 1 */
-sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */
-sfr at 0x92 TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
-sfr at 0x93 TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
-sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */
-sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */
-sfr at 0x96 P7 ; /* PORT 7 */
-sfr at 0x98 SCON ; /* UART0 CONTROL */
-sfr at 0x98 SCON0 ; /* UART0 CONTROL */
-sfr at 0x99 SBUF ; /* UART0 BUFFER */
-sfr at 0x99 SBUF0 ; /* UART0 BUFFER */
-sfr at 0x9A SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
-sfr at 0x9B SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
-sfr at 0x9C ADC1 ; /* ADC 1 DATA */
-sfr at 0x9D SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
-sfr at 0x9E CPT0CN ; /* COMPARATOR 0 CONTROL */
-sfr at 0x9F CPT1CN ; /* COMPARATOR 1 CONTROL */
-sfr at 0xA0 P2 ; /* PORT 2 */
-sfr at 0xA1 EMI0TC ; /* External Memory Timing Control */
-sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */
-sfr at 0xA4 PRT0CF ; /* PORT 0 CONFIGURATION */
-sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
-sfr at 0xA5 PRT1CF ; /* PORT 1 CONFIGURATION */
-sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
-sfr at 0xA6 PRT2CF ; /* PORT 2 CONFIGURATION */
-sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
-sfr at 0xA7 PRT3CF ; /* PORT 3 CONFIGURATION */
-sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
-sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
-sfr at 0xA9 SADDR0 ; /* UART0 Slave Address */
-sfr at 0xAA ADC1CN ; /* ADC 1 CONTROL */
-sfr at 0xAB ADC1CF ; /* ADC 1 CONFIGURATION */
-sfr at 0xAC AMX1SL ; /* ADC 1 MUX CHANNEL SELECTION */
-sfr at 0xAD P3IF ; /* PORT 3 EXTERNAL INTERRUPT FLAGS */
-sfr at 0xAE SADEN1 ; /* UART1 Slave Address Enable */
-sfr at 0xAF EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
-sfr at 0xAF _XPAGE ; /* XDATA/PDATA PAGE */
-sfr at 0xB0 P3 ; /* PORT 3 */
-sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
-sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
-sfr at 0xB5 P74OUT ; /* PORT 4 THROUGH 7 OUTPUT MODE CONFIGURATION */
-sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
-sfr at 0xB7 FLACL ; /* FLASH ACESS LIMIT */
-sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
-sfr at 0xB9 SADEN0 ; /* UART0 Slave Address Enable */
-sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
-sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
-sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
-sfr at 0xBD P1MDIN ; /* PORT 1 Input Mode */
-sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
-sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
-sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
-sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
-sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
-sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
-sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
-sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
-sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
-sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
-sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */
-sfr at 0xC9 T4CON ; /* TIMER 4 CONTROL */
-sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
-sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
-sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
-sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
-sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
-sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
-sfr at 0xD5 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
-sfr at 0xD6 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
-sfr at 0xD7 DAC1CN ; /* DAC 1 CONTROL */
-sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
-sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
-sfr at 0xDA PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
-sfr at 0xDB PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
-sfr at 0xDC PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
-sfr at 0xDD PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
-sfr at 0xDE PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
-sfr at 0xE0 ACC ; /* ACCUMULATOR */
-sfr at 0xE1 XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
-sfr at 0xE2 XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
-sfr at 0xE3 XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
-sfr at 0xE4 RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xE5 RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
-sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
-sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
-sfr at 0xE9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
-sfr at 0xEA PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
-sfr at 0xEB PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
-sfr at 0xEC PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
-sfr at 0xED PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
-sfr at 0xEE PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
-sfr at 0xEF RSTSRC ; /* RESET SOURCE */
-sfr at 0xF0 B ; /* B REGISTER */
-sfr at 0xF1 SCON1 ; /* UART1 CONTROL */
-sfr at 0xF2 SBUF1 ; /* UART1 DATA */
-sfr at 0xF3 SADDR1 ; /* UART1 Slave Address */
-sfr at 0xF4 TL4 ; /* TIMER 4 DATA - LOW BYTE */
-sfr at 0xF5 TH4 ; /* TIMER 4 DATA - HIGH BYTE */
-sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
-sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
-sfr at 0xF8 SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
-sfr at 0xF9 PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
-sfr at 0xFA PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
-sfr at 0xFB PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
-sfr at 0xFC PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
-sfr at 0xFD PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
-sfr at 0xFE PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
-sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
+__sfr __at 0x80 P0 ; /* PORT 0 */
+__sfr __at 0x81 SP ; /* STACK POINTER */
+__sfr __at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
+__sfr __at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
+__sfr __at 0x84 P4 ; /* PORT 4 */
+__sfr __at 0x85 P5 ; /* PORT 5 */
+__sfr __at 0x86 P6 ; /* PORT 6 */
+__sfr __at 0x87 PCON ; /* POWER CONTROL */
+__sfr __at 0x88 TCON ; /* TIMER CONTROL */
+__sfr __at 0x89 TMOD ; /* TIMER MODE */
+__sfr __at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
+__sfr __at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
+__sfr __at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
+__sfr __at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
+__sfr __at 0x8E CKCON ; /* CLOCK CONTROL */
+__sfr __at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
+__sfr __at 0x90 P1 ; /* PORT 1 */
+__sfr __at 0x91 TMR3CN ; /* TIMER 3 CONTROL */
+__sfr __at 0x92 TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
+__sfr __at 0x93 TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
+__sfr __at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */
+__sfr __at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */
+__sfr __at 0x96 P7 ; /* PORT 7 */
+__sfr __at 0x98 SCON ; /* UART0 CONTROL */
+__sfr __at 0x98 SCON0 ; /* UART0 CONTROL */
+__sfr __at 0x99 SBUF ; /* UART0 BUFFER */
+__sfr __at 0x99 SBUF0 ; /* UART0 BUFFER */
+__sfr __at 0x9A SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
+__sfr __at 0x9B SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
+__sfr __at 0x9C ADC1 ; /* ADC 1 DATA */
+__sfr __at 0x9D SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
+__sfr __at 0x9E CPT0CN ; /* COMPARATOR 0 CONTROL */
+__sfr __at 0x9F CPT1CN ; /* COMPARATOR 1 CONTROL */
+__sfr __at 0xA0 P2 ; /* PORT 2 */
+__sfr __at 0xA1 EMI0TC ; /* External Memory Timing Control */
+__sfr __at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */
+__sfr __at 0xA4 PRT0CF ; /* PORT 0 CONFIGURATION */
+__sfr __at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA5 PRT1CF ; /* PORT 1 CONFIGURATION */
+__sfr __at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA6 PRT2CF ; /* PORT 2 CONFIGURATION */
+__sfr __at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA7 PRT3CF ; /* PORT 3 CONFIGURATION */
+__sfr __at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA8 IE ; /* INTERRUPT ENABLE */
+__sfr __at 0xA9 SADDR0 ; /* UART0 Slave Address */
+__sfr __at 0xAA ADC1CN ; /* ADC 1 CONTROL */
+__sfr __at 0xAB ADC1CF ; /* ADC 1 CONFIGURATION */
+__sfr __at 0xAC AMX1SL ; /* ADC 1 MUX CHANNEL SELECTION */
+__sfr __at 0xAD P3IF ; /* PORT 3 EXTERNAL INTERRUPT FLAGS */
+__sfr __at 0xAE SADEN1 ; /* UART1 Slave Address Enable */
+__sfr __at 0xAF EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
+__sfr __at 0xAF _XPAGE ; /* XDATA/PDATA PAGE */
+__sfr __at 0xB0 P3 ; /* PORT 3 */
+__sfr __at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
+__sfr __at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
+__sfr __at 0xB5 P74OUT ; /* PORT 4 THROUGH 7 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
+__sfr __at 0xB7 FLACL ; /* FLASH ACESS LIMIT */
+__sfr __at 0xB8 IP ; /* INTERRUPT PRIORITY */
+__sfr __at 0xB9 SADEN0 ; /* UART0 Slave Address Enable */
+__sfr __at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
+__sfr __at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
+__sfr __at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
+__sfr __at 0xBD P1MDIN ; /* PORT 1 Input Mode */
+__sfr __at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
+__sfr __at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
+__sfr __at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
+__sfr __at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
+__sfr __at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
+__sfr __at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
+__sfr __at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
+__sfr __at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
+__sfr __at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
+__sfr __at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
+__sfr __at 0xC8 T2CON ; /* TIMER 2 CONTROL */
+__sfr __at 0xC9 T4CON ; /* TIMER 4 CONTROL */
+__sfr __at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
+__sfr __at 0xD0 PSW ; /* PROGRAM STATUS WORD */
+__sfr __at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
+__sfr __at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
+__sfr __at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
+__sfr __at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
+__sfr __at 0xD5 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
+__sfr __at 0xD6 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
+__sfr __at 0xD7 DAC1CN ; /* DAC 1 CONTROL */
+__sfr __at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
+__sfr __at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
+__sfr __at 0xDA PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
+__sfr __at 0xDB PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
+__sfr __at 0xDC PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
+__sfr __at 0xDD PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
+__sfr __at 0xDE PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
+__sfr __at 0xE0 ACC ; /* ACCUMULATOR */
+__sfr __at 0xE1 XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
+__sfr __at 0xE2 XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
+__sfr __at 0xE3 XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
+__sfr __at 0xE4 RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xE5 RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
+__sfr __at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
+__sfr __at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
+__sfr __at 0xE9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
+__sfr __at 0xEA PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
+__sfr __at 0xEB PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
+__sfr __at 0xEC PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
+__sfr __at 0xED PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
+__sfr __at 0xEE PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
+__sfr __at 0xEF RSTSRC ; /* RESET SOURCE */
+__sfr __at 0xF0 B ; /* B REGISTER */
+__sfr __at 0xF1 SCON1 ; /* UART1 CONTROL */
+__sfr __at 0xF2 SBUF1 ; /* UART1 DATA */
+__sfr __at 0xF3 SADDR1 ; /* UART1 Slave Address */
+__sfr __at 0xF4 TL4 ; /* TIMER 4 DATA - LOW BYTE */
+__sfr __at 0xF5 TH4 ; /* TIMER 4 DATA - HIGH BYTE */
+__sfr __at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
+__sfr __at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
+__sfr __at 0xF8 SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
+__sfr __at 0xF9 PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
+__sfr __at 0xFA PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
+__sfr __at 0xFB PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
+__sfr __at 0xFC PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
+__sfr __at 0xFD PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
+__sfr __at 0xFE PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
+__sfr __at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
/* BIT Registers */
/* P0 0x80 */
-sbit at 0x80 P0_0 ;
-sbit at 0x81 P0_1 ;
-sbit at 0x82 P0_2 ;
-sbit at 0x83 P0_3 ;
-sbit at 0x84 P0_4 ;
-sbit at 0x85 P0_5 ;
-sbit at 0x86 P0_6 ;
-sbit at 0x87 P0_7 ;
+__sbit __at 0x80 P0_0 ;
+__sbit __at 0x81 P0_1 ;
+__sbit __at 0x82 P0_2 ;
+__sbit __at 0x83 P0_3 ;
+__sbit __at 0x84 P0_4 ;
+__sbit __at 0x85 P0_5 ;
+__sbit __at 0x86 P0_6 ;
+__sbit __at 0x87 P0_7 ;
/* TCON 0x88 */
-sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
-sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
-sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
-sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
-sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
-sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
-sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
-sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
+__sbit __at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
+__sbit __at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
+__sbit __at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
+__sbit __at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
+__sbit __at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
+__sbit __at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
+__sbit __at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
+__sbit __at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
/* P1 0x90 */
-sbit at 0x90 P1_0 ;
-sbit at 0x91 P1_1 ;
-sbit at 0x92 P1_2 ;
-sbit at 0x93 P1_3 ;
-sbit at 0x94 P1_4 ;
-sbit at 0x95 P1_5 ;
-sbit at 0x96 P1_6 ;
-sbit at 0x97 P1_7 ;
+__sbit __at 0x90 P1_0 ;
+__sbit __at 0x91 P1_1 ;
+__sbit __at 0x92 P1_2 ;
+__sbit __at 0x93 P1_3 ;
+__sbit __at 0x94 P1_4 ;
+__sbit __at 0x95 P1_5 ;
+__sbit __at 0x96 P1_6 ;
+__sbit __at 0x97 P1_7 ;
/* SCON 0x98 */
-sbit at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
-sbit at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
-sbit at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
-sbit at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
-sbit at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */
-sbit at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */
-sbit at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
-sbit at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
-sbit at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */
-sbit at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */
-sbit at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
-sbit at 0x9D SM20 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
-sbit at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
-sbit at 0x9E SM1 ; /* SCON.6 - SERIAL MODE CONTROL BIT 1 */
-sbit at 0x9E SM10 ; /* SCON.6 - SERIAL MODE CONTROL BIT 1 */
-sbit at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
-sbit at 0x9F SM00 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
-sbit at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
+__sbit __at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
+__sbit __at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
+__sbit __at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
+__sbit __at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
+__sbit __at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */
+__sbit __at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */
+__sbit __at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
+__sbit __at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
+__sbit __at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */
+__sbit __at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */
+__sbit __at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
+__sbit __at 0x9D SM20 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
+__sbit __at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
+__sbit __at 0x9E SM1 ; /* SCON.6 - SERIAL MODE CONTROL BIT 1 */
+__sbit __at 0x9E SM10 ; /* SCON.6 - SERIAL MODE CONTROL BIT 1 */
+__sbit __at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
+__sbit __at 0x9F SM00 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
+__sbit __at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
/* P2 0xA0 */
-sbit at 0xA0 P2_0 ;
-sbit at 0xA1 P2_1 ;
-sbit at 0xA2 P2_2 ;
-sbit at 0xA3 P2_3 ;
-sbit at 0xA4 P2_4 ;
-sbit at 0xA5 P2_5 ;
-sbit at 0xA6 P2_6 ;
-sbit at 0xA7 P2_7 ;
+__sbit __at 0xA0 P2_0 ;
+__sbit __at 0xA1 P2_1 ;
+__sbit __at 0xA2 P2_2 ;
+__sbit __at 0xA3 P2_3 ;
+__sbit __at 0xA4 P2_4 ;
+__sbit __at 0xA5 P2_5 ;
+__sbit __at 0xA6 P2_6 ;
+__sbit __at 0xA7 P2_7 ;
/* IE 0xA8 */
-sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
-sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
-sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
-sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
-sbit at 0xAC ES ; /* SERIAL PORT 0 INTERRUPT ENABLE */
-sbit at 0xAC ES0 ; /* SERIAL PORT 0 INTERRUPT ENABLE */
-sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
-sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
+__sbit __at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
+__sbit __at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
+__sbit __at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
+__sbit __at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
+__sbit __at 0xAC ES ; /* SERIAL PORT 0 INTERRUPT ENABLE */
+__sbit __at 0xAC ES0 ; /* SERIAL PORT 0 INTERRUPT ENABLE */
+__sbit __at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
+__sbit __at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
/* P3 0xB0 */
-sbit at 0xB0 P3_0 ;
-sbit at 0xB1 P3_1 ;
-sbit at 0xB2 P3_2 ;
-sbit at 0xB3 P3_3 ;
-sbit at 0xB4 P3_4 ;
-sbit at 0xB5 P3_5 ;
-sbit at 0xB6 P3_6 ;
-sbit at 0xB7 P3_7 ;
+__sbit __at 0xB0 P3_0 ;
+__sbit __at 0xB1 P3_1 ;
+__sbit __at 0xB2 P3_2 ;
+__sbit __at 0xB3 P3_3 ;
+__sbit __at 0xB4 P3_4 ;
+__sbit __at 0xB5 P3_5 ;
+__sbit __at 0xB6 P3_6 ;
+__sbit __at 0xB7 P3_7 ;
/* IP 0xB8 */
-sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
-sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
-sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
-sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */
-sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */
-sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */
+__sbit __at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
+__sbit __at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
+__sbit __at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
+__sbit __at 0xBB PT1 ; /* TIMER 1 PRIORITY */
+__sbit __at 0xBC PS ; /* SERIAL PORT PRIORITY */
+__sbit __at 0xBD PT2 ; /* TIMER 2 PRIORITY */
/* SMB0CN 0xC0 */
-sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
-sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
-sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
-sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
-sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
-sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */
-sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
-sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */
+__sbit __at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
+__sbit __at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
+__sbit __at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
+__sbit __at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
+__sbit __at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
+__sbit __at 0xC5 STA ; /* SMBUS 0 START FLAG */
+__sbit __at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
+__sbit __at 0xC7 BUSY ; /* SMBUS 0 BUSY */
/* T2CON 0xC8 */
-sbit at 0xC8 CPRL2 ; /* CAPTURE OR RELOAD SELECT */
-sbit at 0xC9 CT2 ; /* TIMER OR COUNTER SELECT */
-sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
-sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
-sbit at 0xCC TCLK ; /* TRANSMIT CLOCK FLAG */
-sbit at 0xCD RCLK ; /* RECEIVE CLOCK FLAG */
-sbit at 0xCE EXF2 ; /* EXTERNAL FLAG */
-sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
+__sbit __at 0xC8 CPRL2 ; /* CAPTURE OR RELOAD SELECT */
+__sbit __at 0xC9 CT2 ; /* TIMER OR COUNTER SELECT */
+__sbit __at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
+__sbit __at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
+__sbit __at 0xCC TCLK ; /* TRANSMIT CLOCK FLAG */
+__sbit __at 0xCD RCLK ; /* RECEIVE CLOCK FLAG */
+__sbit __at 0xCE EXF2 ; /* EXTERNAL FLAG */
+__sbit __at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
/* PSW 0xD0 */
-sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
-sbit at 0xD1 F1 ; /* USER FLAG 1 */
-sbit at 0xD2 OV ; /* OVERFLOW FLAG */
-sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
-sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
-sbit at 0xD5 F0 ; /* USER FLAG 0 */
-sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
-sbit at 0xD7 CY ; /* CARRY FLAG */
+__sbit __at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
+__sbit __at 0xD1 F1 ; /* USER FLAG 1 */
+__sbit __at 0xD2 OV ; /* OVERFLOW FLAG */
+__sbit __at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
+__sbit __at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
+__sbit __at 0xD5 F0 ; /* USER FLAG 0 */
+__sbit __at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
+__sbit __at 0xD7 CY ; /* CARRY FLAG */
/* PCA0CN 0xD8H */
-sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
-sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
-sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
-sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
-sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
-sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
-sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
+__sbit __at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
+__sbit __at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
+__sbit __at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
+__sbit __at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
+__sbit __at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
+__sbit __at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
+__sbit __at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
/* ADC0CN 0xE8H */
-sbit at 0xE8 ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
-sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
-sbit at 0xE9 ADWINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
-sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
-sbit at 0xEA ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
-sbit at 0xEA AD0CM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
-sbit at 0xEB ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
-sbit at 0xEB AD0CM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
-sbit at 0xEC ADBUSY ; /* ADC 0 BUSY FLAG */
-sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
-sbit at 0xED ADCINT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
-sbit at 0xED AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
-sbit at 0xEE ADCTM ; /* ADC 0 TRACK MODE */
-sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
-sbit at 0xEF ADCEN ; /* ADC 0 ENABLE */
-sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */
+__sbit __at 0xE8 ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
+__sbit __at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
+__sbit __at 0xE9 ADWINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
+__sbit __at 0xE9 AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
+__sbit __at 0xEA ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
+__sbit __at 0xEA AD0CM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
+__sbit __at 0xEB ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
+__sbit __at 0xEB AD0CM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
+__sbit __at 0xEC ADBUSY ; /* ADC 0 BUSY FLAG */
+__sbit __at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
+__sbit __at 0xED ADCINT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
+__sbit __at 0xED AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
+__sbit __at 0xEE ADCTM ; /* ADC 0 TRACK MODE */
+__sbit __at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
+__sbit __at 0xEF ADCEN ; /* ADC 0 ENABLE */
+__sbit __at 0xEF AD0EN ; /* ADC 0 ENABLE */
/* SPI0CN 0xF8H */
-sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
-sbit at 0xF9 MSTEN ; /* SPI 0 MASTER ENABLE */
-sbit at 0xFA SLVSEL ; /* SPI 0 SLAVE SELECT */
-sbit at 0xFB TXBSY ; /* SPI 0 TX BUSY FLAG */
-sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
-sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
-sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
-sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
+__sbit __at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
+__sbit __at 0xF9 MSTEN ; /* SPI 0 MASTER ENABLE */
+__sbit __at 0xFA SLVSEL ; /* SPI 0 SLAVE SELECT */
+__sbit __at 0xFB TXBSY ; /* SPI 0 TX BUSY FLAG */
+__sbit __at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
+__sbit __at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
+__sbit __at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
+__sbit __at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
/* Predefined SFR Bit Masks */
/* BYTE Registers */
/* All Pages */
-sfr at 0x80 P0 ; /* PORT 0 */
-sfr at 0x81 SP ; /* STACK POINTER */
-sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
-sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
-sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */
-sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */
-sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */
-sfr at 0x87 PCON ; /* POWER CONTROL */
-sfr at 0x90 P1 ; /* PORT 1 */
-sfr at 0xA0 P2 ; /* PORT 2 */
-sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
-sfr at 0xB0 P3 ; /* PORT 3 */
-sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
-sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
-sfr at 0xE0 ACC ; /* ACCUMULATOR */
-sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
-sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
-sfr at 0xF0 B ; /* B REGISTER */
-sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
-sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
-sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
+__sfr __at 0x80 P0 ; /* PORT 0 */
+__sfr __at 0x81 SP ; /* STACK POINTER */
+__sfr __at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
+__sfr __at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
+__sfr __at 0x84 SFRPAGE ; /* SFR PAGE SELECT */
+__sfr __at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */
+__sfr __at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */
+__sfr __at 0x87 PCON ; /* POWER CONTROL */
+__sfr __at 0x90 P1 ; /* PORT 1 */
+__sfr __at 0xA0 P2 ; /* PORT 2 */
+__sfr __at 0xA8 IE ; /* INTERRUPT ENABLE */
+__sfr __at 0xB0 P3 ; /* PORT 3 */
+__sfr __at 0xB8 IP ; /* INTERRUPT PRIORITY */
+__sfr __at 0xD0 PSW ; /* PROGRAM STATUS WORD */
+__sfr __at 0xE0 ACC ; /* ACCUMULATOR */
+__sfr __at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
+__sfr __at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
+__sfr __at 0xF0 B ; /* B REGISTER */
+__sfr __at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
+__sfr __at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
+__sfr __at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
/* Page 0x00 */
-sfr at 0x88 TCON ; /* TIMER CONTROL */
-sfr at 0x89 TMOD ; /* TIMER MODE */
-sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
-sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
-sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
-sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
-sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */
-sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */
-sfr at 0x91 SSTA0 ; /* UART 0 STATUS */
-sfr at 0x98 SCON0 ; /* UART 0 CONTROL */
-sfr at 0x98 SCON ; /* UART 0 CONTROL */
-sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */
-sfr at 0x99 SBUF ; /* UART 0 BUFFER */
-sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */
-sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */
-sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */
-sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */
-sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */
-sfr at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */
-sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */
-sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */
-sfr at 0xB7 FLSCL ; /* FLASH SCALE */
-sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */
-sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
-sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
-sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
-sfr at 0xBD AMX0PRT ; /* ADC 0 PORT 3 I/O PIN SELECT */
-sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
-sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
-sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
-sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
-sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
-sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
-sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
-sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
-sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
-sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
-sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
-sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */
-sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
-sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
-sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
-sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
-sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
-sfr at 0xD6 HVA0CN ; /* HIGH VOLTAGE DIFFERENTIAL AMP CONTROL */
-sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
-sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
-sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */
-sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */
-sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */
-sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */
-sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */
-sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */
-sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
-sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xEF RSTSRC ; /* RESET SOURCE */
-sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */
-sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
-sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
-sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
+__sfr __at 0x88 TCON ; /* TIMER CONTROL */
+__sfr __at 0x89 TMOD ; /* TIMER MODE */
+__sfr __at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
+__sfr __at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
+__sfr __at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
+__sfr __at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
+__sfr __at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */
+__sfr __at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */
+__sfr __at 0x91 SSTA0 ; /* UART 0 STATUS */
+__sfr __at 0x98 SCON0 ; /* UART 0 CONTROL */
+__sfr __at 0x98 SCON ; /* UART 0 CONTROL */
+__sfr __at 0x99 SBUF0 ; /* UART 0 BUFFER */
+__sfr __at 0x99 SBUF ; /* UART 0 BUFFER */
+__sfr __at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */
+__sfr __at 0x9B SPI0DAT ; /* SPI 0 DATA */
+__sfr __at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */
+__sfr __at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */
+__sfr __at 0xA2 EMI0CN ; /* EMIF CONTROL */
+__sfr __at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */
+__sfr __at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */
+__sfr __at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */
+__sfr __at 0xB7 FLSCL ; /* FLASH SCALE */
+__sfr __at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */
+__sfr __at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
+__sfr __at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
+__sfr __at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
+__sfr __at 0xBD AMX0PRT ; /* ADC 0 PORT 3 I/O PIN SELECT */
+__sfr __at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
+__sfr __at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
+__sfr __at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
+__sfr __at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
+__sfr __at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
+__sfr __at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
+__sfr __at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
+__sfr __at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
+__sfr __at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
+__sfr __at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
+__sfr __at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
+__sfr __at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */
+__sfr __at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
+__sfr __at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
+__sfr __at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
+__sfr __at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
+__sfr __at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
+__sfr __at 0xD6 HVA0CN ; /* HIGH VOLTAGE DIFFERENTIAL AMP CONTROL */
+__sfr __at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
+__sfr __at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
+__sfr __at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */
+__sfr __at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */
+__sfr __at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */
+__sfr __at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */
+__sfr __at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */
+__sfr __at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */
+__sfr __at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
+__sfr __at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
+__sfr __at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
+__sfr __at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
+__sfr __at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
+__sfr __at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
+__sfr __at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
+__sfr __at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
+__sfr __at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
+__sfr __at 0xEF RSTSRC ; /* RESET SOURCE */
+__sfr __at 0xF8 SPI0CN ; /* SPI 0 CONTROL */
+__sfr __at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
+__sfr __at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
+__sfr __at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
+__sfr __at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
+__sfr __at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
+__sfr __at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
/* Page 0x01 */
-sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */
-sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */
-sfr at 0x98 SCON1 ; /* UART 1 CONTROL */
-sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */
-sfr at 0xC0 CAN0STA ; /* CAN 0 STATUS */
-sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */
-sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */
-sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */
-sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */
-sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
-sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
-sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */
-sfr at 0xD8 CAN0DATL ; /* CAN 0 DATA REGISTER LOW */
-sfr at 0xD9 CAN0DATH ; /* CAN 0 DATA REGISTER HIGH */
-sfr at 0xDA CAN0ADR ; /* CAN 0 ADDRESS */
-sfr at 0xDB CAN0TST ; /* CAN 0 TEST REGISTER */
-sfr at 0xF8 CAN0CN ; /* CAN 0 CONTROL */
+__sfr __at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */
+__sfr __at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */
+__sfr __at 0x98 SCON1 ; /* UART 1 CONTROL */
+__sfr __at 0x99 SBUF1 ; /* UART 1 BUFFER */
+__sfr __at 0xC0 CAN0STA ; /* CAN 0 STATUS */
+__sfr __at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */
+__sfr __at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */
+__sfr __at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */
+__sfr __at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */
+__sfr __at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
+__sfr __at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
+__sfr __at 0xD4 DAC1CN ; /* DAC 1 CONTROL */
+__sfr __at 0xD8 CAN0DATL ; /* CAN 0 DATA REGISTER LOW */
+__sfr __at 0xD9 CAN0DATH ; /* CAN 0 DATA REGISTER HIGH */
+__sfr __at 0xDA CAN0ADR ; /* CAN 0 ADDRESS */
+__sfr __at 0xDB CAN0TST ; /* CAN 0 TEST REGISTER */
+__sfr __at 0xF8 CAN0CN ; /* CAN 0 CONTROL */
/* Page 0x02 */
-sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */
-sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */
-sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */
-sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */
-sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */
-sfr at 0xBE ADC2 ; /* ADC 2 DATA */
-sfr at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */
-sfr at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */
-sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */
-sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */
-sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */
-sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */
-sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */
+__sfr __at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */
+__sfr __at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */
+__sfr __at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */
+__sfr __at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */
+__sfr __at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */
+__sfr __at 0xBE ADC2 ; /* ADC 2 DATA */
+__sfr __at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */
+__sfr __at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */
+__sfr __at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */
+__sfr __at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */
+__sfr __at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */
+__sfr __at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */
+__sfr __at 0xE8 ADC2CN ; /* ADC 2 CONTROL */
/* Page 0x03 */
-sfr at 0x88 CPT2CN ; /* COMPARATOR 2 CONTROL */
-sfr at 0x89 CPT2MD ; /* COMPARATOR 2 CONFIGURATION */
+__sfr __at 0x88 CPT2CN ; /* COMPARATOR 2 CONTROL */
+__sfr __at 0x89 CPT2MD ; /* COMPARATOR 2 CONFIGURATION */
/* Page 0x0F */
-sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
-sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
-sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
-sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */
-sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */
-sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */
-sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */
-sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */
-sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */
-sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */
-sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */
-sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
-sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
-sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */
-sfr at 0xAE P2MDIN ; /* PORT 2 INPUT MODE */
-sfr at 0xAF P3MDIN ; /* PORT 3 INPUT MODE */
-sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */
-sfr at 0xC8 P4 ; /* PORT 4 */
-sfr at 0xD8 P5 ; /* PORT 5 */
-sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */
-sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */
-sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */
-sfr at 0xE4 XBR3 ; /* CROSSBAR CONFIGURATION REGISTER 3 */
-sfr at 0xE8 P6 ; /* PORT 6 */
-sfr at 0xF8 P7 ; /* PORT 7 */
+__sfr __at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
+__sfr __at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
+__sfr __at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
+__sfr __at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */
+__sfr __at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */
+__sfr __at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */
+__sfr __at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */
+__sfr __at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */
+__sfr __at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */
+__sfr __at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */
+__sfr __at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */
+__sfr __at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */
+__sfr __at 0xAE P2MDIN ; /* PORT 2 INPUT MODE */
+__sfr __at 0xAF P3MDIN ; /* PORT 3 INPUT MODE */
+__sfr __at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */
+__sfr __at 0xC8 P4 ; /* PORT 4 */
+__sfr __at 0xD8 P5 ; /* PORT 5 */
+__sfr __at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */
+__sfr __at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */
+__sfr __at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */
+__sfr __at 0xE4 XBR3 ; /* CROSSBAR CONFIGURATION REGISTER 3 */
+__sfr __at 0xE8 P6 ; /* PORT 6 */
+__sfr __at 0xF8 P7 ; /* PORT 7 */
/* BIT Registers */
/* P0 0x80 */
-sbit at 0x80 P0_0 ;
-sbit at 0x81 P0_1 ;
-sbit at 0x82 P0_2 ;
-sbit at 0x83 P0_3 ;
-sbit at 0x84 P0_4 ;
-sbit at 0x85 P0_5 ;
-sbit at 0x86 P0_6 ;
-sbit at 0x87 P0_7 ;
+__sbit __at 0x80 P0_0 ;
+__sbit __at 0x81 P0_1 ;
+__sbit __at 0x82 P0_2 ;
+__sbit __at 0x83 P0_3 ;
+__sbit __at 0x84 P0_4 ;
+__sbit __at 0x85 P0_5 ;
+__sbit __at 0x86 P0_6 ;
+__sbit __at 0x87 P0_7 ;
/* TCON 0x88 */
-sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
-sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
-sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
-sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
-sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
-sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
-sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
-sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
+__sbit __at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
+__sbit __at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
+__sbit __at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
+__sbit __at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
+__sbit __at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
+__sbit __at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
+__sbit __at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
+__sbit __at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
/* CPT0CN 0x88 */
-sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
-sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
-sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
-sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
-sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */
-sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */
-sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */
-sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */
+__sbit __at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
+__sbit __at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
+__sbit __at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
+__sbit __at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
+__sbit __at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */
+__sbit __at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */
+__sbit __at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */
+__sbit __at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */
/* CPT1CN 0x88 */
-sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
-sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
-sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
-sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
-sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */
-sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */
-sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */
-sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */
+__sbit __at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
+__sbit __at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
+__sbit __at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
+__sbit __at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
+__sbit __at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */
+__sbit __at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */
+__sbit __at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */
+__sbit __at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */
/* CPT2CN 0x88 */
-sbit at 0x88 CP2HYN0 ; /* COMPARATOR 2 NEGATIVE HYSTERESIS 0 */
-sbit at 0x89 CP2HYN1 ; /* COMPARATOR 2 NEGATIVE HYSTERESIS 1 */
-sbit at 0x8A CP2HYP0 ; /* COMPARATOR 2 POSITIVE HYSTERESIS 0 */
-sbit at 0x8B CP2HYP1 ; /* COMPARATOR 2 POSITIVE HYSTERESIS 1 */
-sbit at 0x8C CP2FIF ; /* COMPARATOR 2 FALLING EDGE INTERRUPT */
-sbit at 0x8D CP2RIF ; /* COMPARATOR 2 RISING EDGE INTERRUPT */
-sbit at 0x8E CP2OUT ; /* COMPARATOR 2 OUTPUT */
-sbit at 0x8F CP2EN ; /* COMPARATOR 2 ENABLE */
+__sbit __at 0x88 CP2HYN0 ; /* COMPARATOR 2 NEGATIVE HYSTERESIS 0 */
+__sbit __at 0x89 CP2HYN1 ; /* COMPARATOR 2 NEGATIVE HYSTERESIS 1 */
+__sbit __at 0x8A CP2HYP0 ; /* COMPARATOR 2 POSITIVE HYSTERESIS 0 */
+__sbit __at 0x8B CP2HYP1 ; /* COMPARATOR 2 POSITIVE HYSTERESIS 1 */
+__sbit __at 0x8C CP2FIF ; /* COMPARATOR 2 FALLING EDGE INTERRUPT */
+__sbit __at 0x8D CP2RIF ; /* COMPARATOR 2 RISING EDGE INTERRUPT */
+__sbit __at 0x8E CP2OUT ; /* COMPARATOR 2 OUTPUT */
+__sbit __at 0x8F CP2EN ; /* COMPARATOR 2 ENABLE */
/* P1 0x90 */
-sbit at 0x90 P1_0 ;
-sbit at 0x91 P1_1 ;
-sbit at 0x92 P1_2 ;
-sbit at 0x93 P1_3 ;
-sbit at 0x94 P1_4 ;
-sbit at 0x95 P1_5 ;
-sbit at 0x96 P1_6 ;
-sbit at 0x97 P1_7 ;
+__sbit __at 0x90 P1_0 ;
+__sbit __at 0x91 P1_1 ;
+__sbit __at 0x92 P1_2 ;
+__sbit __at 0x93 P1_3 ;
+__sbit __at 0x94 P1_4 ;
+__sbit __at 0x95 P1_5 ;
+__sbit __at 0x96 P1_6 ;
+__sbit __at 0x97 P1_7 ;
/* SCON0 0x98 */
-sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */
-sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */
-sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */
-sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */
-sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */
-sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */
-sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */
-sbit at 0x9C REN ; /* UART 0 RX ENABLE */
-sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */
-sbit at 0x9E SM10 ; /* UART 0 MODE 1 */
-sbit at 0x9F SM00 ; /* UART 0 MODE 0 */
+__sbit __at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */
+__sbit __at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */
+__sbit __at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */
+__sbit __at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */
+__sbit __at 0x9A RB80 ; /* UART 0 RX BIT 8 */
+__sbit __at 0x9B TB80 ; /* UART 0 TX BIT 8 */
+__sbit __at 0x9C REN0 ; /* UART 0 RX ENABLE */
+__sbit __at 0x9C REN ; /* UART 0 RX ENABLE */
+__sbit __at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */
+__sbit __at 0x9E SM10 ; /* UART 0 MODE 1 */
+__sbit __at 0x9F SM00 ; /* UART 0 MODE 0 */
/* SCON1 0x98 */
-sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */
-sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */
-sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */
-sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */
-sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */
-sbit at 0x9D MCE1 ; /* UART 1 MCE */
-sbit at 0x9F S1MODE ; /* UART 1 MODE */
+__sbit __at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */
+__sbit __at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */
+__sbit __at 0x9A RB81 ; /* UART 1 RX BIT 8 */
+__sbit __at 0x9B TB81 ; /* UART 1 TX BIT 8 */
+__sbit __at 0x9C REN1 ; /* UART 1 RX ENABLE */
+__sbit __at 0x9D MCE1 ; /* UART 1 MCE */
+__sbit __at 0x9F S1MODE ; /* UART 1 MODE */
/* P2 0xA0 */
-sbit at 0xA0 P2_0 ;
-sbit at 0xA1 P2_1 ;
-sbit at 0xA2 P2_2 ;
-sbit at 0xA3 P2_3 ;
-sbit at 0xA4 P2_4 ;
-sbit at 0xA5 P2_5 ;
-sbit at 0xA6 P2_6 ;
-sbit at 0xA7 P2_7 ;
+__sbit __at 0xA0 P2_0 ;
+__sbit __at 0xA1 P2_1 ;
+__sbit __at 0xA2 P2_2 ;
+__sbit __at 0xA3 P2_3 ;
+__sbit __at 0xA4 P2_4 ;
+__sbit __at 0xA5 P2_5 ;
+__sbit __at 0xA6 P2_6 ;
+__sbit __at 0xA7 P2_7 ;
/* IE 0xA8 */
-sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
-sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
-sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
-sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
-sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */
-sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */
-sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
-sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
+__sbit __at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
+__sbit __at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
+__sbit __at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
+__sbit __at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
+__sbit __at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */
+__sbit __at 0xAC ES ; /* UART0 INTERRUPT ENABLE */
+__sbit __at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
+__sbit __at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
/* P3 0xB0 */
-sbit at 0xB0 P3_0 ;
-sbit at 0xB1 P3_1 ;
-sbit at 0xB2 P3_2 ;
-sbit at 0xB3 P3_3 ;
-sbit at 0xB4 P3_4 ;
-sbit at 0xB5 P3_5 ;
-sbit at 0xB6 P3_6 ;
-sbit at 0xB7 P3_7 ;
+__sbit __at 0xB0 P3_0 ;
+__sbit __at 0xB1 P3_1 ;
+__sbit __at 0xB2 P3_2 ;
+__sbit __at 0xB3 P3_3 ;
+__sbit __at 0xB4 P3_4 ;
+__sbit __at 0xB5 P3_5 ;
+__sbit __at 0xB6 P3_6 ;
+__sbit __at 0xB7 P3_7 ;
/* IP 0xB8 */
-sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
-sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
-sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
-sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */
-sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */
-sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */
+__sbit __at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
+__sbit __at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
+__sbit __at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
+__sbit __at 0xBB PT1 ; /* TIMER 1 PRIORITY */
+__sbit __at 0xBC PS ; /* SERIAL PORT PRIORITY */
+__sbit __at 0xBD PT2 ; /* TIMER 2 PRIORITY */
/* SMB0CN 0xC0 */
-sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
-sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
-sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
-sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
-sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
-sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */
-sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
-sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */
+__sbit __at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
+__sbit __at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
+__sbit __at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
+__sbit __at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
+__sbit __at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
+__sbit __at 0xC5 STA ; /* SMBUS 0 START FLAG */
+__sbit __at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
+__sbit __at 0xC7 BUSY ; /* SMBUS 0 BUSY */
/* CAN0STA 0xC0 */
-sbit at 0xC3 CANTXOK ; /* CAN TRANSMITTED A MESSAGE SUCCESSFULLY */
-sbit at 0xC4 CANRXOK ; /* CAN RECEIVED A MESSAGE SUCCESSFULLY */
-sbit at 0xC5 CANEPASS; /* CAN ERROR PASSIVE */
-sbit at 0xC6 CANEWARN; /* CAN WARNING STATUS */
-sbit at 0xC7 CANBOFF ; /* CAN BUSOFF STATUS */
+__sbit __at 0xC3 CANTXOK ; /* CAN TRANSMITTED A MESSAGE SUCCESSFULLY */
+__sbit __at 0xC4 CANRXOK ; /* CAN RECEIVED A MESSAGE SUCCESSFULLY */
+__sbit __at 0xC5 CANEPASS; /* CAN ERROR PASSIVE */
+__sbit __at 0xC6 CANEWARN; /* CAN WARNING STATUS */
+__sbit __at 0xC7 CANBOFF ; /* CAN BUSOFF STATUS */
/* TMR2CN 0xC8 */
-sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */
-sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */
-sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
-sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
-sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */
-sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
+__sbit __at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */
+__sbit __at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */
+__sbit __at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
+__sbit __at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
+__sbit __at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */
+__sbit __at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
/* TMR3CN 0xC8 */
-sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */
-sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */
-sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */
-sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */
-sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */
-sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */
+__sbit __at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */
+__sbit __at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */
+__sbit __at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */
+__sbit __at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */
+__sbit __at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */
+__sbit __at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */
/* TMR4CN 0xC8 */
-sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */
-sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */
-sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */
-sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */
-sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */
-sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */
+__sbit __at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */
+__sbit __at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */
+__sbit __at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */
+__sbit __at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */
+__sbit __at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */
+__sbit __at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */
/* P4 0xC8 */
-sbit at 0xC8 P4_0 ;
-sbit at 0xC9 P4_1 ;
-sbit at 0xCA P4_2 ;
-sbit at 0xCB P4_3 ;
-sbit at 0xCC P4_4 ;
-sbit at 0xCD P4_5 ;
-sbit at 0xCE P4_6 ;
-sbit at 0xCF P4_7 ;
+__sbit __at 0xC8 P4_0 ;
+__sbit __at 0xC9 P4_1 ;
+__sbit __at 0xCA P4_2 ;
+__sbit __at 0xCB P4_3 ;
+__sbit __at 0xCC P4_4 ;
+__sbit __at 0xCD P4_5 ;
+__sbit __at 0xCE P4_6 ;
+__sbit __at 0xCF P4_7 ;
/* PSW 0xD0 */
-sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
-sbit at 0xD1 F1 ; /* USER FLAG 1 */
-sbit at 0xD2 OV ; /* OVERFLOW FLAG */
-sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
-sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
-sbit at 0xD5 F0 ; /* USER FLAG 0 */
-sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
-sbit at 0xD7 CY ; /* CARRY FLAG */
+__sbit __at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
+__sbit __at 0xD1 F1 ; /* USER FLAG 1 */
+__sbit __at 0xD2 OV ; /* OVERFLOW FLAG */
+__sbit __at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
+__sbit __at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
+__sbit __at 0xD5 F0 ; /* USER FLAG 0 */
+__sbit __at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
+__sbit __at 0xD7 CY ; /* CARRY FLAG */
/* PCA0CN 0xD8 */
-sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
-sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
-sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
-sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
-sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
-sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */
-sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
-sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
+__sbit __at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
+__sbit __at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
+__sbit __at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
+__sbit __at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
+__sbit __at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
+__sbit __at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */
+__sbit __at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
+__sbit __at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
/* P5 0xD8 */
-sbit at 0xD8 P5_0 ;
-sbit at 0xD9 P5_1 ;
-sbit at 0xDA P5_2 ;
-sbit at 0xDB P5_3 ;
-sbit at 0xDC P5_4 ;
-sbit at 0xDD P5_5 ;
-sbit at 0xDE P5_6 ;
-sbit at 0xDF P5_7 ;
+__sbit __at 0xD8 P5_0 ;
+__sbit __at 0xD9 P5_1 ;
+__sbit __at 0xDA P5_2 ;
+__sbit __at 0xDB P5_3 ;
+__sbit __at 0xDC P5_4 ;
+__sbit __at 0xDD P5_5 ;
+__sbit __at 0xDE P5_6 ;
+__sbit __at 0xDF P5_7 ;
/* ADC0CN 0xE8 */
-sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
-sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */
-sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */
-sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */
-sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
-sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */
-sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
-sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */
+__sbit __at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
+__sbit __at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */
+__sbit __at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */
+__sbit __at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */
+__sbit __at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
+__sbit __at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */
+__sbit __at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
+__sbit __at 0xEF AD0EN ; /* ADC 0 ENABLE */
/* ADC2CN 0xE8 */
-sbit at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */
-sbit at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */
-sbit at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */
-sbit at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */
-sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */
-sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */
-sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */
-sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */
+__sbit __at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */
+__sbit __at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */
+__sbit __at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */
+__sbit __at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */
+__sbit __at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */
+__sbit __at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */
+__sbit __at 0xEE AD2TM ; /* ADC 2 TRACK MODE */
+__sbit __at 0xEF AD2EN ; /* ADC 2 ENABLE */
/* P6 0xE8 */
-sbit at 0xE8 P6_0 ;
-sbit at 0xE9 P6_1 ;
-sbit at 0xEA P6_2 ;
-sbit at 0xEB P6_3 ;
-sbit at 0xEC P6_4 ;
-sbit at 0xED P6_5 ;
-sbit at 0xEE P6_6 ;
-sbit at 0xEF P6_7 ;
+__sbit __at 0xE8 P6_0 ;
+__sbit __at 0xE9 P6_1 ;
+__sbit __at 0xEA P6_2 ;
+__sbit __at 0xEB P6_3 ;
+__sbit __at 0xEC P6_4 ;
+__sbit __at 0xED P6_5 ;
+__sbit __at 0xEE P6_6 ;
+__sbit __at 0xEF P6_7 ;
/* SPI0CN 0xF8 */
-sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
-sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */
-sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */
-sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */
-sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
-sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
-sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
-sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
+__sbit __at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
+__sbit __at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */
+__sbit __at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */
+__sbit __at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */
+__sbit __at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
+__sbit __at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
+__sbit __at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
+__sbit __at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
/* CAN0CN 0xF8 */
-sbit at 0xF8 CANINIT ; /* CAN INITIALIZATION */
-sbit at 0xF9 CANIE ; /* CAN MODULE INTERRUPT ENABLE */
-sbit at 0xFA CANSIE ; /* CAN STATUS CHANGE INTERRUPT ENABLE */
-sbit at 0xFB CANEIE ; /* CAN ERROR INTERRUPT ENABLE */
-sbit at 0xFC CANIF ; /* CAN INTERRUPT FLAG */
-sbit at 0xFD CANDAR ; /* CAN DISABLE AUTOMATIC RETRANSMISSION */
-sbit at 0xFE CANCCE ; /* CAN CONFIGURATION CHANGE ENABLE */
-sbit at 0xFF CANTEST ; /* CAN TEST MODE ENABLE */
+__sbit __at 0xF8 CANINIT ; /* CAN INITIALIZATION */
+__sbit __at 0xF9 CANIE ; /* CAN MODULE INTERRUPT ENABLE */
+__sbit __at 0xFA CANSIE ; /* CAN STATUS CHANGE INTERRUPT ENABLE */
+__sbit __at 0xFB CANEIE ; /* CAN ERROR INTERRUPT ENABLE */
+__sbit __at 0xFC CANIF ; /* CAN INTERRUPT FLAG */
+__sbit __at 0xFD CANDAR ; /* CAN DISABLE AUTOMATIC RETRANSMISSION */
+__sbit __at 0xFE CANCCE ; /* CAN CONFIGURATION CHANGE ENABLE */
+__sbit __at 0xFF CANTEST ; /* CAN TEST MODE ENABLE */
/* P7 0xF8 */
-sbit at 0xF8 P7_0 ;
-sbit at 0xF9 P7_1 ;
-sbit at 0xFA P7_2 ;
-sbit at 0xFB P7_3 ;
-sbit at 0xFC P7_4 ;
-sbit at 0xFD P7_5 ;
-sbit at 0xFE P7_6 ;
-sbit at 0xFF P7_7 ;
+__sbit __at 0xF8 P7_0 ;
+__sbit __at 0xF9 P7_1 ;
+__sbit __at 0xFA P7_2 ;
+__sbit __at 0xFB P7_3 ;
+__sbit __at 0xFC P7_4 ;
+__sbit __at 0xFD P7_5 ;
+__sbit __at 0xFE P7_6 ;
+__sbit __at 0xFF P7_7 ;
/* Predefined SFR Bit Masks */
/* BYTE Registers */
/* All Pages */
-sfr at 0x80 P0 ; /* PORT 0 */
-sfr at 0x81 SP ; /* STACK POINTER */
-sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
-sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
-sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */
-sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */
-sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */
-sfr at 0x87 PCON ; /* POWER CONTROL */
-sfr at 0x90 P1 ; /* PORT 1 */
-sfr at 0xA0 P2 ; /* PORT 2 */
-sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
-sfr at 0xB0 P3 ; /* PORT 3 */
-sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
-sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
-sfr at 0xE0 ACC ; /* ACCUMULATOR */
-sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
-sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
-sfr at 0xF0 B ; /* B REGISTER */
-sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
-sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
-sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
+__sfr __at 0x80 P0 ; /* PORT 0 */
+__sfr __at 0x81 SP ; /* STACK POINTER */
+__sfr __at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
+__sfr __at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
+__sfr __at 0x84 SFRPAGE ; /* SFR PAGE SELECT */
+__sfr __at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */
+__sfr __at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */
+__sfr __at 0x87 PCON ; /* POWER CONTROL */
+__sfr __at 0x90 P1 ; /* PORT 1 */
+__sfr __at 0xA0 P2 ; /* PORT 2 */
+__sfr __at 0xA8 IE ; /* INTERRUPT ENABLE */
+__sfr __at 0xB0 P3 ; /* PORT 3 */
+__sfr __at 0xB8 IP ; /* INTERRUPT PRIORITY */
+__sfr __at 0xD0 PSW ; /* PROGRAM STATUS WORD */
+__sfr __at 0xE0 ACC ; /* ACCUMULATOR */
+__sfr __at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
+__sfr __at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
+__sfr __at 0xF0 B ; /* B REGISTER */
+__sfr __at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
+__sfr __at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
+__sfr __at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
/* Page 0x00 */
-sfr at 0x88 TCON ; /* TIMER CONTROL */
-sfr at 0x89 TMOD ; /* TIMER MODE */
-sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
-sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
-sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
-sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
-sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */
-sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */
-sfr at 0x91 SSTA0 ; /* UART 0 STATUS */
-sfr at 0x98 SCON0 ; /* UART 0 CONTROL */
-sfr at 0x98 SCON ; /* UART 0 CONTROL */
-sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */
-sfr at 0x99 SBUF ; /* UART 0 BUFFER */
-sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */
-sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */
-sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */
-sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */
-sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */
-sfr at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */
-sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */
-sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */
-sfr at 0xB7 FLSCL ; /* FLASH SCALE */
-sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */
-sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
-sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
-sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
-sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
-sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
-sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
-sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
-sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
-sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
-sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
-sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
-sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
-sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
-sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */
-sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
-sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
-sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
-sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
-sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
-sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
-sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
-sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */
-sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */
-sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */
-sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */
-sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */
-sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */
-sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
-sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xEF RSTSRC ; /* RESET SOURCE */
-sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */
-sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
-sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
-sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
+__sfr __at 0x88 TCON ; /* TIMER CONTROL */
+__sfr __at 0x89 TMOD ; /* TIMER MODE */
+__sfr __at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
+__sfr __at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
+__sfr __at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
+__sfr __at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
+__sfr __at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */
+__sfr __at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */
+__sfr __at 0x91 SSTA0 ; /* UART 0 STATUS */
+__sfr __at 0x98 SCON0 ; /* UART 0 CONTROL */
+__sfr __at 0x98 SCON ; /* UART 0 CONTROL */
+__sfr __at 0x99 SBUF0 ; /* UART 0 BUFFER */
+__sfr __at 0x99 SBUF ; /* UART 0 BUFFER */
+__sfr __at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */
+__sfr __at 0x9B SPI0DAT ; /* SPI 0 DATA */
+__sfr __at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */
+__sfr __at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */
+__sfr __at 0xA2 EMI0CN ; /* EMIF CONTROL */
+__sfr __at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */
+__sfr __at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */
+__sfr __at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */
+__sfr __at 0xB7 FLSCL ; /* FLASH SCALE */
+__sfr __at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */
+__sfr __at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
+__sfr __at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
+__sfr __at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
+__sfr __at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
+__sfr __at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
+__sfr __at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
+__sfr __at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
+__sfr __at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
+__sfr __at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
+__sfr __at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
+__sfr __at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
+__sfr __at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
+__sfr __at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
+__sfr __at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */
+__sfr __at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
+__sfr __at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
+__sfr __at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
+__sfr __at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
+__sfr __at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
+__sfr __at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
+__sfr __at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
+__sfr __at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */
+__sfr __at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */
+__sfr __at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */
+__sfr __at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */
+__sfr __at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */
+__sfr __at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */
+__sfr __at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
+__sfr __at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
+__sfr __at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
+__sfr __at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
+__sfr __at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
+__sfr __at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
+__sfr __at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
+__sfr __at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
+__sfr __at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
+__sfr __at 0xEF RSTSRC ; /* RESET SOURCE */
+__sfr __at 0xF8 SPI0CN ; /* SPI 0 CONTROL */
+__sfr __at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
+__sfr __at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
+__sfr __at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
+__sfr __at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
+__sfr __at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
+__sfr __at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
/* Page 0x01 */
-sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */
-sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */
-sfr at 0x98 SCON1 ; /* UART 1 CONTROL */
-sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */
-sfr at 0xBC ADC1CF ; /* ADC 1 CONFIGURATION */
-sfr at 0xBE ADC1L ; /* ADC 1 DATA - LOW BYTE */
-sfr at 0xBF ADC1H ; /* ADC 1 DATA - HIGH BYTE */
-sfr at 0xC0 CAN0STA ; /* CAN 0 STATUS */
-sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */
-sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */
-sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */
-sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */
-sfr at 0xD1 REF1CN ; /* VOLTAGE REFERENCE 1 CONTROL */
-sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
-sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
-sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */
-sfr at 0xD8 CAN0DATL ; /* CAN 0 DATA REGISTER LOW */
-sfr at 0xD9 CAN0DATH ; /* CAN 0 DATA REGISTER HIGH */
-sfr at 0xDA CAN0ADR ; /* CAN 0 ADDRESS */
-sfr at 0xDB CAN0TST ; /* CAN 0 TEST REGISTER */
-sfr at 0xE8 ADC1CN ; /* ADC 1 CONTROL */
-sfr at 0xF8 CAN0CN ; /* CAN 0 CONTROL */
+__sfr __at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */
+__sfr __at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */
+__sfr __at 0x98 SCON1 ; /* UART 1 CONTROL */
+__sfr __at 0x99 SBUF1 ; /* UART 1 BUFFER */
+__sfr __at 0xBC ADC1CF ; /* ADC 1 CONFIGURATION */
+__sfr __at 0xBE ADC1L ; /* ADC 1 DATA - LOW BYTE */
+__sfr __at 0xBF ADC1H ; /* ADC 1 DATA - HIGH BYTE */
+__sfr __at 0xC0 CAN0STA ; /* CAN 0 STATUS */
+__sfr __at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */
+__sfr __at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */
+__sfr __at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */
+__sfr __at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */
+__sfr __at 0xD1 REF1CN ; /* VOLTAGE REFERENCE 1 CONTROL */
+__sfr __at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
+__sfr __at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
+__sfr __at 0xD4 DAC1CN ; /* DAC 1 CONTROL */
+__sfr __at 0xD8 CAN0DATL ; /* CAN 0 DATA REGISTER LOW */
+__sfr __at 0xD9 CAN0DATH ; /* CAN 0 DATA REGISTER HIGH */
+__sfr __at 0xDA CAN0ADR ; /* CAN 0 ADDRESS */
+__sfr __at 0xDB CAN0TST ; /* CAN 0 TEST REGISTER */
+__sfr __at 0xE8 ADC1CN ; /* ADC 1 CONTROL */
+__sfr __at 0xF8 CAN0CN ; /* CAN 0 CONTROL */
/* Page 0x02 */
-sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */
-sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */
-sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */
-sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */
-sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */
-sfr at 0xBE ADC2L ; /* ADC 2 DATA - LOW BYTE */
-sfr at 0xBF ADC2H ; /* ADC 2 DATA - HIGH BYTE */
-sfr at 0xC4 ADC2GTL ; /* ADC 2 GREATER-THAN REGISTER - LOW BYTE */
-sfr at 0xC5 ADC2GTH ; /* ADC 2 GREATER-THAN REGISTER - HIGH BYTE */
-sfr at 0xC6 ADC2LTL ; /* ADC 2 LESS-THAN REGISTER - LOW BYTE */
-sfr at 0xC7 ADC2LTH ; /* ADC 2 LESS-THAN REGISTER - HIGH BYTE */
-sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */
-sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */
-sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */
-sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */
-sfr at 0xD1 REF2CN ; /* VOLTAGE REFERENCE 2 CONTROL */
-sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */
+__sfr __at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */
+__sfr __at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */
+__sfr __at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */
+__sfr __at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */
+__sfr __at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */
+__sfr __at 0xBE ADC2L ; /* ADC 2 DATA - LOW BYTE */
+__sfr __at 0xBF ADC2H ; /* ADC 2 DATA - HIGH BYTE */
+__sfr __at 0xC4 ADC2GTL ; /* ADC 2 GREATER-THAN REGISTER - LOW BYTE */
+__sfr __at 0xC5 ADC2GTH ; /* ADC 2 GREATER-THAN REGISTER - HIGH BYTE */
+__sfr __at 0xC6 ADC2LTL ; /* ADC 2 LESS-THAN REGISTER - LOW BYTE */
+__sfr __at 0xC7 ADC2LTH ; /* ADC 2 LESS-THAN REGISTER - HIGH BYTE */
+__sfr __at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */
+__sfr __at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */
+__sfr __at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */
+__sfr __at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */
+__sfr __at 0xD1 REF2CN ; /* VOLTAGE REFERENCE 2 CONTROL */
+__sfr __at 0xE8 ADC2CN ; /* ADC 2 CONTROL */
/* Page 0x03 */
-sfr at 0x88 CPT2CN ; /* COMPARATOR 2 CONTROL */
-sfr at 0x89 CPT2MD ; /* COMPARATOR 2 CONFIGURATION */
-sfr at 0xD8 DMA0CN ; /* DMA0 CONTROL */
-sfr at 0xD9 DMA0DAL ; /* DMA0 DATA ADDRESS BEGINNING LOW BYTE */
-sfr at 0xDA DMA0DAH ; /* DMA0 DATA ADDRESS BEGINNING HIGH BYTE */
-sfr at 0xDB DMA0DSL ; /* DMA0 DATA ADDRESS POINTER LOW BYTE */
-sfr at 0xDC DMA0DSH ; /* DMA0 DATA ADDRESS POINTER HIGH BYTE */
-sfr at 0xDD DMA0IPT ; /* DMA0 INSTRUCTION WRITE ADDRESS */
-sfr at 0xDE DMA0IDT ; /* DMA0 INSTRUCTION WRITE DATA */
-sfr at 0xF8 DMA0CF ; /* DMA0 CONFIGURATION */
-sfr at 0xF9 DMA0CTL ; /* DMA0 REPEAT COUNTER LIMIT LOW BYTE */
-sfr at 0xFA DMA0CTH ; /* DMA0 REPEAT COUNTER LIMIT HIGH BYTE */
-sfr at 0xFB DMA0CSL ; /* DMA0 REPEAT COUNTER STATUS LOW BYTE */
-sfr at 0xFC DMA0CSH ; /* DMA0 REPEAT COUNTER STATUS HIGH BYTE */
-sfr at 0xFD DMA0BND ; /* DMA0 INSTRUCTION BOUNDARY */
-sfr at 0xFE DMA0ISW ; /* DMA0 INSTRUCTION STATUS */
+__sfr __at 0x88 CPT2CN ; /* COMPARATOR 2 CONTROL */
+__sfr __at 0x89 CPT2MD ; /* COMPARATOR 2 CONFIGURATION */
+__sfr __at 0xD8 DMA0CN ; /* DMA0 CONTROL */
+__sfr __at 0xD9 DMA0DAL ; /* DMA0 DATA ADDRESS BEGINNING LOW BYTE */
+__sfr __at 0xDA DMA0DAH ; /* DMA0 DATA ADDRESS BEGINNING HIGH BYTE */
+__sfr __at 0xDB DMA0DSL ; /* DMA0 DATA ADDRESS POINTER LOW BYTE */
+__sfr __at 0xDC DMA0DSH ; /* DMA0 DATA ADDRESS POINTER HIGH BYTE */
+__sfr __at 0xDD DMA0IPT ; /* DMA0 INSTRUCTION WRITE ADDRESS */
+__sfr __at 0xDE DMA0IDT ; /* DMA0 INSTRUCTION WRITE DATA */
+__sfr __at 0xF8 DMA0CF ; /* DMA0 CONFIGURATION */
+__sfr __at 0xF9 DMA0CTL ; /* DMA0 REPEAT COUNTER LIMIT LOW BYTE */
+__sfr __at 0xFA DMA0CTH ; /* DMA0 REPEAT COUNTER LIMIT HIGH BYTE */
+__sfr __at 0xFB DMA0CSL ; /* DMA0 REPEAT COUNTER STATUS LOW BYTE */
+__sfr __at 0xFC DMA0CSH ; /* DMA0 REPEAT COUNTER STATUS HIGH BYTE */
+__sfr __at 0xFD DMA0BND ; /* DMA0 INSTRUCTION BOUNDARY */
+__sfr __at 0xFE DMA0ISW ; /* DMA0 INSTRUCTION STATUS */
/* Page 0x0F */
-sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
-sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
-sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
-sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */
-sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */
-sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */
-sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */
-sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */
-sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */
-sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */
-sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */
-sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
-sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
-sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */
-sfr at 0xAE P2MDIN ; /* PORT 2 INPUT MODE */
-sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */
-sfr at 0xBA ADC0CPT ; /* ADC0 CALIBRATION POINTER */
-sfr at 0xBB ADC0CCF ; /* ADC0 CALIBRATION COEFFICIENT */
-sfr at 0xC8 P4 ; /* PORT 4 */
-sfr at 0xD8 P5 ; /* PORT 5 */
-sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */
-sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */
-sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */
-sfr at 0xE4 XBR3 ; /* CROSSBAR CONFIGURATION REGISTER 3 */
-sfr at 0xE8 P6 ; /* PORT 6 */
-sfr at 0xF8 P7 ; /* PORT 7 */
+__sfr __at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
+__sfr __at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
+__sfr __at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
+__sfr __at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */
+__sfr __at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */
+__sfr __at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */
+__sfr __at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */
+__sfr __at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */
+__sfr __at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */
+__sfr __at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */
+__sfr __at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */
+__sfr __at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */
+__sfr __at 0xAE P2MDIN ; /* PORT 2 INPUT MODE */
+__sfr __at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */
+__sfr __at 0xBA ADC0CPT ; /* ADC0 CALIBRATION POINTER */
+__sfr __at 0xBB ADC0CCF ; /* ADC0 CALIBRATION COEFFICIENT */
+__sfr __at 0xC8 P4 ; /* PORT 4 */
+__sfr __at 0xD8 P5 ; /* PORT 5 */
+__sfr __at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */
+__sfr __at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */
+__sfr __at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */
+__sfr __at 0xE4 XBR3 ; /* CROSSBAR CONFIGURATION REGISTER 3 */
+__sfr __at 0xE8 P6 ; /* PORT 6 */
+__sfr __at 0xF8 P7 ; /* PORT 7 */
/* BIT Registers */
/* P0 0x80 */
-sbit at 0x80 P0_0 ;
-sbit at 0x81 P0_1 ;
-sbit at 0x82 P0_2 ;
-sbit at 0x83 P0_3 ;
-sbit at 0x84 P0_4 ;
-sbit at 0x85 P0_5 ;
-sbit at 0x86 P0_6 ;
-sbit at 0x87 P0_7 ;
+__sbit __at 0x80 P0_0 ;
+__sbit __at 0x81 P0_1 ;
+__sbit __at 0x82 P0_2 ;
+__sbit __at 0x83 P0_3 ;
+__sbit __at 0x84 P0_4 ;
+__sbit __at 0x85 P0_5 ;
+__sbit __at 0x86 P0_6 ;
+__sbit __at 0x87 P0_7 ;
/* TCON 0x88 */
-sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
-sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
-sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
-sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
-sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
-sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
-sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
-sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
+__sbit __at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
+__sbit __at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
+__sbit __at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
+__sbit __at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
+__sbit __at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
+__sbit __at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
+__sbit __at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
+__sbit __at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
/* CPT0CN 0x88 */
-sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
-sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
-sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
-sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
-sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */
-sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */
-sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */
-sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */
+__sbit __at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
+__sbit __at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
+__sbit __at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
+__sbit __at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
+__sbit __at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */
+__sbit __at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */
+__sbit __at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */
+__sbit __at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */
/* CPT1CN 0x88 */
-sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
-sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
-sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
-sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
-sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */
-sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */
-sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */
-sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */
+__sbit __at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
+__sbit __at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
+__sbit __at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
+__sbit __at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
+__sbit __at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */
+__sbit __at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */
+__sbit __at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */
+__sbit __at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */
/* CPT2CN 0x88 */
-sbit at 0x88 CP2HYN0 ; /* COMPARATOR 2 NEGATIVE HYSTERESIS 0 */
-sbit at 0x89 CP2HYN1 ; /* COMPARATOR 2 NEGATIVE HYSTERESIS 1 */
-sbit at 0x8A CP2HYP0 ; /* COMPARATOR 2 POSITIVE HYSTERESIS 0 */
-sbit at 0x8B CP2HYP1 ; /* COMPARATOR 2 POSITIVE HYSTERESIS 1 */
-sbit at 0x8C CP2FIF ; /* COMPARATOR 2 FALLING EDGE INTERRUPT */
-sbit at 0x8D CP2RIF ; /* COMPARATOR 2 RISING EDGE INTERRUPT */
-sbit at 0x8E CP2OUT ; /* COMPARATOR 2 OUTPUT */
-sbit at 0x8F CP2EN ; /* COMPARATOR 2 ENABLE */
+__sbit __at 0x88 CP2HYN0 ; /* COMPARATOR 2 NEGATIVE HYSTERESIS 0 */
+__sbit __at 0x89 CP2HYN1 ; /* COMPARATOR 2 NEGATIVE HYSTERESIS 1 */
+__sbit __at 0x8A CP2HYP0 ; /* COMPARATOR 2 POSITIVE HYSTERESIS 0 */
+__sbit __at 0x8B CP2HYP1 ; /* COMPARATOR 2 POSITIVE HYSTERESIS 1 */
+__sbit __at 0x8C CP2FIF ; /* COMPARATOR 2 FALLING EDGE INTERRUPT */
+__sbit __at 0x8D CP2RIF ; /* COMPARATOR 2 RISING EDGE INTERRUPT */
+__sbit __at 0x8E CP2OUT ; /* COMPARATOR 2 OUTPUT */
+__sbit __at 0x8F CP2EN ; /* COMPARATOR 2 ENABLE */
/* P1 0x90 */
-sbit at 0x90 P1_0 ;
-sbit at 0x91 P1_1 ;
-sbit at 0x92 P1_2 ;
-sbit at 0x93 P1_3 ;
-sbit at 0x94 P1_4 ;
-sbit at 0x95 P1_5 ;
-sbit at 0x96 P1_6 ;
-sbit at 0x97 P1_7 ;
+__sbit __at 0x90 P1_0 ;
+__sbit __at 0x91 P1_1 ;
+__sbit __at 0x92 P1_2 ;
+__sbit __at 0x93 P1_3 ;
+__sbit __at 0x94 P1_4 ;
+__sbit __at 0x95 P1_5 ;
+__sbit __at 0x96 P1_6 ;
+__sbit __at 0x97 P1_7 ;
/* SCON0 0x98 */
-sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */
-sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */
-sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */
-sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */
-sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */
-sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */
-sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */
-sbit at 0x9C REN ; /* UART 0 RX ENABLE */
-sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */
-sbit at 0x9E SM10 ; /* UART 0 MODE 1 */
-sbit at 0x9F SM00 ; /* UART 0 MODE 0 */
+__sbit __at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */
+__sbit __at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */
+__sbit __at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */
+__sbit __at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */
+__sbit __at 0x9A RB80 ; /* UART 0 RX BIT 8 */
+__sbit __at 0x9B TB80 ; /* UART 0 TX BIT 8 */
+__sbit __at 0x9C REN0 ; /* UART 0 RX ENABLE */
+__sbit __at 0x9C REN ; /* UART 0 RX ENABLE */
+__sbit __at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */
+__sbit __at 0x9E SM10 ; /* UART 0 MODE 1 */
+__sbit __at 0x9F SM00 ; /* UART 0 MODE 0 */
/* SCON1 0x98 */
-sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */
-sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */
-sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */
-sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */
-sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */
-sbit at 0x9D MCE1 ; /* UART 1 MCE */
-sbit at 0x9F S1MODE ; /* UART 1 MODE */
+__sbit __at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */
+__sbit __at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */
+__sbit __at 0x9A RB81 ; /* UART 1 RX BIT 8 */
+__sbit __at 0x9B TB81 ; /* UART 1 TX BIT 8 */
+__sbit __at 0x9C REN1 ; /* UART 1 RX ENABLE */
+__sbit __at 0x9D MCE1 ; /* UART 1 MCE */
+__sbit __at 0x9F S1MODE ; /* UART 1 MODE */
/* P2 0xA0 */
-sbit at 0xA0 P2_0 ;
-sbit at 0xA1 P2_1 ;
-sbit at 0xA2 P2_2 ;
-sbit at 0xA3 P2_3 ;
-sbit at 0xA4 P2_4 ;
-sbit at 0xA5 P2_5 ;
-sbit at 0xA6 P2_6 ;
-sbit at 0xA7 P2_7 ;
+__sbit __at 0xA0 P2_0 ;
+__sbit __at 0xA1 P2_1 ;
+__sbit __at 0xA2 P2_2 ;
+__sbit __at 0xA3 P2_3 ;
+__sbit __at 0xA4 P2_4 ;
+__sbit __at 0xA5 P2_5 ;
+__sbit __at 0xA6 P2_6 ;
+__sbit __at 0xA7 P2_7 ;
/* IE 0xA8 */
-sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
-sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
-sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
-sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
-sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */
-sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */
-sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
-sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
+__sbit __at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
+__sbit __at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
+__sbit __at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
+__sbit __at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
+__sbit __at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */
+__sbit __at 0xAC ES ; /* UART0 INTERRUPT ENABLE */
+__sbit __at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
+__sbit __at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
/* P3 0xB0 */
-sbit at 0xB0 P3_0 ;
-sbit at 0xB1 P3_1 ;
-sbit at 0xB2 P3_2 ;
-sbit at 0xB3 P3_3 ;
-sbit at 0xB4 P3_4 ;
-sbit at 0xB5 P3_5 ;
-sbit at 0xB6 P3_6 ;
-sbit at 0xB7 P3_7 ;
+__sbit __at 0xB0 P3_0 ;
+__sbit __at 0xB1 P3_1 ;
+__sbit __at 0xB2 P3_2 ;
+__sbit __at 0xB3 P3_3 ;
+__sbit __at 0xB4 P3_4 ;
+__sbit __at 0xB5 P3_5 ;
+__sbit __at 0xB6 P3_6 ;
+__sbit __at 0xB7 P3_7 ;
/* IP 0xB8 */
-sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
-sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
-sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
-sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */
-sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */
-sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */
+__sbit __at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
+__sbit __at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
+__sbit __at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
+__sbit __at 0xBB PT1 ; /* TIMER 1 PRIORITY */
+__sbit __at 0xBC PS ; /* SERIAL PORT PRIORITY */
+__sbit __at 0xBD PT2 ; /* TIMER 2 PRIORITY */
/* SMB0CN 0xC0 */
-sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
-sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
-sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
-sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
-sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
-sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */
-sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
-sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */
+__sbit __at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
+__sbit __at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
+__sbit __at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
+__sbit __at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
+__sbit __at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
+__sbit __at 0xC5 STA ; /* SMBUS 0 START FLAG */
+__sbit __at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
+__sbit __at 0xC7 BUSY ; /* SMBUS 0 BUSY */
/* CAN0STA 0xC0 */
-sbit at 0xC3 CANTXOK ; /* CAN TRANSMITTED A MESSAGE SUCCESSFULLY */
-sbit at 0xC4 CANRXOK ; /* CAN RECEIVED A MESSAGE SUCCESSFULLY */
-sbit at 0xC5 CANEPASS; /* CAN ERROR PASSIVE */
-sbit at 0xC6 CANEWARN; /* CAN WARNING STATUS */
-sbit at 0xC7 CANBOFF ; /* CAN BUSOFF STATUS */
+__sbit __at 0xC3 CANTXOK ; /* CAN TRANSMITTED A MESSAGE SUCCESSFULLY */
+__sbit __at 0xC4 CANRXOK ; /* CAN RECEIVED A MESSAGE SUCCESSFULLY */
+__sbit __at 0xC5 CANEPASS; /* CAN ERROR PASSIVE */
+__sbit __at 0xC6 CANEWARN; /* CAN WARNING STATUS */
+__sbit __at 0xC7 CANBOFF ; /* CAN BUSOFF STATUS */
/* TMR2CN 0xC8 */
-sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */
-sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */
-sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
-sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
-sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */
-sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
+__sbit __at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */
+__sbit __at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */
+__sbit __at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
+__sbit __at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
+__sbit __at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */
+__sbit __at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
/* TMR3CN 0xC8 */
-sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */
-sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */
-sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */
-sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */
-sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */
-sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */
+__sbit __at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */
+__sbit __at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */
+__sbit __at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */
+__sbit __at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */
+__sbit __at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */
+__sbit __at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */
/* TMR4CN 0xC8 */
-sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */
-sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */
-sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */
-sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */
-sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */
-sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */
+__sbit __at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */
+__sbit __at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */
+__sbit __at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */
+__sbit __at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */
+__sbit __at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */
+__sbit __at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */
/* P4 0xC8 */
-sbit at 0xC8 P4_0 ;
-sbit at 0xC9 P4_1 ;
-sbit at 0xCA P4_2 ;
-sbit at 0xCB P4_3 ;
-sbit at 0xCC P4_4 ;
-sbit at 0xCD P4_5 ;
-sbit at 0xCE P4_6 ;
-sbit at 0xCF P4_7 ;
+__sbit __at 0xC8 P4_0 ;
+__sbit __at 0xC9 P4_1 ;
+__sbit __at 0xCA P4_2 ;
+__sbit __at 0xCB P4_3 ;
+__sbit __at 0xCC P4_4 ;
+__sbit __at 0xCD P4_5 ;
+__sbit __at 0xCE P4_6 ;
+__sbit __at 0xCF P4_7 ;
/* PSW 0xD0 */
-sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
-sbit at 0xD1 F1 ; /* USER FLAG 1 */
-sbit at 0xD2 OV ; /* OVERFLOW FLAG */
-sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
-sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
-sbit at 0xD5 F0 ; /* USER FLAG 0 */
-sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
-sbit at 0xD7 CY ; /* CARRY FLAG */
+__sbit __at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
+__sbit __at 0xD1 F1 ; /* USER FLAG 1 */
+__sbit __at 0xD2 OV ; /* OVERFLOW FLAG */
+__sbit __at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
+__sbit __at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
+__sbit __at 0xD5 F0 ; /* USER FLAG 0 */
+__sbit __at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
+__sbit __at 0xD7 CY ; /* CARRY FLAG */
/* PCA0CN 0xD8 */
-sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
-sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
-sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
-sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
-sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
-sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */
-sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
-sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
+__sbit __at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
+__sbit __at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
+__sbit __at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
+__sbit __at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
+__sbit __at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
+__sbit __at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */
+__sbit __at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
+__sbit __at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
/* DMA0CN 0xD8 */
-sbit at 0xD8 DMA0DO0 ; /* ADC0 Data Overflow Warning Flag */
-sbit at 0xD9 DMA0DO1 ; /* ADC1 Data Overflow Warning Flag */
-sbit at 0xDA DMA0DOE ; /* Data Overflow Warning Interrupt Enable */
-sbit at 0xDB DMA0DE0 ; /* ADC0 Data Overflow Error Flag */
-sbit at 0xDC DMA0DE1 ; /* ADC1 Data Overflow Error Flag */
-sbit at 0xDD DMA0MD ; /* DMA0 Mode Select */
-sbit at 0xDE DMA0INT ; /* DMA0 Operations Complete Flag */
-sbit at 0xDF DMA0EN ; /* DMA0 Enable */
+__sbit __at 0xD8 DMA0DO0 ; /* ADC0 Data Overflow Warning Flag */
+__sbit __at 0xD9 DMA0DO1 ; /* ADC1 Data Overflow Warning Flag */
+__sbit __at 0xDA DMA0DOE ; /* Data Overflow Warning Interrupt Enable */
+__sbit __at 0xDB DMA0DE0 ; /* ADC0 Data Overflow Error Flag */
+__sbit __at 0xDC DMA0DE1 ; /* ADC1 Data Overflow Error Flag */
+__sbit __at 0xDD DMA0MD ; /* DMA0 Mode Select */
+__sbit __at 0xDE DMA0INT ; /* DMA0 Operations Complete Flag */
+__sbit __at 0xDF DMA0EN ; /* DMA0 Enable */
/* P5 0xD8 */
-sbit at 0xD8 P5_0 ;
-sbit at 0xD9 P5_1 ;
-sbit at 0xDA P5_2 ;
-sbit at 0xDB P5_3 ;
-sbit at 0xDC P5_4 ;
-sbit at 0xDD P5_5 ;
-sbit at 0xDE P5_6 ;
-sbit at 0xDF P5_7 ;
+__sbit __at 0xD8 P5_0 ;
+__sbit __at 0xD9 P5_1 ;
+__sbit __at 0xDA P5_2 ;
+__sbit __at 0xDB P5_3 ;
+__sbit __at 0xDC P5_4 ;
+__sbit __at 0xDD P5_5 ;
+__sbit __at 0xDE P5_6 ;
+__sbit __at 0xDF P5_7 ;
/* ADC0CN 0xE8 */
-sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */
-sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */
-sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */
-sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
-sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */
-sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
-sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */
+__sbit __at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */
+__sbit __at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */
+__sbit __at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */
+__sbit __at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
+__sbit __at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */
+__sbit __at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
+__sbit __at 0xEF AD0EN ; /* ADC 0 ENABLE */
/* ADC1CN 0xE8 */
-sbit at 0xE9 AD1CM0 ; /* ADC 1 CONVERT START MODE BIT 0 */
-sbit at 0xEA AD1CM1 ; /* ADC 1 CONVERT START MODE BIT 1 */
-sbit at 0xEB AD1CM2 ; /* ADC 1 CONVERT START MODE BIT 1 */
-sbit at 0xEC AD1BUSY ; /* ADC 1 BUSY FLAG */
-sbit at 0xED AD1INT ; /* ADC 1 EOC INTERRUPT FLAG */
-sbit at 0xEE AD1TM ; /* ADC 1 TRACK MODE */
-sbit at 0xEF AD1EN ; /* ADC 1 ENABLE */
+__sbit __at 0xE9 AD1CM0 ; /* ADC 1 CONVERT START MODE BIT 0 */
+__sbit __at 0xEA AD1CM1 ; /* ADC 1 CONVERT START MODE BIT 1 */
+__sbit __at 0xEB AD1CM2 ; /* ADC 1 CONVERT START MODE BIT 1 */
+__sbit __at 0xEC AD1BUSY ; /* ADC 1 BUSY FLAG */
+__sbit __at 0xED AD1INT ; /* ADC 1 EOC INTERRUPT FLAG */
+__sbit __at 0xEE AD1TM ; /* ADC 1 TRACK MODE */
+__sbit __at 0xEF AD1EN ; /* ADC 1 ENABLE */
/* ADC2CN 0xE8 */
-sbit at 0xE8 AD2LJST ; /* ADC 2 LEFT JUSTIFY SELECT */
-sbit at 0xE9 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */
-sbit at 0xEA AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */
-sbit at 0xEB AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */
-sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */
-sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */
-sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */
-sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */
+__sbit __at 0xE8 AD2LJST ; /* ADC 2 LEFT JUSTIFY SELECT */
+__sbit __at 0xE9 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */
+__sbit __at 0xEA AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */
+__sbit __at 0xEB AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */
+__sbit __at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */
+__sbit __at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */
+__sbit __at 0xEE AD2TM ; /* ADC 2 TRACK MODE */
+__sbit __at 0xEF AD2EN ; /* ADC 2 ENABLE */
/* P6 0xE8 */
-sbit at 0xE8 P6_0 ;
-sbit at 0xE9 P6_1 ;
-sbit at 0xEA P6_2 ;
-sbit at 0xEB P6_3 ;
-sbit at 0xEC P6_4 ;
-sbit at 0xED P6_5 ;
-sbit at 0xEE P6_6 ;
-sbit at 0xEF P6_7 ;
+__sbit __at 0xE8 P6_0 ;
+__sbit __at 0xE9 P6_1 ;
+__sbit __at 0xEA P6_2 ;
+__sbit __at 0xEB P6_3 ;
+__sbit __at 0xEC P6_4 ;
+__sbit __at 0xED P6_5 ;
+__sbit __at 0xEE P6_6 ;
+__sbit __at 0xEF P6_7 ;
/* SPI0CN 0xF8 */
-sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
-sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */
-sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */
-sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */
-sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
-sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
-sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
-sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
+__sbit __at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
+__sbit __at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */
+__sbit __at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */
+__sbit __at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */
+__sbit __at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
+__sbit __at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
+__sbit __at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
+__sbit __at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
/* CAN0CN 0xF8 */
-sbit at 0xF8 CANINIT ; /* CAN INITIALIZATION */
-sbit at 0xF9 CANIE ; /* CAN MODULE INTERRUPT ENABLE */
-sbit at 0xFA CANSIE ; /* CAN STATUS CHANGE INTERRUPT ENABLE */
-sbit at 0xFB CANEIE ; /* CAN ERROR INTERRUPT ENABLE */
-sbit at 0xFC CANIF ; /* CAN INTERRUPT FLAG */
-sbit at 0xFD CANDAR ; /* CAN DISABLE AUTOMATIC RETRANSMISSION */
-sbit at 0xFE CANCCE ; /* CAN CONFIGURATION CHANGE ENABLE */
-sbit at 0xFF CANTEST ; /* CAN TEST MODE ENABLE */
+__sbit __at 0xF8 CANINIT ; /* CAN INITIALIZATION */
+__sbit __at 0xF9 CANIE ; /* CAN MODULE INTERRUPT ENABLE */
+__sbit __at 0xFA CANSIE ; /* CAN STATUS CHANGE INTERRUPT ENABLE */
+__sbit __at 0xFB CANEIE ; /* CAN ERROR INTERRUPT ENABLE */
+__sbit __at 0xFC CANIF ; /* CAN INTERRUPT FLAG */
+__sbit __at 0xFD CANDAR ; /* CAN DISABLE AUTOMATIC RETRANSMISSION */
+__sbit __at 0xFE CANCCE ; /* CAN CONFIGURATION CHANGE ENABLE */
+__sbit __at 0xFF CANTEST ; /* CAN TEST MODE ENABLE */
/* DMA0CF 0xF8 */
-sbit at 0xF8 DMA0EO ; /* END-OF-OPERATION FLAG */
-sbit at 0xF9 DMA0EOE ; /* END-OF-OPERATION INTERRUPT ENABLE */
-sbit at 0xFA DMA0CI ; /* REPEAT COUNTER OVERFLOW FLAG */
-sbit at 0xFB DMA0CIE ; /* REPEAT COUNTER OVERFLOW INTERRUPT ENABLE */
-sbit at 0xFE DMA0XBY ; /* OFF-CHIP XRAM BUSY FLAG */
-sbit at 0xFF DMA0HLT ; /* HALT DMA0 OFF-CHIP XRAM ACCESS */
+__sbit __at 0xF8 DMA0EO ; /* END-OF-OPERATION FLAG */
+__sbit __at 0xF9 DMA0EOE ; /* END-OF-OPERATION INTERRUPT ENABLE */
+__sbit __at 0xFA DMA0CI ; /* REPEAT COUNTER OVERFLOW FLAG */
+__sbit __at 0xFB DMA0CIE ; /* REPEAT COUNTER OVERFLOW INTERRUPT ENABLE */
+__sbit __at 0xFE DMA0XBY ; /* OFF-CHIP XRAM BUSY FLAG */
+__sbit __at 0xFF DMA0HLT ; /* HALT DMA0 OFF-CHIP XRAM ACCESS */
/* P7 0xF8 */
-sbit at 0xF8 P7_0 ;
-sbit at 0xF9 P7_1 ;
-sbit at 0xFA P7_2 ;
-sbit at 0xFB P7_3 ;
-sbit at 0xFC P7_4 ;
-sbit at 0xFD P7_5 ;
-sbit at 0xFE P7_6 ;
-sbit at 0xFF P7_7 ;
+__sbit __at 0xF8 P7_0 ;
+__sbit __at 0xF9 P7_1 ;
+__sbit __at 0xFA P7_2 ;
+__sbit __at 0xFB P7_3 ;
+__sbit __at 0xFC P7_4 ;
+__sbit __at 0xFD P7_5 ;
+__sbit __at 0xFE P7_6 ;
+__sbit __at 0xFF P7_7 ;
/* Predefined SFR Bit Masks */
/* BYTE Registers */
/* All Pages */
-sfr at 0x80 P0 ; /* PORT 0 */
-sfr at 0x81 SP ; /* STACK POINTER */
-sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
-sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
-sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */
-sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */
-sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */
-sfr at 0x87 PCON ; /* POWER CONTROL */
-sfr at 0x90 P1 ; /* PORT 1 */
-sfr at 0xA0 P2 ; /* PORT 2 */
-sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
-sfr at 0xB0 P3 ; /* PORT 3 */
-sfr at 0xB1 PSBANK ; /* FLASH BANK SELECT */
-sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
-sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
-sfr at 0xE0 ACC ; /* ACCUMULATOR */
-sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
-sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
-sfr at 0xF0 B ; /* B REGISTER */
-sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
-sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
-sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
+__sfr __at 0x80 P0 ; /* PORT 0 */
+__sfr __at 0x81 SP ; /* STACK POINTER */
+__sfr __at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
+__sfr __at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
+__sfr __at 0x84 SFRPAGE ; /* SFR PAGE SELECT */
+__sfr __at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */
+__sfr __at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */
+__sfr __at 0x87 PCON ; /* POWER CONTROL */
+__sfr __at 0x90 P1 ; /* PORT 1 */
+__sfr __at 0xA0 P2 ; /* PORT 2 */
+__sfr __at 0xA8 IE ; /* INTERRUPT ENABLE */
+__sfr __at 0xB0 P3 ; /* PORT 3 */
+__sfr __at 0xB1 PSBANK ; /* FLASH BANK SELECT */
+__sfr __at 0xB8 IP ; /* INTERRUPT PRIORITY */
+__sfr __at 0xD0 PSW ; /* PROGRAM STATUS WORD */
+__sfr __at 0xE0 ACC ; /* ACCUMULATOR */
+__sfr __at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
+__sfr __at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
+__sfr __at 0xF0 B ; /* B REGISTER */
+__sfr __at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
+__sfr __at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
+__sfr __at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
/* Page 0x00 */
-sfr at 0x88 TCON ; /* TIMER CONTROL */
-sfr at 0x89 TMOD ; /* TIMER MODE */
-sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
-sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
-sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
-sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
-sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */
-sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */
-sfr at 0x91 SSTA0 ; /* UART 0 STATUS */
-sfr at 0x98 SCON0 ; /* UART 0 CONTROL */
-sfr at 0x98 SCON ; /* UART 0 CONTROL */
-sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */
-sfr at 0x99 SBUF ; /* UART 0 BUFFER */
-sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */
-sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */
-sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */
-sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */
-sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */
-sfr at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */
-sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */
-sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */
-sfr at 0xB7 FLSCL ; /* FLASH SCALE */
-sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */
-sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
-sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
-sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
-sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
-sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
-sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
-sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
-sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
-sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
-sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
-sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
-sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
-sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
-sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
-sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */
-sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
-sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
-sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
-sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
-sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
-sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
-sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
-sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */
-sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */
-sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */
-sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */
-sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */
-sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */
-sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
-sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xEF RSTSRC ; /* RESET SOURCE */
-sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */
-sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
-sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
-sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
+__sfr __at 0x88 TCON ; /* TIMER CONTROL */
+__sfr __at 0x89 TMOD ; /* TIMER MODE */
+__sfr __at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
+__sfr __at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
+__sfr __at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
+__sfr __at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
+__sfr __at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */
+__sfr __at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */
+__sfr __at 0x91 SSTA0 ; /* UART 0 STATUS */
+__sfr __at 0x98 SCON0 ; /* UART 0 CONTROL */
+__sfr __at 0x98 SCON ; /* UART 0 CONTROL */
+__sfr __at 0x99 SBUF0 ; /* UART 0 BUFFER */
+__sfr __at 0x99 SBUF ; /* UART 0 BUFFER */
+__sfr __at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */
+__sfr __at 0x9B SPI0DAT ; /* SPI 0 DATA */
+__sfr __at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */
+__sfr __at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */
+__sfr __at 0xA2 EMI0CN ; /* EMIF CONTROL */
+__sfr __at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */
+__sfr __at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */
+__sfr __at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */
+__sfr __at 0xB7 FLSCL ; /* FLASH SCALE */
+__sfr __at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */
+__sfr __at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
+__sfr __at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
+__sfr __at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
+__sfr __at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
+__sfr __at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
+__sfr __at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
+__sfr __at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
+__sfr __at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
+__sfr __at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
+__sfr __at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
+__sfr __at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
+__sfr __at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
+__sfr __at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
+__sfr __at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
+__sfr __at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */
+__sfr __at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
+__sfr __at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
+__sfr __at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
+__sfr __at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
+__sfr __at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
+__sfr __at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
+__sfr __at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
+__sfr __at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */
+__sfr __at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */
+__sfr __at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */
+__sfr __at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */
+__sfr __at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */
+__sfr __at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */
+__sfr __at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
+__sfr __at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
+__sfr __at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
+__sfr __at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
+__sfr __at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
+__sfr __at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
+__sfr __at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
+__sfr __at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
+__sfr __at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
+__sfr __at 0xEF RSTSRC ; /* RESET SOURCE */
+__sfr __at 0xF8 SPI0CN ; /* SPI 0 CONTROL */
+__sfr __at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
+__sfr __at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
+__sfr __at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
+__sfr __at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
+__sfr __at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
+__sfr __at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
/* Page 0x01 */
-sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */
-sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */
-sfr at 0x98 SCON1 ; /* UART 1 CONTROL */
-sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */
-sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */
-sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */
-sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */
-sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */
-sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
-sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
-sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */
+__sfr __at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */
+__sfr __at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */
+__sfr __at 0x98 SCON1 ; /* UART 1 CONTROL */
+__sfr __at 0x99 SBUF1 ; /* UART 1 BUFFER */
+__sfr __at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */
+__sfr __at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */
+__sfr __at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */
+__sfr __at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */
+__sfr __at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
+__sfr __at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
+__sfr __at 0xD4 DAC1CN ; /* DAC 1 CONTROL */
/* Page 0x02 */
-sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */
-sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */
-sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */
-sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */
-sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */
-sfr at 0xBE ADC2 ; /* ADC 2 DATA */
-sfr at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */
-sfr at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */
-sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */
-sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */
-sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */
-sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */
-sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */
+__sfr __at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */
+__sfr __at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */
+__sfr __at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */
+__sfr __at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */
+__sfr __at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */
+__sfr __at 0xBE ADC2 ; /* ADC 2 DATA */
+__sfr __at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */
+__sfr __at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */
+__sfr __at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */
+__sfr __at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */
+__sfr __at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */
+__sfr __at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */
+__sfr __at 0xE8 ADC2CN ; /* ADC 2 CONTROL */
/* Page 0x03 */
-sfr at 0x91 MAC0BL ; /* MAC0 B Register Low Byte */
-sfr at 0x92 MAC0BH ; /* MAC0 B Register High Byte */
-sfr at 0x93 MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */
-sfr at 0x94 MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */
-sfr at 0x95 MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */
-sfr at 0x96 MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */
-sfr at 0x97 MAC0OVR ; /* MAC0 Accumulator Overflow */
-sfr at 0xC0 MAC0STA ; /* MAC0 Status Register */
-sfr at 0xC1 MAC0AL ; /* MAC0 A Register Low Byte */
-sfr at 0xC2 MAC0AH ; /* MAC0 A Register High Byte */
-sfr at 0xC3 MAC0CF ; /* MAC0 Configuration */
-sfr at 0xCE MAC0RNDL ; /* MAC0 Rounding Register Low Byte */
-sfr at 0xCF MAC0RNDH ; /* MAC0 Rounding Register High Byte */
+__sfr __at 0x91 MAC0BL ; /* MAC0 B Register Low Byte */
+__sfr __at 0x92 MAC0BH ; /* MAC0 B Register High Byte */
+__sfr __at 0x93 MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */
+__sfr __at 0x94 MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */
+__sfr __at 0x95 MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */
+__sfr __at 0x96 MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */
+__sfr __at 0x97 MAC0OVR ; /* MAC0 Accumulator Overflow */
+__sfr __at 0xC0 MAC0STA ; /* MAC0 Status Register */
+__sfr __at 0xC1 MAC0AL ; /* MAC0 A Register Low Byte */
+__sfr __at 0xC2 MAC0AH ; /* MAC0 A Register High Byte */
+__sfr __at 0xC3 MAC0CF ; /* MAC0 Configuration */
+__sfr __at 0xCE MAC0RNDL ; /* MAC0 Rounding Register Low Byte */
+__sfr __at 0xCF MAC0RNDH ; /* MAC0 Rounding Register High Byte */
/* Page 0x0F */
-sfr at 0x88 FLSTAT ; /* FLASH STATUS */
-sfr at 0x89 PLL0CN ; /* PLL 0 CONTROL */
-sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
-sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
-sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
-sfr at 0x8D PLL0DIV ; /* PLL 0 DIVIDER */
-sfr at 0x8E PLL0MUL ; /* PLL 0 MULTIPLIER */
-sfr at 0x8F PLL0FLT ; /* PLL 0 FILTER */
-sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */
-sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */
-sfr at 0x9A CCH0MA ; /* CACHE MISS ACCUMULATOR */
-sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */
-sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */
-sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */
-sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */
-sfr at 0xA1 CCH0CN ; /* CACHE CONTROL */
-sfr at 0xA2 CCH0TN ; /* CACHE TUNING REGISTER */
-sfr at 0xA3 CCH0LC ; /* CACHE LOCK */
-sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */
-sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */
-sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
-sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
-sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */
-sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */
-sfr at 0xC8 P4 ; /* PORT 4 */
-sfr at 0xD8 P5 ; /* PORT 5 */
-sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */
-sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */
-sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */
-sfr at 0xE8 P6 ; /* PORT 6 */
-sfr at 0xF8 P7 ; /* PORT 7 */
+__sfr __at 0x88 FLSTAT ; /* FLASH STATUS */
+__sfr __at 0x89 PLL0CN ; /* PLL 0 CONTROL */
+__sfr __at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
+__sfr __at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
+__sfr __at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
+__sfr __at 0x8D PLL0DIV ; /* PLL 0 DIVIDER */
+__sfr __at 0x8E PLL0MUL ; /* PLL 0 MULTIPLIER */
+__sfr __at 0x8F PLL0FLT ; /* PLL 0 FILTER */
+__sfr __at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */
+__sfr __at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */
+__sfr __at 0x9A CCH0MA ; /* CACHE MISS ACCUMULATOR */
+__sfr __at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */
+__sfr __at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */
+__sfr __at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */
+__sfr __at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */
+__sfr __at 0xA1 CCH0CN ; /* CACHE CONTROL */
+__sfr __at 0xA2 CCH0TN ; /* CACHE TUNING REGISTER */
+__sfr __at 0xA3 CCH0LC ; /* CACHE LOCK */
+__sfr __at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */
+__sfr __at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */
+__sfr __at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */
+__sfr __at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */
+__sfr __at 0xC8 P4 ; /* PORT 4 */
+__sfr __at 0xD8 P5 ; /* PORT 5 */
+__sfr __at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */
+__sfr __at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */
+__sfr __at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */
+__sfr __at 0xE8 P6 ; /* PORT 6 */
+__sfr __at 0xF8 P7 ; /* PORT 7 */
/* BIT Registers */
/* P0 0x80 */
-sbit at 0x80 P0_0 ;
-sbit at 0x81 P0_1 ;
-sbit at 0x82 P0_2 ;
-sbit at 0x83 P0_3 ;
-sbit at 0x84 P0_4 ;
-sbit at 0x85 P0_5 ;
-sbit at 0x86 P0_6 ;
-sbit at 0x87 P0_7 ;
+__sbit __at 0x80 P0_0 ;
+__sbit __at 0x81 P0_1 ;
+__sbit __at 0x82 P0_2 ;
+__sbit __at 0x83 P0_3 ;
+__sbit __at 0x84 P0_4 ;
+__sbit __at 0x85 P0_5 ;
+__sbit __at 0x86 P0_6 ;
+__sbit __at 0x87 P0_7 ;
/* TCON 0x88 */
-sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
-sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
-sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
-sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
-sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
-sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
-sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
-sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
+__sbit __at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
+__sbit __at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
+__sbit __at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
+__sbit __at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
+__sbit __at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
+__sbit __at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
+__sbit __at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
+__sbit __at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
/* CPT0CN 0x88 */
-sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
-sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
-sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
-sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
-sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */
-sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */
-sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */
-sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */
+__sbit __at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
+__sbit __at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
+__sbit __at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
+__sbit __at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
+__sbit __at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */
+__sbit __at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */
+__sbit __at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */
+__sbit __at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */
/* CPT1CN 0x88 */
-sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
-sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
-sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
-sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
-sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */
-sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */
-sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */
-sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */
+__sbit __at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
+__sbit __at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
+__sbit __at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
+__sbit __at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
+__sbit __at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */
+__sbit __at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */
+__sbit __at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */
+__sbit __at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */
/* FLSTAT 0x88 */
-sbit at 0x88 FLHBUSY ; /* FLASH BUSY */
+__sbit __at 0x88 FLHBUSY ; /* FLASH BUSY */
/* P1 0x90 */
-sbit at 0x90 P1_0 ;
-sbit at 0x91 P1_1 ;
-sbit at 0x92 P1_2 ;
-sbit at 0x93 P1_3 ;
-sbit at 0x94 P1_4 ;
-sbit at 0x95 P1_5 ;
-sbit at 0x96 P1_6 ;
-sbit at 0x97 P1_7 ;
+__sbit __at 0x90 P1_0 ;
+__sbit __at 0x91 P1_1 ;
+__sbit __at 0x92 P1_2 ;
+__sbit __at 0x93 P1_3 ;
+__sbit __at 0x94 P1_4 ;
+__sbit __at 0x95 P1_5 ;
+__sbit __at 0x96 P1_6 ;
+__sbit __at 0x97 P1_7 ;
/* SCON0 0x98 */
-sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */
-sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */
-sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */
-sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */
-sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */
-sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */
-sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */
-sbit at 0x9C REN ; /* UART 0 RX ENABLE */
-sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */
-sbit at 0x9E SM10 ; /* UART 0 MODE 1 */
-sbit at 0x9F SM00 ; /* UART 0 MODE 0 */
+__sbit __at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */
+__sbit __at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */
+__sbit __at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */
+__sbit __at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */
+__sbit __at 0x9A RB80 ; /* UART 0 RX BIT 8 */
+__sbit __at 0x9B TB80 ; /* UART 0 TX BIT 8 */
+__sbit __at 0x9C REN0 ; /* UART 0 RX ENABLE */
+__sbit __at 0x9C REN ; /* UART 0 RX ENABLE */
+__sbit __at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */
+__sbit __at 0x9E SM10 ; /* UART 0 MODE 1 */
+__sbit __at 0x9F SM00 ; /* UART 0 MODE 0 */
/* SCON1 0x98 */
-sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */
-sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */
-sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */
-sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */
-sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */
-sbit at 0x9D MCE1 ; /* UART 1 MCE */
-sbit at 0x9F S1MODE ; /* UART 1 MODE */
+__sbit __at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */
+__sbit __at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */
+__sbit __at 0x9A RB81 ; /* UART 1 RX BIT 8 */
+__sbit __at 0x9B TB81 ; /* UART 1 TX BIT 8 */
+__sbit __at 0x9C REN1 ; /* UART 1 RX ENABLE */
+__sbit __at 0x9D MCE1 ; /* UART 1 MCE */
+__sbit __at 0x9F S1MODE ; /* UART 1 MODE */
/* P2 0xA0 */
-sbit at 0xA0 P2_0 ;
-sbit at 0xA1 P2_1 ;
-sbit at 0xA2 P2_2 ;
-sbit at 0xA3 P2_3 ;
-sbit at 0xA4 P2_4 ;
-sbit at 0xA5 P2_5 ;
-sbit at 0xA6 P2_6 ;
-sbit at 0xA7 P2_7 ;
+__sbit __at 0xA0 P2_0 ;
+__sbit __at 0xA1 P2_1 ;
+__sbit __at 0xA2 P2_2 ;
+__sbit __at 0xA3 P2_3 ;
+__sbit __at 0xA4 P2_4 ;
+__sbit __at 0xA5 P2_5 ;
+__sbit __at 0xA6 P2_6 ;
+__sbit __at 0xA7 P2_7 ;
/* IE 0xA8 */
-sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
-sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
-sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
-sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
-sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */
-sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */
-sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
-sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
+__sbit __at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
+__sbit __at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
+__sbit __at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
+__sbit __at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
+__sbit __at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */
+__sbit __at 0xAC ES ; /* UART0 INTERRUPT ENABLE */
+__sbit __at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
+__sbit __at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
/* P3 0xB0 */
-sbit at 0xB0 P3_0 ;
-sbit at 0xB1 P3_1 ;
-sbit at 0xB2 P3_2 ;
-sbit at 0xB3 P3_3 ;
-sbit at 0xB4 P3_4 ;
-sbit at 0xB5 P3_5 ;
-sbit at 0xB6 P3_6 ;
-sbit at 0xB7 P3_7 ;
+__sbit __at 0xB0 P3_0 ;
+__sbit __at 0xB1 P3_1 ;
+__sbit __at 0xB2 P3_2 ;
+__sbit __at 0xB3 P3_3 ;
+__sbit __at 0xB4 P3_4 ;
+__sbit __at 0xB5 P3_5 ;
+__sbit __at 0xB6 P3_6 ;
+__sbit __at 0xB7 P3_7 ;
/* IP 0xB8 */
-sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
-sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
-sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
-sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */
-sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */
-sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */
+__sbit __at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
+__sbit __at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
+__sbit __at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
+__sbit __at 0xBB PT1 ; /* TIMER 1 PRIORITY */
+__sbit __at 0xBC PS ; /* SERIAL PORT PRIORITY */
+__sbit __at 0xBD PT2 ; /* TIMER 2 PRIORITY */
/* SMB0CN 0xC0 */
-sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
-sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
-sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
-sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
-sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
-sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */
-sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
-sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */
+__sbit __at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
+__sbit __at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
+__sbit __at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
+__sbit __at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
+__sbit __at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
+__sbit __at 0xC5 STA ; /* SMBUS 0 START FLAG */
+__sbit __at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
+__sbit __at 0xC7 BUSY ; /* SMBUS 0 BUSY */
/* TMR2CN 0xC8 */
-sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */
-sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */
-sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
-sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
-sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */
-sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
+__sbit __at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */
+__sbit __at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */
+__sbit __at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
+__sbit __at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
+__sbit __at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */
+__sbit __at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
/* TMR3CN 0xC8 */
-sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */
-sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */
-sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */
-sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */
-sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */
-sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */
+__sbit __at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */
+__sbit __at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */
+__sbit __at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */
+__sbit __at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */
+__sbit __at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */
+__sbit __at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */
/* TMR4CN 0xC8 */
-sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */
-sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */
-sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */
-sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */
-sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */
-sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */
+__sbit __at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */
+__sbit __at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */
+__sbit __at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */
+__sbit __at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */
+__sbit __at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */
+__sbit __at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */
/* P4 0xC8 */
-sbit at 0xC8 P4_0 ;
-sbit at 0xC9 P4_1 ;
-sbit at 0xCA P4_2 ;
-sbit at 0xCB P4_3 ;
-sbit at 0xCC P4_4 ;
-sbit at 0xCD P4_5 ;
-sbit at 0xCE P4_6 ;
-sbit at 0xCF P4_7 ;
+__sbit __at 0xC8 P4_0 ;
+__sbit __at 0xC9 P4_1 ;
+__sbit __at 0xCA P4_2 ;
+__sbit __at 0xCB P4_3 ;
+__sbit __at 0xCC P4_4 ;
+__sbit __at 0xCD P4_5 ;
+__sbit __at 0xCE P4_6 ;
+__sbit __at 0xCF P4_7 ;
/* PSW 0xD0 */
-sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
-sbit at 0xD1 F1 ; /* USER FLAG 1 */
-sbit at 0xD2 OV ; /* OVERFLOW FLAG */
-sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
-sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
-sbit at 0xD5 F0 ; /* USER FLAG 0 */
-sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
-sbit at 0xD7 CY ; /* CARRY FLAG */
+__sbit __at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
+__sbit __at 0xD1 F1 ; /* USER FLAG 1 */
+__sbit __at 0xD2 OV ; /* OVERFLOW FLAG */
+__sbit __at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
+__sbit __at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
+__sbit __at 0xD5 F0 ; /* USER FLAG 0 */
+__sbit __at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
+__sbit __at 0xD7 CY ; /* CARRY FLAG */
/* PCA0CN D8H */
-sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
-sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
-sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
-sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
-sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
-sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */
-sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
-sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
+__sbit __at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
+__sbit __at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
+__sbit __at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
+__sbit __at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
+__sbit __at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
+__sbit __at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */
+__sbit __at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
+__sbit __at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
/* P5 0xD8 */
-sbit at 0xD8 P5_0 ;
-sbit at 0xD9 P5_1 ;
-sbit at 0xDA P5_2 ;
-sbit at 0xDB P5_3 ;
-sbit at 0xDC P5_4 ;
-sbit at 0xDD P5_5 ;
-sbit at 0xDE P5_6 ;
-sbit at 0xDF P5_7 ;
+__sbit __at 0xD8 P5_0 ;
+__sbit __at 0xD9 P5_1 ;
+__sbit __at 0xDA P5_2 ;
+__sbit __at 0xDB P5_3 ;
+__sbit __at 0xDC P5_4 ;
+__sbit __at 0xDD P5_5 ;
+__sbit __at 0xDE P5_6 ;
+__sbit __at 0xDF P5_7 ;
/* ADC0CN E8H */
-sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
-sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */
-sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */
-sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */
-sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
-sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */
-sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
-sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */
+__sbit __at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
+__sbit __at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */
+__sbit __at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */
+__sbit __at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */
+__sbit __at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
+__sbit __at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */
+__sbit __at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
+__sbit __at 0xEF AD0EN ; /* ADC 0 ENABLE */
/* ADC2CN E8H */
-sbit at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */
-sbit at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */
-sbit at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */
-sbit at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */
-sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */
-sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */
-sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */
-sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */
+__sbit __at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */
+__sbit __at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */
+__sbit __at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */
+__sbit __at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */
+__sbit __at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */
+__sbit __at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */
+__sbit __at 0xEE AD2TM ; /* ADC 2 TRACK MODE */
+__sbit __at 0xEF AD2EN ; /* ADC 2 ENABLE */
/* P6 0xE8 */
-sbit at 0xE8 P6_0 ;
-sbit at 0xE9 P6_1 ;
-sbit at 0xEA P6_2 ;
-sbit at 0xEB P6_3 ;
-sbit at 0xEC P6_4 ;
-sbit at 0xED P6_5 ;
-sbit at 0xEE P6_6 ;
-sbit at 0xEF P6_7 ;
+__sbit __at 0xE8 P6_0 ;
+__sbit __at 0xE9 P6_1 ;
+__sbit __at 0xEA P6_2 ;
+__sbit __at 0xEB P6_3 ;
+__sbit __at 0xEC P6_4 ;
+__sbit __at 0xED P6_5 ;
+__sbit __at 0xEE P6_6 ;
+__sbit __at 0xEF P6_7 ;
/* SPI0CN F8H */
-sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
-sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */
-sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */
-sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */
-sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
-sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
-sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
-sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
+__sbit __at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
+__sbit __at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */
+__sbit __at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */
+__sbit __at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */
+__sbit __at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
+__sbit __at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
+__sbit __at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
+__sbit __at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
/* P7 0xF8 */
-sbit at 0xF8 P7_0 ;
-sbit at 0xF9 P7_1 ;
-sbit at 0xFA P7_2 ;
-sbit at 0xFB P7_3 ;
-sbit at 0xFC P7_4 ;
-sbit at 0xFD P7_5 ;
-sbit at 0xFE P7_6 ;
-sbit at 0xFF P7_7 ;
+__sbit __at 0xF8 P7_0 ;
+__sbit __at 0xF9 P7_1 ;
+__sbit __at 0xFA P7_2 ;
+__sbit __at 0xFB P7_3 ;
+__sbit __at 0xFC P7_4 ;
+__sbit __at 0xFD P7_5 ;
+__sbit __at 0xFE P7_6 ;
+__sbit __at 0xFF P7_7 ;
/* Predefined SFR Bit Masks */
/* BYTE Registers */
-sfr at 0x80 P0 ; /* PORT 0 */
-sfr at 0x81 SP ; /* STACK POINTER */
-sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
-sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
-sfr at 0x87 PCON ; /* POWER CONTROL */
-sfr at 0x88 TCON ; /* TIMER CONTROL */
-sfr at 0x89 TMOD ; /* TIMER MODE */
-sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
-sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
-sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
-sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
-sfr at 0x8E CKCON ; /* CLOCK CONTROL */
-sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
-sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */
-sfr at 0x98 SCON0 ; /* SERIAL PORT CONTROL */
-sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */
-sfr at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */
-sfr at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
-sfr at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
-sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
-sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
-sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
-sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
-sfr at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
-sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
-sfr at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */
-sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
-sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
-sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
-sfr at 0xBE ADC0 ; /* ADC 0 DATA */
-sfr at 0xC0 SMB0CN ; /* SMBUS CONTROL */
-sfr at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */
-sfr at 0xC2 SMB0DAT ; /* SMBUS DATA */
-sfr at 0xC4 ADC0GT ; /* ADC 0 GREATER-THAN REGISTER */
-sfr at 0xC6 ADC0LT ; /* ADC 0 LESS-THAN REGISTER */
-sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */
-sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
-sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
-sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
-sfr at 0xD8 PCA0CN ; /* PCA CONTROL */
-sfr at 0xD9 PCA0MD ; /* PCA MODE */
-sfr at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
-sfr at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
-sfr at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
-sfr at 0xE0 ACC ; /* ACCUMULATOR */
-sfr at 0xE1 PRT0MX ; /* PORT MUX CONFIGURATION REGISTER 0 */
-sfr at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
-sfr at 0xE2 PRT1MX ; /* PORT MUX CONFIGURATION REGISTER 1 */
-sfr at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
-sfr at 0xE3 PRT2MX ; /* PORT MUX CONFIGURATION REGISTER 2 */
-sfr at 0xE3 XBR2 ; /* PORT MUX CONFIGURATION REGISTER 2 */
-sfr at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
-sfr at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
-sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
-sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
-sfr at 0xE9 PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
-sfr at 0xEA PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
-sfr at 0xEB PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
-sfr at 0xEC PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
-sfr at 0xEF RSTSRC ; /* RESET SOURCE */
-sfr at 0xF0 B ; /* B REGISTER */
-sfr at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
-sfr at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
-sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
-sfr at 0xF8 CPT0CN ; /* COMPARATOR 0 CONTROL */
-sfr at 0xF9 PCA0L ; /* PCA COUNTER LOW */
-sfr at 0xFA PCA0H ; /* PCA COUNTER HIGH */
-sfr at 0xFB PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
-sfr at 0xFC PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
+__sfr __at 0x80 P0 ; /* PORT 0 */
+__sfr __at 0x81 SP ; /* STACK POINTER */
+__sfr __at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
+__sfr __at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
+__sfr __at 0x87 PCON ; /* POWER CONTROL */
+__sfr __at 0x88 TCON ; /* TIMER CONTROL */
+__sfr __at 0x89 TMOD ; /* TIMER MODE */
+__sfr __at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
+__sfr __at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
+__sfr __at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
+__sfr __at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
+__sfr __at 0x8E CKCON ; /* CLOCK CONTROL */
+__sfr __at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
+__sfr __at 0x98 SCON ; /* SERIAL PORT CONTROL */
+__sfr __at 0x98 SCON0 ; /* SERIAL PORT CONTROL */
+__sfr __at 0x99 SBUF ; /* SERIAL PORT BUFFER */
+__sfr __at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */
+__sfr __at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
+__sfr __at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
+__sfr __at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA8 IE ; /* INTERRUPT ENABLE */
+__sfr __at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
+__sfr __at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
+__sfr __at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
+__sfr __at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
+__sfr __at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */
+__sfr __at 0xB8 IP ; /* INTERRUPT PRIORITY */
+__sfr __at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
+__sfr __at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
+__sfr __at 0xBE ADC0 ; /* ADC 0 DATA */
+__sfr __at 0xC0 SMB0CN ; /* SMBUS CONTROL */
+__sfr __at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */
+__sfr __at 0xC2 SMB0DAT ; /* SMBUS DATA */
+__sfr __at 0xC4 ADC0GT ; /* ADC 0 GREATER-THAN REGISTER */
+__sfr __at 0xC6 ADC0LT ; /* ADC 0 LESS-THAN REGISTER */
+__sfr __at 0xC8 T2CON ; /* TIMER 2 CONTROL */
+__sfr __at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
+__sfr __at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xD0 PSW ; /* PROGRAM STATUS WORD */
+__sfr __at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
+__sfr __at 0xD8 PCA0CN ; /* PCA CONTROL */
+__sfr __at 0xD9 PCA0MD ; /* PCA MODE */
+__sfr __at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
+__sfr __at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
+__sfr __at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
+__sfr __at 0xE0 ACC ; /* ACCUMULATOR */
+__sfr __at 0xE1 PRT0MX ; /* PORT MUX CONFIGURATION REGISTER 0 */
+__sfr __at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
+__sfr __at 0xE2 PRT1MX ; /* PORT MUX CONFIGURATION REGISTER 1 */
+__sfr __at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
+__sfr __at 0xE3 PRT2MX ; /* PORT MUX CONFIGURATION REGISTER 2 */
+__sfr __at 0xE3 XBR2 ; /* PORT MUX CONFIGURATION REGISTER 2 */
+__sfr __at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
+__sfr __at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
+__sfr __at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
+__sfr __at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
+__sfr __at 0xE9 PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
+__sfr __at 0xEA PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
+__sfr __at 0xEB PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
+__sfr __at 0xEC PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
+__sfr __at 0xEF RSTSRC ; /* RESET SOURCE */
+__sfr __at 0xF0 B ; /* B REGISTER */
+__sfr __at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
+__sfr __at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
+__sfr __at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
+__sfr __at 0xF8 CPT0CN ; /* COMPARATOR 0 CONTROL */
+__sfr __at 0xF9 PCA0L ; /* PCA COUNTER LOW */
+__sfr __at 0xFA PCA0H ; /* PCA COUNTER HIGH */
+__sfr __at 0xFB PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
+__sfr __at 0xFC PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
/* BIT Registers */
/* P0 0x80 */
-sbit at 0x80 P0_0 ;
-sbit at 0x81 P0_1 ;
-sbit at 0x82 P0_2 ;
-sbit at 0x83 P0_3 ;
-sbit at 0x84 P0_4 ;
-sbit at 0x85 P0_5 ;
-sbit at 0x86 P0_6 ;
-sbit at 0x87 P0_7 ;
+__sbit __at 0x80 P0_0 ;
+__sbit __at 0x81 P0_1 ;
+__sbit __at 0x82 P0_2 ;
+__sbit __at 0x83 P0_3 ;
+__sbit __at 0x84 P0_4 ;
+__sbit __at 0x85 P0_5 ;
+__sbit __at 0x86 P0_6 ;
+__sbit __at 0x87 P0_7 ;
/* TCON 0x88 */
-sbit at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
-sbit at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
-sbit at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
-sbit at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
-sbit at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
-sbit at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
-sbit at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
-sbit at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
+__sbit __at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
+__sbit __at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
+__sbit __at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
+__sbit __at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
+__sbit __at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
+__sbit __at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
+__sbit __at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
+__sbit __at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
/* SCON 0x98 */
-sbit at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
-sbit at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
-sbit at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
-sbit at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
-sbit at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */
-sbit at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */
-sbit at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
-sbit at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
-sbit at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */
-sbit at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */
-sbit at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
-sbit at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
-sbit at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
-sbit at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
+__sbit __at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
+__sbit __at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
+__sbit __at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
+__sbit __at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
+__sbit __at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */
+__sbit __at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */
+__sbit __at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
+__sbit __at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
+__sbit __at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */
+__sbit __at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */
+__sbit __at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
+__sbit __at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
+__sbit __at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
+__sbit __at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
/* IE 0xA8 */
-sbit at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
-sbit at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
-sbit at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
-sbit at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
-sbit at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
-sbit at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
-sbit at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
-sbit at 0xAE IEGF0 ; /* IE.6 - GENERAL PURPOSE FLAG 0 */
-sbit at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
+__sbit __at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
+__sbit __at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
+__sbit __at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
+__sbit __at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
+__sbit __at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
+__sbit __at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
+__sbit __at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
+__sbit __at 0xAE IEGF0 ; /* IE.6 - GENERAL PURPOSE FLAG 0 */
+__sbit __at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
/* IP 0xB8 */
-sbit at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
-sbit at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */
-sbit at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
-sbit at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */
-sbit at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */
-sbit at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
-sbit at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */
+__sbit __at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
+__sbit __at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */
+__sbit __at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
+__sbit __at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */
+__sbit __at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */
+__sbit __at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
+__sbit __at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */
/* SMB0CN 0xC0 */
-sbit at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
-sbit at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
-sbit at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
-sbit at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
-sbit at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
-sbit at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
-sbit at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
-sbit at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
+__sbit __at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
+__sbit __at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
+__sbit __at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
+__sbit __at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
+__sbit __at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
+__sbit __at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
+__sbit __at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
+__sbit __at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
/* TMR2CN 0xC8 */
-sbit at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
-sbit at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
-sbit at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
-sbit at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
-sbit at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
-sbit at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
-sbit at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
+__sbit __at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
+__sbit __at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
+__sbit __at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
+__sbit __at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
+__sbit __at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
+__sbit __at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
+__sbit __at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
/* PSW 0xD0 */
-sbit at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
-sbit at 0xD1 F1 ; /* PSW.1 - FLAG 1 */
-sbit at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */
-sbit at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
-sbit at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
-sbit at 0xD5 F0 ; /* PSW.5 - FLAG 0 */
-sbit at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
-sbit at 0xD7 CY ; /* PSW.7 - CARRY FLAG */
+__sbit __at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
+__sbit __at 0xD1 F1 ; /* PSW.1 - FLAG 1 */
+__sbit __at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */
+__sbit __at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
+__sbit __at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
+__sbit __at 0xD5 F0 ; /* PSW.5 - FLAG 0 */
+__sbit __at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
+__sbit __at 0xD7 CY ; /* PSW.7 - CARRY FLAG */
/* PCA0CN 0xD8 */
-sbit at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
-sbit at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
-sbit at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
-sbit at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
-sbit at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
+__sbit __at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
+__sbit __at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
+__sbit __at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
+__sbit __at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
+__sbit __at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
/* ADC0CN 0xE8 */
-sbit at 0xE8 AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
-sbit at 0xE9 AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
-sbit at 0xEA AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
-sbit at 0xEB AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
-sbit at 0xEC AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
-sbit at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
-sbit at 0xEE AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
-sbit at 0xEF AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
+__sbit __at 0xE8 AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
+__sbit __at 0xE9 AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
+__sbit __at 0xEA AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
+__sbit __at 0xEB AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
+__sbit __at 0xEC AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
+__sbit __at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
+__sbit __at 0xEE AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
+__sbit __at 0xEF AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
/* CPT0CN 0xF8 */
-sbit at 0xF8 CP0HYN0 ; /* CPT0CN.0 - Comp.0 Neg. Hysteresis Control Bit0*/
-sbit at 0xF9 CP0HYN1 ; /* CPT0CN.1 - Comp.0 Neg. Hysteresis Control Bit1*/
-sbit at 0xFA CP0HYP0 ; /* CPT0CN.2 - Comp.0 Pos. Hysteresis Control Bit0*/
-sbit at 0xFB CP0HYP1 ; /* CPT0CN.3 - Comp.0 Pos. Hysteresis Control Bit1*/
-sbit at 0xFC CP0FIF ; /* CPT0CN.4 - Comparator0 Falling-Edge Int. Flag */
-sbit at 0xFD CP0RIF ; /* CPT0CN.5 - Comparator0 Rising-Edge Int. Flag */
-sbit at 0xFE CP0OUT ; /* CPT0CN.6 - Comparator0 Output State Flag */
-sbit at 0xFF CP0EN ; /* CPT0CN.7 - Comparator0 Enable Bit */
+__sbit __at 0xF8 CP0HYN0 ; /* CPT0CN.0 - Comp.0 Neg. Hysteresis Control Bit0*/
+__sbit __at 0xF9 CP0HYN1 ; /* CPT0CN.1 - Comp.0 Neg. Hysteresis Control Bit1*/
+__sbit __at 0xFA CP0HYP0 ; /* CPT0CN.2 - Comp.0 Pos. Hysteresis Control Bit0*/
+__sbit __at 0xFB CP0HYP1 ; /* CPT0CN.3 - Comp.0 Pos. Hysteresis Control Bit1*/
+__sbit __at 0xFC CP0FIF ; /* CPT0CN.4 - Comparator0 Falling-Edge Int. Flag */
+__sbit __at 0xFD CP0RIF ; /* CPT0CN.5 - Comparator0 Rising-Edge Int. Flag */
+__sbit __at 0xFE CP0OUT ; /* CPT0CN.6 - Comparator0 Output State Flag */
+__sbit __at 0xFF CP0EN ; /* CPT0CN.7 - Comparator0 Enable Bit */
/* Predefined SFR Bit Masks */
/* BYTE Registers */
-sfr at 0x80 P0 ; /* PORT 0 */
-sfr at 0x81 SP ; /* STACK POINTER */
-sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
-sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
-sfr at 0x87 PCON ; /* POWER CONTROL */
-sfr at 0x88 TCON ; /* TIMER CONTROL */
-sfr at 0x89 TMOD ; /* TIMER MODE */
-sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
-sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
-sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
-sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
-sfr at 0x8E CKCON ; /* CLOCK CONTROL */
-sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
-sfr at 0x90 P1 ; /* PORT 1 */
-sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */
-sfr at 0x92 TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
-sfr at 0x93 TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */
-sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */
-sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */
-sfr at 0x98 SCON0 ; /* SERIAL PORT CONTROL */
-sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */
-sfr at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */
-sfr at 0x9A CPT1CN ; /* COMPARATOR 1 CONTROL */
-sfr at 0x9B CPT0CN ; /* COMPARATOR 0 CONTROL */
-sfr at 0x9C CPT1MD ; /* COMPARATOR 1 MODE SELECTION */
-sfr at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
-sfr at 0x9E CPT1MX ; /* COMPARATOR 1 MUX SELECTION */
-sfr at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
-sfr at 0xA0 P2 ; /* PORT 2 */
-sfr at 0xA1 SPI0CFG ; /* SPI0 CONFIGURATION */
-sfr at 0xA2 SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
-sfr at 0xA3 SPI0DAT ; /* SPI0 DATA */
-sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
-sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
-sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
-sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
-sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
-sfr at 0xA9 CLKSEL ; /* SYSTEM CLOCK SELECT */
-sfr at 0xAA EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
-sfr at 0xAA _XPAGE ; /* XDATA/PDATA PAGE */
-sfr at 0xB0 P3 ; /* PORT 3 */
-sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
-sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
-sfr at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
-sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
-sfr at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */
-sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
-sfr at 0xBA AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */
-sfr at 0xBB AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
-sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
-sfr at 0xBD ADC0L ; /* ADC 0 DATA WORD LSB */
-sfr at 0xBE ADC0H ; /* ADC 0 DATA WORD MSB */
-sfr at 0xC0 SMB0CN ; /* SMBUS CONTROL */
-sfr at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */
-sfr at 0xC2 SMB0DAT ; /* SMBUS DATA */
-sfr at 0xC3 ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */
-sfr at 0xC4 ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */
-sfr at 0xC5 ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */
-sfr at 0xC6 ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */
-sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */
-sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
-sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
-sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
-sfr at 0xD4 P0SKIP ; /* PORT 0 SKIP */
-sfr at 0xD5 P1SKIP ; /* PORT 1 SKIP */
-sfr at 0xD6 P2SKIP ; /* PORT 2 SKIP */
-sfr at 0xD8 PCA0CN ; /* PCA CONTROL */
-sfr at 0xD9 PCA0MD ; /* PCA MODE */
-sfr at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
-sfr at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
-sfr at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
-sfr at 0xDD PCA0CPM3 ; /* PCA MODULE 3 MODE REGISTER */
-sfr at 0xDE PCA0CPM4 ; /* PCA MODULE 4 MODE REGISTER */
-sfr at 0xE0 ACC ; /* ACCUMULATOR */
-sfr at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
-sfr at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
-sfr at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
-sfr at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
-sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
-sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
-sfr at 0xE9 PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
-sfr at 0xEA PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
-sfr at 0xEB PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
-sfr at 0xEC PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
-sfr at 0xED PCA0CPL3 ; /* PCA CAPTURE 3 LOW */
-sfr at 0xEE PCA0CPH3 ; /* PCA CAPTURE 3 HIGH */
-sfr at 0xEF RSTSRC ; /* RESET SOURCE */
-sfr at 0xF0 B ; /* B REGISTER */
-sfr at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
-sfr at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
-sfr at 0xF2 P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
-sfr at 0xF2 P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
-sfr at 0xF3 P2MODE ; /* PORT 2 INPUT MODE CONFIGURATION */
-sfr at 0xF3 P2MDIN ; /* PORT 2 INPUT MODE CONFIGURATION */
-sfr at 0xF4 P3MODE ; /* PORT 3 INPUT MODE CONFIGURATION */
-sfr at 0xF4 P3MDIN ; /* PORT 3 INPUT MODE CONFIGURATION */
-sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
-sfr at 0xF8 SPI0CN ; /* SPI0 CONTROL */
-sfr at 0xF9 PCA0L ; /* PCA COUNTER LOW */
-sfr at 0xFA PCA0H ; /* PCA COUNTER HIGH */
-sfr at 0xFB PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
-sfr at 0xFC PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
-sfr at 0xFD PCA0CPL4 ; /* PCA CAPTURE 4 LOW */
-sfr at 0xFE PCA0CPH4 ; /* PCA CAPTURE 4 HIGH */
-sfr at 0xFF VDM0CN ; /* VDD MONITOR CONTROL */
+__sfr __at 0x80 P0 ; /* PORT 0 */
+__sfr __at 0x81 SP ; /* STACK POINTER */
+__sfr __at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
+__sfr __at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
+__sfr __at 0x87 PCON ; /* POWER CONTROL */
+__sfr __at 0x88 TCON ; /* TIMER CONTROL */
+__sfr __at 0x89 TMOD ; /* TIMER MODE */
+__sfr __at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
+__sfr __at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
+__sfr __at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
+__sfr __at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
+__sfr __at 0x8E CKCON ; /* CLOCK CONTROL */
+__sfr __at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
+__sfr __at 0x90 P1 ; /* PORT 1 */
+__sfr __at 0x91 TMR3CN ; /* TIMER 3 CONTROL */
+__sfr __at 0x92 TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0x93 TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */
+__sfr __at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */
+__sfr __at 0x98 SCON ; /* SERIAL PORT CONTROL */
+__sfr __at 0x98 SCON0 ; /* SERIAL PORT CONTROL */
+__sfr __at 0x99 SBUF ; /* SERIAL PORT BUFFER */
+__sfr __at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */
+__sfr __at 0x9A CPT1CN ; /* COMPARATOR 1 CONTROL */
+__sfr __at 0x9B CPT0CN ; /* COMPARATOR 0 CONTROL */
+__sfr __at 0x9C CPT1MD ; /* COMPARATOR 1 MODE SELECTION */
+__sfr __at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
+__sfr __at 0x9E CPT1MX ; /* COMPARATOR 1 MUX SELECTION */
+__sfr __at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
+__sfr __at 0xA0 P2 ; /* PORT 2 */
+__sfr __at 0xA1 SPI0CFG ; /* SPI0 CONFIGURATION */
+__sfr __at 0xA2 SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
+__sfr __at 0xA3 SPI0DAT ; /* SPI0 DATA */
+__sfr __at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA8 IE ; /* INTERRUPT ENABLE */
+__sfr __at 0xA9 CLKSEL ; /* SYSTEM CLOCK SELECT */
+__sfr __at 0xAA EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
+__sfr __at 0xAA _XPAGE ; /* XDATA/PDATA PAGE */
+__sfr __at 0xB0 P3 ; /* PORT 3 */
+__sfr __at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
+__sfr __at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
+__sfr __at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
+__sfr __at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
+__sfr __at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */
+__sfr __at 0xB8 IP ; /* INTERRUPT PRIORITY */
+__sfr __at 0xBA AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */
+__sfr __at 0xBB AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
+__sfr __at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
+__sfr __at 0xBD ADC0L ; /* ADC 0 DATA WORD LSB */
+__sfr __at 0xBE ADC0H ; /* ADC 0 DATA WORD MSB */
+__sfr __at 0xC0 SMB0CN ; /* SMBUS CONTROL */
+__sfr __at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */
+__sfr __at 0xC2 SMB0DAT ; /* SMBUS DATA */
+__sfr __at 0xC3 ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */
+__sfr __at 0xC4 ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */
+__sfr __at 0xC5 ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */
+__sfr __at 0xC6 ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */
+__sfr __at 0xC8 T2CON ; /* TIMER 2 CONTROL */
+__sfr __at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
+__sfr __at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xD0 PSW ; /* PROGRAM STATUS WORD */
+__sfr __at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
+__sfr __at 0xD4 P0SKIP ; /* PORT 0 SKIP */
+__sfr __at 0xD5 P1SKIP ; /* PORT 1 SKIP */
+__sfr __at 0xD6 P2SKIP ; /* PORT 2 SKIP */
+__sfr __at 0xD8 PCA0CN ; /* PCA CONTROL */
+__sfr __at 0xD9 PCA0MD ; /* PCA MODE */
+__sfr __at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
+__sfr __at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
+__sfr __at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
+__sfr __at 0xDD PCA0CPM3 ; /* PCA MODULE 3 MODE REGISTER */
+__sfr __at 0xDE PCA0CPM4 ; /* PCA MODULE 4 MODE REGISTER */
+__sfr __at 0xE0 ACC ; /* ACCUMULATOR */
+__sfr __at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
+__sfr __at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
+__sfr __at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
+__sfr __at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
+__sfr __at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
+__sfr __at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
+__sfr __at 0xE9 PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
+__sfr __at 0xEA PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
+__sfr __at 0xEB PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
+__sfr __at 0xEC PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
+__sfr __at 0xED PCA0CPL3 ; /* PCA CAPTURE 3 LOW */
+__sfr __at 0xEE PCA0CPH3 ; /* PCA CAPTURE 3 HIGH */
+__sfr __at 0xEF RSTSRC ; /* RESET SOURCE */
+__sfr __at 0xF0 B ; /* B REGISTER */
+__sfr __at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
+__sfr __at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
+__sfr __at 0xF2 P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
+__sfr __at 0xF2 P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
+__sfr __at 0xF3 P2MODE ; /* PORT 2 INPUT MODE CONFIGURATION */
+__sfr __at 0xF3 P2MDIN ; /* PORT 2 INPUT MODE CONFIGURATION */
+__sfr __at 0xF4 P3MODE ; /* PORT 3 INPUT MODE CONFIGURATION */
+__sfr __at 0xF4 P3MDIN ; /* PORT 3 INPUT MODE CONFIGURATION */
+__sfr __at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
+__sfr __at 0xF8 SPI0CN ; /* SPI0 CONTROL */
+__sfr __at 0xF9 PCA0L ; /* PCA COUNTER LOW */
+__sfr __at 0xFA PCA0H ; /* PCA COUNTER HIGH */
+__sfr __at 0xFB PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
+__sfr __at 0xFC PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
+__sfr __at 0xFD PCA0CPL4 ; /* PCA CAPTURE 4 LOW */
+__sfr __at 0xFE PCA0CPH4 ; /* PCA CAPTURE 4 HIGH */
+__sfr __at 0xFF VDM0CN ; /* VDD MONITOR CONTROL */
/* BIT Registers */
/* P0 0x80 */
-sbit at 0x80 P0_0 ;
-sbit at 0x81 P0_1 ;
-sbit at 0x82 P0_2 ;
-sbit at 0x83 P0_3 ;
-sbit at 0x84 P0_4 ;
-sbit at 0x85 P0_5 ;
-sbit at 0x86 P0_6 ;
-sbit at 0x87 P0_7 ;
+__sbit __at 0x80 P0_0 ;
+__sbit __at 0x81 P0_1 ;
+__sbit __at 0x82 P0_2 ;
+__sbit __at 0x83 P0_3 ;
+__sbit __at 0x84 P0_4 ;
+__sbit __at 0x85 P0_5 ;
+__sbit __at 0x86 P0_6 ;
+__sbit __at 0x87 P0_7 ;
/* TCON 0x88 */
-sbit at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
-sbit at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
-sbit at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
-sbit at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
-sbit at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
-sbit at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
-sbit at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
-sbit at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
+__sbit __at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
+__sbit __at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
+__sbit __at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
+__sbit __at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
+__sbit __at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
+__sbit __at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
+__sbit __at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
+__sbit __at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
/* P1 0x90 */
-sbit at 0x90 P1_0 ;
-sbit at 0x91 P1_1 ;
-sbit at 0x92 P1_2 ;
-sbit at 0x93 P1_3 ;
-sbit at 0x94 P1_4 ;
-sbit at 0x95 P1_5 ;
-sbit at 0x96 P1_6 ;
-sbit at 0x97 P1_7 ;
+__sbit __at 0x90 P1_0 ;
+__sbit __at 0x91 P1_1 ;
+__sbit __at 0x92 P1_2 ;
+__sbit __at 0x93 P1_3 ;
+__sbit __at 0x94 P1_4 ;
+__sbit __at 0x95 P1_5 ;
+__sbit __at 0x96 P1_6 ;
+__sbit __at 0x97 P1_7 ;
/* SCON 0x98 */
-sbit at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
-sbit at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
-sbit at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
-sbit at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
-sbit at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */
-sbit at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */
-sbit at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
-sbit at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
-sbit at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */
-sbit at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */
-sbit at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
-sbit at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
-sbit at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
-sbit at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
+__sbit __at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
+__sbit __at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
+__sbit __at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
+__sbit __at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
+__sbit __at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */
+__sbit __at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */
+__sbit __at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
+__sbit __at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
+__sbit __at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */
+__sbit __at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */
+__sbit __at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
+__sbit __at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
+__sbit __at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
+__sbit __at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
/* P2 0xA0 */
-sbit at 0xA0 P2_0 ;
-sbit at 0xA1 P2_1 ;
-sbit at 0xA2 P2_2 ;
-sbit at 0xA3 P2_3 ;
-sbit at 0xA4 P2_4 ;
-sbit at 0xA5 P2_5 ;
-sbit at 0xA6 P2_6 ;
-sbit at 0xA7 P2_7 ;
+__sbit __at 0xA0 P2_0 ;
+__sbit __at 0xA1 P2_1 ;
+__sbit __at 0xA2 P2_2 ;
+__sbit __at 0xA3 P2_3 ;
+__sbit __at 0xA4 P2_4 ;
+__sbit __at 0xA5 P2_5 ;
+__sbit __at 0xA6 P2_6 ;
+__sbit __at 0xA7 P2_7 ;
/* IE 0xA8 */
-sbit at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
-sbit at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
-sbit at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
-sbit at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
-sbit at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
-sbit at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
-sbit at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
-sbit at 0xAE ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
-sbit at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
+__sbit __at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
+__sbit __at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
+__sbit __at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
+__sbit __at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
+__sbit __at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
+__sbit __at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
+__sbit __at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
+__sbit __at 0xAE ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
+__sbit __at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
/* P3 0xB0 */
-sbit at 0xB0 P3_0 ;
-sbit at 0xB1 P3_1 ;
-sbit at 0xB2 P3_2 ;
-sbit at 0xB3 P3_3 ;
-sbit at 0xB4 P3_4 ;
-sbit at 0xB5 P3_5 ;
-sbit at 0xB6 P3_6 ;
-sbit at 0xB7 P3_7 ;
+__sbit __at 0xB0 P3_0 ;
+__sbit __at 0xB1 P3_1 ;
+__sbit __at 0xB2 P3_2 ;
+__sbit __at 0xB3 P3_3 ;
+__sbit __at 0xB4 P3_4 ;
+__sbit __at 0xB5 P3_5 ;
+__sbit __at 0xB6 P3_6 ;
+__sbit __at 0xB7 P3_7 ;
/* IP 0xB8 */
-sbit at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
-sbit at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */
-sbit at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
-sbit at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */
-sbit at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */
-sbit at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
-sbit at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */
-sbit at 0xBE PSPI0 ; /* IP.6 - SPI0 PRIORITY */
+__sbit __at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
+__sbit __at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */
+__sbit __at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
+__sbit __at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */
+__sbit __at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */
+__sbit __at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
+__sbit __at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */
+__sbit __at 0xBE PSPI0 ; /* IP.6 - SPI0 PRIORITY */
/* SMB0CN 0xC0 */
-sbit at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
-sbit at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
-sbit at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
-sbit at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
-sbit at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
-sbit at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
-sbit at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
-sbit at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
+__sbit __at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
+__sbit __at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
+__sbit __at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
+__sbit __at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
+__sbit __at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
+__sbit __at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
+__sbit __at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
+__sbit __at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
/* TMR2CN 0xC8 */
-sbit at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
-sbit at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
-sbit at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
-sbit at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
-sbit at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
-sbit at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
-sbit at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
+__sbit __at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
+__sbit __at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
+__sbit __at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
+__sbit __at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
+__sbit __at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
+__sbit __at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
+__sbit __at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
/* PSW 0xD0 */
-sbit at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
-sbit at 0xD1 F1 ; /* PSW.1 - FLAG 1 */
-sbit at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */
-sbit at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
-sbit at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
-sbit at 0xD5 F0 ; /* PSW.5 - FLAG 0 */
-sbit at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
-sbit at 0xD7 CY ; /* PSW.7 - CARRY FLAG */
+__sbit __at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
+__sbit __at 0xD1 F1 ; /* PSW.1 - FLAG 1 */
+__sbit __at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */
+__sbit __at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
+__sbit __at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
+__sbit __at 0xD5 F0 ; /* PSW.5 - FLAG 0 */
+__sbit __at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
+__sbit __at 0xD7 CY ; /* PSW.7 - CARRY FLAG */
/* PCA0CN 0xD8 */
-sbit at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
-sbit at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
-sbit at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
-sbit at 0xDB CCF3 ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */
-sbit at 0xDC CCF4 ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */
-sbit at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
-sbit at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
+__sbit __at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
+__sbit __at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
+__sbit __at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
+__sbit __at 0xDB CCF3 ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */
+__sbit __at 0xDC CCF4 ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */
+__sbit __at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
+__sbit __at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
/* ADC0CN 0xE8 */
-sbit at 0xE8 AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
-sbit at 0xE9 AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
-sbit at 0xEA AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
-sbit at 0xEB AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
-sbit at 0xEC AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
-sbit at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
-sbit at 0xEE AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
-sbit at 0xEF AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
+__sbit __at 0xE8 AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
+__sbit __at 0xE9 AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
+__sbit __at 0xEA AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
+__sbit __at 0xEB AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
+__sbit __at 0xEC AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
+__sbit __at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
+__sbit __at 0xEE AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
+__sbit __at 0xEF AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
/* SPI0CN 0xF8 */
-sbit at 0xF8 SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
-sbit at 0xF9 TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
-sbit at 0xFA NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
-sbit at 0xFB NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
-sbit at 0xFC RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
-sbit at 0xFD MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
-sbit at 0xFE WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
-sbit at 0xFF SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
+__sbit __at 0xF8 SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
+__sbit __at 0xF9 TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
+__sbit __at 0xFA NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
+__sbit __at 0xFB NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
+__sbit __at 0xFC RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
+__sbit __at 0xFD MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
+__sbit __at 0xFE WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
+__sbit __at 0xFF SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
/* Predefined SFR Bit Masks */
/* BYTE Registers */
-sfr at 0x80 P0 ; /* PORT 0 */
-sfr at 0x81 SP ; /* STACK POINTER */
-sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
-sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
-sfr at 0x87 PCON ; /* POWER CONTROL */
-sfr at 0x88 TCON ; /* TIMER CONTROL */
-sfr at 0x89 TMOD ; /* TIMER MODE */
-sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
-sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
-sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
-sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
-sfr at 0x8E CKCON ; /* CLOCK CONTROL */
-sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
-sfr at 0x90 P1 ; /* PORT 1 */
-sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */
-sfr at 0x92 TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
-sfr at 0x93 TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */
-sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */
-sfr at 0x96 USB0ADR ; /* USB0 INDIRECT ADDRESS REGISTER */
-sfr at 0x97 USB0DAT ; /* USB0 DATA REGISTER */
-sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */
-sfr at 0x98 SCON0 ; /* SERIAL PORT CONTROL */
-sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */
-sfr at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */
-sfr at 0x9A CPT1CN ; /* COMPARATOR 1 CONTROL */
-sfr at 0x9B CPT0CN ; /* COMPARATOR 0 CONTROL */
-sfr at 0x9C CPT1MD ; /* COMPARATOR 1 MODE SELECTION */
-sfr at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
-sfr at 0x9E CPT1MX ; /* COMPARATOR 1 MUX SELECTION */
-sfr at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
-sfr at 0xA0 P2 ; /* PORT 2 */
-sfr at 0xA1 SPI0CFG ; /* SPI0 CONFIGURATION */
-sfr at 0xA2 SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
-sfr at 0xA3 SPI0DAT ; /* SPI0 DATA */
-sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
-sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
-sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
-sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
-sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
-sfr at 0xA9 CLKSEL ; /* SYSTEM CLOCK SELECT */
-sfr at 0xAA EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
-sfr at 0xAA _XPAGE ; /* XDATA/PDATA PAGE */
-sfr at 0xB0 P3 ; /* PORT 3 */
-sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
-sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
-sfr at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
-sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
-sfr at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */
-sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
-sfr at 0xB9 CLKMUL ; /* CLOCK MULTIPLIER CONTROL REGISTER */
-sfr at 0xBA AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */
-sfr at 0xBB AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
-sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
-sfr at 0xBD ADC0L ; /* ADC 0 DATA WORD LSB */
-sfr at 0xBE ADC0H ; /* ADC 0 DATA WORD MSB */
-sfr at 0xC0 SMB0CN ; /* SMBUS CONTROL */
-sfr at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */
-sfr at 0xC2 SMB0DAT ; /* SMBUS DATA */
-sfr at 0xC3 ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */
-sfr at 0xC4 ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */
-sfr at 0xC5 ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */
-sfr at 0xC6 ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */
-sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */
-sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
-sfr at 0xC9 REG0CN ; /* VOLTAGE REGULATOR CONTROL */
-sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
-sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
-sfr at 0xD4 P0SKIP ; /* PORT 0 SKIP */
-sfr at 0xD5 P1SKIP ; /* PORT 1 SKIP */
-sfr at 0xD6 P2SKIP ; /* PORT 2 SKIP */
-sfr at 0xD7 USB0XCN ; /* USB0 TRANSCEIVER CONTROL */
-sfr at 0xD8 PCA0CN ; /* PCA CONTROL */
-sfr at 0xD9 PCA0MD ; /* PCA MODE */
-sfr at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
-sfr at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
-sfr at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
-sfr at 0xDD PCA0CPM3 ; /* PCA MODULE 3 MODE REGISTER */
-sfr at 0xDE PCA0CPM4 ; /* PCA MODULE 4 MODE REGISTER */
-sfr at 0xE0 ACC ; /* ACCUMULATOR */
-sfr at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
-sfr at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
-sfr at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
-sfr at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
-sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
-sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
-sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
-sfr at 0xE9 PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
-sfr at 0xEA PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
-sfr at 0xEB PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
-sfr at 0xEC PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
-sfr at 0xED PCA0CPL3 ; /* PCA CAPTURE 3 LOW */
-sfr at 0xEE PCA0CPH3 ; /* PCA CAPTURE 3 HIGH */
-sfr at 0xEF RSTSRC ; /* RESET SOURCE */
-sfr at 0xF0 B ; /* B REGISTER */
-sfr at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
-sfr at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
-sfr at 0xF2 P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
-sfr at 0xF2 P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
-sfr at 0xF3 P2MODE ; /* PORT 2 INPUT MODE CONFIGURATION */
-sfr at 0xF3 P2MDIN ; /* PORT 2 INPUT MODE CONFIGURATION */
-sfr at 0xF4 P3MODE ; /* PORT 3 INPUT MODE CONFIGURATION */
-sfr at 0xF4 P3MDIN ; /* PORT 3 INPUT MODE CONFIGURATION */
-sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
-sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
-sfr at 0xF8 SPI0CN ; /* SPI0 CONTROL */
-sfr at 0xF9 PCA0L ; /* PCA COUNTER LOW */
-sfr at 0xFA PCA0H ; /* PCA COUNTER HIGH */
-sfr at 0xFB PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
-sfr at 0xFC PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
-sfr at 0xFD PCA0CPL4 ; /* PCA CAPTURE 4 LOW */
-sfr at 0xFE PCA0CPH4 ; /* PCA CAPTURE 4 HIGH */
-sfr at 0xFF VDM0CN ; /* VDD MONITOR CONTROL */
+__sfr __at 0x80 P0 ; /* PORT 0 */
+__sfr __at 0x81 SP ; /* STACK POINTER */
+__sfr __at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
+__sfr __at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
+__sfr __at 0x87 PCON ; /* POWER CONTROL */
+__sfr __at 0x88 TCON ; /* TIMER CONTROL */
+__sfr __at 0x89 TMOD ; /* TIMER MODE */
+__sfr __at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
+__sfr __at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
+__sfr __at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
+__sfr __at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
+__sfr __at 0x8E CKCON ; /* CLOCK CONTROL */
+__sfr __at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
+__sfr __at 0x90 P1 ; /* PORT 1 */
+__sfr __at 0x91 TMR3CN ; /* TIMER 3 CONTROL */
+__sfr __at 0x92 TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0x93 TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */
+__sfr __at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */
+__sfr __at 0x96 USB0ADR ; /* USB0 INDIRECT ADDRESS REGISTER */
+__sfr __at 0x97 USB0DAT ; /* USB0 DATA REGISTER */
+__sfr __at 0x98 SCON ; /* SERIAL PORT CONTROL */
+__sfr __at 0x98 SCON0 ; /* SERIAL PORT CONTROL */
+__sfr __at 0x99 SBUF ; /* SERIAL PORT BUFFER */
+__sfr __at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */
+__sfr __at 0x9A CPT1CN ; /* COMPARATOR 1 CONTROL */
+__sfr __at 0x9B CPT0CN ; /* COMPARATOR 0 CONTROL */
+__sfr __at 0x9C CPT1MD ; /* COMPARATOR 1 MODE SELECTION */
+__sfr __at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
+__sfr __at 0x9E CPT1MX ; /* COMPARATOR 1 MUX SELECTION */
+__sfr __at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
+__sfr __at 0xA0 P2 ; /* PORT 2 */
+__sfr __at 0xA1 SPI0CFG ; /* SPI0 CONFIGURATION */
+__sfr __at 0xA2 SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
+__sfr __at 0xA3 SPI0DAT ; /* SPI0 DATA */
+__sfr __at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA8 IE ; /* INTERRUPT ENABLE */
+__sfr __at 0xA9 CLKSEL ; /* SYSTEM CLOCK SELECT */
+__sfr __at 0xAA EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
+__sfr __at 0xAA _XPAGE ; /* XDATA/PDATA PAGE */
+__sfr __at 0xB0 P3 ; /* PORT 3 */
+__sfr __at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
+__sfr __at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
+__sfr __at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
+__sfr __at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
+__sfr __at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */
+__sfr __at 0xB8 IP ; /* INTERRUPT PRIORITY */
+__sfr __at 0xB9 CLKMUL ; /* CLOCK MULTIPLIER CONTROL REGISTER */
+__sfr __at 0xBA AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */
+__sfr __at 0xBB AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
+__sfr __at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
+__sfr __at 0xBD ADC0L ; /* ADC 0 DATA WORD LSB */
+__sfr __at 0xBE ADC0H ; /* ADC 0 DATA WORD MSB */
+__sfr __at 0xC0 SMB0CN ; /* SMBUS CONTROL */
+__sfr __at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */
+__sfr __at 0xC2 SMB0DAT ; /* SMBUS DATA */
+__sfr __at 0xC3 ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */
+__sfr __at 0xC4 ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */
+__sfr __at 0xC5 ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */
+__sfr __at 0xC6 ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */
+__sfr __at 0xC8 T2CON ; /* TIMER 2 CONTROL */
+__sfr __at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
+__sfr __at 0xC9 REG0CN ; /* VOLTAGE REGULATOR CONTROL */
+__sfr __at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xD0 PSW ; /* PROGRAM STATUS WORD */
+__sfr __at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
+__sfr __at 0xD4 P0SKIP ; /* PORT 0 SKIP */
+__sfr __at 0xD5 P1SKIP ; /* PORT 1 SKIP */
+__sfr __at 0xD6 P2SKIP ; /* PORT 2 SKIP */
+__sfr __at 0xD7 USB0XCN ; /* USB0 TRANSCEIVER CONTROL */
+__sfr __at 0xD8 PCA0CN ; /* PCA CONTROL */
+__sfr __at 0xD9 PCA0MD ; /* PCA MODE */
+__sfr __at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
+__sfr __at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
+__sfr __at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
+__sfr __at 0xDD PCA0CPM3 ; /* PCA MODULE 3 MODE REGISTER */
+__sfr __at 0xDE PCA0CPM4 ; /* PCA MODULE 4 MODE REGISTER */
+__sfr __at 0xE0 ACC ; /* ACCUMULATOR */
+__sfr __at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
+__sfr __at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
+__sfr __at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
+__sfr __at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
+__sfr __at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
+__sfr __at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
+__sfr __at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
+__sfr __at 0xE9 PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
+__sfr __at 0xEA PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
+__sfr __at 0xEB PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
+__sfr __at 0xEC PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
+__sfr __at 0xED PCA0CPL3 ; /* PCA CAPTURE 3 LOW */
+__sfr __at 0xEE PCA0CPH3 ; /* PCA CAPTURE 3 HIGH */
+__sfr __at 0xEF RSTSRC ; /* RESET SOURCE */
+__sfr __at 0xF0 B ; /* B REGISTER */
+__sfr __at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
+__sfr __at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
+__sfr __at 0xF2 P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
+__sfr __at 0xF2 P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
+__sfr __at 0xF3 P2MODE ; /* PORT 2 INPUT MODE CONFIGURATION */
+__sfr __at 0xF3 P2MDIN ; /* PORT 2 INPUT MODE CONFIGURATION */
+__sfr __at 0xF4 P3MODE ; /* PORT 3 INPUT MODE CONFIGURATION */
+__sfr __at 0xF4 P3MDIN ; /* PORT 3 INPUT MODE CONFIGURATION */
+__sfr __at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
+__sfr __at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
+__sfr __at 0xF8 SPI0CN ; /* SPI0 CONTROL */
+__sfr __at 0xF9 PCA0L ; /* PCA COUNTER LOW */
+__sfr __at 0xFA PCA0H ; /* PCA COUNTER HIGH */
+__sfr __at 0xFB PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
+__sfr __at 0xFC PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
+__sfr __at 0xFD PCA0CPL4 ; /* PCA CAPTURE 4 LOW */
+__sfr __at 0xFE PCA0CPH4 ; /* PCA CAPTURE 4 HIGH */
+__sfr __at 0xFF VDM0CN ; /* VDD MONITOR CONTROL */
/* BIT Registers */
/* P0 0x80 */
-sbit at 0x80 P0_0 ;
-sbit at 0x81 P0_1 ;
-sbit at 0x82 P0_2 ;
-sbit at 0x83 P0_3 ;
-sbit at 0x84 P0_4 ;
-sbit at 0x85 P0_5 ;
-sbit at 0x86 P0_6 ;
-sbit at 0x87 P0_7 ;
+__sbit __at 0x80 P0_0 ;
+__sbit __at 0x81 P0_1 ;
+__sbit __at 0x82 P0_2 ;
+__sbit __at 0x83 P0_3 ;
+__sbit __at 0x84 P0_4 ;
+__sbit __at 0x85 P0_5 ;
+__sbit __at 0x86 P0_6 ;
+__sbit __at 0x87 P0_7 ;
/* TCON 0x88 */
-sbit at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
-sbit at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
-sbit at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
-sbit at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
-sbit at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
-sbit at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
-sbit at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
-sbit at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
+__sbit __at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
+__sbit __at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
+__sbit __at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
+__sbit __at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
+__sbit __at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
+__sbit __at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
+__sbit __at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
+__sbit __at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
/* P1 0x90 */
-sbit at 0x90 P1_0 ;
-sbit at 0x91 P1_1 ;
-sbit at 0x92 P1_2 ;
-sbit at 0x93 P1_3 ;
-sbit at 0x94 P1_4 ;
-sbit at 0x95 P1_5 ;
-sbit at 0x96 P1_6 ;
-sbit at 0x97 P1_7 ;
+__sbit __at 0x90 P1_0 ;
+__sbit __at 0x91 P1_1 ;
+__sbit __at 0x92 P1_2 ;
+__sbit __at 0x93 P1_3 ;
+__sbit __at 0x94 P1_4 ;
+__sbit __at 0x95 P1_5 ;
+__sbit __at 0x96 P1_6 ;
+__sbit __at 0x97 P1_7 ;
/* SCON 0x98 */
-sbit at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
-sbit at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
-sbit at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
-sbit at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
-sbit at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */
-sbit at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */
-sbit at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
-sbit at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
-sbit at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */
-sbit at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */
-sbit at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
-sbit at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
-sbit at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
-sbit at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
+__sbit __at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
+__sbit __at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
+__sbit __at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
+__sbit __at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
+__sbit __at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */
+__sbit __at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */
+__sbit __at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
+__sbit __at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
+__sbit __at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */
+__sbit __at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */
+__sbit __at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
+__sbit __at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
+__sbit __at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
+__sbit __at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
/* P2 0xA0 */
-sbit at 0xA0 P2_0 ;
-sbit at 0xA1 P2_1 ;
-sbit at 0xA2 P2_2 ;
-sbit at 0xA3 P2_3 ;
-sbit at 0xA4 P2_4 ;
-sbit at 0xA5 P2_5 ;
-sbit at 0xA6 P2_6 ;
-sbit at 0xA7 P2_7 ;
+__sbit __at 0xA0 P2_0 ;
+__sbit __at 0xA1 P2_1 ;
+__sbit __at 0xA2 P2_2 ;
+__sbit __at 0xA3 P2_3 ;
+__sbit __at 0xA4 P2_4 ;
+__sbit __at 0xA5 P2_5 ;
+__sbit __at 0xA6 P2_6 ;
+__sbit __at 0xA7 P2_7 ;
/* IE 0xA8 */
-sbit at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
-sbit at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
-sbit at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
-sbit at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
-sbit at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
-sbit at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
-sbit at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
-sbit at 0xAE ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
-sbit at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
+__sbit __at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
+__sbit __at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
+__sbit __at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
+__sbit __at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
+__sbit __at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
+__sbit __at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
+__sbit __at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
+__sbit __at 0xAE ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
+__sbit __at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
/* P3 0xB0 */
-sbit at 0xB0 P3_0 ;
-sbit at 0xB1 P3_1 ;
-sbit at 0xB2 P3_2 ;
-sbit at 0xB3 P3_3 ;
-sbit at 0xB4 P3_4 ;
-sbit at 0xB5 P3_5 ;
-sbit at 0xB6 P3_6 ;
-sbit at 0xB7 P3_7 ;
+__sbit __at 0xB0 P3_0 ;
+__sbit __at 0xB1 P3_1 ;
+__sbit __at 0xB2 P3_2 ;
+__sbit __at 0xB3 P3_3 ;
+__sbit __at 0xB4 P3_4 ;
+__sbit __at 0xB5 P3_5 ;
+__sbit __at 0xB6 P3_6 ;
+__sbit __at 0xB7 P3_7 ;
/* IP 0xB8 */
-sbit at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
-sbit at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */
-sbit at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
-sbit at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */
-sbit at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */
-sbit at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
-sbit at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */
-sbit at 0xBE PSPI0 ; /* IP.6 - SPI0 PRIORITY */
+__sbit __at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
+__sbit __at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */
+__sbit __at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
+__sbit __at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */
+__sbit __at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */
+__sbit __at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
+__sbit __at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */
+__sbit __at 0xBE PSPI0 ; /* IP.6 - SPI0 PRIORITY */
/* SMB0CN 0xC0 */
-sbit at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
-sbit at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
-sbit at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
-sbit at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
-sbit at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
-sbit at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
-sbit at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
-sbit at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
+__sbit __at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
+__sbit __at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
+__sbit __at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
+__sbit __at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
+__sbit __at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
+__sbit __at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
+__sbit __at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
+__sbit __at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
/* TMR2CN 0xC8 */
-sbit at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
-sbit at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
-sbit at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
-sbit at 0xCC T2SOF ; /* TMR2CN.4 - TIMER 2 START_OF_FRAME CAPTURE ENA */
-sbit at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
-sbit at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
-sbit at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
-sbit at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
+__sbit __at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
+__sbit __at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
+__sbit __at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
+__sbit __at 0xCC T2SOF ; /* TMR2CN.4 - TIMER 2 START_OF_FRAME CAPTURE ENA */
+__sbit __at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
+__sbit __at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
+__sbit __at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
+__sbit __at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
/* PSW 0xD0 */
-sbit at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
-sbit at 0xD1 F1 ; /* PSW.1 - FLAG 1 */
-sbit at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */
-sbit at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
-sbit at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
-sbit at 0xD5 F0 ; /* PSW.5 - FLAG 0 */
-sbit at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
-sbit at 0xD7 CY ; /* PSW.7 - CARRY FLAG */
+__sbit __at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
+__sbit __at 0xD1 F1 ; /* PSW.1 - FLAG 1 */
+__sbit __at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */
+__sbit __at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
+__sbit __at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
+__sbit __at 0xD5 F0 ; /* PSW.5 - FLAG 0 */
+__sbit __at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
+__sbit __at 0xD7 CY ; /* PSW.7 - CARRY FLAG */
/* PCA0CN 0xD8 */
-sbit at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
-sbit at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
-sbit at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
-sbit at 0xDB CCF3 ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */
-sbit at 0xDC CCF4 ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */
-sbit at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
-sbit at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
+__sbit __at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
+__sbit __at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
+__sbit __at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
+__sbit __at 0xDB CCF3 ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */
+__sbit __at 0xDC CCF4 ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */
+__sbit __at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
+__sbit __at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
/* ADC0CN 0xE8 */
-sbit at 0xE8 AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
-sbit at 0xE9 AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
-sbit at 0xEA AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
-sbit at 0xEB AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
-sbit at 0xEC AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
-sbit at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
-sbit at 0xEE AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
-sbit at 0xEF AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
+__sbit __at 0xE8 AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
+__sbit __at 0xE9 AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
+__sbit __at 0xEA AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
+__sbit __at 0xEB AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
+__sbit __at 0xEC AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
+__sbit __at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
+__sbit __at 0xEE AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
+__sbit __at 0xEF AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
/* SPI0CN 0xF8 */
-sbit at 0xF8 SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
-sbit at 0xF9 TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
-sbit at 0xFA NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
-sbit at 0xFB NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
-sbit at 0xFC RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
-sbit at 0xFD MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
-sbit at 0xFE WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
-sbit at 0xFF SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
+__sbit __at 0xF8 SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
+__sbit __at 0xF9 TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
+__sbit __at 0xFA NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
+__sbit __at 0xFB NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
+__sbit __at 0xFC RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
+__sbit __at 0xFD MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
+__sbit __at 0xFE WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
+__sbit __at 0xFF SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
/* Predefined SFR Bit Masks */
/* BYTE Registers */
-sfr at 0x80 P0 ; /* PORT 0 */
-sfr at 0x81 SP ; /* STACK POINTER */
-sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
-sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
-sfr at 0x87 PCON ; /* POWER CONTROL */
-sfr at 0x88 TCON ; /* TIMER CONTROL */
-sfr at 0x89 TMOD ; /* TIMER MODE */
-sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
-sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
-sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
-sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
-sfr at 0x8E CKCON ; /* CLOCK CONTROL */
-sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
-sfr at 0x90 P1 ; /* PORT 1 */
-sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */
-sfr at 0x92 TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
-sfr at 0x93 TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */
-sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */
-sfr at 0x96 IDA0L ; /* CURRENT MODE DAC 0 - LOW BYTE */
-sfr at 0x97 IDA0H ; /* CURRENT MODE DAC 0 - HIGH BYTE */
-sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */
-sfr at 0x98 SCON0 ; /* SERIAL PORT CONTROL */
-sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */
-sfr at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */
-sfr at 0x9B CPT0CN ; /* COMPARATOR 0 CONTROL */
-sfr at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
-sfr at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
-sfr at 0xA0 P2 ; /* PORT 2 */
-sfr at 0xA1 SPI0CFG ; /* SPI0 CONFIGURATION */
-sfr at 0xA2 SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
-sfr at 0xA3 SPI0DAT ; /* SPI0 DATA */
-sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
-sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
-sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
-sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
-sfr at 0xA9 CLKSEL ; /* SYSTEM CLOCK SELECT */
-sfr at 0xAA EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
-sfr at 0xAA _XPAGE ; /* XDATA/PDATA PAGE */
-sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
-sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
-sfr at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
-sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
-sfr at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */
-sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
-sfr at 0xB9 IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */
-sfr at 0xBA AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */
-sfr at 0xBB AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
-sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
-sfr at 0xBD ADC0L ; /* ADC 0 DATA WORD LSB */
-sfr at 0xBE ADC0H ; /* ADC 0 DATA WORD MSB */
-sfr at 0xC0 SMB0CN ; /* SMBUS CONTROL */
-sfr at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */
-sfr at 0xC2 SMB0DAT ; /* SMBUS DATA */
-sfr at 0xC3 ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */
-sfr at 0xC4 ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */
-sfr at 0xC5 ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */
-sfr at 0xC6 ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */
-sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */
-sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
-sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
-sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
-sfr at 0xD4 P0SKIP ; /* PORT 0 SKIP */
-sfr at 0xD5 P1SKIP ; /* PORT 1 SKIP */
-sfr at 0xD8 PCA0CN ; /* PCA CONTROL */
-sfr at 0xD9 PCA0MD ; /* PCA MODE */
-sfr at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
-sfr at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
-sfr at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
-sfr at 0xE0 ACC ; /* ACCUMULATOR */
-sfr at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
-sfr at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
-sfr at 0xE3 OSCLCN ; /* LOW-FREQUENCY OSCILLATOR CONTROL */
-sfr at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
-sfr at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
-sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
-sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
-sfr at 0xE9 PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
-sfr at 0xEA PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
-sfr at 0xEB PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
-sfr at 0xEC PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
-sfr at 0xEF RSTSRC ; /* RESET SOURCE */
-sfr at 0xF0 B ; /* B REGISTER */
-sfr at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
-sfr at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
-sfr at 0xF2 P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
-sfr at 0xF2 P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
-sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
-sfr at 0xF8 SPI0CN ; /* SPI0 CONTROL */
-sfr at 0xF9 PCA0L ; /* PCA COUNTER LOW */
-sfr at 0xFA PCA0H ; /* PCA COUNTER HIGH */
-sfr at 0xFB PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
-sfr at 0xFC PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
-sfr at 0xFF VDM0CN ; /* VDD MONITOR CONTROL */
+__sfr __at 0x80 P0 ; /* PORT 0 */
+__sfr __at 0x81 SP ; /* STACK POINTER */
+__sfr __at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
+__sfr __at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
+__sfr __at 0x87 PCON ; /* POWER CONTROL */
+__sfr __at 0x88 TCON ; /* TIMER CONTROL */
+__sfr __at 0x89 TMOD ; /* TIMER MODE */
+__sfr __at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
+__sfr __at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
+__sfr __at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
+__sfr __at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
+__sfr __at 0x8E CKCON ; /* CLOCK CONTROL */
+__sfr __at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
+__sfr __at 0x90 P1 ; /* PORT 1 */
+__sfr __at 0x91 TMR3CN ; /* TIMER 3 CONTROL */
+__sfr __at 0x92 TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0x93 TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */
+__sfr __at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */
+__sfr __at 0x96 IDA0L ; /* CURRENT MODE DAC 0 - LOW BYTE */
+__sfr __at 0x97 IDA0H ; /* CURRENT MODE DAC 0 - HIGH BYTE */
+__sfr __at 0x98 SCON ; /* SERIAL PORT CONTROL */
+__sfr __at 0x98 SCON0 ; /* SERIAL PORT CONTROL */
+__sfr __at 0x99 SBUF ; /* SERIAL PORT BUFFER */
+__sfr __at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */
+__sfr __at 0x9B CPT0CN ; /* COMPARATOR 0 CONTROL */
+__sfr __at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
+__sfr __at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
+__sfr __at 0xA0 P2 ; /* PORT 2 */
+__sfr __at 0xA1 SPI0CFG ; /* SPI0 CONFIGURATION */
+__sfr __at 0xA2 SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
+__sfr __at 0xA3 SPI0DAT ; /* SPI0 DATA */
+__sfr __at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA8 IE ; /* INTERRUPT ENABLE */
+__sfr __at 0xA9 CLKSEL ; /* SYSTEM CLOCK SELECT */
+__sfr __at 0xAA EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
+__sfr __at 0xAA _XPAGE ; /* XDATA/PDATA PAGE */
+__sfr __at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
+__sfr __at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
+__sfr __at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
+__sfr __at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
+__sfr __at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */
+__sfr __at 0xB8 IP ; /* INTERRUPT PRIORITY */
+__sfr __at 0xB9 IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */
+__sfr __at 0xBA AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */
+__sfr __at 0xBB AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
+__sfr __at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
+__sfr __at 0xBD ADC0L ; /* ADC 0 DATA WORD LSB */
+__sfr __at 0xBE ADC0H ; /* ADC 0 DATA WORD MSB */
+__sfr __at 0xC0 SMB0CN ; /* SMBUS CONTROL */
+__sfr __at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */
+__sfr __at 0xC2 SMB0DAT ; /* SMBUS DATA */
+__sfr __at 0xC3 ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */
+__sfr __at 0xC4 ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */
+__sfr __at 0xC5 ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */
+__sfr __at 0xC6 ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */
+__sfr __at 0xC8 T2CON ; /* TIMER 2 CONTROL */
+__sfr __at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
+__sfr __at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xD0 PSW ; /* PROGRAM STATUS WORD */
+__sfr __at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
+__sfr __at 0xD4 P0SKIP ; /* PORT 0 SKIP */
+__sfr __at 0xD5 P1SKIP ; /* PORT 1 SKIP */
+__sfr __at 0xD8 PCA0CN ; /* PCA CONTROL */
+__sfr __at 0xD9 PCA0MD ; /* PCA MODE */
+__sfr __at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
+__sfr __at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
+__sfr __at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
+__sfr __at 0xE0 ACC ; /* ACCUMULATOR */
+__sfr __at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
+__sfr __at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
+__sfr __at 0xE3 OSCLCN ; /* LOW-FREQUENCY OSCILLATOR CONTROL */
+__sfr __at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
+__sfr __at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
+__sfr __at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
+__sfr __at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
+__sfr __at 0xE9 PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
+__sfr __at 0xEA PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
+__sfr __at 0xEB PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
+__sfr __at 0xEC PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
+__sfr __at 0xEF RSTSRC ; /* RESET SOURCE */
+__sfr __at 0xF0 B ; /* B REGISTER */
+__sfr __at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
+__sfr __at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
+__sfr __at 0xF2 P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
+__sfr __at 0xF2 P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
+__sfr __at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
+__sfr __at 0xF8 SPI0CN ; /* SPI0 CONTROL */
+__sfr __at 0xF9 PCA0L ; /* PCA COUNTER LOW */
+__sfr __at 0xFA PCA0H ; /* PCA COUNTER HIGH */
+__sfr __at 0xFB PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
+__sfr __at 0xFC PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
+__sfr __at 0xFF VDM0CN ; /* VDD MONITOR CONTROL */
/* BIT Registers */
/* P0 0x80 */
-sbit at 0x80 P0_0 ;
-sbit at 0x81 P0_1 ;
-sbit at 0x82 P0_2 ;
-sbit at 0x83 P0_3 ;
-sbit at 0x84 P0_4 ;
-sbit at 0x85 P0_5 ;
-sbit at 0x86 P0_6 ;
-sbit at 0x87 P0_7 ;
+__sbit __at 0x80 P0_0 ;
+__sbit __at 0x81 P0_1 ;
+__sbit __at 0x82 P0_2 ;
+__sbit __at 0x83 P0_3 ;
+__sbit __at 0x84 P0_4 ;
+__sbit __at 0x85 P0_5 ;
+__sbit __at 0x86 P0_6 ;
+__sbit __at 0x87 P0_7 ;
/* TCON 0x88 */
-sbit at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
-sbit at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
-sbit at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
-sbit at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
-sbit at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
-sbit at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
-sbit at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
-sbit at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
+__sbit __at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
+__sbit __at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
+__sbit __at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
+__sbit __at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
+__sbit __at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
+__sbit __at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
+__sbit __at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
+__sbit __at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
/* P1 0x90 */
-sbit at 0x90 P1_0 ;
-sbit at 0x91 P1_1 ;
-sbit at 0x92 P1_2 ;
-sbit at 0x93 P1_3 ;
-sbit at 0x94 P1_4 ;
-sbit at 0x95 P1_5 ;
-sbit at 0x96 P1_6 ;
-sbit at 0x97 P1_7 ;
+__sbit __at 0x90 P1_0 ;
+__sbit __at 0x91 P1_1 ;
+__sbit __at 0x92 P1_2 ;
+__sbit __at 0x93 P1_3 ;
+__sbit __at 0x94 P1_4 ;
+__sbit __at 0x95 P1_5 ;
+__sbit __at 0x96 P1_6 ;
+__sbit __at 0x97 P1_7 ;
/* SCON 0x98 */
-sbit at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
-sbit at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
-sbit at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
-sbit at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
-sbit at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */
-sbit at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */
-sbit at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
-sbit at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
-sbit at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */
-sbit at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */
-sbit at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
-sbit at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
-sbit at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
-sbit at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
+__sbit __at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
+__sbit __at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
+__sbit __at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
+__sbit __at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
+__sbit __at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */
+__sbit __at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */
+__sbit __at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
+__sbit __at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
+__sbit __at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */
+__sbit __at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */
+__sbit __at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
+__sbit __at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
+__sbit __at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
+__sbit __at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
/* P2 0xA0 */
-sbit at 0xA0 P2_0 ;
-sbit at 0xA1 P2_1 ;
-sbit at 0xA2 P2_2 ;
-sbit at 0xA3 P2_3 ;
-sbit at 0xA4 P2_4 ;
-sbit at 0xA5 P2_5 ;
-sbit at 0xA6 P2_6 ;
-sbit at 0xA7 P2_7 ;
+__sbit __at 0xA0 P2_0 ;
+__sbit __at 0xA1 P2_1 ;
+__sbit __at 0xA2 P2_2 ;
+__sbit __at 0xA3 P2_3 ;
+__sbit __at 0xA4 P2_4 ;
+__sbit __at 0xA5 P2_5 ;
+__sbit __at 0xA6 P2_6 ;
+__sbit __at 0xA7 P2_7 ;
/* IE 0xA8 */
-sbit at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
-sbit at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
-sbit at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
-sbit at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
-sbit at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
-sbit at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
-sbit at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
-sbit at 0xAE ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
-sbit at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
+__sbit __at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
+__sbit __at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
+__sbit __at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
+__sbit __at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
+__sbit __at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
+__sbit __at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
+__sbit __at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
+__sbit __at 0xAE ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
+__sbit __at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
/* IP 0xB8 */
-sbit at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
-sbit at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */
-sbit at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
-sbit at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */
-sbit at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */
-sbit at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
-sbit at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */
-sbit at 0xBE PSPI0 ; /* IP.6 - SPI0 PRIORITY */
+__sbit __at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
+__sbit __at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */
+__sbit __at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
+__sbit __at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */
+__sbit __at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */
+__sbit __at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
+__sbit __at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */
+__sbit __at 0xBE PSPI0 ; /* IP.6 - SPI0 PRIORITY */
/* SMB0CN 0xC0 */
-sbit at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
-sbit at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
-sbit at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
-sbit at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
-sbit at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
-sbit at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
-sbit at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
-sbit at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
+__sbit __at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
+__sbit __at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
+__sbit __at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
+__sbit __at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
+__sbit __at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
+__sbit __at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
+__sbit __at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
+__sbit __at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
/* TMR2CN 0xC8 */
-sbit at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
-sbit at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
-sbit at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
-sbit at 0xCD TF2CEN ; /* TMR2CN.5 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/
-sbit at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
-sbit at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
-sbit at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
-sbit at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
+__sbit __at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
+__sbit __at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
+__sbit __at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
+__sbit __at 0xCD TF2CEN ; /* TMR2CN.5 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/
+__sbit __at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
+__sbit __at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
+__sbit __at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
+__sbit __at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
/* PSW 0xD0 */
-sbit at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
-sbit at 0xD1 F1 ; /* PSW.1 - FLAG 1 */
-sbit at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */
-sbit at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
-sbit at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
-sbit at 0xD5 F0 ; /* PSW.5 - FLAG 0 */
-sbit at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
-sbit at 0xD7 CY ; /* PSW.7 - CARRY FLAG */
+__sbit __at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
+__sbit __at 0xD1 F1 ; /* PSW.1 - FLAG 1 */
+__sbit __at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */
+__sbit __at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
+__sbit __at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
+__sbit __at 0xD5 F0 ; /* PSW.5 - FLAG 0 */
+__sbit __at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
+__sbit __at 0xD7 CY ; /* PSW.7 - CARRY FLAG */
/* PCA0CN 0xD8 */
-sbit at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
-sbit at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
-sbit at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
-sbit at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
-sbit at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
+__sbit __at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
+__sbit __at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
+__sbit __at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
+__sbit __at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
+__sbit __at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
/* ADC0CN 0xE8 */
-sbit at 0xE8 AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
-sbit at 0xE9 AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
-sbit at 0xEA AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
-sbit at 0xEB AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
-sbit at 0xEC AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
-sbit at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
-sbit at 0xEE AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
-sbit at 0xEF AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
+__sbit __at 0xE8 AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
+__sbit __at 0xE9 AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
+__sbit __at 0xEA AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
+__sbit __at 0xEB AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
+__sbit __at 0xEC AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
+__sbit __at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
+__sbit __at 0xEE AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
+__sbit __at 0xEF AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
/* SPI0CN 0xF8 */
-sbit at 0xF8 SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
-sbit at 0xF9 TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
-sbit at 0xFA NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
-sbit at 0xFB NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
-sbit at 0xFC RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
-sbit at 0xFD MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
-sbit at 0xFE WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
-sbit at 0xFF SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
+__sbit __at 0xF8 SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
+__sbit __at 0xF9 TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
+__sbit __at 0xFA NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
+__sbit __at 0xFB NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
+__sbit __at 0xFC RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
+__sbit __at 0xFD MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
+__sbit __at 0xFE WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
+__sbit __at 0xFF SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
/* Predefined SFR Bit Masks */
/* BYTE Registers */
-sfr at 0x80 P0 ; /* PORT 0 */
-sfr at 0x81 SP ; /* STACK POINTER */
-sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
-sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
-sfr at 0x87 PCON ; /* POWER CONTROL */
-sfr at 0x88 TCON ; /* TIMER CONTROL */
-sfr at 0x89 TMOD ; /* TIMER MODE */
-sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
-sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
-sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
-sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
-sfr at 0x8E CKCON ; /* CLOCK CONTROL */
-sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
-sfr at 0x90 P1 ; /* PORT 1 */
-sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */
-sfr at 0x92 TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
-sfr at 0x93 TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */
-sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */
-sfr at 0x96 IDA0 ; /* CURRENT MODE DAC 0 */
-sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */
-sfr at 0x98 SCON0 ; /* SERIAL PORT CONTROL */
-sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */
-sfr at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */
-sfr at 0x9A ADC0DECL ; /* ADC DECIMATION LOW */
-sfr at 0x9B ADC0DECH ; /* ADC DECIMATION HIGH */
-sfr at 0x9C CPT0CN ; /* COMPARATOR 0 CONTROL */
-sfr at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
-sfr at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
-sfr at 0xA0 P2 ; /* PORT 2 */
-sfr at 0xA1 SPI0CFG ; /* SPI0 CONFIGURATION */
-sfr at 0xA2 SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
-sfr at 0xA3 SPI0DAT ; /* SPI0 DATA */
-sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
-sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
-sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
-sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
-sfr at 0xA9 CLKSEL ; /* SYSTEM CLOCK SELECT */
-sfr at 0xAA EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
-sfr at 0xAA _XPAGE ; /* XDATA/PDATA PAGE */
-sfr at 0xAB ADC0CGL ; /* ADC 0 GAIN CALIBRATION LOW */
-sfr at 0xAC ADC0CGM ; /* ADC 0 GAIN CALIBRATION MIDDLE */
-sfr at 0xAD ADC0CGH ; /* ADC 0 GAIN CALIBRATION HIGH */
-sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
-sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
-sfr at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
-sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
-sfr at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */
-sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
-sfr at 0xB9 IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */
-sfr at 0xBA ADC0COL ; /* ADC 0 OFFSET CALIBRATION LOW */
-sfr at 0xBB ADC0COM ; /* ADC 0 OFFSET CALIBRATION MIDDLE */
-sfr at 0xBC ADC0COH ; /* ADC 0 OFFSET CALIBRATION HIGH */
-sfr at 0xBD ADC0BUF ; /* ADC 0 BUFFER CONTROL */
-sfr at 0xBE CLKMUL ; /* CLOCK MULTIPLIER */
-sfr at 0xBF ADC0DAC ; /* ADC 0 OFFSET DAC */
-sfr at 0xC0 SMB0CN ; /* SMBUS CONTROL */
-sfr at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */
-sfr at 0xC2 SMB0DAT ; /* SMBUS DATA */
-sfr at 0xC3 ADC0L ; /* ADC 0 OUTPUT LOW BYTE */
-sfr at 0xC4 ADC0M ; /* ADC 0 OUTPUT MIDDLE BYTE */
-sfr at 0xC5 ADC0H ; /* ADC 0 OUTPUT HIGH BYTE */
-sfr at 0xC6 ADC0MUX ; /* ADC 0 MULTIPLEXER */
-sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */
-sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
-sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
-sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
-sfr at 0xD4 P0SKIP ; /* PORT 0 SKIP */
-sfr at 0xD5 P1SKIP ; /* PORT 1 SKIP */
-sfr at 0xD7 IDA1CN ; /* CURRENT MODE DAC 1 - CONTROL */
-sfr at 0xD8 PCA0CN ; /* PCA CONTROL */
-sfr at 0xD9 PCA0MD ; /* PCA MODE */
-sfr at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
-sfr at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
-sfr at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
-sfr at 0xDD IDA1 ; /* CURRENT MODE DAC 1 */
-sfr at 0xE0 ACC ; /* ACCUMULATOR */
-sfr at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
-sfr at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
-sfr at 0xE3 PFE0CN ; /* PREFETCH ENGINE CONTROL */
-sfr at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
-sfr at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
-sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
-sfr at 0xE8 ADC0STA ; /* ADC 0 STATUS */
-sfr at 0xE9 PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
-sfr at 0xEA PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
-sfr at 0xEB PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
-sfr at 0xEC PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
-sfr at 0xED PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
-sfr at 0xEE PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
-sfr at 0xEF RSTSRC ; /* RESET SOURCE */
-sfr at 0xF0 B ; /* B REGISTER */
-sfr at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
-sfr at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
-sfr at 0xF2 P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
-sfr at 0xF2 P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
-sfr at 0xF3 ADC0MD ; /* ADC 0 MODE */
-sfr at 0xF4 ADC0CN ; /* ADC 0 CONTROL */
-sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
-sfr at 0xF7 ADC0CLK ; /* ADC 0 CLOCK */
-sfr at 0xF8 SPI0CN ; /* SPI0 CONTROL */
-sfr at 0xF9 PCA0L ; /* PCA COUNTER LOW */
-sfr at 0xFA PCA0H ; /* PCA COUNTER HIGH */
-sfr at 0xFB ADC0CF ; /* ADC 0 CONFIGURATION */
-sfr at 0xFC ADC0FL ; /* ADC 0 FAST FILTER OUTPUT LOW */
-sfr at 0xFD ADC0FM ; /* ADC 0 FAST FILTER OUTPUT MIDDLE */
-sfr at 0xFE ADC0FH ; /* ADC 0 FAST FILTER OUTPUT HIGH */
-sfr at 0xFF VDM0CN ; /* VDD MONITOR CONTROL */
+__sfr __at 0x80 P0 ; /* PORT 0 */
+__sfr __at 0x81 SP ; /* STACK POINTER */
+__sfr __at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
+__sfr __at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
+__sfr __at 0x87 PCON ; /* POWER CONTROL */
+__sfr __at 0x88 TCON ; /* TIMER CONTROL */
+__sfr __at 0x89 TMOD ; /* TIMER MODE */
+__sfr __at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
+__sfr __at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
+__sfr __at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
+__sfr __at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
+__sfr __at 0x8E CKCON ; /* CLOCK CONTROL */
+__sfr __at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
+__sfr __at 0x90 P1 ; /* PORT 1 */
+__sfr __at 0x91 TMR3CN ; /* TIMER 3 CONTROL */
+__sfr __at 0x92 TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0x93 TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */
+__sfr __at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */
+__sfr __at 0x96 IDA0 ; /* CURRENT MODE DAC 0 */
+__sfr __at 0x98 SCON ; /* SERIAL PORT CONTROL */
+__sfr __at 0x98 SCON0 ; /* SERIAL PORT CONTROL */
+__sfr __at 0x99 SBUF ; /* SERIAL PORT BUFFER */
+__sfr __at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */
+__sfr __at 0x9A ADC0DECL ; /* ADC DECIMATION LOW */
+__sfr __at 0x9B ADC0DECH ; /* ADC DECIMATION HIGH */
+__sfr __at 0x9C CPT0CN ; /* COMPARATOR 0 CONTROL */
+__sfr __at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
+__sfr __at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
+__sfr __at 0xA0 P2 ; /* PORT 2 */
+__sfr __at 0xA1 SPI0CFG ; /* SPI0 CONFIGURATION */
+__sfr __at 0xA2 SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
+__sfr __at 0xA3 SPI0DAT ; /* SPI0 DATA */
+__sfr __at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
+__sfr __at 0xA8 IE ; /* INTERRUPT ENABLE */
+__sfr __at 0xA9 CLKSEL ; /* SYSTEM CLOCK SELECT */
+__sfr __at 0xAA EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
+__sfr __at 0xAA _XPAGE ; /* XDATA/PDATA PAGE */
+__sfr __at 0xAB ADC0CGL ; /* ADC 0 GAIN CALIBRATION LOW */
+__sfr __at 0xAC ADC0CGM ; /* ADC 0 GAIN CALIBRATION MIDDLE */
+__sfr __at 0xAD ADC0CGH ; /* ADC 0 GAIN CALIBRATION HIGH */
+__sfr __at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
+__sfr __at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
+__sfr __at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
+__sfr __at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
+__sfr __at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */
+__sfr __at 0xB8 IP ; /* INTERRUPT PRIORITY */
+__sfr __at 0xB9 IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */
+__sfr __at 0xBA ADC0COL ; /* ADC 0 OFFSET CALIBRATION LOW */
+__sfr __at 0xBB ADC0COM ; /* ADC 0 OFFSET CALIBRATION MIDDLE */
+__sfr __at 0xBC ADC0COH ; /* ADC 0 OFFSET CALIBRATION HIGH */
+__sfr __at 0xBD ADC0BUF ; /* ADC 0 BUFFER CONTROL */
+__sfr __at 0xBE CLKMUL ; /* CLOCK MULTIPLIER */
+__sfr __at 0xBF ADC0DAC ; /* ADC 0 OFFSET DAC */
+__sfr __at 0xC0 SMB0CN ; /* SMBUS CONTROL */
+__sfr __at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */
+__sfr __at 0xC2 SMB0DAT ; /* SMBUS DATA */
+__sfr __at 0xC3 ADC0L ; /* ADC 0 OUTPUT LOW BYTE */
+__sfr __at 0xC4 ADC0M ; /* ADC 0 OUTPUT MIDDLE BYTE */
+__sfr __at 0xC5 ADC0H ; /* ADC 0 OUTPUT HIGH BYTE */
+__sfr __at 0xC6 ADC0MUX ; /* ADC 0 MULTIPLEXER */
+__sfr __at 0xC8 T2CON ; /* TIMER 2 CONTROL */
+__sfr __at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
+__sfr __at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+__sfr __at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+__sfr __at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
+__sfr __at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
+__sfr __at 0xD0 PSW ; /* PROGRAM STATUS WORD */
+__sfr __at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
+__sfr __at 0xD4 P0SKIP ; /* PORT 0 SKIP */
+__sfr __at 0xD5 P1SKIP ; /* PORT 1 SKIP */
+__sfr __at 0xD7 IDA1CN ; /* CURRENT MODE DAC 1 - CONTROL */
+__sfr __at 0xD8 PCA0CN ; /* PCA CONTROL */
+__sfr __at 0xD9 PCA0MD ; /* PCA MODE */
+__sfr __at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
+__sfr __at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
+__sfr __at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
+__sfr __at 0xDD IDA1 ; /* CURRENT MODE DAC 1 */
+__sfr __at 0xE0 ACC ; /* ACCUMULATOR */
+__sfr __at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
+__sfr __at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
+__sfr __at 0xE3 PFE0CN ; /* PREFETCH ENGINE CONTROL */
+__sfr __at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
+__sfr __at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
+__sfr __at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
+__sfr __at 0xE8 ADC0STA ; /* ADC 0 STATUS */
+__sfr __at 0xE9 PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
+__sfr __at 0xEA PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
+__sfr __at 0xEB PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
+__sfr __at 0xEC PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
+__sfr __at 0xED PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
+__sfr __at 0xEE PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
+__sfr __at 0xEF RSTSRC ; /* RESET SOURCE */
+__sfr __at 0xF0 B ; /* B REGISTER */
+__sfr __at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
+__sfr __at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
+__sfr __at 0xF2 P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
+__sfr __at 0xF2 P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
+__sfr __at 0xF3 ADC0MD ; /* ADC 0 MODE */
+__sfr __at 0xF4 ADC0CN ; /* ADC 0 CONTROL */
+__sfr __at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
+__sfr __at 0xF7 ADC0CLK ; /* ADC 0 CLOCK */
+__sfr __at 0xF8 SPI0CN ; /* SPI0 CONTROL */
+__sfr __at 0xF9 PCA0L ; /* PCA COUNTER LOW */
+__sfr __at 0xFA PCA0H ; /* PCA COUNTER HIGH */
+__sfr __at 0xFB ADC0CF ; /* ADC 0 CONFIGURATION */
+__sfr __at 0xFC ADC0FL ; /* ADC 0 FAST FILTER OUTPUT LOW */
+__sfr __at 0xFD ADC0FM ; /* ADC 0 FAST FILTER OUTPUT MIDDLE */
+__sfr __at 0xFE ADC0FH ; /* ADC 0 FAST FILTER OUTPUT HIGH */
+__sfr __at 0xFF VDM0CN ; /* VDD MONITOR CONTROL */
/* BIT Registers */
/* P0 0x80 */
-sbit at 0x80 P0_0 ;
-sbit at 0x81 P0_1 ;
-sbit at 0x82 P0_2 ;
-sbit at 0x83 P0_3 ;
-sbit at 0x84 P0_4 ;
-sbit at 0x85 P0_5 ;
-sbit at 0x86 P0_6 ;
-sbit at 0x87 P0_7 ;
+__sbit __at 0x80 P0_0 ;
+__sbit __at 0x81 P0_1 ;
+__sbit __at 0x82 P0_2 ;
+__sbit __at 0x83 P0_3 ;
+__sbit __at 0x84 P0_4 ;
+__sbit __at 0x85 P0_5 ;
+__sbit __at 0x86 P0_6 ;
+__sbit __at 0x87 P0_7 ;
/* TCON 0x88 */
-sbit at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
-sbit at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
-sbit at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
-sbit at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
-sbit at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
-sbit at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
-sbit at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
-sbit at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
+__sbit __at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
+__sbit __at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
+__sbit __at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
+__sbit __at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
+__sbit __at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
+__sbit __at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
+__sbit __at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
+__sbit __at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
/* P1 0x90 */
-sbit at 0x90 P1_0 ;
-sbit at 0x91 P1_1 ;
-sbit at 0x92 P1_2 ;
-sbit at 0x93 P1_3 ;
-sbit at 0x94 P1_4 ;
-sbit at 0x95 P1_5 ;
-sbit at 0x96 P1_6 ;
-sbit at 0x97 P1_7 ;
+__sbit __at 0x90 P1_0 ;
+__sbit __at 0x91 P1_1 ;
+__sbit __at 0x92 P1_2 ;
+__sbit __at 0x93 P1_3 ;
+__sbit __at 0x94 P1_4 ;
+__sbit __at 0x95 P1_5 ;
+__sbit __at 0x96 P1_6 ;
+__sbit __at 0x97 P1_7 ;
/* SCON 0x98 */
-sbit at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
-sbit at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
-sbit at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
-sbit at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
-sbit at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */
-sbit at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */
-sbit at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
-sbit at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
-sbit at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */
-sbit at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */
-sbit at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
-sbit at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
-sbit at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
-sbit at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
+__sbit __at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
+__sbit __at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
+__sbit __at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
+__sbit __at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
+__sbit __at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */
+__sbit __at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */
+__sbit __at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
+__sbit __at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
+__sbit __at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */
+__sbit __at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */
+__sbit __at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
+__sbit __at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
+__sbit __at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
+__sbit __at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
/* P2 0xA0 */
-sbit at 0xA0 P2_0 ;
-sbit at 0xA1 P2_1 ;
-sbit at 0xA2 P2_2 ;
-sbit at 0xA3 P2_3 ;
-sbit at 0xA4 P2_4 ;
-sbit at 0xA5 P2_5 ;
-sbit at 0xA6 P2_6 ;
-sbit at 0xA7 P2_7 ;
+__sbit __at 0xA0 P2_0 ;
+__sbit __at 0xA1 P2_1 ;
+__sbit __at 0xA2 P2_2 ;
+__sbit __at 0xA3 P2_3 ;
+__sbit __at 0xA4 P2_4 ;
+__sbit __at 0xA5 P2_5 ;
+__sbit __at 0xA6 P2_6 ;
+__sbit __at 0xA7 P2_7 ;
/* IE 0xA8 */
-sbit at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
-sbit at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
-sbit at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
-sbit at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
-sbit at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
-sbit at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
-sbit at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
-sbit at 0xAE ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
-sbit at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
+__sbit __at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
+__sbit __at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
+__sbit __at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
+__sbit __at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
+__sbit __at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
+__sbit __at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
+__sbit __at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
+__sbit __at 0xAE ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
+__sbit __at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
/* IP 0xB8 */
-sbit at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
-sbit at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */
-sbit at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
-sbit at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */
-sbit at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */
-sbit at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
-sbit at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */
-sbit at 0xBE PSPI0 ; /* IP.6 - SPI0 PRIORITY */
+__sbit __at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
+__sbit __at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */
+__sbit __at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
+__sbit __at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */
+__sbit __at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */
+__sbit __at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
+__sbit __at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */
+__sbit __at 0xBE PSPI0 ; /* IP.6 - SPI0 PRIORITY */
/* SMB0CN 0xC0 */
-sbit at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
-sbit at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
-sbit at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
-sbit at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
-sbit at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
-sbit at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
-sbit at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
-sbit at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
+__sbit __at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
+__sbit __at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
+__sbit __at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
+__sbit __at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
+__sbit __at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
+__sbit __at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
+__sbit __at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
+__sbit __at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
/* TMR2CN 0xC8 */
-sbit at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
-sbit at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
-sbit at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
-sbit at 0xCD TF2CEN ; /* TMR2CN.5 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/
-sbit at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
-sbit at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
-sbit at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
-sbit at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
+__sbit __at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
+__sbit __at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
+__sbit __at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
+__sbit __at 0xCD TF2CEN ; /* TMR2CN.5 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/
+__sbit __at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
+__sbit __at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
+__sbit __at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
+__sbit __at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
/* PSW 0xD0 */
-sbit at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
-sbit at 0xD1 F1 ; /* PSW.1 - FLAG 1 */
-sbit at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */
-sbit at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
-sbit at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
-sbit at 0xD5 F0 ; /* PSW.5 - FLAG 0 */
-sbit at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
-sbit at 0xD7 CY ; /* PSW.7 - CARRY FLAG */
+__sbit __at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
+__sbit __at 0xD1 F1 ; /* PSW.1 - FLAG 1 */
+__sbit __at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */
+__sbit __at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
+__sbit __at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
+__sbit __at 0xD5 F0 ; /* PSW.5 - FLAG 0 */
+__sbit __at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
+__sbit __at 0xD7 CY ; /* PSW.7 - CARRY FLAG */
/* PCA0CN 0xD8 */
-sbit at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
-sbit at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
-sbit at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
-sbit at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
-sbit at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
+__sbit __at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
+__sbit __at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
+__sbit __at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
+__sbit __at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
+__sbit __at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
/* ADC0STA 0xE8 */
-sbit at 0xE8 AD0OVR ; /* ADC0CN.0 - ADC 0 OVERRUN FLAG */
-sbit at 0xE9 AD0ERR ; /* ADC0CN.1 - ADC 0 ERROR FLAG */
-sbit at 0xEA AD0CALC ; /* ADC0CN.2 - ADC 0 CALIBRATION COMPLETE FLAG */
-sbit at 0xEB AD0FFC ; /* ADC0CN.3 - ADC 0 FAST FILTER CLIP FLAG */
-sbit at 0xEC AD0S3C ; /* ADC0CN.4 - ADC 0 SINC3 FILTER CLIP FLAG */
-sbit at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
-sbit at 0xEE AD0CBSY ; /* ADC0CN.6 - ADC 0 CALIBRATION IN PROGRESS FLAG */
-sbit at 0xEF AD0BUSY ; /* ADC0CN.7 - ADC 0 CONVERSION IN PROGRESS FLAG */
+__sbit __at 0xE8 AD0OVR ; /* ADC0CN.0 - ADC 0 OVERRUN FLAG */
+__sbit __at 0xE9 AD0ERR ; /* ADC0CN.1 - ADC 0 ERROR FLAG */
+__sbit __at 0xEA AD0CALC ; /* ADC0CN.2 - ADC 0 CALIBRATION COMPLETE FLAG */
+__sbit __at 0xEB AD0FFC ; /* ADC0CN.3 - ADC 0 FAST FILTER CLIP FLAG */
+__sbit __at 0xEC AD0S3C ; /* ADC0CN.4 - ADC 0 SINC3 FILTER CLIP FLAG */
+__sbit __at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
+__sbit __at 0xEE AD0CBSY ; /* ADC0CN.6 - ADC 0 CALIBRATION IN PROGRESS FLAG */
+__sbit __at 0xEF AD0BUSY ; /* ADC0CN.7 - ADC 0 CONVERSION IN PROGRESS FLAG */
/* SPI0CN 0xF8 */
-sbit at 0xF8 SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
-sbit at 0xF9 TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
-sbit at 0xFA NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
-sbit at 0xFB NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
-sbit at 0xFC RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
-sbit at 0xFD MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
-sbit at 0xFE WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
-sbit at 0xFF SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
+__sbit __at 0xF8 SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
+__sbit __at 0xF9 TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
+__sbit __at 0xFA NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
+__sbit __at 0xFB NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
+__sbit __at 0xFC RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
+__sbit __at 0xFD MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
+__sbit __at 0xFE WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
+__sbit __at 0xFF SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
/* Predefined SFR Bit Masks */
/* Special Function Registers */
-sfr at 0x80 P0 ; // Port 0
-sfr at 0x81 SP ; // Stack Pointer
-sfr at 0x82 DPL ; // Data Pointer Low
-sfr at 0x83 DPH ; // Data Pointer High
-sfr at 0x84 P0M1 ; // Port 0 output mode 1
-sfr at 0x85 P0M2 ; // Port 0 output mode 2
-sfr at 0x86 KBI ; // Keyboard interrupt
-sfr at 0x87 PCON ; // Power Control
-sfr at 0x88 TCON ; // Timer Control
-sfr at 0x89 TMOD ; // Timer Mode
-sfr at 0x8A TL0 ; // Timer Low 0
-sfr at 0x8B TL1 ; // Timer Low 1
-sfr at 0x8C TH0 ; // Timer High 0
-sfr at 0x8D TH1 ; // Timer High 1
-
-sfr at 0x90 P1 ; // Port 1
-sfr at 0x91 P1M1 ; // Port 1 output mode 1
-sfr at 0x92 P1M2 ; // Port 1 output mode 2
-sfr at 0x95 DIVM ; // CPU clock divide by N control
-sfr at 0x98 SCON ; // Serial Control
-sfr at 0x99 SBUF ; // Serial Data Buffer
-
-sfr at 0xA0 P2 ; // Port 2
-sfr at 0xA2 AUXR1 ; // Auxilliary 1 (not available on 80C51FA/87C51Fx)
-sfr at 0xA4 P2M1 ; // Port 2 output mode 1
-sfr at 0xA5 P2M2 ; // Port 2 output mode 2
-sfr at 0xA6 WDRST ; // Watchdog reset register
-sfr at 0xA7 WDCON ; // Watchdog control register
-sfr at 0xA8 IEN0 ; // Interrupt Enable 0
-sfr at 0xA9 SADDR ; // Serial slave Address
-sfr at 0xAC CMP1 ; // Comparator 1 control register
-sfr at 0xAD CMP2 ; // Comparator 2 control register
-
-sfr at 0xB7 IP0H ; // Interrupt Priority 0 High
-sfr at 0xB8 IP0 ; // Interrupt Priority 0
-sfr at 0xB9 SADEN ; // Serial slave Address Mask
-
-sfr at 0xC8 I2CFG ; // I2C configuration register
-
-sfr at 0xD0 PSW ; // Program Status Word
-sfr at 0xD8 I2CON ; // I2C control register
-sfr at 0xD9 I2DAT ; // I2C data register
-
-sfr at 0xE0 ACC ; // Accumulator
-sfr at 0xE8 IEN1 ; // Interrupt enable 1
-
-sfr at 0xF0 B ; // B Register
-sfr at 0xF6 PT0AD ; // Port 0 digital input disable
-sfr at 0xF7 IP1H ; // Interrupt Priority 1 High
-sfr at 0xF8 IP1 ; // Interrupt Priority 1
+__sfr __at 0x80 P0 ; // Port 0
+__sfr __at 0x81 SP ; // Stack Pointer
+__sfr __at 0x82 DPL ; // Data Pointer Low
+__sfr __at 0x83 DPH ; // Data Pointer High
+__sfr __at 0x84 P0M1 ; // Port 0 output mode 1
+__sfr __at 0x85 P0M2 ; // Port 0 output mode 2
+__sfr __at 0x86 KBI ; // Keyboard interrupt
+__sfr __at 0x87 PCON ; // Power Control
+__sfr __at 0x88 TCON ; // Timer Control
+__sfr __at 0x89 TMOD ; // Timer Mode
+__sfr __at 0x8A TL0 ; // Timer Low 0
+__sfr __at 0x8B TL1 ; // Timer Low 1
+__sfr __at 0x8C TH0 ; // Timer High 0
+__sfr __at 0x8D TH1 ; // Timer High 1
+
+__sfr __at 0x90 P1 ; // Port 1
+__sfr __at 0x91 P1M1 ; // Port 1 output mode 1
+__sfr __at 0x92 P1M2 ; // Port 1 output mode 2
+__sfr __at 0x95 DIVM ; // CPU clock divide by N control
+__sfr __at 0x98 SCON ; // Serial Control
+__sfr __at 0x99 SBUF ; // Serial Data Buffer
+
+__sfr __at 0xA0 P2 ; // Port 2
+__sfr __at 0xA2 AUXR1 ; // Auxilliary 1 (not available on 80C51FA/87C51Fx)
+__sfr __at 0xA4 P2M1 ; // Port 2 output mode 1
+__sfr __at 0xA5 P2M2 ; // Port 2 output mode 2
+__sfr __at 0xA6 WDRST ; // Watchdog reset register
+__sfr __at 0xA7 WDCON ; // Watchdog control register
+__sfr __at 0xA8 IEN0 ; // Interrupt Enable 0
+__sfr __at 0xA9 SADDR ; // Serial slave Address
+__sfr __at 0xAC CMP1 ; // Comparator 1 control register
+__sfr __at 0xAD CMP2 ; // Comparator 2 control register
+
+__sfr __at 0xB7 IP0H ; // Interrupt Priority 0 High
+__sfr __at 0xB8 IP0 ; // Interrupt Priority 0
+__sfr __at 0xB9 SADEN ; // Serial slave Address Mask
+
+__sfr __at 0xC8 I2CFG ; // I2C configuration register
+
+__sfr __at 0xD0 PSW ; // Program Status Word
+__sfr __at 0xD8 I2CON ; // I2C control register
+__sfr __at 0xD9 I2DAT ; // I2C data register
+
+__sfr __at 0xE0 ACC ; // Accumulator
+__sfr __at 0xE8 IEN1 ; // Interrupt enable 1
+
+__sfr __at 0xF0 B ; // B Register
+__sfr __at 0xF6 PT0AD ; // Port 0 digital input disable
+__sfr __at 0xF7 IP1H ; // Interrupt Priority 1 High
+__sfr __at 0xF8 IP1 ; // Interrupt Priority 1
/* Bit Addressable Registers */
/* P0 */
-sbit at 0x80 P0_0 ; // Also CMP2
-sbit at 0x81 P0_1 ; // Also CIN2B
-sbit at 0x82 P0_2 ; // Also CIN2A
-sbit at 0x83 P0_3 ; // Also CIN1B
-sbit at 0x84 P0_4 ; // Also CIN1A
-sbit at 0x85 P0_5 ; // Also CMPREF
-sbit at 0x86 P0_6 ; // Also CMP1
-sbit at 0x87 P0_7 ; // Also T1
+__sbit __at 0x80 P0_0 ; // Also CMP2
+__sbit __at 0x81 P0_1 ; // Also CIN2B
+__sbit __at 0x82 P0_2 ; // Also CIN2A
+__sbit __at 0x83 P0_3 ; // Also CIN1B
+__sbit __at 0x84 P0_4 ; // Also CIN1A
+__sbit __at 0x85 P0_5 ; // Also CMPREF
+__sbit __at 0x86 P0_6 ; // Also CMP1
+__sbit __at 0x87 P0_7 ; // Also T1
/* TCON */
-sbit at 0x88 IT0 ; // External Interrupt 0 Type
-sbit at 0x89 IE0 ; // External Interrupt 0 Edge Flag
-sbit at 0x8A IT1 ; // External Interrupt 1 Type
-sbit at 0x8B IE1 ; // External Interrupt 1 Edge Flag
-sbit at 0x8C TR0 ; // Timer 0 Run Control
-sbit at 0x8D TF0 ; // Timer 0 Overflow Flag
-sbit at 0x8E TR1 ; // Timer 1 Run Control
-sbit at 0x8F TF1 ; // Timer 1 Overflow Flag
+__sbit __at 0x88 IT0 ; // External Interrupt 0 Type
+__sbit __at 0x89 IE0 ; // External Interrupt 0 Edge Flag
+__sbit __at 0x8A IT1 ; // External Interrupt 1 Type
+__sbit __at 0x8B IE1 ; // External Interrupt 1 Edge Flag
+__sbit __at 0x8C TR0 ; // Timer 0 Run Control
+__sbit __at 0x8D TF0 ; // Timer 0 Overflow Flag
+__sbit __at 0x8E TR1 ; // Timer 1 Run Control
+__sbit __at 0x8F TF1 ; // Timer 1 Overflow Flag
/* P1 */
-sbit at 0x90 P1_0 ; // Also TxD
-sbit at 0x91 P1_1 ; // Also RxD
-sbit at 0x92 P1_2 ; // Also T0
-sbit at 0x93 P1_3 ; // Also INT0
-sbit at 0x94 P1_4 ; // Also INT1
-sbit at 0x95 P1_5 ; // Also RST
-sbit at 0x96 P1_6 ;
-sbit at 0x97 P1_7 ;
+__sbit __at 0x90 P1_0 ; // Also TxD
+__sbit __at 0x91 P1_1 ; // Also RxD
+__sbit __at 0x92 P1_2 ; // Also T0
+__sbit __at 0x93 P1_3 ; // Also INT0
+__sbit __at 0x94 P1_4 ; // Also INT1
+__sbit __at 0x95 P1_5 ; // Also RST
+__sbit __at 0x96 P1_6 ;
+__sbit __at 0x97 P1_7 ;
/* SCON */
-sbit at 0x98 RI ; // Receive Interrupt Flag
-sbit at 0x99 TI ; // Transmit Interrupt Flag
-sbit at 0x9A RB8 ; // Receive Bit 8
-sbit at 0x9B TB8 ; // Transmit Bit 8
-sbit at 0x9C REN ; // Receiver Enable
-sbit at 0x9D SM2 ; // Serial Mode Control Bit 2
-sbit at 0x9E SM1 ; // Serial Mode Control Bit 1
-sbit at 0x9F SM0 ; // Serial Mode Control Bit 0
+__sbit __at 0x98 RI ; // Receive Interrupt Flag
+__sbit __at 0x99 TI ; // Transmit Interrupt Flag
+__sbit __at 0x9A RB8 ; // Receive Bit 8
+__sbit __at 0x9B TB8 ; // Transmit Bit 8
+__sbit __at 0x9C REN ; // Receiver Enable
+__sbit __at 0x9D SM2 ; // Serial Mode Control Bit 2
+__sbit __at 0x9E SM1 ; // Serial Mode Control Bit 1
+__sbit __at 0x9F SM0 ; // Serial Mode Control Bit 0
/* P2 */
-sbit at 0xA0 P2_0 ; // Also X2
-sbit at 0xA1 P2_1 ; // Also X1
+__sbit __at 0xA0 P2_0 ; // Also X2
+__sbit __at 0xA1 P2_1 ; // Also X1
/* IEN0 */
-sbit at 0xA8 EX0 ; // External Interrupt 0 Enable
-sbit at 0xA9 ET0 ; // Timer 0 Interrupt Enable
-sbit at 0xAA EX1 ; // External Interrupt 1 Enable
-sbit at 0xAB ET1 ; // Timer 1 Interrupt Enable
-sbit at 0xAC ES ; // Serial Port Interrupt Enable
-sbit at 0xAD EBO ; // Brownout Interrupt Enable
-sbit at 0xAE EWD ; // Watchdog Interrupt Enable
-sbit at 0xAF EA ; // Global Interrupt Enable
+__sbit __at 0xA8 EX0 ; // External Interrupt 0 Enable
+__sbit __at 0xA9 ET0 ; // Timer 0 Interrupt Enable
+__sbit __at 0xAA EX1 ; // External Interrupt 1 Enable
+__sbit __at 0xAB ET1 ; // Timer 1 Interrupt Enable
+__sbit __at 0xAC ES ; // Serial Port Interrupt Enable
+__sbit __at 0xAD EBO ; // Brownout Interrupt Enable
+__sbit __at 0xAE EWD ; // Watchdog Interrupt Enable
+__sbit __at 0xAF EA ; // Global Interrupt Enable
/* IP0 */
-sbit at 0xB8 PX0 ; // External Interrupt 0 Priority
-sbit at 0xB9 PT0 ; // Timer 0 Interrupt Priority
-sbit at 0xBA PX1 ; // External Interrupt 1 Priority
-sbit at 0xBB PT1 ; // Timer 1 Interrupt Priority
-sbit at 0xBC PS ; // Serial Port Interrupt Priority
-sbit at 0xBD PB0 ; // Brownout Interrupt Priority
-sbit at 0xBE PWD ; // Watchdog Interrupt Priority
+__sbit __at 0xB8 PX0 ; // External Interrupt 0 Priority
+__sbit __at 0xB9 PT0 ; // Timer 0 Interrupt Priority
+__sbit __at 0xBA PX1 ; // External Interrupt 1 Priority
+__sbit __at 0xBB PT1 ; // Timer 1 Interrupt Priority
+__sbit __at 0xBC PS ; // Serial Port Interrupt Priority
+__sbit __at 0xBD PB0 ; // Brownout Interrupt Priority
+__sbit __at 0xBE PWD ; // Watchdog Interrupt Priority
/* I2CFG */
-sbit at 0xC8 CT0 ; // Clock Time Select 0
-sbit at 0xC9 CT1 ; // Clock Time Select 1
-sbit at 0xCC TIRUN ; // Timer I Run Enable
-sbit at 0xCD CLRTI ; // Clear Timer I
-sbit at 0xCE MASTRQ; // Master Request
-sbit at 0xCF SLAVEN; // Slave Enable
+__sbit __at 0xC8 CT0 ; // Clock Time Select 0
+__sbit __at 0xC9 CT1 ; // Clock Time Select 1
+__sbit __at 0xCC TIRUN ; // Timer I Run Enable
+__sbit __at 0xCD CLRTI ; // Clear Timer I
+__sbit __at 0xCE MASTRQ; // Master Request
+__sbit __at 0xCF SLAVEN; // Slave Enable
/* PSW */
-sbit at 0xD0 P ; // Accumulator Parity Flag
-sbit at 0xD1 F1 ; // Flag 1
-sbit at 0xD2 OV ; // Overflow Flag
-sbit at 0xD3 RS0 ; // Register Bank Select 0
-sbit at 0xD4 RS1 ; // Register Bank Select 1
-sbit at 0xD5 F0 ; // Flag 0
-sbit at 0xD6 AC ; // Auxiliary Carry Flag
-sbit at 0xD7 CY ; // Carry Flag
+__sbit __at 0xD0 P ; // Accumulator Parity Flag
+__sbit __at 0xD1 F1 ; // Flag 1
+__sbit __at 0xD2 OV ; // Overflow Flag
+__sbit __at 0xD3 RS0 ; // Register Bank Select 0
+__sbit __at 0xD4 RS1 ; // Register Bank Select 1
+__sbit __at 0xD5 F0 ; // Flag 0
+__sbit __at 0xD6 AC ; // Auxiliary Carry Flag
+__sbit __at 0xD7 CY ; // Carry Flag
/* I2CON */
-sbit at 0xD8 XSTP ;
-sbit at 0xD9 MASTER;// Master Status
-sbit at 0xDA STP ; // Stop Detect Flag
-sbit at 0xDB STR ; // Start Detect Flag
-sbit at 0xDC ARL ; // Arbitration Loss Flag
-sbit at 0xDD DRDY ; // Data Ready Flag
-sbit at 0xDE ATN ; // Attention: I2C Interrupt Flag
-sbit at 0xDF RDAT ; // I2C Read Data
+__sbit __at 0xD8 XSTP ;
+__sbit __at 0xD9 MASTER;// Master Status
+__sbit __at 0xDA STP ; // Stop Detect Flag
+__sbit __at 0xDB STR ; // Start Detect Flag
+__sbit __at 0xDC ARL ; // Arbitration Loss Flag
+__sbit __at 0xDD DRDY ; // Data Ready Flag
+__sbit __at 0xDE ATN ; // Attention: I2C Interrupt Flag
+__sbit __at 0xDF RDAT ; // I2C Read Data
/* ACC */
-sbit at 0xE0 ACC_0;
-sbit at 0xE1 ACC_1;
-sbit at 0xE2 ACC_2;
-sbit at 0xE3 ACC_3;
-sbit at 0xE4 ACC_4;
-sbit at 0xE5 ACC_5;
-sbit at 0xE6 ACC_6;
-sbit at 0xE7 ACC_7;
+__sbit __at 0xE0 ACC_0;
+__sbit __at 0xE1 ACC_1;
+__sbit __at 0xE2 ACC_2;
+__sbit __at 0xE3 ACC_3;
+__sbit __at 0xE4 ACC_4;
+__sbit __at 0xE5 ACC_5;
+__sbit __at 0xE6 ACC_6;
+__sbit __at 0xE7 ACC_7;
/* IEN1 */
-sbit at 0xE8 EI2 ; // I2C Interrupt Enable
-sbit at 0xE9 EKB ; // Keyboard Interrupt Enable
-sbit at 0xEA EC2 ; // Comparator 2 Interrupt Enable
-sbit at 0xED EC1 ; // Comparator 1 Interrupt Enable
-sbit at 0xEF ETI ; // Timer I Interrupt Enable
+__sbit __at 0xE8 EI2 ; // I2C Interrupt Enable
+__sbit __at 0xE9 EKB ; // Keyboard Interrupt Enable
+__sbit __at 0xEA EC2 ; // Comparator 2 Interrupt Enable
+__sbit __at 0xED EC1 ; // Comparator 1 Interrupt Enable
+__sbit __at 0xEF ETI ; // Timer I Interrupt Enable
/* B */
-sbit at 0xF0 B_0;
-sbit at 0xF1 B_1;
-sbit at 0xF2 B_2;
-sbit at 0xF3 B_3;
-sbit at 0xF4 B_4;
-sbit at 0xF5 B_5;
-sbit at 0xF6 B_6;
-sbit at 0xF7 B_7;
+__sbit __at 0xF0 B_0;
+__sbit __at 0xF1 B_1;
+__sbit __at 0xF2 B_2;
+__sbit __at 0xF3 B_3;
+__sbit __at 0xF4 B_4;
+__sbit __at 0xF5 B_5;
+__sbit __at 0xF6 B_6;
+__sbit __at 0xF7 B_7;
/* IP1 */
-sbit at 0xF8 PI2; // I2C Interrupt Priority
-sbit at 0xF9 PKB; // Keyboard Interrupt Priority
-sbit at 0xFA PC2; // Comparator 2 Interrupt Priority
-sbit at 0xFD PC1; // Comparator 1 Interrupt Priority
-sbit at 0xFF PTI; // Timer I Interrupt Priority
+__sbit __at 0xF8 PI2; // I2C Interrupt Priority
+__sbit __at 0xF9 PKB; // Keyboard Interrupt Priority
+__sbit __at 0xFA PC2; // Comparator 2 Interrupt Priority
+__sbit __at 0xFD PC1; // Comparator 1 Interrupt Priority
+__sbit __at 0xFF PTI; // Timer I Interrupt Priority
/* Bitmasks for SFRs */
unsigned char dummy;
} *can_msgp;
-xdata at CAN_CTRL struct
+__xdata __at CAN_CTRL struct
{
unsigned char cr;
unsigned char sr;
/* Byte registers in numerical order */
-sfr at 0x80 P0;
-sfr at 0x81 SP;
-sfr at 0x82 DPL;
-sfr at 0x83 DPH;
-sfr at 0x86 WDTREL;
-sfr at 0x87 PCON;
-sfr at 0x88 TCON;
-sfr at 0x88 PCON1;
-sfr at 0x89 TMOD;
-sfr at 0x8A TL0;
-sfr at 0x8B TL1;
-sfr at 0x8C TH0;
-sfr at 0x8D TH1;
-sfr at 0x90 P1;
-sfr at 0x91 XPAGE;
-sfr at 0x92 DPSEL;
-sfr at 0x93 SSCCON;
-sfr at 0x94 STB;
-sfr at 0x95 SRB;
-sfr at 0x96 SSCMOD;
-sfr at 0x98 SCON;
-sfr at 0x99 SBUF;
-sfr at 0x9A IEN2;
-sfr at 0xA0 P2;
-sfr at 0xA8 IEN0;
-sfr at 0xA9 IP0;
-sfr at 0xAA SRELL;
-sfr at 0xAB SCF;
-sfr at 0xAC SCIEN;
-sfr at 0xB0 P3;
-sfr at 0xB1 SYSCON;
-sfr at 0xB8 IEN1;
-sfr at 0xB9 IP1;
-sfr at 0xBA SRELH;
-sfr at 0xC0 IRCON;
-sfr at 0xC1 CCEN;
-sfr at 0xC2 CCL1;
-sfr at 0xC3 CCH1;
-sfr at 0xC4 CCL2;
-sfr at 0xC5 CCH2;
-sfr at 0xC6 CCL3;
-sfr at 0xC7 CCH3;
-sfr at 0xC8 T2CON;
-sfr at 0xCA CRCL;
-sfr at 0xCB CRCH;
-sfr at 0xCC TL2;
-sfr at 0xCD TH2;
-sfr at 0xD0 PSW;
-sfr at 0xD8 ADCON0;
-sfr at 0xD9 ADDATH;
-sfr at 0xDA ADDATL;
-sfr at 0xDB P6;
-sfr at 0xDC ADCON1;
-sfr at 0xE0 ACC;
-sfr at 0xE8 P4;
-sfr at 0xF0 B;
-sfr at 0xF8 P5;
-sfr at 0xF8 DIR5;
-sfr at 0xFA P7;
+__sfr __at 0x80 P0;
+__sfr __at 0x81 SP;
+__sfr __at 0x82 DPL;
+__sfr __at 0x83 DPH;
+__sfr __at 0x86 WDTREL;
+__sfr __at 0x87 PCON;
+__sfr __at 0x88 TCON;
+__sfr __at 0x88 PCON1;
+__sfr __at 0x89 TMOD;
+__sfr __at 0x8A TL0;
+__sfr __at 0x8B TL1;
+__sfr __at 0x8C TH0;
+__sfr __at 0x8D TH1;
+__sfr __at 0x90 P1;
+__sfr __at 0x91 XPAGE;
+__sfr __at 0x92 DPSEL;
+__sfr __at 0x93 SSCCON;
+__sfr __at 0x94 STB;
+__sfr __at 0x95 SRB;
+__sfr __at 0x96 SSCMOD;
+__sfr __at 0x98 SCON;
+__sfr __at 0x99 SBUF;
+__sfr __at 0x9A IEN2;
+__sfr __at 0xA0 P2;
+__sfr __at 0xA8 IEN0;
+__sfr __at 0xA9 IP0;
+__sfr __at 0xAA SRELL;
+__sfr __at 0xAB SCF;
+__sfr __at 0xAC SCIEN;
+__sfr __at 0xB0 P3;
+__sfr __at 0xB1 SYSCON;
+__sfr __at 0xB8 IEN1;
+__sfr __at 0xB9 IP1;
+__sfr __at 0xBA SRELH;
+__sfr __at 0xC0 IRCON;
+__sfr __at 0xC1 CCEN;
+__sfr __at 0xC2 CCL1;
+__sfr __at 0xC3 CCH1;
+__sfr __at 0xC4 CCL2;
+__sfr __at 0xC5 CCH2;
+__sfr __at 0xC6 CCL3;
+__sfr __at 0xC7 CCH3;
+__sfr __at 0xC8 T2CON;
+__sfr __at 0xCA CRCL;
+__sfr __at 0xCB CRCH;
+__sfr __at 0xCC TL2;
+__sfr __at 0xCD TH2;
+__sfr __at 0xD0 PSW;
+__sfr __at 0xD8 ADCON0;
+__sfr __at 0xD9 ADDATH;
+__sfr __at 0xDA ADDATL;
+__sfr __at 0xDB P6;
+__sfr __at 0xDC ADCON1;
+__sfr __at 0xE0 ACC;
+__sfr __at 0xE8 P4;
+__sfr __at 0xF0 B;
+__sfr __at 0xF8 P5;
+__sfr __at 0xF8 DIR5;
+__sfr __at 0xFA P7;
/* defining bits in SFR P0 */
-sbit at 0x80 P0_0;
-sbit at 0x81 P0_1;
-sbit at 0x82 P0_2;
-sbit at 0x83 P0_3;
-sbit at 0x84 P0_4;
-sbit at 0x85 P0_5;
-sbit at 0x86 P0_6;
-sbit at 0x87 P0_7;
+__sbit __at 0x80 P0_0;
+__sbit __at 0x81 P0_1;
+__sbit __at 0x82 P0_2;
+__sbit __at 0x83 P0_3;
+__sbit __at 0x84 P0_4;
+__sbit __at 0x85 P0_5;
+__sbit __at 0x86 P0_6;
+__sbit __at 0x87 P0_7;
/* defining bits in SFR PCON1 */
-sbit at 0x88 IT0;
-sbit at 0x89 IE0;
-sbit at 0x8a IT1;
-sbit at 0x8b IE1;
-sbit at 0x8c TR0;
-sbit at 0x8d TF0;
-sbit at 0x8e TR1;
-sbit at 0x8f TF1;
-sbit at 0x8f EWPD;
+__sbit __at 0x88 IT0;
+__sbit __at 0x89 IE0;
+__sbit __at 0x8a IT1;
+__sbit __at 0x8b IE1;
+__sbit __at 0x8c TR0;
+__sbit __at 0x8d TF0;
+__sbit __at 0x8e TR1;
+__sbit __at 0x8f TF1;
+__sbit __at 0x8f EWPD;
/* defining bits in SFR P1 */
-sbit at 0x90 P1_0;
-sbit at 0x90 INT3;
-sbit at 0x91 P1_1;
-sbit at 0x91 INT4;
-sbit at 0x92 P1_2;
-sbit at 0x92 INT5;
-sbit at 0x93 P1_3;
-sbit at 0x93 INT6;
-sbit at 0x94 P1_4;
-sbit at 0x94 INT2;
-sbit at 0x95 P1_5;
-sbit at 0x95 T2EX;
-sbit at 0x96 P1_6;
-sbit at 0x96 CLKOUT;
-sbit at 0x97 P1_7;
-sbit at 0x97 T2;
+__sbit __at 0x90 P1_0;
+__sbit __at 0x90 INT3;
+__sbit __at 0x91 P1_1;
+__sbit __at 0x91 INT4;
+__sbit __at 0x92 P1_2;
+__sbit __at 0x92 INT5;
+__sbit __at 0x93 P1_3;
+__sbit __at 0x93 INT6;
+__sbit __at 0x94 P1_4;
+__sbit __at 0x94 INT2;
+__sbit __at 0x95 P1_5;
+__sbit __at 0x95 T2EX;
+__sbit __at 0x96 P1_6;
+__sbit __at 0x96 CLKOUT;
+__sbit __at 0x97 P1_7;
+__sbit __at 0x97 T2;
/* defining bits in SFR SCON */
-sbit at 0x98 RI;
-sbit at 0x99 TI;
-sbit at 0x9a RB8;
-sbit at 0x9b TB8;
-sbit at 0x9c REN;
-sbit at 0x9d SM2;
-sbit at 0x9e SM1;
-sbit at 0x9f SM0;
+__sbit __at 0x98 RI;
+__sbit __at 0x99 TI;
+__sbit __at 0x9a RB8;
+__sbit __at 0x9b TB8;
+__sbit __at 0x9c REN;
+__sbit __at 0x9d SM2;
+__sbit __at 0x9e SM1;
+__sbit __at 0x9f SM0;
/* defining bits in SFR P2 */
-sbit at 0xa0 P2_0;
-sbit at 0xa1 P2_1;
-sbit at 0xa2 P2_2;
-sbit at 0xa3 P2_3;
-sbit at 0xa4 P2_4;
-sbit at 0xa5 P2_5;
-sbit at 0xa6 P2_6;
-sbit at 0xa7 P2_7;
+__sbit __at 0xa0 P2_0;
+__sbit __at 0xa1 P2_1;
+__sbit __at 0xa2 P2_2;
+__sbit __at 0xa3 P2_3;
+__sbit __at 0xa4 P2_4;
+__sbit __at 0xa5 P2_5;
+__sbit __at 0xa6 P2_6;
+__sbit __at 0xa7 P2_7;
/* defining bits in SFR IEN0 */
-sbit at 0xa8 EX0;
-sbit at 0xa9 ET0;
-sbit at 0xaa EX1;
-sbit at 0xab ET1;
-sbit at 0xac ES;
-sbit at 0xad ET2;
-sbit at 0xae WDT;
-sbit at 0xaf EA;
+__sbit __at 0xa8 EX0;
+__sbit __at 0xa9 ET0;
+__sbit __at 0xaa EX1;
+__sbit __at 0xab ET1;
+__sbit __at 0xac ES;
+__sbit __at 0xad ET2;
+__sbit __at 0xae WDT;
+__sbit __at 0xaf EA;
/* defining bits in SFR P3 */
-sbit at 0xb0 P3_0;
-sbit at 0xb0 RXD;
-sbit at 0xb1 P3_1;
-sbit at 0xb1 TXD;
-sbit at 0xb2 P3_2;
-sbit at 0xb2 INT0;
-sbit at 0xb3 P3_3;
-sbit at 0xb3 INT1;
-sbit at 0xb4 P3_4;
-sbit at 0xb4 T0;
-sbit at 0xb5 P3_5;
-sbit at 0xb5 T1;
-sbit at 0xb6 P3_6;
-sbit at 0xb6 WR;
-sbit at 0xb7 P3_7;
-sbit at 0xb7 RD;
+__sbit __at 0xb0 P3_0;
+__sbit __at 0xb0 RXD;
+__sbit __at 0xb1 P3_1;
+__sbit __at 0xb1 TXD;
+__sbit __at 0xb2 P3_2;
+__sbit __at 0xb2 INT0;
+__sbit __at 0xb3 P3_3;
+__sbit __at 0xb3 INT1;
+__sbit __at 0xb4 P3_4;
+__sbit __at 0xb4 T0;
+__sbit __at 0xb5 P3_5;
+__sbit __at 0xb5 T1;
+__sbit __at 0xb6 P3_6;
+__sbit __at 0xb6 WR;
+__sbit __at 0xb7 P3_7;
+__sbit __at 0xb7 RD;
/* defining bits in SFR IEN1 */
-sbit at 0xb8 EADC;
-sbit at 0xb9 EX2;
-sbit at 0xba EX3;
-sbit at 0xbb EX4;
-sbit at 0xbc EX5;
-sbit at 0xbd EX6;
-sbit at 0xbe SWDT;
-sbit at 0xbf EXEN2;
+__sbit __at 0xb8 EADC;
+__sbit __at 0xb9 EX2;
+__sbit __at 0xba EX3;
+__sbit __at 0xbb EX4;
+__sbit __at 0xbc EX5;
+__sbit __at 0xbd EX6;
+__sbit __at 0xbe SWDT;
+__sbit __at 0xbf EXEN2;
/* defining bits in SFR IRCON */
-sbit at 0xc0 IADC;
-sbit at 0xc1 IEX2;
-sbit at 0xc2 IEX3;
-sbit at 0xc3 IEX4;
-sbit at 0xc4 IEX5;
-sbit at 0xc5 IEX6;
-sbit at 0xc6 TF2;
-sbit at 0xc7 EXF2;
+__sbit __at 0xc0 IADC;
+__sbit __at 0xc1 IEX2;
+__sbit __at 0xc2 IEX3;
+__sbit __at 0xc3 IEX4;
+__sbit __at 0xc4 IEX5;
+__sbit __at 0xc5 IEX6;
+__sbit __at 0xc6 TF2;
+__sbit __at 0xc7 EXF2;
/* defining bits in SFR T2CON */
-sbit at 0xc8 T2I0;
-sbit at 0xc9 T2I1;
-sbit at 0xca T2CM;
-sbit at 0xcb T2R0;
-sbit at 0xcc T2R1;
-sbit at 0xcd I2FR;
-sbit at 0xce I3FR;
-sbit at 0xcf T2PS;
+__sbit __at 0xc8 T2I0;
+__sbit __at 0xc9 T2I1;
+__sbit __at 0xca T2CM;
+__sbit __at 0xcb T2R0;
+__sbit __at 0xcc T2R1;
+__sbit __at 0xcd I2FR;
+__sbit __at 0xce I3FR;
+__sbit __at 0xcf T2PS;
/* defining bits in SFR PSW */
-sbit at 0xd0 P;
-sbit at 0xd1 F1;
-sbit at 0xd2 OV;
-sbit at 0xd3 RS0;
-sbit at 0xd4 RS1;
-sbit at 0xd5 F0;
-sbit at 0xd6 AC;
-sbit at 0xd7 CY;
+__sbit __at 0xd0 P;
+__sbit __at 0xd1 F1;
+__sbit __at 0xd2 OV;
+__sbit __at 0xd3 RS0;
+__sbit __at 0xd4 RS1;
+__sbit __at 0xd5 F0;
+__sbit __at 0xd6 AC;
+__sbit __at 0xd7 CY;
/* defining bits in SFR ADCON0 */
-sbit at 0xd8 MX0;
-sbit at 0xd9 MX1;
-sbit at 0xda MX2;
-sbit at 0xdb ADM;
-sbit at 0xdc BSY;
-sbit at 0xdd ADEX;
-sbit at 0xde CLK;
-sbit at 0xdf BD;
+__sbit __at 0xd8 MX0;
+__sbit __at 0xd9 MX1;
+__sbit __at 0xda MX2;
+__sbit __at 0xdb ADM;
+__sbit __at 0xdc BSY;
+__sbit __at 0xdd ADEX;
+__sbit __at 0xde CLK;
+__sbit __at 0xdf BD;
/* defining bits in SFR ACC */
-sbit at 0xe0 ACC_0;
-sbit at 0xe1 ACC_1;
-sbit at 0xe2 ACC_2;
-sbit at 0xe3 ACC_3;
-sbit at 0xe4 ACC_4;
-sbit at 0xe5 ACC_5;
-sbit at 0xe6 ACC_6;
-sbit at 0xe7 ACC_7;
+__sbit __at 0xe0 ACC_0;
+__sbit __at 0xe1 ACC_1;
+__sbit __at 0xe2 ACC_2;
+__sbit __at 0xe3 ACC_3;
+__sbit __at 0xe4 ACC_4;
+__sbit __at 0xe5 ACC_5;
+__sbit __at 0xe6 ACC_6;
+__sbit __at 0xe7 ACC_7;
/* defining bits in SFR P4 */
-sbit at 0xe8 P4_0;
-sbit at 0xe8 ADST;
-sbit at 0xe9 P4_1;
-sbit at 0xe9 SCLK;
-sbit at 0xea P4_2;
-sbit at 0xea SRI;
-sbit at 0xeb P4_3;
-sbit at 0xeb STO;
-sbit at 0xec P4_4;
-sbit at 0xec SLS;
-sbit at 0xed P4_5;
-sbit at 0xed INT8;
-sbit at 0xee P4_6;
-sbit at 0xee TXDC;
-sbit at 0xef P4_7;
-sbit at 0xef RXDC;
+__sbit __at 0xe8 P4_0;
+__sbit __at 0xe8 ADST;
+__sbit __at 0xe9 P4_1;
+__sbit __at 0xe9 SCLK;
+__sbit __at 0xea P4_2;
+__sbit __at 0xea SRI;
+__sbit __at 0xeb P4_3;
+__sbit __at 0xeb STO;
+__sbit __at 0xec P4_4;
+__sbit __at 0xec SLS;
+__sbit __at 0xed P4_5;
+__sbit __at 0xed INT8;
+__sbit __at 0xee P4_6;
+__sbit __at 0xee TXDC;
+__sbit __at 0xef P4_7;
+__sbit __at 0xef RXDC;
/* defining bits in SFR B */
-sbit at 0xf0 B_0;
-sbit at 0xf1 B_1;
-sbit at 0xf2 B_2;
-sbit at 0xf3 B_3;
-sbit at 0xf4 B_4;
-sbit at 0xf5 B_5;
-sbit at 0xf6 B_6;
-sbit at 0xf7 B_7;
+__sbit __at 0xf0 B_0;
+__sbit __at 0xf1 B_1;
+__sbit __at 0xf2 B_2;
+__sbit __at 0xf3 B_3;
+__sbit __at 0xf4 B_4;
+__sbit __at 0xf5 B_5;
+__sbit __at 0xf6 B_6;
+__sbit __at 0xf7 B_7;
/* defining bits in SFR DIR5 */
-sbit at 0xf8 P5_0;
-sbit at 0xf9 P5_1;
-sbit at 0xfa P5_2;
-sbit at 0xfb P5_3;
-sbit at 0xfc P5_4;
-sbit at 0xfd P5_5;
-sbit at 0xfe P5_6;
-sbit at 0xff P5_7;
-sbit at 0xf8 DIR5_0;
-sbit at 0xf9 DIR5_1;
-sbit at 0xfa DIR5_2;
-sbit at 0xfb DIR5_3;
-sbit at 0xfc DIR5_4;
-sbit at 0xfd DIR5_5;
-sbit at 0xfe DIR5_6;
-sbit at 0xff DIR5_7;
+__sbit __at 0xf8 P5_0;
+__sbit __at 0xf9 P5_1;
+__sbit __at 0xfa P5_2;
+__sbit __at 0xfb P5_3;
+__sbit __at 0xfc P5_4;
+__sbit __at 0xfd P5_5;
+__sbit __at 0xfe P5_6;
+__sbit __at 0xff P5_7;
+__sbit __at 0xf8 DIR5_0;
+__sbit __at 0xf9 DIR5_1;
+__sbit __at 0xfa DIR5_2;
+__sbit __at 0xfb DIR5_3;
+__sbit __at 0xfc DIR5_4;
+__sbit __at 0xfd DIR5_5;
+__sbit __at 0xfe DIR5_6;
+__sbit __at 0xff DIR5_7;
#endif /* _REGC515C_H */
#define SAB80515_H
/* BYTE addressable registers */
-sfr at 0x80 P0 ;
-sfr at 0x81 SP ;
-sfr at 0x82 DPL ;
-sfr at 0x83 DPH ;
-sfr at 0x87 PCON ;
-sfr at 0x88 TCON ;
-sfr at 0x89 TMOD ;
-sfr at 0x8A TL0 ;
-sfr at 0x8B TL1 ;
-sfr at 0x8C TH0 ;
-sfr at 0x8D TH1 ;
-sfr at 0x90 P1 ;
-sfr at 0x98 SCON ;
-sfr at 0x99 SBUF ;
-sfr at 0xA0 P2 ;
-sfr at 0xA8 IE ;
-sfr at 0xA8 IEN0 ; /* as called by Siemens */
-sfr at 0xA9 IP0 ; /* interrupt priority register - SAB80515 specific */
-sfr at 0xB0 P3 ;
-sfr at 0xB8 IEN1 ; /* interrupt enable register - SAB80515 specific */
-sfr at 0xB9 IP1 ; /* interrupt priority register as called by Siemens */
-sfr at 0xC0 IRCON ; /* interrupt control register - SAB80515 specific */
-sfr at 0xC1 CCEN ; /* compare/capture enable register */
-sfr at 0xC2 CCL1 ; /* compare/capture register 1, low byte */
-sfr at 0xC3 CCH1 ; /* compare/capture register 1, high byte */
-sfr at 0xC4 CCL2 ; /* compare/capture register 2, low byte */
-sfr at 0xC5 CCH2 ; /* compare/capture register 2, high byte */
-sfr at 0xC6 CCL3 ; /* compare/capture register 3, low byte */
-sfr at 0xC7 CCH3 ; /* compare/capture register 3, high byte */
-sfr at 0xC8 T2CON ;
-sfr at 0xCA CRCL ; /* compare/reload/capture register, low byte */
-sfr at 0xCB CRCH ; /* compare/reload/capture register, high byte */
-sfr at 0xCC TL2 ;
-sfr at 0xCD TH2 ;
-sfr at 0xD0 PSW ;
-sfr at 0xD8 ADCON ; /* A/D-converter control register */
-sfr at 0xD9 ADDAT ; /* A/D-converter data register */
-sfr at 0xDA DAPR ; /* D/A-converter program register */
-sfr at 0xDB P6 ; /* Port 6 - SAB80515 specific */
-sfr at 0xE0 ACC ;
-sfr at 0xE0 A ;
-sfr at 0xE8 P4 ; /* Port 4 - SAB80515 specific */
-sfr at 0xF0 B ;
-sfr at 0xF8 P5 ; /* Port 5 - SAB80515 specific */
+__sfr __at 0x80 P0 ;
+__sfr __at 0x81 SP ;
+__sfr __at 0x82 DPL ;
+__sfr __at 0x83 DPH ;
+__sfr __at 0x87 PCON ;
+__sfr __at 0x88 TCON ;
+__sfr __at 0x89 TMOD ;
+__sfr __at 0x8A TL0 ;
+__sfr __at 0x8B TL1 ;
+__sfr __at 0x8C TH0 ;
+__sfr __at 0x8D TH1 ;
+__sfr __at 0x90 P1 ;
+__sfr __at 0x98 SCON ;
+__sfr __at 0x99 SBUF ;
+__sfr __at 0xA0 P2 ;
+__sfr __at 0xA8 IE ;
+__sfr __at 0xA8 IEN0 ; /* as called by Siemens */
+__sfr __at 0xA9 IP0 ; /* interrupt priority register - SAB80515 specific */
+__sfr __at 0xB0 P3 ;
+__sfr __at 0xB8 IEN1 ; /* interrupt enable register - SAB80515 specific */
+__sfr __at 0xB9 IP1 ; /* interrupt priority register as called by Siemens */
+__sfr __at 0xC0 IRCON ; /* interrupt control register - SAB80515 specific */
+__sfr __at 0xC1 CCEN ; /* compare/capture enable register */
+__sfr __at 0xC2 CCL1 ; /* compare/capture register 1, low byte */
+__sfr __at 0xC3 CCH1 ; /* compare/capture register 1, high byte */
+__sfr __at 0xC4 CCL2 ; /* compare/capture register 2, low byte */
+__sfr __at 0xC5 CCH2 ; /* compare/capture register 2, high byte */
+__sfr __at 0xC6 CCL3 ; /* compare/capture register 3, low byte */
+__sfr __at 0xC7 CCH3 ; /* compare/capture register 3, high byte */
+__sfr __at 0xC8 T2CON ;
+__sfr __at 0xCA CRCL ; /* compare/reload/capture register, low byte */
+__sfr __at 0xCB CRCH ; /* compare/reload/capture register, high byte */
+__sfr __at 0xCC TL2 ;
+__sfr __at 0xCD TH2 ;
+__sfr __at 0xD0 PSW ;
+__sfr __at 0xD8 ADCON ; /* A/D-converter control register */
+__sfr __at 0xD9 ADDAT ; /* A/D-converter data register */
+__sfr __at 0xDA DAPR ; /* D/A-converter program register */
+__sfr __at 0xDB P6 ; /* Port 6 - SAB80515 specific */
+__sfr __at 0xE0 ACC ;
+__sfr __at 0xE0 A ;
+__sfr __at 0xE8 P4 ; /* Port 4 - SAB80515 specific */
+__sfr __at 0xF0 B ;
+__sfr __at 0xF8 P5 ; /* Port 5 - SAB80515 specific */
/* BIT addressable registers */
/* P0 */
-sbit at 0x80 P0_0 ;
-sbit at 0x81 P0_1 ;
-sbit at 0x82 P0_2 ;
-sbit at 0x83 P0_3 ;
-sbit at 0x84 P0_4 ;
-sbit at 0x85 P0_5 ;
-sbit at 0x86 P0_6 ;
-sbit at 0x87 P0_7 ;
+__sbit __at 0x80 P0_0 ;
+__sbit __at 0x81 P0_1 ;
+__sbit __at 0x82 P0_2 ;
+__sbit __at 0x83 P0_3 ;
+__sbit __at 0x84 P0_4 ;
+__sbit __at 0x85 P0_5 ;
+__sbit __at 0x86 P0_6 ;
+__sbit __at 0x87 P0_7 ;
/* TCON */
-sbit at 0x88 IT0 ;
-sbit at 0x89 IE0 ;
-sbit at 0x8A IT1 ;
-sbit at 0x8B IE1 ;
-sbit at 0x8C TR0 ;
-sbit at 0x8D TF0 ;
-sbit at 0x8E TR1 ;
-sbit at 0x8F TF1 ;
+__sbit __at 0x88 IT0 ;
+__sbit __at 0x89 IE0 ;
+__sbit __at 0x8A IT1 ;
+__sbit __at 0x8B IE1 ;
+__sbit __at 0x8C TR0 ;
+__sbit __at 0x8D TF0 ;
+__sbit __at 0x8E TR1 ;
+__sbit __at 0x8F TF1 ;
/* P1 */
-sbit at 0x90 P1_0 ;
-sbit at 0x91 P1_1 ;
-sbit at 0x92 P1_2 ;
-sbit at 0x93 P1_3 ;
-sbit at 0x94 P1_4 ;
-sbit at 0x95 P1_5 ;
-sbit at 0x96 P1_6 ;
-sbit at 0x97 P1_7 ;
-
-sbit at 0x90 INT3_CC0 ; /* P1 alternate functions - SAB80515 specific */
-sbit at 0x91 INT4_CC1 ;
-sbit at 0x92 INT5_CC2 ;
-sbit at 0x93 INT6_CC3 ;
-sbit at 0x94 INT2 ;
-sbit at 0x95 T2EX ;
-sbit at 0x96 CLKOUT ;
-sbit at 0x97 T2 ;
+__sbit __at 0x90 P1_0 ;
+__sbit __at 0x91 P1_1 ;
+__sbit __at 0x92 P1_2 ;
+__sbit __at 0x93 P1_3 ;
+__sbit __at 0x94 P1_4 ;
+__sbit __at 0x95 P1_5 ;
+__sbit __at 0x96 P1_6 ;
+__sbit __at 0x97 P1_7 ;
+
+__sbit __at 0x90 INT3_CC0 ; /* P1 alternate functions - SAB80515 specific */
+__sbit __at 0x91 INT4_CC1 ;
+__sbit __at 0x92 INT5_CC2 ;
+__sbit __at 0x93 INT6_CC3 ;
+__sbit __at 0x94 INT2 ;
+__sbit __at 0x95 T2EX ;
+__sbit __at 0x96 CLKOUT ;
+__sbit __at 0x97 T2 ;
/* SCON */
-sbit at 0x98 RI ;
-sbit at 0x99 TI ;
-sbit at 0x9A RB8 ;
-sbit at 0x9B TB8 ;
-sbit at 0x9C REN ;
-sbit at 0x9D SM2 ;
-sbit at 0x9E SM1 ;
-sbit at 0x9F SM0 ;
+__sbit __at 0x98 RI ;
+__sbit __at 0x99 TI ;
+__sbit __at 0x9A RB8 ;
+__sbit __at 0x9B TB8 ;
+__sbit __at 0x9C REN ;
+__sbit __at 0x9D SM2 ;
+__sbit __at 0x9E SM1 ;
+__sbit __at 0x9F SM0 ;
/* P2 */
-sbit at 0xA0 P2_0 ;
-sbit at 0xA1 P2_1 ;
-sbit at 0xA2 P2_2 ;
-sbit at 0xA3 P2_3 ;
-sbit at 0xA4 P2_4 ;
-sbit at 0xA5 P2_5 ;
-sbit at 0xA6 P2_6 ;
-sbit at 0xA7 P2_7 ;
+__sbit __at 0xA0 P2_0 ;
+__sbit __at 0xA1 P2_1 ;
+__sbit __at 0xA2 P2_2 ;
+__sbit __at 0xA3 P2_3 ;
+__sbit __at 0xA4 P2_4 ;
+__sbit __at 0xA5 P2_5 ;
+__sbit __at 0xA6 P2_6 ;
+__sbit __at 0xA7 P2_7 ;
/* IEN0 */
-sbit at 0xA8 EX0 ;
-sbit at 0xA9 ET0 ;
-sbit at 0xAA EX1 ;
-sbit at 0xAB ET1 ;
-sbit at 0xAC ES ;
-sbit at 0xAD ET2 ;
-sbit at 0xAE WDT ; /* watchdog timer reset - SAB80515 specific */
-sbit at 0xAF EA ;
+__sbit __at 0xA8 EX0 ;
+__sbit __at 0xA9 ET0 ;
+__sbit __at 0xAA EX1 ;
+__sbit __at 0xAB ET1 ;
+__sbit __at 0xAC ES ;
+__sbit __at 0xAD ET2 ;
+__sbit __at 0xAE WDT ; /* watchdog timer reset - SAB80515 specific */
+__sbit __at 0xAF EA ;
-sbit at 0xAF EAL ; /* EA as called by Siemens */
+__sbit __at 0xAF EAL ; /* EA as called by Siemens */
/* P3 */
-sbit at 0xB0 P3_0 ;
-sbit at 0xB1 P3_1 ;
-sbit at 0xB2 P3_2 ;
-sbit at 0xB3 P3_3 ;
-sbit at 0xB4 P3_4 ;
-sbit at 0xB5 P3_5 ;
-sbit at 0xB6 P3_6 ;
-sbit at 0xB7 P3_7 ;
-
-sbit at 0xB0 RXD ;
-sbit at 0xB1 TXD ;
-sbit at 0xB2 INT0 ;
-sbit at 0xB3 INT1 ;
-sbit at 0xB4 T0 ;
-sbit at 0xB5 T1 ;
-sbit at 0xB6 WR ;
-sbit at 0xB7 RD ;
+__sbit __at 0xB0 P3_0 ;
+__sbit __at 0xB1 P3_1 ;
+__sbit __at 0xB2 P3_2 ;
+__sbit __at 0xB3 P3_3 ;
+__sbit __at 0xB4 P3_4 ;
+__sbit __at 0xB5 P3_5 ;
+__sbit __at 0xB6 P3_6 ;
+__sbit __at 0xB7 P3_7 ;
+
+__sbit __at 0xB0 RXD ;
+__sbit __at 0xB1 TXD ;
+__sbit __at 0xB2 INT0 ;
+__sbit __at 0xB3 INT1 ;
+__sbit __at 0xB4 T0 ;
+__sbit __at 0xB5 T1 ;
+__sbit __at 0xB6 WR ;
+__sbit __at 0xB7 RD ;
/* IEN1 */
-sbit at 0xB8 EADC ; /* A/D converter interrupt enable */
-sbit at 0xB9 EX2 ;
-sbit at 0xBA EX3 ;
-sbit at 0xBB EX4 ;
-sbit at 0xBC EX5 ;
-sbit at 0xBD EX6 ;
-sbit at 0xBE SWDT ; /* watchdog timer start/reset */
-sbit at 0xBF EXEN2 ; /* timer2 external reload interrupt enable */
+__sbit __at 0xB8 EADC ; /* A/D converter interrupt enable */
+__sbit __at 0xB9 EX2 ;
+__sbit __at 0xBA EX3 ;
+__sbit __at 0xBB EX4 ;
+__sbit __at 0xBC EX5 ;
+__sbit __at 0xBD EX6 ;
+__sbit __at 0xBE SWDT ; /* watchdog timer start/reset */
+__sbit __at 0xBF EXEN2 ; /* timer2 external reload interrupt enable */
/* IRCON */
-sbit at 0xC0 IADC ; /* A/D converter irq flag */
-sbit at 0xC1 IEX2 ; /* external interrupt edge detect flag */
-sbit at 0xC2 IEX3 ;
-sbit at 0xC3 IEX4 ;
-sbit at 0xC4 IEX5 ;
-sbit at 0xC5 IEX6 ;
-sbit at 0xC6 TF2 ; /* timer 2 owerflow flag */
-sbit at 0xC7 EXF2 ; /* timer2 reload flag */
+__sbit __at 0xC0 IADC ; /* A/D converter irq flag */
+__sbit __at 0xC1 IEX2 ; /* external interrupt edge detect flag */
+__sbit __at 0xC2 IEX3 ;
+__sbit __at 0xC3 IEX4 ;
+__sbit __at 0xC4 IEX5 ;
+__sbit __at 0xC5 IEX6 ;
+__sbit __at 0xC6 TF2 ; /* timer 2 owerflow flag */
+__sbit __at 0xC7 EXF2 ; /* timer2 reload flag */
/* T2CON */
-sbit at 0xC8 T2CON_0 ;
-sbit at 0xC9 T2CON_1 ;
-sbit at 0xCA T2CON_2 ;
-sbit at 0xCB T2CON_3 ;
-sbit at 0xCC T2CON_4 ;
-sbit at 0xCD T2CON_5 ;
-sbit at 0xCE T2CON_6 ;
-sbit at 0xCF T2CON_7 ;
-
-sbit at 0xC8 T2I0 ;
-sbit at 0xC9 T2I1 ;
-sbit at 0xCA T2CM ;
-sbit at 0xCB T2R0 ;
-sbit at 0xCC T2R1 ;
-sbit at 0xCD I2FR ;
-sbit at 0xCE I3FR ;
-sbit at 0xCF T2PS ;
+__sbit __at 0xC8 T2CON_0 ;
+__sbit __at 0xC9 T2CON_1 ;
+__sbit __at 0xCA T2CON_2 ;
+__sbit __at 0xCB T2CON_3 ;
+__sbit __at 0xCC T2CON_4 ;
+__sbit __at 0xCD T2CON_5 ;
+__sbit __at 0xCE T2CON_6 ;
+__sbit __at 0xCF T2CON_7 ;
+
+__sbit __at 0xC8 T2I0 ;
+__sbit __at 0xC9 T2I1 ;
+__sbit __at 0xCA T2CM ;
+__sbit __at 0xCB T2R0 ;
+__sbit __at 0xCC T2R1 ;
+__sbit __at 0xCD I2FR ;
+__sbit __at 0xCE I3FR ;
+__sbit __at 0xCF T2PS ;
/* PSW */
-sbit at 0xD0 P ;
-sbit at 0xD1 FL ;
-sbit at 0xD2 OV ;
-sbit at 0xD3 RS0 ;
-sbit at 0xD4 RS1 ;
-sbit at 0xD5 F0 ;
-sbit at 0xD6 AC ;
-sbit at 0xD7 CY ;
+__sbit __at 0xD0 P ;
+__sbit __at 0xD1 FL ;
+__sbit __at 0xD2 OV ;
+__sbit __at 0xD3 RS0 ;
+__sbit __at 0xD4 RS1 ;
+__sbit __at 0xD5 F0 ;
+__sbit __at 0xD6 AC ;
+__sbit __at 0xD7 CY ;
-sbit at 0xD1 F1 ;
+__sbit __at 0xD1 F1 ;
/* ADCON */
-sbit at 0xD8 MX0 ;
-sbit at 0xD9 MX1 ;
-sbit at 0xDA MX2 ;
-sbit at 0xDB ADM ;
-sbit at 0xDC BSY ;
+__sbit __at 0xD8 MX0 ;
+__sbit __at 0xD9 MX1 ;
+__sbit __at 0xDA MX2 ;
+__sbit __at 0xDB ADM ;
+__sbit __at 0xDC BSY ;
-sbit at 0xDE CLK ;
-sbit at 0xDF BD ;
+__sbit __at 0xDE CLK ;
+__sbit __at 0xDF BD ;
/* A */
-sbit at 0xA0 AREG_F0 ;
-sbit at 0xA1 AREG_F1 ;
-sbit at 0xA2 AREG_F2 ;
-sbit at 0xA3 AREG_F3 ;
-sbit at 0xA4 AREG_F4 ;
-sbit at 0xA5 AREG_F5 ;
-sbit at 0xA6 AREG_F6 ;
-sbit at 0xA7 AREG_F7 ;
+__sbit __at 0xA0 AREG_F0 ;
+__sbit __at 0xA1 AREG_F1 ;
+__sbit __at 0xA2 AREG_F2 ;
+__sbit __at 0xA3 AREG_F3 ;
+__sbit __at 0xA4 AREG_F4 ;
+__sbit __at 0xA5 AREG_F5 ;
+__sbit __at 0xA6 AREG_F6 ;
+__sbit __at 0xA7 AREG_F7 ;
/* P4 */
-sbit at 0xE8 P4_0 ;
-sbit at 0xE9 P4_1 ;
-sbit at 0xEA P4_2 ;
-sbit at 0xEB P4_3 ;
-sbit at 0xEC P4_4 ;
-sbit at 0xED P4_5 ;
-sbit at 0xEE P4_6 ;
-sbit at 0xEF P4_7 ;
+__sbit __at 0xE8 P4_0 ;
+__sbit __at 0xE9 P4_1 ;
+__sbit __at 0xEA P4_2 ;
+__sbit __at 0xEB P4_3 ;
+__sbit __at 0xEC P4_4 ;
+__sbit __at 0xED P4_5 ;
+__sbit __at 0xEE P4_6 ;
+__sbit __at 0xEF P4_7 ;
/* B */
-sbit at 0xF0 BREG_F0 ;
-sbit at 0xF1 BREG_F1 ;
-sbit at 0xF2 BREG_F2 ;
-sbit at 0xF3 BREG_F3 ;
-sbit at 0xF4 BREG_F4 ;
-sbit at 0xF5 BREG_F5 ;
-sbit at 0xF6 BREG_F6 ;
-sbit at 0xF7 BREG_F7 ;
+__sbit __at 0xF0 BREG_F0 ;
+__sbit __at 0xF1 BREG_F1 ;
+__sbit __at 0xF2 BREG_F2 ;
+__sbit __at 0xF3 BREG_F3 ;
+__sbit __at 0xF4 BREG_F4 ;
+__sbit __at 0xF5 BREG_F5 ;
+__sbit __at 0xF6 BREG_F6 ;
+__sbit __at 0xF7 BREG_F7 ;
/* P5 */
-sbit at 0xF8 P5_0 ;
-sbit at 0xF9 P5_1 ;
-sbit at 0xFA P5_2 ;
-sbit at 0xFB P5_3 ;
-sbit at 0xFC P5_4 ;
-sbit at 0xFD P5_5 ;
-sbit at 0xFE P5_6 ;
-sbit at 0xFF P5_7 ;
+__sbit __at 0xF8 P5_0 ;
+__sbit __at 0xF9 P5_1 ;
+__sbit __at 0xFA P5_2 ;
+__sbit __at 0xFB P5_3 ;
+__sbit __at 0xFC P5_4 ;
+__sbit __at 0xFD P5_5 ;
+__sbit __at 0xFE P5_6 ;
+__sbit __at 0xFF P5_7 ;
/* BIT definitions for bits that are not directly accessible */
/* PCON bits */
#elif defined(SDCC_USE_XSTACK)
typedef unsigned char pdata * va_list ;
-#define va_arg(marker,type) *((type data *)(marker -= sizeof(type)))
-#define va_start(marker,first) { marker = (va_list)((char pdata *)&first); }
+#define va_arg(marker,type) *((type __data *)(marker -= sizeof(type)))
+#define va_start(marker,first) { marker = (va_list)((char __pdata *)&first); }
#else
typedef unsigned char data * va_list ;
-#define va_arg(marker,type) *((type data * )(marker -= sizeof(type)))
-#define va_start(marker,first) { marker = (va_list) ((char data * )&first); }
+#define va_arg(marker,type) *((type __data * )(marker -= sizeof(type)))
+#define va_start(marker,first) { marker = (va_list) ((char __data * )&first); }
#endif
#ifndef __SDC51_STDBOOL_H
#define __SDC51_STDBOOL_H 1
-#define _Bool bit
+#define _Bool __bit
#define bool _Bool
#define true 1
//as long as bit/bool cannot be used reentrant
#define BOOL char
#else
- #define BOOL bit
+ #define BOOL __bit
#endif
#endif
extern void *memmove (void *, void *, size_t ) ;
#ifdef SDCC_ds390
-extern void xdata * memcpyx(void xdata *, void xdata *, int) _naked;
+extern void __xdata * memcpyx(void __xdata *, void __xdata *, int) __naked;
#endif
extern void LcdPutChar(char c);
extern void LcdPutString(char *string);
extern void LcdLPutString(unsigned int collumnRow, char *string);
-extern void LcdPrintf(const char *format, ...) reentrant;
-extern void LcdLPrintf(unsigned int collumnRow, const char *format, ...) reentrant;
+extern void LcdPrintf(const char *format, ...) __reentrant;
+extern void LcdLPrintf(unsigned int collumnRow, const char *format, ...) __reentrant;
// from i2c390.c
#define I2C_BUFSIZE 128
// internal functions used by tinibios.c
unsigned char _sdcc_external_startup(void);
-void Serial0IrqHandler (void) interrupt 4;
-void Serial1IrqHandler (void) interrupt 7;
+void Serial0IrqHandler (void) __interrupt 4;
+void Serial1IrqHandler (void) __interrupt 7;
#if !defined(SDCC_ds400)
void ClockInit();
-void ClockIrqHandler (void) interrupt 1 _naked;
+void ClockIrqHandler (void) __interrupt 1 __naked;
#endif
#if defined(SDCC_ds400)
/* will want this to be the case by default (I think) */
#pragma portmode z180
-static void _ENABLE_Z180_ASSEMBLER_(void) _naked { _asm .hd64 _endasm; }
+static void _ENABLE_Z180_ASSEMBLER_(void) __naked { __asm .hd64 __endasm; }
/*
*---------------------------------------------------------------------------
* Z180/HD64180 internal port addresses
*/
-sfr at (Z180_IO_BASE+0x00) CNTLA0; /* ASCI control register A channel 0 */
-sfr at (Z180_IO_BASE+0x01) CNTLA1; /* ASCI control register A channel 1 */
-sfr at (Z180_IO_BASE+0x02) CNTLB0; /* ASCI control register B channel 0 */
-sfr at (Z180_IO_BASE+0x03) CNTLB1; /* ASCI control register B channel 0 */
-sfr at (Z180_IO_BASE+0x04) STAT0 ; /* ASCI status register channel 0 */
-sfr at (Z180_IO_BASE+0x05) STAT1 ; /* ASCI status register channel 1 */
-sfr at (Z180_IO_BASE+0x06) TDR0 ; /* ASCI transmit data reg, channel 0 */
-sfr at (Z180_IO_BASE+0x07) TDR1 ; /* ASCI transmit data reg, channel 1 */
-sfr at (Z180_IO_BASE+0x08) RDR0 ; /* ASCI receive data reg, channel 0 */
-sfr at (Z180_IO_BASE+0x09) RDR1 ; /* ASCI receive data reg, channel 0 */
-sfr at (Z180_IO_BASE+0x0A) CNTR ; /* CSI/0 control register */
-sfr at (Z180_IO_BASE+0x0B) TRDR ; /* CSI/0 transmit/receive data reg */
+__sfr __at (Z180_IO_BASE+0x00) CNTLA0; /* ASCI control register A channel 0 */
+__sfr __at (Z180_IO_BASE+0x01) CNTLA1; /* ASCI control register A channel 1 */
+__sfr __at (Z180_IO_BASE+0x02) CNTLB0; /* ASCI control register B channel 0 */
+__sfr __at (Z180_IO_BASE+0x03) CNTLB1; /* ASCI control register B channel 0 */
+__sfr __at (Z180_IO_BASE+0x04) STAT0 ; /* ASCI status register channel 0 */
+__sfr __at (Z180_IO_BASE+0x05) STAT1 ; /* ASCI status register channel 1 */
+__sfr __at (Z180_IO_BASE+0x06) TDR0 ; /* ASCI transmit data reg, channel 0 */
+__sfr __at (Z180_IO_BASE+0x07) TDR1 ; /* ASCI transmit data reg, channel 1 */
+__sfr __at (Z180_IO_BASE+0x08) RDR0 ; /* ASCI receive data reg, channel 0 */
+__sfr __at (Z180_IO_BASE+0x09) RDR1 ; /* ASCI receive data reg, channel 0 */
+__sfr __at (Z180_IO_BASE+0x0A) CNTR ; /* CSI/0 control register */
+__sfr __at (Z180_IO_BASE+0x0B) TRDR ; /* CSI/0 transmit/receive data reg */
-sfr at (Z180_IO_BASE+0x0C) TMDR0L; /* Timer data register, channel 0L */
-sfr at (Z180_IO_BASE+0x0D) TMDR0H; /* Timer data register, channel 0H */
-sfr at (Z180_IO_BASE+0x0E) RLDR0L; /* Timer reload register, channel 0L */
-sfr at (Z180_IO_BASE+0x0F) RLDR0H; /* Timer reload register, channel 0H */
-sfr at (Z180_IO_BASE+0x10) TCR ; /* Timer control register */
-sfr at (Z180_IO_BASE+0x14) TMDR1L; /* Timer data register, channel 1L */
-sfr at (Z180_IO_BASE+0x15) TMDR1H; /* Timer data register, channel 1H */
-sfr at (Z180_IO_BASE+0x16) RLDR1L; /* Timer reload register, channel 1L */
-sfr at (Z180_IO_BASE+0x17) RLDR1H; /* Timer reload register, channel 1H */
-sfr at (Z180_IO_BASE+0x18) FRC ; /* Timer Free running counter */
+__sfr __at (Z180_IO_BASE+0x0C) TMDR0L; /* Timer data register, channel 0L */
+__sfr __at (Z180_IO_BASE+0x0D) TMDR0H; /* Timer data register, channel 0H */
+__sfr __at (Z180_IO_BASE+0x0E) RLDR0L; /* Timer reload register, channel 0L */
+__sfr __at (Z180_IO_BASE+0x0F) RLDR0H; /* Timer reload register, channel 0H */
+__sfr __at (Z180_IO_BASE+0x10) TCR ; /* Timer control register */
+__sfr __at (Z180_IO_BASE+0x14) TMDR1L; /* Timer data register, channel 1L */
+__sfr __at (Z180_IO_BASE+0x15) TMDR1H; /* Timer data register, channel 1H */
+__sfr __at (Z180_IO_BASE+0x16) RLDR1L; /* Timer reload register, channel 1L */
+__sfr __at (Z180_IO_BASE+0x17) RLDR1H; /* Timer reload register, channel 1H */
+__sfr __at (Z180_IO_BASE+0x18) FRC ; /* Timer Free running counter */
-sfr at (Z180_IO_BASE+0x20) SAR0L ; /* DMA source address reg, channel 0L */
-sfr at (Z180_IO_BASE+0x21) SAR0H ; /* DMA source address reg, channel 0H */
-sfr at (Z180_IO_BASE+0x22) SAR0B ; /* DMA source address reg, channel 0B */
-sfr at (Z180_IO_BASE+0x23) DAR0L ; /* DMA dest address reg, channel 0L */
-sfr at (Z180_IO_BASE+0x24) DAR0H ; /* DMA dest address reg, channel 0H */
-sfr at (Z180_IO_BASE+0x25) DAR0B ; /* DMA dest address reg, channel 0B */
-sfr at (Z180_IO_BASE+0x26) BCR0L ; /* DMA byte count reg, channel 0L */
-sfr at (Z180_IO_BASE+0x27) BCR0H ; /* DMA byte count reg, channel 0H */
-sfr at (Z180_IO_BASE+0x28) MAR1L ; /* DMA memory address reg, channel 1L */
-sfr at (Z180_IO_BASE+0x29) MAR1H ; /* DMA memory address reg, channel 1H */
-sfr at (Z180_IO_BASE+0x2A) MAR1B ; /* DMA memory address reg, channel 1B */
-sfr at (Z180_IO_BASE+0x2B) IAR1L ; /* DMA I/O address reg, channel 1L */
-sfr at (Z180_IO_BASE+0x2C) IAR1H ; /* DMA I/O address reg, channel 1H */
-sfr at (Z180_IO_BASE+0x2E) BCR1L ; /* DMA byte count reg, channel 1L */
-sfr at (Z180_IO_BASE+0x2F) BCR1H ; /* DMA byte count reg, channel 1H */
-sfr at (Z180_IO_BASE+0x30) DSTAT ; /* DMA status register */
-sfr at (Z180_IO_BASE+0x31) DMODE ; /* DMA mode register */
-sfr at (Z180_IO_BASE+0x32) DCNTL ; /* DMA/WAIT control register */
+__sfr __at (Z180_IO_BASE+0x20) SAR0L ; /* DMA source address reg, channel 0L */
+__sfr __at (Z180_IO_BASE+0x21) SAR0H ; /* DMA source address reg, channel 0H */
+__sfr __at (Z180_IO_BASE+0x22) SAR0B ; /* DMA source address reg, channel 0B */
+__sfr __at (Z180_IO_BASE+0x23) DAR0L ; /* DMA dest address reg, channel 0L */
+__sfr __at (Z180_IO_BASE+0x24) DAR0H ; /* DMA dest address reg, channel 0H */
+__sfr __at (Z180_IO_BASE+0x25) DAR0B ; /* DMA dest address reg, channel 0B */
+__sfr __at (Z180_IO_BASE+0x26) BCR0L ; /* DMA byte count reg, channel 0L */
+__sfr __at (Z180_IO_BASE+0x27) BCR0H ; /* DMA byte count reg, channel 0H */
+__sfr __at (Z180_IO_BASE+0x28) MAR1L ; /* DMA memory address reg, channel 1L */
+__sfr __at (Z180_IO_BASE+0x29) MAR1H ; /* DMA memory address reg, channel 1H */
+__sfr __at (Z180_IO_BASE+0x2A) MAR1B ; /* DMA memory address reg, channel 1B */
+__sfr __at (Z180_IO_BASE+0x2B) IAR1L ; /* DMA I/O address reg, channel 1L */
+__sfr __at (Z180_IO_BASE+0x2C) IAR1H ; /* DMA I/O address reg, channel 1H */
+__sfr __at (Z180_IO_BASE+0x2E) BCR1L ; /* DMA byte count reg, channel 1L */
+__sfr __at (Z180_IO_BASE+0x2F) BCR1H ; /* DMA byte count reg, channel 1H */
+__sfr __at (Z180_IO_BASE+0x30) DSTAT ; /* DMA status register */
+__sfr __at (Z180_IO_BASE+0x31) DMODE ; /* DMA mode register */
+__sfr __at (Z180_IO_BASE+0x32) DCNTL ; /* DMA/WAIT control register */
-sfr at (Z180_IO_BASE+0x33) IL ; /* Interrupt vector low register */
-sfr at (Z180_IO_BASE+0x34) ITC ; /* INT/TRAP control register */
+__sfr __at (Z180_IO_BASE+0x33) IL ; /* Interrupt vector low register */
+__sfr __at (Z180_IO_BASE+0x34) ITC ; /* INT/TRAP control register */
-sfr at (Z180_IO_BASE+0x36) RCR ; /* Refresh control register */
+__sfr __at (Z180_IO_BASE+0x36) RCR ; /* Refresh control register */
-sfr at (Z180_IO_BASE+0x38) CBR ; /* MMU common base register */
-sfr at (Z180_IO_BASE+0x39) BBR ; /* MMU bank base register */
-sfr at (Z180_IO_BASE+0x3A) CBAR ; /* MMU common/bank area register */
+__sfr __at (Z180_IO_BASE+0x38) CBR ; /* MMU common base register */
+__sfr __at (Z180_IO_BASE+0x39) BBR ; /* MMU bank base register */
+__sfr __at (Z180_IO_BASE+0x3A) CBAR ; /* MMU common/bank area register */
-sfr at (Z180_IO_BASE+0x3E) OMCR ; /* Operation mode control register */
+__sfr __at (Z180_IO_BASE+0x3E) OMCR ; /* Operation mode control register */
-sfr at 0x3F ICR ; /* I/O base control register - does not move */
+__sfr __at 0x3F ICR ; /* I/O base control register - does not move */
/*
*---------------------------------------------------------------------------
projects / fw / sdcc / commitdiff