riscv: Regenerated debug_defines.h and encoding.h

The main intention is to get access to some of the CSRs
that were so far unknown to OpenOCD (tinfo, mcountinhibit, ...).

https://github.com/riscv/riscv-openocd/pull/659

Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: I824fdb558d5c1f73432b0f56f3b0b4d865eceeba
Reviewed-on: https://review.openocd.org/c/openocd/+/6682
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

diff --git a/src/target/riscv/debug_defines.h b/src/target/riscv/debug_defines.h
index b5104d53060f58186053c2430c0ee9c643e29724..5c9eef4eafee2877ed18c8e5d0da9f3554fb5106 100644 (file)
--- a/src/target/riscv/debug_defines.h
+++ b/src/target/riscv/debug_defines.h
@@ -1,6 +1,6 @@
 /*
  * This file is auto-generated by running 'make debug_defines.h' in
- * https://github.com/riscv/riscv-debug-spec/ (63c985f)
+ * https://github.com/riscv/riscv-debug-spec/ (3dfe4f7)
  * License: Creative Commons Attribution 4.0 International Public License (CC BY 4.0)
  */
 
@@ -266,7 +266,7 @@
  *
  * 1: An {\tt ebreak} instruction was executed. (priority 3)
  *
- * 2: The Trigger Module caused a breakpoint exception. (priority 4)
+ * 2: A Trigger Module trigger fired with action=0. (priority 4)
  *
  * 3: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq.
  * (priority 1)
@@ -461,7 +461,7 @@
  *
  * \FcsrTcontrolMpte and \FcsrTcontrolMte provide one solution to a problem
  * regarding triggers with action=0 firing in M-mode trap handlers. See
- * Section~\ref{sec:mmtrigger} for more details.
+ * Section~\ref{sec:nativetrigger} for more details.
  *
  * When a trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of
  * \FcsrTcontrolMte.
@@ -811,8 +811,9 @@
 #define CSR_MCONTROL6_VU_LENGTH             1
 #define CSR_MCONTROL6_VU                    (0x1ULL << CSR_MCONTROL6_VU_OFFSET)
 /*
- * If this bit is implemented, the hardware sets it when this
- * trigger matches. The trigger's user can set or clear it at any
+ * If this bit is implemented then it must become set when this
+ * trigger fires and may become set when this trigger matches.
+ * The trigger's user can set or clear it at any
  * time. It is used to determine which
  * trigger(s) matched.  If the bit is not implemented, it is always 0
  * and writing it has no effect.
@@ -1237,7 +1238,8 @@
 #define CSR_ETRIGGER_VU                     (0x1ULL << CSR_ETRIGGER_VU_OFFSET)
 /*
  * When set, non-maskable interrupts cause this
- * trigger to fire, regardless of the values of \FcsrEtriggerM, \FcsrEtriggerS, and \FcsrEtriggerU.
+ * trigger to fire, regardless of the values of \FcsrEtriggerM,
+ * \FcsrEtriggerS, \FcsrEtriggerU, \FcsrEtriggerVs, and \FcsrEtriggerVu.
  */
 #define CSR_ETRIGGER_NMI_OFFSET             10
 #define CSR_ETRIGGER_NMI_LENGTH             1
@@ -1361,10 +1363,15 @@
  * 1: This trigger will only match if the low bits of
  * \RcsrScontext equal \FcsrTextraThirtytwoSvalue.
  *
- * 2: This trigger will only match if the currently active ASID
- * value, from either \Rsatp or \Rvsatp,
- * equals the lower ASIDMAX (defined in the Privileged Spec) bits of
+ * 2: This trigger will only match if:
+ * \begin{itemize}[noitemsep,nolistsep]
+ * \item the mode is VS-mode or VU-mode and ASID in \Rvsatp
+ * equals the lower ASIDMAX (defined in the Privileged Spec) bits
+ * of \FcsrTextraThirtytwoSvalue.
+ * \item in all other modes, ASID in \Rsatp equals the lower
+ * ASIDMAX (defined in the Privileged Spec) bits of
  * \FcsrTextraThirtytwoSvalue.
+ * \end{itemize}
  *
  * This field should be tied to 0 when S-mode is not supported.
  */

diff --git a/src/target/riscv/encoding.h b/src/target/riscv/encoding.h
index 4a035e2885256a42f6f1babaf07d04aaf865039e..4445f0bd2eb3414aa9e1074ff6cacf0c76c36f36 100644 (file)
--- a/src/target/riscv/encoding.h
+++ b/src/target/riscv/encoding.h
@@ -1,6 +1,6 @@
 /*
  * This file is auto-generated by running 'make ../riscv-openocd/src/target/riscv/encoding.h' in
- * https://github.com/riscv/riscv-opcodes (876ee63)
+ * https://github.com/riscv/riscv-opcodes (6c34f60)
  */
 
 /* See LICENSE for license details. */
@@ -14,7 +14,7 @@
 #define MSTATUS_MIE         0x00000008
 #define MSTATUS_UPIE        0x00000010
 #define MSTATUS_SPIE        0x00000020
-#define MSTATUS_HPIE        0x00000040
+#define MSTATUS_UBE         0x00000040
 #define MSTATUS_MPIE        0x00000080
 #define MSTATUS_SPP         0x00000100
 #define MSTATUS_VS          0x00000600
@@ -30,14 +30,22 @@
 #define MSTATUS32_SD        0x80000000
 #define MSTATUS_UXL         0x0000000300000000
 #define MSTATUS_SXL         0x0000000C00000000
+#define MSTATUS_SBE         0x0000001000000000
+#define MSTATUS_MBE         0x0000002000000000
 #define MSTATUS_GVA         0x0000004000000000
 #define MSTATUS_MPV         0x0000008000000000
 #define MSTATUS64_SD        0x8000000000000000
 
+#define MSTATUSH_SBE        0x00000010
+#define MSTATUSH_MBE        0x00000020
+#define MSTATUSH_GVA        0x00000040
+#define MSTATUSH_MPV        0x00000080
+
 #define SSTATUS_UIE         0x00000001
 #define SSTATUS_SIE         0x00000002
 #define SSTATUS_UPIE        0x00000010
 #define SSTATUS_SPIE        0x00000020
+#define SSTATUS_UBE         0x00000040
 #define SSTATUS_SPP         0x00000100
 #define SSTATUS_VS          0x00000600
 #define SSTATUS_FS          0x00006000
@@ -48,10 +56,6 @@
 #define SSTATUS_UXL         0x0000000300000000
 #define SSTATUS64_SD        0x8000000000000000
 
-#define SSTATUS_VS_MASK     (SSTATUS_SIE | SSTATUS_SPIE | \
-                                                        SSTATUS_SPP | SSTATUS_SUM | \
-                                                        SSTATUS_MXR | SSTATUS_UXL)
-
 #define HSTATUS_VSXL        0x300000000
 #define HSTATUS_VTSR        0x00400000
 #define HSTATUS_VTW         0x00200000
@@ -205,12 +209,6 @@
 #define IRQ_COP      12
 #define IRQ_HOST     13
 
-#define DEFAULT_RSTVEC     0x00001000
-#define CLINT_BASE         0x02000000
-#define CLINT_SIZE         0x000c0000
-#define EXT_IO_BASE        0x40000000
-#define DRAM_BASE          0x80000000
-
 /* page table entry (PTE) fields */
 #define PTE_V     0x001 /* Valid */
 #define PTE_R     0x002 /* Read */
@@ -221,6 +219,10 @@
 #define PTE_A     0x040 /* Accessed */
 #define PTE_D     0x080 /* Dirty */
 #define PTE_SOFT  0x300 /* Reserved for Software */
+#define PTE_RSVD  0x1FC0000000000000 /* Reserved for future standard use */
+#define PTE_PBMT  0x6000000000000000 /* Svpbmt: Page-based memory types */
+#define PTE_N     0x8000000000000000 /* Svnapot: NAPOT translation contiguity */
+#define PTE_ATTR  0xFFC0000000000000 /* All attributes and reserved bits */
 
 #define PTE_PPN_SHIFT 10
 
@@ -347,18 +349,12 @@
 #define MASK_AUIPC  0x7f
 #define MATCH_ADDI 0x13
 #define MASK_ADDI  0x707f
-#define MATCH_SLLI 0x1013
-#define MASK_SLLI  0xfc00707f
 #define MATCH_SLTI 0x2013
 #define MASK_SLTI  0x707f
 #define MATCH_SLTIU 0x3013
 #define MASK_SLTIU  0x707f
 #define MATCH_XORI 0x4013
 #define MASK_XORI  0x707f
-#define MATCH_SRLI 0x5013
-#define MASK_SRLI  0xfc00707f
-#define MATCH_SRAI 0x40005013
-#define MASK_SRAI  0xfc00707f
 #define MATCH_ORI 0x6013
 #define MASK_ORI  0x707f
 #define MATCH_ANDI 0x7013
@@ -427,6 +423,12 @@
 #define MASK_LWU  0x707f
 #define MATCH_SD 0x3023
 #define MASK_SD  0x707f
+#define MATCH_SLLI 0x1013
+#define MASK_SLLI  0xfc00707f
+#define MATCH_SRLI 0x5013
+#define MASK_SRLI  0xfc00707f
+#define MATCH_SRAI 0x40005013
+#define MASK_SRAI  0xfc00707f
 #define MATCH_MUL 0x2000033
 #define MASK_MUL  0xfe00707f
 #define MATCH_MULH 0x2001033
@@ -715,12 +717,216 @@
 #define MASK_FCVT_Q_L  0xfff0007f
 #define MATCH_FCVT_Q_LU 0xd6300053
 #define MASK_FCVT_Q_LU  0xfff0007f
+#define MATCH_ANDN 0x40007033
+#define MASK_ANDN  0xfe00707f
+#define MATCH_ORN 0x40006033
+#define MASK_ORN  0xfe00707f
+#define MATCH_XNOR 0x40004033
+#define MASK_XNOR  0xfe00707f
+#define MATCH_SLO 0x20001033
+#define MASK_SLO  0xfe00707f
+#define MATCH_SRO 0x20005033
+#define MASK_SRO  0xfe00707f
+#define MATCH_ROL 0x60001033
+#define MASK_ROL  0xfe00707f
+#define MATCH_ROR 0x60005033
+#define MASK_ROR  0xfe00707f
+#define MATCH_BCLR 0x48001033
+#define MASK_BCLR  0xfe00707f
+#define MATCH_BSET 0x28001033
+#define MASK_BSET  0xfe00707f
+#define MATCH_BINV 0x68001033
+#define MASK_BINV  0xfe00707f
+#define MATCH_BEXT 0x48005033
+#define MASK_BEXT  0xfe00707f
+#define MATCH_GORC 0x28005033
+#define MASK_GORC  0xfe00707f
+#define MATCH_GREV 0x68005033
+#define MASK_GREV  0xfe00707f
+#define MATCH_SLOI 0x20001013
+#define MASK_SLOI  0xfc00707f
+#define MATCH_SROI 0x20005013
+#define MASK_SROI  0xfc00707f
+#define MATCH_RORI 0x60005013
+#define MASK_RORI  0xfc00707f
+#define MATCH_BCLRI 0x48001013
+#define MASK_BCLRI  0xfc00707f
+#define MATCH_BSETI 0x28001013
+#define MASK_BSETI  0xfc00707f
+#define MATCH_BINVI 0x68001013
+#define MASK_BINVI  0xfc00707f
+#define MATCH_BEXTI 0x48005013
+#define MASK_BEXTI  0xfc00707f
+#define MATCH_GORCI 0x28005013
+#define MASK_GORCI  0xfc00707f
+#define MATCH_GREVI 0x68005013
+#define MASK_GREVI  0xfc00707f
+#define MATCH_CMIX 0x6001033
+#define MASK_CMIX  0x600707f
+#define MATCH_CMOV 0x6005033
+#define MASK_CMOV  0x600707f
+#define MATCH_FSL 0x4001033
+#define MASK_FSL  0x600707f
+#define MATCH_FSR 0x4005033
+#define MASK_FSR  0x600707f
+#define MATCH_FSRI 0x4005013
+#define MASK_FSRI  0x400707f
+#define MATCH_CLZ 0x60001013
+#define MASK_CLZ  0xfff0707f
+#define MATCH_CTZ 0x60101013
+#define MASK_CTZ  0xfff0707f
+#define MATCH_CPOP 0x60201013
+#define MASK_CPOP  0xfff0707f
+#define MATCH_SEXT_B 0x60401013
+#define MASK_SEXT_B  0xfff0707f
+#define MATCH_SEXT_H 0x60501013
+#define MASK_SEXT_H  0xfff0707f
+#define MATCH_CRC32_B 0x61001013
+#define MASK_CRC32_B  0xfff0707f
+#define MATCH_CRC32_H 0x61101013
+#define MASK_CRC32_H  0xfff0707f
+#define MATCH_CRC32_W 0x61201013
+#define MASK_CRC32_W  0xfff0707f
+#define MATCH_CRC32C_B 0x61801013
+#define MASK_CRC32C_B  0xfff0707f
+#define MATCH_CRC32C_H 0x61901013
+#define MASK_CRC32C_H  0xfff0707f
+#define MATCH_CRC32C_W 0x61a01013
+#define MASK_CRC32C_W  0xfff0707f
+#define MATCH_SH1ADD 0x20002033
+#define MASK_SH1ADD  0xfe00707f
+#define MATCH_SH2ADD 0x20004033
+#define MASK_SH2ADD  0xfe00707f
+#define MATCH_SH3ADD 0x20006033
+#define MASK_SH3ADD  0xfe00707f
+#define MATCH_CLMUL 0xa001033
+#define MASK_CLMUL  0xfe00707f
+#define MATCH_CLMULR 0xa002033
+#define MASK_CLMULR  0xfe00707f
+#define MATCH_CLMULH 0xa003033
+#define MASK_CLMULH  0xfe00707f
+#define MATCH_MIN 0xa004033
+#define MASK_MIN  0xfe00707f
+#define MATCH_MINU 0xa005033
+#define MASK_MINU  0xfe00707f
+#define MATCH_MAX 0xa006033
+#define MASK_MAX  0xfe00707f
+#define MATCH_MAXU 0xa007033
+#define MASK_MAXU  0xfe00707f
+#define MATCH_SHFL 0x8001033
+#define MASK_SHFL  0xfe00707f
+#define MATCH_UNSHFL 0x8005033
+#define MASK_UNSHFL  0xfe00707f
+#define MATCH_BCOMPRESS 0x8006033
+#define MASK_BCOMPRESS  0xfe00707f
+#define MATCH_BDECOMPRESS 0x48006033
+#define MASK_BDECOMPRESS  0xfe00707f
+#define MATCH_PACK 0x8004033
+#define MASK_PACK  0xfe00707f
+#define MATCH_PACKU 0x48004033
+#define MASK_PACKU  0xfe00707f
+#define MATCH_PACKH 0x8007033
+#define MASK_PACKH  0xfe00707f
+#define MATCH_BFP 0x48007033
+#define MASK_BFP  0xfe00707f
+#define MATCH_SHFLI 0x8001013
+#define MASK_SHFLI  0xfe00707f
+#define MATCH_UNSHFLI 0x8005013
+#define MASK_UNSHFLI  0xfe00707f
+#define MATCH_XPERM4 0x28002033
+#define MASK_XPERM4  0xfe00707f
+#define MATCH_XPERM8 0x28004033
+#define MASK_XPERM8  0xfe00707f
+#define MATCH_XPERM16 0x28006033
+#define MASK_XPERM16  0xfe00707f
+#define MATCH_BMATFLIP 0x60301013
+#define MASK_BMATFLIP  0xfff0707f
+#define MATCH_CRC32_D 0x61301013
+#define MASK_CRC32_D  0xfff0707f
+#define MATCH_CRC32C_D 0x61b01013
+#define MASK_CRC32C_D  0xfff0707f
+#define MATCH_BMATOR 0x8003033
+#define MASK_BMATOR  0xfe00707f
+#define MATCH_BMATXOR 0x48003033
+#define MASK_BMATXOR  0xfe00707f
+#define MATCH_SLLI_UW 0x800101b
+#define MASK_SLLI_UW  0xfc00707f
+#define MATCH_ADD_UW 0x800003b
+#define MASK_ADD_UW  0xfe00707f
+#define MATCH_SLOW 0x2000103b
+#define MASK_SLOW  0xfe00707f
+#define MATCH_SROW 0x2000503b
+#define MASK_SROW  0xfe00707f
+#define MATCH_ROLW 0x6000103b
+#define MASK_ROLW  0xfe00707f
+#define MATCH_RORW 0x6000503b
+#define MASK_RORW  0xfe00707f
+#define MATCH_SBCLRW 0x4800103b
+#define MASK_SBCLRW  0xfe00707f
+#define MATCH_SBSETW 0x2800103b
+#define MASK_SBSETW  0xfe00707f
+#define MATCH_SBINVW 0x6800103b
+#define MASK_SBINVW  0xfe00707f
+#define MATCH_SBEXTW 0x4800503b
+#define MASK_SBEXTW  0xfe00707f
+#define MATCH_GORCW 0x2800503b
+#define MASK_GORCW  0xfe00707f
+#define MATCH_GREVW 0x6800503b
+#define MASK_GREVW  0xfe00707f
+#define MATCH_SLOIW 0x2000101b
+#define MASK_SLOIW  0xfe00707f
+#define MATCH_SROIW 0x2000501b
+#define MASK_SROIW  0xfe00707f
+#define MATCH_RORIW 0x6000501b
+#define MASK_RORIW  0xfe00707f
+#define MATCH_SBCLRIW 0x4800101b
+#define MASK_SBCLRIW  0xfe00707f
+#define MATCH_SBSETIW 0x2800101b
+#define MASK_SBSETIW  0xfe00707f
+#define MATCH_SBINVIW 0x6800101b
+#define MASK_SBINVIW  0xfe00707f
+#define MATCH_GORCIW 0x2800501b
+#define MASK_GORCIW  0xfe00707f
+#define MATCH_GREVIW 0x6800501b
+#define MASK_GREVIW  0xfe00707f
+#define MATCH_FSLW 0x400103b
+#define MASK_FSLW  0x600707f
+#define MATCH_FSRW 0x400503b
+#define MASK_FSRW  0x600707f
+#define MATCH_FSRIW 0x400501b
+#define MASK_FSRIW  0x600707f
+#define MATCH_CLZW 0x6000101b
+#define MASK_CLZW  0xfff0707f
+#define MATCH_CTZW 0x6010101b
+#define MASK_CTZW  0xfff0707f
+#define MATCH_CPOPW 0x6020101b
+#define MASK_CPOPW  0xfff0707f
+#define MATCH_SH1ADD_UW 0x2000203b
+#define MASK_SH1ADD_UW  0xfe00707f
+#define MATCH_SH2ADD_UW 0x2000403b
+#define MASK_SH2ADD_UW  0xfe00707f
+#define MATCH_SH3ADD_UW 0x2000603b
+#define MASK_SH3ADD_UW  0xfe00707f
+#define MATCH_SHFLW 0x800103b
+#define MASK_SHFLW  0xfe00707f
+#define MATCH_UNSHFLW 0x800503b
+#define MASK_UNSHFLW  0xfe00707f
+#define MATCH_BCOMPRESSW 0x800603b
+#define MASK_BCOMPRESSW  0xfe00707f
+#define MATCH_BDECOMPRESSW 0x4800603b
+#define MASK_BDECOMPRESSW  0xfe00707f
+#define MATCH_PACKW 0x800403b
+#define MASK_PACKW  0xfe00707f
+#define MATCH_PACKUW 0x4800403b
+#define MASK_PACKUW  0xfe00707f
+#define MATCH_BFPW 0x4800703b
+#define MASK_BFPW  0xfe00707f
+#define MATCH_XPERM32 0x28000033
+#define MASK_XPERM32  0xfe00707f
 #define MATCH_ECALL 0x73
 #define MASK_ECALL  0xffffffff
 #define MATCH_EBREAK 0x100073
 #define MASK_EBREAK  0xffffffff
-#define MATCH_URET 0x200073
-#define MASK_URET  0xffffffff
 #define MATCH_SRET 0x10200073
 #define MASK_SRET  0xffffffff
 #define MATCH_MRET 0x30200073
@@ -743,6 +949,146 @@
 #define MASK_CSRRSI  0x707f
 #define MATCH_CSRRCI 0x7073
 #define MASK_CSRRCI  0x707f
+#define MATCH_SINVAL_VMA 0x16000073
+#define MASK_SINVAL_VMA  0xfe007fff
+#define MATCH_SFENCE_W_INVAL 0x18000073
+#define MASK_SFENCE_W_INVAL  0xffffffff
+#define MATCH_SFENCE_INVAL_IR 0x18100073
+#define MASK_SFENCE_INVAL_IR  0xffffffff
+#define MATCH_HINVAL_VVMA 0x36000073
+#define MASK_HINVAL_VVMA  0xfe007fff
+#define MATCH_HINVAL_GVMA 0x76000073
+#define MASK_HINVAL_GVMA  0xfe007fff
+#define MATCH_FADD_H 0x4000053
+#define MASK_FADD_H  0xfe00007f
+#define MATCH_FSUB_H 0xc000053
+#define MASK_FSUB_H  0xfe00007f
+#define MATCH_FMUL_H 0x14000053
+#define MASK_FMUL_H  0xfe00007f
+#define MATCH_FDIV_H 0x1c000053
+#define MASK_FDIV_H  0xfe00007f
+#define MATCH_FSGNJ_H 0x24000053
+#define MASK_FSGNJ_H  0xfe00707f
+#define MATCH_FSGNJN_H 0x24001053
+#define MASK_FSGNJN_H  0xfe00707f
+#define MATCH_FSGNJX_H 0x24002053
+#define MASK_FSGNJX_H  0xfe00707f
+#define MATCH_FMIN_H 0x2c000053
+#define MASK_FMIN_H  0xfe00707f
+#define MATCH_FMAX_H 0x2c001053
+#define MASK_FMAX_H  0xfe00707f
+#define MATCH_FCVT_H_S 0x44000053
+#define MASK_FCVT_H_S  0xfff0007f
+#define MATCH_FCVT_S_H 0x40200053
+#define MASK_FCVT_S_H  0xfff0007f
+#define MATCH_FSQRT_H 0x5c000053
+#define MASK_FSQRT_H  0xfff0007f
+#define MATCH_FLE_H 0xa4000053
+#define MASK_FLE_H  0xfe00707f
+#define MATCH_FLT_H 0xa4001053
+#define MASK_FLT_H  0xfe00707f
+#define MATCH_FEQ_H 0xa4002053
+#define MASK_FEQ_H  0xfe00707f
+#define MATCH_FCVT_W_H 0xc4000053
+#define MASK_FCVT_W_H  0xfff0007f
+#define MATCH_FCVT_WU_H 0xc4100053
+#define MASK_FCVT_WU_H  0xfff0007f
+#define MATCH_FMV_X_H 0xe4000053
+#define MASK_FMV_X_H  0xfff0707f
+#define MATCH_FCLASS_H 0xe4001053
+#define MASK_FCLASS_H  0xfff0707f
+#define MATCH_FCVT_H_W 0xd4000053
+#define MASK_FCVT_H_W  0xfff0007f
+#define MATCH_FCVT_H_WU 0xd4100053
+#define MASK_FCVT_H_WU  0xfff0007f
+#define MATCH_FMV_H_X 0xf4000053
+#define MASK_FMV_H_X  0xfff0707f
+#define MATCH_FLH 0x1007
+#define MASK_FLH  0x707f
+#define MATCH_FSH 0x1027
+#define MASK_FSH  0x707f
+#define MATCH_FMADD_H 0x4000043
+#define MASK_FMADD_H  0x600007f
+#define MATCH_FMSUB_H 0x4000047
+#define MASK_FMSUB_H  0x600007f
+#define MATCH_FNMSUB_H 0x400004b
+#define MASK_FNMSUB_H  0x600007f
+#define MATCH_FNMADD_H 0x400004f
+#define MASK_FNMADD_H  0x600007f
+#define MATCH_FCVT_H_D 0x44100053
+#define MASK_FCVT_H_D  0xfff0007f
+#define MATCH_FCVT_D_H 0x42200053
+#define MASK_FCVT_D_H  0xfff0007f
+#define MATCH_FCVT_H_Q 0x44300053
+#define MASK_FCVT_H_Q  0xfff0007f
+#define MATCH_FCVT_Q_H 0x46200053
+#define MASK_FCVT_Q_H  0xfff0007f
+#define MATCH_FCVT_L_H 0xc4200053
+#define MASK_FCVT_L_H  0xfff0007f
+#define MATCH_FCVT_LU_H 0xc4300053
+#define MASK_FCVT_LU_H  0xfff0007f
+#define MATCH_FCVT_H_L 0xd4200053
+#define MASK_FCVT_H_L  0xfff0007f
+#define MATCH_FCVT_H_LU 0xd4300053
+#define MASK_FCVT_H_LU  0xfff0007f
+#define MATCH_SM4ED 0x30000033
+#define MASK_SM4ED  0x3e00707f
+#define MATCH_SM4KS 0x34000033
+#define MASK_SM4KS  0x3e00707f
+#define MATCH_SM3P0 0x10801013
+#define MASK_SM3P0  0xfff0707f
+#define MATCH_SM3P1 0x10901013
+#define MASK_SM3P1  0xfff0707f
+#define MATCH_SHA256SUM0 0x10001013
+#define MASK_SHA256SUM0  0xfff0707f
+#define MATCH_SHA256SUM1 0x10101013
+#define MASK_SHA256SUM1  0xfff0707f
+#define MATCH_SHA256SIG0 0x10201013
+#define MASK_SHA256SIG0  0xfff0707f
+#define MATCH_SHA256SIG1 0x10301013
+#define MASK_SHA256SIG1  0xfff0707f
+#define MATCH_AES32ESMI 0x26000033
+#define MASK_AES32ESMI  0x3e00707f
+#define MATCH_AES32ESI 0x22000033
+#define MASK_AES32ESI  0x3e00707f
+#define MATCH_AES32DSMI 0x2e000033
+#define MASK_AES32DSMI  0x3e00707f
+#define MATCH_AES32DSI 0x2a000033
+#define MASK_AES32DSI  0x3e00707f
+#define MATCH_SHA512SUM0R 0x50000033
+#define MASK_SHA512SUM0R  0xfe00707f
+#define MATCH_SHA512SUM1R 0x52000033
+#define MASK_SHA512SUM1R  0xfe00707f
+#define MATCH_SHA512SIG0L 0x54000033
+#define MASK_SHA512SIG0L  0xfe00707f
+#define MATCH_SHA512SIG0H 0x5c000033
+#define MASK_SHA512SIG0H  0xfe00707f
+#define MATCH_SHA512SIG1L 0x56000033
+#define MASK_SHA512SIG1L  0xfe00707f
+#define MATCH_SHA512SIG1H 0x5e000033
+#define MASK_SHA512SIG1H  0xfe00707f
+#define MATCH_AES64KS1I 0x31001013
+#define MASK_AES64KS1I  0xff00707f
+#define MATCH_AES64IM 0x30001013
+#define MASK_AES64IM  0xfff0707f
+#define MATCH_AES64KS2 0x7e000033
+#define MASK_AES64KS2  0xfe00707f
+#define MATCH_AES64ESM 0x36000033
+#define MASK_AES64ESM  0xfe00707f
+#define MATCH_AES64ES 0x32000033
+#define MASK_AES64ES  0xfe00707f
+#define MATCH_AES64DSM 0x3e000033
+#define MASK_AES64DSM  0xfe00707f
+#define MATCH_AES64DS 0x3a000033
+#define MASK_AES64DS  0xfe00707f
+#define MATCH_SHA512SUM0 0x10401013
+#define MASK_SHA512SUM0  0xfff0707f
+#define MATCH_SHA512SUM1 0x10501013
+#define MASK_SHA512SUM1  0xfff0707f
+#define MATCH_SHA512SIG0 0x10601013
+#define MASK_SHA512SIG0  0xfff0707f
+#define MATCH_SHA512SIG1 0x10701013
+#define MASK_SHA512SIG1  0xfff0707f
 #define MATCH_C_NOP 0x1
 #define MASK_C_NOP  0xffff
 #define MATCH_C_ADDI16SP 0x6101
@@ -881,10 +1227,16 @@
 #define MASK_CUSTOM3_RD_RS1  0x707f
 #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
 #define MASK_CUSTOM3_RD_RS1_RS2  0x707f
+#define MATCH_VSETIVLI 0xc0007057
+#define MASK_VSETIVLI  0xc000707f
 #define MATCH_VSETVLI 0x7057
 #define MASK_VSETVLI  0x8000707f
 #define MATCH_VSETVL 0x80007057
 #define MASK_VSETVL  0xfe00707f
+#define MATCH_VLM_V 0x2b00007
+#define MASK_VLM_V  0xfff0707f
+#define MATCH_VSM_V 0x2b00027
+#define MASK_VSM_V  0xfff0707f
 #define MATCH_VLE8_V 0x7
 #define MASK_VLE8_V  0x1df0707f
 #define MATCH_VLE16_V 0x5007
@@ -917,6 +1269,38 @@
 #define MASK_VSE512_V  0x1df0707f
 #define MATCH_VSE1024_V 0x10007027
 #define MASK_VSE1024_V  0x1df0707f
+#define MATCH_VLUXEI8_V 0x4000007
+#define MASK_VLUXEI8_V  0x1c00707f
+#define MATCH_VLUXEI16_V 0x4005007
+#define MASK_VLUXEI16_V  0x1c00707f
+#define MATCH_VLUXEI32_V 0x4006007
+#define MASK_VLUXEI32_V  0x1c00707f
+#define MATCH_VLUXEI64_V 0x4007007
+#define MASK_VLUXEI64_V  0x1c00707f
+#define MATCH_VLUXEI128_V 0x14000007
+#define MASK_VLUXEI128_V  0x1c00707f
+#define MATCH_VLUXEI256_V 0x14005007
+#define MASK_VLUXEI256_V  0x1c00707f
+#define MATCH_VLUXEI512_V 0x14006007
+#define MASK_VLUXEI512_V  0x1c00707f
+#define MATCH_VLUXEI1024_V 0x14007007
+#define MASK_VLUXEI1024_V  0x1c00707f
+#define MATCH_VSUXEI8_V 0x4000027
+#define MASK_VSUXEI8_V  0x1c00707f
+#define MATCH_VSUXEI16_V 0x4005027
+#define MASK_VSUXEI16_V  0x1c00707f
+#define MATCH_VSUXEI32_V 0x4006027
+#define MASK_VSUXEI32_V  0x1c00707f
+#define MATCH_VSUXEI64_V 0x4007027
+#define MASK_VSUXEI64_V  0x1c00707f
+#define MATCH_VSUXEI128_V 0x14000027
+#define MASK_VSUXEI128_V  0x1c00707f
+#define MATCH_VSUXEI256_V 0x14005027
+#define MASK_VSUXEI256_V  0x1c00707f
+#define MATCH_VSUXEI512_V 0x14006027
+#define MASK_VSUXEI512_V  0x1c00707f
+#define MATCH_VSUXEI1024_V 0x14007027
+#define MASK_VSUXEI1024_V  0x1c00707f
 #define MATCH_VLSE8_V 0x8000007
 #define MASK_VLSE8_V  0x1c00707f
 #define MATCH_VLSE16_V 0x8005007
@@ -949,54 +1333,38 @@
 #define MASK_VSSE512_V  0x1c00707f
 #define MATCH_VSSE1024_V 0x18007027
 #define MASK_VSSE1024_V  0x1c00707f
-#define MATCH_VLXEI8_V 0xc000007
-#define MASK_VLXEI8_V  0x1c00707f
-#define MATCH_VLXEI16_V 0xc005007
-#define MASK_VLXEI16_V  0x1c00707f
-#define MATCH_VLXEI32_V 0xc006007
-#define MASK_VLXEI32_V  0x1c00707f
-#define MATCH_VLXEI64_V 0xc007007
-#define MASK_VLXEI64_V  0x1c00707f
-#define MATCH_VLXEI128_V 0x1c000007
-#define MASK_VLXEI128_V  0x1c00707f
-#define MATCH_VLXEI256_V 0x1c005007
-#define MASK_VLXEI256_V  0x1c00707f
-#define MATCH_VLXEI512_V 0x1c006007
-#define MASK_VLXEI512_V  0x1c00707f
-#define MATCH_VLXEI1024_V 0x1c007007
-#define MASK_VLXEI1024_V  0x1c00707f
-#define MATCH_VSXEI8_V 0xc000027
-#define MASK_VSXEI8_V  0x1c00707f
-#define MATCH_VSXEI16_V 0xc005027
-#define MASK_VSXEI16_V  0x1c00707f
-#define MATCH_VSXEI32_V 0xc006027
-#define MASK_VSXEI32_V  0x1c00707f
-#define MATCH_VSXEI64_V 0xc007027
-#define MASK_VSXEI64_V  0x1c00707f
-#define MATCH_VSXEI128_V 0x1c000027
-#define MASK_VSXEI128_V  0x1c00707f
-#define MATCH_VSXEI256_V 0x1c005027
-#define MASK_VSXEI256_V  0x1c00707f
-#define MATCH_VSXEI512_V 0x1c006027
-#define MASK_VSXEI512_V  0x1c00707f
-#define MATCH_VSXEI1024_V 0x1c007027
-#define MASK_VSXEI1024_V  0x1c00707f
-#define MATCH_VSUXEI8_V 0x4000027
-#define MASK_VSUXEI8_V  0x1c00707f
-#define MATCH_VSUXEI16_V 0x4005027
-#define MASK_VSUXEI16_V  0x1c00707f
-#define MATCH_VSUXEI32_V 0x4006027
-#define MASK_VSUXEI32_V  0x1c00707f
-#define MATCH_VSUXEI64_V 0x4007027
-#define MASK_VSUXEI64_V  0x1c00707f
-#define MATCH_VSUXEI128_V 0x14000027
-#define MASK_VSUXEI128_V  0x1c00707f
-#define MATCH_VSUXEI256_V 0x14005027
-#define MASK_VSUXEI256_V  0x1c00707f
-#define MATCH_VSUXEI512_V 0x14006027
-#define MASK_VSUXEI512_V  0x1c00707f
-#define MATCH_VSUXEI1024_V 0x14007027
-#define MASK_VSUXEI1024_V  0x1c00707f
+#define MATCH_VLOXEI8_V 0xc000007
+#define MASK_VLOXEI8_V  0x1c00707f
+#define MATCH_VLOXEI16_V 0xc005007
+#define MASK_VLOXEI16_V  0x1c00707f
+#define MATCH_VLOXEI32_V 0xc006007
+#define MASK_VLOXEI32_V  0x1c00707f
+#define MATCH_VLOXEI64_V 0xc007007
+#define MASK_VLOXEI64_V  0x1c00707f
+#define MATCH_VLOXEI128_V 0x1c000007
+#define MASK_VLOXEI128_V  0x1c00707f
+#define MATCH_VLOXEI256_V 0x1c005007
+#define MASK_VLOXEI256_V  0x1c00707f
+#define MATCH_VLOXEI512_V 0x1c006007
+#define MASK_VLOXEI512_V  0x1c00707f
+#define MATCH_VLOXEI1024_V 0x1c007007
+#define MASK_VLOXEI1024_V  0x1c00707f
+#define MATCH_VSOXEI8_V 0xc000027
+#define MASK_VSOXEI8_V  0x1c00707f
+#define MATCH_VSOXEI16_V 0xc005027
+#define MASK_VSOXEI16_V  0x1c00707f
+#define MATCH_VSOXEI32_V 0xc006027
+#define MASK_VSOXEI32_V  0x1c00707f
+#define MATCH_VSOXEI64_V 0xc007027
+#define MASK_VSOXEI64_V  0x1c00707f
+#define MATCH_VSOXEI128_V 0x1c000027
+#define MASK_VSOXEI128_V  0x1c00707f
+#define MATCH_VSOXEI256_V 0x1c005027
+#define MASK_VSOXEI256_V  0x1c00707f
+#define MATCH_VSOXEI512_V 0x1c006027
+#define MASK_VSOXEI512_V  0x1c00707f
+#define MATCH_VSOXEI1024_V 0x1c007027
+#define MASK_VSOXEI1024_V  0x1c00707f
 #define MATCH_VLE8FF_V 0x1000007
 #define MASK_VLE8FF_V  0x1df0707f
 #define MATCH_VLE16FF_V 0x1005007
@@ -1133,8 +1501,8 @@
 #define MASK_VFWNMSAC_VF  0xfc00707f
 #define MATCH_VFADD_VV 0x1057
 #define MASK_VFADD_VV  0xfc00707f
-#define MATCH_VFREDSUM_VS 0x4001057
-#define MASK_VFREDSUM_VS  0xfc00707f
+#define MATCH_VFREDUSUM_VS 0x4001057
+#define MASK_VFREDUSUM_VS  0xfc00707f
 #define MATCH_VFSUB_VV 0x8001057
 #define MASK_VFSUB_VV  0xfc00707f
 #define MATCH_VFREDOSUM_VS 0xc001057
@@ -1227,12 +1595,16 @@
 #define MASK_VFNCVT_RTZ_X_F_W  0xfc0ff07f
 #define MATCH_VFSQRT_V 0x4c001057
 #define MASK_VFSQRT_V  0xfc0ff07f
+#define MATCH_VFRSQRT7_V 0x4c021057
+#define MASK_VFRSQRT7_V  0xfc0ff07f
+#define MATCH_VFREC7_V 0x4c029057
+#define MASK_VFREC7_V  0xfc0ff07f
 #define MATCH_VFCLASS_V 0x4c081057
 #define MASK_VFCLASS_V  0xfc0ff07f
 #define MATCH_VFWADD_VV 0xc0001057
 #define MASK_VFWADD_VV  0xfc00707f
-#define MATCH_VFWREDSUM_VS 0xc4001057
-#define MASK_VFWREDSUM_VS  0xfc00707f
+#define MATCH_VFWREDUSUM_VS 0xc4001057
+#define MASK_VFWREDUSUM_VS  0xfc00707f
 #define MATCH_VFWSUB_VV 0xc8001057
 #define MASK_VFWSUB_VV  0xfc00707f
 #define MATCH_VFWREDOSUM_VS 0xcc001057
@@ -1243,8 +1615,6 @@
 #define MASK_VFWSUB_WV  0xfc00707f
 #define MATCH_VFWMUL_VV 0xe0001057
 #define MASK_VFWMUL_VV  0xfc00707f
-#define MATCH_VFDOT_VV 0xe4001057
-#define MASK_VFDOT_VV  0xfc00707f
 #define MATCH_VFWMACC_VV 0xf0001057
 #define MASK_VFWMACC_VV  0xfc00707f
 #define MATCH_VFWNMACC_VV 0xf4001057
@@ -1282,11 +1652,15 @@
 #define MATCH_VADC_VXM 0x40004057
 #define MASK_VADC_VXM  0xfe00707f
 #define MATCH_VMADC_VXM 0x44004057
-#define MASK_VMADC_VXM  0xfc00707f
+#define MASK_VMADC_VXM  0xfe00707f
+#define MATCH_VMADC_VX 0x46004057
+#define MASK_VMADC_VX  0xfe00707f
 #define MATCH_VSBC_VXM 0x48004057
 #define MASK_VSBC_VXM  0xfe00707f
 #define MATCH_VMSBC_VXM 0x4c004057
-#define MASK_VMSBC_VXM  0xfc00707f
+#define MASK_VMSBC_VXM  0xfe00707f
+#define MATCH_VMSBC_VX 0x4e004057
+#define MASK_VMSBC_VX  0xfe00707f
 #define MATCH_VMERGE_VXM 0x5c004057
 #define MASK_VMERGE_VXM  0xfe00707f
 #define MATCH_VMV_V_X 0x5e004057
@@ -1335,14 +1709,6 @@
 #define MASK_VNCLIPU_WX  0xfc00707f
 #define MATCH_VNCLIP_WX 0xbc004057
 #define MASK_VNCLIP_WX  0xfc00707f
-#define MATCH_VQMACCU_VX 0xf0004057
-#define MASK_VQMACCU_VX  0xfc00707f
-#define MATCH_VQMACC_VX 0xf4004057
-#define MASK_VQMACC_VX  0xfc00707f
-#define MATCH_VQMACCUS_VX 0xf8004057
-#define MASK_VQMACCUS_VX  0xfc00707f
-#define MATCH_VQMACCSU_VX 0xfc004057
-#define MASK_VQMACCSU_VX  0xfc00707f
 #define MATCH_VADD_VV 0x57
 #define MASK_VADD_VV  0xfc00707f
 #define MATCH_VSUB_VV 0x8000057
@@ -1368,11 +1734,15 @@
 #define MATCH_VADC_VVM 0x40000057
 #define MASK_VADC_VVM  0xfe00707f
 #define MATCH_VMADC_VVM 0x44000057
-#define MASK_VMADC_VVM  0xfc00707f
+#define MASK_VMADC_VVM  0xfe00707f
+#define MATCH_VMADC_VV 0x46000057
+#define MASK_VMADC_VV  0xfe00707f
 #define MATCH_VSBC_VVM 0x48000057
 #define MASK_VSBC_VVM  0xfe00707f
 #define MATCH_VMSBC_VVM 0x4c000057
-#define MASK_VMSBC_VVM  0xfc00707f
+#define MASK_VMSBC_VVM  0xfe00707f
+#define MATCH_VMSBC_VV 0x4e000057
+#define MASK_VMSBC_VV  0xfe00707f
 #define MATCH_VMERGE_VVM 0x5c000057
 #define MASK_VMERGE_VVM  0xfe00707f
 #define MATCH_VMV_V_V 0x5e000057
@@ -1421,16 +1791,6 @@
 #define MASK_VWREDSUMU_VS  0xfc00707f
 #define MATCH_VWREDSUM_VS 0xc4000057
 #define MASK_VWREDSUM_VS  0xfc00707f
-#define MATCH_VDOTU_VV 0xe0000057
-#define MASK_VDOTU_VV  0xfc00707f
-#define MATCH_VDOT_VV 0xe4000057
-#define MASK_VDOT_VV  0xfc00707f
-#define MATCH_VQMACCU_VV 0xf0000057
-#define MASK_VQMACCU_VV  0xfc00707f
-#define MATCH_VQMACC_VV 0xf4000057
-#define MASK_VQMACC_VV  0xfc00707f
-#define MATCH_VQMACCSU_VV 0xfc000057
-#define MASK_VQMACCSU_VV  0xfc00707f
 #define MATCH_VADD_VI 0x3057
 #define MASK_VADD_VI  0xfc00707f
 #define MATCH_VRSUB_VI 0xc003057
@@ -1450,7 +1810,9 @@
 #define MATCH_VADC_VIM 0x40003057
 #define MASK_VADC_VIM  0xfe00707f
 #define MATCH_VMADC_VIM 0x44003057
-#define MASK_VMADC_VIM  0xfc00707f
+#define MASK_VMADC_VIM  0xfe00707f
+#define MATCH_VMADC_VI 0x46003057
+#define MASK_VMADC_VI  0xfe00707f
 #define MATCH_VMERGE_VIM 0x5c003057
 #define MASK_VMERGE_VIM  0xfe00707f
 #define MATCH_VMV_V_I 0x5e003057
@@ -1563,8 +1925,8 @@
 #define MASK_VIOTA_M  0xfc0ff07f
 #define MATCH_VID_V 0x5008a057
 #define MASK_VID_V  0xfdfff07f
-#define MATCH_VPOPC_M 0x40082057
-#define MASK_VPOPC_M  0xfc0ff07f
+#define MATCH_VCPOP_M 0x40082057
+#define MASK_VCPOP_M  0xfc0ff07f
 #define MATCH_VFIRST_M 0x4008a057
 #define MASK_VFIRST_M  0xfc0ff07f
 #define MATCH_VDIVU_VV 0x80002057
@@ -1759,6 +2121,658 @@
 #define MASK_VAMOMINUEI64_V  0xf800707f
 #define MATCH_VAMOMAXUEI64_V 0xe000702f
 #define MASK_VAMOMAXUEI64_V  0xf800707f
+#define MATCH_ADD8 0x48000077
+#define MASK_ADD8  0xfe00707f
+#define MATCH_ADD16 0x40000077
+#define MASK_ADD16  0xfe00707f
+#define MATCH_ADD64 0xc0001077
+#define MASK_ADD64  0xfe00707f
+#define MATCH_AVE 0xe0000077
+#define MASK_AVE  0xfe00707f
+#define MATCH_BITREV 0xe6000077
+#define MASK_BITREV  0xfe00707f
+#define MATCH_BITREVI 0xe8000077
+#define MASK_BITREVI  0xfc00707f
+#define MATCH_BPICK 0x3077
+#define MASK_BPICK  0x600707f
+#define MATCH_CLRS8 0xae000077
+#define MASK_CLRS8  0xfff0707f
+#define MATCH_CLRS16 0xae800077
+#define MASK_CLRS16  0xfff0707f
+#define MATCH_CLRS32 0xaf800077
+#define MASK_CLRS32  0xfff0707f
+#define MATCH_CLO8 0xae300077
+#define MASK_CLO8  0xfff0707f
+#define MATCH_CLO16 0xaeb00077
+#define MASK_CLO16  0xfff0707f
+#define MATCH_CLO32 0xafb00077
+#define MASK_CLO32  0xfff0707f
+#define MATCH_CLZ8 0xae100077
+#define MASK_CLZ8  0xfff0707f
+#define MATCH_CLZ16 0xae900077
+#define MASK_CLZ16  0xfff0707f
+#define MATCH_CLZ32 0xaf900077
+#define MASK_CLZ32  0xfff0707f
+#define MATCH_CMPEQ8 0x4e000077
+#define MASK_CMPEQ8  0xfe00707f
+#define MATCH_CMPEQ16 0x4c000077
+#define MASK_CMPEQ16  0xfe00707f
+#define MATCH_CRAS16 0x44000077
+#define MASK_CRAS16  0xfe00707f
+#define MATCH_CRSA16 0x46000077
+#define MASK_CRSA16  0xfe00707f
+#define MATCH_INSB 0xac000077
+#define MASK_INSB  0xff80707f
+#define MATCH_KABS8 0xad000077
+#define MASK_KABS8  0xfff0707f
+#define MATCH_KABS16 0xad100077
+#define MASK_KABS16  0xfff0707f
+#define MATCH_KABSW 0xad400077
+#define MASK_KABSW  0xfff0707f
+#define MATCH_KADD8 0x18000077
+#define MASK_KADD8  0xfe00707f
+#define MATCH_KADD16 0x10000077
+#define MASK_KADD16  0xfe00707f
+#define MATCH_KADD64 0x90001077
+#define MASK_KADD64  0xfe00707f
+#define MATCH_KADDH 0x4001077
+#define MASK_KADDH  0xfe00707f
+#define MATCH_KADDW 0x1077
+#define MASK_KADDW  0xfe00707f
+#define MATCH_KCRAS16 0x14000077
+#define MASK_KCRAS16  0xfe00707f
+#define MATCH_KCRSA16 0x16000077
+#define MASK_KCRSA16  0xfe00707f
+#define MATCH_KDMBB 0xa001077
+#define MASK_KDMBB  0xfe00707f
+#define MATCH_KDMBT 0x1a001077
+#define MASK_KDMBT  0xfe00707f
+#define MATCH_KDMTT 0x2a001077
+#define MASK_KDMTT  0xfe00707f
+#define MATCH_KDMABB 0xd2001077
+#define MASK_KDMABB  0xfe00707f
+#define MATCH_KDMABT 0xe2001077
+#define MASK_KDMABT  0xfe00707f
+#define MATCH_KDMATT 0xf2001077
+#define MASK_KDMATT  0xfe00707f
+#define MATCH_KHM8 0x8e000077
+#define MASK_KHM8  0xfe00707f
+#define MATCH_KHMX8 0x9e000077
+#define MASK_KHMX8  0xfe00707f
+#define MATCH_KHM16 0x86000077
+#define MASK_KHM16  0xfe00707f
+#define MATCH_KHMX16 0x96000077
+#define MASK_KHMX16  0xfe00707f
+#define MATCH_KHMBB 0xc001077
+#define MASK_KHMBB  0xfe00707f
+#define MATCH_KHMBT 0x1c001077
+#define MASK_KHMBT  0xfe00707f
+#define MATCH_KHMTT 0x2c001077
+#define MASK_KHMTT  0xfe00707f
+#define MATCH_KMABB 0x5a001077
+#define MASK_KMABB  0xfe00707f
+#define MATCH_KMABT 0x6a001077
+#define MASK_KMABT  0xfe00707f
+#define MATCH_KMATT 0x7a001077
+#define MASK_KMATT  0xfe00707f
+#define MATCH_KMADA 0x48001077
+#define MASK_KMADA  0xfe00707f
+#define MATCH_KMAXDA 0x4a001077
+#define MASK_KMAXDA  0xfe00707f
+#define MATCH_KMADS 0x5c001077
+#define MASK_KMADS  0xfe00707f
+#define MATCH_KMADRS 0x6c001077
+#define MASK_KMADRS  0xfe00707f
+#define MATCH_KMAXDS 0x7c001077
+#define MASK_KMAXDS  0xfe00707f
+#define MATCH_KMAR64 0x94001077
+#define MASK_KMAR64  0xfe00707f
+#define MATCH_KMDA 0x38001077
+#define MASK_KMDA  0xfe00707f
+#define MATCH_KMXDA 0x3a001077
+#define MASK_KMXDA  0xfe00707f
+#define MATCH_KMMAC 0x60001077
+#define MASK_KMMAC  0xfe00707f
+#define MATCH_KMMAC_U 0x70001077
+#define MASK_KMMAC_U  0xfe00707f
+#define MATCH_KMMAWB 0x46001077
+#define MASK_KMMAWB  0xfe00707f
+#define MATCH_KMMAWB_U 0x56001077
+#define MASK_KMMAWB_U  0xfe00707f
+#define MATCH_KMMAWB2 0xce001077
+#define MASK_KMMAWB2  0xfe00707f
+#define MATCH_KMMAWB2_U 0xde001077
+#define MASK_KMMAWB2_U  0xfe00707f
+#define MATCH_KMMAWT 0x66001077
+#define MASK_KMMAWT  0xfe00707f
+#define MATCH_KMMAWT_U 0x76001077
+#define MASK_KMMAWT_U  0xfe00707f
+#define MATCH_KMMAWT2 0xee001077
+#define MASK_KMMAWT2  0xfe00707f
+#define MATCH_KMMAWT2_U 0xfe001077
+#define MASK_KMMAWT2_U  0xfe00707f
+#define MATCH_KMMSB 0x42001077
+#define MASK_KMMSB  0xfe00707f
+#define MATCH_KMMSB_U 0x52001077
+#define MASK_KMMSB_U  0xfe00707f
+#define MATCH_KMMWB2 0x8e001077
+#define MASK_KMMWB2  0xfe00707f
+#define MATCH_KMMWB2_U 0x9e001077
+#define MASK_KMMWB2_U  0xfe00707f
+#define MATCH_KMMWT2 0xae001077
+#define MASK_KMMWT2  0xfe00707f
+#define MATCH_KMMWT2_U 0xbe001077
+#define MASK_KMMWT2_U  0xfe00707f
+#define MATCH_KMSDA 0x4c001077
+#define MASK_KMSDA  0xfe00707f
+#define MATCH_KMSXDA 0x4e001077
+#define MASK_KMSXDA  0xfe00707f
+#define MATCH_KMSR64 0x96001077
+#define MASK_KMSR64  0xfe00707f
+#define MATCH_KSLLW 0x26001077
+#define MASK_KSLLW  0xfe00707f
+#define MATCH_KSLLIW 0x36001077
+#define MASK_KSLLIW  0xfe00707f
+#define MATCH_KSLL8 0x6c000077
+#define MASK_KSLL8  0xfe00707f
+#define MATCH_KSLLI8 0x7c800077
+#define MASK_KSLLI8  0xff80707f
+#define MATCH_KSLL16 0x64000077
+#define MASK_KSLL16  0xfe00707f
+#define MATCH_KSLLI16 0x75000077
+#define MASK_KSLLI16  0xff00707f
+#define MATCH_KSLRA8 0x5e000077
+#define MASK_KSLRA8  0xfe00707f
+#define MATCH_KSLRA8_U 0x6e000077
+#define MASK_KSLRA8_U  0xfe00707f
+#define MATCH_KSLRA16 0x56000077
+#define MASK_KSLRA16  0xfe00707f
+#define MATCH_KSLRA16_U 0x66000077
+#define MASK_KSLRA16_U  0xfe00707f
+#define MATCH_KSLRAW 0x6e001077
+#define MASK_KSLRAW  0xfe00707f
+#define MATCH_KSLRAW_U 0x7e001077
+#define MASK_KSLRAW_U  0xfe00707f
+#define MATCH_KSTAS16 0xc4002077
+#define MASK_KSTAS16  0xfe00707f
+#define MATCH_KSTSA16 0xc6002077
+#define MASK_KSTSA16  0xfe00707f
+#define MATCH_KSUB8 0x1a000077
+#define MASK_KSUB8  0xfe00707f
+#define MATCH_KSUB16 0x12000077
+#define MASK_KSUB16  0xfe00707f
+#define MATCH_KSUB64 0x92001077
+#define MASK_KSUB64  0xfe00707f
+#define MATCH_KSUBH 0x6001077
+#define MASK_KSUBH  0xfe00707f
+#define MATCH_KSUBW 0x2001077
+#define MASK_KSUBW  0xfe00707f
+#define MATCH_KWMMUL 0x62001077
+#define MASK_KWMMUL  0xfe00707f
+#define MATCH_KWMMUL_U 0x72001077
+#define MASK_KWMMUL_U  0xfe00707f
+#define MATCH_MADDR32 0xc4001077
+#define MASK_MADDR32  0xfe00707f
+#define MATCH_MAXW 0xf2000077
+#define MASK_MAXW  0xfe00707f
+#define MATCH_MINW 0xf0000077
+#define MASK_MINW  0xfe00707f
+#define MATCH_MSUBR32 0xc6001077
+#define MASK_MSUBR32  0xfe00707f
+#define MATCH_MULR64 0xf0001077
+#define MASK_MULR64  0xfe00707f
+#define MATCH_MULSR64 0xe0001077
+#define MASK_MULSR64  0xfe00707f
+#define MATCH_PBSAD 0xfc000077
+#define MASK_PBSAD  0xfe00707f
+#define MATCH_PBSADA 0xfe000077
+#define MASK_PBSADA  0xfe00707f
+#define MATCH_PKBB16 0xe001077
+#define MASK_PKBB16  0xfe00707f
+#define MATCH_PKBT16 0x1e001077
+#define MASK_PKBT16  0xfe00707f
+#define MATCH_PKTT16 0x2e001077
+#define MASK_PKTT16  0xfe00707f
+#define MATCH_PKTB16 0x3e001077
+#define MASK_PKTB16  0xfe00707f
+#define MATCH_RADD8 0x8000077
+#define MASK_RADD8  0xfe00707f
+#define MATCH_RADD16 0x77
+#define MASK_RADD16  0xfe00707f
+#define MATCH_RADD64 0x80001077
+#define MASK_RADD64  0xfe00707f
+#define MATCH_RADDW 0x20001077
+#define MASK_RADDW  0xfe00707f
+#define MATCH_RCRAS16 0x4000077
+#define MASK_RCRAS16  0xfe00707f
+#define MATCH_RCRSA16 0x6000077
+#define MASK_RCRSA16  0xfe00707f
+#define MATCH_RSTAS16 0xb4002077
+#define MASK_RSTAS16  0xfe00707f
+#define MATCH_RSTSA16 0xb6002077
+#define MASK_RSTSA16  0xfe00707f
+#define MATCH_RSUB8 0xa000077
+#define MASK_RSUB8  0xfe00707f
+#define MATCH_RSUB16 0x2000077
+#define MASK_RSUB16  0xfe00707f
+#define MATCH_RSUB64 0x82001077
+#define MASK_RSUB64  0xfe00707f
+#define MATCH_RSUBW 0x22001077
+#define MASK_RSUBW  0xfe00707f
+#define MATCH_SCLIP8 0x8c000077
+#define MASK_SCLIP8  0xff80707f
+#define MATCH_SCLIP16 0x84000077
+#define MASK_SCLIP16  0xff00707f
+#define MATCH_SCLIP32 0xe4000077
+#define MASK_SCLIP32  0xfe00707f
+#define MATCH_SCMPLE8 0x1e000077
+#define MASK_SCMPLE8  0xfe00707f
+#define MATCH_SCMPLE16 0x1c000077
+#define MASK_SCMPLE16  0xfe00707f
+#define MATCH_SCMPLT8 0xe000077
+#define MASK_SCMPLT8  0xfe00707f
+#define MATCH_SCMPLT16 0xc000077
+#define MASK_SCMPLT16  0xfe00707f
+#define MATCH_SLL8 0x5c000077
+#define MASK_SLL8  0xfe00707f
+#define MATCH_SLLI8 0x7c000077
+#define MASK_SLLI8  0xff80707f
+#define MATCH_SLL16 0x54000077
+#define MASK_SLL16  0xfe00707f
+#define MATCH_SLLI16 0x74000077
+#define MASK_SLLI16  0xff00707f
+#define MATCH_SMAL 0x5e001077
+#define MASK_SMAL  0xfe00707f
+#define MATCH_SMALBB 0x88001077
+#define MASK_SMALBB  0xfe00707f
+#define MATCH_SMALBT 0x98001077
+#define MASK_SMALBT  0xfe00707f
+#define MATCH_SMALTT 0xa8001077
+#define MASK_SMALTT  0xfe00707f
+#define MATCH_SMALDA 0x8c001077
+#define MASK_SMALDA  0xfe00707f
+#define MATCH_SMALXDA 0x9c001077
+#define MASK_SMALXDA  0xfe00707f
+#define MATCH_SMALDS 0x8a001077
+#define MASK_SMALDS  0xfe00707f
+#define MATCH_SMALDRS 0x9a001077
+#define MASK_SMALDRS  0xfe00707f
+#define MATCH_SMALXDS 0xaa001077
+#define MASK_SMALXDS  0xfe00707f
+#define MATCH_SMAR64 0x84001077
+#define MASK_SMAR64  0xfe00707f
+#define MATCH_SMAQA 0xc8000077
+#define MASK_SMAQA  0xfe00707f
+#define MATCH_SMAQA_SU 0xca000077
+#define MASK_SMAQA_SU  0xfe00707f
+#define MATCH_SMAX8 0x8a000077
+#define MASK_SMAX8  0xfe00707f
+#define MATCH_SMAX16 0x82000077
+#define MASK_SMAX16  0xfe00707f
+#define MATCH_SMBB16 0x8001077
+#define MASK_SMBB16  0xfe00707f
+#define MATCH_SMBT16 0x18001077
+#define MASK_SMBT16  0xfe00707f
+#define MATCH_SMTT16 0x28001077
+#define MASK_SMTT16  0xfe00707f
+#define MATCH_SMDS 0x58001077
+#define MASK_SMDS  0xfe00707f
+#define MATCH_SMDRS 0x68001077
+#define MASK_SMDRS  0xfe00707f
+#define MATCH_SMXDS 0x78001077
+#define MASK_SMXDS  0xfe00707f
+#define MATCH_SMIN8 0x88000077
+#define MASK_SMIN8  0xfe00707f
+#define MATCH_SMIN16 0x80000077
+#define MASK_SMIN16  0xfe00707f
+#define MATCH_SMMUL 0x40001077
+#define MASK_SMMUL  0xfe00707f
+#define MATCH_SMMUL_U 0x50001077
+#define MASK_SMMUL_U  0xfe00707f
+#define MATCH_SMMWB 0x44001077
+#define MASK_SMMWB  0xfe00707f
+#define MATCH_SMMWB_U 0x54001077
+#define MASK_SMMWB_U  0xfe00707f
+#define MATCH_SMMWT 0x64001077
+#define MASK_SMMWT  0xfe00707f
+#define MATCH_SMMWT_U 0x74001077
+#define MASK_SMMWT_U  0xfe00707f
+#define MATCH_SMSLDA 0xac001077
+#define MASK_SMSLDA  0xfe00707f
+#define MATCH_SMSLXDA 0xbc001077
+#define MASK_SMSLXDA  0xfe00707f
+#define MATCH_SMSR64 0x86001077
+#define MASK_SMSR64  0xfe00707f
+#define MATCH_SMUL8 0xa8000077
+#define MASK_SMUL8  0xfe00707f
+#define MATCH_SMULX8 0xaa000077
+#define MASK_SMULX8  0xfe00707f
+#define MATCH_SMUL16 0xa0000077
+#define MASK_SMUL16  0xfe00707f
+#define MATCH_SMULX16 0xa2000077
+#define MASK_SMULX16  0xfe00707f
+#define MATCH_SRA_U 0x24001077
+#define MASK_SRA_U  0xfe00707f
+#define MATCH_SRAI_U 0xd4001077
+#define MASK_SRAI_U  0xfc00707f
+#define MATCH_SRA8 0x58000077
+#define MASK_SRA8  0xfe00707f
+#define MATCH_SRA8_U 0x68000077
+#define MASK_SRA8_U  0xfe00707f
+#define MATCH_SRAI8 0x78000077
+#define MASK_SRAI8  0xff80707f
+#define MATCH_SRAI8_U 0x78800077
+#define MASK_SRAI8_U  0xff80707f
+#define MATCH_SRA16 0x50000077
+#define MASK_SRA16  0xfe00707f
+#define MATCH_SRA16_U 0x60000077
+#define MASK_SRA16_U  0xfe00707f
+#define MATCH_SRAI16 0x70000077
+#define MASK_SRAI16  0xff00707f
+#define MATCH_SRAI16_U 0x71000077
+#define MASK_SRAI16_U  0xff00707f
+#define MATCH_SRL8 0x5a000077
+#define MASK_SRL8  0xfe00707f
+#define MATCH_SRL8_U 0x6a000077
+#define MASK_SRL8_U  0xfe00707f
+#define MATCH_SRLI8 0x7a000077
+#define MASK_SRLI8  0xff80707f
+#define MATCH_SRLI8_U 0x7a800077
+#define MASK_SRLI8_U  0xff80707f
+#define MATCH_SRL16 0x52000077
+#define MASK_SRL16  0xfe00707f
+#define MATCH_SRL16_U 0x62000077
+#define MASK_SRL16_U  0xfe00707f
+#define MATCH_SRLI16 0x72000077
+#define MASK_SRLI16  0xff00707f
+#define MATCH_SRLI16_U 0x73000077
+#define MASK_SRLI16_U  0xff00707f
+#define MATCH_STAS16 0xf4002077
+#define MASK_STAS16  0xfe00707f
+#define MATCH_STSA16 0xf6002077
+#define MASK_STSA16  0xfe00707f
+#define MATCH_SUB8 0x4a000077
+#define MASK_SUB8  0xfe00707f
+#define MATCH_SUB16 0x42000077
+#define MASK_SUB16  0xfe00707f
+#define MATCH_SUB64 0xc2001077
+#define MASK_SUB64  0xfe00707f
+#define MATCH_SUNPKD810 0xac800077
+#define MASK_SUNPKD810  0xfff0707f
+#define MATCH_SUNPKD820 0xac900077
+#define MASK_SUNPKD820  0xfff0707f
+#define MATCH_SUNPKD830 0xaca00077
+#define MASK_SUNPKD830  0xfff0707f
+#define MATCH_SUNPKD831 0xacb00077
+#define MASK_SUNPKD831  0xfff0707f
+#define MATCH_SUNPKD832 0xad300077
+#define MASK_SUNPKD832  0xfff0707f
+#define MATCH_SWAP8 0xad800077
+#define MASK_SWAP8  0xfff0707f
+#define MATCH_UCLIP8 0x8d000077
+#define MASK_UCLIP8  0xff80707f
+#define MATCH_UCLIP16 0x85000077
+#define MASK_UCLIP16  0xff00707f
+#define MATCH_UCLIP32 0xf4000077
+#define MASK_UCLIP32  0xfe00707f
+#define MATCH_UCMPLE8 0x3e000077
+#define MASK_UCMPLE8  0xfe00707f
+#define MATCH_UCMPLE16 0x3c000077
+#define MASK_UCMPLE16  0xfe00707f
+#define MATCH_UCMPLT8 0x2e000077
+#define MASK_UCMPLT8  0xfe00707f
+#define MATCH_UCMPLT16 0x2c000077
+#define MASK_UCMPLT16  0xfe00707f
+#define MATCH_UKADD8 0x38000077
+#define MASK_UKADD8  0xfe00707f
+#define MATCH_UKADD16 0x30000077
+#define MASK_UKADD16  0xfe00707f
+#define MATCH_UKADD64 0xb0001077
+#define MASK_UKADD64  0xfe00707f
+#define MATCH_UKADDH 0x14001077
+#define MASK_UKADDH  0xfe00707f
+#define MATCH_UKADDW 0x10001077
+#define MASK_UKADDW  0xfe00707f
+#define MATCH_UKCRAS16 0x34000077
+#define MASK_UKCRAS16  0xfe00707f
+#define MATCH_UKCRSA16 0x36000077
+#define MASK_UKCRSA16  0xfe00707f
+#define MATCH_UKMAR64 0xb4001077
+#define MASK_UKMAR64  0xfe00707f
+#define MATCH_UKMSR64 0xb6001077
+#define MASK_UKMSR64  0xfe00707f
+#define MATCH_UKSTAS16 0xe4002077
+#define MASK_UKSTAS16  0xfe00707f
+#define MATCH_UKSTSA16 0xe6002077
+#define MASK_UKSTSA16  0xfe00707f
+#define MATCH_UKSUB8 0x3a000077
+#define MASK_UKSUB8  0xfe00707f
+#define MATCH_UKSUB16 0x32000077
+#define MASK_UKSUB16  0xfe00707f
+#define MATCH_UKSUB64 0xb2001077
+#define MASK_UKSUB64  0xfe00707f
+#define MATCH_UKSUBH 0x16001077
+#define MASK_UKSUBH  0xfe00707f
+#define MATCH_UKSUBW 0x12001077
+#define MASK_UKSUBW  0xfe00707f
+#define MATCH_UMAR64 0xa4001077
+#define MASK_UMAR64  0xfe00707f
+#define MATCH_UMAQA 0xcc000077
+#define MASK_UMAQA  0xfe00707f
+#define MATCH_UMAX8 0x9a000077
+#define MASK_UMAX8  0xfe00707f
+#define MATCH_UMAX16 0x92000077
+#define MASK_UMAX16  0xfe00707f
+#define MATCH_UMIN8 0x98000077
+#define MASK_UMIN8  0xfe00707f
+#define MATCH_UMIN16 0x90000077
+#define MASK_UMIN16  0xfe00707f
+#define MATCH_UMSR64 0xa6001077
+#define MASK_UMSR64  0xfe00707f
+#define MATCH_UMUL8 0xb8000077
+#define MASK_UMUL8  0xfe00707f
+#define MATCH_UMULX8 0xba000077
+#define MASK_UMULX8  0xfe00707f
+#define MATCH_UMUL16 0xb0000077
+#define MASK_UMUL16  0xfe00707f
+#define MATCH_UMULX16 0xb2000077
+#define MASK_UMULX16  0xfe00707f
+#define MATCH_URADD8 0x28000077
+#define MASK_URADD8  0xfe00707f
+#define MATCH_URADD16 0x20000077
+#define MASK_URADD16  0xfe00707f
+#define MATCH_URADD64 0xa0001077
+#define MASK_URADD64  0xfe00707f
+#define MATCH_URADDW 0x30001077
+#define MASK_URADDW  0xfe00707f
+#define MATCH_URCRAS16 0x24000077
+#define MASK_URCRAS16  0xfe00707f
+#define MATCH_URCRSA16 0x26000077
+#define MASK_URCRSA16  0xfe00707f
+#define MATCH_URSTAS16 0xd4002077
+#define MASK_URSTAS16  0xfe00707f
+#define MATCH_URSTSA16 0xd6002077
+#define MASK_URSTSA16  0xfe00707f
+#define MATCH_URSUB8 0x2a000077
+#define MASK_URSUB8  0xfe00707f
+#define MATCH_URSUB16 0x22000077
+#define MASK_URSUB16  0xfe00707f
+#define MATCH_URSUB64 0xa2001077
+#define MASK_URSUB64  0xfe00707f
+#define MATCH_URSUBW 0x32001077
+#define MASK_URSUBW  0xfe00707f
+#define MATCH_WEXTI 0xde000077
+#define MASK_WEXTI  0xfe00707f
+#define MATCH_WEXT 0xce000077
+#define MASK_WEXT  0xfe00707f
+#define MATCH_ZUNPKD810 0xacc00077
+#define MASK_ZUNPKD810  0xfff0707f
+#define MATCH_ZUNPKD820 0xacd00077
+#define MASK_ZUNPKD820  0xfff0707f
+#define MATCH_ZUNPKD830 0xace00077
+#define MASK_ZUNPKD830  0xfff0707f
+#define MATCH_ZUNPKD831 0xacf00077
+#define MASK_ZUNPKD831  0xfff0707f
+#define MATCH_ZUNPKD832 0xad700077
+#define MASK_ZUNPKD832  0xfff0707f
+#define MATCH_ADD32 0x40002077
+#define MASK_ADD32  0xfe00707f
+#define MATCH_CRAS32 0x44002077
+#define MASK_CRAS32  0xfe00707f
+#define MATCH_CRSA32 0x46002077
+#define MASK_CRSA32  0xfe00707f
+#define MATCH_KABS32 0xad200077
+#define MASK_KABS32  0xfff0707f
+#define MATCH_KADD32 0x10002077
+#define MASK_KADD32  0xfe00707f
+#define MATCH_KCRAS32 0x14002077
+#define MASK_KCRAS32  0xfe00707f
+#define MATCH_KCRSA32 0x16002077
+#define MASK_KCRSA32  0xfe00707f
+#define MATCH_KDMBB16 0xda001077
+#define MASK_KDMBB16  0xfe00707f
+#define MATCH_KDMBT16 0xea001077
+#define MASK_KDMBT16  0xfe00707f
+#define MATCH_KDMTT16 0xfa001077
+#define MASK_KDMTT16  0xfe00707f
+#define MATCH_KDMABB16 0xd8001077
+#define MASK_KDMABB16  0xfe00707f
+#define MATCH_KDMABT16 0xe8001077
+#define MASK_KDMABT16  0xfe00707f
+#define MATCH_KDMATT16 0xf8001077
+#define MASK_KDMATT16  0xfe00707f
+#define MATCH_KHMBB16 0xdc001077
+#define MASK_KHMBB16  0xfe00707f
+#define MATCH_KHMBT16 0xec001077
+#define MASK_KHMBT16  0xfe00707f
+#define MATCH_KHMTT16 0xfc001077
+#define MASK_KHMTT16  0xfe00707f
+#define MATCH_KMABB32 0x5a002077
+#define MASK_KMABB32  0xfe00707f
+#define MATCH_KMABT32 0x6a002077
+#define MASK_KMABT32  0xfe00707f
+#define MATCH_KMATT32 0x7a002077
+#define MASK_KMATT32  0xfe00707f
+#define MATCH_KMAXDA32 0x4a002077
+#define MASK_KMAXDA32  0xfe00707f
+#define MATCH_KMDA32 0x38002077
+#define MASK_KMDA32  0xfe00707f
+#define MATCH_KMXDA32 0x3a002077
+#define MASK_KMXDA32  0xfe00707f
+#define MATCH_KMADS32 0x5c002077
+#define MASK_KMADS32  0xfe00707f
+#define MATCH_KMADRS32 0x6c002077
+#define MASK_KMADRS32  0xfe00707f
+#define MATCH_KMAXDS32 0x7c002077
+#define MASK_KMAXDS32  0xfe00707f
+#define MATCH_KMSDA32 0x4c002077
+#define MASK_KMSDA32  0xfe00707f
+#define MATCH_KMSXDA32 0x4e002077
+#define MASK_KMSXDA32  0xfe00707f
+#define MATCH_KSLL32 0x64002077
+#define MASK_KSLL32  0xfe00707f
+#define MATCH_KSLLI32 0x84002077
+#define MASK_KSLLI32  0xfe00707f
+#define MATCH_KSLRA32 0x56002077
+#define MASK_KSLRA32  0xfe00707f
+#define MATCH_KSLRA32_U 0x66002077
+#define MASK_KSLRA32_U  0xfe00707f
+#define MATCH_KSTAS32 0xc0002077
+#define MASK_KSTAS32  0xfe00707f
+#define MATCH_KSTSA32 0xc2002077
+#define MASK_KSTSA32  0xfe00707f
+#define MATCH_KSUB32 0x12002077
+#define MASK_KSUB32  0xfe00707f
+#define MATCH_PKBB32 0xe002077
+#define MASK_PKBB32  0xfe00707f
+#define MATCH_PKBT32 0x1e002077
+#define MASK_PKBT32  0xfe00707f
+#define MATCH_PKTT32 0x2e002077
+#define MASK_PKTT32  0xfe00707f
+#define MATCH_PKTB32 0x3e002077
+#define MASK_PKTB32  0xfe00707f
+#define MATCH_RADD32 0x2077
+#define MASK_RADD32  0xfe00707f
+#define MATCH_RCRAS32 0x4002077
+#define MASK_RCRAS32  0xfe00707f
+#define MATCH_RCRSA32 0x6002077
+#define MASK_RCRSA32  0xfe00707f
+#define MATCH_RSTAS32 0xb0002077
+#define MASK_RSTAS32  0xfe00707f
+#define MATCH_RSTSA32 0xb2002077
+#define MASK_RSTSA32  0xfe00707f
+#define MATCH_RSUB32 0x2002077
+#define MASK_RSUB32  0xfe00707f
+#define MATCH_SLL32 0x54002077
+#define MASK_SLL32  0xfe00707f
+#define MATCH_SLLI32 0x74002077
+#define MASK_SLLI32  0xfe00707f
+#define MATCH_SMAX32 0x92002077
+#define MASK_SMAX32  0xfe00707f
+#define MATCH_SMBT32 0x18002077
+#define MASK_SMBT32  0xfe00707f
+#define MATCH_SMTT32 0x28002077
+#define MASK_SMTT32  0xfe00707f
+#define MATCH_SMDS32 0x58002077
+#define MASK_SMDS32  0xfe00707f
+#define MATCH_SMDRS32 0x68002077
+#define MASK_SMDRS32  0xfe00707f
+#define MATCH_SMXDS32 0x78002077
+#define MASK_SMXDS32  0xfe00707f
+#define MATCH_SMIN32 0x90002077
+#define MASK_SMIN32  0xfe00707f
+#define MATCH_SRA32 0x50002077
+#define MASK_SRA32  0xfe00707f
+#define MATCH_SRA32_U 0x60002077
+#define MASK_SRA32_U  0xfe00707f
+#define MATCH_SRAI32 0x70002077
+#define MASK_SRAI32  0xfe00707f
+#define MATCH_SRAI32_U 0x80002077
+#define MASK_SRAI32_U  0xfe00707f
+#define MATCH_SRAIW_U 0x34001077
+#define MASK_SRAIW_U  0xfe00707f
+#define MATCH_SRL32 0x52002077
+#define MASK_SRL32  0xfe00707f
+#define MATCH_SRL32_U 0x62002077
+#define MASK_SRL32_U  0xfe00707f
+#define MATCH_SRLI32 0x72002077
+#define MASK_SRLI32  0xfe00707f
+#define MATCH_SRLI32_U 0x82002077
+#define MASK_SRLI32_U  0xfe00707f
+#define MATCH_STAS32 0xf0002077
+#define MASK_STAS32  0xfe00707f
+#define MATCH_STSA32 0xf2002077
+#define MASK_STSA32  0xfe00707f
+#define MATCH_SUB32 0x42002077
+#define MASK_SUB32  0xfe00707f
+#define MATCH_UKADD32 0x30002077
+#define MASK_UKADD32  0xfe00707f
+#define MATCH_UKCRAS32 0x34002077
+#define MASK_UKCRAS32  0xfe00707f
+#define MATCH_UKCRSA32 0x36002077
+#define MASK_UKCRSA32  0xfe00707f
+#define MATCH_UKSTAS32 0xe0002077
+#define MASK_UKSTAS32  0xfe00707f
+#define MATCH_UKSTSA32 0xe2002077
+#define MASK_UKSTSA32  0xfe00707f
+#define MATCH_UKSUB32 0x32002077
+#define MASK_UKSUB32  0xfe00707f
+#define MATCH_UMAX32 0xa2002077
+#define MASK_UMAX32  0xfe00707f
+#define MATCH_UMIN32 0xa0002077
+#define MASK_UMIN32  0xfe00707f
+#define MATCH_URADD32 0x20002077
+#define MASK_URADD32  0xfe00707f
+#define MATCH_URCRAS32 0x24002077
+#define MASK_URCRAS32  0xfe00707f
+#define MATCH_URCRSA32 0x26002077
+#define MASK_URCRSA32  0xfe00707f
+#define MATCH_URSTAS32 0xd0002077
+#define MASK_URSTAS32  0xfe00707f
+#define MATCH_URSTSA32 0xd2002077
+#define MASK_URSTSA32  0xfe00707f
+#define MATCH_URSUB32 0x22002077
+#define MASK_URSUB32  0xfe00707f
 #define MATCH_VMVNFR_V 0x9e003057
 #define MASK_VMVNFR_V  0xfe00707f
 #define MATCH_VL1R_V 0x2800007
@@ -1769,21 +2783,24 @@
 #define MASK_VL4R_V  0xfff0707f
 #define MATCH_VL8R_V 0x1e807007
 #define MASK_VL8R_V  0xfff0707f
+#define MATCH_VLE1_V 0x2b00007
+#define MASK_VLE1_V  0xfff0707f
+#define MATCH_VSE1_V 0x2b00027
+#define MASK_VSE1_V  0xfff0707f
+#define MATCH_VFREDSUM_VS 0x4001057
+#define MASK_VFREDSUM_VS  0xfc00707f
+#define MATCH_VFWREDSUM_VS 0xc4001057
+#define MASK_VFWREDSUM_VS  0xfc00707f
+#define MATCH_VPOPC_M 0x40082057
+#define MASK_VPOPC_M  0xfc0ff07f
 #define CSR_FFLAGS 0x1
 #define CSR_FRM 0x2
 #define CSR_FCSR 0x3
-#define CSR_USTATUS 0x0
-#define CSR_UIE 0x4
-#define CSR_UTVEC 0x5
 #define CSR_VSTART 0x8
 #define CSR_VXSAT 0x9
 #define CSR_VXRM 0xa
 #define CSR_VCSR 0xf
-#define CSR_USCRATCH 0x40
-#define CSR_UEPC 0x41
-#define CSR_UCAUSE 0x42
-#define CSR_UTVAL 0x43
-#define CSR_UIP 0x44
+#define CSR_SEED 0x15
 #define CSR_CYCLE 0xc00
 #define CSR_TIME 0xc01
 #define CSR_INSTRET 0xc02
@@ -1831,6 +2848,7 @@
 #define CSR_STVAL 0x143
 #define CSR_SIP 0x144
 #define CSR_SATP 0x180
+#define CSR_SCONTEXT 0x5a8
 #define CSR_VSSTATUS 0x200
 #define CSR_VSIE 0x204
 #define CSR_VSTVEC 0x205
@@ -1852,6 +2870,7 @@
 #define CSR_HVIP 0x645
 #define CSR_HTINST 0x64a
 #define CSR_HGATP 0x680
+#define CSR_HCONTEXT 0x6a8
 #define CSR_HGEIP 0xe12
 #define CSR_UTVT 0x7
 #define CSR_UNXTI 0x45
@@ -1907,6 +2926,10 @@
 #define CSR_TDATA1 0x7a1
 #define CSR_TDATA2 0x7a2
 #define CSR_TDATA3 0x7a3
+#define CSR_TINFO 0x7a4
+#define CSR_TCONTROL 0x7a5
+#define CSR_MCONTEXT 0x7a8
+#define CSR_MSCONTEXT 0x7aa
 #define CSR_DCSR 0x7b0
 #define CSR_DPC 0x7b1
 #define CSR_DSCRATCH0 0x7b2
@@ -2095,12 +3118,9 @@ DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
 DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
 DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
 DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
-DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
 DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
 DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
 DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
-DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
-DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
 DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
 DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
 DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
@@ -2135,6 +3155,9 @@ DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
 DECLARE_INSN(ld, MATCH_LD, MASK_LD)
 DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
 DECLARE_INSN(sd, MATCH_SD, MASK_SD)
+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
 DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
 DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
@@ -2279,9 +3302,111 @@ DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
 DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
 DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
 DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
+DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN)
+DECLARE_INSN(orn, MATCH_ORN, MASK_ORN)
+DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR)
+DECLARE_INSN(slo, MATCH_SLO, MASK_SLO)
+DECLARE_INSN(sro, MATCH_SRO, MASK_SRO)
+DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
+DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
+DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
+DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
+DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
+DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
+DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC)
+DECLARE_INSN(grev, MATCH_GREV, MASK_GREV)
+DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI)
+DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI)
+DECLARE_INSN(rori, MATCH_RORI, MASK_RORI)
+DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
+DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
+DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
+DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI)
+DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI)
+DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI)
+DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX)
+DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV)
+DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL)
+DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR)
+DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI)
+DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
+DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
+DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP)
+DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B)
+DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H)
+DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B)
+DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H)
+DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W)
+DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B)
+DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H)
+DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W)
+DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD)
+DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD)
+DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD)
+DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
+DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
+DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
+DECLARE_INSN(min, MATCH_MIN, MASK_MIN)
+DECLARE_INSN(minu, MATCH_MINU, MASK_MINU)
+DECLARE_INSN(max, MATCH_MAX, MASK_MAX)
+DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU)
+DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL)
+DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL)
+DECLARE_INSN(bcompress, MATCH_BCOMPRESS, MASK_BCOMPRESS)
+DECLARE_INSN(bdecompress, MATCH_BDECOMPRESS, MASK_BDECOMPRESS)
+DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
+DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU)
+DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
+DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP)
+DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI)
+DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI)
+DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4)
+DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8)
+DECLARE_INSN(xperm16, MATCH_XPERM16, MASK_XPERM16)
+DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP)
+DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D)
+DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D)
+DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
+DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
+DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
+DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW)
+DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW)
+DECLARE_INSN(srow, MATCH_SROW, MASK_SROW)
+DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
+DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
+DECLARE_INSN(sbclrw, MATCH_SBCLRW, MASK_SBCLRW)
+DECLARE_INSN(sbsetw, MATCH_SBSETW, MASK_SBSETW)
+DECLARE_INSN(sbinvw, MATCH_SBINVW, MASK_SBINVW)
+DECLARE_INSN(sbextw, MATCH_SBEXTW, MASK_SBEXTW)
+DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW)
+DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW)
+DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW)
+DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW)
+DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
+DECLARE_INSN(sbclriw, MATCH_SBCLRIW, MASK_SBCLRIW)
+DECLARE_INSN(sbsetiw, MATCH_SBSETIW, MASK_SBSETIW)
+DECLARE_INSN(sbinviw, MATCH_SBINVIW, MASK_SBINVIW)
+DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW)
+DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW)
+DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW)
+DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
+DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW)
+DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
+DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
+DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW)
+DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW)
+DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW)
+DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW)
+DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW)
+DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW)
+DECLARE_INSN(bcompressw, MATCH_BCOMPRESSW, MASK_BCOMPRESSW)
+DECLARE_INSN(bdecompressw, MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW)
+DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
+DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW)
+DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW)
+DECLARE_INSN(xperm32, MATCH_XPERM32, MASK_XPERM32)
 DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
 DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
-DECLARE_INSN(uret, MATCH_URET, MASK_URET)
 DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
 DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
 DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
@@ -2293,6 +3418,76 @@ DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
 DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
 DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
 DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA)
+DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL)
+DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR)
+DECLARE_INSN(hinval_vvma, MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA)
+DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA)
+DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
+DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H)
+DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H)
+DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H)
+DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H)
+DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H)
+DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H)
+DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H)
+DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H)
+DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S)
+DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H)
+DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H)
+DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
+DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
+DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H)
+DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H)
+DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
+DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
+DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H)
+DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W)
+DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU)
+DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X)
+DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
+DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
+DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
+DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
+DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
+DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
+DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D)
+DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
+DECLARE_INSN(fcvt_h_q, MATCH_FCVT_H_Q, MASK_FCVT_H_Q)
+DECLARE_INSN(fcvt_q_h, MATCH_FCVT_Q_H, MASK_FCVT_Q_H)
+DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
+DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
+DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
+DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
+DECLARE_INSN(sm4ed, MATCH_SM4ED, MASK_SM4ED)
+DECLARE_INSN(sm4ks, MATCH_SM4KS, MASK_SM4KS)
+DECLARE_INSN(sm3p0, MATCH_SM3P0, MASK_SM3P0)
+DECLARE_INSN(sm3p1, MATCH_SM3P1, MASK_SM3P1)
+DECLARE_INSN(sha256sum0, MATCH_SHA256SUM0, MASK_SHA256SUM0)
+DECLARE_INSN(sha256sum1, MATCH_SHA256SUM1, MASK_SHA256SUM1)
+DECLARE_INSN(sha256sig0, MATCH_SHA256SIG0, MASK_SHA256SIG0)
+DECLARE_INSN(sha256sig1, MATCH_SHA256SIG1, MASK_SHA256SIG1)
+DECLARE_INSN(aes32esmi, MATCH_AES32ESMI, MASK_AES32ESMI)
+DECLARE_INSN(aes32esi, MATCH_AES32ESI, MASK_AES32ESI)
+DECLARE_INSN(aes32dsmi, MATCH_AES32DSMI, MASK_AES32DSMI)
+DECLARE_INSN(aes32dsi, MATCH_AES32DSI, MASK_AES32DSI)
+DECLARE_INSN(sha512sum0r, MATCH_SHA512SUM0R, MASK_SHA512SUM0R)
+DECLARE_INSN(sha512sum1r, MATCH_SHA512SUM1R, MASK_SHA512SUM1R)
+DECLARE_INSN(sha512sig0l, MATCH_SHA512SIG0L, MASK_SHA512SIG0L)
+DECLARE_INSN(sha512sig0h, MATCH_SHA512SIG0H, MASK_SHA512SIG0H)
+DECLARE_INSN(sha512sig1l, MATCH_SHA512SIG1L, MASK_SHA512SIG1L)
+DECLARE_INSN(sha512sig1h, MATCH_SHA512SIG1H, MASK_SHA512SIG1H)
+DECLARE_INSN(aes64ks1i, MATCH_AES64KS1I, MASK_AES64KS1I)
+DECLARE_INSN(aes64im, MATCH_AES64IM, MASK_AES64IM)
+DECLARE_INSN(aes64ks2, MATCH_AES64KS2, MASK_AES64KS2)
+DECLARE_INSN(aes64esm, MATCH_AES64ESM, MASK_AES64ESM)
+DECLARE_INSN(aes64es, MATCH_AES64ES, MASK_AES64ES)
+DECLARE_INSN(aes64dsm, MATCH_AES64DSM, MASK_AES64DSM)
+DECLARE_INSN(aes64ds, MATCH_AES64DS, MASK_AES64DS)
+DECLARE_INSN(sha512sum0, MATCH_SHA512SUM0, MASK_SHA512SUM0)
+DECLARE_INSN(sha512sum1, MATCH_SHA512SUM1, MASK_SHA512SUM1)
+DECLARE_INSN(sha512sig0, MATCH_SHA512SIG0, MASK_SHA512SIG0)
+DECLARE_INSN(sha512sig1, MATCH_SHA512SIG1, MASK_SHA512SIG1)
 DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
 DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
 DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
@@ -2362,8 +3557,11 @@ DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
 DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
 DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
 DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
+DECLARE_INSN(vsetivli, MATCH_VSETIVLI, MASK_VSETIVLI)
 DECLARE_INSN(vsetvli, MATCH_VSETVLI, MASK_VSETVLI)
 DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL)
+DECLARE_INSN(vlm_v, MATCH_VLM_V, MASK_VLM_V)
+DECLARE_INSN(vsm_v, MATCH_VSM_V, MASK_VSM_V)
 DECLARE_INSN(vle8_v, MATCH_VLE8_V, MASK_VLE8_V)
 DECLARE_INSN(vle16_v, MATCH_VLE16_V, MASK_VLE16_V)
 DECLARE_INSN(vle32_v, MATCH_VLE32_V, MASK_VLE32_V)
@@ -2380,6 +3578,22 @@ DECLARE_INSN(vse128_v, MATCH_VSE128_V, MASK_VSE128_V)
 DECLARE_INSN(vse256_v, MATCH_VSE256_V, MASK_VSE256_V)
 DECLARE_INSN(vse512_v, MATCH_VSE512_V, MASK_VSE512_V)
 DECLARE_INSN(vse1024_v, MATCH_VSE1024_V, MASK_VSE1024_V)
+DECLARE_INSN(vluxei8_v, MATCH_VLUXEI8_V, MASK_VLUXEI8_V)
+DECLARE_INSN(vluxei16_v, MATCH_VLUXEI16_V, MASK_VLUXEI16_V)
+DECLARE_INSN(vluxei32_v, MATCH_VLUXEI32_V, MASK_VLUXEI32_V)
+DECLARE_INSN(vluxei64_v, MATCH_VLUXEI64_V, MASK_VLUXEI64_V)
+DECLARE_INSN(vluxei128_v, MATCH_VLUXEI128_V, MASK_VLUXEI128_V)
+DECLARE_INSN(vluxei256_v, MATCH_VLUXEI256_V, MASK_VLUXEI256_V)
+DECLARE_INSN(vluxei512_v, MATCH_VLUXEI512_V, MASK_VLUXEI512_V)
+DECLARE_INSN(vluxei1024_v, MATCH_VLUXEI1024_V, MASK_VLUXEI1024_V)
+DECLARE_INSN(vsuxei8_v, MATCH_VSUXEI8_V, MASK_VSUXEI8_V)
+DECLARE_INSN(vsuxei16_v, MATCH_VSUXEI16_V, MASK_VSUXEI16_V)
+DECLARE_INSN(vsuxei32_v, MATCH_VSUXEI32_V, MASK_VSUXEI32_V)
+DECLARE_INSN(vsuxei64_v, MATCH_VSUXEI64_V, MASK_VSUXEI64_V)
+DECLARE_INSN(vsuxei128_v, MATCH_VSUXEI128_V, MASK_VSUXEI128_V)
+DECLARE_INSN(vsuxei256_v, MATCH_VSUXEI256_V, MASK_VSUXEI256_V)
+DECLARE_INSN(vsuxei512_v, MATCH_VSUXEI512_V, MASK_VSUXEI512_V)
+DECLARE_INSN(vsuxei1024_v, MATCH_VSUXEI1024_V, MASK_VSUXEI1024_V)
 DECLARE_INSN(vlse8_v, MATCH_VLSE8_V, MASK_VLSE8_V)
 DECLARE_INSN(vlse16_v, MATCH_VLSE16_V, MASK_VLSE16_V)
 DECLARE_INSN(vlse32_v, MATCH_VLSE32_V, MASK_VLSE32_V)
@@ -2396,30 +3610,22 @@ DECLARE_INSN(vsse128_v, MATCH_VSSE128_V, MASK_VSSE128_V)
 DECLARE_INSN(vsse256_v, MATCH_VSSE256_V, MASK_VSSE256_V)
 DECLARE_INSN(vsse512_v, MATCH_VSSE512_V, MASK_VSSE512_V)
 DECLARE_INSN(vsse1024_v, MATCH_VSSE1024_V, MASK_VSSE1024_V)
-DECLARE_INSN(vlxei8_v, MATCH_VLXEI8_V, MASK_VLXEI8_V)
-DECLARE_INSN(vlxei16_v, MATCH_VLXEI16_V, MASK_VLXEI16_V)
-DECLARE_INSN(vlxei32_v, MATCH_VLXEI32_V, MASK_VLXEI32_V)
-DECLARE_INSN(vlxei64_v, MATCH_VLXEI64_V, MASK_VLXEI64_V)
-DECLARE_INSN(vlxei128_v, MATCH_VLXEI128_V, MASK_VLXEI128_V)
-DECLARE_INSN(vlxei256_v, MATCH_VLXEI256_V, MASK_VLXEI256_V)
-DECLARE_INSN(vlxei512_v, MATCH_VLXEI512_V, MASK_VLXEI512_V)
-DECLARE_INSN(vlxei1024_v, MATCH_VLXEI1024_V, MASK_VLXEI1024_V)
-DECLARE_INSN(vsxei8_v, MATCH_VSXEI8_V, MASK_VSXEI8_V)
-DECLARE_INSN(vsxei16_v, MATCH_VSXEI16_V, MASK_VSXEI16_V)
-DECLARE_INSN(vsxei32_v, MATCH_VSXEI32_V, MASK_VSXEI32_V)
-DECLARE_INSN(vsxei64_v, MATCH_VSXEI64_V, MASK_VSXEI64_V)
-DECLARE_INSN(vsxei128_v, MATCH_VSXEI128_V, MASK_VSXEI128_V)
-DECLARE_INSN(vsxei256_v, MATCH_VSXEI256_V, MASK_VSXEI256_V)
-DECLARE_INSN(vsxei512_v, MATCH_VSXEI512_V, MASK_VSXEI512_V)
-DECLARE_INSN(vsxei1024_v, MATCH_VSXEI1024_V, MASK_VSXEI1024_V)
-DECLARE_INSN(vsuxei8_v, MATCH_VSUXEI8_V, MASK_VSUXEI8_V)
-DECLARE_INSN(vsuxei16_v, MATCH_VSUXEI16_V, MASK_VSUXEI16_V)
-DECLARE_INSN(vsuxei32_v, MATCH_VSUXEI32_V, MASK_VSUXEI32_V)
-DECLARE_INSN(vsuxei64_v, MATCH_VSUXEI64_V, MASK_VSUXEI64_V)
-DECLARE_INSN(vsuxei128_v, MATCH_VSUXEI128_V, MASK_VSUXEI128_V)
-DECLARE_INSN(vsuxei256_v, MATCH_VSUXEI256_V, MASK_VSUXEI256_V)
-DECLARE_INSN(vsuxei512_v, MATCH_VSUXEI512_V, MASK_VSUXEI512_V)
-DECLARE_INSN(vsuxei1024_v, MATCH_VSUXEI1024_V, MASK_VSUXEI1024_V)
+DECLARE_INSN(vloxei8_v, MATCH_VLOXEI8_V, MASK_VLOXEI8_V)
+DECLARE_INSN(vloxei16_v, MATCH_VLOXEI16_V, MASK_VLOXEI16_V)
+DECLARE_INSN(vloxei32_v, MATCH_VLOXEI32_V, MASK_VLOXEI32_V)
+DECLARE_INSN(vloxei64_v, MATCH_VLOXEI64_V, MASK_VLOXEI64_V)
+DECLARE_INSN(vloxei128_v, MATCH_VLOXEI128_V, MASK_VLOXEI128_V)
+DECLARE_INSN(vloxei256_v, MATCH_VLOXEI256_V, MASK_VLOXEI256_V)
+DECLARE_INSN(vloxei512_v, MATCH_VLOXEI512_V, MASK_VLOXEI512_V)
+DECLARE_INSN(vloxei1024_v, MATCH_VLOXEI1024_V, MASK_VLOXEI1024_V)
+DECLARE_INSN(vsoxei8_v, MATCH_VSOXEI8_V, MASK_VSOXEI8_V)
+DECLARE_INSN(vsoxei16_v, MATCH_VSOXEI16_V, MASK_VSOXEI16_V)
+DECLARE_INSN(vsoxei32_v, MATCH_VSOXEI32_V, MASK_VSOXEI32_V)
+DECLARE_INSN(vsoxei64_v, MATCH_VSOXEI64_V, MASK_VSOXEI64_V)
+DECLARE_INSN(vsoxei128_v, MATCH_VSOXEI128_V, MASK_VSOXEI128_V)
+DECLARE_INSN(vsoxei256_v, MATCH_VSOXEI256_V, MASK_VSOXEI256_V)
+DECLARE_INSN(vsoxei512_v, MATCH_VSOXEI512_V, MASK_VSOXEI512_V)
+DECLARE_INSN(vsoxei1024_v, MATCH_VSOXEI1024_V, MASK_VSOXEI1024_V)
 DECLARE_INSN(vle8ff_v, MATCH_VLE8FF_V, MASK_VLE8FF_V)
 DECLARE_INSN(vle16ff_v, MATCH_VLE16FF_V, MASK_VLE16FF_V)
 DECLARE_INSN(vle32ff_v, MATCH_VLE32FF_V, MASK_VLE32FF_V)
@@ -2488,7 +3694,7 @@ DECLARE_INSN(vfwnmacc_vf, MATCH_VFWNMACC_VF, MASK_VFWNMACC_VF)
 DECLARE_INSN(vfwmsac_vf, MATCH_VFWMSAC_VF, MASK_VFWMSAC_VF)
 DECLARE_INSN(vfwnmsac_vf, MATCH_VFWNMSAC_VF, MASK_VFWNMSAC_VF)
 DECLARE_INSN(vfadd_vv, MATCH_VFADD_VV, MASK_VFADD_VV)
-DECLARE_INSN(vfredsum_vs, MATCH_VFREDSUM_VS, MASK_VFREDSUM_VS)
+DECLARE_INSN(vfredusum_vs, MATCH_VFREDUSUM_VS, MASK_VFREDUSUM_VS)
 DECLARE_INSN(vfsub_vv, MATCH_VFSUB_VV, MASK_VFSUB_VV)
 DECLARE_INSN(vfredosum_vs, MATCH_VFREDOSUM_VS, MASK_VFREDOSUM_VS)
 DECLARE_INSN(vfmin_vv, MATCH_VFMIN_VV, MASK_VFMIN_VV)
@@ -2535,15 +3741,16 @@ DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W)
 DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W)
 DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W)
 DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V)
+DECLARE_INSN(vfrsqrt7_v, MATCH_VFRSQRT7_V, MASK_VFRSQRT7_V)
+DECLARE_INSN(vfrec7_v, MATCH_VFREC7_V, MASK_VFREC7_V)
 DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V)
 DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV)
-DECLARE_INSN(vfwredsum_vs, MATCH_VFWREDSUM_VS, MASK_VFWREDSUM_VS)
+DECLARE_INSN(vfwredusum_vs, MATCH_VFWREDUSUM_VS, MASK_VFWREDUSUM_VS)
 DECLARE_INSN(vfwsub_vv, MATCH_VFWSUB_VV, MASK_VFWSUB_VV)
 DECLARE_INSN(vfwredosum_vs, MATCH_VFWREDOSUM_VS, MASK_VFWREDOSUM_VS)
 DECLARE_INSN(vfwadd_wv, MATCH_VFWADD_WV, MASK_VFWADD_WV)
 DECLARE_INSN(vfwsub_wv, MATCH_VFWSUB_WV, MASK_VFWSUB_WV)
 DECLARE_INSN(vfwmul_vv, MATCH_VFWMUL_VV, MASK_VFWMUL_VV)
-DECLARE_INSN(vfdot_vv, MATCH_VFDOT_VV, MASK_VFDOT_VV)
 DECLARE_INSN(vfwmacc_vv, MATCH_VFWMACC_VV, MASK_VFWMACC_VV)
 DECLARE_INSN(vfwnmacc_vv, MATCH_VFWNMACC_VV, MASK_VFWNMACC_VV)
 DECLARE_INSN(vfwmsac_vv, MATCH_VFWMSAC_VV, MASK_VFWMSAC_VV)
@@ -2563,8 +3770,10 @@ DECLARE_INSN(vslideup_vx, MATCH_VSLIDEUP_VX, MASK_VSLIDEUP_VX)
 DECLARE_INSN(vslidedown_vx, MATCH_VSLIDEDOWN_VX, MASK_VSLIDEDOWN_VX)
 DECLARE_INSN(vadc_vxm, MATCH_VADC_VXM, MASK_VADC_VXM)
 DECLARE_INSN(vmadc_vxm, MATCH_VMADC_VXM, MASK_VMADC_VXM)
+DECLARE_INSN(vmadc_vx, MATCH_VMADC_VX, MASK_VMADC_VX)
 DECLARE_INSN(vsbc_vxm, MATCH_VSBC_VXM, MASK_VSBC_VXM)
 DECLARE_INSN(vmsbc_vxm, MATCH_VMSBC_VXM, MASK_VMSBC_VXM)
+DECLARE_INSN(vmsbc_vx, MATCH_VMSBC_VX, MASK_VMSBC_VX)
 DECLARE_INSN(vmerge_vxm, MATCH_VMERGE_VXM, MASK_VMERGE_VXM)
 DECLARE_INSN(vmv_v_x, MATCH_VMV_V_X, MASK_VMV_V_X)
 DECLARE_INSN(vmseq_vx, MATCH_VMSEQ_VX, MASK_VMSEQ_VX)
@@ -2589,10 +3798,6 @@ DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX)
 DECLARE_INSN(vnsra_wx, MATCH_VNSRA_WX, MASK_VNSRA_WX)
 DECLARE_INSN(vnclipu_wx, MATCH_VNCLIPU_WX, MASK_VNCLIPU_WX)
 DECLARE_INSN(vnclip_wx, MATCH_VNCLIP_WX, MASK_VNCLIP_WX)
-DECLARE_INSN(vqmaccu_vx, MATCH_VQMACCU_VX, MASK_VQMACCU_VX)
-DECLARE_INSN(vqmacc_vx, MATCH_VQMACC_VX, MASK_VQMACC_VX)
-DECLARE_INSN(vqmaccus_vx, MATCH_VQMACCUS_VX, MASK_VQMACCUS_VX)
-DECLARE_INSN(vqmaccsu_vx, MATCH_VQMACCSU_VX, MASK_VQMACCSU_VX)
 DECLARE_INSN(vadd_vv, MATCH_VADD_VV, MASK_VADD_VV)
 DECLARE_INSN(vsub_vv, MATCH_VSUB_VV, MASK_VSUB_VV)
 DECLARE_INSN(vminu_vv, MATCH_VMINU_VV, MASK_VMINU_VV)
@@ -2606,8 +3811,10 @@ DECLARE_INSN(vrgather_vv, MATCH_VRGATHER_VV, MASK_VRGATHER_VV)
 DECLARE_INSN(vrgatherei16_vv, MATCH_VRGATHEREI16_VV, MASK_VRGATHEREI16_VV)
 DECLARE_INSN(vadc_vvm, MATCH_VADC_VVM, MASK_VADC_VVM)
 DECLARE_INSN(vmadc_vvm, MATCH_VMADC_VVM, MASK_VMADC_VVM)
+DECLARE_INSN(vmadc_vv, MATCH_VMADC_VV, MASK_VMADC_VV)
 DECLARE_INSN(vsbc_vvm, MATCH_VSBC_VVM, MASK_VSBC_VVM)
 DECLARE_INSN(vmsbc_vvm, MATCH_VMSBC_VVM, MASK_VMSBC_VVM)
+DECLARE_INSN(vmsbc_vv, MATCH_VMSBC_VV, MASK_VMSBC_VV)
 DECLARE_INSN(vmerge_vvm, MATCH_VMERGE_VVM, MASK_VMERGE_VVM)
 DECLARE_INSN(vmv_v_v, MATCH_VMV_V_V, MASK_VMV_V_V)
 DECLARE_INSN(vmseq_vv, MATCH_VMSEQ_VV, MASK_VMSEQ_VV)
@@ -2632,11 +3839,6 @@ DECLARE_INSN(vnclipu_wv, MATCH_VNCLIPU_WV, MASK_VNCLIPU_WV)
 DECLARE_INSN(vnclip_wv, MATCH_VNCLIP_WV, MASK_VNCLIP_WV)
 DECLARE_INSN(vwredsumu_vs, MATCH_VWREDSUMU_VS, MASK_VWREDSUMU_VS)
 DECLARE_INSN(vwredsum_vs, MATCH_VWREDSUM_VS, MASK_VWREDSUM_VS)
-DECLARE_INSN(vdotu_vv, MATCH_VDOTU_VV, MASK_VDOTU_VV)
-DECLARE_INSN(vdot_vv, MATCH_VDOT_VV, MASK_VDOT_VV)
-DECLARE_INSN(vqmaccu_vv, MATCH_VQMACCU_VV, MASK_VQMACCU_VV)
-DECLARE_INSN(vqmacc_vv, MATCH_VQMACC_VV, MASK_VQMACC_VV)
-DECLARE_INSN(vqmaccsu_vv, MATCH_VQMACCSU_VV, MASK_VQMACCSU_VV)
 DECLARE_INSN(vadd_vi, MATCH_VADD_VI, MASK_VADD_VI)
 DECLARE_INSN(vrsub_vi, MATCH_VRSUB_VI, MASK_VRSUB_VI)
 DECLARE_INSN(vand_vi, MATCH_VAND_VI, MASK_VAND_VI)
@@ -2647,6 +3849,7 @@ DECLARE_INSN(vslideup_vi, MATCH_VSLIDEUP_VI, MASK_VSLIDEUP_VI)
 DECLARE_INSN(vslidedown_vi, MATCH_VSLIDEDOWN_VI, MASK_VSLIDEDOWN_VI)
 DECLARE_INSN(vadc_vim, MATCH_VADC_VIM, MASK_VADC_VIM)
 DECLARE_INSN(vmadc_vim, MATCH_VMADC_VIM, MASK_VMADC_VIM)
+DECLARE_INSN(vmadc_vi, MATCH_VMADC_VI, MASK_VMADC_VI)
 DECLARE_INSN(vmerge_vim, MATCH_VMERGE_VIM, MASK_VMERGE_VIM)
 DECLARE_INSN(vmv_v_i, MATCH_VMV_V_I, MASK_VMV_V_I)
 DECLARE_INSN(vmseq_vi, MATCH_VMSEQ_VI, MASK_VMSEQ_VI)
@@ -2703,7 +3906,7 @@ DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M)
 DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M)
 DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M)
 DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V)
-DECLARE_INSN(vpopc_m, MATCH_VPOPC_M, MASK_VPOPC_M)
+DECLARE_INSN(vcpop_m, MATCH_VCPOP_M, MASK_VCPOP_M)
 DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M)
 DECLARE_INSN(vdivu_vv, MATCH_VDIVU_VV, MASK_VDIVU_VV)
 DECLARE_INSN(vdiv_vv, MATCH_VDIV_VV, MASK_VDIV_VV)
@@ -2801,28 +4004,352 @@ DECLARE_INSN(vamominei64_v, MATCH_VAMOMINEI64_V, MASK_VAMOMINEI64_V)
 DECLARE_INSN(vamomaxei64_v, MATCH_VAMOMAXEI64_V, MASK_VAMOMAXEI64_V)
 DECLARE_INSN(vamominuei64_v, MATCH_VAMOMINUEI64_V, MASK_VAMOMINUEI64_V)
 DECLARE_INSN(vamomaxuei64_v, MATCH_VAMOMAXUEI64_V, MASK_VAMOMAXUEI64_V)
+DECLARE_INSN(add8, MATCH_ADD8, MASK_ADD8)
+DECLARE_INSN(add16, MATCH_ADD16, MASK_ADD16)
+DECLARE_INSN(add64, MATCH_ADD64, MASK_ADD64)
+DECLARE_INSN(ave, MATCH_AVE, MASK_AVE)
+DECLARE_INSN(bitrev, MATCH_BITREV, MASK_BITREV)
+DECLARE_INSN(bitrevi, MATCH_BITREVI, MASK_BITREVI)
+DECLARE_INSN(bpick, MATCH_BPICK, MASK_BPICK)
+DECLARE_INSN(clrs8, MATCH_CLRS8, MASK_CLRS8)
+DECLARE_INSN(clrs16, MATCH_CLRS16, MASK_CLRS16)
+DECLARE_INSN(clrs32, MATCH_CLRS32, MASK_CLRS32)
+DECLARE_INSN(clo8, MATCH_CLO8, MASK_CLO8)
+DECLARE_INSN(clo16, MATCH_CLO16, MASK_CLO16)
+DECLARE_INSN(clo32, MATCH_CLO32, MASK_CLO32)
+DECLARE_INSN(clz8, MATCH_CLZ8, MASK_CLZ8)
+DECLARE_INSN(clz16, MATCH_CLZ16, MASK_CLZ16)
+DECLARE_INSN(clz32, MATCH_CLZ32, MASK_CLZ32)
+DECLARE_INSN(cmpeq8, MATCH_CMPEQ8, MASK_CMPEQ8)
+DECLARE_INSN(cmpeq16, MATCH_CMPEQ16, MASK_CMPEQ16)
+DECLARE_INSN(cras16, MATCH_CRAS16, MASK_CRAS16)
+DECLARE_INSN(crsa16, MATCH_CRSA16, MASK_CRSA16)
+DECLARE_INSN(insb, MATCH_INSB, MASK_INSB)
+DECLARE_INSN(kabs8, MATCH_KABS8, MASK_KABS8)
+DECLARE_INSN(kabs16, MATCH_KABS16, MASK_KABS16)
+DECLARE_INSN(kabsw, MATCH_KABSW, MASK_KABSW)
+DECLARE_INSN(kadd8, MATCH_KADD8, MASK_KADD8)
+DECLARE_INSN(kadd16, MATCH_KADD16, MASK_KADD16)
+DECLARE_INSN(kadd64, MATCH_KADD64, MASK_KADD64)
+DECLARE_INSN(kaddh, MATCH_KADDH, MASK_KADDH)
+DECLARE_INSN(kaddw, MATCH_KADDW, MASK_KADDW)
+DECLARE_INSN(kcras16, MATCH_KCRAS16, MASK_KCRAS16)
+DECLARE_INSN(kcrsa16, MATCH_KCRSA16, MASK_KCRSA16)
+DECLARE_INSN(kdmbb, MATCH_KDMBB, MASK_KDMBB)
+DECLARE_INSN(kdmbt, MATCH_KDMBT, MASK_KDMBT)
+DECLARE_INSN(kdmtt, MATCH_KDMTT, MASK_KDMTT)
+DECLARE_INSN(kdmabb, MATCH_KDMABB, MASK_KDMABB)
+DECLARE_INSN(kdmabt, MATCH_KDMABT, MASK_KDMABT)
+DECLARE_INSN(kdmatt, MATCH_KDMATT, MASK_KDMATT)
+DECLARE_INSN(khm8, MATCH_KHM8, MASK_KHM8)
+DECLARE_INSN(khmx8, MATCH_KHMX8, MASK_KHMX8)
+DECLARE_INSN(khm16, MATCH_KHM16, MASK_KHM16)
+DECLARE_INSN(khmx16, MATCH_KHMX16, MASK_KHMX16)
+DECLARE_INSN(khmbb, MATCH_KHMBB, MASK_KHMBB)
+DECLARE_INSN(khmbt, MATCH_KHMBT, MASK_KHMBT)
+DECLARE_INSN(khmtt, MATCH_KHMTT, MASK_KHMTT)
+DECLARE_INSN(kmabb, MATCH_KMABB, MASK_KMABB)
+DECLARE_INSN(kmabt, MATCH_KMABT, MASK_KMABT)
+DECLARE_INSN(kmatt, MATCH_KMATT, MASK_KMATT)
+DECLARE_INSN(kmada, MATCH_KMADA, MASK_KMADA)
+DECLARE_INSN(kmaxda, MATCH_KMAXDA, MASK_KMAXDA)
+DECLARE_INSN(kmads, MATCH_KMADS, MASK_KMADS)
+DECLARE_INSN(kmadrs, MATCH_KMADRS, MASK_KMADRS)
+DECLARE_INSN(kmaxds, MATCH_KMAXDS, MASK_KMAXDS)
+DECLARE_INSN(kmar64, MATCH_KMAR64, MASK_KMAR64)
+DECLARE_INSN(kmda, MATCH_KMDA, MASK_KMDA)
+DECLARE_INSN(kmxda, MATCH_KMXDA, MASK_KMXDA)
+DECLARE_INSN(kmmac, MATCH_KMMAC, MASK_KMMAC)
+DECLARE_INSN(kmmac_u, MATCH_KMMAC_U, MASK_KMMAC_U)
+DECLARE_INSN(kmmawb, MATCH_KMMAWB, MASK_KMMAWB)
+DECLARE_INSN(kmmawb_u, MATCH_KMMAWB_U, MASK_KMMAWB_U)
+DECLARE_INSN(kmmawb2, MATCH_KMMAWB2, MASK_KMMAWB2)
+DECLARE_INSN(kmmawb2_u, MATCH_KMMAWB2_U, MASK_KMMAWB2_U)
+DECLARE_INSN(kmmawt, MATCH_KMMAWT, MASK_KMMAWT)
+DECLARE_INSN(kmmawt_u, MATCH_KMMAWT_U, MASK_KMMAWT_U)
+DECLARE_INSN(kmmawt2, MATCH_KMMAWT2, MASK_KMMAWT2)
+DECLARE_INSN(kmmawt2_u, MATCH_KMMAWT2_U, MASK_KMMAWT2_U)
+DECLARE_INSN(kmmsb, MATCH_KMMSB, MASK_KMMSB)
+DECLARE_INSN(kmmsb_u, MATCH_KMMSB_U, MASK_KMMSB_U)
+DECLARE_INSN(kmmwb2, MATCH_KMMWB2, MASK_KMMWB2)
+DECLARE_INSN(kmmwb2_u, MATCH_KMMWB2_U, MASK_KMMWB2_U)
+DECLARE_INSN(kmmwt2, MATCH_KMMWT2, MASK_KMMWT2)
+DECLARE_INSN(kmmwt2_u, MATCH_KMMWT2_U, MASK_KMMWT2_U)
+DECLARE_INSN(kmsda, MATCH_KMSDA, MASK_KMSDA)
+DECLARE_INSN(kmsxda, MATCH_KMSXDA, MASK_KMSXDA)
+DECLARE_INSN(kmsr64, MATCH_KMSR64, MASK_KMSR64)
+DECLARE_INSN(ksllw, MATCH_KSLLW, MASK_KSLLW)
+DECLARE_INSN(kslliw, MATCH_KSLLIW, MASK_KSLLIW)
+DECLARE_INSN(ksll8, MATCH_KSLL8, MASK_KSLL8)
+DECLARE_INSN(kslli8, MATCH_KSLLI8, MASK_KSLLI8)
+DECLARE_INSN(ksll16, MATCH_KSLL16, MASK_KSLL16)
+DECLARE_INSN(kslli16, MATCH_KSLLI16, MASK_KSLLI16)
+DECLARE_INSN(kslra8, MATCH_KSLRA8, MASK_KSLRA8)
+DECLARE_INSN(kslra8_u, MATCH_KSLRA8_U, MASK_KSLRA8_U)
+DECLARE_INSN(kslra16, MATCH_KSLRA16, MASK_KSLRA16)
+DECLARE_INSN(kslra16_u, MATCH_KSLRA16_U, MASK_KSLRA16_U)
+DECLARE_INSN(kslraw, MATCH_KSLRAW, MASK_KSLRAW)
+DECLARE_INSN(kslraw_u, MATCH_KSLRAW_U, MASK_KSLRAW_U)
+DECLARE_INSN(kstas16, MATCH_KSTAS16, MASK_KSTAS16)
+DECLARE_INSN(kstsa16, MATCH_KSTSA16, MASK_KSTSA16)
+DECLARE_INSN(ksub8, MATCH_KSUB8, MASK_KSUB8)
+DECLARE_INSN(ksub16, MATCH_KSUB16, MASK_KSUB16)
+DECLARE_INSN(ksub64, MATCH_KSUB64, MASK_KSUB64)
+DECLARE_INSN(ksubh, MATCH_KSUBH, MASK_KSUBH)
+DECLARE_INSN(ksubw, MATCH_KSUBW, MASK_KSUBW)
+DECLARE_INSN(kwmmul, MATCH_KWMMUL, MASK_KWMMUL)
+DECLARE_INSN(kwmmul_u, MATCH_KWMMUL_U, MASK_KWMMUL_U)
+DECLARE_INSN(maddr32, MATCH_MADDR32, MASK_MADDR32)
+DECLARE_INSN(maxw, MATCH_MAXW, MASK_MAXW)
+DECLARE_INSN(minw, MATCH_MINW, MASK_MINW)
+DECLARE_INSN(msubr32, MATCH_MSUBR32, MASK_MSUBR32)
+DECLARE_INSN(mulr64, MATCH_MULR64, MASK_MULR64)
+DECLARE_INSN(mulsr64, MATCH_MULSR64, MASK_MULSR64)
+DECLARE_INSN(pbsad, MATCH_PBSAD, MASK_PBSAD)
+DECLARE_INSN(pbsada, MATCH_PBSADA, MASK_PBSADA)
+DECLARE_INSN(pkbb16, MATCH_PKBB16, MASK_PKBB16)
+DECLARE_INSN(pkbt16, MATCH_PKBT16, MASK_PKBT16)
+DECLARE_INSN(pktt16, MATCH_PKTT16, MASK_PKTT16)
+DECLARE_INSN(pktb16, MATCH_PKTB16, MASK_PKTB16)
+DECLARE_INSN(radd8, MATCH_RADD8, MASK_RADD8)
+DECLARE_INSN(radd16, MATCH_RADD16, MASK_RADD16)
+DECLARE_INSN(radd64, MATCH_RADD64, MASK_RADD64)
+DECLARE_INSN(raddw, MATCH_RADDW, MASK_RADDW)
+DECLARE_INSN(rcras16, MATCH_RCRAS16, MASK_RCRAS16)
+DECLARE_INSN(rcrsa16, MATCH_RCRSA16, MASK_RCRSA16)
+DECLARE_INSN(rstas16, MATCH_RSTAS16, MASK_RSTAS16)
+DECLARE_INSN(rstsa16, MATCH_RSTSA16, MASK_RSTSA16)
+DECLARE_INSN(rsub8, MATCH_RSUB8, MASK_RSUB8)
+DECLARE_INSN(rsub16, MATCH_RSUB16, MASK_RSUB16)
+DECLARE_INSN(rsub64, MATCH_RSUB64, MASK_RSUB64)
+DECLARE_INSN(rsubw, MATCH_RSUBW, MASK_RSUBW)
+DECLARE_INSN(sclip8, MATCH_SCLIP8, MASK_SCLIP8)
+DECLARE_INSN(sclip16, MATCH_SCLIP16, MASK_SCLIP16)
+DECLARE_INSN(sclip32, MATCH_SCLIP32, MASK_SCLIP32)
+DECLARE_INSN(scmple8, MATCH_SCMPLE8, MASK_SCMPLE8)
+DECLARE_INSN(scmple16, MATCH_SCMPLE16, MASK_SCMPLE16)
+DECLARE_INSN(scmplt8, MATCH_SCMPLT8, MASK_SCMPLT8)
+DECLARE_INSN(scmplt16, MATCH_SCMPLT16, MASK_SCMPLT16)
+DECLARE_INSN(sll8, MATCH_SLL8, MASK_SLL8)
+DECLARE_INSN(slli8, MATCH_SLLI8, MASK_SLLI8)
+DECLARE_INSN(sll16, MATCH_SLL16, MASK_SLL16)
+DECLARE_INSN(slli16, MATCH_SLLI16, MASK_SLLI16)
+DECLARE_INSN(smal, MATCH_SMAL, MASK_SMAL)
+DECLARE_INSN(smalbb, MATCH_SMALBB, MASK_SMALBB)
+DECLARE_INSN(smalbt, MATCH_SMALBT, MASK_SMALBT)
+DECLARE_INSN(smaltt, MATCH_SMALTT, MASK_SMALTT)
+DECLARE_INSN(smalda, MATCH_SMALDA, MASK_SMALDA)
+DECLARE_INSN(smalxda, MATCH_SMALXDA, MASK_SMALXDA)
+DECLARE_INSN(smalds, MATCH_SMALDS, MASK_SMALDS)
+DECLARE_INSN(smaldrs, MATCH_SMALDRS, MASK_SMALDRS)
+DECLARE_INSN(smalxds, MATCH_SMALXDS, MASK_SMALXDS)
+DECLARE_INSN(smar64, MATCH_SMAR64, MASK_SMAR64)
+DECLARE_INSN(smaqa, MATCH_SMAQA, MASK_SMAQA)
+DECLARE_INSN(smaqa_su, MATCH_SMAQA_SU, MASK_SMAQA_SU)
+DECLARE_INSN(smax8, MATCH_SMAX8, MASK_SMAX8)
+DECLARE_INSN(smax16, MATCH_SMAX16, MASK_SMAX16)
+DECLARE_INSN(smbb16, MATCH_SMBB16, MASK_SMBB16)
+DECLARE_INSN(smbt16, MATCH_SMBT16, MASK_SMBT16)
+DECLARE_INSN(smtt16, MATCH_SMTT16, MASK_SMTT16)
+DECLARE_INSN(smds, MATCH_SMDS, MASK_SMDS)
+DECLARE_INSN(smdrs, MATCH_SMDRS, MASK_SMDRS)
+DECLARE_INSN(smxds, MATCH_SMXDS, MASK_SMXDS)
+DECLARE_INSN(smin8, MATCH_SMIN8, MASK_SMIN8)
+DECLARE_INSN(smin16, MATCH_SMIN16, MASK_SMIN16)
+DECLARE_INSN(smmul, MATCH_SMMUL, MASK_SMMUL)
+DECLARE_INSN(smmul_u, MATCH_SMMUL_U, MASK_SMMUL_U)
+DECLARE_INSN(smmwb, MATCH_SMMWB, MASK_SMMWB)
+DECLARE_INSN(smmwb_u, MATCH_SMMWB_U, MASK_SMMWB_U)
+DECLARE_INSN(smmwt, MATCH_SMMWT, MASK_SMMWT)
+DECLARE_INSN(smmwt_u, MATCH_SMMWT_U, MASK_SMMWT_U)
+DECLARE_INSN(smslda, MATCH_SMSLDA, MASK_SMSLDA)
+DECLARE_INSN(smslxda, MATCH_SMSLXDA, MASK_SMSLXDA)
+DECLARE_INSN(smsr64, MATCH_SMSR64, MASK_SMSR64)
+DECLARE_INSN(smul8, MATCH_SMUL8, MASK_SMUL8)
+DECLARE_INSN(smulx8, MATCH_SMULX8, MASK_SMULX8)
+DECLARE_INSN(smul16, MATCH_SMUL16, MASK_SMUL16)
+DECLARE_INSN(smulx16, MATCH_SMULX16, MASK_SMULX16)
+DECLARE_INSN(sra_u, MATCH_SRA_U, MASK_SRA_U)
+DECLARE_INSN(srai_u, MATCH_SRAI_U, MASK_SRAI_U)
+DECLARE_INSN(sra8, MATCH_SRA8, MASK_SRA8)
+DECLARE_INSN(sra8_u, MATCH_SRA8_U, MASK_SRA8_U)
+DECLARE_INSN(srai8, MATCH_SRAI8, MASK_SRAI8)
+DECLARE_INSN(srai8_u, MATCH_SRAI8_U, MASK_SRAI8_U)
+DECLARE_INSN(sra16, MATCH_SRA16, MASK_SRA16)
+DECLARE_INSN(sra16_u, MATCH_SRA16_U, MASK_SRA16_U)
+DECLARE_INSN(srai16, MATCH_SRAI16, MASK_SRAI16)
+DECLARE_INSN(srai16_u, MATCH_SRAI16_U, MASK_SRAI16_U)
+DECLARE_INSN(srl8, MATCH_SRL8, MASK_SRL8)
+DECLARE_INSN(srl8_u, MATCH_SRL8_U, MASK_SRL8_U)
+DECLARE_INSN(srli8, MATCH_SRLI8, MASK_SRLI8)
+DECLARE_INSN(srli8_u, MATCH_SRLI8_U, MASK_SRLI8_U)
+DECLARE_INSN(srl16, MATCH_SRL16, MASK_SRL16)
+DECLARE_INSN(srl16_u, MATCH_SRL16_U, MASK_SRL16_U)
+DECLARE_INSN(srli16, MATCH_SRLI16, MASK_SRLI16)
+DECLARE_INSN(srli16_u, MATCH_SRLI16_U, MASK_SRLI16_U)
+DECLARE_INSN(stas16, MATCH_STAS16, MASK_STAS16)
+DECLARE_INSN(stsa16, MATCH_STSA16, MASK_STSA16)
+DECLARE_INSN(sub8, MATCH_SUB8, MASK_SUB8)
+DECLARE_INSN(sub16, MATCH_SUB16, MASK_SUB16)
+DECLARE_INSN(sub64, MATCH_SUB64, MASK_SUB64)
+DECLARE_INSN(sunpkd810, MATCH_SUNPKD810, MASK_SUNPKD810)
+DECLARE_INSN(sunpkd820, MATCH_SUNPKD820, MASK_SUNPKD820)
+DECLARE_INSN(sunpkd830, MATCH_SUNPKD830, MASK_SUNPKD830)
+DECLARE_INSN(sunpkd831, MATCH_SUNPKD831, MASK_SUNPKD831)
+DECLARE_INSN(sunpkd832, MATCH_SUNPKD832, MASK_SUNPKD832)
+DECLARE_INSN(swap8, MATCH_SWAP8, MASK_SWAP8)
+DECLARE_INSN(uclip8, MATCH_UCLIP8, MASK_UCLIP8)
+DECLARE_INSN(uclip16, MATCH_UCLIP16, MASK_UCLIP16)
+DECLARE_INSN(uclip32, MATCH_UCLIP32, MASK_UCLIP32)
+DECLARE_INSN(ucmple8, MATCH_UCMPLE8, MASK_UCMPLE8)
+DECLARE_INSN(ucmple16, MATCH_UCMPLE16, MASK_UCMPLE16)
+DECLARE_INSN(ucmplt8, MATCH_UCMPLT8, MASK_UCMPLT8)
+DECLARE_INSN(ucmplt16, MATCH_UCMPLT16, MASK_UCMPLT16)
+DECLARE_INSN(ukadd8, MATCH_UKADD8, MASK_UKADD8)
+DECLARE_INSN(ukadd16, MATCH_UKADD16, MASK_UKADD16)
+DECLARE_INSN(ukadd64, MATCH_UKADD64, MASK_UKADD64)
+DECLARE_INSN(ukaddh, MATCH_UKADDH, MASK_UKADDH)
+DECLARE_INSN(ukaddw, MATCH_UKADDW, MASK_UKADDW)
+DECLARE_INSN(ukcras16, MATCH_UKCRAS16, MASK_UKCRAS16)
+DECLARE_INSN(ukcrsa16, MATCH_UKCRSA16, MASK_UKCRSA16)
+DECLARE_INSN(ukmar64, MATCH_UKMAR64, MASK_UKMAR64)
+DECLARE_INSN(ukmsr64, MATCH_UKMSR64, MASK_UKMSR64)
+DECLARE_INSN(ukstas16, MATCH_UKSTAS16, MASK_UKSTAS16)
+DECLARE_INSN(ukstsa16, MATCH_UKSTSA16, MASK_UKSTSA16)
+DECLARE_INSN(uksub8, MATCH_UKSUB8, MASK_UKSUB8)
+DECLARE_INSN(uksub16, MATCH_UKSUB16, MASK_UKSUB16)
+DECLARE_INSN(uksub64, MATCH_UKSUB64, MASK_UKSUB64)
+DECLARE_INSN(uksubh, MATCH_UKSUBH, MASK_UKSUBH)
+DECLARE_INSN(uksubw, MATCH_UKSUBW, MASK_UKSUBW)
+DECLARE_INSN(umar64, MATCH_UMAR64, MASK_UMAR64)
+DECLARE_INSN(umaqa, MATCH_UMAQA, MASK_UMAQA)
+DECLARE_INSN(umax8, MATCH_UMAX8, MASK_UMAX8)
+DECLARE_INSN(umax16, MATCH_UMAX16, MASK_UMAX16)
+DECLARE_INSN(umin8, MATCH_UMIN8, MASK_UMIN8)
+DECLARE_INSN(umin16, MATCH_UMIN16, MASK_UMIN16)
+DECLARE_INSN(umsr64, MATCH_UMSR64, MASK_UMSR64)
+DECLARE_INSN(umul8, MATCH_UMUL8, MASK_UMUL8)
+DECLARE_INSN(umulx8, MATCH_UMULX8, MASK_UMULX8)
+DECLARE_INSN(umul16, MATCH_UMUL16, MASK_UMUL16)
+DECLARE_INSN(umulx16, MATCH_UMULX16, MASK_UMULX16)
+DECLARE_INSN(uradd8, MATCH_URADD8, MASK_URADD8)
+DECLARE_INSN(uradd16, MATCH_URADD16, MASK_URADD16)
+DECLARE_INSN(uradd64, MATCH_URADD64, MASK_URADD64)
+DECLARE_INSN(uraddw, MATCH_URADDW, MASK_URADDW)
+DECLARE_INSN(urcras16, MATCH_URCRAS16, MASK_URCRAS16)
+DECLARE_INSN(urcrsa16, MATCH_URCRSA16, MASK_URCRSA16)
+DECLARE_INSN(urstas16, MATCH_URSTAS16, MASK_URSTAS16)
+DECLARE_INSN(urstsa16, MATCH_URSTSA16, MASK_URSTSA16)
+DECLARE_INSN(ursub8, MATCH_URSUB8, MASK_URSUB8)
+DECLARE_INSN(ursub16, MATCH_URSUB16, MASK_URSUB16)
+DECLARE_INSN(ursub64, MATCH_URSUB64, MASK_URSUB64)
+DECLARE_INSN(ursubw, MATCH_URSUBW, MASK_URSUBW)
+DECLARE_INSN(wexti, MATCH_WEXTI, MASK_WEXTI)
+DECLARE_INSN(wext, MATCH_WEXT, MASK_WEXT)
+DECLARE_INSN(zunpkd810, MATCH_ZUNPKD810, MASK_ZUNPKD810)
+DECLARE_INSN(zunpkd820, MATCH_ZUNPKD820, MASK_ZUNPKD820)
+DECLARE_INSN(zunpkd830, MATCH_ZUNPKD830, MASK_ZUNPKD830)
+DECLARE_INSN(zunpkd831, MATCH_ZUNPKD831, MASK_ZUNPKD831)
+DECLARE_INSN(zunpkd832, MATCH_ZUNPKD832, MASK_ZUNPKD832)
+DECLARE_INSN(add32, MATCH_ADD32, MASK_ADD32)
+DECLARE_INSN(cras32, MATCH_CRAS32, MASK_CRAS32)
+DECLARE_INSN(crsa32, MATCH_CRSA32, MASK_CRSA32)
+DECLARE_INSN(kabs32, MATCH_KABS32, MASK_KABS32)
+DECLARE_INSN(kadd32, MATCH_KADD32, MASK_KADD32)
+DECLARE_INSN(kcras32, MATCH_KCRAS32, MASK_KCRAS32)
+DECLARE_INSN(kcrsa32, MATCH_KCRSA32, MASK_KCRSA32)
+DECLARE_INSN(kdmbb16, MATCH_KDMBB16, MASK_KDMBB16)
+DECLARE_INSN(kdmbt16, MATCH_KDMBT16, MASK_KDMBT16)
+DECLARE_INSN(kdmtt16, MATCH_KDMTT16, MASK_KDMTT16)
+DECLARE_INSN(kdmabb16, MATCH_KDMABB16, MASK_KDMABB16)
+DECLARE_INSN(kdmabt16, MATCH_KDMABT16, MASK_KDMABT16)
+DECLARE_INSN(kdmatt16, MATCH_KDMATT16, MASK_KDMATT16)
+DECLARE_INSN(khmbb16, MATCH_KHMBB16, MASK_KHMBB16)
+DECLARE_INSN(khmbt16, MATCH_KHMBT16, MASK_KHMBT16)
+DECLARE_INSN(khmtt16, MATCH_KHMTT16, MASK_KHMTT16)
+DECLARE_INSN(kmabb32, MATCH_KMABB32, MASK_KMABB32)
+DECLARE_INSN(kmabt32, MATCH_KMABT32, MASK_KMABT32)
+DECLARE_INSN(kmatt32, MATCH_KMATT32, MASK_KMATT32)
+DECLARE_INSN(kmaxda32, MATCH_KMAXDA32, MASK_KMAXDA32)
+DECLARE_INSN(kmda32, MATCH_KMDA32, MASK_KMDA32)
+DECLARE_INSN(kmxda32, MATCH_KMXDA32, MASK_KMXDA32)
+DECLARE_INSN(kmads32, MATCH_KMADS32, MASK_KMADS32)
+DECLARE_INSN(kmadrs32, MATCH_KMADRS32, MASK_KMADRS32)
+DECLARE_INSN(kmaxds32, MATCH_KMAXDS32, MASK_KMAXDS32)
+DECLARE_INSN(kmsda32, MATCH_KMSDA32, MASK_KMSDA32)
+DECLARE_INSN(kmsxda32, MATCH_KMSXDA32, MASK_KMSXDA32)
+DECLARE_INSN(ksll32, MATCH_KSLL32, MASK_KSLL32)
+DECLARE_INSN(kslli32, MATCH_KSLLI32, MASK_KSLLI32)
+DECLARE_INSN(kslra32, MATCH_KSLRA32, MASK_KSLRA32)
+DECLARE_INSN(kslra32_u, MATCH_KSLRA32_U, MASK_KSLRA32_U)
+DECLARE_INSN(kstas32, MATCH_KSTAS32, MASK_KSTAS32)
+DECLARE_INSN(kstsa32, MATCH_KSTSA32, MASK_KSTSA32)
+DECLARE_INSN(ksub32, MATCH_KSUB32, MASK_KSUB32)
+DECLARE_INSN(pkbb32, MATCH_PKBB32, MASK_PKBB32)
+DECLARE_INSN(pkbt32, MATCH_PKBT32, MASK_PKBT32)
+DECLARE_INSN(pktt32, MATCH_PKTT32, MASK_PKTT32)
+DECLARE_INSN(pktb32, MATCH_PKTB32, MASK_PKTB32)
+DECLARE_INSN(radd32, MATCH_RADD32, MASK_RADD32)
+DECLARE_INSN(rcras32, MATCH_RCRAS32, MASK_RCRAS32)
+DECLARE_INSN(rcrsa32, MATCH_RCRSA32, MASK_RCRSA32)
+DECLARE_INSN(rstas32, MATCH_RSTAS32, MASK_RSTAS32)
+DECLARE_INSN(rstsa32, MATCH_RSTSA32, MASK_RSTSA32)
+DECLARE_INSN(rsub32, MATCH_RSUB32, MASK_RSUB32)
+DECLARE_INSN(sll32, MATCH_SLL32, MASK_SLL32)
+DECLARE_INSN(slli32, MATCH_SLLI32, MASK_SLLI32)
+DECLARE_INSN(smax32, MATCH_SMAX32, MASK_SMAX32)
+DECLARE_INSN(smbt32, MATCH_SMBT32, MASK_SMBT32)
+DECLARE_INSN(smtt32, MATCH_SMTT32, MASK_SMTT32)
+DECLARE_INSN(smds32, MATCH_SMDS32, MASK_SMDS32)
+DECLARE_INSN(smdrs32, MATCH_SMDRS32, MASK_SMDRS32)
+DECLARE_INSN(smxds32, MATCH_SMXDS32, MASK_SMXDS32)
+DECLARE_INSN(smin32, MATCH_SMIN32, MASK_SMIN32)
+DECLARE_INSN(sra32, MATCH_SRA32, MASK_SRA32)
+DECLARE_INSN(sra32_u, MATCH_SRA32_U, MASK_SRA32_U)
+DECLARE_INSN(srai32, MATCH_SRAI32, MASK_SRAI32)
+DECLARE_INSN(srai32_u, MATCH_SRAI32_U, MASK_SRAI32_U)
+DECLARE_INSN(sraiw_u, MATCH_SRAIW_U, MASK_SRAIW_U)
+DECLARE_INSN(srl32, MATCH_SRL32, MASK_SRL32)
+DECLARE_INSN(srl32_u, MATCH_SRL32_U, MASK_SRL32_U)
+DECLARE_INSN(srli32, MATCH_SRLI32, MASK_SRLI32)
+DECLARE_INSN(srli32_u, MATCH_SRLI32_U, MASK_SRLI32_U)
+DECLARE_INSN(stas32, MATCH_STAS32, MASK_STAS32)
+DECLARE_INSN(stsa32, MATCH_STSA32, MASK_STSA32)
+DECLARE_INSN(sub32, MATCH_SUB32, MASK_SUB32)
+DECLARE_INSN(ukadd32, MATCH_UKADD32, MASK_UKADD32)
+DECLARE_INSN(ukcras32, MATCH_UKCRAS32, MASK_UKCRAS32)
+DECLARE_INSN(ukcrsa32, MATCH_UKCRSA32, MASK_UKCRSA32)
+DECLARE_INSN(ukstas32, MATCH_UKSTAS32, MASK_UKSTAS32)
+DECLARE_INSN(ukstsa32, MATCH_UKSTSA32, MASK_UKSTSA32)
+DECLARE_INSN(uksub32, MATCH_UKSUB32, MASK_UKSUB32)
+DECLARE_INSN(umax32, MATCH_UMAX32, MASK_UMAX32)
+DECLARE_INSN(umin32, MATCH_UMIN32, MASK_UMIN32)
+DECLARE_INSN(uradd32, MATCH_URADD32, MASK_URADD32)
+DECLARE_INSN(urcras32, MATCH_URCRAS32, MASK_URCRAS32)
+DECLARE_INSN(urcrsa32, MATCH_URCRSA32, MASK_URCRSA32)
+DECLARE_INSN(urstas32, MATCH_URSTAS32, MASK_URSTAS32)
+DECLARE_INSN(urstsa32, MATCH_URSTSA32, MASK_URSTSA32)
+DECLARE_INSN(ursub32, MATCH_URSUB32, MASK_URSUB32)
 DECLARE_INSN(vmvnfr_v, MATCH_VMVNFR_V, MASK_VMVNFR_V)
 DECLARE_INSN(vl1r_v, MATCH_VL1R_V, MASK_VL1R_V)
 DECLARE_INSN(vl2r_v, MATCH_VL2R_V, MASK_VL2R_V)
 DECLARE_INSN(vl4r_v, MATCH_VL4R_V, MASK_VL4R_V)
 DECLARE_INSN(vl8r_v, MATCH_VL8R_V, MASK_VL8R_V)
+DECLARE_INSN(vle1_v, MATCH_VLE1_V, MASK_VLE1_V)
+DECLARE_INSN(vse1_v, MATCH_VSE1_V, MASK_VSE1_V)
+DECLARE_INSN(vfredsum_vs, MATCH_VFREDSUM_VS, MASK_VFREDSUM_VS)
+DECLARE_INSN(vfwredsum_vs, MATCH_VFWREDSUM_VS, MASK_VFWREDSUM_VS)
+DECLARE_INSN(vpopc_m, MATCH_VPOPC_M, MASK_VPOPC_M)
 #endif
 #ifdef DECLARE_CSR
 DECLARE_CSR(fflags, CSR_FFLAGS)
 DECLARE_CSR(frm, CSR_FRM)
 DECLARE_CSR(fcsr, CSR_FCSR)
-DECLARE_CSR(ustatus, CSR_USTATUS)
-DECLARE_CSR(uie, CSR_UIE)
-DECLARE_CSR(utvec, CSR_UTVEC)
 DECLARE_CSR(vstart, CSR_VSTART)
 DECLARE_CSR(vxsat, CSR_VXSAT)
 DECLARE_CSR(vxrm, CSR_VXRM)
 DECLARE_CSR(vcsr, CSR_VCSR)
-DECLARE_CSR(uscratch, CSR_USCRATCH)
-DECLARE_CSR(uepc, CSR_UEPC)
-DECLARE_CSR(ucause, CSR_UCAUSE)
-DECLARE_CSR(utval, CSR_UTVAL)
-DECLARE_CSR(uip, CSR_UIP)
+DECLARE_CSR(seed, CSR_SEED)
 DECLARE_CSR(cycle, CSR_CYCLE)
 DECLARE_CSR(time, CSR_TIME)
 DECLARE_CSR(instret, CSR_INSTRET)
@@ -2870,6 +4397,7 @@ DECLARE_CSR(scause, CSR_SCAUSE)
 DECLARE_CSR(stval, CSR_STVAL)
 DECLARE_CSR(sip, CSR_SIP)
 DECLARE_CSR(satp, CSR_SATP)
+DECLARE_CSR(scontext, CSR_SCONTEXT)
 DECLARE_CSR(vsstatus, CSR_VSSTATUS)
 DECLARE_CSR(vsie, CSR_VSIE)
 DECLARE_CSR(vstvec, CSR_VSTVEC)
@@ -2891,6 +4419,7 @@ DECLARE_CSR(hip, CSR_HIP)
 DECLARE_CSR(hvip, CSR_HVIP)
 DECLARE_CSR(htinst, CSR_HTINST)
 DECLARE_CSR(hgatp, CSR_HGATP)
+DECLARE_CSR(hcontext, CSR_HCONTEXT)
 DECLARE_CSR(hgeip, CSR_HGEIP)
 DECLARE_CSR(utvt, CSR_UTVT)
 DECLARE_CSR(unxti, CSR_UNXTI)
@@ -2946,6 +4475,10 @@ DECLARE_CSR(tselect, CSR_TSELECT)
 DECLARE_CSR(tdata1, CSR_TDATA1)
 DECLARE_CSR(tdata2, CSR_TDATA2)
 DECLARE_CSR(tdata3, CSR_TDATA3)
+DECLARE_CSR(tinfo, CSR_TINFO)
+DECLARE_CSR(tcontrol, CSR_TCONTROL)
+DECLARE_CSR(mcontext, CSR_MCONTEXT)
+DECLARE_CSR(mscontext, CSR_MSCONTEXT)
 DECLARE_CSR(dcsr, CSR_DCSR)
 DECLARE_CSR(dpc, CSR_DPC)
 DECLARE_CSR(dscratch0, CSR_DSCRATCH0)