- changed jtag_add_reset errors to warnings

- removed extra jtag reset warnings from arm7_9 and cortex_m3

git-svn-id: svn://svn.berlios.de/openocd/trunk@520 b42882b7-edfa-0310-969c-e2dbd0fdcd60

diff --git a/src/jtag/jtag.c b/src/jtag/jtag.c
index 7d0dcab9d80ce91f33b6a43733815db16d691886..a27396a1df85bf345f64621e8925a0be76280d1d 100644 (file)
--- a/src/jtag/jtag.c
+++ b/src/jtag/jtag.c
@@ -899,7 +899,7 @@ int jtag_add_reset(int req_trst, int req_srst)
        /* if SRST pulls TRST, we can't fulfill srst == 1 with trst == 0 */
        if (((jtag_reset_config & RESET_SRST_PULLS_TRST) && (req_srst == 1)) && (req_trst == 0))
        {
-               ERROR("requested reset would assert trst");
+               WARNING("requested reset would assert trst");
                return ERROR_JTAG_RESET_WOULD_ASSERT_TRST;
        }
                
@@ -912,7 +912,7 @@ int jtag_add_reset(int req_trst, int req_srst)
        
        if (req_srst && !(jtag_reset_config & RESET_HAS_SRST))
        {
-               ERROR("requested nSRST assertion, but the current configuration doesn't support this");
+               WARNING("requested nSRST assertion, but the current configuration doesn't support this");
                return ERROR_JTAG_RESET_CANT_SRST;
        }
        

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 5ce1db5671d50d254448c9826fcd74382a73143b..ed2945b052f82faeded9bf914c8f0fdc17bf6fd6 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -750,7 +750,6 @@ int arm7_9_assert_reset(target_t *target)
                {
                        if (retval == ERROR_JTAG_RESET_CANT_SRST)
                        {
-                               WARNING("can't assert srst");
                                return retval;
                        }
                        else
@@ -779,7 +778,6 @@ int arm7_9_assert_reset(target_t *target)
                        
                        if (retval == ERROR_JTAG_RESET_CANT_SRST)
                        {
-                               WARNING("can't assert srst");
                                return retval;
                        }
                        else if (retval != ERROR_OK)

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index d7603678216715d1f42c8875c43b6dd377d7a3b1..0209f0f46f00a0d3dbd42a46626156e109c4611d 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -731,7 +731,6 @@ int cortex_m3_assert_reset(target_t *target)
                {
                        if (retval == ERROR_JTAG_RESET_CANT_SRST)
                        {
-                               WARNING("can't assert srst");
                                return retval;
                        }
                        else
@@ -745,7 +744,6 @@ int cortex_m3_assert_reset(target_t *target)
                {
                        if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
                        {
-                               WARNING("srst resets test logic, too");
                                retval = jtag_add_reset(1, 1);
                        }
                }
@@ -756,13 +754,11 @@ int cortex_m3_assert_reset(target_t *target)
                {
                        if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
                        {
-                               WARNING("srst resets test logic, too");
                                retval = jtag_add_reset(1, 1);
                        }
                        
                        if (retval == ERROR_JTAG_RESET_CANT_SRST)
                        {
-                               WARNING("can't assert srsrt");
                                return retval;
                        }
                        else if (retval != ERROR_OK)
@@ -1136,16 +1132,16 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ
                        ERROR("JTAG failure %i",retval);
                        return ERROR_JTAG_DEVICE_ERROR;
                }
-               /* DEBUG("load from core reg %i  value 0x%x",num,*value); */
+               DEBUG("load from core reg %i  value 0x%x",num,*value);
        }
        else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
        {
                /* read other registers */
-               /* cortex_m3_MRS(struct target_s *target, int num, u32* value) */
                u32 savedram;
                u32 SYSm;
                u32 instr;
                SYSm = num & 0x1F;
+               
                ahbap_read_system_u32(swjdp, 0x20000000, &savedram);
                instr = ARMV7M_T_MRS(0, SYSm);
                ahbap_write_system_u32(swjdp, 0x20000000, ARMV7M_T_MRS(0, SYSm));
@@ -1158,7 +1154,10 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ
                swjdp_transaction_endcheck(swjdp);
                DEBUG("load from special reg %i value 0x%x", SYSm, *value);
        }
-       else return ERROR_INVALID_ARGUMENTS;
+       else
+       {
+               return ERROR_INVALID_ARGUMENTS;
+       }
        
        return ERROR_OK;
 }
@@ -1190,6 +1189,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty
                u32 SYSm;
                u32 instr;
                SYSm = num & 0x1F;
+               
                ahbap_read_system_u32(swjdp, 0x20000000, &savedram);
                instr = ARMV7M_T_MSR(SYSm, 0);
                ahbap_write_system_u32(swjdp, 0x20000000, ARMV7M_T_MSR(SYSm, 0));
@@ -1203,7 +1203,10 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty
                swjdp_transaction_endcheck(swjdp);
                DEBUG("write special reg %i value 0x%x ", SYSm, value);
        }
-       else return ERROR_INVALID_ARGUMENTS;
+       else
+       {
+               return ERROR_INVALID_ARGUMENTS;
+       }
        
        return ERROR_OK;        
 }