You're ready to go :)
-To run the gdb server, do (you do not need sudo if you have set up
-permissions correctly):
+COMPILING
+~~~~~~~~~
+This project was converted to Autotools by a well meaning individual. The
+following steps will build the project for you.
+
+$ ./autogen.sh
+$ ./configure
+$ make
+
+USING THE GDBSERVER
+~~~~~~~~~~~~~~~~~~~
+To run the gdb server: (you do not need sudo if you have set up
+permissions correctly)
+
$ make && [sudo] ./st-util
There are a few options:
-p 4242, --listen_port=1234
Set the gdb server listen port. (default port: 4242)
-Then, in gdb: (remember, you need to run an _ARM_ gdb, not an x86 gdb)
-(gdb) target remote :4242
+Then, in your project directory, someting like this...
+(remember, you need to run an _ARM_ gdb, not an x86 gdb)
+
+$ arm-none-eabi-gdb fancyblink.elf
+...
+(gdb) tar extended-remote :4242
+...
+(gdb) load
+Loading section .text, size 0x458 lma 0x8000000
+Loading section .data, size 0x8 lma 0x8000458
+Start address 0x80001c1, load size 1120
+Transfer rate: 1 KB/sec, 560 bytes/write.
+(gdb)
+...
+(gdb) continue
Have fun!
\begin{itemize}
\item libusb-1.0
\item pkg-config
+\item autotools
\end{itemize}
\paragraph{}
\begin{small}
\begin{lstlisting}[frame=tb]
$> cd stlink.git
-$> make
+$> ./autogen.sh
+$> ./configure
+$> make
\end{lstlisting}
\end{small}
It includes:
\begin{itemize}
\item a communication library (stlink.git/libstlink.a),
-\item a GDB server (stlink.git/gdbserver/st-util),
-\item a flash manipulation tool (stlink.git/flash/flash).
+\item a GDB server (stlink.git/st-util),
+\item a flash manipulation tool (stlink.git/st-flash).
\end{itemize}
\newpage
-\section{Building and running a program in SRAM}
+\section{Using the GDB server}
\paragraph{}
-A simple LED blinking example is provided in the example directory. It is built using:\\
-\begin{small}
-\begin{lstlisting}[frame=tb]
-cd stlink.git/example/blink ;
-PATH=$TOOLCHAIN_PATH/bin:$PATH make
-\end{lstlisting}
-\end{small}
-This builds three files, one for each of the Discovery boards currently
-available, linked to run from SRAM. (So no risk of overwriting anything you didn't mean to)
-These blink examples can safely be used to verify that:
+This assumes you have got the libopencm3 project downloaded in [ocm3]. The
+libopencm3 project has some good, reliable examples for each of the Discovery boards.
+
+Even if you don't plan on using libopencm3, the examples they provide will help you
+verify that:
\begin{itemize}
\item Your installed toolchain is capable of compiling for cortex M3/M4 targets
Then, GDB can be used to interact with the kit:\\
\begin{small}
\begin{lstlisting}[frame=tb]
-$> $TOOLCHAIN_PATH/bin/arm-none-eabi-gdb
+$> $TOOLCHAIN_PATH/bin/arm-none-eabi-gdb example_file.elf
\end{lstlisting}
\end{small}
From GDB, connect to the server using:\\
\begin{small}
\begin{lstlisting}[frame=tb]
-$> target extended localhost:4242
+(gdb) target extended localhost:4242
\end{lstlisting}
\end{small}
\paragraph{}
-By default, the program was linked such that the base address is 0x20000000. From the architecture
-memory map, GDB knows this address belongs to SRAM. To load the program in SRAM, simply use:\\
+GDB has memory maps for as many chips as it knows about, and will load your project
+into either flash or SRAM based on how the project was linked. Linking projects
+to boot from SRAM is beyond the scope of this document.
+
+Because of these built in memory maps, after specifying the .elf at the command line, now
+we can simply "load" the target:\\
\begin{small}
\begin{lstlisting}[frame=tb]
-$> # Choose one as appropriate for your Discovery kit
-$> load blink_32L.elf | load blink_32VL.elf | load blink_F4.elf
+(gdb) load
\end{lstlisting}
\end{small}
\paragraph{}
-GDB automatically set the PC register to the correct value, 0x20000000 in this case. Then, you
-can run the program using:\\
+st-util will load all sections into their appropriate addresses, and "correctly" set the PC
+register. So, to run your freshly loaded program, simply "continue"\\
\begin{small}
\begin{lstlisting}[frame=tb]
-$> continue
+(gdb) continue
\end{lstlisting}
\end{small}
\paragraph{}
-All the LEDs on the board should now be blinking in time (those leds are near the user and reset buttons).
+Your program should now be running, and, if you used one of the blinking examples from
+libopencm3, the LEDs on the board should be blinking for you.
\newpage
\section{Building and flashing a program}
\paragraph{}
-FLASH memory reading and writing is done by a separate tool, as shown below:\\
+If you want to simply flash binary files to arbitrary sections of memory, or
+read arbitary addresses of memory out to a binary file, use the st-flash tool,
+as shown below:\\
\begin{small}
\begin{lstlisting}[frame=tb]
-# change to the flash tool directory
-$> cd stlink.git/flash ;
# stlinkv1 command to read 4096 from flash into out.bin
-$> ./flash read v1 out.bin 0x8000000 4096
+$> ./st-flash read v1 out.bin 0x8000000 4096
# stlinkv2 command
-$> ./flash read out.bin 0x8000000 4096
+$> ./st-flash read out.bin 0x8000000 4096
# stlinkv1 command to write the file in.bin into flash
-$> ./flash write v1 in.bin 0x8000000
+$> ./st-flash write v1 in.bin 0x8000000
# stlinkv2 command
-$> ./flash write in.bin 0x8000000
+$> ./st-flash write in.bin 0x8000000
\end{lstlisting}
\end{small}
\paragraph{}
-A LED blinking example is provided:\\
+Of course, you can use this instead of the gdb server, if you prefer. Just remember
+to use the ".bin" image, rather than the .elf file.\\
\begin{small}
\begin{lstlisting}[frame=tb]
-# build the example, resulting in blink.bin
-$> cd stlink.git/example/blink_flash
-$> PATH=$TOOLCHAIN_PATH:$PATH make CONFIG_STM32L_DISCOVERY=1
# write blink.bin into FLASH
-$> sudo ./flash write blink.bin 0x08000000
+$> [sudo] ./st-flash write fancy_blink.bin 0x08000000
\end{lstlisting}
\end{small}
\paragraph{}
Upon reset, the board LEDs should be blinking.
-\newpage
-\section{Building and installing the CHIBIOS kernel}
-\paragraph{}
-CHIBIOS is an open source RTOS. More information can be found on the project website:
-\begin{center}
-http://www.chibios.org/dokuwiki/doku.php
-\end{center}
-
-\paragraph{}
-It supports several boards, including the STM32L DISCOVERY kit:
-\begin{center}
-http://www.chibios.org/dokuwiki/doku.php?id=chibios:articles:stm32l\_discovery
-\end{center}
-
-\paragraph{}
-The installation procedure is detailed below:\\
-\begin{small}
-\begin{lstlisting}[frame=tb]
-# checkout and build CHIBIOS for STM32L DISCOVERY kits
-svn checkout https://chibios.svn.sourceforge.net/svnroot/chibios/trunk
-cd chibios/trunk/demos/ARMCM3-STM32L152-DISCOVERY
-PATH=$TOOLCHAIN_PATH:$PATH make
-
-# flash the image into STM32L
-sudo ./flash write build/ch.bin 0x08000000
-\end{lstlisting}
-\end{small}
-
\newpage
\section{Notes}
if you want to disassemble the code at 0x20000000, use:\\
\begin{small}
\begin{lstlisting}[frame=tb]
-$> disassemble 0x20000001
-\end{lstlisting}
-\end{small}
-
-
-\subsection{libstm32l\_discovery}
-\paragraph{}
-The repository includes the STM32L discovery library source code from ST original firmware packages,
-available here:\\
-\begin{small}
-\begin{lstlisting}[frame=tb]
-http://www.st.com/internet/evalboard/product/250990.jsp#FIRMWARE
-\end{lstlisting}
-\end{small}
-
-\paragraph{}
-It is built using:\\
-\begin{small}
-\begin{lstlisting}[frame=tb]
-$> cd stlink.git/example/libstm32l_discovery/build
-$> make
-\end{lstlisting}
-\end{small}
-
-\paragraph{}
-An example using the library can be built using:\\
-\begin{small}
-\begin{lstlisting}[frame=tb]
-$> cd stlink.git/example/lcd
-$> make
+(gdb) disassemble 0x20000001
\end{lstlisting}
\end{small}
documentation related to the STM32L mcu
\item http://www.st.com/internet/evalboard/product/250990.jsp\\
documentation related to the STM32L discovery kit
+\item http://www.libopencm3.org\\
+ libopencm3, a project providing a firmware library, with solid examples for Cortex
+ M3, M4 and M0 processors from any vendor.
\end{itemize}
\end{document}
+++ /dev/null
-EXECUTABLE=dac.elf
-BIN_IMAGE=dac.bin
-
-CC=arm-none-eabi-gcc
-OBJCOPY=arm-none-eabi-objcopy
-
-CFLAGS=-O3 -mlittle-endian -mthumb
-CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY=1
-CFLAGS+=-ffreestanding -nostdlib -nostdinc
-
-# to run from FLASH
-CFLAGS+=-Wl,-T,stm32_flash.ld
-
-PLATFORM=stm32l1xx
-LIBS_STM_PATH=../libs_stm
-
-# stm32l_discovery lib
-CFLAGS+=-I$(LIBS_STM_PATH)/inc/base
-CFLAGS+=-I$(LIBS_STM_PATH)/inc/core_support
-CFLAGS+=-I$(LIBS_STM_PATH)/inc/device_support
-CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM)
-
-LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32_stdperiph_l1xx
-
-all: $(BIN_IMAGE)
-
-$(BIN_IMAGE): $(EXECUTABLE)
- $(OBJCOPY) -O binary $^ $@
-
-$(EXECUTABLE): main.c system_stm32l1xx.c startup_stm32l1xx_md.s
- $(CC) $(CFLAGS) $^ -o $@ $(LDFLAGS)
-
-clean:
- rm -rf $(EXECUTABLE)
- rm -rf $(BIN_IMAGE)
-
-write: all
- sudo ../../flash/flash write ./dac.bin 0x08000000
-
-.PHONY: all clean write
+++ /dev/null
- /**\r
- ******************************************************************************\r
- * @file discover_board.h\r
- * @author Microcontroller Division\r
- * @version V1.0.2\r
- * @date September-2011\r
- * @brief Input/Output defines\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-\r
-#ifndef __DISCOVER_BOARD_H\r
-#define __DISCOVER_BOARD_H\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-/* #include "stm32l1xx.h" */\r
-\r
-#define bool _Bool\r
-#define FALSE 0\r
-#define TRUE !FALSE\r
-\r
-/* MACROs for SET, RESET or TOGGLE Output port */\r
-\r
-#define GPIO_HIGH(a,b) a->BSRRL = b\r
-#define GPIO_LOW(a,b) a->BSRRH = b\r
-#define GPIO_TOGGLE(a,b) a->ODR ^= b \r
-\r
-#define USERBUTTON_GPIO_PORT GPIOA\r
-#define USERBUTTON_GPIO_PIN GPIO_Pin_0\r
-#define USERBUTTON_GPIO_CLK RCC_AHBPeriph_GPIOA\r
-\r
-#define LD_GPIO_PORT GPIOB\r
-#define LD_GREEN_GPIO_PIN GPIO_Pin_7\r
-#define LD_BLUE_GPIO_PIN GPIO_Pin_6\r
-#define LD_GPIO_PORT_CLK RCC_AHBPeriph_GPIOB\r
-\r
-#define CTN_GPIO_PORT GPIOC\r
-#define CTN_CNTEN_GPIO_PIN GPIO_Pin_13\r
-#define CTN_GPIO_CLK RCC_AHBPeriph_GPIOC\r
-\r
-#define WAKEUP_GPIO_PORT GPIOA\r
-\r
-#define IDD_MEASURE_PORT GPIOA\r
-#define IDD_MEASURE GPIO_Pin_4\r
-\r
-\r
-#endif\r
-\r
-\r
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/* base headers */
-#include "stdint.h"
-
-/* libstm32l_discovery headers */
-#include "stm32l1xx_gpio.h"
-#include "stm32l1xx_adc.h"
-#include "stm32l1xx_dac.h"
-#include "stm32l1xx_lcd.h"
-#include "stm32l1xx_rcc.h"
-#include "stm32l1xx_rtc.h"
-#include "stm32l1xx_exti.h"
-#include "stm32l1xx_pwr.h"
-#include "stm32l1xx_flash.h"
-#include "stm32l1xx_syscfg.h"
-#include "stm32l1xx_dbgmcu.h"
-
-/* board specific macros */
-#include "discover_board.h"
-
-
-/* hardware configuration */
-
-#if CONFIG_STM32VL_DISCOVERY
-
-# define GPIOC 0x40011000 /* port C */
-# define GPIOC_CRH (GPIOC + 0x04) /* port configuration register high */
-# define GPIOC_ODR (GPIOC + 0x0c) /* port output data register */
-
-# define LED_BLUE (1 << 8) /* port C, pin 8 */
-# define LED_GREEN (1 << 9) /* port C, pin 9 */
-
-static inline void setup_leds(void)
-{
- *(volatile uint32_t*)GPIOC_CRH = 0x44444411;
-}
-
-static inline void switch_leds_on(void)
-{
- *(volatile uint32_t*)GPIOC_ODR = LED_BLUE | LED_GREEN;
-}
-
-static inline void switch_leds_off(void)
-{
- *(volatile uint32_t*)GPIOC_ODR = 0;
-}
-
-#elif CONFIG_STM32L_DISCOVERY
-
-# define GPIOB_MODER (GPIOB + 0x00) /* port mode register */
-# define GPIOB_ODR (GPIOB + 0x14) /* port output data register */
-
-# define LED_BLUE (1 << 6) /* port B, pin 6 */
-# define LED_GREEN (1 << 7) /* port B, pin 7 */
-
-static inline void setup_leds(void)
-{
- /* configure port 6 and 7 as output */
- *(volatile uint32_t*)GPIOB_MODER |= (1 << (7 * 2)) | (1 << (6 * 2));
-}
-
-static inline void switch_leds_on(void)
-{
- GPIO_HIGH(LD_GPIO_PORT, LD_GREEN_GPIO_PIN);
- GPIO_HIGH(LD_GPIO_PORT, LD_BLUE_GPIO_PIN);
-}
-
-static inline void switch_leds_off(void)
-{
- GPIO_LOW(LD_GPIO_PORT, LD_GREEN_GPIO_PIN);
- GPIO_LOW(LD_GPIO_PORT, LD_BLUE_GPIO_PIN);
-}
-
-#endif /* otherwise, error */
-
-
-#define delay() \
-do { \
- volatile unsigned int i; \
- for (i = 0; i < 1000000; ++i) \
- __asm__ __volatile__ ("nop\n\t":::"memory"); \
-} while (0)
-
-
-static void RCC_Configuration(void)
-{
- /* HSI is 16mhz RC clock directly fed to SYSCLK (rm00038, figure 9) */
-
- /* enable the HSI clock (high speed internal) */
- RCC_HSICmd(ENABLE);
-
- /* wail til HSI ready */
- while (RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET)
- {}
-
- /* at startup, SYSCLK driven by MSI. set to HSI */
- RCC_SYSCLKConfig(RCC_SYSCLKSource_HSI);
-
- /* set MSI to 4mhz */
- RCC_MSIRangeConfig(RCC_MSIRange_6);
-
- /* turn HSE off */
- RCC_HSEConfig(RCC_HSE_OFF);
- if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
- {
- while (1) ;
- }
-}
-
-
-static void RTC_Configuration(void)
-{
- /* Allow access to the RTC */
- PWR_RTCAccessCmd(ENABLE);
-
- /* Reset Backup Domain */
- RCC_RTCResetCmd(ENABLE);
- RCC_RTCResetCmd(DISABLE);
-
- /* LSE Enable */
- RCC_LSEConfig(RCC_LSE_ON);
-
- /* Wait till LSE is ready */
- while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
- {}
-
- RCC_RTCCLKCmd(ENABLE);
-
- /* LCD Clock Source Selection */
- RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
-
-}
-
-static void setup_dac1(void)
-{
- /* see 10.2 notes */
-
- static GPIO_InitTypeDef GPIO_InitStructure;
- static DAC_InitTypeDef DAC_InitStructure;
-
- /* DAC clock path:
- HSI (16mhz) -> SYSCLK -> HCLK(/1) -> PCLK1(/1)
- */
-
- /* set the AHB clock (HCLK) prescaler to 1 */
- RCC_HCLKConfig(RCC_SYSCLK_Div1);
-
- /* set the low speed APB clock (APB1, ie. PCLK1) prescaler to 1 */
- RCC_PCLK1Config(RCC_HCLK_Div1);
-
- /* enable DAC APB1 clock */
- /* signal connections: HSI(16mhz) -> SYSCLK -> AHB */
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);
-
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; /* GPIO_Pin_5 for channel 2 */
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- DAC_StructInit(&DAC_InitStructure);
- DAC_InitStructure.DAC_Trigger = DAC_Trigger_None;
-#if 0 /* triangle waveform generation */
- DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_Triangle;
- DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_TriangleAmplitude_1;
-#else
- DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;
- DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
-#endif
- DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
- DAC_Init(DAC_Channel_1, &DAC_InitStructure);
-
- /* enable dac channel */
- DAC_Cmd(DAC_Channel_1, ENABLE);
-}
-
-static inline void set_dac1_mv(unsigned int mv)
-{
- /* mv the millivolts */
-
- /* vref in millivolts */
- /* #define CONFIG_VREF 5000 */
-#define CONFIG_VREF 3000
-
- /* resolution in bits */
-#define CONFIG_DAC_RES 12
-
- const uint16_t n = (mv * (1 << (CONFIG_DAC_RES - 1))) / CONFIG_VREF;
- DAC_SetChannel1Data(DAC_Align_12b_R, n);
-}
-
-void main(void)
-{
- static RCC_ClocksTypeDef RCC_Clocks;
- static GPIO_InitTypeDef GPIO_InitStructure;
- static uint16_t dac_value;
- static unsigned int led_state = 0;
-
- /* Configure Clocks for Application need */
- RCC_Configuration();
-
- /* Configure RTC Clocks */
- RTC_Configuration();
-
-#if 0
- /* Set internal voltage regulator to 1.8v */
- PWR_VoltageScalingConfig(PWR_VoltageScaling_Range1);
- /* Wait Until the Voltage Regulator is ready */
- while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET) ;
-#endif
-
- /* configure gpios */
-
- /* Enable GPIOs clock */
- RCC_AHBPeriphClockCmd(LD_GPIO_PORT_CLK, ENABLE);
-
- /* Configure the GPIO_LED pins LD3 & LD4*/
- GPIO_InitStructure.GPIO_Pin = LD_GREEN_GPIO_PIN | LD_BLUE_GPIO_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
- GPIO_Init(LD_GPIO_PORT, &GPIO_InitStructure);
- GPIO_LOW(LD_GPIO_PORT, LD_GREEN_GPIO_PIN);
- GPIO_LOW(LD_GPIO_PORT, LD_BLUE_GPIO_PIN);
-
- setup_dac1();
-
- dac_value = 0;
-
- while (1)
- {
- DAC_SetChannel1Data(DAC_Align_12b_R, dac_value & 0xfff);
- dac_value += 0x10;
-
- if (led_state & 1) switch_leds_on();
- else switch_leds_off();
- led_state ^= 1;
-
- delay();
- }
-}
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file startup_stm32l1xx_md.s\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief STM32L1xx Ultra Low Power Medium-density Devices vector table for \r
- * RIDE7 toolchain.\r
- * This module performs:\r
- * - Set the initial SP\r
- * - Set the initial PC == Reset_Handler,\r
- * - Set the vector table entries with the exceptions ISR address\r
- * - Branches to main in the C library (which eventually\r
- * calls main()).\r
- * After Reset the Cortex-M3 processor is in Thread mode,\r
- * priority is Privileged, and the Stack is set to Main.\r
- *******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ******************************************************************************* \r
- */\r
- \r
- .syntax unified\r
- .cpu cortex-m3\r
- .fpu softvfp\r
- .thumb\r
-\r
-.global g_pfnVectors\r
-.global Default_Handler\r
-\r
-/* start address for the initialization values of the .data section. \r
-defined in linker script */\r
-.word _sidata\r
-/* start address for the .data section. defined in linker script */ \r
-.word _sdata\r
-/* end address for the .data section. defined in linker script */\r
-.word _edata\r
-/* start address for the .bss section. defined in linker script */\r
-.word _sbss\r
-/* end address for the .bss section. defined in linker script */\r
-.word _ebss\r
-\r
-.equ BootRAM, 0xF108F85F\r
-/**\r
- * @brief This is the code that gets called when the processor first\r
- * starts execution following a reset event. Only the absolutely\r
- * necessary set is performed, after which the application\r
- * supplied main() routine is called. \r
- * @param None\r
- * @retval : None\r
-*/\r
-\r
- .section .text.Reset_Handler\r
- .weak Reset_Handler\r
- .type Reset_Handler, %function\r
-Reset_Handler:\r
-/* Copy the data segment initializers from flash to SRAM */ \r
- movs r1, #0\r
- b LoopCopyDataInit\r
-\r
-CopyDataInit:\r
- ldr r3, =_sidata\r
- ldr r3, [r3, r1]\r
- str r3, [r0, r1]\r
- adds r1, r1, #4\r
- \r
-LoopCopyDataInit:\r
- ldr r0, =_sdata\r
- ldr r3, =_edata\r
- adds r2, r0, r1\r
- cmp r2, r3\r
- bcc CopyDataInit\r
- ldr r2, =_sbss\r
- b LoopFillZerobss\r
-/* Zero fill the bss segment. */ \r
-FillZerobss:\r
- movs r3, #0\r
- str r3, [r2], #4\r
- \r
-LoopFillZerobss:\r
- ldr r3, = _ebss\r
- cmp r2, r3\r
- bcc FillZerobss\r
-/* Call the clock system intitialization function.*/\r
-/* let main do the system initialization */\r
- bl SystemInit\r
-/* Call the application's entry point.*/\r
- bl main\r
- bx lr\r
-.size Reset_Handler, .-Reset_Handler\r
-\r
-/**\r
- * @brief This is the code that gets called when the processor receives an \r
- * unexpected interrupt. This simply enters an infinite loop, preserving\r
- * the system state for examination by a debugger.\r
- *\r
- * @param None \r
- * @retval None \r
-*/\r
- .section .text.Default_Handler,"ax",%progbits\r
-Default_Handler:\r
-Infinite_Loop:\r
- b Infinite_Loop\r
- .size Default_Handler, .-Default_Handler\r
-/*******************************************************************************\r
-*\r
-* The minimal vector table for a Cortex M3. Note that the proper constructs\r
-* must be placed on this to ensure that it ends up at physical address\r
-* 0x0000.0000.\r
-*******************************************************************************/ \r
- .section .isr_vector,"a",%progbits\r
- .type g_pfnVectors, %object\r
- .size g_pfnVectors, .-g_pfnVectors\r
- \r
- \r
-g_pfnVectors:\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word SysTick_Handler\r
- .word WWDG_IRQHandler\r
- .word PVD_IRQHandler\r
- .word TAMPER_STAMP_IRQHandler\r
- .word RTC_WKUP_IRQHandler\r
- .word FLASH_IRQHandler\r
- .word RCC_IRQHandler\r
- .word EXTI0_IRQHandler\r
- .word EXTI1_IRQHandler\r
- .word EXTI2_IRQHandler\r
- .word EXTI3_IRQHandler\r
- .word EXTI4_IRQHandler\r
- .word DMA1_Channel1_IRQHandler\r
- .word DMA1_Channel2_IRQHandler\r
- .word DMA1_Channel3_IRQHandler\r
- .word DMA1_Channel4_IRQHandler\r
- .word DMA1_Channel5_IRQHandler\r
- .word DMA1_Channel6_IRQHandler\r
- .word DMA1_Channel7_IRQHandler\r
- .word ADC1_IRQHandler\r
- .word USB_HP_IRQHandler\r
- .word USB_LP_IRQHandler\r
- .word DAC_IRQHandler\r
- .word COMP_IRQHandler\r
- .word EXTI9_5_IRQHandler\r
- .word LCD_IRQHandler\r
- .word TIM9_IRQHandler\r
- .word TIM10_IRQHandler\r
- .word TIM11_IRQHandler\r
- .word TIM2_IRQHandler\r
- .word TIM3_IRQHandler\r
- .word TIM4_IRQHandler\r
- .word I2C1_EV_IRQHandler\r
- .word I2C1_ER_IRQHandler\r
- .word I2C2_EV_IRQHandler\r
- .word I2C2_ER_IRQHandler\r
- .word SPI1_IRQHandler\r
- .word SPI2_IRQHandler\r
- .word USART1_IRQHandler\r
- .word USART2_IRQHandler\r
- .word USART3_IRQHandler\r
- .word EXTI15_10_IRQHandler\r
- .word RTC_Alarm_IRQHandler\r
- .word USB_FS_WKUP_IRQHandler\r
- .word TIM6_IRQHandler\r
- .word TIM7_IRQHandler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word BootRAM /* @0x108. This is for boot in RAM mode for \r
- STM32L15x ULtra Low Power Medium-density devices. */\r
- \r
-/*******************************************************************************\r
-*\r
-* Provide weak aliases for each Exception handler to the Default_Handler. \r
-* As they are weak aliases, any function with the same name will override \r
-* this definition.\r
-*\r
-*******************************************************************************/\r
- \r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
-\r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
-\r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
-\r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-\r
- .weak SysTick_Handler\r
- .thumb_set SysTick_Handler,Default_Handler\r
-\r
- .weak WWDG_IRQHandler\r
- .thumb_set WWDG_IRQHandler,Default_Handler\r
-\r
- .weak PVD_IRQHandler\r
- .thumb_set PVD_IRQHandler,Default_Handler\r
-\r
- .weak TAMPER_STAMP_IRQHandler\r
- .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler\r
-\r
- .weak RTC_WKUP_IRQHandler\r
- .thumb_set RTC_WKUP_IRQHandler,Default_Handler\r
-\r
- .weak FLASH_IRQHandler\r
- .thumb_set FLASH_IRQHandler,Default_Handler\r
-\r
- .weak RCC_IRQHandler\r
- .thumb_set RCC_IRQHandler,Default_Handler\r
-\r
- .weak EXTI0_IRQHandler\r
- .thumb_set EXTI0_IRQHandler,Default_Handler\r
-\r
- .weak EXTI1_IRQHandler\r
- .thumb_set EXTI1_IRQHandler,Default_Handler\r
-\r
- .weak EXTI2_IRQHandler\r
- .thumb_set EXTI2_IRQHandler,Default_Handler\r
-\r
- .weak EXTI3_IRQHandler\r
- .thumb_set EXTI3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI4_IRQHandler\r
- .thumb_set EXTI4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel1_IRQHandler\r
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel2_IRQHandler\r
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel3_IRQHandler\r
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel4_IRQHandler\r
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel5_IRQHandler\r
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel6_IRQHandler\r
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel7_IRQHandler\r
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
-\r
- .weak ADC1_IRQHandler\r
- .thumb_set ADC1_IRQHandler,Default_Handler\r
-\r
- .weak USB_HP_IRQHandler\r
- .thumb_set USB_HP_IRQHandler,Default_Handler\r
-\r
- .weak USB_LP_IRQHandler\r
- .thumb_set USB_LP_IRQHandler,Default_Handler\r
-\r
- .weak DAC_IRQHandler\r
- .thumb_set DAC_IRQHandler,Default_Handler\r
-\r
- .weak COMP_IRQHandler\r
- .thumb_set COMP_IRQHandler,Default_Handler\r
-\r
- .weak EXTI9_5_IRQHandler\r
- .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
-\r
- .weak LCD_IRQHandler\r
- .thumb_set LCD_IRQHandler,Default_Handler\r
- \r
- .weak TIM9_IRQHandler\r
- .thumb_set TIM9_IRQHandler,Default_Handler\r
-\r
- .weak TIM10_IRQHandler\r
- .thumb_set TIM10_IRQHandler,Default_Handler\r
-\r
- .weak TIM11_IRQHandler\r
- .thumb_set TIM11_IRQHandler,Default_Handler\r
-\r
- .weak TIM2_IRQHandler\r
- .thumb_set TIM2_IRQHandler,Default_Handler\r
-\r
- .weak TIM3_IRQHandler\r
- .thumb_set TIM3_IRQHandler,Default_Handler\r
-\r
- .weak TIM4_IRQHandler\r
- .thumb_set TIM4_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_EV_IRQHandler\r
- .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_ER_IRQHandler\r
- .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_EV_IRQHandler\r
- .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_ER_IRQHandler\r
- .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
-\r
- .weak SPI1_IRQHandler\r
- .thumb_set SPI1_IRQHandler,Default_Handler\r
-\r
- .weak SPI2_IRQHandler\r
- .thumb_set SPI2_IRQHandler,Default_Handler\r
-\r
- .weak USART1_IRQHandler\r
- .thumb_set USART1_IRQHandler,Default_Handler\r
-\r
- .weak USART2_IRQHandler\r
- .thumb_set USART2_IRQHandler,Default_Handler\r
-\r
- .weak USART3_IRQHandler\r
- .thumb_set USART3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI15_10_IRQHandler\r
- .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
-\r
- .weak RTC_Alarm_IRQHandler\r
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler\r
-\r
- .weak USB_FS_WKUP_IRQHandler\r
- .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler\r
-\r
- .weak TIM6_IRQHandler\r
- .thumb_set TIM6_IRQHandler,Default_Handler\r
-\r
- .weak TIM7_IRQHandler\r
- .thumb_set TIM7_IRQHandler,Default_Handler\r
-\r
-/******************** (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***/\r
-\r
+++ /dev/null
-/*
-*****************************************************************************
-**
-** File : stm32_flash.ld
-**
-** Abstract : Linker script for STM32L152RB Device with
-** 128KByte FLASH, 16KByte RAM
-**
-** Set heap size, stack size and stack location according
-** to application requirements.
-**
-** Set memory bank area and size if external memory is used.
-**
-** Target : STMicroelectronics STM32
-**
-** Environment : Atollic TrueSTUDIO(R)
-**
-** Distribution: The file is distributed \93as is,\94 without any warranty
-** of any kind.
-**
-** (c)Copyright Atollic AB.
-** You may use this file as-is or modify it according to the needs of your
-** project. Distribution of this file (unmodified or modified) is not
-** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
-** rights to distribute the assembled, compiled & linked contents of this
-** file as part of an application binary file, provided that it is built
-** using the Atollic TrueSTUDIO(R) toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20004000; /* end of 16K RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0; /* required amount of heap */
-_Min_Stack_Size = 0x80; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
- RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K
- MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
- RW_EEPROM (rw) : ORIGIN = 0x08080000, LENGTH = 32
-}
-
-/* Define output sections */
-SECTIONS
-{
- /* The startup code goes first into FLASH */
- .isr_vector :
- {
- . = ALIGN(4);
- KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
- } >FLASH
-
- /* The program code and other data goes into FLASH */
- .text :
- {
- . = ALIGN(4);
- *(.text) /* .text sections (code) */
- *(.text*) /* .text* sections (code) */
- *(.rodata) /* .rodata sections (constants, strings, etc.) */
- *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
- *(.glue_7) /* glue arm to thumb code */
- *(.glue_7t) /* glue thumb to arm code */
- *(.eh_frame)
-
- KEEP (*(.init))
- KEEP (*(.fini))
-
- . = ALIGN(4);
- _etext = .; /* define a global symbols at end of code */
- } >FLASH
-
-
- .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
- .ARM : {
- __exidx_start = .;
- *(.ARM.exidx*)
- __exidx_end = .;
- } >FLASH
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array*))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >FLASH
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array*))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >FLASH
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(.fini_array*))
- KEEP (*(SORT(.fini_array.*)))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } >FLASH
-
- /* used by the startup to initialize data */
- _sidata = .;
-
- /* Initialized data sections goes into RAM, load LMA copy after code */
- .data : AT ( _sidata )
- {
- . = ALIGN(4);
- _sdata = .; /* create a global symbol at data start */
- *(.data) /* .data sections */
- *(.data*) /* .data* sections */
-
- . = ALIGN(4);
- _edata = .; /* define a global symbol at data end */
- } >RAM
-
- /* Uninitialized data section */
- . = ALIGN(4);
- .bss :
- {
- /* This is used by the startup in order to initialize the .bss secion */
- _sbss = .; /* define a global symbol at bss start */
- __bss_start__ = _sbss;
- *(.bss)
- *(.bss*)
- *(COMMON)
-
- . = ALIGN(4);
- _ebss = .; /* define a global symbol at bss end */
- __bss_end__ = _ebss;
- } >RAM
-
- /* User_heap_stack section, used to check that there is enough RAM left */
- ._user_heap_stack :
- {
- . = ALIGN(4);
- PROVIDE ( end = . );
- PROVIDE ( _end = . );
- . = . + _Min_Heap_Size;
- . = . + _Min_Stack_Size;
- . = ALIGN(4);
- } >RAM
-
- /* MEMORY_bank1 section, code must be located here explicitly */
- /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
- .memory_b1_text :
- {
- *(.mb1text) /* .mb1text sections (code) */
- *(.mb1text*) /* .mb1text* sections (code) */
- *(.mb1rodata) /* read-only data (constants) */
- *(.mb1rodata*)
- } >MEMORY_B1
-
- /* Remove information from the standard libraries */
- /DISCARD/ :
- {
- libc.a ( * )
- libm.a ( * )
- libgcc.a ( * )
- }
-
- .ARM.attributes 0 : { *(.ARM.attributes) }
-
- .DataFlash (NOLOAD): {*(.DataFlash)} >RW_EEPROM
-}
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file system_stm32l1xx.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 2-June-2011\r
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.\r
- * This file contains the system clock configuration for STM32L1xx Ultra\r
- * Low Medium-density devices, and is generated by the clock configuration\r
- * tool "STM32L1xx_Clock_Configuration_V1.0.0.xls".\r
- * \r
- * 1. This file provides two functions and one global variable to be called from \r
- * user application:\r
- * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier\r
- * and Divider factors, AHB/APBx prescalers and Flash settings),\r
- * depending on the configuration made in the clock xls tool. \r
- * This function is called at startup just after reset and \r
- * before branch to main program. This call is made inside\r
- * the "startup_stm32l1xx_md.s" file.\r
- * \r
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
- * by the user application to setup the SysTick \r
- * timer or configure other parameters.\r
- * \r
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
- * be called whenever the core clock is changed\r
- * during program execution. \r
- * \r
- * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.\r
- * Then SystemInit() function is called, in "startup_stm32l1xx_md.s" file, to\r
- * configure the system clock before to branch to main program. \r
- * \r
- * 3. If the system clock source selected by user fails to startup, the SystemInit()\r
- * function will do nothing and MSI still used as system clock source. User can \r
- * add some code to deal with this issue inside the SetSysClock() function. \r
- * \r
- * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define\r
- * in "stm32l1xx.h" file. When HSE is used as system clock source, directly or\r
- * through PLL, and you are using different crystal you have to adapt the HSE\r
- * value to your own configuration.\r
- * \r
- * 5. This file configures the system clock as follows: \r
- *=============================================================================\r
- * System Clock Configuration\r
- *=============================================================================\r
- * System clock source | HSI\r
- *----------------------------------------------------------------------------- \r
- * SYSCLK | 16000000 Hz\r
- *----------------------------------------------------------------------------- \r
- * HCLK | 16000000 Hz\r
- *----------------------------------------------------------------------------- \r
- * AHB Prescaler | 1\r
- *----------------------------------------------------------------------------- \r
- * APB1 Prescaler | 1\r
- *----------------------------------------------------------------------------- \r
- * APB2 Prescaler | 1\r
- *----------------------------------------------------------------------------- \r
- * HSE Frequency | 8000000 Hz\r
- *----------------------------------------------------------------------------- \r
- * PLL DIV | Not Used\r
- *----------------------------------------------------------------------------- \r
- * PLL MUL | Not Used\r
- *----------------------------------------------------------------------------- \r
- * VDD | 3.3 V\r
- *----------------------------------------------------------------------------- \r
- * Vcore | 1.8 V (Range 1)\r
- *----------------------------------------------------------------------------- \r
- * Flash Latency | 0 WS\r
- *----------------------------------------------------------------------------- \r
- * Require 48MHz for USB clock | Disabled\r
- *----------------------------------------------------------------------------- \r
- *=============================================================================\r
- ****************************************************************************** \r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */\r
-\r
-/** @addtogroup CMSIS\r
- * @{\r
- */\r
-\r
-/** @addtogroup stm32l1xx_system\r
- * @{\r
- */ \r
- \r
-/** @addtogroup STM32L1xx_System_Private_Includes\r
- * @{\r
- */\r
-\r
-#include "stm32l1xx.h"\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32L1xx_System_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32L1xx_System_Private_Defines\r
- * @{\r
- */\r
-/*!< Uncomment the following line if you need to relocate your vector Table in\r
- Internal SRAM. */ \r
-/* #define VECT_TAB_SRAM */\r
-#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. \r
- This value must be a multiple of 0x200. */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32L1xx_System_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32L1xx_System_Private_Variables\r
- * @{\r
- */\r
-uint32_t SystemCoreClock = 16000000;\r
-__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};\r
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-static void SetSysClock(void);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32L1xx_System_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Setup the microcontroller system.\r
- * Initialize the Embedded Flash Interface, the PLL and update the \r
- * SystemCoreClock variable.\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemInit (void)\r
-{\r
- /*!< Set MSION bit */\r
- RCC->CR |= (uint32_t)0x00000100;\r
-\r
- /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */\r
- RCC->CFGR &= (uint32_t)0x88FFC00C;\r
- \r
- /*!< Reset HSION, HSEON, CSSON and PLLON bits */\r
- RCC->CR &= (uint32_t)0xEEFEFFFE;\r
-\r
- /*!< Reset HSEBYP bit */\r
- RCC->CR &= (uint32_t)0xFFFBFFFF;\r
-\r
- /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */\r
- RCC->CFGR &= (uint32_t)0xFF02FFFF;\r
-\r
- /*!< Disable all interrupts */\r
- RCC->CIR = 0x00000000;\r
- \r
- /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */\r
- SetSysClock();\r
-\r
-#ifdef VECT_TAB_SRAM\r
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */\r
-#else\r
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */\r
-#endif\r
-}\r
-\r
-/**\r
- * @brief Update SystemCoreClock according to Clock Register Values\r
- * @note - The system frequency computed by this function is not the real \r
- * frequency in the chip. It is calculated based on the predefined \r
- * constant and the selected clock source:\r
- * \r
- * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI \r
- * value as defined by the MSI range.\r
- * \r
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r
- * \r
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r
- * \r
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \r
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
- * \r
- * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value\r
- * 16 MHz) but the real value may vary depending on the variations\r
- * in voltage and temperature. \r
- * \r
- * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value\r
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real\r
- * frequency of the crystal used. Otherwise, this function may\r
- * have wrong result.\r
- * \r
- * - The result of this function could be not correct when using fractional\r
- * value for HSE crystal. \r
- * @param None\r
- * @retval None\r
- */\r
-void SystemCoreClockUpdate (void)\r
-{\r
- uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;\r
-\r
- /* Get SYSCLK source -------------------------------------------------------*/\r
- tmp = RCC->CFGR & RCC_CFGR_SWS;\r
- \r
- switch (tmp)\r
- {\r
- case 0x00: /* MSI used as system clock */\r
- msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;\r
- SystemCoreClock = (32768 * (1 << (msirange + 1)));\r
- break;\r
- case 0x04: /* HSI used as system clock */\r
- SystemCoreClock = HSI_VALUE;\r
- break;\r
- case 0x08: /* HSE used as system clock */\r
- SystemCoreClock = HSE_VALUE;\r
- break;\r
- case 0x0C: /* PLL used as system clock */\r
- /* Get PLL clock source and multiplication factor ----------------------*/\r
- pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;\r
- plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;\r
- pllmul = PLLMulTable[(pllmul >> 18)];\r
- plldiv = (plldiv >> 22) + 1;\r
- \r
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
-\r
- if (pllsource == 0x00)\r
- {\r
- /* HSI oscillator clock selected as PLL clock entry */\r
- SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);\r
- }\r
- else\r
- {\r
- /* HSE selected as PLL clock entry */\r
- SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);\r
- }\r
- break;\r
- default: /* MSI used as system clock */\r
- msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;\r
- SystemCoreClock = (32768 * (1 << (msirange + 1)));\r
- break;\r
- }\r
- /* Compute HCLK clock frequency --------------------------------------------*/\r
- /* Get HCLK prescaler */\r
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
- /* HCLK clock frequency */\r
- SystemCoreClock >>= tmp;\r
-}\r
-\r
-/**\r
- * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash \r
- * settings.\r
- * @note This function should be called only once the RCC clock configuration \r
- * is reset to the default reset state (done in SystemInit() function). \r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClock(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
- /* Enable HSI */\r
- RCC->CR |= ((uint32_t)RCC_CR_HSION);\r
- \r
- /* Wait till HSI is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSIStatus = RCC->CR & RCC_CR_HSIRDY;\r
- } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));\r
-\r
- if ((RCC->CR & RCC_CR_HSIRDY) != RESET)\r
- {\r
- HSIStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSIStatus = (uint32_t)0x00;\r
- }\r
- \r
- if (HSIStatus == (uint32_t)0x01)\r
- {\r
- /* Flash 0 wait state */\r
- FLASH->ACR &= ~FLASH_ACR_LATENCY;\r
- \r
- /* Disable Prefetch Buffer */\r
- FLASH->ACR &= ~FLASH_ACR_PRFTEN;\r
-\r
- /* Disable 64-bit access */\r
- FLASH->ACR &= ~FLASH_ACR_ACC64;\r
- \r
-\r
- /* Power enable */\r
- RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
- \r
- /* Select the Voltage Range 1 (1.8 V) */\r
- PWR->CR = PWR_CR_VOS_0;\r
- \r
- \r
- /* Wait Until the Voltage Regulator is ready */\r
- while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
- {\r
- }\r
- \r
- /* HCLK = SYSCLK /1*/\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- /* PCLK2 = HCLK /1*/\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK /1*/\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
- \r
- /* Select HSI as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;\r
-\r
- /* Wait till HSI is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSI)\r
- {\r
- }\r
- }\r
- else\r
- {\r
- /* If HSI fails to start-up, the application will have wrong clock\r
- configuration. User can add here some code to deal with this error */\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-ELF=lcd.elf
-
-CC=arm-none-eabi-gcc
-
-CFLAGS=-O2 -mlittle-endian -mthumb -g
-CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc
-
-CFLAGS+=-I.
-
-
-PLATFORM=stm32l1xx
-LIBS_STM_PATH=../libs_stm
-
-CFLAGS+=-I$(LIBS_STM_PATH)/inc/base
-CFLAGS+=-I$(LIBS_STM_PATH)/inc/core_support
-CFLAGS+=-I$(LIBS_STM_PATH)/inc/device_support
-CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM)
-
-# to run from SRAM
-CFLAGS+=-Wl,-T,linker_stm32l.lds
-
-LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32_stdperiph_l1xx
-
-SRCS=\
-main.c\
-stm32l_discovery_lcd.c
-
-OBJS=$(SRCS:.c=.o)
-
-all: $(ELF)
-
-$(ELF): $(OBJS)
- $(CC) $(CFLAGS) -o $@ $(OBJS) $(LDFLAGS)
-
-%.o: %.c
- $(CC) $(CFLAGS) -c -o $@ $^
-
-clean:
- -rm -f $(OBJS)
- -rm -f $(ELF)
-
-.PHONY: all clean
+++ /dev/null
- /**\r
- ******************************************************************************\r
- * @file discover_board.h\r
- * @author Microcontroller Division\r
- * @version V1.0.2\r
- * @date September-2011\r
- * @brief Input/Output defines\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-\r
-#ifndef __DISCOVER_BOARD_H\r
-#define __DISCOVER_BOARD_H\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h" \r
-\r
-#define bool _Bool\r
-#define FALSE 0\r
-#define TRUE !FALSE\r
-\r
-/* MACROs for SET, RESET or TOGGLE Output port */\r
-\r
-#define GPIO_HIGH(a,b) a->BSRRL = b\r
-#define GPIO_LOW(a,b) a->BSRRH = b\r
-#define GPIO_TOGGLE(a,b) a->ODR ^= b \r
-\r
-#define USERBUTTON_GPIO_PORT GPIOA\r
-#define USERBUTTON_GPIO_PIN GPIO_Pin_0\r
-#define USERBUTTON_GPIO_CLK RCC_AHBPeriph_GPIOA\r
-\r
-#define LD_GPIO_PORT GPIOB\r
-#define LD_GREEN_GPIO_PIN GPIO_Pin_7\r
-#define LD_BLUE_GPIO_PIN GPIO_Pin_6\r
-#define LD_GPIO_PORT_CLK RCC_AHBPeriph_GPIOB\r
-\r
-#define CTN_GPIO_PORT GPIOC\r
-#define CTN_CNTEN_GPIO_PIN GPIO_Pin_13\r
-#define CTN_GPIO_CLK RCC_AHBPeriph_GPIOC\r
-\r
-#define WAKEUP_GPIO_PORT GPIOA\r
-\r
-#define IDD_MEASURE_PORT GPIOA\r
-#define IDD_MEASURE GPIO_Pin_4\r
-\r
-\r
-#endif\r
-\r
-\r
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-OUTPUT_FORMAT("elf32-littlearm")
-ENTRY(_main)
-
-MEMORY
-{
- sram : ORIGIN = 0x20000000, LENGTH = 0x4000
-}
-
-SECTIONS
-{
- .text(ORIGIN(sram)):
- {
- _main = .;
- _ftext = .;
- *(.text .stub .text.* .gnu.linkonce.t.*)
- _etext = .;
- } > sram
-
- .rodata :
- {
- . = ALIGN(4);
- _frodata = .;
- *(.rodata .rodata.* .gnu.linkonce.r.*)
- *(.rodata1)
- _erodata = .;
- } > sram
-
- .data :
- {
- . = ALIGN(4);
- _fdata = .;
- *(.data .data.* .gnu.linkonce.d.*)
- *(.data1)
- _gp = ALIGN(16);
- *(.sdata .sdata.* .gnu.linkonce.s.*)
- _edata = .;
- } > sram
-
- .bss :
- {
- . = ALIGN(4);
- _fbss = .;
- *(.dynsbss)
- *(.sbss .sbss.* .gnu.linkonce.sb.*)
- *(.scommon)
- *(.dynbss)
- *(.bss .bss.* .gnu.linkonce.b.*)
- *(COMMON)
- _ebss = .;
- _end = .;
- } > sram
-}
-
-PROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);
+++ /dev/null
-/* this example is only for stm32l discover.
- adapted from ST firmwares projects.
- */
-
-/* base headers */
-#include "stdint.h"
-
-/* libstm32l_discovery headers */
-#include "stm32l1xx_gpio.h"
-#include "stm32l1xx_adc.h"
-#include "stm32l1xx_lcd.h"
-#include "stm32l1xx_rcc.h"
-#include "stm32l1xx_rtc.h"
-#include "stm32l1xx_exti.h"
-#include "stm32l1xx_pwr.h"
-#include "stm32l1xx_syscfg.h"
-#include "stm32l1xx_dbgmcu.h"
-
-/* lcd wrapper routines header */
-#include "stm32l_discovery_lcd.h"
-
-/* boot mode */
-
-#define CONFIG_BOOT_SRAM 1
-#define CONFIG_BOOT_FLASH 0
-
-
-/* gpios
- refer to CD00277537.pdf, APB memory space.
- refer to CD00240193.pdf, GPIO.
-*/
-
-#define GPIOA_MODER (GPIOA_BASE + 0x00)
-#define GPIOA_ODR (GPIOA_BASE + 0x14)
-
-#define GPIOB_MODER (GPIOB_BASE + 0x00)
-#define GPIOB_ODR (GPIOB_BASE + 0x14)
-
-#define GPIOC_MODER (GPIOC_BASE + 0x00)
-#define GPIOC_ODR (GPIOC_BASE + 0x14)
-
-
-/* leds */
-
-#define LED_BLUE (1 << 6) /* port B, pin 6 */
-#define LED_GREEN (1 << 7) /* port B, pin 7 */
-
-static inline void setup_leds(void)
-{
- /* configure port 6 and 7 as output */
- *(volatile uint32_t*)GPIOB_MODER |= (1 << (7 * 2)) | (1 << (6 * 2));
-}
-
-static inline void switch_leds_on(void)
-{
- *(volatile uint32_t*)GPIOB_ODR = LED_BLUE | LED_GREEN;
-}
-
-static inline void switch_leds_off(void)
-{
- *(volatile uint32_t*)GPIOB_ODR = 0;
-}
-
-
-#define delay() \
-do { \
- register unsigned int i; \
- for (i = 0; i < 1000000; ++i) \
- __asm__ __volatile__ ("nop\n\t":::"memory"); \
-} while (0)
-
-
-#if CONFIG_BOOT_SRAM
-
-extern uint32_t _fstack;
-
-static inline void setup_stack(void)
-{
- /* setup the stack to point to _fstack (refer to ld script) */
-
- static const uint32_t fstack = (uint32_t)&_fstack;
-
- __asm__ __volatile__
- (
- "ldr sp, %0\n\t"
- :
- : "m"(fstack)
- : "sp"
- );
-}
-
-#endif /* CONFIG_BOOT_SRAM */
-
-
-/* application related setup */
-
-static void RCC_Configuration(void)
-{
- /* Enable HSI Clock */
- RCC_HSICmd(ENABLE);
-
- /*!< Wait till HSI is ready */
- while (RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET);
-
- /* Set HSI as sys clock*/
- RCC_SYSCLKConfig(RCC_SYSCLKSource_HSI);
-
- /* Set MSI clock range to ~4.194MHz*/
- RCC_MSIRangeConfig(RCC_MSIRange_6);
-
- /* Enable the GPIOs clocks */
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC| RCC_AHBPeriph_GPIOD| RCC_AHBPeriph_GPIOE| RCC_AHBPeriph_GPIOH, ENABLE);
-
- /* Enable comparator, LCD and PWR mngt clocks */
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP | RCC_APB1Periph_LCD | RCC_APB1Periph_PWR,ENABLE);
-
- /* Enable ADC & SYSCFG clocks */
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_SYSCFG , ENABLE);
-
- /* Allow access to the RTC */
- PWR_RTCAccessCmd(ENABLE);
-
- /* Reset RTC Backup Domain */
- RCC_RTCResetCmd(ENABLE);
- RCC_RTCResetCmd(DISABLE);
-
- /* LSE Enable */
- RCC_LSEConfig(RCC_LSE_ON);
-
- /* Wait until LSE is ready */
- while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET);
-
- /* RTC Clock Source Selection */
- RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
-
- /* Enable the RTC */
- RCC_RTCCLKCmd(ENABLE);
-
- /*Disable HSE*/
- RCC_HSEConfig(RCC_HSE_OFF);
- if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET )
- {
- /* Stay in infinite loop if HSE is not disabled*/
- while(1);
- }
-}
-
-static void Init_GPIOs(void)
-{
-#if 0 /* fixme: GPIO_Init raises a bug in some gcc toolchains */
-
- /* GPIO, EXTI and NVIC Init structure declaration */
- GPIO_InitTypeDef GPIO_InitStructure;
-
-#if 0
- EXTI_InitTypeDef EXTI_InitStructure;
- NVIC_InitTypeDef NVIC_InitStructure;
-#endif
-
-#if 0
- /* Configure User Button pin as input */
- GPIO_InitStructure.GPIO_Pin = USERBUTTON_GPIO_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
- GPIO_Init(USERBUTTON_GPIO_PORT, &GPIO_InitStructure);
-#endif
-
-#if 0
- /* Select User Button pin as input source for EXTI Line */
- SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA,EXTI_PinSource0);
-
- /* Configure EXT1 Line 0 in interrupt mode trigged on Rising edge */
- EXTI_InitStructure.EXTI_Line = EXTI_Line0 ; // PA0 for User button AND IDD_WakeUP
- EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
- EXTI_InitStructure.EXTI_LineCmd = ENABLE;
- EXTI_Init(&EXTI_InitStructure);
-
- /* Enable and set EXTI0 Interrupt to the lowest priority */
- NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn ;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
-#endif
-
-#if 0
- /* Configure the LED_pin as output push-pull for LD3 & LD4 usage*/
- GPIO_InitStructure.GPIO_Pin = LD_GREEN_GPIO_PIN | LD_BLUE_GPIO_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
- GPIO_Init(LD_GPIO_PORT, &GPIO_InitStructure);
-
- /* Force a low level on LEDs*/
- GPIO_LOW(LD_GPIO_PORT,LD_GREEN_GPIO_PIN);
- GPIO_LOW(LD_GPIO_PORT,LD_BLUE_GPIO_PIN);
-
- /* Counter enable: GPIO set in output for enable the counter */
- GPIO_InitStructure.GPIO_Pin = CTN_CNTEN_GPIO_PIN;
- GPIO_Init( CTN_GPIO_PORT, &GPIO_InitStructure);
-
- /* To prepare to start counter */
- GPIO_HIGH(CTN_GPIO_PORT,CTN_CNTEN_GPIO_PIN);
-
- /* Configure Port A LCD Output pins as alternate function */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_8 | GPIO_Pin_9 |GPIO_Pin_10 |GPIO_Pin_15;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_Init( GPIOA, &GPIO_InitStructure);
-
- /* Select LCD alternate function for Port A LCD Output pins */
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource1,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource2,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource3,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource8,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource9,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource10,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource15,GPIO_AF_LCD) ;
-
- /* Configure Port B LCD Output pins as alternate function */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 \
- | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_Init( GPIOB, &GPIO_InitStructure);
-
- /* Select LCD alternate function for Port B LCD Output pins */
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource3,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource4,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource5,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource8,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource9,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource10,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource11,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource12,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource13,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource14,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource15,GPIO_AF_LCD) ;
-#endif
-
-#if 0
- /* Configure Port C LCD Output pins as alternate function */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 \
- | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |GPIO_Pin_11 ;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_Init( GPIOC, &GPIO_InitStructure);
-
- /* Select LCD alternate function for Port B LCD Output pins */
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource0,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource1,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource2,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource3,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource6,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource7,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource8,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource9,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource10,GPIO_AF_LCD) ;
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource11,GPIO_AF_LCD) ;
-#endif
-
-#if 0
- /* Configure ADC (IDD_MEASURE) pin as Analogue */
- GPIO_InitStructure.GPIO_Pin = IDD_MEASURE ;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;
- GPIO_Init( IDD_MEASURE_PORT, &GPIO_InitStructure);
-#endif
-
-#else /* fixme */
-
- /* set every port in digital output mode */
-
- /* PA[1:3,8:10,15] */
- *(volatile uint32_t*)GPIOA_MODER |=
- (GPIO_Mode_AF << (1 * 2)) |
- (GPIO_Mode_AF << (2 * 2)) |
- (GPIO_Mode_AF << (3 * 2)) |
- (GPIO_Mode_AF << (8 * 2)) |
- (GPIO_Mode_AF << (9 * 2)) |
- (GPIO_Mode_AF << (10 * 2)) |
- (GPIO_Mode_AF << (15 * 2));
-
- /* PB[3:5,8:15] */
- *(volatile uint32_t*)GPIOB_MODER |=
- (GPIO_Mode_AF << (3 * 2)) |
- (GPIO_Mode_AF << (4 * 2)) |
- (GPIO_Mode_AF << (5 * 2)) |
- (GPIO_Mode_AF << (8 * 2)) |
- (GPIO_Mode_AF << (9 * 2)) |
- (GPIO_Mode_AF << (10 * 2)) |
- (GPIO_Mode_AF << (11 * 2)) |
- (GPIO_Mode_AF << (12 * 2)) |
- (GPIO_Mode_AF << (13 * 2)) |
- (GPIO_Mode_AF << (14 * 2)) |
- (GPIO_Mode_AF << (15 * 2));
-
- /* PC[0:3,6:11] */
- *(volatile uint32_t*)GPIOC_MODER |=
- (GPIO_Mode_AF << (0 * 2)) |
- (GPIO_Mode_AF << (1 * 2)) |
- (GPIO_Mode_AF << (2 * 2)) |
- (GPIO_Mode_AF << (3 * 2)) |
- (GPIO_Mode_AF << (6 * 2)) |
- (GPIO_Mode_AF << (7 * 2)) |
- (GPIO_Mode_AF << (8 * 2)) |
- (GPIO_Mode_AF << (9 * 2)) |
- (GPIO_Mode_AF << (10 * 2)) |
- (GPIO_Mode_AF << (11 * 2));
-
-#endif /* fixme */
-}
-
-
-/* main */
-
-static void __attribute__((naked)) __attribute__((used)) main(void)
-{
-#if CONFIG_BOOT_SRAM
- /* do not use previsouly setup stack, if any */
- setup_stack();
-#endif /* CONFIG_BOOT_SRAM */
-
- RCC_Configuration();
-
- Init_GPIOs();
-
- LCD_GLASS_Init();
-
- setup_leds();
-
- while (1)
- {
- /* switch_leds_on(); */
- GPIO_HIGH(LD_GPIO_PORT, LD_GREEN_GPIO_PIN);
- GPIO_HIGH(LD_GPIO_PORT, LD_BLUE_GPIO_PIN);
-
- LCD_GLASS_Clear();
- LCD_GLASS_DisplayString("ON ");
-
- delay();
-
- /* switch_leds_off(); */
- GPIO_LOW(LD_GPIO_PORT, LD_GREEN_GPIO_PIN);
- GPIO_LOW(LD_GPIO_PORT, LD_BLUE_GPIO_PIN);
-
- LCD_GLASS_Clear();
- LCD_GLASS_DisplayString(" OFF");
-
- delay();
- }
-}
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l_discovery_lcd.c\r
- * @author Microcontroller Division\r
- * @version V1.0.0\r
- * @date Apri-2011\r
- * @brief This file includes driver for the glass LCD Module mounted on \r
- * STM32l discovery board MB963\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l_discovery_lcd.h"\r
-#include "discover_board.h"\r
-#include "stm32l1xx_lcd.h"\r
-#include "stm32l1xx_gpio.h"\r
-#include "stm32l1xx_rcc.h"\r
-/* #include "main.h" */\r
-\r
-/* this variable can be used for accelerate the scrolling exit when push user button */\r
-volatile bool KeyPressed = FALSE; \r
- \r
-/* LCD BAR status: We don't write directly in LCD RAM for save the bar setting */\r
-uint8_t t_bar[2]={0x0,0X0};\r
- \r
-/* =========================================================================\r
- LCD MAPPING\r
- =========================================================================\r
- A\r
- _ ----------\r
-COL |_| |\ |J /|\r
- F| H | K |B\r
- _ | \ | / |\r
-COL |_| --G-- --M--\r
- | /| \ |\r
- E| Q | N |C\r
- _ | / |P \| \r
-DP |_| ----------- \r
- D \r
-\r
- An LCD character coding is based on the following matrix:\r
- { E , D , P , N }\r
- { M , C , COL , DP}\r
- { B , A , K , J }\r
- { G , F , Q , H }\r
-\r
- The character 'A' for example is:\r
- -------------------------------\r
-LSB { 1 , 0 , 0 , 0 }\r
- { 1 , 1 , 0 , 0 }\r
- { 1 , 1 , 0 , 0 }\r
-MSB { 1 , 1 , 0 , 0 }\r
- -------------------\r
- 'A' = F E 0 0 hexa\r
-\r
-*/\r
-\r
-/* Constant table for cap characters 'A' --> 'Z' */\r
-const uint16_t CapLetterMap[26]=\r
- {\r
- /* A B C D E F G H I */\r
- 0xFE00,0x6714,0x1d00,0x4714,0x9d00,0x9c00,0x3f00,0xfa00,0x0014,\r
- /* J K L M N O P Q R */\r
- 0x5300,0x9841,0x1900,0x5a48,0x5a09,0x5f00,0xFC00,0x5F01,0xFC01,\r
- /* S T U V W X Y Z */\r
- 0xAF00,0x0414,0x5b00,0x18c0,0x5a81,0x00c9,0x0058,0x05c0\r
- };\r
-\r
-/* Constant table for number '0' --> '9' */\r
-const uint16_t NumberMap[10]=\r
- {\r
- /* 0 1 2 3 4 5 6 7 8 9 */\r
- 0x5F00,0x4200,0xF500,0x6700,0xEa00,0xAF00,0xBF00,0x04600,0xFF00,0xEF00\r
- };\r
-\r
-static void LCD_Conv_Char_Seg(uint8_t* c,bool point,bool column,uint8_t* digit);\r
-\r
-/**\r
- * @brief Configures the LCD GLASS relative GPIO port IOs and LCD peripheral.\r
- * @param None\r
- * @retval None\r
- */\r
-void LCD_GLASS_Init(void)\r
-{\r
- LCD_InitTypeDef LCD_InitStruct;\r
-\r
- \r
- LCD_InitStruct.LCD_Prescaler = LCD_Prescaler_1;\r
- LCD_InitStruct.LCD_Divider = LCD_Divider_31;\r
- LCD_InitStruct.LCD_Duty = LCD_Duty_1_4;\r
- LCD_InitStruct.LCD_Bias = LCD_Bias_1_3;\r
- LCD_InitStruct.LCD_VoltageSource = LCD_VoltageSource_Internal;\r
-\r
- \r
- /* Initialize the LCD */\r
- LCD_Init(&LCD_InitStruct);\r
- \r
- LCD_MuxSegmentCmd(ENABLE);\r
- \r
- /* To set contrast to mean value */\r
- LCD_ContrastConfig(LCD_Contrast_Level_4);\r
- \r
- LCD_DeadTimeConfig(LCD_DeadTime_0);\r
- LCD_PulseOnDurationConfig(LCD_PulseOnDuration_4);\r
-\r
- /* Wait Until the LCD FCR register is synchronized */\r
- LCD_WaitForSynchro();\r
- \r
- /* Enable LCD peripheral */\r
- LCD_Cmd(ENABLE);\r
- \r
- /* Wait Until the LCD is enabled */\r
- while(LCD_GetFlagStatus(LCD_FLAG_ENS) == RESET)\r
- {\r
- }\r
- /*!< Wait Until the LCD Booster is ready */ \r
- while(LCD_GetFlagStatus(LCD_FLAG_RDY) == RESET)\r
- {\r
- } \r
-\r
- LCD_BlinkConfig(LCD_BlinkMode_Off,LCD_BlinkFrequency_Div32); \r
- LCD_GLASS_Clear();\r
-}\r
-\r
-/**\r
- * @brief To initialize the LCD pins\r
- * @caller main\r
- * @param None\r
- * @retval None\r
- */\r
-\r
-void LCD_GLASS_Configure_GPIO(void)\r
-{\r
- GPIO_InitTypeDef GPIO_InitStructure;\r
- \r
-/* Enable GPIOs clock */ \r
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC |\r
- RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE | RCC_AHBPeriph_GPIOH, ENABLE);\r
-\r
- \r
-/* Configure Output for LCD */\r
-/* Port A */\r
- GPIO_StructInit(&GPIO_InitStructure);\r
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_8 | GPIO_Pin_9 |GPIO_Pin_10 |GPIO_Pin_15;\r
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
- GPIO_Init( GPIOA, &GPIO_InitStructure);\r
-\r
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource1,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource2,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource3,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource8,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource9,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource10,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource15,GPIO_AF_LCD) ; \r
- \r
-/* Configure Output for LCD */\r
-/* Port B */ \r
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 \\r
- | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; \r
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
- GPIO_Init( GPIOB, &GPIO_InitStructure);\r
- \r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource3,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource4,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource5,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource8,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource9,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource10,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource11,GPIO_AF_LCD) ; \r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource12,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource13,GPIO_AF_LCD) ; \r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource14,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource15,GPIO_AF_LCD) ; \r
- \r
-/* Configure Output for LCD */\r
-/* Port C*/ \r
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 \\r
- | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |GPIO_Pin_11 ; \r
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
- GPIO_Init( GPIOC, &GPIO_InitStructure); \r
- \r
-\r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource0,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource1,GPIO_AF_LCD) ; \r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource2,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource3,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource6,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource7,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource8,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource9,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource10,GPIO_AF_LCD) ; \r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource11,GPIO_AF_LCD) ; \r
-\r
-/* Disable GPIOs clock */ \r
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC |\r
- RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE | RCC_AHBPeriph_GPIOH, DISABLE);\r
- \r
-}\r
-\r
-/**\r
- * @brief LCD contrast setting min-->max-->min by pressing user button\r
- * @param None\r
- * @retval None\r
- */\r
-\r
-static void Delay(uint32_t nTime)\r
-{\r
- while((nTime--) != 0); \r
-}\r
-\r
-void LCD_contrast()\r
-{\r
- uint32_t contrast ;\r
- \r
- /* To get the actual contrast value in register */\r
- contrast = LCD->FCR & LCD_Contrast_Level_7;\r
- \r
- while ((GPIOC->IDR & USERBUTTON_GPIO_PIN) == 0x0)\r
- {\r
- contrast += LCD_Contrast_Level_1; \r
- \r
- if (contrast > LCD_Contrast_Level_7)\r
- contrast=LCD_Contrast_Level_0;\r
- \r
- LCD_ContrastConfig(contrast);\r
- Delay(100);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Setting bar on LCD, writes bar value in LCD frame buffer \r
- * @param None\r
- * @retval None\r
- */\r
-void LCD_bar()\r
-{\r
- \r
- LCD->RAM[LCD_RAMRegister_4] &= 0xffff5fff;\r
- LCD->RAM[LCD_RAMRegister_6] &= 0xffff5fff;\r
-/* bar1 bar3 */\r
- LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(t_bar[0]<<12);\r
- \r
-/*bar0 bar2 */\r
- LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(t_bar[1]<<12);\r
- \r
-}\r
-\r
-/**\r
- * @brief Converts an ascii char to the a LCD digit.\r
- * @param c: a char to display.\r
- * @param point: a point to add in front of char\r
- * This parameter can be: POINT_OFF or POINT_ON\r
- * @param column : flag indicating if a column has to be add in front\r
- * of displayed character.\r
- * This parameter can be: COLUMN_OFF or COLUMN_ON.\r
- * @param digit array with segment \r
- * @retval None\r
- */\r
-static void LCD_Conv_Char_Seg(uint8_t* c,bool point,bool column, uint8_t* digit)\r
-{\r
- uint16_t ch = 0 ;\r
- uint8_t i,j;\r
- \r
- switch (*c)\r
- {\r
- case ' ' : \r
- ch = 0x00;\r
- break;\r
- \r
- case '*':\r
- ch = star;\r
- break;\r
- \r
- case 'µ' :\r
- ch = C_UMAP;\r
- break;\r
- \r
- case 'm' :\r
- ch = C_mMap;\r
- break;\r
- \r
- case 'n' :\r
- ch = C_nMap;\r
- break; \r
- \r
- case '-' :\r
- ch = C_minus;\r
- break;\r
- \r
- case '/' :\r
- ch = C_slatch;\r
- break; \r
- \r
- case '°' :\r
- ch = C_percent_1;\r
- break; \r
- case '%' :\r
- ch = C_percent_2; \r
- break;\r
- case 255 :\r
- ch = C_full;\r
- break ;\r
- \r
- case '0':\r
- case '1':\r
- case '2':\r
- case '3':\r
- case '4':\r
- case '5':\r
- case '6':\r
- case '7':\r
- case '8':\r
- case '9': \r
- ch = NumberMap[*c-0x30]; \r
- break;\r
- \r
- default:\r
- /* The character c is one letter in upper case*/\r
- if ( (*c < 0x5b) && (*c > 0x40) )\r
- {\r
- ch = CapLetterMap[*c-'A'];\r
- }\r
- /* The character c is one letter in lower case*/\r
- if ( (*c <0x7b) && ( *c> 0x60) )\r
- {\r
- ch = CapLetterMap[*c-'a'];\r
- }\r
- break;\r
- }\r
- \r
- /* Set the digital point can be displayed if the point is on */\r
- if (point)\r
- {\r
- ch |= 0x0002;\r
- }\r
-\r
- /* Set the "COL" segment in the character that can be displayed if the column is on */\r
- if (column)\r
- {\r
- ch |= 0x0020;\r
- } \r
-\r
- for (i = 12,j=0 ;j<4; i-=4,j++)\r
- {\r
- digit[j] = (ch >> i) & 0x0f; //To isolate the less signifiant dibit\r
- }\r
-}\r
-\r
-/**\r
- * @brief This function writes a char in the LCD frame buffer.\r
- * @param ch: the character to display.\r
- * @param point: a point to add in front of char\r
- * This parameter can be: POINT_OFF or POINT_ON\r
- * @param column: flag indicating if a column has to be add in front\r
- * of displayed character.\r
- * This parameter can be: COLUMN_OFF or COLUMN_ON. \r
- * @param position: position in the LCD of the caracter to write [0:7]\r
- * @retval None\r
- * @par Required preconditions: The LCD should be cleared before to start the\r
- * write operation. \r
- */\r
-void LCD_GLASS_WriteChar(uint8_t* ch, bool point, bool column, uint8_t position)\r
-{\r
- uint8_t digit[4]; /* Digit frame buffer */\r
- \r
-/* To convert displayed character in segment in array digit */\r
- LCD_Conv_Char_Seg(ch,point,column,digit);\r
-\r
-/* TO wait LCD Ready */ \r
- while( LCD_GetFlagStatus (LCD_FLAG_UDR) != RESET) ;\r
- \r
- switch (position)\r
- {\r
- /* Position 1 on LCD (Digit1)*/\r
- case 1:\r
- LCD->RAM[LCD_RAMRegister_0] &= 0xcffffffc;\r
- LCD->RAM[LCD_RAMRegister_2] &= 0xcffffffc;\r
- LCD->RAM[LCD_RAMRegister_4] &= 0xcffffffc;\r
- LCD->RAM[LCD_RAMRegister_6] &= 0xcffffffc;\r
-\r
- LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 26 ) | (digit[0]& 0x03) ; // 1G 1B 1M 1E \r
- LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 26 ) | (digit[1]& 0x03) ; // 1F 1A 1C 1D \r
- LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 26 ) | (digit[2]& 0x03) ; // 1Q 1K 1Col 1P \r
- LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 26 ) | (digit[3]& 0x03) ; // 1H 1J 1DP 1N\r
-\r
- break;\r
- \r
- /* Position 2 on LCD (Digit2)*/\r
- case 2:\r
- LCD->RAM[LCD_RAMRegister_0] &= 0xf3ffff03;\r
- LCD->RAM[LCD_RAMRegister_2] &= 0xf3ffff03; \r
- LCD->RAM[LCD_RAMRegister_4] &= 0xf3ffff03;\r
- LCD->RAM[LCD_RAMRegister_6] &= 0xf3ffff03;\r
- \r
- LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 24 )|((digit[0]& 0x02) << 6 )|((digit[0]& 0x01) << 2 ) ; // 2G 2B 2M 2E \r
- LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 24 )|((digit[1]& 0x02) << 6 )|((digit[1]& 0x01) << 2 ) ; // 2F 2A 2C 2D\r
- LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 24 )|((digit[2]& 0x02) << 6 )|((digit[2]& 0x01) << 2 ) ; // 2Q 2K 2Col 2P\r
- LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 24 )|((digit[3]& 0x02) << 6 )|((digit[3]& 0x01) << 2 ) ; // 2H 2J 2DP 2N\r
- \r
- break;\r
- \r
- /* Position 3 on LCD (Digit3)*/\r
- case 3:\r
- LCD->RAM[LCD_RAMRegister_0] &= 0xfcfffcff;\r
- LCD->RAM[LCD_RAMRegister_2] &= 0xfcfffcff;\r
- LCD->RAM[LCD_RAMRegister_4] &= 0xfcfffcff;\r
- LCD->RAM[LCD_RAMRegister_6] &= 0xfcfffcff;\r
-\r
- LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 22 ) | ((digit[0]& 0x03) << 8 ) ; // 3G 3B 3M 3E \r
- LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 22 ) | ((digit[1]& 0x03) << 8 ) ; // 3F 3A 3C 3D\r
- LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 22 ) | ((digit[2]& 0x03) << 8 ) ; // 3Q 3K 3Col 3P\r
- LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 22 ) | ((digit[3]& 0x03) << 8 ) ; // 3H 3J 3DP 3N\r
- \r
- break;\r
- \r
- /* Position 4 on LCD (Digit4)*/\r
- case 4:\r
- LCD->RAM[LCD_RAMRegister_0] &= 0xffcff3ff;\r
- LCD->RAM[LCD_RAMRegister_2] &= 0xffcff3ff;\r
- LCD->RAM[LCD_RAMRegister_4] &= 0xffcff3ff;\r
- LCD->RAM[LCD_RAMRegister_6] &= 0xffcff3ff;\r
- \r
- LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 18 ) | ((digit[0]& 0x03) << 10 ) ; // 4G 4B 4M 4E \r
- LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 18 ) | ((digit[1]& 0x03) << 10 ) ; // 4F 4A 4C 4D\r
- LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 18 ) | ((digit[2]& 0x03) << 10 ) ; // 4Q 4K 4Col 4P\r
- LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 18 ) | ((digit[3]& 0x03) << 10 ) ; // 4H 4J 4DP 4N\r
- \r
- break;\r
- \r
- /* Position 5 on LCD (Digit5)*/\r
- case 5:\r
- LCD->RAM[LCD_RAMRegister_0] &= 0xfff3cfff;\r
- LCD->RAM[LCD_RAMRegister_2] &= 0xfff3cfff;\r
- LCD->RAM[LCD_RAMRegister_4] &= 0xfff3efff;\r
- LCD->RAM[LCD_RAMRegister_6] &= 0xfff3efff;\r
-\r
- LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 16 ) | ((digit[0]& 0x03) << 12 ) ; // 5G 5B 5M 5E \r
- LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 16 ) | ((digit[1]& 0x03) << 12 ) ; // 5F 5A 5C 5D\r
- LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 16 ) | ((digit[2]& 0x01) << 12 ) ; // 5Q 5K 5P \r
- LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 16 ) | ((digit[3]& 0x01) << 12 ) ; // 5H 5J 5N\r
- \r
- break;\r
- \r
- /* Position 6 on LCD (Digit6)*/\r
- case 6:\r
- LCD->RAM[LCD_RAMRegister_0] &= 0xfffc3fff;\r
- LCD->RAM[LCD_RAMRegister_2] &= 0xfffc3fff;\r
- LCD->RAM[LCD_RAMRegister_4] &= 0xfffc3fff;\r
- LCD->RAM[LCD_RAMRegister_6] &= 0xfffc3fff;\r
-\r
- LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x04) << 15 ) | ((digit[0]& 0x08) << 13 ) | ((digit[0]& 0x03) << 14 ) ; // 6B 6G 6M 6E \r
- LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x04) << 15 ) | ((digit[1]& 0x08) << 13 ) | ((digit[1]& 0x03) << 14 ) ; // 6A 6F 6C 6D\r
- LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x04) << 15 ) | ((digit[2]& 0x08) << 13 ) | ((digit[2]& 0x01) << 14 ) ; // 6K 6Q 6P \r
- LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x04) << 15 ) | ((digit[3]& 0x08) << 13 ) | ((digit[3]& 0x01) << 14 ) ; // 6J 6H 6N\r
- \r
- break;\r
- \r
- default:\r
- break;\r
- }\r
-\r
-/* Refresh LCD bar */\r
- LCD_bar();\r
-\r
-/* Update the LCD display */\r
- LCD_UpdateDisplayRequest();\r
- \r
-}\r
-\r
-/**\r
- * @brief This function writes a char in the LCD RAM.\r
- * @param ptr: Pointer to string to display on the LCD Glass.\r
- * @retval None\r
- */\r
-void LCD_GLASS_DisplayString(uint8_t* ptr)\r
-{\r
- uint8_t i = 0x01;\r
-\r
- /* Send the string character by character on lCD */\r
- while ((*ptr != 0) & (i < 8))\r
- {\r
- /* Display one character on LCD */\r
- LCD_GLASS_WriteChar(ptr, FALSE, FALSE, i);\r
-\r
- /* Point on the next character */\r
- ptr++;\r
-\r
- /* Increment the character counter */\r
- i++;\r
- }\r
-}\r
-\r
-/**\r
- * @brief This function writes a char in the LCD RAM.\r
- * @param ptr: Pointer to string to display on the LCD Glass.\r
- * @retval None\r
- * @par Required preconditions: Char is ASCCI value "Ored" with decimal point or Column flag\r
- */\r
-void LCD_GLASS_DisplayStrDeci(uint16_t* ptr)\r
-{\r
- uint8_t i = 0x01;\r
- uint8_t char_tmp;\r
- \r
-// LCD_GLASS_Clear();\r
- /* Send the string character by character on lCD */\r
- while ((*ptr != 0) & (i < 8))\r
- { \r
- char_tmp = (*ptr) & 0x00ff;\r
- \r
- switch ((*ptr) & 0xf000)\r
- {\r
- case DOT:\r
- /* Display one character on LCD with decimal point */\r
- LCD_GLASS_WriteChar(&char_tmp, POINT_ON, COLUMN_OFF, i);\r
- break;\r
- case DOUBLE_DOT:\r
- /* Display one character on LCD with decimal point */\r
- LCD_GLASS_WriteChar(&char_tmp, POINT_OFF, COLUMN_ON, i);\r
- break;\r
- default:\r
- LCD_GLASS_WriteChar(&char_tmp, POINT_OFF, COLUMN_OFF, i); \r
- break;\r
- }/* Point on the next character */\r
- ptr++;\r
- \r
- /* Increment the character counter */\r
- i++;\r
- }\r
-}\r
-\r
-/**\r
- * @brief This function Clear the whole LCD RAM.\r
- * @param None\r
- * @retval None\r
- */\r
-void LCD_GLASS_Clear(void)\r
-{\r
- uint8_t counter = 0;\r
-\r
- /* TO wait LCD Ready */ \r
- while( LCD_GetFlagStatus (LCD_FLAG_UDR) != RESET) ;\r
- \r
- for (counter = LCD_RAMRegister_0; counter <= LCD_RAMRegister_15; counter++)\r
- {\r
- LCD->RAM[counter] = 0;\r
- }\r
-\r
- /* Update the LCD display */\r
- LCD_UpdateDisplayRequest();\r
- \r
-}\r
-\r
-/**\r
- * @brief Display a string in scrolling mode\r
- * @param ptr: Pointer to string to display on the LCD Glass.\r
- * @param nScroll: Specifies how many time the message will be scrolled\r
- * @param ScrollSpeed : Speciifes the speed of the scroll, low value gives\r
- * higher speed \r
- * @retval None\r
- * @par Required preconditions: The LCD should be cleared before to start the\r
- * write operation.\r
- */\r
-void LCD_GLASS_ScrollSentence(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed)\r
-{\r
- uint8_t Repetition;\r
- uint8_t Char_Nb;\r
- uint8_t* ptr1;\r
- uint8_t str[7]="";\r
- uint8_t Str_size;\r
- \r
- if (ptr == 0) return;\r
-\r
-/* To calculate end of string */\r
- for (ptr1=ptr,Str_size = 0 ; *ptr1 != 0; Str_size++,ptr1++) ;\r
- \r
- ptr1 = ptr;\r
- \r
- LCD_GLASS_DisplayString(ptr);\r
- Delay(ScrollSpeed);\r
- \r
-/* To shift the string for scrolling display*/\r
- for (Repetition=0; Repetition<nScroll; Repetition++)\r
- {\r
- for (Char_Nb=0; Char_Nb<Str_size; Char_Nb++)\r
- {\r
- *(str) =* (ptr1+((Char_Nb+1)%Str_size));\r
- *(str+1) =* (ptr1+((Char_Nb+2)%Str_size));\r
- *(str+2) =* (ptr1+((Char_Nb+3)%Str_size));\r
- *(str+3) =* (ptr1+((Char_Nb+4)%Str_size));\r
- *(str+4) =* (ptr1+((Char_Nb+5)%Str_size));\r
- *(str+5) =* (ptr1+((Char_Nb+6)%Str_size));\r
- LCD_GLASS_Clear();\r
- LCD_GLASS_DisplayString(str);\r
- \r
- /* user button pressed stop the scrolling sentence */\r
- if (KeyPressed)\r
- return; \r
- Delay(ScrollSpeed);\r
- } \r
- }\r
-\r
-}\r
-\r
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
- /**\r
- ******************************************************************************\r
- * @file stm32l_discovery_lcd.h\r
- * @author Microcontroller Division\r
- * @version V1.0.0\r
- * @date Apri-2011\r
- * @brief This file contains all the functions prototypes for the glass LCD\r
- * firmware driver.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __stm32l_discovery_lcd\r
-#define __stm32l_discovery_lcd\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h" \r
-#include "discover_board.h"\r
-\r
-/* Define for scrolling sentences*/\r
-#define SCROLL_SPEED 300\r
-#define SCROLL_SPEED_L 600\r
-#define SCROLL_NUM 1\r
-\r
-/* Define for character '.' */\r
-#define POINT_OFF FALSE\r
-#define POINT_ON TRUE\r
-\r
-/* Define for caracter ":" */\r
-#define COLUMN_OFF FALSE\r
-#define COLUMN_ON TRUE\r
-\r
-#define DOT 0x8000 /* for add decimal point in string */\r
-#define DOUBLE_DOT 0x4000 /* for add decimal point in string */\r
-\r
-\r
-/* =========================================================================\r
- LCD MAPPING\r
- =========================================================================\r
- A\r
- _ ----------\r
-COL |_| |\ |J /|\r
- F| H | K |B\r
- _ | \ | / |\r
-COL |_| --G-- --M--\r
- | /| \ |\r
- E| Q | N |C\r
- _ | / |P \| \r
-DP |_| ----------- \r
- D \r
-\r
- An LCD character coding is based on the following matrix:\r
- { E , D , P , N }\r
- { M , C , COL , DP}\r
- { B , A , K , J }\r
- { G , F , Q , H }\r
-\r
- The character 'A' for example is:\r
- -------------------------------\r
-LSB { 1 , 0 , 0 , 0 }\r
- { 1 , 1 , 0 , 0 }\r
- { 1 , 1 , 0 , 0 }\r
-MSB { 1 , 1 , 0 , 0 }\r
- -------------------\r
- 'A' = F E 0 0 hexa\r
-\r
-*/\r
-/* Macros used for set/reset bar LCD bar */\r
-#define BAR0_ON t_bar[1] |= 8\r
-#define BAR0_OFF t_bar[1] &= ~8\r
-#define BAR1_ON t_bar[0] |= 8\r
-#define BAR1_OFF t_bar[0] &= ~8\r
-#define BAR2_ON t_bar[1] |= 2\r
-#define BAR2_OFF t_bar[1] &= ~2\r
-#define BAR3_ON t_bar[0] |= 2 \r
-#define BAR3_OFF t_bar[0] &= ~2 \r
-\r
-/* code for 'µ' character */\r
-#define C_UMAP 0x6084\r
-\r
-/* code for 'm' character */\r
-#define C_mMap 0xb210\r
-\r
-/* code for 'n' character */\r
-#define C_nMap 0x2210\r
-\r
-/* constant code for '*' character */\r
-#define star 0xA0DD\r
-\r
-/* constant code for '-' character */\r
-#define C_minus 0xA000\r
-\r
-/* constant code for '/' */\r
-#define C_slatch 0x00c0\r
-\r
-/* constant code for ° */\r
-#define C_percent_1 0xec00\r
-\r
-/* constant code for small o */\r
-#define C_percent_2 0xb300\r
-\r
-#define C_full 0xffdd\r
-\r
-void LCD_bar(void);\r
-void LCD_GLASS_Init(void);\r
-void LCD_GLASS_WriteChar(uint8_t* ch, bool point, bool column,uint8_t position);\r
-void LCD_GLASS_DisplayString(uint8_t* ptr);\r
-void LCD_GLASS_DisplayStrDeci(uint16_t* ptr);\r
-void LCD_GLASS_ClearChar(uint8_t position);\r
-void LCD_GLASS_Clear(void);\r
-void LCD_GLASS_ScrollSentence(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed);\r
-void LCD_GLASS_WriteTime(char a, uint8_t posi, bool column);\r
-void LCD_GLASS_Configure_GPIO(void);\r
-\r
-#endif /* stm32l_discovery_lcd*/\r
-\r
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-# build an elf from the an3268 demonstration code
-APP=32vl_factory_demo
-
-CC=arm-none-eabi-gcc
-OBJCOPY=arm-none-eabi-objcopy
-
-CFLAGS=-O2 -mlittle-endian -mthumb
-CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc
-ifeq ($(DEBUG),1)
- CFLAGS+=-g
-endif
-
-# to run from SRAM
-CFLAGS+=-Wl,-Ttext,0x20000000 -Wl,-e,0x20000000
-
-# to write to flash then run
-# CFLAGS+=-Wl,-Ttext,0x08000000 -Wl,-e,0x08000000
-
-PLATFORM=stm32f10x
-BOARD_SUPPORT=../board_support/discovery_32vl
-LIBS_STM_PATH=../libs_stm
-
-CFLAGS+=-I.
-CFLAGS+=-I$(LIBS_STM_PATH)/inc/base
-CFLAGS+=-I$(LIBS_STM_PATH)/inc/core_support
-CFLAGS+=-I$(LIBS_STM_PATH)/inc/device_support
-CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM)
-CFLAGS+=-I$(BOARD_SUPPORT)
-
-LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32_stdperiph_f10x
-
-
-SRCS=$(wildcard *.c)
-SRCS+=$(wildcard $(BOARD_SUPPORT)/*.c)
-
-OBJS=$(SRCS:.c=.o)
-
-all: $(APP).elf
-
-%.bin: %.elf
- $(OBJCOPY) -O binary $^ $@
-
-$(APP).elf: $(OBJS)
- $(CC) $(CFLAGS) -o $@ $(OBJS) $(LDFLAGS)
-
-%.o: %.c
- $(CC) $(CFLAGS) -c -o $@ $^
-
-clean:
- rm -rf $(OBJS)
- rm -rf $(APP).*
-
-.PHONY: all clean
+++ /dev/null
-This source is copied from AN3268, the STM demo code for the VL discovery board.
-
-It was modified to add includes and things where needed, but nothing else was touched.
-
-Eventually, this should be usable to restore a board to virgin state. (but not yet)
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file Demo/src/main.c \r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 09/13/2010\r
- * @brief Main program body\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-#include "stm32f10x_conf.h"\r
-#include "STM32vldiscovery.h"\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-#define LSE_FAIL_FLAG 0x80\r
-#define LSE_PASS_FLAG 0x100\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private consts ------------------------------------------------------------*/\r
-\r
-/* Private variables ---------------------------------------------------------*/\r
-u32 LSE_Delay = 0;\r
-u32 count = 0;\r
-u32 BlinkSpeed = 0;\r
-u32 KeyState = 0;\r
-static __IO uint32_t TimingDelay;\r
-/* Private function prototypes -----------------------------------------------*/\r
-void Delay(uint32_t nTime);\r
-void TimingDelay_Decrement(void);\r
-\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/**\r
- * @brief Main program.\r
- * @param None\r
- * @retval None\r
- */\r
-\r
-int main(void)\r
-{\r
- /* Enable GPIOx Clock */\r
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);\r
- \r
- /* Initialise LEDs LD3&LD4, both off */\r
- STM32vldiscovery_LEDInit(LED3);\r
- STM32vldiscovery_LEDInit(LED4);\r
- \r
- STM32vldiscovery_LEDOff(LED3);\r
- STM32vldiscovery_LEDOff(LED4);\r
- \r
- /* Initialise USER Button */\r
- STM32vldiscovery_PBInit(BUTTON_USER, BUTTON_MODE_GPIO); \r
- \r
- /* Setup SysTick Timer for 1 msec interrupts */\r
- if (SysTick_Config(SystemCoreClock / 1000))\r
- { \r
- /* Capture error */ \r
- while (1);\r
- }\r
-\r
- /* Enable access to the backup register => LSE can be enabled */\r
- PWR_BackupAccessCmd(ENABLE);\r
- \r
- /* Enable LSE (Low Speed External Oscillation) */\r
- RCC_LSEConfig(RCC_LSE_ON);\r
- \r
- /* Check the LSE Status */\r
- while(1)\r
- {\r
- if(LSE_Delay < LSE_FAIL_FLAG)\r
- {\r
- /* check whether LSE is ready, with 4 seconds timeout */\r
- Delay (500);\r
- LSE_Delay += 0x10;\r
- if(RCC_GetFlagStatus(RCC_FLAG_LSERDY) != RESET)\r
- {\r
- /* Set flag: LSE PASS */\r
- LSE_Delay |= LSE_PASS_FLAG;\r
- /* Turn Off Led4 */\r
- STM32vldiscovery_LEDOff(LED4);\r
- /* Disable LSE */\r
- RCC_LSEConfig(RCC_LSE_OFF);\r
- break;\r
- } \r
- }\r
- \r
- /* LSE_FAIL_FLAG = 0x80 */ \r
- else if(LSE_Delay >= LSE_FAIL_FLAG)\r
- { \r
- if(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)\r
- {\r
- /* Set flag: LSE FAIL */\r
- LSE_Delay |= LSE_FAIL_FLAG;\r
- /* Turn On Led4 */\r
- STM32vldiscovery_LEDOn(LED4);\r
- } \r
- /* Disable LSE */\r
- RCC_LSEConfig(RCC_LSE_OFF);\r
- break;\r
- }\r
- }\r
- \r
- /* main while */\r
- while(1)\r
- {\r
- if(0 == STM32vldiscovery_PBGetState(BUTTON_USER))\r
- {\r
- if(KeyState == 1)\r
- {\r
- if(0 == STM32vldiscovery_PBGetState(BUTTON_USER))\r
- {\r
- /* USER Button released */\r
- KeyState = 0;\r
- /* Turn Off LED4 */\r
- STM32vldiscovery_LEDOff(LED4);\r
- } \r
- }\r
- }\r
- else if(STM32vldiscovery_PBGetState(BUTTON_USER))\r
- { \r
- if(KeyState == 0)\r
- {\r
- if(STM32vldiscovery_PBGetState(BUTTON_USER))\r
- {\r
- /* USER Button released */\r
- KeyState = 1;\r
- /* Turn ON LED4 */\r
- STM32vldiscovery_LEDOn(LED4);\r
- Delay(1000);\r
- /* Turn OFF LED4 */\r
- STM32vldiscovery_LEDOff(LED4);\r
- /* BlinkSpeed: 0 -> 1 -> 2, then re-cycle */ \r
- BlinkSpeed ++ ; \r
- }\r
- }\r
- }\r
- count++;\r
- Delay(100);\r
- /* BlinkSpeed: 0 */ \r
- if(BlinkSpeed == 0)\r
- {\r
- if(4 == (count % 8))\r
- STM32vldiscovery_LEDOn(LED3);\r
- if(0 == (count % 8))\r
- STM32vldiscovery_LEDOff(LED3);\r
- }\r
- /* BlinkSpeed: 1 */ \r
- if(BlinkSpeed == 1)\r
- {\r
- if(2 == (count % 4))\r
- STM32vldiscovery_LEDOn(LED3);\r
- if(0 == (count % 4))\r
- STM32vldiscovery_LEDOff(LED3);\r
- } \r
- /* BlinkSpeed: 2 */ \r
- if(BlinkSpeed == 2)\r
- {\r
- if(0 == (count % 2))\r
- STM32vldiscovery_LEDOn(LED3);\r
- else\r
- STM32vldiscovery_LEDOff(LED3); \r
- } \r
- /* BlinkSpeed: 3 */ \r
- else if(BlinkSpeed == 3)\r
- BlinkSpeed = 0;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Inserts a delay time.\r
- * @param nTime: specifies the delay time length, in milliseconds.\r
- * @retval None\r
- */\r
-void Delay(uint32_t nTime)\r
-{ \r
- TimingDelay = nTime;\r
-\r
- while(TimingDelay != 0);\r
-}\r
-\r
-/**\r
- * @brief Decrements the TimingDelay variable.\r
- * @param None\r
- * @retval None\r
- */\r
-void TimingDelay_Decrement(void)\r
-{\r
- if (TimingDelay != 0x00)\r
- { \r
- TimingDelay--;\r
- }\r
-}\r
-\r
-#ifdef USE_FULL_ASSERT\r
-/**\r
- * @brief Reports the name of the source file and the source line number\r
- * where the assert_param error has occurred.\r
- * @param file: pointer to the source file name\r
- * @param line: assert_param error line source number\r
- * @retval None\r
- */\r
-void assert_failed(uint8_t* file, uint32_t line)\r
-{ \r
- /* User can add his own implementation to report the file name and line number,\r
- ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */\r
-\r
- /* Infinite loop */\r
- while (1)\r
- {\r
- }\r
-}\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file Demo/inc/stm32f10x_conf.h \r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 09/13/2010\r
- * @brief Library configuration file.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_CONF_H\r
-#define __STM32F10x_CONF_H\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-/* Uncomment the line below to enable peripheral header file inclusion */\r
-/* #include "stm32f10x_adc.h" */\r
-/* #include "stm32f10x_bkp.h" */\r
-/* #include "stm32f10x_can.h" */\r
-/* #include "stm32f10x_crc.h" */\r
-/* #include "stm32f10x_dac.h" */\r
-/* #include "stm32f10x_dbgmcu.h" */\r
-/* #include "stm32f10x_dma.h" */\r
-#include "stm32f10x_exti.h"\r
-#include "stm32f10x_flash.h"\r
-/* #include "stm32f10x_fsmc.h" */\r
-#include "stm32f10x_gpio.h"\r
-/* #include "stm32f10x_i2c.h" */\r
-/* #include "stm32f10x_iwdg.h" */\r
-#include "stm32f10x_pwr.h"\r
-#include "stm32f10x_rcc.h"\r
-/* #include "stm32f10x_rtc.h" */\r
-/* #include "stm32f10x_sdio.h" */\r
-/* #include "stm32f10x_spi.h" */\r
-/* #include "stm32f10x_tim.h" */\r
-/* #include "stm32f10x_usart.h" */\r
-/* #include "stm32f10x_wwdg.h" */\r
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-/* Uncomment the line below to expanse the "assert_param" macro in the \r
- Standard Peripheral Library drivers code */\r
-/* #define USE_FULL_ASSERT 1 */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-#ifdef USE_FULL_ASSERT\r
-\r
-/**\r
- * @brief The assert_param macro is used for function's parameters check.\r
- * @param expr: If expr is false, it calls assert_failed function\r
- * which reports the name of the source file and the source\r
- * line number of the call that failed. \r
- * If expr is true, it returns no value.\r
- * @retval None\r
- */\r
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))\r
-/* Exported functions ------------------------------------------------------- */\r
- void assert_failed(uint8_t* file, uint32_t line);\r
-#else\r
- #define assert_param(expr) ((void)0)\r
-#endif /* USE_FULL_ASSERT */\r
-\r
-#endif /* __STM32F10x_CONF_H */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file Demo/src/stm32f10x_it.c \r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 09/13/2010\r
- * @brief Main Interrupt Service Routines.\r
- * This file provides template for all exceptions handler and peripherals\r
- * interrupt service routine.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_it.h"\r
-void TimingDelay_Decrement(void);\r
-/** @addtogroup Demo\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/******************************************************************************/\r
-/* Cortex-M3 Processor Exceptions Handlers */\r
-/******************************************************************************/\r
-\r
-/**\r
- * @brief This function handles NMI exception.\r
- * @param None\r
- * @retval None\r
- */\r
-void NMI_Handler(void)\r
-{\r
-}\r
-\r
-/**\r
- * @brief This function handles Hard Fault exception.\r
- * @param None\r
- * @retval None\r
- */\r
-void HardFault_Handler(void)\r
-{\r
- /* Go to infinite loop when Hard Fault exception occurs */\r
- while (1)\r
- {\r
- }\r
-}\r
-\r
-/**\r
- * @brief This function handles Memory Manage exception.\r
- * @param None\r
- * @retval None\r
- */\r
-void MemManage_Handler(void)\r
-{\r
- /* Go to infinite loop when Memory Manage exception occurs */\r
- while (1)\r
- {\r
- }\r
-}\r
-\r
-/**\r
- * @brief This function handles Bus Fault exception.\r
- * @param None\r
- * @retval None\r
- */\r
-void BusFault_Handler(void)\r
-{\r
- /* Go to infinite loop when Bus Fault exception occurs */\r
- while (1)\r
- {\r
- }\r
-}\r
-\r
-/**\r
- * @brief This function handles Usage Fault exception.\r
- * @param None\r
- * @retval None\r
- */\r
-void UsageFault_Handler(void)\r
-{\r
- /* Go to infinite loop when Usage Fault exception occurs */\r
- while (1)\r
- {\r
- }\r
-}\r
-\r
-/**\r
- * @brief This function handles SVCall exception.\r
- * @param None\r
- * @retval None\r
- */\r
-void SVC_Handler(void)\r
-{\r
-}\r
-\r
-/**\r
- * @brief This function handles Debug Monitor exception.\r
- * @param None\r
- * @retval None\r
- */\r
-void DebugMon_Handler(void)\r
-{\r
-}\r
-\r
-/**\r
- * @brief This function handles PendSV_Handler exception.\r
- * @param None\r
- * @retval None\r
- */\r
-void PendSV_Handler(void)\r
-{\r
-}\r
-\r
-/**\r
- * @brief This function handles SysTick Handler.\r
- * @param None\r
- * @retval None\r
- */\r
-void SysTick_Handler(void)\r
-{\r
- TimingDelay_Decrement();\r
-}\r
-\r
-/******************************************************************************/\r
-/* STM32F10x Peripherals Interrupt Handlers */\r
-/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */\r
-/* available peripheral interrupt handler's name please refer to the startup */\r
-/* file (startup_stm32f10x_xx.s). */\r
-/******************************************************************************/\r
-\r
-/**\r
- * @brief This function handles PPP interrupt request.\r
- * @param None\r
- * @retval None\r
- */\r
-/*void PPP_IRQHandler(void)\r
-{\r
-}*/\r
-\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file Demo/inc/stm32f10x_it.h \r
- * @author MCD Team\r
- * @version V1.0.0\r
- * @date 09/13/2010\r
- * @brief This file contains the headers of the interrupt handlers.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_IT_H\r
-#define __STM32F10x_IT_H\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-extern vu32 TickValue;\r
-/* Exported constants --------------------------------------------------------*/\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-void NMI_Handler(void);\r
-void HardFault_Handler(void);\r
-void MemManage_Handler(void);\r
-void BusFault_Handler(void);\r
-void UsageFault_Handler(void);\r
-void SVC_Handler(void);\r
-void DebugMon_Handler(void);\r
-void PendSV_Handler(void);\r
-void SysTick_Handler(void);\r
-\r
-#endif /* __STM32F10x_IT_H */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file system_stm32f10x.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.\r
- ****************************************************************************** \r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ******************************************************************************\r
- */\r
-\r
-/** @addtogroup CMSIS\r
- * @{\r
- */\r
-\r
-/** @addtogroup stm32f10x_system\r
- * @{\r
- */ \r
- \r
-/** @addtogroup STM32F10x_System_Private_Includes\r
- * @{\r
- */\r
-\r
-#include "stm32f10x.h"\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Private_Defines\r
- * @{\r
- */\r
-\r
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)\r
- frequency (after reset the HSI is used as SYSCLK source)\r
- \r
- IMPORTANT NOTE:\r
- ============== \r
- 1. After each device reset the HSI is used as System clock source.\r
-\r
- 2. Please make sure that the selected System clock doesn't exceed your device's\r
- maximum frequency.\r
- \r
- 3. If none of the define below is enabled, the HSI is used as System clock\r
- source.\r
-\r
- 4. The System clock configuration functions provided within this file assume that:\r
- - For Low and Medium density Value line devices an external 8MHz crystal \r
- is used to drive the System clock.\r
- - For Low, Medium and High density devices an external 8MHz crystal is\r
- used to drive the System clock.\r
- - For Connectivity line devices an external 25MHz crystal is used to drive\r
- the System clock.\r
- If you are using different crystal you have to adapt those functions accordingly.\r
- */\r
- \r
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) \r
-/* #define SYSCLK_FREQ_HSE HSE_Value */\r
- #define SYSCLK_FREQ_24MHz 24000000\r
-#else\r
-/* #define SYSCLK_FREQ_HSE HSE_Value */\r
-/* #define SYSCLK_FREQ_24MHz 24000000 */ \r
-/* #define SYSCLK_FREQ_36MHz 36000000 */\r
-/* #define SYSCLK_FREQ_48MHz 48000000 */\r
-/* #define SYSCLK_FREQ_56MHz 56000000 */\r
-#define SYSCLK_FREQ_72MHz 72000000\r
-#endif\r
-\r
-/*!< Uncomment the following line if you need to use external SRAM mounted\r
- on STM3210E-EVAL board (STM32 High density and XL-density devices) as data memory */ \r
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL)\r
-/* #define DATA_IN_ExtSRAM */\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Private_Variables\r
- * @{\r
- */\r
-\r
-/*******************************************************************************\r
-* Clock Definitions\r
-*******************************************************************************/\r
-#ifdef SYSCLK_FREQ_HSE\r
- uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */\r
-#elif defined SYSCLK_FREQ_24MHz\r
- uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */\r
-#elif defined SYSCLK_FREQ_36MHz\r
- uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */\r
-#elif defined SYSCLK_FREQ_48MHz\r
- uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */\r
-#elif defined SYSCLK_FREQ_56MHz\r
- uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */\r
-#elif defined SYSCLK_FREQ_72MHz\r
- uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */\r
-#else /*!< HSI Selected as System Clock source */\r
- uint32_t SystemCoreClock = HSI_Value; /*!< System Clock Frequency (Core Clock) */\r
-#endif\r
-\r
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-static void SetSysClock(void);\r
-\r
-#ifdef SYSCLK_FREQ_HSE\r
- static void SetSysClockToHSE(void);\r
-#elif defined SYSCLK_FREQ_24MHz\r
- static void SetSysClockTo24(void);\r
-#elif defined SYSCLK_FREQ_36MHz\r
- static void SetSysClockTo36(void);\r
-#elif defined SYSCLK_FREQ_48MHz\r
- static void SetSysClockTo48(void);\r
-#elif defined SYSCLK_FREQ_56MHz\r
- static void SetSysClockTo56(void); \r
-#elif defined SYSCLK_FREQ_72MHz\r
- static void SetSysClockTo72(void);\r
-#endif\r
-\r
-#ifdef DATA_IN_ExtSRAM\r
- static void SystemInit_ExtMemCtl(void); \r
-#endif /* DATA_IN_ExtSRAM */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Setup the microcontroller system\r
- * Initialize the Embedded Flash Interface, the PLL and update the \r
- * SystemCoreClock variable.\r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemInit (void)\r
-{\r
- /* Reset the RCC clock configuration to the default reset state(for debug purpose) */\r
- /* Set HSION bit */\r
- RCC->CR |= (uint32_t)0x00000001;\r
-\r
- /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */\r
-#ifndef STM32F10X_CL\r
- RCC->CFGR &= (uint32_t)0xF8FF0000;\r
-#else\r
- RCC->CFGR &= (uint32_t)0xF0FF0000;\r
-#endif /* STM32F10X_CL */ \r
- \r
- /* Reset HSEON, CSSON and PLLON bits */\r
- RCC->CR &= (uint32_t)0xFEF6FFFF;\r
-\r
- /* Reset HSEBYP bit */\r
- RCC->CR &= (uint32_t)0xFFFBFFFF;\r
-\r
- /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */\r
- RCC->CFGR &= (uint32_t)0xFF80FFFF;\r
-\r
-#ifdef STM32F10X_CL\r
- /* Reset PLL2ON and PLL3ON bits */\r
- RCC->CR &= (uint32_t)0xEBFFFFFF;\r
-\r
- /* Disable all interrupts and clear pending bits */\r
- RCC->CIR = 0x00FF0000;\r
-\r
- /* Reset CFGR2 register */\r
- RCC->CFGR2 = 0x00000000;\r
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) \r
- /* Disable all interrupts and clear pending bits */\r
- RCC->CIR = 0x009F0000;\r
-\r
- /* Reset CFGR2 register */\r
- RCC->CFGR2 = 0x00000000; \r
-#else\r
- /* Disable all interrupts and clear pending bits */\r
- RCC->CIR = 0x009F0000;\r
-#endif /* STM32F10X_CL */\r
- \r
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL)\r
- #ifdef DATA_IN_ExtSRAM\r
- SystemInit_ExtMemCtl(); \r
- #endif /* DATA_IN_ExtSRAM */\r
-#endif \r
-\r
- /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */\r
- /* Configure the Flash Latency cycles and enable prefetch buffer */\r
- SetSysClock();\r
-}\r
-\r
-/**\r
- * @brief Update SystemCoreClock according to Clock Register Values\r
- * @note None\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemCoreClockUpdate (void)\r
-{\r
- uint32_t tmp = 0, pllmull = 0, pllsource = 0;\r
-\r
-#ifdef STM32F10X_CL\r
- uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;\r
-#endif /* STM32F10X_CL */\r
-\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
- uint32_t prediv1factor = 0;\r
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL */\r
- \r
- /* Get SYSCLK source -------------------------------------------------------*/\r
- tmp = RCC->CFGR & RCC_CFGR_SWS;\r
- \r
- switch (tmp)\r
- {\r
- case 0x00: /* HSI used as system clock */\r
- SystemCoreClock = HSI_Value;\r
- break;\r
- case 0x04: /* HSE used as system clock */\r
- SystemCoreClock = HSE_Value;\r
- break;\r
- case 0x08: /* PLL used as system clock */\r
-\r
- /* Get PLL clock source and multiplication factor ----------------------*/\r
- pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;\r
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
- \r
-#ifndef STM32F10X_CL \r
- pllmull = ( pllmull >> 18) + 2;\r
- \r
- if (pllsource == 0x00)\r
- {\r
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */\r
- SystemCoreClock = (HSI_Value >> 1) * pllmull;\r
- }\r
- else\r
- {\r
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;\r
- /* HSE oscillator clock selected as PREDIV1 clock entry */\r
- SystemCoreClock = (HSE_Value / prediv1factor) * pllmull; \r
- #else\r
- /* HSE selected as PLL clock entry */\r
- if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)\r
- {/* HSE oscillator clock divided by 2 */\r
- SystemCoreClock = (HSE_Value >> 1) * pllmull;\r
- }\r
- else\r
- {\r
- SystemCoreClock = HSE_Value * pllmull;\r
- }\r
- #endif\r
- }\r
-#else\r
- pllmull = pllmull >> 18;\r
- \r
- if (pllmull != 0x0D)\r
- {\r
- pllmull += 2;\r
- }\r
- else\r
- { /* PLL multiplication factor = PLL input clock * 6.5 */\r
- pllmull = 13 / 2; \r
- }\r
- \r
- if (pllsource == 0x00)\r
- {\r
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */\r
- SystemCoreClock = (HSI_Value >> 1) * pllmull;\r
- }\r
- else\r
- {/* PREDIV1 selected as PLL clock entry */\r
- \r
- /* Get PREDIV1 clock source and division factor */\r
- prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;\r
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;\r
- \r
- if (prediv1source == 0)\r
- { \r
- /* HSE oscillator clock selected as PREDIV1 clock entry */\r
- SystemCoreClock = (HSE_Value / prediv1factor) * pllmull; \r
- }\r
- else\r
- {/* PLL2 clock selected as PREDIV1 clock entry */\r
- \r
- /* Get PREDIV2 division factor and PLL2 multiplication factor */\r
- prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;\r
- pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; \r
- SystemCoreClock = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull; \r
- }\r
- }\r
-#endif /* STM32F10X_CL */ \r
- break;\r
-\r
- default:\r
- SystemCoreClock = HSI_Value;\r
- break;\r
- }\r
- \r
- /* Compute HCLK clock frequency ----------------*/\r
- /* Get HCLK prescaler */\r
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
- /* HCLK clock frequency */\r
- SystemCoreClock >>= tmp; \r
-}\r
-\r
-/**\r
- * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClock(void)\r
-{\r
-#ifdef SYSCLK_FREQ_HSE\r
- SetSysClockToHSE();\r
-#elif defined SYSCLK_FREQ_24MHz\r
- SetSysClockTo24();\r
-#elif defined SYSCLK_FREQ_36MHz\r
- SetSysClockTo36();\r
-#elif defined SYSCLK_FREQ_48MHz\r
- SetSysClockTo48();\r
-#elif defined SYSCLK_FREQ_56MHz\r
- SetSysClockTo56(); \r
-#elif defined SYSCLK_FREQ_72MHz\r
- SetSysClockTo72();\r
-#endif\r
- \r
- /* If none of the define above is enabled, the HSI is used as System clock\r
- source (default after reset) */ \r
-}\r
-\r
-/**\r
- * @brief Setup the external memory controller. Called in startup_stm32f10x.s \r
- * before jump to __main\r
- * @param None\r
- * @retval None\r
- */ \r
-#ifdef DATA_IN_ExtSRAM\r
-/**\r
- * @brief Setup the external memory controller. \r
- * Called in startup_stm32f10x_xx.s/.c before jump to main.\r
- * This function configures the external SRAM mounted on STM3210E-EVAL\r
- * board (STM32 High density devices). This SRAM will be used as program\r
- * data memory (including heap and stack).\r
- * @param None\r
- * @retval None\r
- */ \r
-void SystemInit_ExtMemCtl(void) \r
-{\r
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is \r
- required, then adjust the Register Addresses */\r
-\r
- /* Enable FSMC clock */\r
- RCC->AHBENR = 0x00000114;\r
- \r
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ \r
- RCC->APB2ENR = 0x000001E0;\r
- \r
-/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/\r
-/*---------------- SRAM Address lines configuration -------------------------*/\r
-/*---------------- NOE and NWE configuration --------------------------------*/ \r
-/*---------------- NE3 configuration ----------------------------------------*/\r
-/*---------------- NBL0, NBL1 configuration ---------------------------------*/\r
- \r
- GPIOD->CRL = 0x44BB44BB; \r
- GPIOD->CRH = 0xBBBBBBBB;\r
-\r
- GPIOE->CRL = 0xB44444BB; \r
- GPIOE->CRH = 0xBBBBBBBB;\r
-\r
- GPIOF->CRL = 0x44BBBBBB; \r
- GPIOF->CRH = 0xBBBB4444;\r
-\r
- GPIOG->CRL = 0x44BBBBBB; \r
- GPIOG->CRH = 0x44444B44;\r
- \r
-/*---------------- FSMC Configuration ---------------------------------------*/ \r
-/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/\r
- \r
- FSMC_Bank1->BTCR[4] = 0x00001011;\r
- FSMC_Bank1->BTCR[5] = 0x00000200;\r
-}\r
-#endif /* DATA_IN_ExtSRAM */\r
-\r
-#ifdef SYSCLK_FREQ_HSE\r
-/**\r
- * @brief Selects HSE as System clock source and configure HCLK, PCLK2\r
- * and PCLK1 prescalers.\r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClockToHSE(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
- /* Enable HSE */ \r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
- StartUpCounter++; \r
- } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
- {\r
- HSEStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSEStatus = (uint32_t)0x00;\r
- } \r
-\r
- if (HSEStatus == (uint32_t)0x01)\r
- {\r
-\r
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL \r
- /* Enable Prefetch Buffer */\r
- FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
- /* Flash 0 wait state */\r
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
-\r
-#ifndef STM32F10X_CL\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;\r
-#else\r
- if (HSE_Value <= 24000000)\r
- {\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;\r
- }\r
- else\r
- {\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;\r
- }\r
-#endif /* STM32F10X_CL */\r
-#endif\r
- \r
- /* HCLK = SYSCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- \r
- /* PCLK2 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
- \r
- /* Select HSE as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; \r
-\r
- /* Wait till HSE is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)\r
- {\r
- }\r
- }\r
- else\r
- { /* If HSE fails to start-up, the application will have wrong clock \r
- configuration. User can add here some code to deal with this error */\r
- } \r
-}\r
-#elif defined SYSCLK_FREQ_24MHz\r
-/**\r
- * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 \r
- * and PCLK1 prescalers.\r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClockTo24(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
- /* Enable HSE */ \r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
- StartUpCounter++; \r
- } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
- {\r
- HSEStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSEStatus = (uint32_t)0x00;\r
- } \r
-\r
- if (HSEStatus == (uint32_t)0x01)\r
- {\r
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL \r
- /* Enable Prefetch Buffer */\r
- FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
- /* Flash 0 wait state */\r
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; \r
-#endif\r
- \r
- /* HCLK = SYSCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- \r
- /* PCLK2 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
- \r
-#ifdef STM32F10X_CL\r
- /* Configure PLLs ------------------------------------------------------*/\r
- /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ \r
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
- RCC_CFGR_PLLMULL6); \r
-\r
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ \r
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);\r
- \r
- /* Enable PLL2 */\r
- RCC->CR |= RCC_CR_PLL2ON;\r
- /* Wait till PLL2 is ready */\r
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
- {\r
- } \r
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
- /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);\r
-#else \r
- /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);\r
-#endif /* STM32F10X_CL */\r
-\r
- /* Enable PLL */\r
- RCC->CR |= RCC_CR_PLLON;\r
-\r
- /* Wait till PLL is ready */\r
- while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
- {\r
- }\r
-\r
- /* Select PLL as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
-\r
- /* Wait till PLL is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
- {\r
- }\r
- }\r
- else\r
- { /* If HSE fails to start-up, the application will have wrong clock \r
- configuration. User can add here some code to deal with this error */\r
- } \r
-}\r
-#elif defined SYSCLK_FREQ_36MHz\r
-/**\r
- * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 \r
- * and PCLK1 prescalers. \r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClockTo36(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
- /* Enable HSE */ \r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
- StartUpCounter++; \r
- } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
- {\r
- HSEStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSEStatus = (uint32_t)0x00;\r
- } \r
-\r
- if (HSEStatus == (uint32_t)0x01)\r
- {\r
- /* Enable Prefetch Buffer */\r
- FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
- /* Flash 1 wait state */\r
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; \r
- \r
- /* HCLK = SYSCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- \r
- /* PCLK2 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
- \r
-#ifdef STM32F10X_CL\r
- /* Configure PLLs ------------------------------------------------------*/\r
- \r
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ \r
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
- RCC_CFGR_PLLMULL9); \r
-\r
- /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */\r
- \r
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);\r
- \r
- /* Enable PLL2 */\r
- RCC->CR |= RCC_CR_PLL2ON;\r
- /* Wait till PLL2 is ready */\r
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
- {\r
- }\r
- \r
-#else \r
- /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);\r
-#endif /* STM32F10X_CL */\r
-\r
- /* Enable PLL */\r
- RCC->CR |= RCC_CR_PLLON;\r
-\r
- /* Wait till PLL is ready */\r
- while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
- {\r
- }\r
-\r
- /* Select PLL as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
-\r
- /* Wait till PLL is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
- {\r
- }\r
- }\r
- else\r
- { /* If HSE fails to start-up, the application will have wrong clock \r
- configuration. User can add here some code to deal with this error */\r
- } \r
-}\r
-#elif defined SYSCLK_FREQ_48MHz\r
-/**\r
- * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 \r
- * and PCLK1 prescalers. \r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClockTo48(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
- /* Enable HSE */ \r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
- StartUpCounter++; \r
- } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
- {\r
- HSEStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSEStatus = (uint32_t)0x00;\r
- } \r
-\r
- if (HSEStatus == (uint32_t)0x01)\r
- {\r
- /* Enable Prefetch Buffer */\r
- FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
- /* Flash 1 wait state */\r
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; \r
- \r
- /* HCLK = SYSCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- \r
- /* PCLK2 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
- \r
-#ifdef STM32F10X_CL\r
- /* Configure PLLs ------------------------------------------------------*/\r
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
- \r
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
- \r
- /* Enable PLL2 */\r
- RCC->CR |= RCC_CR_PLL2ON;\r
- /* Wait till PLL2 is ready */\r
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
- {\r
- }\r
- \r
- \r
- /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ \r
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
- RCC_CFGR_PLLMULL6); \r
-#else \r
- /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);\r
-#endif /* STM32F10X_CL */\r
-\r
- /* Enable PLL */\r
- RCC->CR |= RCC_CR_PLLON;\r
-\r
- /* Wait till PLL is ready */\r
- while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
- {\r
- }\r
-\r
- /* Select PLL as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
-\r
- /* Wait till PLL is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
- {\r
- }\r
- }\r
- else\r
- { /* If HSE fails to start-up, the application will have wrong clock \r
- configuration. User can add here some code to deal with this error */\r
- } \r
-}\r
-\r
-#elif defined SYSCLK_FREQ_56MHz\r
-/**\r
- * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 \r
- * and PCLK1 prescalers. \r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClockTo56(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
- /* Enable HSE */ \r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
- StartUpCounter++; \r
- } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
- {\r
- HSEStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSEStatus = (uint32_t)0x00;\r
- } \r
-\r
- if (HSEStatus == (uint32_t)0x01)\r
- {\r
- /* Enable Prefetch Buffer */\r
- FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
- /* Flash 2 wait state */\r
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; \r
- \r
- /* HCLK = SYSCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- \r
- /* PCLK2 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
-\r
-#ifdef STM32F10X_CL\r
- /* Configure PLLs ------------------------------------------------------*/\r
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
- \r
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
- \r
- /* Enable PLL2 */\r
- RCC->CR |= RCC_CR_PLL2ON;\r
- /* Wait till PLL2 is ready */\r
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
- {\r
- }\r
- \r
- \r
- /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ \r
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
- RCC_CFGR_PLLMULL7); \r
-#else \r
- /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);\r
-\r
-#endif /* STM32F10X_CL */\r
-\r
- /* Enable PLL */\r
- RCC->CR |= RCC_CR_PLLON;\r
-\r
- /* Wait till PLL is ready */\r
- while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
- {\r
- }\r
-\r
- /* Select PLL as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
-\r
- /* Wait till PLL is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
- {\r
- }\r
- }\r
- else\r
- { /* If HSE fails to start-up, the application will have wrong clock \r
- configuration. User can add here some code to deal with this error */\r
- } \r
-}\r
-\r
-#elif defined SYSCLK_FREQ_72MHz\r
-/**\r
- * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 \r
- * and PCLK1 prescalers. \r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClockTo72(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
- /* Enable HSE */ \r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
- StartUpCounter++; \r
- } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
- {\r
- HSEStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSEStatus = (uint32_t)0x00;\r
- } \r
-\r
- if (HSEStatus == (uint32_t)0x01)\r
- {\r
- /* Enable Prefetch Buffer */\r
- FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
- /* Flash 2 wait state */\r
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; \r
-\r
- \r
- /* HCLK = SYSCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- \r
- /* PCLK2 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
-\r
-#ifdef STM32F10X_CL\r
- /* Configure PLLs ------------------------------------------------------*/\r
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
- \r
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
- \r
- /* Enable PLL2 */\r
- RCC->CR |= RCC_CR_PLL2ON;\r
- /* Wait till PLL2 is ready */\r
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
- {\r
- }\r
- \r
- \r
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ \r
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
- RCC_CFGR_PLLMULL9); \r
-#else \r
- /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |\r
- RCC_CFGR_PLLMULL));\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);\r
-#endif /* STM32F10X_CL */\r
-\r
- /* Enable PLL */\r
- RCC->CR |= RCC_CR_PLLON;\r
-\r
- /* Wait till PLL is ready */\r
- while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
- {\r
- }\r
- \r
- /* Select PLL as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
-\r
- /* Wait till PLL is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
- {\r
- }\r
- }\r
- else\r
- { /* If HSE fails to start-up, the application will have wrong clock \r
- configuration. User can add here some code to deal with this error */\r
- }\r
-}\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/**\r
- * @}\r
- */ \r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-Don't trust many of these examples yet... A lot of them are a work in
-progress...
-
-A good source of examples is in the libopencm3 sources: http://sourceforge.net/projects/libopencm3/
-
-
+++ /dev/null
-CC=arm-none-eabi-gcc
-OBJCOPY=arm-none-eabi-objcopy
-
-DEF_CFLAGS=-g -O2 -mlittle-endian -mthumb -ffreestanding -nostdlib -nostdinc
-
-# to run from SRAM
-DEF_CFLAGS+=-Wl,-Ttext,0x20000000 -Wl,-e,0x20000000
-
-# to write to flash then run
-# DEF_CFLAGS+=-Wl,-Ttext,0x08000000 -Wl,-e,0x08000000
-
-CFLAGS_VL=$(DEF_CFLAGS) -mcpu=cortex-m3 -DCONFIG_STM32VL_DISCOVERY=1
-CFLAGS_L=$(DEF_CFLAGS) -mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY
-CFLAGS_F4=$(DEF_CFLAGS) -mcpu=cortex-m4 -DCONFIG_STM32F4_DISCOVERY=1
-CFLAGS_F0=$(DEF_CFLAGS) -mcpu=cortex-m0 -DCONFIG_STM32F0_DISCOVERY=1
-
-all: blink_32VL.elf blink_32L.elf blink_F4.elf blink_F0.elf
-
-%.bin: %.elf
- $(OBJCOPY) -O binary $^ $@
-
-blink_32VL.elf: main.c
- $(CC) $(CFLAGS_VL) $^ -o $@
-blink_32L.elf: main.c
- $(CC) $(CFLAGS_L) $^ -o $@
-blink_F4.elf: main.c
- $(CC) $(CFLAGS_F4) $^ -o $@
-blink_F0.elf: main.c
- $(CC) $(CFLAGS_F0) $^ -o $@
-
-clean:
- rm -rf *.elf
- rm -rf *.bin
-
-.PHONY: all clean
+++ /dev/null
-/* missing type */
-
-typedef unsigned int uint32_t;
-void main(void);
-
-/* hardware configuration */
-
-#if CONFIG_STM32VL_DISCOVERY
-
-#define GPIOC 0x40011000 /* port C */
-#define GPIOC_CRH (GPIOC + 0x04) /* port configuration register high */
-#define LED_PORT_ODR (GPIOC + 0x0c) /* port output data register */
-
-#define LED_BLUE (1 << 8) /* port C, pin 8 */
-#define LED_GREEN (1 << 9) /* port C, pin 9 */
-#define LED_ORANGE 0
-#define LED_RED 0
-
-static inline void setup_leds(void)
-{
- *(volatile uint32_t*)GPIOC_CRH = 0x44444411;
-}
-
-#elif CONFIG_STM32L_DISCOVERY
-
-#define GPIOB 0x40020400 /* port B */
-#define GPIOB_MODER (GPIOB + 0x00) /* port mode register */
-#define LED_PORT_ODR (GPIOB + 0x14) /* port output data register */
-
-#define LED_BLUE (1 << 6) /* port B, pin 6 */
-#define LED_GREEN (1 << 7) /* port B, pin 7 */
-#define LED_ORANGE 0
-#define LED_RED 0
-
-static inline void setup_leds(void)
-{
- /* configure port 6 and 7 as output */
- *(volatile uint32_t*)GPIOB_MODER |= (1 << (7 * 2)) | (1 << (6 * 2));
-}
-
-#elif CONFIG_STM32F4_DISCOVERY
-
-#define GPIOD 0x40020C00 /* port D */
-#define GPIOD_MODER (GPIOD + 0x00) /* port mode register */
-#define LED_PORT_ODR (GPIOD + 0x14) /* port output data register */
-
-#define LED_GREEN (1 << 12) /* port D, pin 12 */
-#define LED_ORANGE (1 << 13) /* port D, pin 13 */
-#define LED_RED (1 << 14) /* port D, pin 14 */
-#define LED_BLUE (1 << 15) /* port D, pin 15 */
-
-void _tmain(void) {
- main();
-}
-static inline void setup_leds(void)
-{
- *(volatile uint32_t*)GPIOD_MODER |= (1 << (12 * 2)) | (1 << (13 * 2)) |
- (1 << (13 * 2)) | (1 << (14 * 2)) | (1 << (15 * 2));
-}
-
-#elif CONFIG_STM32F0_DISCOVERY
-
-#define GPIOC 0x48000800 /* port C */
-#define GPIOC_MODER (GPIOC + 0x00) /* port mode register */
-#define LED_PORT_ODR (GPIOC + 0x14) /* port output data register */
-
-#define LED_BLUE (1 << 8) /* port C, pin 8 */
-#define LED_GREEN (1 << 9) /* port C, pin 9 */
-#define LED_ORANGE 0
-#define LED_RED 0
-
-void _tmain(void) {
- main();
-}
-static inline void setup_leds(void)
-{
- /* configure port 8 and 9 as output */
- *(volatile uint32_t*)GPIOC_MODER |= (1 << (9* 2)) | (1 << (8 * 2));
-}
-
-#else
-#error "Architecture must be defined!"
-#endif /* otherwise, error */
-
-static inline void switch_leds_on(void)
-{
- *(volatile uint32_t*)LED_PORT_ODR = LED_BLUE | LED_GREEN | LED_ORANGE | LED_RED;
-}
-
-static inline void switch_leds_off(void)
-{
- *(volatile uint32_t*)LED_PORT_ODR = 0;
-}
-
-#define delay() \
-do { \
- register unsigned int i; \
- for (i = 0; i < 1000000; ++i) \
- __asm__ __volatile__ ("nop\n\t":::"memory"); \
-} while (0)
-
-/* static void __attribute__((naked)) __attribute__((used)) main(void) */
-void main(void)
-{
- setup_leds();
-
- while (1)
- {
- switch_leds_on();
- delay();
- switch_leds_off();
- delay();
- }
-}
+++ /dev/null
-EXECUTABLE=blink.elf
-BIN_IMAGE=blink.bin
-
-CC=arm-none-eabi-gcc
-OBJCOPY=arm-none-eabi-objcopy
-
-CFLAGS=-O3 -mlittle-endian -mthumb
-ifeq ($(CONFIG_STM32L_DISCOVERY), 1)
- CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY=1
-else ifeq ($(CONFIG_STM32VL_DISCOVERY), 1)
- CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32VL_DISCOVERY=1
-else ifeq ($(CONFIG_STM32F4_DISCOVERY), 1)
- CFLAGS+=-mcpu=cortex-m4 -DCONFIG_STM32F4_DISCOVERY=1
-else
-$(error "must specify CONFIG_ for board!")
-endif
-CFLAGS+=-ffreestanding -nostdlib -nostdinc
-
-# to run from FLASH
-CFLAGS+=-Wl,-T,stm32_flash.ld
-
-PLATFORM=stm32l1xx
-LIBS_STM_PATH=../libs_stm
-
-# stm32l_discovery lib
-CFLAGS+=-I$(LIBS_STM_PATH)/inc/base
-CFLAGS+=-I$(LIBS_STM_PATH)/inc/core_support
-CFLAGS+=-I$(LIBS_STM_PATH)/inc/device_support
-CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM)
-
-LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32_stdperiph_l1xx
-
-all: $(BIN_IMAGE)
-
-$(BIN_IMAGE): $(EXECUTABLE)
- $(OBJCOPY) -O binary $^ $@
-
-$(EXECUTABLE): main.c system_stm32l1xx.c startup_stm32l1xx_md.s
- $(CC) $(CFLAGS) $^ -o $@ $(LDFLAGS)
-
-clean:
- rm -rf $(EXECUTABLE)
- rm -rf $(BIN_IMAGE)
-
-write: all
- sudo ../../flash/flash write ./blink.bin 0x08000000
-
-.PHONY: all clean
+++ /dev/null
- /**\r
- ******************************************************************************\r
- * @file discover_board.h\r
- * @author Microcontroller Division\r
- * @version V1.0.2\r
- * @date September-2011\r
- * @brief Input/Output defines\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-\r
-#ifndef __DISCOVER_BOARD_H\r
-#define __DISCOVER_BOARD_H\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-/* #include "stm32l1xx.h" */\r
-\r
-#define bool _Bool\r
-#define FALSE 0\r
-#define TRUE !FALSE\r
-\r
-/* MACROs for SET, RESET or TOGGLE Output port */\r
-\r
-#define GPIO_HIGH(a,b) a->BSRRL = b\r
-#define GPIO_LOW(a,b) a->BSRRH = b\r
-#define GPIO_TOGGLE(a,b) a->ODR ^= b \r
-\r
-#define USERBUTTON_GPIO_PORT GPIOA\r
-#define USERBUTTON_GPIO_PIN GPIO_Pin_0\r
-#define USERBUTTON_GPIO_CLK RCC_AHBPeriph_GPIOA\r
-\r
-#define LD_GPIO_PORT GPIOB\r
-#define LD_GREEN_GPIO_PIN GPIO_Pin_7\r
-#define LD_BLUE_GPIO_PIN GPIO_Pin_6\r
-#define LD_GPIO_PORT_CLK RCC_AHBPeriph_GPIOB\r
-\r
-#define CTN_GPIO_PORT GPIOC\r
-#define CTN_CNTEN_GPIO_PIN GPIO_Pin_13\r
-#define CTN_GPIO_CLK RCC_AHBPeriph_GPIOC\r
-\r
-#define WAKEUP_GPIO_PORT GPIOA\r
-\r
-#define IDD_MEASURE_PORT GPIOA\r
-#define IDD_MEASURE GPIO_Pin_4\r
-\r
-\r
-#endif\r
-\r
-\r
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/* base headers */
-#include "stdint.h"
-
-/* libstm32l_discovery headers */
-#include "stm32l1xx_gpio.h"
-#include "stm32l1xx_adc.h"
-#include "stm32l1xx_lcd.h"
-#include "stm32l1xx_rcc.h"
-#include "stm32l1xx_rtc.h"
-#include "stm32l1xx_exti.h"
-#include "stm32l1xx_pwr.h"
-#include "stm32l1xx_flash.h"
-#include "stm32l1xx_syscfg.h"
-#include "stm32l1xx_dbgmcu.h"
-
-/* board specific macros */
-#include "discover_board.h"
-
-
-/* hardware configuration */
-
-#if CONFIG_STM32VL_DISCOVERY
-
-# define GPIOC 0x40011000 /* port C */
-# define GPIOC_CRH (GPIOC + 0x04) /* port configuration register high */
-# define GPIOC_ODR (GPIOC + 0x0c) /* port output data register */
-
-# define LED_BLUE (1 << 8) /* port C, pin 8 */
-# define LED_GREEN (1 << 9) /* port C, pin 9 */
-
-static inline void setup_leds(void)
-{
- *(volatile uint32_t*)GPIOC_CRH = 0x44444411;
-}
-
-static inline void switch_leds_on(void)
-{
- *(volatile uint32_t*)GPIOC_ODR = LED_BLUE | LED_GREEN;
-}
-
-static inline void switch_leds_off(void)
-{
- *(volatile uint32_t*)GPIOC_ODR = 0;
-}
-
-#elif CONFIG_STM32L_DISCOVERY
-
-# define GPIOB_MODER (GPIOB + 0x00) /* port mode register */
-# define GPIOB_ODR (GPIOB + 0x14) /* port output data register */
-
-# define LED_BLUE (1 << 6) /* port B, pin 6 */
-# define LED_GREEN (1 << 7) /* port B, pin 7 */
-
-static inline void setup_leds(void)
-{
- /* configure port 6 and 7 as output */
- *(volatile uint32_t*)GPIOB_MODER |= (1 << (7 * 2)) | (1 << (6 * 2));
-}
-
-static inline void switch_leds_on(void)
-{
- GPIO_HIGH(LD_GPIO_PORT, LD_GREEN_GPIO_PIN);
- GPIO_HIGH(LD_GPIO_PORT, LD_BLUE_GPIO_PIN);
-}
-
-static inline void switch_leds_off(void)
-{
- GPIO_LOW(LD_GPIO_PORT, LD_GREEN_GPIO_PIN);
- GPIO_LOW(LD_GPIO_PORT, LD_BLUE_GPIO_PIN);
-}
-
-#elif CONFIG_STM32F4_DISCOVERY
-
-//#define GPIOD 0x40020C00 /* port D */
-# define GPIOD_MODER (GPIOD + 0x00) /* port mode register */
-# define GPIOD_ODR (GPIOD + 0x14) /* port output data register */
-
-# define LED_GREEN (1 << 12) /* port B, pin 12 */
-# define LED_ORANGE (1 << 13) /* port B, pin 13 */
-# define LED_RED (1 << 14) /* port B, pin 14 */
-# define LED_BLUE (1 << 15) /* port B, pin 15 */
-
-void _tmain(void) {
- main();
-}
-static inline void setup_leds(void)
-{
- *(volatile uint32_t*)GPIOD_MODER |= (1 << (12 * 2)) | (1 << (13 * 2)) |
- (1 << (13 * 2)) | (1 << (14 * 2)) | (1 << (15 * 2));
-}
-
-
-static inline void switch_leds_on(void)
-{
- *(volatile uint32_t*)GPIOD_ODR = LED_GREEN | LED_RED ;
-}
-
-static inline void switch_leds_off(void)
-{
- *(volatile uint32_t*)GPIOD_ODR = 0;
-}
-
-#endif /* otherwise, error */
-
-
-#define delay() \
-do { \
- volatile unsigned int i; \
- for (i = 0; i < 1000000; ++i) \
- __asm__ __volatile__ ("nop\n\t":::"memory"); \
-} while (0)
-
-
-static void RCC_Configuration(void)
-{
- /* Enable HSI Clock */
- RCC_HSICmd(ENABLE);
-
- /*!< Wait till HSI is ready */
- while (RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET)
- {}
-
- RCC_SYSCLKConfig(RCC_SYSCLKSource_HSI);
-
- RCC_MSIRangeConfig(RCC_MSIRange_6);
-
- RCC_HSEConfig(RCC_HSE_OFF);
- if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET )
- {
- while(1);
- }
-}
-
-
-static void RTC_Configuration(void)
-{
- /* Allow access to the RTC */
- PWR_RTCAccessCmd(ENABLE);
-
- /* Reset Backup Domain */
- RCC_RTCResetCmd(ENABLE);
- RCC_RTCResetCmd(DISABLE);
-
- /* LSE Enable */
- RCC_LSEConfig(RCC_LSE_ON);
-
- /* Wait till LSE is ready */
- while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
- {}
-
- RCC_RTCCLKCmd(ENABLE);
-
- /* LCD Clock Source Selection */
- RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
-
-}
-
-void main(void)
-{
- static RCC_ClocksTypeDef RCC_Clocks;
- static GPIO_InitTypeDef GPIO_InitStructure;
-
- /* Configure Clocks for Application need */
- RCC_Configuration();
-
- /* Configure RTC Clocks */
- RTC_Configuration();
-
- /* Set internal voltage regulator to 1.8V */
- PWR_VoltageScalingConfig(PWR_VoltageScaling_Range1);
-
- /* Wait Until the Voltage Regulator is ready */
- while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET) ;
-
- /* configure gpios */
-
- /* Enable GPIOs clock */
- RCC_AHBPeriphClockCmd(LD_GPIO_PORT_CLK, ENABLE);
-
- /* Configure the GPIO_LED pins LD3 & LD4*/
- GPIO_InitStructure.GPIO_Pin = LD_GREEN_GPIO_PIN | LD_BLUE_GPIO_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
- GPIO_Init(LD_GPIO_PORT, &GPIO_InitStructure);
- GPIO_LOW(LD_GPIO_PORT, LD_GREEN_GPIO_PIN);
- GPIO_LOW(LD_GPIO_PORT, LD_BLUE_GPIO_PIN);
-
- while (1)
- {
- switch_leds_on();
- delay();
- switch_leds_off();
- delay();
- }
-}
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file startup_stm32l1xx_md.s\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief STM32L1xx Ultra Low Power Medium-density Devices vector table for \r
- * RIDE7 toolchain.\r
- * This module performs:\r
- * - Set the initial SP\r
- * - Set the initial PC == Reset_Handler,\r
- * - Set the vector table entries with the exceptions ISR address\r
- * - Branches to main in the C library (which eventually\r
- * calls main()).\r
- * After Reset the Cortex-M3 processor is in Thread mode,\r
- * priority is Privileged, and the Stack is set to Main.\r
- *******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ******************************************************************************* \r
- */\r
- \r
- .syntax unified\r
- .cpu cortex-m3\r
- .fpu softvfp\r
- .thumb\r
-\r
-.global g_pfnVectors\r
-.global Default_Handler\r
-\r
-/* start address for the initialization values of the .data section. \r
-defined in linker script */\r
-.word _sidata\r
-/* start address for the .data section. defined in linker script */ \r
-.word _sdata\r
-/* end address for the .data section. defined in linker script */\r
-.word _edata\r
-/* start address for the .bss section. defined in linker script */\r
-.word _sbss\r
-/* end address for the .bss section. defined in linker script */\r
-.word _ebss\r
-\r
-.equ BootRAM, 0xF108F85F\r
-/**\r
- * @brief This is the code that gets called when the processor first\r
- * starts execution following a reset event. Only the absolutely\r
- * necessary set is performed, after which the application\r
- * supplied main() routine is called. \r
- * @param None\r
- * @retval : None\r
-*/\r
-\r
- .section .text.Reset_Handler\r
- .weak Reset_Handler\r
- .type Reset_Handler, %function\r
-Reset_Handler:\r
-/* Copy the data segment initializers from flash to SRAM */ \r
- movs r1, #0\r
- b LoopCopyDataInit\r
-\r
-CopyDataInit:\r
- ldr r3, =_sidata\r
- ldr r3, [r3, r1]\r
- str r3, [r0, r1]\r
- adds r1, r1, #4\r
- \r
-LoopCopyDataInit:\r
- ldr r0, =_sdata\r
- ldr r3, =_edata\r
- adds r2, r0, r1\r
- cmp r2, r3\r
- bcc CopyDataInit\r
- ldr r2, =_sbss\r
- b LoopFillZerobss\r
-/* Zero fill the bss segment. */ \r
-FillZerobss:\r
- movs r3, #0\r
- str r3, [r2], #4\r
- \r
-LoopFillZerobss:\r
- ldr r3, = _ebss\r
- cmp r2, r3\r
- bcc FillZerobss\r
-/* Call the clock system intitialization function.*/\r
-/* let main do the system initialization */\r
- bl SystemInit\r
-/* Call the application's entry point.*/\r
- bl main\r
- bx lr\r
-.size Reset_Handler, .-Reset_Handler\r
-\r
-/**\r
- * @brief This is the code that gets called when the processor receives an \r
- * unexpected interrupt. This simply enters an infinite loop, preserving\r
- * the system state for examination by a debugger.\r
- *\r
- * @param None \r
- * @retval None \r
-*/\r
- .section .text.Default_Handler,"ax",%progbits\r
-Default_Handler:\r
-Infinite_Loop:\r
- b Infinite_Loop\r
- .size Default_Handler, .-Default_Handler\r
-/*******************************************************************************\r
-*\r
-* The minimal vector table for a Cortex M3. Note that the proper constructs\r
-* must be placed on this to ensure that it ends up at physical address\r
-* 0x0000.0000.\r
-*******************************************************************************/ \r
- .section .isr_vector,"a",%progbits\r
- .type g_pfnVectors, %object\r
- .size g_pfnVectors, .-g_pfnVectors\r
- \r
- \r
-g_pfnVectors:\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word SysTick_Handler\r
- .word WWDG_IRQHandler\r
- .word PVD_IRQHandler\r
- .word TAMPER_STAMP_IRQHandler\r
- .word RTC_WKUP_IRQHandler\r
- .word FLASH_IRQHandler\r
- .word RCC_IRQHandler\r
- .word EXTI0_IRQHandler\r
- .word EXTI1_IRQHandler\r
- .word EXTI2_IRQHandler\r
- .word EXTI3_IRQHandler\r
- .word EXTI4_IRQHandler\r
- .word DMA1_Channel1_IRQHandler\r
- .word DMA1_Channel2_IRQHandler\r
- .word DMA1_Channel3_IRQHandler\r
- .word DMA1_Channel4_IRQHandler\r
- .word DMA1_Channel5_IRQHandler\r
- .word DMA1_Channel6_IRQHandler\r
- .word DMA1_Channel7_IRQHandler\r
- .word ADC1_IRQHandler\r
- .word USB_HP_IRQHandler\r
- .word USB_LP_IRQHandler\r
- .word DAC_IRQHandler\r
- .word COMP_IRQHandler\r
- .word EXTI9_5_IRQHandler\r
- .word LCD_IRQHandler\r
- .word TIM9_IRQHandler\r
- .word TIM10_IRQHandler\r
- .word TIM11_IRQHandler\r
- .word TIM2_IRQHandler\r
- .word TIM3_IRQHandler\r
- .word TIM4_IRQHandler\r
- .word I2C1_EV_IRQHandler\r
- .word I2C1_ER_IRQHandler\r
- .word I2C2_EV_IRQHandler\r
- .word I2C2_ER_IRQHandler\r
- .word SPI1_IRQHandler\r
- .word SPI2_IRQHandler\r
- .word USART1_IRQHandler\r
- .word USART2_IRQHandler\r
- .word USART3_IRQHandler\r
- .word EXTI15_10_IRQHandler\r
- .word RTC_Alarm_IRQHandler\r
- .word USB_FS_WKUP_IRQHandler\r
- .word TIM6_IRQHandler\r
- .word TIM7_IRQHandler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word BootRAM /* @0x108. This is for boot in RAM mode for \r
- STM32L15x ULtra Low Power Medium-density devices. */\r
- \r
-/*******************************************************************************\r
-*\r
-* Provide weak aliases for each Exception handler to the Default_Handler. \r
-* As they are weak aliases, any function with the same name will override \r
-* this definition.\r
-*\r
-*******************************************************************************/\r
- \r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
-\r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
-\r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
-\r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-\r
- .weak SysTick_Handler\r
- .thumb_set SysTick_Handler,Default_Handler\r
-\r
- .weak WWDG_IRQHandler\r
- .thumb_set WWDG_IRQHandler,Default_Handler\r
-\r
- .weak PVD_IRQHandler\r
- .thumb_set PVD_IRQHandler,Default_Handler\r
-\r
- .weak TAMPER_STAMP_IRQHandler\r
- .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler\r
-\r
- .weak RTC_WKUP_IRQHandler\r
- .thumb_set RTC_WKUP_IRQHandler,Default_Handler\r
-\r
- .weak FLASH_IRQHandler\r
- .thumb_set FLASH_IRQHandler,Default_Handler\r
-\r
- .weak RCC_IRQHandler\r
- .thumb_set RCC_IRQHandler,Default_Handler\r
-\r
- .weak EXTI0_IRQHandler\r
- .thumb_set EXTI0_IRQHandler,Default_Handler\r
-\r
- .weak EXTI1_IRQHandler\r
- .thumb_set EXTI1_IRQHandler,Default_Handler\r
-\r
- .weak EXTI2_IRQHandler\r
- .thumb_set EXTI2_IRQHandler,Default_Handler\r
-\r
- .weak EXTI3_IRQHandler\r
- .thumb_set EXTI3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI4_IRQHandler\r
- .thumb_set EXTI4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel1_IRQHandler\r
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel2_IRQHandler\r
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel3_IRQHandler\r
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel4_IRQHandler\r
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel5_IRQHandler\r
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel6_IRQHandler\r
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel7_IRQHandler\r
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
-\r
- .weak ADC1_IRQHandler\r
- .thumb_set ADC1_IRQHandler,Default_Handler\r
-\r
- .weak USB_HP_IRQHandler\r
- .thumb_set USB_HP_IRQHandler,Default_Handler\r
-\r
- .weak USB_LP_IRQHandler\r
- .thumb_set USB_LP_IRQHandler,Default_Handler\r
-\r
- .weak DAC_IRQHandler\r
- .thumb_set DAC_IRQHandler,Default_Handler\r
-\r
- .weak COMP_IRQHandler\r
- .thumb_set COMP_IRQHandler,Default_Handler\r
-\r
- .weak EXTI9_5_IRQHandler\r
- .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
-\r
- .weak LCD_IRQHandler\r
- .thumb_set LCD_IRQHandler,Default_Handler\r
- \r
- .weak TIM9_IRQHandler\r
- .thumb_set TIM9_IRQHandler,Default_Handler\r
-\r
- .weak TIM10_IRQHandler\r
- .thumb_set TIM10_IRQHandler,Default_Handler\r
-\r
- .weak TIM11_IRQHandler\r
- .thumb_set TIM11_IRQHandler,Default_Handler\r
-\r
- .weak TIM2_IRQHandler\r
- .thumb_set TIM2_IRQHandler,Default_Handler\r
-\r
- .weak TIM3_IRQHandler\r
- .thumb_set TIM3_IRQHandler,Default_Handler\r
-\r
- .weak TIM4_IRQHandler\r
- .thumb_set TIM4_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_EV_IRQHandler\r
- .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_ER_IRQHandler\r
- .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_EV_IRQHandler\r
- .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_ER_IRQHandler\r
- .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
-\r
- .weak SPI1_IRQHandler\r
- .thumb_set SPI1_IRQHandler,Default_Handler\r
-\r
- .weak SPI2_IRQHandler\r
- .thumb_set SPI2_IRQHandler,Default_Handler\r
-\r
- .weak USART1_IRQHandler\r
- .thumb_set USART1_IRQHandler,Default_Handler\r
-\r
- .weak USART2_IRQHandler\r
- .thumb_set USART2_IRQHandler,Default_Handler\r
-\r
- .weak USART3_IRQHandler\r
- .thumb_set USART3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI15_10_IRQHandler\r
- .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
-\r
- .weak RTC_Alarm_IRQHandler\r
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler\r
-\r
- .weak USB_FS_WKUP_IRQHandler\r
- .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler\r
-\r
- .weak TIM6_IRQHandler\r
- .thumb_set TIM6_IRQHandler,Default_Handler\r
-\r
- .weak TIM7_IRQHandler\r
- .thumb_set TIM7_IRQHandler,Default_Handler\r
-\r
-/******************** (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***/\r
-\r
+++ /dev/null
-/*
-*****************************************************************************
-**
-** File : stm32_flash.ld
-**
-** Abstract : Linker script for STM32L152RB Device with
-** 128KByte FLASH, 16KByte RAM
-**
-** Set heap size, stack size and stack location according
-** to application requirements.
-**
-** Set memory bank area and size if external memory is used.
-**
-** Target : STMicroelectronics STM32
-**
-** Environment : Atollic TrueSTUDIO(R)
-**
-** Distribution: The file is distributed \93as is,\94 without any warranty
-** of any kind.
-**
-** (c)Copyright Atollic AB.
-** You may use this file as-is or modify it according to the needs of your
-** project. Distribution of this file (unmodified or modified) is not
-** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
-** rights to distribute the assembled, compiled & linked contents of this
-** file as part of an application binary file, provided that it is built
-** using the Atollic TrueSTUDIO(R) toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20004000; /* end of 16K RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0; /* required amount of heap */
-_Min_Stack_Size = 0x80; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
- RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K
- MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
- RW_EEPROM (rw) : ORIGIN = 0x08080000, LENGTH = 32
-}
-
-/* Define output sections */
-SECTIONS
-{
- /* The startup code goes first into FLASH */
- .isr_vector :
- {
- . = ALIGN(4);
- KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
- } >FLASH
-
- /* The program code and other data goes into FLASH */
- .text :
- {
- . = ALIGN(4);
- *(.text) /* .text sections (code) */
- *(.text*) /* .text* sections (code) */
- *(.rodata) /* .rodata sections (constants, strings, etc.) */
- *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
- *(.glue_7) /* glue arm to thumb code */
- *(.glue_7t) /* glue thumb to arm code */
- *(.eh_frame)
-
- KEEP (*(.init))
- KEEP (*(.fini))
-
- . = ALIGN(4);
- _etext = .; /* define a global symbols at end of code */
- } >FLASH
-
-
- .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
- .ARM : {
- __exidx_start = .;
- *(.ARM.exidx*)
- __exidx_end = .;
- } >FLASH
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array*))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >FLASH
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array*))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >FLASH
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(.fini_array*))
- KEEP (*(SORT(.fini_array.*)))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } >FLASH
-
- /* used by the startup to initialize data */
- _sidata = .;
-
- /* Initialized data sections goes into RAM, load LMA copy after code */
- .data : AT ( _sidata )
- {
- . = ALIGN(4);
- _sdata = .; /* create a global symbol at data start */
- *(.data) /* .data sections */
- *(.data*) /* .data* sections */
-
- . = ALIGN(4);
- _edata = .; /* define a global symbol at data end */
- } >RAM
-
- /* Uninitialized data section */
- . = ALIGN(4);
- .bss :
- {
- /* This is used by the startup in order to initialize the .bss secion */
- _sbss = .; /* define a global symbol at bss start */
- __bss_start__ = _sbss;
- *(.bss)
- *(.bss*)
- *(COMMON)
-
- . = ALIGN(4);
- _ebss = .; /* define a global symbol at bss end */
- __bss_end__ = _ebss;
- } >RAM
-
- /* User_heap_stack section, used to check that there is enough RAM left */
- ._user_heap_stack :
- {
- . = ALIGN(4);
- PROVIDE ( end = . );
- PROVIDE ( _end = . );
- . = . + _Min_Heap_Size;
- . = . + _Min_Stack_Size;
- . = ALIGN(4);
- } >RAM
-
- /* MEMORY_bank1 section, code must be located here explicitly */
- /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
- .memory_b1_text :
- {
- *(.mb1text) /* .mb1text sections (code) */
- *(.mb1text*) /* .mb1text* sections (code) */
- *(.mb1rodata) /* read-only data (constants) */
- *(.mb1rodata*)
- } >MEMORY_B1
-
- /* Remove information from the standard libraries */
- /DISCARD/ :
- {
- libc.a ( * )
- libm.a ( * )
- libgcc.a ( * )
- }
-
- .ARM.attributes 0 : { *(.ARM.attributes) }
-
- .DataFlash (NOLOAD): {*(.DataFlash)} >RW_EEPROM
-}
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file system_stm32l1xx.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 2-June-2011\r
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.\r
- * This file contains the system clock configuration for STM32L1xx Ultra\r
- * Low Medium-density devices, and is generated by the clock configuration\r
- * tool "STM32L1xx_Clock_Configuration_V1.0.0.xls".\r
- * \r
- * 1. This file provides two functions and one global variable to be called from \r
- * user application:\r
- * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier\r
- * and Divider factors, AHB/APBx prescalers and Flash settings),\r
- * depending on the configuration made in the clock xls tool. \r
- * This function is called at startup just after reset and \r
- * before branch to main program. This call is made inside\r
- * the "startup_stm32l1xx_md.s" file.\r
- * \r
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
- * by the user application to setup the SysTick \r
- * timer or configure other parameters.\r
- * \r
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
- * be called whenever the core clock is changed\r
- * during program execution. \r
- * \r
- * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.\r
- * Then SystemInit() function is called, in "startup_stm32l1xx_md.s" file, to\r
- * configure the system clock before to branch to main program. \r
- * \r
- * 3. If the system clock source selected by user fails to startup, the SystemInit()\r
- * function will do nothing and MSI still used as system clock source. User can \r
- * add some code to deal with this issue inside the SetSysClock() function. \r
- * \r
- * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define\r
- * in "stm32l1xx.h" file. When HSE is used as system clock source, directly or\r
- * through PLL, and you are using different crystal you have to adapt the HSE\r
- * value to your own configuration.\r
- * \r
- * 5. This file configures the system clock as follows: \r
- *=============================================================================\r
- * System Clock Configuration\r
- *=============================================================================\r
- * System clock source | HSI\r
- *----------------------------------------------------------------------------- \r
- * SYSCLK | 16000000 Hz\r
- *----------------------------------------------------------------------------- \r
- * HCLK | 16000000 Hz\r
- *----------------------------------------------------------------------------- \r
- * AHB Prescaler | 1\r
- *----------------------------------------------------------------------------- \r
- * APB1 Prescaler | 1\r
- *----------------------------------------------------------------------------- \r
- * APB2 Prescaler | 1\r
- *----------------------------------------------------------------------------- \r
- * HSE Frequency | 8000000 Hz\r
- *----------------------------------------------------------------------------- \r
- * PLL DIV | Not Used\r
- *----------------------------------------------------------------------------- \r
- * PLL MUL | Not Used\r
- *----------------------------------------------------------------------------- \r
- * VDD | 3.3 V\r
- *----------------------------------------------------------------------------- \r
- * Vcore | 1.8 V (Range 1)\r
- *----------------------------------------------------------------------------- \r
- * Flash Latency | 0 WS\r
- *----------------------------------------------------------------------------- \r
- * Require 48MHz for USB clock | Disabled\r
- *----------------------------------------------------------------------------- \r
- *=============================================================================\r
- ****************************************************************************** \r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */\r
-\r
-/** @addtogroup CMSIS\r
- * @{\r
- */\r
-\r
-/** @addtogroup stm32l1xx_system\r
- * @{\r
- */ \r
- \r
-/** @addtogroup STM32L1xx_System_Private_Includes\r
- * @{\r
- */\r
-\r
-#include "stm32l1xx.h"\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32L1xx_System_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32L1xx_System_Private_Defines\r
- * @{\r
- */\r
-/*!< Uncomment the following line if you need to relocate your vector Table in\r
- Internal SRAM. */ \r
-/* #define VECT_TAB_SRAM */\r
-#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. \r
- This value must be a multiple of 0x200. */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32L1xx_System_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32L1xx_System_Private_Variables\r
- * @{\r
- */\r
-uint32_t SystemCoreClock = 16000000;\r
-__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};\r
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-static void SetSysClock(void);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32L1xx_System_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Setup the microcontroller system.\r
- * Initialize the Embedded Flash Interface, the PLL and update the \r
- * SystemCoreClock variable.\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemInit (void)\r
-{\r
- /*!< Set MSION bit */\r
- RCC->CR |= (uint32_t)0x00000100;\r
-\r
- /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */\r
- RCC->CFGR &= (uint32_t)0x88FFC00C;\r
- \r
- /*!< Reset HSION, HSEON, CSSON and PLLON bits */\r
- RCC->CR &= (uint32_t)0xEEFEFFFE;\r
-\r
- /*!< Reset HSEBYP bit */\r
- RCC->CR &= (uint32_t)0xFFFBFFFF;\r
-\r
- /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */\r
- RCC->CFGR &= (uint32_t)0xFF02FFFF;\r
-\r
- /*!< Disable all interrupts */\r
- RCC->CIR = 0x00000000;\r
- \r
- /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */\r
- SetSysClock();\r
-\r
-#ifdef VECT_TAB_SRAM\r
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */\r
-#else\r
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */\r
-#endif\r
-}\r
-\r
-/**\r
- * @brief Update SystemCoreClock according to Clock Register Values\r
- * @note - The system frequency computed by this function is not the real \r
- * frequency in the chip. It is calculated based on the predefined \r
- * constant and the selected clock source:\r
- * \r
- * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI \r
- * value as defined by the MSI range.\r
- * \r
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r
- * \r
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r
- * \r
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \r
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
- * \r
- * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value\r
- * 16 MHz) but the real value may vary depending on the variations\r
- * in voltage and temperature. \r
- * \r
- * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value\r
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real\r
- * frequency of the crystal used. Otherwise, this function may\r
- * have wrong result.\r
- * \r
- * - The result of this function could be not correct when using fractional\r
- * value for HSE crystal. \r
- * @param None\r
- * @retval None\r
- */\r
-void SystemCoreClockUpdate (void)\r
-{\r
- uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;\r
-\r
- /* Get SYSCLK source -------------------------------------------------------*/\r
- tmp = RCC->CFGR & RCC_CFGR_SWS;\r
- \r
- switch (tmp)\r
- {\r
- case 0x00: /* MSI used as system clock */\r
- msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;\r
- SystemCoreClock = (32768 * (1 << (msirange + 1)));\r
- break;\r
- case 0x04: /* HSI used as system clock */\r
- SystemCoreClock = HSI_VALUE;\r
- break;\r
- case 0x08: /* HSE used as system clock */\r
- SystemCoreClock = HSE_VALUE;\r
- break;\r
- case 0x0C: /* PLL used as system clock */\r
- /* Get PLL clock source and multiplication factor ----------------------*/\r
- pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;\r
- plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;\r
- pllmul = PLLMulTable[(pllmul >> 18)];\r
- plldiv = (plldiv >> 22) + 1;\r
- \r
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
-\r
- if (pllsource == 0x00)\r
- {\r
- /* HSI oscillator clock selected as PLL clock entry */\r
- SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);\r
- }\r
- else\r
- {\r
- /* HSE selected as PLL clock entry */\r
- SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);\r
- }\r
- break;\r
- default: /* MSI used as system clock */\r
- msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;\r
- SystemCoreClock = (32768 * (1 << (msirange + 1)));\r
- break;\r
- }\r
- /* Compute HCLK clock frequency --------------------------------------------*/\r
- /* Get HCLK prescaler */\r
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
- /* HCLK clock frequency */\r
- SystemCoreClock >>= tmp;\r
-}\r
-\r
-/**\r
- * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash \r
- * settings.\r
- * @note This function should be called only once the RCC clock configuration \r
- * is reset to the default reset state (done in SystemInit() function). \r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClock(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
- /* Enable HSI */\r
- RCC->CR |= ((uint32_t)RCC_CR_HSION);\r
- \r
- /* Wait till HSI is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSIStatus = RCC->CR & RCC_CR_HSIRDY;\r
- } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));\r
-\r
- if ((RCC->CR & RCC_CR_HSIRDY) != RESET)\r
- {\r
- HSIStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSIStatus = (uint32_t)0x00;\r
- }\r
- \r
- if (HSIStatus == (uint32_t)0x01)\r
- {\r
- /* Flash 0 wait state */\r
- FLASH->ACR &= ~FLASH_ACR_LATENCY;\r
- \r
- /* Disable Prefetch Buffer */\r
- FLASH->ACR &= ~FLASH_ACR_PRFTEN;\r
-\r
- /* Disable 64-bit access */\r
- FLASH->ACR &= ~FLASH_ACR_ACC64;\r
- \r
-\r
- /* Power enable */\r
- RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
- \r
- /* Select the Voltage Range 1 (1.8 V) */\r
- PWR->CR = PWR_CR_VOS_0;\r
- \r
- \r
- /* Wait Until the Voltage Regulator is ready */\r
- while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
- {\r
- }\r
- \r
- /* HCLK = SYSCLK /1*/\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- /* PCLK2 = HCLK /1*/\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK /1*/\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
- \r
- /* Select HSI as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;\r
-\r
- /* Wait till HSI is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSI)\r
- {\r
- }\r
- }\r
- else\r
- {\r
- /* If HSI fails to start-up, the application will have wrong clock\r
- configuration. User can add here some code to deal with this error */\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-This directory contains the StdPeriph libraries from ST, and the CMSIS core and device
-support, all from ST.
-
-Issues:
-* No tracking of which version of which library (yet)
-* Both of these define assert_param() as empty. That may not be what you
- want!
-
-
+++ /dev/null
-
-all:
- make -f Makefile.f10x
- make -f Makefile.l1xx
-
-clean:
- make -f Makefile.f10x clean
- make -f Makefile.l1xx clean
-
-.PHONY: all clean
+++ /dev/null
-CC = arm-none-eabi-gcc
-AR = arm-none-eabi-ar
-RANLIB = arm-none-eabi-ranlib
-
-
-INC_CORE_SUPPORT=../inc/core_support
-SRC_CORE_SUPPORT=../inc/core_support
-INC_DEVICE_SUPPORT=../inc/device_support
-INC_PLATFORM=../inc/$(PLATFORM)
-SRC_PLATFORM=../src/$(PLATFORM)
-
-CFLAGS += -Wall -O2 -mlittle-endian -mthumb
-CFLAGS += -mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc
-CFLAGS += -I$(INC_PLATFORM) -I$(INC_DEVICE_SUPPORT) -I$(INC_CORE_SUPPORT) -I../inc/base
-
-SRCS=$(wildcard $(SRC_PLATFORM)/*.c)
-SRCS+=$(SRC_CORE_SUPPORT)/core_cm3.c
-
-OBJS = $(SRCS:.c=.o)
-
-all: $(LIB)
-
-$(LIB): $(OBJS)
- $(AR) -r $(LIB) $(OBJS)
- $(RANLIB) $(LIB)
-
-%.o : %.c
- $(CC) $(CFLAGS) -c -o $@ $^
-
-clean:
- -rm -f $(OBJS)
- -rm -f $(LIB)
-
-.PHONY: all clean
+++ /dev/null
-LIB = libstm32_stdperiph_f10x.a
-PLATFORM=stm32f10x
-CFLAGS+= -mcpu=cortex-m3
-
-include Makefile.common
+++ /dev/null
-LIB = libstm32_stdperiph_l1xx.a
-PLATFORM=stm32l1xx
-CFLAGS+=-mcpu=cortex-m3
-
-include Makefile.common
+++ /dev/null
-#ifndef STDINT_H_INCLUDED
-# define STDINT_H_INCLUDED
-
-
-typedef char int8_t;
-typedef short int16_t;
-typedef int int32_t;
-typedef long long int64_t;
-
-typedef unsigned char uint8_t;
-typedef unsigned short uint16_t;
-typedef unsigned int uint32_t;
-typedef unsigned long long uint64_t;
-
-
-#endif /* ! STDINT_H_INCLUDED */
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm3.c\r
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File\r
- * @version V1.30\r
- * @date 30. October 2009\r
- *\r
- * @note\r
- * Copyright (C) 2009 ARM Limited. All rights reserved.\r
- *\r
- * @par\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
- * processor based microcontrollers. This file can be freely distributed \r
- * within development tools that are supporting such ARM based processors. \r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-#include <stdint.h>\r
-\r
-/* define compiler specific symbols */\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
-\r
-#endif\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-__ASM uint32_t __get_PSP(void)\r
-{\r
- mrs r0, psp\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-__ASM void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- msr psp, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-__ASM uint32_t __get_MSP(void)\r
-{\r
- mrs r0, msp\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-__ASM void __set_MSP(uint32_t mainStackPointer)\r
-{\r
- msr msp, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-__ASM uint32_t __REV16(uint16_t value)\r
-{\r
- rev16 r0, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-__ASM int32_t __REVSH(int16_t value)\r
-{\r
- revsh r0, r0\r
- bx lr\r
-}\r
-\r
-\r
-#if (__ARMCC_VERSION < 400000)\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-__ASM void __CLREX(void)\r
-{\r
- clrex\r
-}\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-__ASM uint32_t __get_BASEPRI(void)\r
-{\r
- mrs r0, basepri\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-__ASM void __set_BASEPRI(uint32_t basePri)\r
-{\r
- msr basepri, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-__ASM uint32_t __get_PRIMASK(void)\r
-{\r
- mrs r0, primask\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-__ASM void __set_PRIMASK(uint32_t priMask)\r
-{\r
- msr primask, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-__ASM uint32_t __get_FAULTMASK(void)\r
-{\r
- mrs r0, faultmask\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-__ASM void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- msr faultmask, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-__ASM uint32_t __get_CONTROL(void)\r
-{\r
- mrs r0, control\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-__ASM void __set_CONTROL(uint32_t control)\r
-{\r
- msr control, r0\r
- bx lr\r
-}\r
-\r
-#endif /* __ARMCC_VERSION */ \r
-\r
-\r
-\r
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-#pragma diag_suppress=Pe940\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-uint32_t __get_PSP(void)\r
-{\r
- __ASM("mrs r0, psp");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- __ASM("msr psp, r0");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-uint32_t __get_MSP(void)\r
-{\r
- __ASM("mrs r0, msp");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- __ASM("msr msp, r0");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-uint32_t __REV16(uint16_t value)\r
-{\r
- __ASM("rev16 r0, r0");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-uint32_t __RBIT(uint32_t value)\r
-{\r
- __ASM("rbit r0, r0");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive (8 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 8 bit values)\r
- */\r
-uint8_t __LDREXB(uint8_t *addr)\r
-{\r
- __ASM("ldrexb r0, [r0]");\r
- __ASM("bx lr"); \r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive (16 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 16 bit values\r
- */\r
-uint16_t __LDREXH(uint16_t *addr)\r
-{\r
- __ASM("ldrexh r0, [r0]");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive (32 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 32 bit values\r
- */\r
-uint32_t __LDREXW(uint32_t *addr)\r
-{\r
- __ASM("ldrex r0, [r0]");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive (8 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 8 bit values\r
- */\r
-uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
-{\r
- __ASM("strexb r0, r0, [r1]");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive (16 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 16 bit values\r
- */\r
-uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
-{\r
- __ASM("strexh r0, r0, [r1]");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive (32 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 32 bit values\r
- */\r
-uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
-{\r
- __ASM("strex r0, r0, [r1]");\r
- __ASM("bx lr");\r
-}\r
-\r
-#pragma diag_default=Pe940\r
-\r
-\r
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-uint32_t __get_PSP(void) __attribute__( ( naked ) );\r
-uint32_t __get_PSP(void)\r
-{\r
- uint32_t result=0;\r
-\r
- __ASM volatile ("MRS %0, psp\n\t" \r
- "MOV r0, %0 \n\t"\r
- "BX lr \n\t" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );\r
-void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- __ASM volatile ("MSR psp, %0\n\t"\r
- "BX lr \n\t" : : "r" (topOfProcStack) );\r
-}\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-uint32_t __get_MSP(void) __attribute__( ( naked ) );\r
-uint32_t __get_MSP(void)\r
-{\r
- uint32_t result=0;\r
-\r
- __ASM volatile ("MRS %0, msp\n\t" \r
- "MOV r0, %0 \n\t"\r
- "BX lr \n\t" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );\r
-void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- __ASM volatile ("MSR msp, %0\n\t"\r
- "BX lr \n\t" : : "r" (topOfMainStack) );\r
-}\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-uint32_t __get_BASEPRI(void)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-void __set_BASEPRI(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
-}\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-uint32_t __get_PRIMASK(void)\r
-{\r
- uint32_t result=0;\r
-\r
- __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-void __set_PRIMASK(uint32_t priMask)\r
-{\r
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
-}\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-uint32_t __get_FAULTMASK(void)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
-}\r
-\r
-/**\r
- * @brief Return the Control Register value\r
-* \r
-* @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-uint32_t __get_CONTROL(void)\r
-{\r
- uint32_t result=0;\r
-\r
- __ASM volatile ("MRS %0, control" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-void __set_CONTROL(uint32_t control)\r
-{\r
- __ASM volatile ("MSR control, %0" : : "r" (control) );\r
-}\r
-\r
-\r
-/**\r
- * @brief Reverse byte order in integer value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in integer value\r
- */\r
-uint32_t __REV(uint32_t value)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-uint32_t __REV16(uint16_t value)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-int32_t __REVSH(int16_t value)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-uint32_t __RBIT(uint32_t value)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive (8 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 8 bit value\r
- */\r
-uint8_t __LDREXB(uint8_t *addr)\r
-{\r
- uint8_t result=0;\r
- \r
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive (16 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 16 bit values\r
- */\r
-uint16_t __LDREXH(uint16_t *addr)\r
-{\r
- uint16_t result=0;\r
- \r
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive (32 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 32 bit values\r
- */\r
-uint32_t __LDREXW(uint32_t *addr)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive (8 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 8 bit values\r
- */\r
-uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive (16 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 16 bit values\r
- */\r
-uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive (32 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 32 bit values\r
- */\r
-uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm3.h\r
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
- * @version V1.30\r
- * @date 30. October 2009\r
- *\r
- * @note\r
- * Copyright (C) 2009 ARM Limited. All rights reserved.\r
- *\r
- * @par\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
- * processor based microcontrollers. This file can be freely distributed \r
- * within development tools that are supporting such ARM based processors. \r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-#ifndef __CM3_CORE_H__\r
-#define __CM3_CORE_H__\r
-\r
-/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration\r
- *\r
- * List of Lint messages which will be suppressed and not shown:\r
- * - Error 10: \n\r
- * register uint32_t __regBasePri __asm("basepri"); \n\r
- * Error 10: Expecting ';'\r
- * .\r
- * - Error 530: \n\r
- * return(__regBasePri); \n\r
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized\r
- * . \r
- * - Error 550: \n\r
- * __regBasePri = (basePri & 0x1ff); \n\r
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed\r
- * .\r
- * - Error 754: \n\r
- * uint32_t RESERVED0[24]; \n\r
- * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced\r
- * .\r
- * - Error 750: \n\r
- * #define __CM3_CORE_H__ \n\r
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced\r
- * .\r
- * - Error 528: \n\r
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced\r
- * .\r
- * - Error 751: \n\r
- * } InterruptType_Type; \n\r
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced\r
- * .\r
- * Note: To re-enable a Message, insert a space before 'lint' *\r
- *\r
- */\r
-\r
-/*lint -save */\r
-/*lint -e10 */\r
-/*lint -e530 */\r
-/*lint -e550 */\r
-/*lint -e754 */\r
-/*lint -e750 */\r
-/*lint -e528 */\r
-/*lint -e751 */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions\r
- This file defines all structures and symbols for CMSIS core:\r
- - CMSIS version number\r
- - Cortex-M core registers and bitfields\r
- - Cortex-M core peripheral base address\r
- @{\r
- */\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x03) /*!< Cortex core */\r
-\r
-#include <stdint.h> /* Include standard types */\r
-\r
-#if defined (__ICCARM__)\r
- #include <intrinsics.h> /* IAR Intrinsics */\r
-#endif\r
-\r
-\r
-#ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */\r
-#endif\r
-\r
-\r
-\r
-\r
-/**\r
- * IO definitions\r
- *\r
- * define access restrictions to peripheral registers\r
- */\r
-\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< defines 'write only' permissions */\r
-#define __IO volatile /*!< defines 'read / write' permissions */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- ******************************************************************************/\r
-/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register\r
- @{\r
-*/\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC\r
- memory mapped structure for Nested Vectored Interrupt Controller (NVIC)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24]; \r
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24]; \r
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24]; \r
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24]; \r
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */\r
- uint32_t RESERVED4[56]; \r
- __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644]; \r
- __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */\r
-} NVIC_Type; \r
-/*@}*/ /* end of group CMSIS_CM3_NVIC */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB\r
- memory mapped structure for System Control Block (SCB)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */\r
- __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */\r
- __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */\r
- __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */\r
- __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */\r
- __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */\r
- __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */\r
- __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */\r
- __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */\r
- __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */\r
- __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */\r
- __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */\r
- __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */\r
- __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */\r
- __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */\r
- __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */\r
- __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */\r
- __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */\r
-} SCB_Type; \r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
-#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
-\r
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
- \r
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Registers Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* SCB Hard Fault Status Registers Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_SCB */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick\r
- memory mapped structure for SysTick\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */\r
- __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */\r
- __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */\r
- __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_SysTick */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM\r
- memory mapped structure for Instrumentation Trace Macrocell (ITM)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __O union \r
- {\r
- __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */\r
- __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */\r
- __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */\r
- } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864]; \r
- __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */\r
- uint32_t RESERVED1[15]; \r
- __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15]; \r
- __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */\r
- uint32_t RESERVED3[29]; \r
- __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */\r
- __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */\r
- __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43]; \r
- __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */\r
- __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */\r
- uint32_t RESERVED5[6]; \r
- __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */\r
- __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */\r
- __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */\r
- __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */\r
- __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */\r
- __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */\r
- __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */\r
- __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */\r
- __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */\r
- __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */\r
- __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */\r
- __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */\r
-} ITM_Type; \r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_ITM */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type\r
- memory mapped structure for Interrupt Type\r
- @{\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0;\r
- __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */\r
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
- __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */\r
-#else\r
- uint32_t RESERVED1;\r
-#endif\r
-} InterruptType_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */\r
-#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */\r
-\r
-/* Auxiliary Control Register Definitions */\r
-#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */\r
-#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */\r
-\r
-#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */\r
-#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */\r
-\r
-#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */\r
-#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_InterruptType */\r
-\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
-/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU\r
- memory mapped structure for Memory Protection Unit (MPU)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */\r
- __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */\r
- __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */\r
- __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */\r
- __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */\r
- __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */\r
- __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */\r
- __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type; \r
-\r
-/* MPU Type Register */\r
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register */\r
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register */\r
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register */\r
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */\r
-#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */\r
-#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */\r
-#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */\r
-#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */\r
-\r
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */\r
-#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */\r
-\r
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */\r
-#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_MPU */\r
-#endif\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug\r
- memory mapped structure for Core Debug Register\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */\r
- __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */\r
- __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */\r
- __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_CoreDebug */\r
-\r
-\r
-/* Memory mapping of Cortex-M3 Hardware */\r
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
-\r
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_core_register */\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- ******************************************************************************/\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
-\r
-#endif\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#define __enable_fault_irq __enable_fiq\r
-#define __disable_fault_irq __disable_fiq\r
-\r
-#define __NOP __nop\r
-#define __WFI __wfi\r
-#define __WFE __wfe\r
-#define __SEV __sev\r
-#define __ISB() __isb(0)\r
-#define __DSB() __dsb(0)\r
-#define __DMB() __dmb(0)\r
-#define __REV __rev\r
-#define __RBIT __rbit\r
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))\r
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))\r
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))\r
-#define __STREXB(value, ptr) __strex(value, ptr)\r
-#define __STREXH(value, ptr) __strex(value, ptr)\r
-#define __STREXW(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
-/* intrinsic void __enable_irq(); */\r
-/* intrinsic void __disable_irq(); */\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-extern int32_t __REVSH(int16_t value);\r
-\r
-\r
-#if (__ARMCC_VERSION < 400000)\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-extern void __CLREX(void);\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-extern uint32_t __get_BASEPRI(void);\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-extern void __set_BASEPRI(uint32_t basePri);\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-extern uint32_t __get_PRIMASK(void);\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-extern void __set_PRIMASK(uint32_t priMask);\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-extern uint32_t __get_FAULTMASK(void);\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-extern void __set_FAULTMASK(uint32_t faultMask);\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-extern uint32_t __get_CONTROL(void);\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-extern void __set_CONTROL(uint32_t control);\r
-\r
-#else /* (__ARMCC_VERSION >= 400000) */\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-#define __CLREX __clrex\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-static __INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- return(__regBasePri);\r
-}\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-static __INLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- __regBasePri = (basePri & 0xff);\r
-}\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-static __INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- return(__regPriMask);\r
-}\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-static __INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- __regPriMask = (priMask);\r
-}\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-static __INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- return(__regFaultMask);\r
-}\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- __regFaultMask = (faultMask & 1);\r
-}\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-static __INLINE uint32_t __get_CONTROL(void)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- return(__regControl);\r
-}\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-static __INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- __regControl = control;\r
-}\r
-\r
-#endif /* __ARMCC_VERSION */ \r
-\r
-\r
-\r
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
-\r
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
-\r
-#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ \r
-static __INLINE void __WFI() { __ASM ("wfi"); }\r
-static __INLINE void __WFE() { __ASM ("wfe"); }\r
-static __INLINE void __SEV() { __ASM ("sev"); }\r
-static __INLINE void __CLREX() { __ASM ("clrex"); }\r
-\r
-/* intrinsic void __ISB(void) */\r
-/* intrinsic void __DSB(void) */\r
-/* intrinsic void __DMB(void) */\r
-/* intrinsic void __set_PRIMASK(); */\r
-/* intrinsic void __get_PRIMASK(); */\r
-/* intrinsic void __set_FAULTMASK(); */\r
-/* intrinsic void __get_FAULTMASK(); */\r
-/* intrinsic uint32_t __REV(uint32_t value); */\r
-/* intrinsic uint32_t __REVSH(uint32_t value); */\r
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
-/* intrinsic unsigned long __LDREX(unsigned long *); */\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
-\r
-/**\r
- * @brief LDR Exclusive (8 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 8 bit values)\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (16 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 16 bit values\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (32 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 32 bit values\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (8 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 8 bit values\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (16 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 16 bit values\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (32 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 32 bit values\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
-\r
-\r
-\r
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }\r
-static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }\r
-\r
-static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }\r
-\r
-static __INLINE void __NOP() { __ASM volatile ("nop"); }\r
-static __INLINE void __WFI() { __ASM volatile ("wfi"); }\r
-static __INLINE void __WFE() { __ASM volatile ("wfe"); }\r
-static __INLINE void __SEV() { __ASM volatile ("sev"); }\r
-static __INLINE void __ISB() { __ASM volatile ("isb"); }\r
-static __INLINE void __DSB() { __ASM volatile ("dsb"); }\r
-static __INLINE void __DMB() { __ASM volatile ("dmb"); }\r
-static __INLINE void __CLREX() { __ASM volatile ("clrex"); }\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-extern uint32_t __get_BASEPRI(void);\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-extern void __set_BASEPRI(uint32_t basePri);\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-extern uint32_t __get_PRIMASK(void);\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-extern void __set_PRIMASK(uint32_t priMask);\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-extern uint32_t __get_FAULTMASK(void);\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-extern void __set_FAULTMASK(uint32_t faultMask);\r
-\r
-/**\r
- * @brief Return the Control Register value\r
-* \r
-* @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-extern uint32_t __get_CONTROL(void);\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-extern void __set_CONTROL(uint32_t control);\r
-\r
-/**\r
- * @brief Reverse byte order in integer value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in integer value\r
- */\r
-extern uint32_t __REV(uint32_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-extern int32_t __REVSH(int16_t value);\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
-\r
-/**\r
- * @brief LDR Exclusive (8 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 8 bit value\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (16 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 16 bit values\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (32 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 32 bit values\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (8 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 8 bit values\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (16 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 16 bit values\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (32 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 32 bit values\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
-\r
-\r
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface\r
- Core Function Interface containing:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Reset Functions\r
-*/\r
-/*@{*/\r
-\r
-/* ########################## NVIC functions #################################### */\r
-\r
-/**\r
- * @brief Set the Priority Grouping in NVIC Interrupt Controller\r
- *\r
- * @param PriorityGroup is priority grouping field\r
- *\r
- * Set the priority grouping field using the required unlock sequence.\r
- * The parameter priority_grouping is assigned to the field \r
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- */\r
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- \r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
- reg_value = (reg_value |\r
- (0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-/**\r
- * @brief Get the Priority Grouping from NVIC Interrupt Controller\r
- *\r
- * @return priority grouping field \r
- *\r
- * Get the priority grouping from NVIC Interrupt Controller.\r
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
- */\r
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
-}\r
-\r
-/**\r
- * @brief Enable Interrupt in NVIC Interrupt Controller\r
- *\r
- * @param IRQn The positive number of the external interrupt to enable\r
- *\r
- * Enable a device specific interupt in the NVIC interrupt controller.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
-}\r
-\r
-/**\r
- * @brief Disable the interrupt line for external interrupt specified\r
- * \r
- * @param IRQn The positive number of the external interrupt to disable\r
- * \r
- * Disable a device specific interupt in the NVIC interrupt controller.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
-}\r
-\r
-/**\r
- * @brief Read the interrupt pending bit for a device specific interrupt source\r
- * \r
- * @param IRQn The number of the device specifc interrupt\r
- * @return 1 = interrupt pending, 0 = interrupt not pending\r
- *\r
- * Read the pending register in NVIC and return 1 if its status is pending, \r
- * otherwise it returns 0\r
- */\r
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
-}\r
-\r
-/**\r
- * @brief Set the pending bit for an external interrupt\r
- * \r
- * @param IRQn The number of the interrupt for set pending\r
- *\r
- * Set the pending bit for the specified interrupt.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
-}\r
-\r
-/**\r
- * @brief Clear the pending bit for an external interrupt\r
- *\r
- * @param IRQn The number of the interrupt for clear pending\r
- *\r
- * Clear the pending bit for the specified interrupt. \r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
-}\r
-\r
-/**\r
- * @brief Read the active bit for an external interrupt\r
- *\r
- * @param IRQn The number of the interrupt for read active bit\r
- * @return 1 = interrupt active, 0 = interrupt not active\r
- *\r
- * Read the active register in NVIC and returns 1 if its status is active, \r
- * otherwise it returns 0.\r
- */\r
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
-}\r
-\r
-/**\r
- * @brief Set the priority for an interrupt\r
- *\r
- * @param IRQn The number of the interrupt for set priority\r
- * @param priority The priority to set\r
- *\r
- * Set the priority for the specified interrupt. The interrupt \r
- * number can be positive to specify an external (device specific) \r
- * interrupt, or negative to specify an internal (core) interrupt.\r
- *\r
- * Note: The priority cannot be set for every core interrupt.\r
- */\r
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if(IRQn < 0) {\r
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
- else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
-}\r
-\r
-/**\r
- * @brief Read the priority for an interrupt\r
- *\r
- * @param IRQn The number of the interrupt for get priority\r
- * @return The priority for the interrupt\r
- *\r
- * Read the priority for the specified interrupt. The interrupt \r
- * number can be positive to specify an external (device specific) \r
- * interrupt, or negative to specify an internal (core) interrupt.\r
- *\r
- * The returned priority value is automatically aligned to the implemented\r
- * priority bits of the microcontroller.\r
- *\r
- * Note: The priority cannot be set for every core interrupt.\r
- */\r
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if(IRQn < 0) {\r
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */\r
- else {\r
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
-}\r
-\r
-\r
-/**\r
- * @brief Encode the priority for an interrupt\r
- *\r
- * @param PriorityGroup The used priority group\r
- * @param PreemptPriority The preemptive priority value (starting from 0)\r
- * @param SubPriority The sub priority value (starting from 0)\r
- * @return The encoded priority for the interrupt\r
- *\r
- * Encode the priority for an interrupt with the given priority group,\r
- * preemptive priority value and sub priority value.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
- *\r
- * The returned priority value can be used for NVIC_SetPriority(...) function\r
- */\r
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
- \r
- return (\r
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
- );\r
-}\r
-\r
-\r
-/**\r
- * @brief Decode the priority of an interrupt\r
- *\r
- * @param Priority The priority for the interrupt\r
- * @param PriorityGroup The used priority group\r
- * @param pPreemptPriority The preemptive priority value (starting from 0)\r
- * @param pSubPriority The sub priority value (starting from 0)\r
- *\r
- * Decode an interrupt priority value with the given priority group to \r
- * preemptive priority value and sub priority value.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
- *\r
- * The priority value can be retrieved with NVIC_GetPriority(...) function\r
- */\r
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
- \r
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
-}\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-\r
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
-\r
-/**\r
- * @brief Initialize and start the SysTick counter and its interrupt.\r
- *\r
- * @param ticks number of ticks between two interrupts\r
- * @return 1 = failed, 0 = successful\r
- *\r
- * Initialise the system tick timer and its interrupt and start the\r
- * system tick timer / counter in free running mode to generate \r
- * periodical interrupts.\r
- */\r
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{ \r
- if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
- \r
- SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | \r
- SysTick_CTRL_TICKINT_Msk | \r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-\r
-\r
-\r
-/* ################################## Reset function ############################################ */\r
-\r
-/**\r
- * @brief Initiate a system reset request.\r
- *\r
- * Initiate a system reset request to reset the MCU\r
- */\r
-static __INLINE void NVIC_SystemReset(void)\r
-{\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | \r
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */ \r
- while(1); /* wait until reset */\r
-}\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-\r
-/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface\r
- Core Debug Interface containing:\r
- - Core Debug Receive / Transmit Functions\r
- - Core Debug Defines\r
- - Core Debug Variables\r
-*/\r
-/*@{*/\r
-\r
-extern volatile int ITM_RxBuffer; /*!< variable to receive characters */\r
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
-\r
-\r
-/**\r
- * @brief Outputs a character via the ITM channel 0\r
- *\r
- * @param ch character to output\r
- * @return character to output\r
- *\r
- * The function outputs a character via the ITM channel 0. \r
- * The function returns when no debugger is connected that has booked the output. \r
- * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
- */\r
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
- (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */\r
- {\r
- while (ITM->PORT[0].u32 == 0);\r
- ITM->PORT[0].u8 = (uint8_t) ch;\r
- } \r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- * @brief Inputs a character via variable ITM_RxBuffer\r
- *\r
- * @return received character, -1 = no character received\r
- *\r
- * The function inputs a character via variable ITM_RxBuffer. \r
- * The function returns when no debugger is connected that has booked the output. \r
- * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
- */\r
-static __INLINE int ITM_ReceiveChar (void) {\r
- int ch = -1; /* no character available */\r
-\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
- ch = ITM_RxBuffer;\r
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
- }\r
- \r
- return (ch); \r
-}\r
-\r
-\r
-/**\r
- * @brief Check if a character via variable ITM_RxBuffer is available\r
- *\r
- * @return 1 = character available, 0 = no character available\r
- *\r
- * The function checks variable ITM_RxBuffer whether a character is available or not. \r
- * The function returns '1' if a character is available and '0' if no character is available. \r
- */\r
-static __INLINE int ITM_CheckChar (void) {\r
-\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
- return (0); /* no character available */\r
- } else {\r
- return (1); /* character available */\r
- }\r
-}\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_core_definitions */\r
-\r
-#endif /* __CM3_CORE_H__ */\r
-\r
-/*lint -restore */\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. \r
- * This file contains all the peripheral register's definitions, bits \r
- * definitions and memory mapping for STM32F10x Connectivity line, High\r
- * density, Medium density, Medium density Value line, Low density \r
- * and Low density Value line and XL-density devices.\r
- ****************************************************************************** \r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ******************************************************************************\r
- */\r
-\r
-/** @addtogroup CMSIS\r
- * @{\r
- */\r
-\r
-/** @addtogroup stm32f10x\r
- * @{\r
- */\r
- \r
-#ifndef __STM32F10x_H\r
-#define __STM32F10x_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-#define assert_param(__p)\r
-\r
- \r
-/** @addtogroup Library_configuration_section\r
- * @{\r
- */\r
- \r
-/* Uncomment the line below according to the target STM32 device used in your\r
- application \r
- */\r
-\r
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) \r
- /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */\r
- /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ \r
- /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */\r
- /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ \r
- /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */\r
- #define STM32F10X_XL /*!< STM32F10X_XL: STM32 XL-density devices */\r
- /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */\r
-#endif\r
-/* Tip: To avoid modifying this file each time you need to switch between these\r
- devices, you can define the device in your toolchain compiler preprocessor.\r
-\r
- - Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers\r
- where the Flash memory density ranges between 16 and 32 Kbytes.\r
- - Low-density value line devices are STM32F100xx microcontrollers where the Flash\r
- memory density ranges between 16 and 32 Kbytes.\r
- - Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers\r
- where the Flash memory density ranges between 64 and 128 Kbytes.\r
- - Medium-density value line devices are STM32F100xx microcontrollers where the \r
- Flash memory density ranges between 64 and 128 Kbytes. \r
- - High density devices are STM32F101xx and STM32F103xx microcontrollers where\r
- the Flash memory density ranges between 256 and 512 Kbytes.\r
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where\r
- the Flash memory density ranges between 512 and 1024 Kbytes.\r
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\r
- */\r
-\r
-#if !defined USE_STDPERIPH_DRIVER\r
-/**\r
- * @brief Comment the line below if you will not use the peripherals drivers.\r
- In this case, these drivers will not be included and the application code will \r
- be based on direct access to peripherals registers \r
- */\r
- /*#define USE_STDPERIPH_DRIVER*/\r
-#endif\r
-\r
-/**\r
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)\r
- used in your application \r
- \r
- Tip: To avoid modifying this file each time you need to use different HSE, you\r
- can define the HSE value in your toolchain compiler preprocessor.\r
- */ \r
-#if !defined HSE_VALUE\r
- #ifdef STM32F10X_CL \r
- #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\r
- #else \r
- #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */\r
- #endif /* STM32F10X_CL */\r
-#endif /* HSE_VALUE */\r
-\r
-\r
-/**\r
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup \r
- Timeout value \r
- */\r
-#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */\r
-\r
-#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/\r
-\r
-/**\r
- * @brief STM32F10x Standard Peripheral Library version number\r
- */\r
-#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */\r
-#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x03) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */\r
-#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */\r
-#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\\r
- | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\\r
- | __STM32F10X_STDPERIPH_VERSION_SUB2)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup Configuration_section_for_CMSIS\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configuration of the Cortex-M3 Processor and Core Peripherals \r
- */\r
-#ifdef STM32F10X_XL\r
- #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */\r
-#else\r
- #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */\r
-#endif /* STM32F10X_XL */\r
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */\r
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
-\r
-/**\r
- * @brief STM32F10x Interrupt Number Definition, according to the selected device \r
- * in @ref Library_configuration_section \r
- */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** STM32 specific Interrupt Numbers *********************************************************/\r
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
- PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r
- TAMPER_IRQn = 2, /*!< Tamper Interrupt */\r
- RTC_IRQn = 3, /*!< RTC global Interrupt */\r
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
- RCC_IRQn = 5, /*!< RCC global Interrupt */\r
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
- DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */\r
- DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */\r
- DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */\r
- DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */\r
- DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */\r
- DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */\r
- DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */\r
-\r
-#ifdef STM32F10X_LD\r
- ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
- USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
- USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\r
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\r
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\r
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
- USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
- USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
- RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
- USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ \r
-#endif /* STM32F10X_LD */ \r
-\r
-#ifdef STM32F10X_LD_VL\r
- ADC1_IRQn = 18, /*!< ADC1 global Interrupt */\r
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
- TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */\r
- TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */\r
- TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */\r
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
- USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
- USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
- RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
- CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */\r
- TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */\r
- TIM7_IRQn = 55 /*!< TIM7 Interrupt */ \r
-#endif /* STM32F10X_LD_VL */\r
-\r
-#ifdef STM32F10X_MD\r
- ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
- USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
- USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\r
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\r
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\r
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
- USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
- USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
- USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
- RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
- USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ \r
-#endif /* STM32F10X_MD */ \r
-\r
-#ifdef STM32F10X_MD_VL\r
- ADC1_IRQn = 18, /*!< ADC1 global Interrupt */\r
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
- TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */\r
- TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */\r
- TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */\r
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
- USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
- USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
- USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
- RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
- CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */\r
- TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */\r
- TIM7_IRQn = 55 /*!< TIM7 Interrupt */ \r
-#endif /* STM32F10X_MD_VL */\r
-\r
-#ifdef STM32F10X_HD\r
- ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
- USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
- USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\r
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\r
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\r
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
- USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
- USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
- USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
- RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
- USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */\r
- TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */\r
- TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */\r
- TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */\r
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\r
- ADC3_IRQn = 47, /*!< ADC3 global Interrupt */\r
- FSMC_IRQn = 48, /*!< FSMC global Interrupt */\r
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */\r
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
- UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
- UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
- TIM6_IRQn = 54, /*!< TIM6 global Interrupt */\r
- TIM7_IRQn = 55, /*!< TIM7 global Interrupt */\r
- DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */\r
- DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */\r
- DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */\r
- DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */\r
-#endif /* STM32F10X_HD */ \r
-\r
-#ifdef STM32F10X_XL\r
- ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
- USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
- USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */\r
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */\r
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\r
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
- USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
- USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
- USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
- RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
- USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */\r
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */\r
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */\r
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\r
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\r
- ADC3_IRQn = 47, /*!< ADC3 global Interrupt */\r
- FSMC_IRQn = 48, /*!< FSMC global Interrupt */\r
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */\r
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
- UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
- UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
- TIM6_IRQn = 54, /*!< TIM6 global Interrupt */\r
- TIM7_IRQn = 55, /*!< TIM7 global Interrupt */\r
- DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */\r
- DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */\r
- DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */\r
- DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */\r
-#endif /* STM32F10X_XL */ \r
-\r
-#ifdef STM32F10X_CL\r
- ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
- CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
- CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\r
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\r
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\r
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
- USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
- USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
- USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
- RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */\r
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
- UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
- UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
- TIM6_IRQn = 54, /*!< TIM6 global Interrupt */\r
- TIM7_IRQn = 55, /*!< TIM7 global Interrupt */\r
- DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */\r
- DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */\r
- DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */\r
- DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */\r
- DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */\r
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */\r
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */\r
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */\r
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */\r
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */\r
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */\r
- OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */\r
-#endif /* STM32F10X_CL */ \r
-} IRQn_Type;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#include "core_cm3.h"\r
-#include "system_stm32f10x.h"\r
-#include <stdint.h>\r
-\r
-/** @addtogroup Exported_types\r
- * @{\r
- */ \r
-\r
-/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */\r
-typedef int32_t s32;\r
-typedef int16_t s16;\r
-typedef int8_t s8;\r
-\r
-typedef const int32_t sc32; /*!< Read Only */\r
-typedef const int16_t sc16; /*!< Read Only */\r
-typedef const int8_t sc8; /*!< Read Only */\r
-\r
-typedef __IO int32_t vs32;\r
-typedef __IO int16_t vs16;\r
-typedef __IO int8_t vs8;\r
-\r
-typedef __I int32_t vsc32; /*!< Read Only */\r
-typedef __I int16_t vsc16; /*!< Read Only */\r
-typedef __I int8_t vsc8; /*!< Read Only */\r
-\r
-typedef uint32_t u32;\r
-typedef uint16_t u16;\r
-typedef uint8_t u8;\r
-\r
-typedef const uint32_t uc32; /*!< Read Only */\r
-typedef const uint16_t uc16; /*!< Read Only */\r
-typedef const uint8_t uc8; /*!< Read Only */\r
-\r
-typedef __IO uint32_t vu32;\r
-typedef __IO uint16_t vu16;\r
-typedef __IO uint8_t vu8;\r
-\r
-typedef __I uint32_t vuc32; /*!< Read Only */\r
-typedef __I uint16_t vuc16; /*!< Read Only */\r
-typedef __I uint8_t vuc8; /*!< Read Only */\r
-\r
-#ifndef __cplusplus\r
-typedef enum {FALSE = 0, TRUE = !FALSE} bool;\r
-#endif\r
-\r
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\r
-\r
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
-\r
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
-\r
-/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */\r
-#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT\r
-#define HSE_Value HSE_VALUE\r
-#define HSI_Value HSI_VALUE\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup Peripheral_registers_structures\r
- * @{\r
- */ \r
-\r
-/** \r
- * @brief Analog to Digital Converter \r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t SR;\r
- __IO uint32_t CR1;\r
- __IO uint32_t CR2;\r
- __IO uint32_t SMPR1;\r
- __IO uint32_t SMPR2;\r
- __IO uint32_t JOFR1;\r
- __IO uint32_t JOFR2;\r
- __IO uint32_t JOFR3;\r
- __IO uint32_t JOFR4;\r
- __IO uint32_t HTR;\r
- __IO uint32_t LTR;\r
- __IO uint32_t SQR1;\r
- __IO uint32_t SQR2;\r
- __IO uint32_t SQR3;\r
- __IO uint32_t JSQR;\r
- __IO uint32_t JDR1;\r
- __IO uint32_t JDR2;\r
- __IO uint32_t JDR3;\r
- __IO uint32_t JDR4;\r
- __IO uint32_t DR;\r
-} ADC_TypeDef;\r
-\r
-/** \r
- * @brief Backup Registers \r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t RESERVED0;\r
- __IO uint16_t DR1;\r
- uint16_t RESERVED1;\r
- __IO uint16_t DR2;\r
- uint16_t RESERVED2;\r
- __IO uint16_t DR3;\r
- uint16_t RESERVED3;\r
- __IO uint16_t DR4;\r
- uint16_t RESERVED4;\r
- __IO uint16_t DR5;\r
- uint16_t RESERVED5;\r
- __IO uint16_t DR6;\r
- uint16_t RESERVED6;\r
- __IO uint16_t DR7;\r
- uint16_t RESERVED7;\r
- __IO uint16_t DR8;\r
- uint16_t RESERVED8;\r
- __IO uint16_t DR9;\r
- uint16_t RESERVED9;\r
- __IO uint16_t DR10;\r
- uint16_t RESERVED10; \r
- __IO uint16_t RTCCR;\r
- uint16_t RESERVED11;\r
- __IO uint16_t CR;\r
- uint16_t RESERVED12;\r
- __IO uint16_t CSR;\r
- uint16_t RESERVED13[5];\r
- __IO uint16_t DR11;\r
- uint16_t RESERVED14;\r
- __IO uint16_t DR12;\r
- uint16_t RESERVED15;\r
- __IO uint16_t DR13;\r
- uint16_t RESERVED16;\r
- __IO uint16_t DR14;\r
- uint16_t RESERVED17;\r
- __IO uint16_t DR15;\r
- uint16_t RESERVED18;\r
- __IO uint16_t DR16;\r
- uint16_t RESERVED19;\r
- __IO uint16_t DR17;\r
- uint16_t RESERVED20;\r
- __IO uint16_t DR18;\r
- uint16_t RESERVED21;\r
- __IO uint16_t DR19;\r
- uint16_t RESERVED22;\r
- __IO uint16_t DR20;\r
- uint16_t RESERVED23;\r
- __IO uint16_t DR21;\r
- uint16_t RESERVED24;\r
- __IO uint16_t DR22;\r
- uint16_t RESERVED25;\r
- __IO uint16_t DR23;\r
- uint16_t RESERVED26;\r
- __IO uint16_t DR24;\r
- uint16_t RESERVED27;\r
- __IO uint16_t DR25;\r
- uint16_t RESERVED28;\r
- __IO uint16_t DR26;\r
- uint16_t RESERVED29;\r
- __IO uint16_t DR27;\r
- uint16_t RESERVED30;\r
- __IO uint16_t DR28;\r
- uint16_t RESERVED31;\r
- __IO uint16_t DR29;\r
- uint16_t RESERVED32;\r
- __IO uint16_t DR30;\r
- uint16_t RESERVED33; \r
- __IO uint16_t DR31;\r
- uint16_t RESERVED34;\r
- __IO uint16_t DR32;\r
- uint16_t RESERVED35;\r
- __IO uint16_t DR33;\r
- uint16_t RESERVED36;\r
- __IO uint16_t DR34;\r
- uint16_t RESERVED37;\r
- __IO uint16_t DR35;\r
- uint16_t RESERVED38;\r
- __IO uint16_t DR36;\r
- uint16_t RESERVED39;\r
- __IO uint16_t DR37;\r
- uint16_t RESERVED40;\r
- __IO uint16_t DR38;\r
- uint16_t RESERVED41;\r
- __IO uint16_t DR39;\r
- uint16_t RESERVED42;\r
- __IO uint16_t DR40;\r
- uint16_t RESERVED43;\r
- __IO uint16_t DR41;\r
- uint16_t RESERVED44;\r
- __IO uint16_t DR42;\r
- uint16_t RESERVED45; \r
-} BKP_TypeDef;\r
- \r
-/** \r
- * @brief Controller Area Network TxMailBox \r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t TIR;\r
- __IO uint32_t TDTR;\r
- __IO uint32_t TDLR;\r
- __IO uint32_t TDHR;\r
-} CAN_TxMailBox_TypeDef;\r
-\r
-/** \r
- * @brief Controller Area Network FIFOMailBox \r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t RIR;\r
- __IO uint32_t RDTR;\r
- __IO uint32_t RDLR;\r
- __IO uint32_t RDHR;\r
-} CAN_FIFOMailBox_TypeDef;\r
-\r
-/** \r
- * @brief Controller Area Network FilterRegister \r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t FR1;\r
- __IO uint32_t FR2;\r
-} CAN_FilterRegister_TypeDef;\r
-\r
-/** \r
- * @brief Controller Area Network \r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t MCR;\r
- __IO uint32_t MSR;\r
- __IO uint32_t TSR;\r
- __IO uint32_t RF0R;\r
- __IO uint32_t RF1R;\r
- __IO uint32_t IER;\r
- __IO uint32_t ESR;\r
- __IO uint32_t BTR;\r
- uint32_t RESERVED0[88];\r
- CAN_TxMailBox_TypeDef sTxMailBox[3];\r
- CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];\r
- uint32_t RESERVED1[12];\r
- __IO uint32_t FMR;\r
- __IO uint32_t FM1R;\r
- uint32_t RESERVED2;\r
- __IO uint32_t FS1R;\r
- uint32_t RESERVED3;\r
- __IO uint32_t FFA1R;\r
- uint32_t RESERVED4;\r
- __IO uint32_t FA1R;\r
- uint32_t RESERVED5[8];\r
-#ifndef STM32F10X_CL\r
- CAN_FilterRegister_TypeDef sFilterRegister[14];\r
-#else\r
- CAN_FilterRegister_TypeDef sFilterRegister[28];\r
-#endif /* STM32F10X_CL */ \r
-} CAN_TypeDef;\r
-\r
-/** \r
- * @brief Consumer Electronics Control (CEC)\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t CFGR;\r
- __IO uint32_t OAR;\r
- __IO uint32_t PRES;\r
- __IO uint32_t ESR;\r
- __IO uint32_t CSR;\r
- __IO uint32_t TXD;\r
- __IO uint32_t RXD; \r
-} CEC_TypeDef;\r
-\r
-/** \r
- * @brief CRC calculation unit \r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t DR;\r
- __IO uint8_t IDR;\r
- uint8_t RESERVED0;\r
- uint16_t RESERVED1;\r
- __IO uint32_t CR;\r
-} CRC_TypeDef;\r
-\r
-/** \r
- * @brief Digital to Analog Converter\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR;\r
- __IO uint32_t SWTRIGR;\r
- __IO uint32_t DHR12R1;\r
- __IO uint32_t DHR12L1;\r
- __IO uint32_t DHR8R1;\r
- __IO uint32_t DHR12R2;\r
- __IO uint32_t DHR12L2;\r
- __IO uint32_t DHR8R2;\r
- __IO uint32_t DHR12RD;\r
- __IO uint32_t DHR12LD;\r
- __IO uint32_t DHR8RD;\r
- __IO uint32_t DOR1;\r
- __IO uint32_t DOR2;\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
- __IO uint32_t SR;\r
-#endif\r
-} DAC_TypeDef;\r
-\r
-/** \r
- * @brief Debug MCU\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t IDCODE;\r
- __IO uint32_t CR; \r
-}DBGMCU_TypeDef;\r
-\r
-/** \r
- * @brief DMA Controller\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CCR;\r
- __IO uint32_t CNDTR;\r
- __IO uint32_t CPAR;\r
- __IO uint32_t CMAR;\r
-} DMA_Channel_TypeDef;\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t ISR;\r
- __IO uint32_t IFCR;\r
-} DMA_TypeDef;\r
-\r
-/** \r
- * @brief Ethernet MAC\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t MACCR;\r
- __IO uint32_t MACFFR;\r
- __IO uint32_t MACHTHR;\r
- __IO uint32_t MACHTLR;\r
- __IO uint32_t MACMIIAR;\r
- __IO uint32_t MACMIIDR;\r
- __IO uint32_t MACFCR;\r
- __IO uint32_t MACVLANTR; /* 8 */\r
- uint32_t RESERVED0[2];\r
- __IO uint32_t MACRWUFFR; /* 11 */\r
- __IO uint32_t MACPMTCSR;\r
- uint32_t RESERVED1[2];\r
- __IO uint32_t MACSR; /* 15 */\r
- __IO uint32_t MACIMR;\r
- __IO uint32_t MACA0HR;\r
- __IO uint32_t MACA0LR;\r
- __IO uint32_t MACA1HR;\r
- __IO uint32_t MACA1LR;\r
- __IO uint32_t MACA2HR;\r
- __IO uint32_t MACA2LR;\r
- __IO uint32_t MACA3HR;\r
- __IO uint32_t MACA3LR; /* 24 */\r
- uint32_t RESERVED2[40];\r
- __IO uint32_t MMCCR; /* 65 */\r
- __IO uint32_t MMCRIR;\r
- __IO uint32_t MMCTIR;\r
- __IO uint32_t MMCRIMR;\r
- __IO uint32_t MMCTIMR; /* 69 */\r
- uint32_t RESERVED3[14];\r
- __IO uint32_t MMCTGFSCCR; /* 84 */\r
- __IO uint32_t MMCTGFMSCCR;\r
- uint32_t RESERVED4[5];\r
- __IO uint32_t MMCTGFCR;\r
- uint32_t RESERVED5[10];\r
- __IO uint32_t MMCRFCECR;\r
- __IO uint32_t MMCRFAECR;\r
- uint32_t RESERVED6[10];\r
- __IO uint32_t MMCRGUFCR;\r
- uint32_t RESERVED7[334];\r
- __IO uint32_t PTPTSCR;\r
- __IO uint32_t PTPSSIR;\r
- __IO uint32_t PTPTSHR;\r
- __IO uint32_t PTPTSLR;\r
- __IO uint32_t PTPTSHUR;\r
- __IO uint32_t PTPTSLUR;\r
- __IO uint32_t PTPTSAR;\r
- __IO uint32_t PTPTTHR;\r
- __IO uint32_t PTPTTLR;\r
- uint32_t RESERVED8[567];\r
- __IO uint32_t DMABMR;\r
- __IO uint32_t DMATPDR;\r
- __IO uint32_t DMARPDR;\r
- __IO uint32_t DMARDLAR;\r
- __IO uint32_t DMATDLAR;\r
- __IO uint32_t DMASR;\r
- __IO uint32_t DMAOMR;\r
- __IO uint32_t DMAIER;\r
- __IO uint32_t DMAMFBOCR;\r
- uint32_t RESERVED9[9];\r
- __IO uint32_t DMACHTDR;\r
- __IO uint32_t DMACHRDR;\r
- __IO uint32_t DMACHTBAR;\r
- __IO uint32_t DMACHRBAR;\r
-} ETH_TypeDef;\r
-\r
-/** \r
- * @brief External Interrupt/Event Controller\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t IMR;\r
- __IO uint32_t EMR;\r
- __IO uint32_t RTSR;\r
- __IO uint32_t FTSR;\r
- __IO uint32_t SWIER;\r
- __IO uint32_t PR;\r
-} EXTI_TypeDef;\r
-\r
-/** \r
- * @brief FLASH Registers\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t ACR;\r
- __IO uint32_t KEYR;\r
- __IO uint32_t OPTKEYR;\r
- __IO uint32_t SR;\r
- __IO uint32_t CR;\r
- __IO uint32_t AR;\r
- __IO uint32_t RESERVED;\r
- __IO uint32_t OBR;\r
- __IO uint32_t WRPR;\r
-#ifdef STM32F10X_XL\r
- uint32_t RESERVED1[8]; \r
- __IO uint32_t KEYR2;\r
- uint32_t RESERVED2; \r
- __IO uint32_t SR2;\r
- __IO uint32_t CR2;\r
- __IO uint32_t AR2; \r
-#endif /* STM32F10X_XL */ \r
-} FLASH_TypeDef;\r
-\r
-/** \r
- * @brief Option Bytes Registers\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint16_t RDP;\r
- __IO uint16_t USER;\r
- __IO uint16_t Data0;\r
- __IO uint16_t Data1;\r
- __IO uint16_t WRP0;\r
- __IO uint16_t WRP1;\r
- __IO uint16_t WRP2;\r
- __IO uint16_t WRP3;\r
-} OB_TypeDef;\r
-\r
-/** \r
- * @brief Flexible Static Memory Controller\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t BTCR[8]; \r
-} FSMC_Bank1_TypeDef; \r
-\r
-/** \r
- * @brief Flexible Static Memory Controller Bank1E\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t BWTR[7];\r
-} FSMC_Bank1E_TypeDef;\r
-\r
-/** \r
- * @brief Flexible Static Memory Controller Bank2\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t PCR2;\r
- __IO uint32_t SR2;\r
- __IO uint32_t PMEM2;\r
- __IO uint32_t PATT2;\r
- uint32_t RESERVED0; \r
- __IO uint32_t ECCR2; \r
-} FSMC_Bank2_TypeDef; \r
-\r
-/** \r
- * @brief Flexible Static Memory Controller Bank3\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t PCR3;\r
- __IO uint32_t SR3;\r
- __IO uint32_t PMEM3;\r
- __IO uint32_t PATT3;\r
- uint32_t RESERVED0; \r
- __IO uint32_t ECCR3; \r
-} FSMC_Bank3_TypeDef; \r
-\r
-/** \r
- * @brief Flexible Static Memory Controller Bank4\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t PCR4;\r
- __IO uint32_t SR4;\r
- __IO uint32_t PMEM4;\r
- __IO uint32_t PATT4;\r
- __IO uint32_t PIO4; \r
-} FSMC_Bank4_TypeDef; \r
-\r
-/** \r
- * @brief General Purpose I/O\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CRL;\r
- __IO uint32_t CRH;\r
- __IO uint32_t IDR;\r
- __IO uint32_t ODR;\r
- __IO uint32_t BSRR;\r
- __IO uint32_t BRR;\r
- __IO uint32_t LCKR;\r
-} GPIO_TypeDef;\r
-\r
-/** \r
- * @brief Alternate Function I/O\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t EVCR;\r
- __IO uint32_t MAPR;\r
- __IO uint32_t EXTICR[4];\r
- uint32_t RESERVED0;\r
- __IO uint32_t MAPR2; \r
-} AFIO_TypeDef;\r
-/** \r
- * @brief Inter-integrated Circuit Interface\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint16_t CR1;\r
- uint16_t RESERVED0;\r
- __IO uint16_t CR2;\r
- uint16_t RESERVED1;\r
- __IO uint16_t OAR1;\r
- uint16_t RESERVED2;\r
- __IO uint16_t OAR2;\r
- uint16_t RESERVED3;\r
- __IO uint16_t DR;\r
- uint16_t RESERVED4;\r
- __IO uint16_t SR1;\r
- uint16_t RESERVED5;\r
- __IO uint16_t SR2;\r
- uint16_t RESERVED6;\r
- __IO uint16_t CCR;\r
- uint16_t RESERVED7;\r
- __IO uint16_t TRISE;\r
- uint16_t RESERVED8;\r
-} I2C_TypeDef;\r
-\r
-/** \r
- * @brief Independent WATCHDOG\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t KR;\r
- __IO uint32_t PR;\r
- __IO uint32_t RLR;\r
- __IO uint32_t SR;\r
-} IWDG_TypeDef;\r
-\r
-/** \r
- * @brief Power Control\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR;\r
- __IO uint32_t CSR;\r
-} PWR_TypeDef;\r
-\r
-/** \r
- * @brief Reset and Clock Control\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR;\r
- __IO uint32_t CFGR;\r
- __IO uint32_t CIR;\r
- __IO uint32_t APB2RSTR;\r
- __IO uint32_t APB1RSTR;\r
- __IO uint32_t AHBENR;\r
- __IO uint32_t APB2ENR;\r
- __IO uint32_t APB1ENR;\r
- __IO uint32_t BDCR;\r
- __IO uint32_t CSR;\r
-\r
-#ifdef STM32F10X_CL \r
- __IO uint32_t AHBRSTR;\r
- __IO uint32_t CFGR2;\r
-#endif /* STM32F10X_CL */ \r
-\r
-#if defined STM32F10X_LD_VL || defined STM32F10X_MD_VL \r
- uint32_t RESERVED0;\r
- __IO uint32_t CFGR2;\r
-#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL */ \r
-} RCC_TypeDef;\r
-\r
-/** \r
- * @brief Real-Time Clock\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint16_t CRH;\r
- uint16_t RESERVED0;\r
- __IO uint16_t CRL;\r
- uint16_t RESERVED1;\r
- __IO uint16_t PRLH;\r
- uint16_t RESERVED2;\r
- __IO uint16_t PRLL;\r
- uint16_t RESERVED3;\r
- __IO uint16_t DIVH;\r
- uint16_t RESERVED4;\r
- __IO uint16_t DIVL;\r
- uint16_t RESERVED5;\r
- __IO uint16_t CNTH;\r
- uint16_t RESERVED6;\r
- __IO uint16_t CNTL;\r
- uint16_t RESERVED7;\r
- __IO uint16_t ALRH;\r
- uint16_t RESERVED8;\r
- __IO uint16_t ALRL;\r
- uint16_t RESERVED9;\r
-} RTC_TypeDef;\r
-\r
-/** \r
- * @brief SD host Interface\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t POWER;\r
- __IO uint32_t CLKCR;\r
- __IO uint32_t ARG;\r
- __IO uint32_t CMD;\r
- __I uint32_t RESPCMD;\r
- __I uint32_t RESP1;\r
- __I uint32_t RESP2;\r
- __I uint32_t RESP3;\r
- __I uint32_t RESP4;\r
- __IO uint32_t DTIMER;\r
- __IO uint32_t DLEN;\r
- __IO uint32_t DCTRL;\r
- __I uint32_t DCOUNT;\r
- __I uint32_t STA;\r
- __IO uint32_t ICR;\r
- __IO uint32_t MASK;\r
- uint32_t RESERVED0[2];\r
- __I uint32_t FIFOCNT;\r
- uint32_t RESERVED1[13];\r
- __IO uint32_t FIFO;\r
-} SDIO_TypeDef;\r
-\r
-/** \r
- * @brief Serial Peripheral Interface\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint16_t CR1;\r
- uint16_t RESERVED0;\r
- __IO uint16_t CR2;\r
- uint16_t RESERVED1;\r
- __IO uint16_t SR;\r
- uint16_t RESERVED2;\r
- __IO uint16_t DR;\r
- uint16_t RESERVED3;\r
- __IO uint16_t CRCPR;\r
- uint16_t RESERVED4;\r
- __IO uint16_t RXCRCR;\r
- uint16_t RESERVED5;\r
- __IO uint16_t TXCRCR;\r
- uint16_t RESERVED6;\r
- __IO uint16_t I2SCFGR;\r
- uint16_t RESERVED7;\r
- __IO uint16_t I2SPR;\r
- uint16_t RESERVED8; \r
-} SPI_TypeDef;\r
-\r
-/** \r
- * @brief TIM\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint16_t CR1;\r
- uint16_t RESERVED0;\r
- __IO uint16_t CR2;\r
- uint16_t RESERVED1;\r
- __IO uint16_t SMCR;\r
- uint16_t RESERVED2;\r
- __IO uint16_t DIER;\r
- uint16_t RESERVED3;\r
- __IO uint16_t SR;\r
- uint16_t RESERVED4;\r
- __IO uint16_t EGR;\r
- uint16_t RESERVED5;\r
- __IO uint16_t CCMR1;\r
- uint16_t RESERVED6;\r
- __IO uint16_t CCMR2;\r
- uint16_t RESERVED7;\r
- __IO uint16_t CCER;\r
- uint16_t RESERVED8;\r
- __IO uint16_t CNT;\r
- uint16_t RESERVED9;\r
- __IO uint16_t PSC;\r
- uint16_t RESERVED10;\r
- __IO uint16_t ARR;\r
- uint16_t RESERVED11;\r
- __IO uint16_t RCR;\r
- uint16_t RESERVED12;\r
- __IO uint16_t CCR1;\r
- uint16_t RESERVED13;\r
- __IO uint16_t CCR2;\r
- uint16_t RESERVED14;\r
- __IO uint16_t CCR3;\r
- uint16_t RESERVED15;\r
- __IO uint16_t CCR4;\r
- uint16_t RESERVED16;\r
- __IO uint16_t BDTR;\r
- uint16_t RESERVED17;\r
- __IO uint16_t DCR;\r
- uint16_t RESERVED18;\r
- __IO uint16_t DMAR;\r
- uint16_t RESERVED19;\r
-} TIM_TypeDef;\r
-\r
-/** \r
- * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint16_t SR;\r
- uint16_t RESERVED0;\r
- __IO uint16_t DR;\r
- uint16_t RESERVED1;\r
- __IO uint16_t BRR;\r
- uint16_t RESERVED2;\r
- __IO uint16_t CR1;\r
- uint16_t RESERVED3;\r
- __IO uint16_t CR2;\r
- uint16_t RESERVED4;\r
- __IO uint16_t CR3;\r
- uint16_t RESERVED5;\r
- __IO uint16_t GTPR;\r
- uint16_t RESERVED6;\r
-} USART_TypeDef;\r
-\r
-/** \r
- * @brief Window WATCHDOG\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR;\r
- __IO uint32_t CFR;\r
- __IO uint32_t SR;\r
-} WWDG_TypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @addtogroup Peripheral_memory_map\r
- * @{\r
- */\r
-\r
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */\r
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */\r
-\r
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the bit-band region */\r
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the bit-band region */\r
-\r
-#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */\r
-\r
-/*!< Peripheral memory map */\r
-#define APB1PERIPH_BASE PERIPH_BASE\r
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)\r
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)\r
-\r
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)\r
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)\r
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)\r
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)\r
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)\r
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)\r
-#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)\r
-#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)\r
-#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)\r
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)\r
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)\r
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)\r
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)\r
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)\r
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)\r
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)\r
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)\r
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000)\r
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)\r
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)\r
-#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)\r
-#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)\r
-#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)\r
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)\r
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)\r
-#define CEC_BASE (APB1PERIPH_BASE + 0x7800)\r
-\r
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)\r
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)\r
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)\r
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)\r
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)\r
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)\r
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)\r
-#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)\r
-#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)\r
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)\r
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)\r
-#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)\r
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)\r
-#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)\r
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)\r
-#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)\r
-#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)\r
-#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)\r
-#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)\r
-#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)\r
-#define TIM10_BASE (APB2PERIPH_BASE + 0x5000)\r
-#define TIM11_BASE (APB2PERIPH_BASE + 0x5400)\r
-\r
-#define SDIO_BASE (PERIPH_BASE + 0x18000)\r
-\r
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)\r
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)\r
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)\r
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)\r
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)\r
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)\r
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)\r
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)\r
-#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)\r
-#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)\r
-#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)\r
-#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)\r
-#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)\r
-#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)\r
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)\r
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)\r
-\r
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */\r
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */\r
-\r
-#define ETH_BASE (AHBPERIPH_BASE + 0x8000)\r
-#define ETH_MAC_BASE (ETH_BASE)\r
-#define ETH_MMC_BASE (ETH_BASE + 0x0100)\r
-#define ETH_PTP_BASE (ETH_BASE + 0x0700)\r
-#define ETH_DMA_BASE (ETH_BASE + 0x1000)\r
-\r
-#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */\r
-#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */\r
-#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */\r
-#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */\r
-#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */\r
-\r
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @addtogroup Peripheral_declaration\r
- * @{\r
- */ \r
-\r
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)\r
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
-#define TIM12 ((TIM_TypeDef *) TIM12_BASE)\r
-#define TIM13 ((TIM_TypeDef *) TIM13_BASE)\r
-#define TIM14 ((TIM_TypeDef *) TIM14_BASE)\r
-#define RTC ((RTC_TypeDef *) RTC_BASE)\r
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)\r
-#define USART2 ((USART_TypeDef *) USART2_BASE)\r
-#define USART3 ((USART_TypeDef *) USART3_BASE)\r
-#define UART4 ((USART_TypeDef *) UART4_BASE)\r
-#define UART5 ((USART_TypeDef *) UART5_BASE)\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
-#define CAN1 ((CAN_TypeDef *) CAN1_BASE)\r
-#define CAN2 ((CAN_TypeDef *) CAN2_BASE)\r
-#define BKP ((BKP_TypeDef *) BKP_BASE)\r
-#define PWR ((PWR_TypeDef *) PWR_BASE)\r
-#define DAC ((DAC_TypeDef *) DAC_BASE)\r
-#define CEC ((CEC_TypeDef *) CEC_BASE)\r
-#define AFIO ((AFIO_TypeDef *) AFIO_BASE)\r
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\r
-#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)\r
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)\r
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)\r
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)\r
-#define TIM8 ((TIM_TypeDef *) TIM8_BASE)\r
-#define USART1 ((USART_TypeDef *) USART1_BASE)\r
-#define ADC3 ((ADC_TypeDef *) ADC3_BASE)\r
-#define TIM15 ((TIM_TypeDef *) TIM15_BASE)\r
-#define TIM16 ((TIM_TypeDef *) TIM16_BASE)\r
-#define TIM17 ((TIM_TypeDef *) TIM17_BASE)\r
-#define TIM9 ((TIM_TypeDef *) TIM9_BASE)\r
-#define TIM10 ((TIM_TypeDef *) TIM10_BASE)\r
-#define TIM11 ((TIM_TypeDef *) TIM11_BASE)\r
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)\r
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\r
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\r
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\r
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\r
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)\r
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)\r
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)\r
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)\r
-#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)\r
-#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)\r
-#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)\r
-#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)\r
-#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)\r
-#define RCC ((RCC_TypeDef *) RCC_BASE)\r
-#define CRC ((CRC_TypeDef *) CRC_BASE)\r
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r
-#define OB ((OB_TypeDef *) OB_BASE) \r
-#define ETH ((ETH_TypeDef *) ETH_BASE)\r
-#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)\r
-#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)\r
-#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)\r
-#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)\r
-#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)\r
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup Exported_constants\r
- * @{\r
- */\r
- \r
- /** @addtogroup Peripheral_Registers_Bits_Definition\r
- * @{\r
- */\r
- \r
-/******************************************************************************/\r
-/* Peripheral Registers_Bits_Definition */\r
-/******************************************************************************/\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* CRC calculation unit */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for CRC_DR register *********************/\r
-#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */\r
-\r
-\r
-/******************* Bit definition for CRC_IDR register ********************/\r
-#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */\r
-\r
-\r
-/******************** Bit definition for CRC_CR register ********************/\r
-#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Power Control */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************** Bit definition for PWR_CR register ********************/\r
-#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */\r
-#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */\r
-#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */\r
-#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */\r
-#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */\r
-\r
-#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */\r
-#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */\r
-#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */\r
-#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */\r
-\r
-/*!< PVD level configuration */\r
-#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */\r
-#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */\r
-#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */\r
-#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */\r
-#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */\r
-#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */\r
-#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */\r
-#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */\r
-\r
-#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */\r
-\r
-\r
-/******************* Bit definition for PWR_CSR register ********************/\r
-#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */\r
-#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */\r
-#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */\r
-#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Backup registers */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for BKP_DR1 register ********************/\r
-#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR2 register ********************/\r
-#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR3 register ********************/\r
-#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR4 register ********************/\r
-#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR5 register ********************/\r
-#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR6 register ********************/\r
-#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR7 register ********************/\r
-#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR8 register ********************/\r
-#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR9 register ********************/\r
-#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR10 register *******************/\r
-#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR11 register *******************/\r
-#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR12 register *******************/\r
-#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR13 register *******************/\r
-#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR14 register *******************/\r
-#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR15 register *******************/\r
-#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR16 register *******************/\r
-#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR17 register *******************/\r
-#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/****************** Bit definition for BKP_DR18 register ********************/\r
-#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR19 register *******************/\r
-#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR20 register *******************/\r
-#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR21 register *******************/\r
-#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR22 register *******************/\r
-#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR23 register *******************/\r
-#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR24 register *******************/\r
-#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR25 register *******************/\r
-#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR26 register *******************/\r
-#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR27 register *******************/\r
-#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR28 register *******************/\r
-#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR29 register *******************/\r
-#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR30 register *******************/\r
-#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR31 register *******************/\r
-#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR32 register *******************/\r
-#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR33 register *******************/\r
-#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR34 register *******************/\r
-#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR35 register *******************/\r
-#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR36 register *******************/\r
-#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR37 register *******************/\r
-#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR38 register *******************/\r
-#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR39 register *******************/\r
-#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR40 register *******************/\r
-#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR41 register *******************/\r
-#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR42 register *******************/\r
-#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */\r
-\r
-/****************** Bit definition for BKP_RTCCR register *******************/\r
-#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */\r
-#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */\r
-#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */\r
-#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */\r
-\r
-/******************** Bit definition for BKP_CR register ********************/\r
-#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */\r
-#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */\r
-\r
-/******************* Bit definition for BKP_CSR register ********************/\r
-#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */\r
-#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */\r
-#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */\r
-#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */\r
-#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Reset and Clock Control */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************** Bit definition for RCC_CR register ********************/\r
-#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */\r
-#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */\r
-#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */\r
-#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */\r
-#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */\r
-#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */\r
-#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */\r
-#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */\r
-#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */\r
-#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */\r
-\r
-#ifdef STM32F10X_CL\r
- #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */\r
- #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */\r
- #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */\r
- #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */\r
-#endif /* STM32F10X_CL */\r
-\r
-/******************* Bit definition for RCC_CFGR register *******************/\r
-/*!< SW configuration */\r
-#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */\r
-#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-\r
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */\r
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */\r
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */\r
-\r
-/*!< SWS configuration */\r
-#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */\r
-#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
-#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
-\r
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */\r
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */\r
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */\r
-\r
-/*!< HPRE configuration */\r
-#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */\r
-#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
-#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
-#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
-#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
-\r
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */\r
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */\r
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */\r
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */\r
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */\r
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */\r
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */\r
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */\r
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */\r
-\r
-/*!< PPRE1 configuration */\r
-#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */\r
-#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
-#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
-#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
-\r
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */\r
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */\r
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */\r
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */\r
-\r
-/*!< PPRE2 configuration */\r
-#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */\r
-#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */\r
-#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */\r
-#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */\r
-\r
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */\r
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */\r
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */\r
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */\r
-\r
-/*!< ADCPPRE configuration */\r
-#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */\r
-#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */\r
-#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */\r
-\r
-#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */\r
-#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */\r
-#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */\r
-#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */\r
-\r
-#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */\r
-\r
-#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */\r
-\r
-/*!< PLLMUL configuration */\r
-#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */\r
-#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
-#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
-#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
-#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */\r
-\r
-#ifdef STM32F10X_CL\r
- #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */\r
- #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */\r
-\r
- #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */\r
- #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */\r
-\r
- #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */\r
- #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */\r
- #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */\r
- #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */\r
- #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */\r
- #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */\r
- #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */\r
- \r
- #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */\r
- \r
-/*!< MCO configuration */\r
- #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */\r
- #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
- #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
- #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
- #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */\r
-\r
- #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
- #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */\r
- #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */\r
- #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */\r
- #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */\r
- #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/\r
- #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/\r
- #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */\r
- #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */\r
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
- #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */\r
- #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */\r
-\r
- #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */\r
- #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */\r
-\r
- #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */\r
- #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */\r
- #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */\r
- #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */\r
- #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */\r
- #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */\r
- #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */\r
- #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */\r
- #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */\r
- #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */\r
- #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */\r
- #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */\r
- #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */\r
- #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */\r
- #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */\r
-\r
-/*!< MCO configuration */\r
- #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */\r
- #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
- #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
- #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
-\r
- #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
- #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */\r
- #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */\r
- #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */\r
- #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */\r
-#else\r
- #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */\r
- #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */\r
-\r
- #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */\r
- #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */\r
-\r
- #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */\r
- #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */\r
- #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */\r
- #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */\r
- #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */\r
- #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */\r
- #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */\r
- #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */\r
- #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */\r
- #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */\r
- #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */\r
- #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */\r
- #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */\r
- #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */\r
- #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */\r
- #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */\r
-\r
-/*!< MCO configuration */\r
- #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */\r
- #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
- #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
- #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
-\r
- #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
- #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */\r
- #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */\r
- #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */\r
- #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */\r
-#endif /* STM32F10X_CL */\r
-\r
-/*!<****************** Bit definition for RCC_CIR register ********************/\r
-#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */\r
-#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */\r
-#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */\r
-#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */\r
-#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */\r
-#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */\r
-#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */\r
-#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */\r
-#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */\r
-#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */\r
-#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */\r
-#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */\r
-#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */\r
-#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */\r
-#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */\r
-#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */\r
-#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */\r
-\r
-#ifdef STM32F10X_CL\r
- #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */\r
- #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */\r
- #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */\r
- #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */\r
- #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */\r
- #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */\r
-#endif /* STM32F10X_CL */\r
-\r
-/***************** Bit definition for RCC_APB2RSTR register *****************/\r
-#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */\r
-#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */\r
-#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */\r
-#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */\r
-#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */\r
-#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */\r
-\r
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL)\r
-#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */\r
-#endif\r
-\r
-#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */\r
-#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */\r
-#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */\r
-\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
-#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */\r
-#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */\r
-#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */\r
-#endif\r
-\r
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)\r
- #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */\r
-#endif /* STM32F10X_LD && STM32F10X_LD_VL */\r
-\r
-#if defined (STM32F10X_HD) || defined (STM32F10X_XL)\r
- #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */\r
- #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */\r
- #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */\r
- #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */\r
-#endif\r
-\r
-#ifdef STM32F10X_XL\r
- #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */\r
- #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */\r
- #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */\r
-#endif /* STM32F10X_XL */\r
-\r
-/***************** Bit definition for RCC_APB1RSTR register *****************/\r
-#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */\r
-#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */\r
-#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */\r
-#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */\r
-#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */\r
-\r
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL)\r
-#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */\r
-#endif\r
-\r
-#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */\r
-#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */\r
-\r
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)\r
- #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */\r
- #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */\r
- #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */\r
- #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */\r
-#endif /* STM32F10X_LD && STM32F10X_LD_VL */\r
-\r
-#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL)\r
- #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */\r
-#endif\r
-\r
-#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL)\r
- #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */\r
- #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */\r
- #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */\r
- #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */\r
- #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */\r
- #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */\r
- #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */\r
-#endif\r
-\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
- #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */\r
- #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */\r
- #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */\r
- #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ \r
-#endif\r
-\r
-#ifdef STM32F10X_CL\r
- #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */\r
-#endif /* STM32F10X_CL */\r
-\r
-#ifdef STM32F10X_XL\r
- #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */\r
- #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */\r
- #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */\r
-#endif /* STM32F10X_XL */\r
-\r
-/****************** Bit definition for RCC_AHBENR register ******************/\r
-#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */\r
-#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */\r
-#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */\r
-#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */\r
-\r
-#if defined (STM32F10X_HD) || defined (STM32F10X_CL)\r
- #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */\r
-#endif\r
-\r
-#if defined (STM32F10X_HD) || defined (STM32F10X_XL)\r
- #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */\r
- #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */\r
-#endif\r
-\r
-#ifdef STM32F10X_CL\r
- #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */\r
- #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */\r
- #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */\r
- #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */\r
-#endif /* STM32F10X_CL */\r
-\r
-/****************** Bit definition for RCC_APB2ENR register *****************/\r
-#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */\r
-#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */\r
-#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */\r
-#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */\r
-#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */\r
-#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */\r
-\r
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL)\r
-#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */\r
-#endif\r
-\r
-#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */\r
-#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */\r
-#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */\r
-\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
-#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */\r
-#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */\r
-#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */\r
-#endif\r
-\r
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)\r
- #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */\r
-#endif /* STM32F10X_LD && STM32F10X_LD_VL */\r
-\r
-#if defined (STM32F10X_HD) || defined (STM32F10X_XL)\r
- #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */\r
- #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */\r
- #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */\r
- #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */\r
-#endif\r
-\r
-#ifdef STM32F10X_XL\r
- #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */\r
- #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */\r
- #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */\r
-#endif\r
-\r
-/***************** Bit definition for RCC_APB1ENR register ******************/\r
-#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/\r
-#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */\r
-#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */\r
-#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */\r
-#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */\r
-\r
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL)\r
-#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */\r
-#endif\r
-\r
-#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */\r
-#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */\r
-\r
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)\r
- #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */\r
- #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */\r
- #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */\r
- #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */\r
-#endif /* STM32F10X_LD && STM32F10X_LD_VL */\r
-\r
-#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)\r
- #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */\r
-#endif\r
-\r
-#if defined (STM32F10X_HD) || defined (STM32F10X_CL)\r
- #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */\r
- #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */\r
- #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */\r
- #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */\r
- #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */\r
- #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */\r
- #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */\r
-#endif\r
-\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
- #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */\r
- #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */\r
- #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */\r
- #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ \r
-#endif\r
-\r
-#ifdef STM32F10X_CL\r
- #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */\r
-#endif /* STM32F10X_CL */\r
-\r
-#ifdef STM32F10X_XL\r
- #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */\r
- #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */\r
- #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */\r
-#endif /* STM32F10X_XL */\r
-\r
-/******************* Bit definition for RCC_BDCR register *******************/\r
-#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */\r
-#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */\r
-#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */\r
-\r
-#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */\r
-#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
-#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
-\r
-/*!< RTC congiguration */\r
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */\r
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */\r
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */\r
-\r
-#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */\r
-#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */\r
-\r
-/******************* Bit definition for RCC_CSR register ********************/ \r
-#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */\r
-#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */\r
-#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */\r
-#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */\r
-#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */\r
-#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */\r
-#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */\r
-#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */\r
-#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */\r
-\r
-#ifdef STM32F10X_CL\r
-/******************* Bit definition for RCC_AHBRSTR register ****************/\r
- #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */\r
- #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */\r
-\r
-/******************* Bit definition for RCC_CFGR2 register ******************/\r
-/*!< PREDIV1 configuration */\r
- #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */\r
- #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
- #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
- #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
- #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
-\r
- #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */\r
- #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */\r
- #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */\r
- #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */\r
- #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */\r
- #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */\r
- #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */\r
- #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */\r
- #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */\r
- #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */\r
- #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */\r
- #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */\r
- #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */\r
- #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */\r
- #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */\r
- #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */\r
-\r
-/*!< PREDIV2 configuration */\r
- #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */\r
- #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
- #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
- #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
- #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
-\r
- #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */\r
- #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */\r
- #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */\r
- #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */\r
- #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */\r
- #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */\r
- #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */\r
- #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */\r
- #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */\r
- #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */\r
- #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */\r
- #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */\r
- #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */\r
- #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */\r
- #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */\r
- #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */\r
-\r
-/*!< PLL2MUL configuration */\r
- #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */\r
- #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
- #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
- #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
- #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
-\r
- #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */\r
- #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */\r
- #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */\r
- #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */\r
- #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */\r
- #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */\r
- #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */\r
- #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */\r
- #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */\r
-\r
-/*!< PLL3MUL configuration */\r
- #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */\r
- #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
- #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
- #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */\r
- #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */\r
-\r
- #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */\r
- #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */\r
- #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */\r
- #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */\r
- #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */\r
- #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */\r
- #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */\r
- #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */\r
- #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */\r
-\r
- #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */\r
- #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */\r
- #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */\r
- #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */\r
- #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */\r
-#endif /* STM32F10X_CL */\r
-\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
-/******************* Bit definition for RCC_CFGR2 register ******************/\r
-/*!< PREDIV1 configuration */\r
- #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */\r
- #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
- #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
- #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
- #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
-\r
- #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */\r
- #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */\r
- #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */\r
- #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */\r
- #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */\r
- #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */\r
- #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */\r
- #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */\r
- #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */\r
- #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */\r
- #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */\r
- #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */\r
- #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */\r
- #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */\r
- #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */\r
- #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */\r
-#endif\r
- \r
-/******************************************************************************/\r
-/* */\r
-/* General Purpose and Alternate Function I/O */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for GPIO_CRL register *******************/\r
-#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */\r
-\r
-#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */\r
-#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-\r
-#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */\r
-#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
-#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
-\r
-#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */\r
-#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
-#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
-\r
-#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */\r
-#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
-#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
-\r
-#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */\r
-#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
-#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
-\r
-#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */\r
-#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
-#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
-\r
-#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */\r
-#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
-#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
-\r
-#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */\r
-#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
-#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
-\r
-#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */\r
-\r
-#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */\r
-#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
-#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
-\r
-#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */\r
-#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
-#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
-\r
-#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */\r
-#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-\r
-#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */\r
-#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */\r
-#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */\r
-\r
-#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */\r
-#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
-#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
-\r
-#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */\r
-#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */\r
-#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */\r
-\r
-#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */\r
-#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
-#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
-\r
-#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */\r
-#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */\r
-#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */\r
-\r
-/******************* Bit definition for GPIO_CRH register *******************/\r
-#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */\r
-\r
-#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */\r
-#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-\r
-#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */\r
-#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
-#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
-\r
-#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */\r
-#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
-#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
-\r
-#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */\r
-#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
-#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
-\r
-#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */\r
-#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
-#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
-\r
-#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */\r
-#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
-#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
-\r
-#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */\r
-#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
-#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
-\r
-#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */\r
-#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
-#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
-\r
-#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */\r
-\r
-#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */\r
-#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
-#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
-\r
-#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */\r
-#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
-#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
-\r
-#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */\r
-#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-\r
-#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */\r
-#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */\r
-#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */\r
-\r
-#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */\r
-#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
-#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
-\r
-#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */\r
-#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */\r
-#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */\r
-\r
-#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */\r
-#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
-#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
-\r
-#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */\r
-#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */\r
-#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */\r
-\r
-/*!<****************** Bit definition for GPIO_IDR register *******************/\r
-#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */\r
-#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */\r
-#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */\r
-#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */\r
-#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */\r
-#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */\r
-#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */\r
-#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */\r
-#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */\r
-#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */\r
-#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */\r
-#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */\r
-#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */\r
-#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */\r
-#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */\r
-#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */\r
-\r
-/******************* Bit definition for GPIO_ODR register *******************/\r
-#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */\r
-#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */\r
-#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */\r
-#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */\r
-#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */\r
-#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */\r
-#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */\r
-#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */\r
-#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */\r
-#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */\r
-#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */\r
-#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */\r
-#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */\r
-#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */\r
-#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */\r
-#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */\r
-\r
-/****************** Bit definition for GPIO_BSRR register *******************/\r
-#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */\r
-#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */\r
-#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */\r
-#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */\r
-#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */\r
-#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */\r
-#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */\r
-#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */\r
-#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */\r
-#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */\r
-#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */\r
-#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */\r
-#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */\r
-#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */\r
-#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */\r
-#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */\r
-\r
-#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */\r
-#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */\r
-#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */\r
-#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */\r
-#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */\r
-#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */\r
-#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */\r
-#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */\r
-#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */\r
-#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */\r
-#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */\r
-#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */\r
-#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */\r
-#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */\r
-#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */\r
-#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */\r
-\r
-/******************* Bit definition for GPIO_BRR register *******************/\r
-#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */\r
-#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */\r
-#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */\r
-#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */\r
-#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */\r
-#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */\r
-#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */\r
-#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */\r
-#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */\r
-#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */\r
-#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */\r
-#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */\r
-#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */\r
-#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */\r
-#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */\r
-#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */\r
-\r
-/****************** Bit definition for GPIO_LCKR register *******************/\r
-#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */\r
-#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */\r
-#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */\r
-#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */\r
-#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */\r
-#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */\r
-#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */\r
-#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */\r
-#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */\r
-#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */\r
-#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */\r
-#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */\r
-#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */\r
-#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */\r
-#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */\r
-#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */\r
-#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/****************** Bit definition for AFIO_EVCR register *******************/\r
-#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */\r
-#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */\r
-#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */\r
-#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */\r
-#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */\r
-\r
-/*!< PIN configuration */\r
-#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */\r
-#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */\r
-#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */\r
-#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */\r
-#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */\r
-#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */\r
-#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */\r
-#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */\r
-#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */\r
-#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */\r
-#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */\r
-#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */\r
-#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */\r
-#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */\r
-#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */\r
-#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */\r
-\r
-#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */\r
-#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */\r
-#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */\r
-#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */\r
-\r
-/*!< PORT configuration */\r
-#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */\r
-#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */\r
-#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */\r
-#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */\r
-#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */\r
-\r
-#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */\r
-\r
-/****************** Bit definition for AFIO_MAPR register *******************/\r
-#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */\r
-#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */\r
-#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */\r
-#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */\r
-\r
-#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */\r
-#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
-#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
-\r
-/* USART3_REMAP configuration */\r
-#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */\r
-#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */\r
-#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */\r
-\r
-#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */\r
-#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
-#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
-\r
-/*!< TIM1_REMAP configuration */\r
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */\r
-#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */\r
-#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */\r
-\r
-#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */\r
-#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
-#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
-\r
-/*!< TIM2_REMAP configuration */\r
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */\r
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */\r
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */\r
-#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */\r
-\r
-#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */\r
-#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-\r
-/*!< TIM3_REMAP configuration */\r
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */\r
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */\r
-#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */\r
-\r
-#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */\r
-\r
-#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */\r
-#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */\r
-#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */\r
-\r
-/*!< CAN_REMAP configuration */\r
-#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */\r
-#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */\r
-#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */\r
-\r
-#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */\r
-#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */\r
-#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */\r
-#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */\r
-#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */\r
-#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */\r
-\r
-/*!< SWJ_CFG configuration */\r
-#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */\r
-#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
-#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
-#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
-\r
-#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */\r
-#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */\r
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */\r
-#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */\r
-\r
-#ifdef STM32F10X_CL\r
-/*!< ETH_REMAP configuration */\r
- #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */\r
-\r
-/*!< CAN2_REMAP configuration */\r
- #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */\r
-\r
-/*!< MII_RMII_SEL configuration */\r
- #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */\r
-\r
-/*!< SPI3_REMAP configuration */\r
- #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */\r
-\r
-/*!< TIM2ITR1_IREMAP configuration */\r
- #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */\r
-\r
-/*!< PTP_PPS_REMAP configuration */\r
- #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */\r
-#endif\r
-\r
-/***************** Bit definition for AFIO_EXTICR1 register *****************/\r
-#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */\r
-#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */\r
-#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */\r
-#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */\r
-\r
-/*!< EXTI0 configuration */\r
-#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */\r
-#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */\r
-#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */\r
-#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */\r
-#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */\r
-#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */\r
-#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */\r
-\r
-/*!< EXTI1 configuration */\r
-#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */\r
-#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */\r
-#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */\r
-#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */\r
-#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */\r
-#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */\r
-#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */\r
-\r
-/*!< EXTI2 configuration */ \r
-#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */\r
-#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */\r
-#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */\r
-#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */\r
-#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */\r
-#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */\r
-#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */\r
-\r
-/*!< EXTI3 configuration */\r
-#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */\r
-#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */\r
-#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */\r
-#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */\r
-#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */\r
-#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */\r
-#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */\r
-\r
-/***************** Bit definition for AFIO_EXTICR2 register *****************/\r
-#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */\r
-#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */\r
-#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */\r
-#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */\r
-\r
-/*!< EXTI4 configuration */\r
-#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */\r
-#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */\r
-#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */\r
-#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */\r
-#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */\r
-#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */\r
-#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */\r
-\r
-/* EXTI5 configuration */\r
-#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */\r
-#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */\r
-#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */\r
-#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */\r
-#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */\r
-#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */\r
-#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */\r
-\r
-/*!< EXTI6 configuration */ \r
-#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */\r
-#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */\r
-#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */\r
-#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */\r
-#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */\r
-#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */\r
-#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */\r
-\r
-/*!< EXTI7 configuration */\r
-#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */\r
-#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */\r
-#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */\r
-#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */\r
-#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */\r
-#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */\r
-#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */\r
-\r
-/***************** Bit definition for AFIO_EXTICR3 register *****************/\r
-#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */\r
-#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */\r
-#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */\r
-#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */\r
-\r
-/*!< EXTI8 configuration */\r
-#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */\r
-#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */\r
-#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */\r
-#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */\r
-#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */\r
-#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */\r
-#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */\r
-\r
-/*!< EXTI9 configuration */\r
-#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */\r
-#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */\r
-#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */\r
-#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */\r
-#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */\r
-#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */\r
-#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */\r
-\r
-/*!< EXTI10 configuration */ \r
-#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */\r
-#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */\r
-#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */\r
-#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */\r
-#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */\r
-#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */\r
-#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */\r
-\r
-/*!< EXTI11 configuration */\r
-#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */\r
-#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */\r
-#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */\r
-#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */\r
-#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */\r
-#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */\r
-#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */\r
-\r
-/***************** Bit definition for AFIO_EXTICR4 register *****************/\r
-#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */\r
-#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */\r
-#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */\r
-#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */\r
-\r
-/* EXTI12 configuration */\r
-#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */\r
-#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */\r
-#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */\r
-#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */\r
-#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */\r
-#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */\r
-#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */\r
-\r
-/* EXTI13 configuration */\r
-#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */\r
-#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */\r
-#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */\r
-#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */\r
-#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */\r
-#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */\r
-#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */\r
-\r
-/*!< EXTI14 configuration */ \r
-#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */\r
-#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */\r
-#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */\r
-#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */\r
-#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */\r
-#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */\r
-#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */\r
-\r
-/*!< EXTI15 configuration */\r
-#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */\r
-#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */\r
-#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */\r
-#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */\r
-#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */\r
-#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */\r
-#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */\r
-\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) \r
-/****************** Bit definition for AFIO_MAPR2 register ******************/\r
-#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */\r
-#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */\r
-#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */\r
-#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */\r
-#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */\r
-#endif\r
-\r
-#ifdef STM32F10X_XL \r
-/****************** Bit definition for AFIO_MAPR2 register ******************/\r
-#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */\r
-#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */\r
-#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */\r
-#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */\r
-#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */\r
-#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */\r
-#endif\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* SystemTick */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/***************** Bit definition for SysTick_CTRL register *****************/\r
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */\r
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */\r
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */\r
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */\r
-\r
-/***************** Bit definition for SysTick_LOAD register *****************/\r
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */\r
-\r
-/***************** Bit definition for SysTick_VAL register ******************/\r
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */\r
-\r
-/***************** Bit definition for SysTick_CALIB register ****************/\r
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */\r
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */\r
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Nested Vectored Interrupt Controller */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/****************** Bit definition for NVIC_ISER register *******************/\r
-#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */\r
-#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
-#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
-#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
-#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
-#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
-#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
-#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
-#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
-#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
-#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
-#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
-#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
-#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
-#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
-#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
-#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
-#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
-#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
-#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
-#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
-#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
-#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
-#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
-#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
-#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
-#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
-#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
-#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
-#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
-#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
-#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
-#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
-\r
-/****************** Bit definition for NVIC_ICER register *******************/\r
-#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */\r
-#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
-#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
-#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
-#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
-#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
-#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
-#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
-#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
-#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
-#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
-#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
-#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
-#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
-#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
-#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
-#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
-#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
-#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
-#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
-#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
-#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
-#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
-#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
-#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
-#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
-#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
-#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
-#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
-#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
-#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
-#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
-#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
-\r
-/****************** Bit definition for NVIC_ISPR register *******************/\r
-#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */\r
-#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
-#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
-#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
-#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
-#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
-#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
-#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
-#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
-#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
-#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
-#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
-#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
-#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
-#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
-#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
-#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
-#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
-#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
-#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
-#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
-#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
-#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
-#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
-#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
-#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
-#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
-#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
-#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
-#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
-#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
-#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
-#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
-\r
-/****************** Bit definition for NVIC_ICPR register *******************/\r
-#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */\r
-#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
-#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
-#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
-#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
-#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
-#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
-#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
-#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
-#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
-#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
-#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
-#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
-#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
-#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
-#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
-#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
-#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
-#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
-#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
-#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
-#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
-#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
-#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
-#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
-#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
-#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
-#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
-#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
-#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
-#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
-#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
-#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
-\r
-/****************** Bit definition for NVIC_IABR register *******************/\r
-#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */\r
-#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
-#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
-#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
-#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
-#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
-#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
-#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
-#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
-#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
-#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
-#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
-#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
-#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
-#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
-#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
-#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
-#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
-#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
-#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
-#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
-#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
-#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
-#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
-#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
-#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
-#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
-#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
-#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
-#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
-#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
-#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
-#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
-\r
-/****************** Bit definition for NVIC_PRI0 register *******************/\r
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */\r
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */\r
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */\r
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */\r
-\r
-/****************** Bit definition for NVIC_PRI1 register *******************/\r
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */\r
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */\r
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */\r
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */\r
-\r
-/****************** Bit definition for NVIC_PRI2 register *******************/\r
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */\r
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */\r
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */\r
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */\r
-\r
-/****************** Bit definition for NVIC_PRI3 register *******************/\r
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */\r
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */\r
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */\r
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */\r
-\r
-/****************** Bit definition for NVIC_PRI4 register *******************/\r
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */\r
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */\r
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */\r
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */\r
-\r
-/****************** Bit definition for NVIC_PRI5 register *******************/\r
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */\r
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */\r
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */\r
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */\r
-\r
-/****************** Bit definition for NVIC_PRI6 register *******************/\r
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */\r
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */\r
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */\r
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */\r
-\r
-/****************** Bit definition for NVIC_PRI7 register *******************/\r
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */\r
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */\r
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */\r
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */\r
-\r
-/****************** Bit definition for SCB_CPUID register *******************/\r
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */\r
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */\r
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */\r
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */\r
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */\r
-\r
-/******************* Bit definition for SCB_ICSR register *******************/\r
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */\r
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */\r
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */\r
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */\r
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */\r
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */\r
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */\r
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */\r
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */\r
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */\r
-\r
-/******************* Bit definition for SCB_VTOR register *******************/\r
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */\r
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */\r
-\r
-/*!<***************** Bit definition for SCB_AIRCR register *******************/\r
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */\r
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */\r
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */\r
-\r
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */\r
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
-\r
-/* prority group configuration */\r
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */\r
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */\r
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */\r
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */\r
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */\r
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */\r
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */\r
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */\r
-\r
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */\r
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */\r
-\r
-/******************* Bit definition for SCB_SCR register ********************/\r
-#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */\r
-#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */\r
-#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */\r
-\r
-/******************** Bit definition for SCB_CCR register *******************/\r
-#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */\r
-#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */\r
-#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */\r
-#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */\r
-#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */\r
-#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */\r
-\r
-/******************* Bit definition for SCB_SHPR register ********************/\r
-#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */\r
-#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */\r
-#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */\r
-#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */\r
-\r
-/****************** Bit definition for SCB_SHCSR register *******************/\r
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */\r
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */\r
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */\r
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */\r
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */\r
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */\r
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */\r
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */\r
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */\r
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */\r
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */\r
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */\r
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */\r
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */\r
-\r
-/******************* Bit definition for SCB_CFSR register *******************/\r
-/*!< MFSR */\r
-#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */\r
-#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */\r
-#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */\r
-#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */\r
-#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */\r
-/*!< BFSR */\r
-#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */\r
-#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */\r
-#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */\r
-#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */\r
-#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */\r
-#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */\r
-/*!< UFSR */\r
-#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */\r
-#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */\r
-#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */\r
-#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */\r
-#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */\r
-#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */\r
-\r
-/******************* Bit definition for SCB_HFSR register *******************/\r
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */\r
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */\r
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */\r
-\r
-/******************* Bit definition for SCB_DFSR register *******************/\r
-#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */\r
-#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */\r
-#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */\r
-#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */\r
-#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */\r
-\r
-/******************* Bit definition for SCB_MMFAR register ******************/\r
-#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */\r
-\r
-/******************* Bit definition for SCB_BFAR register *******************/\r
-#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */\r
-\r
-/******************* Bit definition for SCB_afsr register *******************/\r
-#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* External Interrupt/Event Controller */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for EXTI_IMR register *******************/\r
-#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */\r
-#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */\r
-#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */\r
-#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */\r
-#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */\r
-#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */\r
-#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */\r
-#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */\r
-#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */\r
-#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */\r
-#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */\r
-#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */\r
-#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */\r
-#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */\r
-#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */\r
-#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */\r
-#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */\r
-#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */\r
-#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */\r
-#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */\r
-\r
-/******************* Bit definition for EXTI_EMR register *******************/\r
-#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */\r
-#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */\r
-#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */\r
-#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */\r
-#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */\r
-#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */\r
-#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */\r
-#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */\r
-#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */\r
-#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */\r
-#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */\r
-#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */\r
-#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */\r
-#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */\r
-#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */\r
-#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */\r
-#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */\r
-#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */\r
-#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */\r
-#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */\r
-\r
-/****************** Bit definition for EXTI_RTSR register *******************/\r
-#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */\r
-#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */\r
-#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */\r
-#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */\r
-#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */\r
-#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */\r
-#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */\r
-#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */\r
-#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */\r
-#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */\r
-#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */\r
-#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */\r
-#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */\r
-#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */\r
-#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */\r
-#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */\r
-#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */\r
-#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */\r
-#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */\r
-#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */\r
-\r
-/****************** Bit definition for EXTI_FTSR register *******************/\r
-#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */\r
-#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */\r
-#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */\r
-#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */\r
-#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */\r
-#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */\r
-#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */\r
-#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */\r
-#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */\r
-#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */\r
-#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */\r
-#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */\r
-#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */\r
-#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */\r
-#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */\r
-#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */\r
-#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */\r
-#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */\r
-#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */\r
-#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */\r
-\r
-/****************** Bit definition for EXTI_SWIER register ******************/\r
-#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */\r
-#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */\r
-#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */\r
-#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */\r
-#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */\r
-#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */\r
-#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */\r
-#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */\r
-#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */\r
-#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */\r
-#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */\r
-#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */\r
-#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */\r
-#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */\r
-#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */\r
-#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */\r
-#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */\r
-#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */\r
-#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */\r
-#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */\r
-\r
-/******************* Bit definition for EXTI_PR register ********************/\r
-#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */\r
-#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */\r
-#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */\r
-#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */\r
-#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */\r
-#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */\r
-#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */\r
-#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */\r
-#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */\r
-#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */\r
-#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */\r
-#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */\r
-#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */\r
-#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */\r
-#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */\r
-#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */\r
-#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */\r
-#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */\r
-#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */\r
-#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* DMA Controller */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for DMA_ISR register ********************/\r
-#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */\r
-#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */\r
-#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */\r
-#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */\r
-#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */\r
-#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */\r
-#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */\r
-#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */\r
-#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */\r
-#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */\r
-#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */\r
-#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */\r
-#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */\r
-#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */\r
-#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */\r
-#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */\r
-#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */\r
-#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */\r
-#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */\r
-#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */\r
-#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */\r
-#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */\r
-#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */\r
-#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */\r
-#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */\r
-#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */\r
-#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */\r
-#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */\r
-\r
-/******************* Bit definition for DMA_IFCR register *******************/\r
-#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */\r
-#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */\r
-#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */\r
-#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */\r
-#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */\r
-#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */\r
-#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */\r
-#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */\r
-\r
-/******************* Bit definition for DMA_CCR1 register *******************/\r
-#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/\r
-#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
-#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
-#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
-#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
-#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
-#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
-#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
-\r
-#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
-#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
-#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
-\r
-#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
-#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
-#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
-\r
-#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */\r
-#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
-#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
-\r
-#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
-\r
-/******************* Bit definition for DMA_CCR2 register *******************/\r
-#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */\r
-#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */\r
-#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
-#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
-#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
-#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
-#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
-#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
-\r
-#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
-#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
-#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
-\r
-#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
-#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
-#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
-\r
-#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
-#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
-#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
-\r
-#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
-\r
-/******************* Bit definition for DMA_CCR3 register *******************/\r
-#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */\r
-#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
-#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
-#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
-#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
-#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
-#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
-#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
-\r
-#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
-#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
-#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
-\r
-#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
-#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
-#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
-\r
-#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
-#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
-#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
-\r
-#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
-\r
-/*!<****************** Bit definition for DMA_CCR4 register *******************/\r
-#define DMA_CCR4_EN ((uint16_t)0x0001) /*!<Channel enable */\r
-#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */\r
-#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */\r
-#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */\r
-#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!<Data transfer direction */\r
-#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!<Circular mode */\r
-#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */\r
-#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!<Memory increment mode */\r
-\r
-#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */\r
-#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-\r
-#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */\r
-#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-\r
-#define DMA_CCR4_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */\r
-#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */\r
-\r
-/****************** Bit definition for DMA_CCR5 register *******************/\r
-#define DMA_CCR5_EN ((uint16_t)0x0001) /*!<Channel enable */\r
-#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */\r
-#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */\r
-#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */\r
-#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!<Data transfer direction */\r
-#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!<Circular mode */\r
-#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */\r
-#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!<Memory increment mode */\r
-\r
-#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */\r
-#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-\r
-#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */\r
-#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-\r
-#define DMA_CCR5_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */\r
-#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */\r
-\r
-/******************* Bit definition for DMA_CCR6 register *******************/\r
-#define DMA_CCR6_EN ((uint16_t)0x0001) /*!<Channel enable */\r
-#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */\r
-#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */\r
-#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */\r
-#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!<Data transfer direction */\r
-#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!<Circular mode */\r
-#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */\r
-#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!<Memory increment mode */\r
-\r
-#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */\r
-#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-\r
-#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */\r
-#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-\r
-#define DMA_CCR6_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */\r
-#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */\r
-\r
-/******************* Bit definition for DMA_CCR7 register *******************/\r
-#define DMA_CCR7_EN ((uint16_t)0x0001) /*!<Channel enable */\r
-#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */\r
-#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */\r
-#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */\r
-#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!<Data transfer direction */\r
-#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!<Circular mode */\r
-#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */\r
-#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!<Memory increment mode */\r
-\r
-#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */\r
-#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-\r
-#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */\r
-#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-\r
-#define DMA_CCR7_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */\r
-#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */\r
-\r
-/****************** Bit definition for DMA_CNDTR1 register ******************/\r
-#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */\r
-\r
-/****************** Bit definition for DMA_CNDTR2 register ******************/\r
-#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */\r
-\r
-/****************** Bit definition for DMA_CNDTR3 register ******************/\r
-#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */\r
-\r
-/****************** Bit definition for DMA_CNDTR4 register ******************/\r
-#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */\r
-\r
-/****************** Bit definition for DMA_CNDTR5 register ******************/\r
-#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */\r
-\r
-/****************** Bit definition for DMA_CNDTR6 register ******************/\r
-#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */\r
-\r
-/****************** Bit definition for DMA_CNDTR7 register ******************/\r
-#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */\r
-\r
-/****************** Bit definition for DMA_CPAR1 register *******************/\r
-#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */\r
-\r
-/****************** Bit definition for DMA_CPAR2 register *******************/\r
-#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */\r
-\r
-/****************** Bit definition for DMA_CPAR3 register *******************/\r
-#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */\r
-\r
-\r
-/****************** Bit definition for DMA_CPAR4 register *******************/\r
-#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */\r
-\r
-/****************** Bit definition for DMA_CPAR5 register *******************/\r
-#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */\r
-\r
-/****************** Bit definition for DMA_CPAR6 register *******************/\r
-#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */\r
-\r
-\r
-/****************** Bit definition for DMA_CPAR7 register *******************/\r
-#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */\r
-\r
-/****************** Bit definition for DMA_CMAR1 register *******************/\r
-#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */\r
-\r
-/****************** Bit definition for DMA_CMAR2 register *******************/\r
-#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */\r
-\r
-/****************** Bit definition for DMA_CMAR3 register *******************/\r
-#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */\r
-\r
-\r
-/****************** Bit definition for DMA_CMAR4 register *******************/\r
-#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */\r
-\r
-/****************** Bit definition for DMA_CMAR5 register *******************/\r
-#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */\r
-\r
-/****************** Bit definition for DMA_CMAR6 register *******************/\r
-#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */\r
-\r
-/****************** Bit definition for DMA_CMAR7 register *******************/\r
-#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Analog to Digital Converter */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************** Bit definition for ADC_SR register ********************/\r
-#define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */\r
-#define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */\r
-#define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */\r
-#define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */\r
-#define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */\r
-\r
-/******************* Bit definition for ADC_CR1 register ********************/\r
-#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
-#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-\r
-#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */\r
-#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */\r
-#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */\r
-#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */\r
-#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */\r
-#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */\r
-#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */\r
-#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */\r
-\r
-#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\r
-#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
-#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
-#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
-\r
-#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!<DUALMOD[3:0] bits (Dual mode selection) */\r
-#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-\r
-#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */\r
-#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */\r
-\r
- \r
-/******************* Bit definition for ADC_CR2 register ********************/\r
-#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */\r
-#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */\r
-#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!<A/D Calibration */\r
-#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!<Reset Calibration */\r
-#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */\r
-#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */\r
-\r
-#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!<JEXTSEL[2:0] bits (External event select for injected group) */\r
-#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
-#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
-#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
-\r
-#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!<External Trigger Conversion mode for injected channels */\r
-\r
-#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!<EXTSEL[2:0] bits (External Event Select for regular group) */\r
-#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
-#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
-#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
-\r
-#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!<External Trigger Conversion mode for regular channels */\r
-#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!<Start Conversion of injected channels */\r
-#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!<Start Conversion of regular channels */\r
-#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */\r
-\r
-/****************** Bit definition for ADC_SMPR1 register *******************/\r
-#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\r
-#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-\r
-#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\r
-#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
-#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
-#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
-\r
-#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\r
-#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
-#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
-#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */\r
-\r
-#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\r
-#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
-#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
-#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
-\r
-#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\r
-#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
-#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
-#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
-\r
-#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\r
-#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
-#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
-#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
-\r
-#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\r
-#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
-#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
-#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */\r
-\r
-#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\r
-#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */\r
-#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */\r
-#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
-\r
-/****************** Bit definition for ADC_SMPR2 register *******************/\r
-#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\r
-#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-\r
-#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\r
-#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
-\r
-#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\r
-#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */\r
-\r
-#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\r
-#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
-\r
-#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\r
-#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
-\r
-#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\r
-#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
-\r
-#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\r
-#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */\r
-\r
-#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\r
-#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
-\r
-#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\r
-#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-\r
-#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\r
-#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */\r
-\r
-/****************** Bit definition for ADC_JOFR1 register *******************/\r
-#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */\r
-\r
-/****************** Bit definition for ADC_JOFR2 register *******************/\r
-#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */\r
-\r
-/****************** Bit definition for ADC_JOFR3 register *******************/\r
-#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */\r
-\r
-/****************** Bit definition for ADC_JOFR4 register *******************/\r
-#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */\r
-\r
-/******************* Bit definition for ADC_HTR register ********************/\r
-#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */\r
-\r
-/******************* Bit definition for ADC_LTR register ********************/\r
-#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */\r
-\r
-/******************* Bit definition for ADC_SQR1 register *******************/\r
-#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\r
-#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-\r
-#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\r
-#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
-#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
-#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
-#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
-#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
-\r
-#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\r
-#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
-#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
-#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
-\r
-#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\r
-#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
-#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
-#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
-#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
-#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
-\r
-#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */\r
-#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-/******************* Bit definition for ADC_SQR2 register *******************/\r
-#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\r
-#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-\r
-#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\r
-#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
-#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
-#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
-#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
-#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
-\r
-#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\r
-#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
-#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
-#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
-\r
-#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\r
-#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
-#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
-#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
-#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
-#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
-\r
-#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\r
-#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */\r
-\r
-#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\r
-#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */\r
-#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */\r
-#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */\r
-#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */\r
-#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */\r
-\r
-/******************* Bit definition for ADC_SQR3 register *******************/\r
-#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\r
-#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-\r
-#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\r
-#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
-#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
-#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
-#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
-#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
-\r
-#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\r
-#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
-#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
-#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
-\r
-#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\r
-#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
-#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
-#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
-#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
-#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
-\r
-#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\r
-#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */\r
-\r
-#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\r
-#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */\r
-#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */\r
-#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */\r
-#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */\r
-#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */\r
-\r
-/******************* Bit definition for ADC_JSQR register *******************/\r
-#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ \r
-#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-\r
-#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\r
-#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
-#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
-#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
-#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
-#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
-\r
-#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\r
-#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
-#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
-#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
-\r
-#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\r
-#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
-#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
-#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
-#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
-#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
-\r
-#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */\r
-#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-\r
-/******************* Bit definition for ADC_JDR1 register *******************/\r
-#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
-\r
-/******************* Bit definition for ADC_JDR2 register *******************/\r
-#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
-\r
-/******************* Bit definition for ADC_JDR3 register *******************/\r
-#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
-\r
-/******************* Bit definition for ADC_JDR4 register *******************/\r
-#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
-\r
-/******************** Bit definition for ADC_DR register ********************/\r
-#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */\r
-#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Digital to Analog Converter */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************** Bit definition for DAC_CR register ********************/\r
-#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */\r
-#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */\r
-#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */\r
-\r
-#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
-#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
-#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
-#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
-\r
-#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r
-#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
-#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
-\r
-#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
-#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */\r
-#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */\r
-#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */\r
-#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */\r
-\r
-#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
-#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */\r
-#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */\r
-#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */\r
-\r
-#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
-#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */\r
-#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */\r
-\r
-#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
-#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */\r
-\r
-/***************** Bit definition for DAC_SWTRIGR register ******************/\r
-#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */\r
-#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */\r
-\r
-/***************** Bit definition for DAC_DHR12R1 register ******************/\r
-#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12L1 register ******************/\r
-#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */\r
-\r
-/****************** Bit definition for DAC_DHR8R1 register ******************/\r
-#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12R2 register ******************/\r
-#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12L2 register ******************/\r
-#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */\r
-\r
-/****************** Bit definition for DAC_DHR8R2 register ******************/\r
-#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12RD register ******************/\r
-#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */\r
-#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12LD register ******************/\r
-#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */\r
-#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */\r
-\r
-/****************** Bit definition for DAC_DHR8RD register ******************/\r
-#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */\r
-#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */\r
-\r
-/******************* Bit definition for DAC_DOR1 register *******************/\r
-#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */\r
-\r
-/******************* Bit definition for DAC_DOR2 register *******************/\r
-#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */\r
-\r
-/******************** Bit definition for DAC_SR register ********************/\r
-#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */\r
-#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* CEC */\r
-/* */\r
-/******************************************************************************/\r
-/******************** Bit definition for CEC_CFGR register ******************/\r
-#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */\r
-#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */\r
-#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */\r
-#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */\r
-\r
-/******************** Bit definition for CEC_OAR register ******************/\r
-#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */\r
-#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */\r
-#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */\r
-#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */\r
-#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */\r
-\r
-/******************** Bit definition for CEC_PRES register ******************/\r
-#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */\r
-\r
-/******************** Bit definition for CEC_ESR register ******************/\r
-#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */\r
-#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */\r
-#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */\r
-#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */\r
-#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */\r
-#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */\r
-#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finsihed Error */\r
-\r
-/******************** Bit definition for CEC_CSR register ******************/\r
-#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */\r
-#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */\r
-#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */\r
-#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */\r
-#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */\r
-#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */\r
-#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */\r
-#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */\r
-\r
-/******************** Bit definition for CEC_TXD register ******************/\r
-#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */\r
-\r
-/******************** Bit definition for CEC_RXD register ******************/\r
-#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* TIM */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for TIM_CR1 register ********************/\r
-#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */\r
-#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */\r
-#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */\r
-#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */\r
-#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */\r
-\r
-#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
-#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */\r
-#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */\r
-\r
-#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */\r
-\r
-#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */\r
-#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-\r
-/******************* Bit definition for TIM_CR2 register ********************/\r
-#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */\r
-#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */\r
-#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */\r
-\r
-#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */\r
-#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-\r
-#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */\r
-#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */\r
-#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */\r
-#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */\r
-#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */\r
-#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */\r
-#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */\r
-#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */\r
-\r
-/******************* Bit definition for TIM_SMCR register *******************/\r
-#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */\r
-#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
-\r
-#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */\r
-#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-\r
-#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */\r
-\r
-#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */\r
-#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
-#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
-\r
-#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */\r
-#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */\r
-#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */\r
-\r
-/******************* Bit definition for TIM_DIER register *******************/\r
-#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */\r
-#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */\r
-#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */\r
-#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */\r
-#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */\r
-#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */\r
-#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */\r
-#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */\r
-#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */\r
-#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */\r
-#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */\r
-#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */\r
-#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */\r
-#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */\r
-#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */\r
-\r
-/******************** Bit definition for TIM_SR register ********************/\r
-#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */\r
-#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */\r
-#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */\r
-#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */\r
-#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */\r
-#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */\r
-#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */\r
-#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */\r
-#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */\r
-#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */\r
-#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */\r
-#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */\r
-\r
-/******************* Bit definition for TIM_EGR register ********************/\r
-#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */\r
-#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */\r
-#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */\r
-#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */\r
-#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */\r
-#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */\r
-#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */\r
-#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */\r
-\r
-/****************** Bit definition for TIM_CCMR1 register *******************/\r
-#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
-#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */\r
-#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */\r
-\r
-#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
-#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-\r
-#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */\r
-\r
-#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
-#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */\r
-#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */\r
-\r
-#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
-#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
-\r
-#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
-#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
-#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
-#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
-\r
-#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
-#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
-#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
-#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
-\r
-/****************** Bit definition for TIM_CCMR2 register *******************/\r
-#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
-#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */\r
-#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */\r
-\r
-#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
-#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-\r
-#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */\r
-\r
-#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
-#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */\r
-#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */\r
-\r
-#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
-#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
-\r
-#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
-#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
-#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
-#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
-\r
-#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
-#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
-#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
-#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
-\r
-/******************* Bit definition for TIM_CCER register *******************/\r
-#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */\r
-#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */\r
-#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */\r
-#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */\r
-#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */\r
-#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */\r
-#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */\r
-#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */\r
-#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */\r
-#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */\r
-#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */\r
-#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */\r
-#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */\r
-#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */\r
-\r
-/******************* Bit definition for TIM_CNT register ********************/\r
-#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */\r
-\r
-/******************* Bit definition for TIM_PSC register ********************/\r
-#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */\r
-\r
-/******************* Bit definition for TIM_ARR register ********************/\r
-#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */\r
-\r
-/******************* Bit definition for TIM_RCR register ********************/\r
-#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */\r
-\r
-/******************* Bit definition for TIM_CCR1 register *******************/\r
-#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */\r
-\r
-/******************* Bit definition for TIM_CCR2 register *******************/\r
-#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */\r
-\r
-/******************* Bit definition for TIM_CCR3 register *******************/\r
-#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */\r
-\r
-/******************* Bit definition for TIM_CCR4 register *******************/\r
-#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */\r
-\r
-/******************* Bit definition for TIM_BDTR register *******************/\r
-#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r
-#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
-#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
-#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
-#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */\r
-#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */\r
-#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */\r
-\r
-#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */\r
-#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-\r
-#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */\r
-#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */\r
-#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */\r
-#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */\r
-#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */\r
-#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */\r
-\r
-/******************* Bit definition for TIM_DCR register ********************/\r
-#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */\r
-#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
-#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
-#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
-\r
-#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */\r
-#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
-#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
-#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */\r
-\r
-/******************* Bit definition for TIM_DMAR register *******************/\r
-#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Real-Time Clock */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for RTC_CRH register ********************/\r
-#define RTC_CRH_SECIE ((uint8_t)0x01) /*!<Second Interrupt Enable */\r
-#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!<Alarm Interrupt Enable */\r
-#define RTC_CRH_OWIE ((uint8_t)0x04) /*!<OverfloW Interrupt Enable */\r
-\r
-/******************* Bit definition for RTC_CRL register ********************/\r
-#define RTC_CRL_SECF ((uint8_t)0x01) /*!<Second Flag */\r
-#define RTC_CRL_ALRF ((uint8_t)0x02) /*!<Alarm Flag */\r
-#define RTC_CRL_OWF ((uint8_t)0x04) /*!<OverfloW Flag */\r
-#define RTC_CRL_RSF ((uint8_t)0x08) /*!<Registers Synchronized Flag */\r
-#define RTC_CRL_CNF ((uint8_t)0x10) /*!<Configuration Flag */\r
-#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!<RTC operation OFF */\r
-\r
-/******************* Bit definition for RTC_PRLH register *******************/\r
-#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!<RTC Prescaler Reload Value High */\r
-\r
-/******************* Bit definition for RTC_PRLL register *******************/\r
-#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!<RTC Prescaler Reload Value Low */\r
-\r
-/******************* Bit definition for RTC_DIVH register *******************/\r
-#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!<RTC Clock Divider High */\r
-\r
-/******************* Bit definition for RTC_DIVL register *******************/\r
-#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!<RTC Clock Divider Low */\r
-\r
-/******************* Bit definition for RTC_CNTH register *******************/\r
-#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter High */\r
-\r
-/******************* Bit definition for RTC_CNTL register *******************/\r
-#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter Low */\r
-\r
-/******************* Bit definition for RTC_ALRH register *******************/\r
-#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm High */\r
-\r
-/******************* Bit definition for RTC_ALRL register *******************/\r
-#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm Low */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Independent WATCHDOG */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for IWDG_KR register ********************/\r
-#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */\r
-\r
-/******************* Bit definition for IWDG_PR register ********************/\r
-#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */\r
-#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */\r
-#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */\r
-#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */\r
-\r
-/******************* Bit definition for IWDG_RLR register *******************/\r
-#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */\r
-\r
-/******************* Bit definition for IWDG_SR register ********************/\r
-#define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */\r
-#define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Window WATCHDOG */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for WWDG_CR register ********************/\r
-#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
-#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */\r
-#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */\r
-#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */\r
-#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */\r
-#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */\r
-#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */\r
-#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */\r
-\r
-#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */\r
-\r
-/******************* Bit definition for WWDG_CFR register *******************/\r
-#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */\r
-#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */\r
-#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */\r
-#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */\r
-#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */\r
-#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */\r
-\r
-#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */\r
-#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */\r
-#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */\r
-\r
-#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */\r
-\r
-/******************* Bit definition for WWDG_SR register ********************/\r
-#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Flexible Static Memory Controller */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/****************** Bit definition for FSMC_BCR1 register *******************/\r
-#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
-#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
-\r
-#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
-#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
-#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
-\r
-#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
-#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
-#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
-#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
-#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
-#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
-#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
-#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
-#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
-#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
-\r
-/****************** Bit definition for FSMC_BCR2 register *******************/\r
-#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
-#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
-\r
-#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
-#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
-#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
-\r
-#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
-#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
-#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
-#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
-#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
-#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
-#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
-#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
-#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
-#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
-\r
-/****************** Bit definition for FSMC_BCR3 register *******************/\r
-#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
-#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
-\r
-#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
-#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
-#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
-\r
-#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
-#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
-#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
-#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit. */\r
-#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
-#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
-#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
-#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
-#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
-#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
-\r
-/****************** Bit definition for FSMC_BCR4 register *******************/\r
-#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
-#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
-\r
-#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
-#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
-#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
-\r
-#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
-#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
-#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
-#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
-#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
-#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
-#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
-#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
-#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
-#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
-\r
-/****************** Bit definition for FSMC_BTR1 register ******************/\r
-#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
-#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FSMC_BTR2 register *******************/\r
-#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
-#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/******************* Bit definition for FSMC_BTR3 register *******************/\r
-#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
-#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FSMC_BTR4 register *******************/\r
-#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
-#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FSMC_BWTR1 register ******************/\r
-#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FSMC_BWTR2 register ******************/\r
-#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/\r
-#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FSMC_BWTR3 register ******************/\r
-#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FSMC_BWTR4 register ******************/\r
-#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FSMC_PCR2 register *******************/\r
-#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
-#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
-#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
-\r
-#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
-#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
-\r
-#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
-#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
-#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
-#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
-#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
-\r
-#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
-#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
-#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
-#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
-#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
-\r
-#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */\r
-#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
-#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
-#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
-\r
-/****************** Bit definition for FSMC_PCR3 register *******************/\r
-#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
-#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
-#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
-\r
-#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
-#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
-\r
-#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
-#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
-#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
-#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
-#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
-\r
-#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
-#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
-#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
-#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
-#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
-\r
-#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */\r
-#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
-#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
-#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
-\r
-/****************** Bit definition for FSMC_PCR4 register *******************/\r
-#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
-#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
-#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
-\r
-#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
-#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
-\r
-#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
-#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
-#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
-#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
-#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
-\r
-#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
-#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
-#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
-#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
-#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
-\r
-#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */\r
-#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
-#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
-#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
-\r
-/******************* Bit definition for FSMC_SR2 register *******************/\r
-#define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
-#define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
-#define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
-#define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
-#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
-#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
-#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
-\r
-/******************* Bit definition for FSMC_SR3 register *******************/\r
-#define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
-#define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
-#define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
-#define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
-#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
-#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
-#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
-\r
-/******************* Bit definition for FSMC_SR4 register *******************/\r
-#define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
-#define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
-#define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
-#define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
-#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
-#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
-#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
-\r
-/****************** Bit definition for FSMC_PMEM2 register ******************/\r
-#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */\r
-#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */\r
-#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */\r
-#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */\r
-#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FSMC_PMEM3 register ******************/\r
-#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\r
-#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\r
-#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\r
-#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\r
-#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FSMC_PMEM4 register ******************/\r
-#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */\r
-#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */\r
-#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */\r
-#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */\r
-#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FSMC_PATT2 register ******************/\r
-#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */\r
-#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */\r
-#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */\r
-#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */\r
-#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FSMC_PATT3 register ******************/\r
-#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\r
-#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\r
-#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\r
-#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\r
-#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FSMC_PATT4 register ******************/\r
-#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */\r
-#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */\r
-#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */\r
-#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */\r
-#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FSMC_PIO4 register *******************/\r
-#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */\r
-#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */\r
-#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */\r
-#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */\r
-#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FSMC_ECCR2 register ******************/\r
-#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */\r
-\r
-/****************** Bit definition for FSMC_ECCR3 register ******************/\r
-#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* SD host Interface */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/****************** Bit definition for SDIO_POWER register ******************/\r
-#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */\r
-#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */\r
-#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for SDIO_CLKCR register ******************/\r
-#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */\r
-#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */\r
-#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */\r
-#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */\r
-\r
-#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\r
-#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */\r
-#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */\r
-\r
-#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */\r
-#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */\r
-\r
-/******************* Bit definition for SDIO_ARG register *******************/\r
-#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */\r
-\r
-/******************* Bit definition for SDIO_CMD register *******************/\r
-#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */\r
-\r
-#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */\r
-#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */\r
-#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */\r
-\r
-#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */\r
-#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\r
-#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */\r
-#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */\r
-#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */\r
-#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */\r
-#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */\r
-\r
-/***************** Bit definition for SDIO_RESPCMD register *****************/\r
-#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */\r
-\r
-/****************** Bit definition for SDIO_RESP0 register ******************/\r
-#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
-\r
-/****************** Bit definition for SDIO_RESP1 register ******************/\r
-#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
-\r
-/****************** Bit definition for SDIO_RESP2 register ******************/\r
-#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
-\r
-/****************** Bit definition for SDIO_RESP3 register ******************/\r
-#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
-\r
-/****************** Bit definition for SDIO_RESP4 register ******************/\r
-#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
-\r
-/****************** Bit definition for SDIO_DTIMER register *****************/\r
-#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */\r
-\r
-/****************** Bit definition for SDIO_DLEN register *******************/\r
-#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */\r
-\r
-/****************** Bit definition for SDIO_DCTRL register ******************/\r
-#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */\r
-#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */\r
-#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */\r
-#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */\r
-\r
-#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */\r
-#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
-\r
-#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */\r
-#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */\r
-#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */\r
-#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */\r
-\r
-/****************** Bit definition for SDIO_DCOUNT register *****************/\r
-#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */\r
-\r
-/****************** Bit definition for SDIO_STA register ********************/\r
-#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */\r
-#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */\r
-#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */\r
-#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */\r
-#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */\r
-#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */\r
-#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */\r
-#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */\r
-#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */\r
-#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */\r
-#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */\r
-#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */\r
-#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */\r
-#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */\r
-#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r
-#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\r
-#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */\r
-#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */\r
-#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */\r
-#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */\r
-#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */\r
-#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */\r
-#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */\r
-#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */\r
-\r
-/******************* Bit definition for SDIO_ICR register *******************/\r
-#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */\r
-#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */\r
-#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */\r
-#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */\r
-#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */\r
-#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */\r
-#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */\r
-#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */\r
-#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */\r
-#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */\r
-#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */\r
-#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */\r
-#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */\r
-\r
-/****************** Bit definition for SDIO_MASK register *******************/\r
-#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */\r
-#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */\r
-#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */\r
-#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */\r
-#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */\r
-#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */\r
-#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */\r
-#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */\r
-#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */\r
-#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */\r
-#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */\r
-#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */\r
-#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */\r
-#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */\r
-#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */\r
-#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */\r
-#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */\r
-#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */\r
-#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */\r
-#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */\r
-#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */\r
-#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */\r
-#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */\r
-#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */\r
-\r
-/***************** Bit definition for SDIO_FIFOCNT register *****************/\r
-#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */\r
-\r
-/****************** Bit definition for SDIO_FIFO register *******************/\r
-#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* USB Device FS */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/*!<Endpoint-specific registers */\r
-/******************* Bit definition for USB_EP0R register *******************/\r
-#define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
-\r
-#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-\r
-#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
-#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
-#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
-\r
-#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
-#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
-\r
-#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
-\r
-#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
-#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP1R register *******************/\r
-#define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
-\r
-#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-\r
-#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
-#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
-#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
-\r
-#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
-#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
-\r
-#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
-\r
-#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
-#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP2R register *******************/\r
-#define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
-\r
-#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-\r
-#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
-#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
-#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
-\r
-#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
-#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
-\r
-#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
-\r
-#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
-#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP3R register *******************/\r
-#define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
-\r
-#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-\r
-#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
-#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
-#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
-\r
-#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
-#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
-\r
-#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
-\r
-#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
-#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP4R register *******************/\r
-#define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
-\r
-#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-\r
-#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
-#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
-#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
-\r
-#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
-#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
-\r
-#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
-\r
-#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
-#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP5R register *******************/\r
-#define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
-\r
-#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-\r
-#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
-#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
-#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
-\r
-#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
-#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
-\r
-#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
-\r
-#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
-#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP6R register *******************/\r
-#define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
-\r
-#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-\r
-#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
-#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
-#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
-\r
-#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
-#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
-\r
-#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
-\r
-#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
-#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP7R register *******************/\r
-#define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
-\r
-#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-\r
-#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
-#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
-#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
-\r
-#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
-#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
-\r
-#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
-\r
-#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
-#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
-\r
-/*!<Common registers */\r
-/******************* Bit definition for USB_CNTR register *******************/\r
-#define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */\r
-#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */\r
-#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */\r
-#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */\r
-#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */\r
-#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */\r
-#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */\r
-#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */\r
-#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */\r
-#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */\r
-#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */\r
-#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */\r
-#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */\r
-\r
-/******************* Bit definition for USB_ISTR register *******************/\r
-#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */\r
-#define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */\r
-#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */\r
-#define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */\r
-#define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */\r
-#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */\r
-#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */\r
-#define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */\r
-#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */\r
-#define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */\r
-\r
-/******************* Bit definition for USB_FNR register ********************/\r
-#define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */\r
-#define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */\r
-#define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */\r
-#define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */\r
-#define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */\r
-\r
-/****************** Bit definition for USB_DADDR register *******************/\r
-#define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */\r
-#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */\r
-#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */\r
-#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */\r
-#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */\r
-#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */\r
-#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */\r
-#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */\r
-\r
-#define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */\r
-\r
-/****************** Bit definition for USB_BTABLE register ******************/ \r
-#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */\r
-\r
-/*!<Buffer descriptor table */\r
-/***************** Bit definition for USB_ADDR0_TX register *****************/\r
-#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 0 */\r
-\r
-/***************** Bit definition for USB_ADDR1_TX register *****************/\r
-#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 1 */\r
-\r
-/***************** Bit definition for USB_ADDR2_TX register *****************/\r
-#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 2 */\r
-\r
-/***************** Bit definition for USB_ADDR3_TX register *****************/\r
-#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 3 */\r
-\r
-/***************** Bit definition for USB_ADDR4_TX register *****************/\r
-#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 4 */\r
-\r
-/***************** Bit definition for USB_ADDR5_TX register *****************/\r
-#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 5 */\r
-\r
-/***************** Bit definition for USB_ADDR6_TX register *****************/\r
-#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 6 */\r
-\r
-/***************** Bit definition for USB_ADDR7_TX register *****************/\r
-#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 7 */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/***************** Bit definition for USB_COUNT0_TX register ****************/\r
-#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 0 */\r
-\r
-/***************** Bit definition for USB_COUNT1_TX register ****************/\r
-#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 1 */\r
-\r
-/***************** Bit definition for USB_COUNT2_TX register ****************/\r
-#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 2 */\r
-\r
-/***************** Bit definition for USB_COUNT3_TX register ****************/\r
-#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 3 */\r
-\r
-/***************** Bit definition for USB_COUNT4_TX register ****************/\r
-#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 4 */\r
-\r
-/***************** Bit definition for USB_COUNT5_TX register ****************/\r
-#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 5 */\r
-\r
-/***************** Bit definition for USB_COUNT6_TX register ****************/\r
-#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 6 */\r
-\r
-/***************** Bit definition for USB_COUNT7_TX register ****************/\r
-#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 7 */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/**************** Bit definition for USB_COUNT0_TX_0 register ***************/\r
-#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 0 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT0_TX_1 register ***************/\r
-#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 0 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT1_TX_0 register ***************/\r
-#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 1 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT1_TX_1 register ***************/\r
-#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 1 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT2_TX_0 register ***************/\r
-#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 2 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT2_TX_1 register ***************/\r
-#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 2 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT3_TX_0 register ***************/\r
-#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!<Transmission Byte Count 3 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT3_TX_1 register ***************/\r
-#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!<Transmission Byte Count 3 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT4_TX_0 register ***************/\r
-#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 4 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT4_TX_1 register ***************/\r
-#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 4 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT5_TX_0 register ***************/\r
-#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 5 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT5_TX_1 register ***************/\r
-#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 5 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT6_TX_0 register ***************/\r
-#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 6 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT6_TX_1 register ***************/\r
-#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 6 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT7_TX_0 register ***************/\r
-#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 7 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT7_TX_1 register ***************/\r
-#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 7 (high) */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/***************** Bit definition for USB_ADDR0_RX register *****************/\r
-#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 0 */\r
-\r
-/***************** Bit definition for USB_ADDR1_RX register *****************/\r
-#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 1 */\r
-\r
-/***************** Bit definition for USB_ADDR2_RX register *****************/\r
-#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 2 */\r
-\r
-/***************** Bit definition for USB_ADDR3_RX register *****************/\r
-#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 3 */\r
-\r
-/***************** Bit definition for USB_ADDR4_RX register *****************/\r
-#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 4 */\r
-\r
-/***************** Bit definition for USB_ADDR5_RX register *****************/\r
-#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 5 */\r
-\r
-/***************** Bit definition for USB_ADDR6_RX register *****************/\r
-#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 6 */\r
-\r
-/***************** Bit definition for USB_ADDR7_RX register *****************/\r
-#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 7 */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/***************** Bit definition for USB_COUNT0_RX register ****************/\r
-#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */\r
-\r
-#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */\r
-#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */\r
-#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT1_RX register ****************/\r
-#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */\r
-\r
-#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */\r
-#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */\r
-#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT2_RX register ****************/\r
-#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */\r
-\r
-#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */\r
-#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */\r
-#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT3_RX register ****************/\r
-#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */\r
-\r
-#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */\r
-#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */\r
-#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT4_RX register ****************/\r
-#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */\r
-\r
-#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */\r
-#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */\r
-#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT5_RX register ****************/\r
-#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */\r
-\r
-#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */\r
-#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */\r
-#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT6_RX register ****************/\r
-#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */\r
-\r
-#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */\r
-#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */\r
-#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT7_RX register ****************/\r
-#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */\r
-\r
-#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */\r
-#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */\r
-#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/**************** Bit definition for USB_COUNT0_RX_0 register ***************/\r
-#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */\r
-\r
-#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT0_RX_1 register ***************/\r
-#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */\r
-\r
-#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 1 */\r
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */\r
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */\r
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */\r
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */\r
-\r
-/**************** Bit definition for USB_COUNT1_RX_0 register ***************/\r
-#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */\r
-\r
-#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT1_RX_1 register ***************/\r
-#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */\r
-\r
-#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */\r
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */\r
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */\r
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */\r
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */\r
-\r
-/**************** Bit definition for USB_COUNT2_RX_0 register ***************/\r
-#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */\r
-\r
-#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT2_RX_1 register ***************/\r
-#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */\r
-\r
-#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */\r
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */\r
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */\r
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */\r
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */\r
-\r
-/**************** Bit definition for USB_COUNT3_RX_0 register ***************/\r
-#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */\r
-\r
-#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT3_RX_1 register ***************/\r
-#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */\r
-\r
-#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */\r
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */\r
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */\r
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */\r
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */\r
-\r
-/**************** Bit definition for USB_COUNT4_RX_0 register ***************/\r
-#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */\r
-\r
-#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT4_RX_1 register ***************/\r
-#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */\r
-\r
-#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */\r
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */\r
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */\r
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */\r
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */\r
-\r
-/**************** Bit definition for USB_COUNT5_RX_0 register ***************/\r
-#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */\r
-\r
-#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT5_RX_1 register ***************/\r
-#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */\r
-\r
-#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */\r
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */\r
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */\r
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */\r
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */\r
-\r
-/*************** Bit definition for USB_COUNT6_RX_0 register ***************/\r
-#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */\r
-\r
-#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT6_RX_1 register ***************/\r
-#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */\r
-\r
-#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */\r
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */\r
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */\r
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */\r
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */\r
-\r
-/*************** Bit definition for USB_COUNT7_RX_0 register ****************/\r
-#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */\r
-\r
-#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */\r
-\r
-/*************** Bit definition for USB_COUNT7_RX_1 register ****************/\r
-#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */\r
-\r
-#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */\r
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */\r
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */\r
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */\r
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */\r
-\r
-#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Controller Area Network */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/*!<CAN control and status registers */\r
-/******************* Bit definition for CAN_MCR register ********************/\r
-#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */\r
-#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */\r
-#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */\r
-#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */\r
-#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */\r
-#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */\r
-#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */\r
-#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */\r
-#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */\r
-\r
-/******************* Bit definition for CAN_MSR register ********************/\r
-#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */\r
-#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */\r
-#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */\r
-#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */\r
-#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */\r
-#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */\r
-#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */\r
-#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */\r
-#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */\r
-\r
-/******************* Bit definition for CAN_TSR register ********************/\r
-#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */\r
-#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */\r
-#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */\r
-#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */\r
-#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */\r
-#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */\r
-#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */\r
-#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */\r
-#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */\r
-#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */\r
-#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */\r
-#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */\r
-#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */\r
-#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */\r
-#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */\r
-#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */\r
-\r
-#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */\r
-#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */\r
-#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */\r
-#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */\r
-\r
-#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */\r
-#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */\r
-#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */\r
-#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */\r
-\r
-/******************* Bit definition for CAN_RF0R register *******************/\r
-#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */\r
-#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */\r
-#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */\r
-#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */\r
-\r
-/******************* Bit definition for CAN_RF1R register *******************/\r
-#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */\r
-#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */\r
-#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */\r
-#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */\r
-\r
-/******************** Bit definition for CAN_IER register *******************/\r
-#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */\r
-#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */\r
-#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */\r
-#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */\r
-#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */\r
-#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */\r
-#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */\r
-#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */\r
-#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */\r
-#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */\r
-#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */\r
-#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */\r
-#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */\r
-#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */\r
-\r
-/******************** Bit definition for CAN_ESR register *******************/\r
-#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */\r
-#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */\r
-#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */\r
-\r
-#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */\r
-#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-\r
-#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */\r
-#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */\r
-\r
-/******************* Bit definition for CAN_BTR register ********************/\r
-#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */\r
-#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */\r
-#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */\r
-#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */\r
-#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */\r
-#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */\r
-\r
-/*!<Mailbox registers */\r
-/****************** Bit definition for CAN_TI0R register ********************/\r
-#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
-#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
-#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
-#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
-#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
-\r
-/****************** Bit definition for CAN_TDT0R register *******************/\r
-#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
-#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
-#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
-\r
-/****************** Bit definition for CAN_TDL0R register *******************/\r
-#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
-#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
-#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
-#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
-\r
-/****************** Bit definition for CAN_TDH0R register *******************/\r
-#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
-#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
-#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
-#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
-\r
-/******************* Bit definition for CAN_TI1R register *******************/\r
-#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
-#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
-#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
-#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
-#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
-\r
-/******************* Bit definition for CAN_TDT1R register ******************/\r
-#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
-#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
-#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
-\r
-/******************* Bit definition for CAN_TDL1R register ******************/\r
-#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
-#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
-#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
-#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
-\r
-/******************* Bit definition for CAN_TDH1R register ******************/\r
-#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
-#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
-#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
-#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
-\r
-/******************* Bit definition for CAN_TI2R register *******************/\r
-#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
-#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
-#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
-#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */\r
-#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
-\r
-/******************* Bit definition for CAN_TDT2R register ******************/ \r
-#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
-#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
-#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
-\r
-/******************* Bit definition for CAN_TDL2R register ******************/\r
-#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
-#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
-#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
-#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
-\r
-/******************* Bit definition for CAN_TDH2R register ******************/\r
-#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
-#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
-#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
-#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
-\r
-/******************* Bit definition for CAN_RI0R register *******************/\r
-#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
-#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
-#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
-#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
-\r
-/******************* Bit definition for CAN_RDT0R register ******************/\r
-#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
-#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */\r
-#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
-\r
-/******************* Bit definition for CAN_RDL0R register ******************/\r
-#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
-#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
-#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
-#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
-\r
-/******************* Bit definition for CAN_RDH0R register ******************/\r
-#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
-#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
-#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
-#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
-\r
-/******************* Bit definition for CAN_RI1R register *******************/\r
-#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
-#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
-#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */\r
-#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
-\r
-/******************* Bit definition for CAN_RDT1R register ******************/\r
-#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
-#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */\r
-#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
-\r
-/******************* Bit definition for CAN_RDL1R register ******************/\r
-#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
-#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
-#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
-#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
-\r
-/******************* Bit definition for CAN_RDH1R register ******************/\r
-#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
-#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
-#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
-#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
-\r
-/*!<CAN filter registers */\r
-/******************* Bit definition for CAN_FMR register ********************/\r
-#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */\r
-\r
-/******************* Bit definition for CAN_FM1R register *******************/\r
-#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */\r
-#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */\r
-#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */\r
-#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */\r
-#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */\r
-#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */\r
-#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */\r
-#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */\r
-#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */\r
-#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */\r
-#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */\r
-#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */\r
-#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */\r
-#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */\r
-#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */\r
-\r
-/******************* Bit definition for CAN_FS1R register *******************/\r
-#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */\r
-#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */\r
-#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */\r
-#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */\r
-#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */\r
-#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */\r
-#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */\r
-#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */\r
-#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */\r
-#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */\r
-#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */\r
-#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */\r
-#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */\r
-#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */\r
-#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */\r
-\r
-/****************** Bit definition for CAN_FFA1R register *******************/\r
-#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */\r
-#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */\r
-#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */\r
-#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */\r
-#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */\r
-#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */\r
-#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */\r
-#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */\r
-#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */\r
-#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */\r
-#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */\r
-#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */\r
-#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */\r
-#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */\r
-#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */\r
-\r
-/******************* Bit definition for CAN_FA1R register *******************/\r
-#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */\r
-#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */\r
-#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */\r
-#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */\r
-#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */\r
-#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */\r
-#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */\r
-#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */\r
-#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */\r
-#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */\r
-#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */\r
-#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */\r
-#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */\r
-#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */\r
-#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */\r
-\r
-/******************* Bit definition for CAN_F0R1 register *******************/\r
-#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F1R1 register *******************/\r
-#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F2R1 register *******************/\r
-#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F3R1 register *******************/\r
-#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F4R1 register *******************/\r
-#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F5R1 register *******************/\r
-#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F6R1 register *******************/\r
-#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F7R1 register *******************/\r
-#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F8R1 register *******************/\r
-#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F9R1 register *******************/\r
-#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F10R1 register ******************/\r
-#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F11R1 register ******************/\r
-#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F12R1 register ******************/\r
-#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F13R1 register ******************/\r
-#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F0R2 register *******************/\r
-#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F1R2 register *******************/\r
-#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F2R2 register *******************/\r
-#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F3R2 register *******************/\r
-#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F4R2 register *******************/\r
-#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F5R2 register *******************/\r
-#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F6R2 register *******************/\r
-#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F7R2 register *******************/\r
-#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F8R2 register *******************/\r
-#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F9R2 register *******************/\r
-#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F10R2 register ******************/\r
-#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F11R2 register ******************/\r
-#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F12R2 register ******************/\r
-#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F13R2 register ******************/\r
-#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Serial Peripheral Interface */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for SPI_CR1 register ********************/\r
-#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */\r
-#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */\r
-#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */\r
-\r
-#define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */\r
-#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */\r
-#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */\r
-#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */\r
-\r
-#define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */\r
-#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */\r
-#define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */\r
-#define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */\r
-#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */\r
-#define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */\r
-#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */\r
-#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */\r
-#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */\r
-#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */\r
-\r
-/******************* Bit definition for SPI_CR2 register ********************/\r
-#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */\r
-#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */\r
-#define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */\r
-#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */\r
-#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */\r
-#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */\r
-\r
-/******************** Bit definition for SPI_SR register ********************/\r
-#define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */\r
-#define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */\r
-#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */\r
-#define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */\r
-#define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */\r
-#define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */\r
-#define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */\r
-#define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */\r
-\r
-/******************** Bit definition for SPI_DR register ********************/\r
-#define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */\r
-\r
-/******************* Bit definition for SPI_CRCPR register ******************/\r
-#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */\r
-\r
-/****************** Bit definition for SPI_RXCRCR register ******************/\r
-#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */\r
-\r
-/****************** Bit definition for SPI_TXCRCR register ******************/\r
-#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */\r
-\r
-/****************** Bit definition for SPI_I2SCFGR register *****************/\r
-#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */\r
-\r
-#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */\r
-#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */\r
-#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */\r
-\r
-#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */\r
-\r
-#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */\r
-#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-\r
-#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */\r
-\r
-#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */\r
-#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-\r
-#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */\r
-#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */\r
-\r
-/****************** Bit definition for SPI_I2SPR register *******************/\r
-#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */\r
-#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */\r
-#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Inter-integrated Circuit Interface */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for I2C_CR1 register ********************/\r
-#define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */\r
-#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */\r
-#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */\r
-#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */\r
-#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */\r
-#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */\r
-#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */\r
-#define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */\r
-#define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */\r
-#define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */\r
-#define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */\r
-#define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */\r
-#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */\r
-#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */\r
-\r
-/******************* Bit definition for I2C_CR2 register ********************/\r
-#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */\r
-#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
-#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
-#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
-#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */\r
-\r
-#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */\r
-#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */\r
-#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */\r
-#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */\r
-#define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */\r
-\r
-/******************* Bit definition for I2C_OAR1 register *******************/\r
-#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */\r
-#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */\r
-\r
-#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */\r
-#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */\r
-#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */\r
-#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */\r
-#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */\r
-#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */\r
-#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */\r
-#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */\r
-\r
-#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */\r
-\r
-/******************* Bit definition for I2C_OAR2 register *******************/\r
-#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */\r
-#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */\r
-\r
-/******************** Bit definition for I2C_DR register ********************/\r
-#define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */\r
-\r
-/******************* Bit definition for I2C_SR1 register ********************/\r
-#define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */\r
-#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */\r
-#define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */\r
-#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */\r
-#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */\r
-#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */\r
-#define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */\r
-#define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */\r
-#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */\r
-#define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */\r
-#define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */\r
-#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */\r
-#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */\r
-#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */\r
-\r
-/******************* Bit definition for I2C_SR2 register ********************/\r
-#define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */\r
-#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */\r
-#define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */\r
-#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */\r
-#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */\r
-#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */\r
-#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */\r
-#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */\r
-\r
-/******************* Bit definition for I2C_CCR register ********************/\r
-#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */\r
-#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */\r
-#define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */\r
-\r
-/****************** Bit definition for I2C_TRISE register *******************/\r
-#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Universal Synchronous Asynchronous Receiver Transmitter */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for USART_SR register *******************/\r
-#define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */\r
-#define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */\r
-#define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */\r
-#define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */\r
-#define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */\r
-#define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */\r
-#define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */\r
-#define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */\r
-#define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */\r
-#define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */\r
-\r
-/******************* Bit definition for USART_DR register *******************/\r
-#define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */\r
-\r
-/****************** Bit definition for USART_BRR register *******************/\r
-#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */\r
-#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */\r
-\r
-/****************** Bit definition for USART_CR1 register *******************/\r
-#define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */\r
-#define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */\r
-#define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */\r
-#define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */\r
-#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */\r
-#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */\r
-#define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */\r
-#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */\r
-#define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */\r
-#define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */\r
-#define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */\r
-#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */\r
-#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */\r
-#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */\r
-#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversmapling 8-bits */\r
-\r
-/****************** Bit definition for USART_CR2 register *******************/\r
-#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */\r
-#define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */\r
-#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */\r
-#define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */\r
-#define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */\r
-#define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */\r
-#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */\r
-\r
-#define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */\r
-#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */\r
-\r
-/****************** Bit definition for USART_CR3 register *******************/\r
-#define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */\r
-#define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */\r
-#define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */\r
-#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */\r
-#define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */\r
-#define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */\r
-#define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */\r
-#define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */\r
-#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */\r
-#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */\r
-#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */\r
-#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<One Bit method */\r
-\r
-/****************** Bit definition for USART_GTPR register ******************/\r
-#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */\r
-#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
-#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
-#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
-#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */\r
-#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */\r
-#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */\r
-\r
-#define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Debug MCU */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/**************** Bit definition for DBGMCU_IDCODE register *****************/\r
-#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!<Device Identifier */\r
-\r
-#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!<REV_ID[15:0] bits (Revision Identifier) */\r
-#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!<Bit 8 */\r
-#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!<Bit 9 */\r
-#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!<Bit 10 */\r
-#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!<Bit 11 */\r
-#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!<Bit 12 */\r
-#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!<Bit 13 */\r
-#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!<Bit 14 */\r
-#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!<Bit 15 */\r
-\r
-/****************** Bit definition for DBGMCU_CR register *******************/\r
-#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!<Debug Sleep Mode */\r
-#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!<Debug Stop Mode */\r
-#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!<Debug Standby mode */\r
-#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!<Trace Pin Assignment Control */\r
-\r
-#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!<TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */\r
-#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
-#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
-\r
-#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!<Debug Independent Watchdog stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!<Debug Window Watchdog stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!<TIM1 counter stopped when core is halted */\r
-#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!<TIM2 counter stopped when core is halted */\r
-#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!<TIM3 counter stopped when core is halted */\r
-#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!<TIM4 counter stopped when core is halted */\r
-#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!<Debug CAN1 stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!<SMBUS timeout mode stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!<SMBUS timeout mode stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!<TIM8 counter stopped when core is halted */\r
-#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!<TIM5 counter stopped when core is halted */\r
-#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!<TIM6 counter stopped when core is halted */\r
-#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!<TIM7 counter stopped when core is halted */\r
-#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!<Debug CAN2 stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!<Debug TIM15 stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!<Debug TIM16 stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!<Debug TIM17 stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!<Debug TIM12 stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!<Debug TIM13 stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!<Debug TIM14 stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!<Debug TIM9 stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!<Debug TIM10 stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!<Debug TIM11 stopped when Core is halted */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* FLASH and Option Bytes Registers */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for FLASH_ACR register ******************/\r
-#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!<LATENCY[2:0] bits (Latency) */\r
-#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!<Bit 0 */\r
-#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!<Bit 0 */\r
-#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!<Bit 1 */\r
-\r
-#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!<Flash Half Cycle Access Enable */\r
-#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!<Prefetch Buffer Enable */\r
-#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!<Prefetch Buffer Status */\r
-\r
-/****************** Bit definition for FLASH_KEYR register ******************/\r
-#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!<FPEC Key */\r
-\r
-/***************** Bit definition for FLASH_OPTKEYR register ****************/\r
-#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!<Option Byte Key */\r
-\r
-/****************** Bit definition for FLASH_SR register *******************/\r
-#define FLASH_SR_BSY ((uint8_t)0x01) /*!<Busy */\r
-#define FLASH_SR_PGERR ((uint8_t)0x04) /*!<Programming Error */\r
-#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!<Write Protection Error */\r
-#define FLASH_SR_EOP ((uint8_t)0x20) /*!<End of operation */\r
-\r
-/******************* Bit definition for FLASH_CR register *******************/\r
-#define FLASH_CR_PG ((uint16_t)0x0001) /*!<Programming */\r
-#define FLASH_CR_PER ((uint16_t)0x0002) /*!<Page Erase */\r
-#define FLASH_CR_MER ((uint16_t)0x0004) /*!<Mass Erase */\r
-#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!<Option Byte Programming */\r
-#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!<Option Byte Erase */\r
-#define FLASH_CR_STRT ((uint16_t)0x0040) /*!<Start */\r
-#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!<Lock */\r
-#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!<Option Bytes Write Enable */\r
-#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!<Error Interrupt Enable */\r
-#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!<End of operation interrupt enable */\r
-\r
-/******************* Bit definition for FLASH_AR register *******************/\r
-#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!<Flash Address */\r
-\r
-/****************** Bit definition for FLASH_OBR register *******************/\r
-#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!<Option Byte Error */\r
-#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!<Read protection */\r
-\r
-#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!<User Option Bytes */\r
-#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!<WDG_SW */\r
-#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!<nRST_STOP */\r
-#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!<nRST_STDBY */\r
-#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!<BFB2 */\r
-\r
-/****************** Bit definition for FLASH_WRPR register ******************/\r
-#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!<Write Protect */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/****************** Bit definition for FLASH_RDP register *******************/\r
-#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!<Read protection option byte */\r
-#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!<Read protection complemented option byte */\r
-\r
-/****************** Bit definition for FLASH_USER register ******************/\r
-#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!<User option byte */\r
-#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!<User complemented option byte */\r
-\r
-/****************** Bit definition for FLASH_Data0 register *****************/\r
-#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!<User data storage option byte */\r
-#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!<User data storage complemented option byte */\r
-\r
-/****************** Bit definition for FLASH_Data1 register *****************/\r
-#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!<User data storage option byte */\r
-#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!<User data storage complemented option byte */\r
-\r
-/****************** Bit definition for FLASH_WRP0 register ******************/\r
-#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */\r
-#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */\r
-\r
-/****************** Bit definition for FLASH_WRP1 register ******************/\r
-#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */\r
-#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */\r
-\r
-/****************** Bit definition for FLASH_WRP2 register ******************/\r
-#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */\r
-#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */\r
-\r
-/****************** Bit definition for FLASH_WRP3 register ******************/\r
-#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */\r
-#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */\r
-\r
-#ifdef STM32F10X_CL\r
-/******************************************************************************/\r
-/* Ethernet MAC Registers bits definitions */\r
-/******************************************************************************/\r
-/* Bit definition for Ethernet MAC Control Register register */\r
-#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */\r
-#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */\r
-#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */\r
- #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */\r
- #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */\r
- #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */\r
- #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */\r
- #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ \r
- #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */\r
- #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */\r
- #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ \r
-#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */\r
-#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */\r
-#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */\r
-#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */\r
-#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */\r
-#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */\r
-#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */\r
-#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */\r
-#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling\r
- a transmission attempt during retries after a collision: 0 =< r <2^k */\r
- #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */\r
- #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */\r
- #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */\r
- #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ \r
-#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */\r
-#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */\r
-#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */\r
-\r
-/* Bit definition for Ethernet MAC Frame Filter Register */\r
-#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ \r
-#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ \r
-#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ \r
-#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ \r
-#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */\r
- #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */\r
- #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */\r
- #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ \r
-#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ \r
-#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ \r
-#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ \r
-#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ \r
-#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */\r
-#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */\r
-\r
-/* Bit definition for Ethernet MAC Hash Table High Register */\r
-#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */\r
-\r
-/* Bit definition for Ethernet MAC Hash Table Low Register */\r
-#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */\r
-\r
-/* Bit definition for Ethernet MAC MII Address Register */\r
-#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ \r
-#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ \r
-#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ \r
- #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */\r
- #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */\r
- #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */\r
-#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ \r
-#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ \r
- \r
-/* Bit definition for Ethernet MAC MII Data Register */\r
-#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */\r
-\r
-/* Bit definition for Ethernet MAC Flow Control Register */\r
-#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */\r
-#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */\r
-#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */\r
- #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */\r
- #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */\r
- #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */\r
- #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ \r
-#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */\r
-#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */\r
-#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */\r
-#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */\r
-\r
-/* Bit definition for Ethernet MAC VLAN Tag Register */\r
-#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */\r
-#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */\r
-\r
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ \r
-#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */\r
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.\r
- Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */\r
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask\r
- Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask\r
- Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask\r
- Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask\r
- Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - \r
- RSVD - Filter1 Command - RSVD - Filter0 Command\r
- Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset\r
- Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16\r
- Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */\r
-\r
-/* Bit definition for Ethernet MAC PMT Control and Status Register */ \r
-#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */\r
-#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */\r
-#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */\r
-#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */\r
-#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */\r
-#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */\r
-#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */\r
-\r
-/* Bit definition for Ethernet MAC Status Register */\r
-#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */\r
-#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */\r
-#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */\r
-#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */\r
-#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */\r
-\r
-/* Bit definition for Ethernet MAC Interrupt Mask Register */\r
-#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */\r
-#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */\r
-\r
-/* Bit definition for Ethernet MAC Address0 High Register */\r
-#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */\r
-\r
-/* Bit definition for Ethernet MAC Address0 Low Register */\r
-#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */\r
-\r
-/* Bit definition for Ethernet MAC Address1 High Register */\r
-#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */\r
-#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */\r
-#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\r
- #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
- #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
- #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
- #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
- #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
- #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ \r
-#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */\r
-\r
-/* Bit definition for Ethernet MAC Address1 Low Register */\r
-#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */\r
-\r
-/* Bit definition for Ethernet MAC Address2 High Register */\r
-#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */\r
-#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */\r
-#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */\r
- #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
- #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
- #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
- #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
- #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
- #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */\r
-#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */\r
-\r
-/* Bit definition for Ethernet MAC Address2 Low Register */\r
-#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */\r
-\r
-/* Bit definition for Ethernet MAC Address3 High Register */\r
-#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */\r
-#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */\r
-#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */\r
- #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
- #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
- #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
- #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
- #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
- #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */\r
-#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */\r
-\r
-/* Bit definition for Ethernet MAC Address3 Low Register */\r
-#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */\r
-\r
-/******************************************************************************/\r
-/* Ethernet MMC Registers bits definition */\r
-/******************************************************************************/\r
-\r
-/* Bit definition for Ethernet MMC Contol Register */\r
-#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */\r
-#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */\r
-#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */\r
-#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */\r
-\r
-/* Bit definition for Ethernet MMC Receive Interrupt Register */\r
-#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */\r
-#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */\r
-#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */\r
-\r
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */\r
-#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */\r
-#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */\r
-#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */\r
-\r
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */\r
-#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */\r
-#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */\r
-#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */\r
-\r
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */\r
-#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */\r
-#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */\r
-#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */\r
-\r
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */\r
-#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */\r
-\r
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */\r
-#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */\r
-\r
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */\r
-#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */\r
-\r
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */\r
-#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */\r
-\r
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */\r
-#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */\r
-\r
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */\r
-#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */\r
-\r
-/******************************************************************************/\r
-/* Ethernet PTP Registers bits definition */\r
-/******************************************************************************/\r
-\r
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */\r
-#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */\r
-#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */\r
-#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */\r
-#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */\r
-#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */\r
-#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */\r
-\r
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */\r
-#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */\r
-\r
-/* Bit definition for Ethernet PTP Time Stamp High Register */\r
-#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */\r
-\r
-/* Bit definition for Ethernet PTP Time Stamp Low Register */\r
-#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */\r
-#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */\r
-\r
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */\r
-#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */\r
-\r
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */\r
-#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */\r
-#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */\r
-\r
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */\r
-#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */\r
-\r
-/* Bit definition for Ethernet PTP Target Time High Register */\r
-#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */\r
-\r
-/* Bit definition for Ethernet PTP Target Time Low Register */\r
-#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */\r
-\r
-/******************************************************************************/\r
-/* Ethernet DMA Registers bits definition */\r
-/******************************************************************************/\r
-\r
-/* Bit definition for Ethernet DMA Bus Mode Register */\r
-#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */\r
-#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */\r
-#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */\r
-#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */\r
- #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
- #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
- #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
- #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
- #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
- #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ \r
- #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
- #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
- #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
- #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
- #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
- #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ \r
-#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */\r
-#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */\r
- #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */\r
- #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */\r
- #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */\r
- #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ \r
-#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */\r
- #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
- #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
- #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
- #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
- #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
- #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ \r
- #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
- #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
- #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
- #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
- #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
- #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
-#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */\r
-#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */\r
-#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */\r
-\r
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */\r
-#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */\r
-\r
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */\r
-#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */\r
-\r
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */\r
-#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */\r
-\r
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */\r
-#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */\r
-\r
-/* Bit definition for Ethernet DMA Status Register */\r
-#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */\r
-#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */\r
-#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */\r
-#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */\r
- /* combination with EBS[2:0] for GetFlagStatus function */\r
- #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */\r
- #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */\r
- #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */\r
-#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */\r
- #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */\r
- #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */\r
- #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */\r
- #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */\r
- #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */\r
- #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */\r
-#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */\r
- #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */\r
- #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */\r
- #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */\r
- #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */\r
- #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */\r
- #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */\r
-#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */\r
-#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */\r
-#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */\r
-#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */\r
-#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */\r
-#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */\r
-#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */\r
-#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */\r
-#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */\r
-#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */\r
-#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */\r
-#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */\r
-#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */\r
-#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */\r
-#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */\r
-\r
-/* Bit definition for Ethernet DMA Operation Mode Register */\r
-#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */\r
-#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */\r
-#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */\r
-#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */\r
-#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */\r
-#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */\r
- #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */\r
- #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */\r
- #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */\r
- #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */\r
- #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */\r
- #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */\r
- #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */\r
- #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */\r
-#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */\r
-#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */\r
-#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */\r
-#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */\r
- #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */\r
- #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */\r
- #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */\r
- #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */\r
-#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */\r
-#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */\r
-\r
-/* Bit definition for Ethernet DMA Interrupt Enable Register */\r
-#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */\r
-#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */\r
-#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */\r
-#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */\r
-#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */\r
-#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */\r
-#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */\r
-#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */\r
-#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */\r
-#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */\r
-#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */\r
-#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */\r
-#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */\r
-#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */\r
-#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */\r
-\r
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */\r
-#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */\r
-#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */\r
-#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */\r
-#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */\r
-\r
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */\r
-#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */\r
-\r
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */\r
-#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */\r
-\r
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */\r
-#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */\r
-\r
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */\r
-#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */\r
-#endif /* STM32F10X_CL */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
- /**\r
- * @}\r
- */ \r
-\r
-#ifdef USE_STDPERIPH_DRIVER\r
- #include "stm32f10x_conf.h"\r
-#endif\r
-\r
-/** @addtogroup Exported_macro\r
- * @{\r
- */\r
-\r
-#define SET_BIT(REG, BIT) ((REG) |= (BIT))\r
-\r
-#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))\r
-\r
-#define READ_BIT(REG, BIT) ((REG) & (BIT))\r
-\r
-#define CLEAR_REG(REG) ((REG) = (0x0))\r
-\r
-#define WRITE_REG(REG, VAL) ((REG) = (VAL))\r
-\r
-#define READ_REG(REG) ((REG))\r
-\r
-#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
- /**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. \r
- * This file contains all the peripheral register's definitions, bits \r
- * definitions and memory mapping for STM32L1xx devices. \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ******************************************************************************\r
- */\r
-\r
-/** @addtogroup CMSIS\r
- * @{\r
- */\r
-\r
-/** @addtogroup stm32l1xx\r
- * @{\r
- */\r
- \r
-#ifndef __STM32L1XX_H\r
-#define __STM32L1XX_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-#define assert_param(__p)\r
- \r
-/** @addtogroup Library_configuration_section\r
- * @{\r
- */\r
- \r
-/* Uncomment the line below according to the target STM32L device used in your \r
- application \r
- */\r
-\r
-#if !defined (STM32L1XX_MD)\r
- #define STM32L1XX_MD /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */\r
-#endif\r
-/* Tip: To avoid modifying this file each time you need to switch between these\r
- devices, you can define the device in your toolchain compiler preprocessor.\r
-\r
- - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx \r
- microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\r
-\r
- */\r
-\r
-#if !defined (STM32L1XX_MD)\r
- #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"\r
-#endif\r
-\r
-#if !defined USE_STDPERIPH_DRIVER\r
-/**\r
- * @brief Comment the line below if you will not use the peripherals drivers.\r
- In this case, these drivers will not be included and the application code will \r
- be based on direct access to peripherals registers \r
- */\r
- /*#define USE_STDPERIPH_DRIVER*/\r
-#endif\r
-\r
-/**\r
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)\r
- used in your application \r
- \r
- Tip: To avoid modifying this file each time you need to use different HSE, you\r
- can define the HSE value in your toolchain compiler preprocessor.\r
- */ \r
-#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/\r
-\r
-/**\r
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup \r
- Timeout value \r
- */\r
-#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */\r
-\r
-/**\r
- * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup \r
- Timeout value \r
- */\r
-#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */\r
-\r
-#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz.\r
- The real value may vary depending on the variations\r
- in voltage and temperature. */\r
-#define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz\r
- The real value may vary depending on the variations\r
- in voltage and temperature. */\r
-#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */\r
-\r
-/**\r
- * @brief STM32L1xx Standard Peripheral Library version number\r
- */\r
-#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ \r
-#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */\r
-#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\r
-#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ \r
-#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\\r
- |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\\r
- |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\\r
- |(__STM32L1XX_STDPERIPH_VERSION_RC))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup Configuration_section_for_CMSIS\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device \r
- * in @ref Library_configuration_section \r
- */\r
-#define __MPU_PRESENT 1 /*!< STM32L provides MPU */\r
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */\r
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
-\r
-/*!< Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** STM32L specific Interrupt Numbers ***********************************************************/\r
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
- PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r
- TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */\r
- RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */\r
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
- RCC_IRQn = 5, /*!< RCC global Interrupt */\r
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
- DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */\r
- DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */\r
- DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */\r
- DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */\r
- DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */\r
- DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */\r
- DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */\r
- ADC1_IRQn = 18, /*!< ADC1 global Interrupt */\r
- USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */\r
- USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */\r
- DAC_IRQn = 21, /*!< DAC Interrupt */\r
- COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */\r
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
- LCD_IRQn = 24, /*!< LCD Interrupt */\r
- TIM9_IRQn = 25, /*!< TIM9 global Interrupt */\r
- TIM10_IRQn = 26, /*!< TIM10 global Interrupt */\r
- TIM11_IRQn = 27, /*!< TIM11 global Interrupt */\r
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
- USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
- USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
- USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
- USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */\r
- TIM6_IRQn = 43, /*!< TIM6 global Interrupt */\r
- TIM7_IRQn = 44 /*!< TIM7 global Interrupt */\r
-} IRQn_Type;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#include "core_cm3.h"\r
-#include "system_stm32l1xx.h"\r
-#include <stdint.h>\r
-\r
-/** @addtogroup Exported_types\r
- * @{\r
- */ \r
-\r
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\r
-\r
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
-\r
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
-\r
-/** \r
- * @brief __RAM_FUNC definition \r
- */ \r
-#if defined ( __CC_ARM )\r
-/* ARM Compiler\r
- ------------\r
- RAM functions are defined using the toolchain options. \r
- Functions that are executed in RAM should reside in a separate source \r
- module. Using the 'Options for File' dialog you can simply change the \r
- 'Code / Const' area of a module to a memory space in physical RAM.\r
- Available memory areas are declared in the 'Target' tab of the \r
- 'Options for Target' dialog. \r
-*/\r
- #define __RAM_FUNC FLASH_Status \r
-\r
-#elif defined ( __ICCARM__ )\r
-/* ICCARM Compiler\r
- ---------------\r
- RAM functions are defined using a specific toolchain keyword "__ramfunc". \r
-*/\r
- #define __RAM_FUNC __ramfunc FLASH_Status\r
-\r
-#elif defined ( __GNUC__ )\r
-/* GNU Compiler\r
- ------------\r
- RAM functions are defined using a specific toolchain attribute \r
- "__attribute__((section(".data")))". \r
-*/\r
- #define __RAM_FUNC FLASH_Status __attribute__((section(".data")))\r
-\r
-#elif defined ( __TASKING__ )\r
-/* TASKING Compiler\r
- ----------------\r
- RAM functions are defined using a specific toolchain pragma. This pragma is \r
- defined in the stm32l1xx_flash_ramfunc.c \r
-*/\r
- #define __RAM_FUNC FLASH_Status\r
-\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup Peripheral_registers_structures\r
- * @{\r
- */ \r
-\r
-/** \r
- * @brief Analog to Digital Converter \r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t SR;\r
- __IO uint32_t CR1;\r
- __IO uint32_t CR2;\r
- __IO uint32_t SMPR1;\r
- __IO uint32_t SMPR2;\r
- __IO uint32_t SMPR3;\r
- __IO uint32_t JOFR1;\r
- __IO uint32_t JOFR2;\r
- __IO uint32_t JOFR3;\r
- __IO uint32_t JOFR4;\r
- __IO uint32_t HTR;\r
- __IO uint32_t LTR;\r
- __IO uint32_t SQR1;\r
- __IO uint32_t SQR2;\r
- __IO uint32_t SQR3;\r
- __IO uint32_t SQR4;\r
- __IO uint32_t SQR5;\r
- __IO uint32_t JSQR;\r
- __IO uint32_t JDR1;\r
- __IO uint32_t JDR2;\r
- __IO uint32_t JDR3;\r
- __IO uint32_t JDR4;\r
- __IO uint32_t DR;\r
-} ADC_TypeDef;\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CSR;\r
- __IO uint32_t CCR;\r
-} ADC_Common_TypeDef;\r
-\r
-\r
-/** \r
- * @brief Comparator \r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CSR;\r
-} COMP_TypeDef;\r
-\r
-/** \r
- * @brief CRC calculation unit \r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t DR;\r
- __IO uint8_t IDR;\r
- uint8_t RESERVED0;\r
- uint16_t RESERVED1;\r
- __IO uint32_t CR;\r
-} CRC_TypeDef;\r
-\r
-/** \r
- * @brief Digital to Analog Converter\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR;\r
- __IO uint32_t SWTRIGR;\r
- __IO uint32_t DHR12R1;\r
- __IO uint32_t DHR12L1;\r
- __IO uint32_t DHR8R1;\r
- __IO uint32_t DHR12R2;\r
- __IO uint32_t DHR12L2;\r
- __IO uint32_t DHR8R2;\r
- __IO uint32_t DHR12RD;\r
- __IO uint32_t DHR12LD;\r
- __IO uint32_t DHR8RD;\r
- __IO uint32_t DOR1;\r
- __IO uint32_t DOR2;\r
- __IO uint32_t SR; \r
-} DAC_TypeDef;\r
-\r
-/** \r
- * @brief Debug MCU\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t IDCODE;\r
- __IO uint32_t CR;\r
- __IO uint32_t APB1FZ;\r
- __IO uint32_t APB2FZ; \r
-}DBGMCU_TypeDef;\r
-\r
-/** \r
- * @brief DMA Controller\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CCR;\r
- __IO uint32_t CNDTR;\r
- __IO uint32_t CPAR;\r
- __IO uint32_t CMAR;\r
-} DMA_Channel_TypeDef;\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t ISR;\r
- __IO uint32_t IFCR;\r
-} DMA_TypeDef;\r
-\r
-/** \r
- * @brief External Interrupt/Event Controller\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t IMR;\r
- __IO uint32_t EMR;\r
- __IO uint32_t RTSR;\r
- __IO uint32_t FTSR;\r
- __IO uint32_t SWIER;\r
- __IO uint32_t PR;\r
-} EXTI_TypeDef;\r
-\r
-/** \r
- * @brief FLASH Registers\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t ACR;\r
- __IO uint32_t PECR;\r
- __IO uint32_t PDKEYR;\r
- __IO uint32_t PEKEYR;\r
- __IO uint32_t PRGKEYR;\r
- __IO uint32_t OPTKEYR;\r
- __IO uint32_t SR;\r
- __IO uint32_t OBR;\r
- __IO uint32_t WRPR; \r
-} FLASH_TypeDef;\r
-\r
-/** \r
- * @brief Option Bytes Registers\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t RDP;\r
- __IO uint32_t USER;\r
- __IO uint32_t WRP01;\r
- __IO uint32_t WRP23;\r
-} OB_TypeDef;\r
-\r
-/** \r
- * @brief General Purpose IO\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t MODER;\r
- __IO uint16_t OTYPER;\r
- uint16_t RESERVED0;\r
- __IO uint32_t OSPEEDR;\r
- __IO uint32_t PUPDR;\r
- __IO uint16_t IDR;\r
- uint16_t RESERVED1;\r
- __IO uint16_t ODR;\r
- uint16_t RESERVED2;\r
- __IO uint16_t BSRRL; /* BSRR register is split to 2 * 16-bit fields BSRRL */\r
- __IO uint16_t BSRRH; /* BSRR register is split to 2 * 16-bit fields BSRRH */\r
- __IO uint32_t LCKR;\r
- __IO uint32_t AFR[2];\r
-} GPIO_TypeDef;\r
-\r
-/** \r
- * @brief SysTem Configuration\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t MEMRMP;\r
- __IO uint32_t PMC;\r
- __IO uint32_t EXTICR[4];\r
-} SYSCFG_TypeDef;\r
-\r
-/** \r
- * @brief Inter-integrated Circuit Interface\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint16_t CR1;\r
- uint16_t RESERVED0;\r
- __IO uint16_t CR2;\r
- uint16_t RESERVED1;\r
- __IO uint16_t OAR1;\r
- uint16_t RESERVED2;\r
- __IO uint16_t OAR2;\r
- uint16_t RESERVED3;\r
- __IO uint16_t DR;\r
- uint16_t RESERVED4;\r
- __IO uint16_t SR1;\r
- uint16_t RESERVED5;\r
- __IO uint16_t SR2;\r
- uint16_t RESERVED6;\r
- __IO uint16_t CCR;\r
- uint16_t RESERVED7;\r
- __IO uint16_t TRISE;\r
- uint16_t RESERVED8;\r
-} I2C_TypeDef;\r
-\r
-/** \r
- * @brief Independent WATCHDOG\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t KR;\r
- __IO uint32_t PR;\r
- __IO uint32_t RLR;\r
- __IO uint32_t SR;\r
-} IWDG_TypeDef;\r
-\r
-\r
-/** \r
- * @brief LCD\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR;\r
- __IO uint32_t FCR;\r
- __IO uint32_t SR;\r
- __IO uint32_t CLR;\r
- uint32_t RESERVED;\r
- __IO uint32_t RAM[16];\r
-} LCD_TypeDef;\r
-\r
-/** \r
- * @brief Power Control\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR;\r
- __IO uint32_t CSR;\r
-} PWR_TypeDef;\r
-\r
-/** \r
- * @brief Reset and Clock Control\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR;\r
- __IO uint32_t ICSCR;\r
- __IO uint32_t CFGR;\r
- __IO uint32_t CIR;\r
- __IO uint32_t AHBRSTR;\r
- __IO uint32_t APB2RSTR;\r
- __IO uint32_t APB1RSTR;\r
- __IO uint32_t AHBENR;\r
- __IO uint32_t APB2ENR;\r
- __IO uint32_t APB1ENR;\r
- __IO uint32_t AHBLPENR;\r
- __IO uint32_t APB2LPENR;\r
- __IO uint32_t APB1LPENR; \r
- __IO uint32_t CSR; \r
-} RCC_TypeDef;\r
-\r
-/** \r
- * @brief Routing Interface \r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t ICR;\r
- __IO uint32_t ASCR1;\r
- __IO uint32_t ASCR2;\r
- __IO uint32_t HYSCR1;\r
- __IO uint32_t HYSCR2;\r
- __IO uint32_t HYSCR3;\r
-} RI_TypeDef;\r
-\r
-/** \r
- * @brief Real-Time Clock\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t TR;\r
- __IO uint32_t DR;\r
- __IO uint32_t CR;\r
- __IO uint32_t ISR;\r
- __IO uint32_t PRER;\r
- __IO uint32_t WUTR;\r
- __IO uint32_t CALIBR;\r
- __IO uint32_t ALRMAR;\r
- __IO uint32_t ALRMBR;\r
- __IO uint32_t WPR;\r
- uint32_t RESERVED1;\r
- uint32_t RESERVED2;\r
- __IO uint32_t TSTR;\r
- __IO uint32_t TSDR;\r
- uint32_t RESERVED3;\r
- uint32_t RESERVED4;\r
- __IO uint32_t TAFCR;\r
- uint32_t RESERVED5;\r
- uint32_t RESERVED6;\r
- uint32_t RESERVED7;\r
- __IO uint32_t BKP0R;\r
- __IO uint32_t BKP1R;\r
- __IO uint32_t BKP2R;\r
- __IO uint32_t BKP3R;\r
- __IO uint32_t BKP4R;\r
- __IO uint32_t BKP5R;\r
- __IO uint32_t BKP6R;\r
- __IO uint32_t BKP7R;\r
- __IO uint32_t BKP8R;\r
- __IO uint32_t BKP9R;\r
- __IO uint32_t BKP10R;\r
- __IO uint32_t BKP11R;\r
- __IO uint32_t BKP12R;\r
- __IO uint32_t BKP13R;\r
- __IO uint32_t BKP14R;\r
- __IO uint32_t BKP15R;\r
- __IO uint32_t BKP16R;\r
- __IO uint32_t BKP17R;\r
- __IO uint32_t BKP18R;\r
- __IO uint32_t BKP19R;\r
-} RTC_TypeDef;\r
-\r
-/** \r
- * @brief Serial Peripheral Interface\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint16_t CR1;\r
- uint16_t RESERVED0;\r
- __IO uint16_t CR2;\r
- uint16_t RESERVED1;\r
- __IO uint16_t SR;\r
- uint16_t RESERVED2;\r
- __IO uint16_t DR;\r
- uint16_t RESERVED3;\r
- __IO uint16_t CRCPR;\r
- uint16_t RESERVED4;\r
- __IO uint16_t RXCRCR;\r
- uint16_t RESERVED5;\r
- __IO uint16_t TXCRCR;\r
- uint16_t RESERVED6; \r
-} SPI_TypeDef;\r
-\r
-/** \r
- * @brief TIM\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint16_t CR1;\r
- uint16_t RESERVED0;\r
- __IO uint16_t CR2;\r
- uint16_t RESERVED1;\r
- __IO uint16_t SMCR;\r
- uint16_t RESERVED2;\r
- __IO uint16_t DIER;\r
- uint16_t RESERVED3;\r
- __IO uint16_t SR;\r
- uint16_t RESERVED4;\r
- __IO uint16_t EGR;\r
- uint16_t RESERVED5;\r
- __IO uint16_t CCMR1;\r
- uint16_t RESERVED6;\r
- __IO uint16_t CCMR2;\r
- uint16_t RESERVED7;\r
- __IO uint16_t CCER;\r
- uint16_t RESERVED8;\r
- __IO uint16_t CNT;\r
- uint16_t RESERVED9;\r
- __IO uint16_t PSC;\r
- uint16_t RESERVED10;\r
- __IO uint16_t ARR;\r
- uint16_t RESERVED11;\r
- uint32_t RESERVED12;\r
- __IO uint16_t CCR1;\r
- uint16_t RESERVED13;\r
- __IO uint16_t CCR2;\r
- uint16_t RESERVED14;\r
- __IO uint16_t CCR3;\r
- uint16_t RESERVED15;\r
- __IO uint16_t CCR4;\r
- uint16_t RESERVED16;\r
- uint32_t RESERVED17;\r
- __IO uint16_t DCR;\r
- uint16_t RESERVED18;\r
- __IO uint16_t DMAR;\r
- uint16_t RESERVED19;\r
- __IO uint16_t OR;\r
- uint16_t RESERVED20;\r
-} TIM_TypeDef;\r
-\r
-/** \r
- * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint16_t SR;\r
- uint16_t RESERVED0;\r
- __IO uint16_t DR;\r
- uint16_t RESERVED1;\r
- __IO uint16_t BRR;\r
- uint16_t RESERVED2;\r
- __IO uint16_t CR1;\r
- uint16_t RESERVED3;\r
- __IO uint16_t CR2;\r
- uint16_t RESERVED4;\r
- __IO uint16_t CR3;\r
- uint16_t RESERVED5;\r
- __IO uint16_t GTPR;\r
- uint16_t RESERVED6;\r
-} USART_TypeDef;\r
-\r
-/** \r
- * @brief Window WATCHDOG\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR;\r
- __IO uint32_t CFR;\r
- __IO uint32_t SR;\r
-} WWDG_TypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @addtogroup Peripheral_memory_map\r
- * @{\r
- */\r
-\r
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */\r
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */\r
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */\r
-\r
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */\r
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */\r
-\r
-/*!< Peripheral memory map */\r
-#define APB1PERIPH_BASE PERIPH_BASE\r
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)\r
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)\r
-\r
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)\r
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)\r
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)\r
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)\r
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)\r
-#define LCD_BASE (APB1PERIPH_BASE + 0x2400)\r
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)\r
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)\r
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)\r
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)\r
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)\r
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)\r
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)\r
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)\r
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)\r
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)\r
-#define COMP_BASE (APB1PERIPH_BASE + 0x7C00)\r
-#define RI_BASE (APB1PERIPH_BASE + 0x7C04)\r
-\r
-#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000)\r
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)\r
-#define TIM9_BASE (APB2PERIPH_BASE + 0x0800)\r
-#define TIM10_BASE (APB2PERIPH_BASE + 0x0C00)\r
-#define TIM11_BASE (APB2PERIPH_BASE + 0x1000)\r
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)\r
-#define ADC_BASE (APB2PERIPH_BASE + 0x2700)\r
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)\r
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)\r
-\r
-#define GPIOA_BASE (AHBPERIPH_BASE + 0x0000)\r
-#define GPIOB_BASE (AHBPERIPH_BASE + 0x0400)\r
-#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800)\r
-#define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00)\r
-#define GPIOE_BASE (AHBPERIPH_BASE + 0x1000)\r
-#define GPIOH_BASE (AHBPERIPH_BASE + 0x1400)\r
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)\r
-#define RCC_BASE (AHBPERIPH_BASE + 0x3800)\r
-\r
-\r
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */\r
-#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */\r
-\r
-#define DMA1_BASE (AHBPERIPH_BASE + 0x6000)\r
-#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008)\r
-#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C)\r
-#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030)\r
-#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044)\r
-#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058)\r
-#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C)\r
-#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080)\r
-\r
-\r
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @addtogroup Peripheral_declaration\r
- * @{\r
- */ \r
-\r
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
-#define LCD ((LCD_TypeDef *) LCD_BASE)\r
-#define RTC ((RTC_TypeDef *) RTC_BASE)\r
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
-#define USART2 ((USART_TypeDef *) USART2_BASE)\r
-#define USART3 ((USART_TypeDef *) USART3_BASE)\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
-#define PWR ((PWR_TypeDef *) PWR_BASE)\r
-#define DAC ((DAC_TypeDef *) DAC_BASE)\r
-#define COMP ((COMP_TypeDef *) COMP_BASE)\r
-#define RI ((RI_TypeDef *) RI_BASE)\r
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
-\r
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
-#define ADC ((ADC_Common_TypeDef *) ADC_BASE)\r
-#define TIM9 ((TIM_TypeDef *) TIM9_BASE)\r
-#define TIM10 ((TIM_TypeDef *) TIM10_BASE)\r
-#define TIM11 ((TIM_TypeDef *) TIM11_BASE)\r
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)\r
-#define USART1 ((USART_TypeDef *) USART1_BASE)\r
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\r
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\r
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\r
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)\r
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)\r
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)\r
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)\r
-#define RCC ((RCC_TypeDef *) RCC_BASE)\r
-#define CRC ((CRC_TypeDef *) CRC_BASE)\r
-\r
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r
-#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)\r
-\r
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r
-#define OB ((OB_TypeDef *) OB_BASE) \r
-\r
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup Exported_constants\r
- * @{\r
- */\r
- \r
- /** @addtogroup Peripheral_Registers_Bits_Definition\r
- * @{\r
- */\r
- \r
-/******************************************************************************/\r
-/* Peripheral Registers Bits Definition */\r
-/******************************************************************************/\r
-/******************************************************************************/\r
-/* */\r
-/* Analog to Digital Converter (ADC) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************** Bit definition for ADC_SR register ********************/\r
-#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */\r
-#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */\r
-#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */\r
-#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */\r
-#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */\r
-#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */\r
-#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */\r
-#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */\r
-#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */\r
-\r
-/******************* Bit definition for ADC_CR1 register ********************/\r
-#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
-#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
-#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
-#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
-\r
-#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */\r
-#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */\r
-#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */\r
-#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */\r
-#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */\r
-#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */\r
-#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */\r
-#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */\r
-\r
-#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */\r
-#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */\r
-#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */\r
-#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */\r
-\r
-#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */\r
-#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */\r
-\r
-#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */\r
-#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */\r
-\r
-#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */\r
-#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
-#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
-\r
-#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */\r
- \r
-/******************* Bit definition for ADC_CR2 register ********************/\r
-#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */\r
-#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */\r
-\r
-#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */\r
-#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
-#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
-#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
-\r
-#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */\r
-#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */\r
-#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */\r
-#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */\r
-\r
-#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */\r
-#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
-#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
-#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
-#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
-\r
-#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */\r
-#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
-#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
-\r
-#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */\r
-\r
-#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */\r
-#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
-#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
-#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
-#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */\r
-\r
-#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */\r
-#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
-#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
-\r
-#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */\r
-\r
-/****************** Bit definition for ADC_SMPR1 register *******************/\r
-#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */\r
-#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */\r
-#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
-#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
-#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */\r
-#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
-#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
-#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */\r
-#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */\r
-#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */\r
-#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */\r
-#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
-#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
-#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */\r
-#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
-#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
-#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
-\r
-/****************** Bit definition for ADC_SMPR2 register *******************/\r
-#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */\r
-#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */\r
-#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
-#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
-#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */\r
-#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
-#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
-#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */\r
-#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */\r
-#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */\r
-#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */\r
-#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
-#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
-#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */\r
-#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
-#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
-#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */\r
-#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
-#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
-#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */\r
-#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
-#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
-#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */\r
-#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
-#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
-#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */\r
-#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */\r
-#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */\r
-#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */\r
-\r
-/****************** Bit definition for ADC_SMPR3 register *******************/\r
-#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */\r
-#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
- \r
-#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */\r
-#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
-#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
-#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */\r
-#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
-#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
-#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */\r
-#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */\r
-#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */\r
-#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */\r
-#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
-#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
-#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */\r
-#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
-#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
-#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */\r
-#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
-#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
-#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */\r
-#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
-#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
-#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */\r
-#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
-#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
-#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
-\r
-#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */\r
-#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */\r
-#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */\r
-#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */\r
-\r
-\r
-/****************** Bit definition for ADC_JOFR1 register *******************/\r
-#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */\r
-\r
-/****************** Bit definition for ADC_JOFR2 register *******************/\r
-#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */\r
-\r
-/****************** Bit definition for ADC_JOFR3 register *******************/\r
-#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */\r
-\r
-/****************** Bit definition for ADC_JOFR4 register *******************/\r
-#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */\r
-\r
-/******************* Bit definition for ADC_HTR register ********************/\r
-#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */\r
-\r
-/******************* Bit definition for ADC_LTR register ********************/\r
-#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */\r
-\r
-/******************* Bit definition for ADC_SQR1 register *******************/\r
-#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */\r
-#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
-#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
-#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
-\r
-#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */\r
-#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
-#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
-#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
-#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
-#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
-\r
-#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */\r
-#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
-#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
-#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
-\r
-#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */\r
-#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
-#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
-#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
-#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
-\r
-/******************* Bit definition for ADC_SQR2 register *******************/\r
-#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */\r
-#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
-#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
-#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
-\r
-#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */\r
-#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
-#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
-#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
-#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
-#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
-\r
-#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */\r
-#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
-#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
-#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
-\r
-#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */\r
-#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
-#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
-#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
-#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
-#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
-\r
-#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */\r
-#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
-#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
-#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
-#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
-#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */\r
-\r
-#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */\r
-#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */\r
-#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */\r
-#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */\r
-#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */\r
-#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */\r
-\r
-/******************* Bit definition for ADC_SQR3 register *******************/\r
-#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */\r
-#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
-#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
-#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
-\r
-#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */\r
-#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
-#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
-#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
-#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
-#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
-\r
-#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */\r
-#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
-#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
-#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
-\r
-#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */\r
-#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
-#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
-#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
-#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
-#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
-\r
-#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */\r
-#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
-#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
-#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
-#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
-#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */\r
-\r
-#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */\r
-#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */\r
-#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */\r
-#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */\r
-#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */\r
-#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */\r
-\r
-/******************* Bit definition for ADC_SQR4 register *******************/\r
-#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */\r
-#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
-#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
-#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
-\r
-#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */\r
-#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
-#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
-#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
-#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
-#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
-\r
-#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */\r
-#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
-#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
-#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
-\r
-#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */\r
-#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
-#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
-#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
-#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
-#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
-\r
-#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */\r
-#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
-#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
-#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
-#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
-#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */\r
-\r
-#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */\r
-#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */\r
-#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */\r
-#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */\r
-#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */\r
-#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */\r
-\r
-/******************* Bit definition for ADC_SQR5 register *******************/\r
-#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */\r
-#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
-#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
-#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
-\r
-#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */\r
-#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
-#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
-#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
-#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
-#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
-\r
-#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */\r
-#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
-#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
-#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
-\r
-#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */\r
-#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
-#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
-#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
-#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
-#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
-\r
-#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */\r
-#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
-#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
-#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
-#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
-#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */\r
-\r
-#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */\r
-#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */\r
-#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */\r
-#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */\r
-#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */\r
-#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */\r
-\r
-\r
-/******************* Bit definition for ADC_JSQR register *******************/\r
-#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ \r
-#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
-#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
-#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
-\r
-#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */\r
-#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
-#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
-#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
-#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
-#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
-\r
-#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */\r
-#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
-#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
-#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
-\r
-#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */\r
-#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
-#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
-#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
-#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
-#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
-\r
-#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */\r
-#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
-#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
-\r
-/******************* Bit definition for ADC_JDR1 register *******************/\r
-#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */\r
-\r
-/******************* Bit definition for ADC_JDR2 register *******************/\r
-#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */\r
-\r
-/******************* Bit definition for ADC_JDR3 register *******************/\r
-#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */\r
-\r
-/******************* Bit definition for ADC_JDR4 register *******************/\r
-#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */\r
-\r
-/******************** Bit definition for ADC_DR register ********************/\r
-#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */\r
-\r
-\r
-/******************* Bit definition for ADC_CSR register ********************/\r
-#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */\r
-#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */\r
-#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */\r
-#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */\r
-#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */\r
-#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */\r
-#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */\r
-\r
-/******************* Bit definition for ADC_CCR register ********************/\r
-#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/\r
-#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
-#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ \r
-#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Analog Comparators (COMP) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/****************** Bit definition for COMP_CSR register ********************/\r
-#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */\r
-#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */\r
-#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */\r
-#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */\r
-\r
-#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */\r
-#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */\r
-\r
-#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */\r
-#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */\r
-\r
-#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */\r
-#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */\r
-\r
-#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */\r
-#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
-#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
-#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
-\r
-#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */\r
-#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
-#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
-#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* CRC calculation unit (CRC) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for CRC_DR register *********************/\r
-#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */\r
-\r
-/******************* Bit definition for CRC_IDR register ********************/\r
-#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */\r
-\r
-/******************** Bit definition for CRC_CR register ********************/\r
-#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Digital to Analog Converter (DAC) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************** Bit definition for DAC_CR register ********************/\r
-#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */\r
-#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */\r
-#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */\r
-\r
-#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
-#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
-#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
-#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
-\r
-#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r
-#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
-#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
-\r
-#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
-#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */\r
-#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */\r
-#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */\r
-#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */\r
-\r
-#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
-#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */\r
-#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */\r
-#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */\r
-\r
-#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
-#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */\r
-#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */\r
-\r
-#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
-#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */\r
-\r
-/***************** Bit definition for DAC_SWTRIGR register ******************/\r
-#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */\r
-#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */\r
-\r
-/***************** Bit definition for DAC_DHR12R1 register ******************/\r
-#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12L1 register ******************/\r
-#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */\r
-\r
-/****************** Bit definition for DAC_DHR8R1 register ******************/\r
-#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12R2 register ******************/\r
-#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12L2 register ******************/\r
-#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */\r
-\r
-/****************** Bit definition for DAC_DHR8R2 register ******************/\r
-#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12RD register ******************/\r
-#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */\r
-#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12LD register ******************/\r
-#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */\r
-#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */\r
-\r
-/****************** Bit definition for DAC_DHR8RD register ******************/\r
-#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */\r
-#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */\r
-\r
-/******************* Bit definition for DAC_DOR1 register *******************/\r
-#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */\r
-\r
-/******************* Bit definition for DAC_DOR2 register *******************/\r
-#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */\r
-\r
-/******************** Bit definition for DAC_SR register ********************/\r
-#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */\r
-#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Debug MCU (DBGMCU) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/**************** Bit definition for DBGMCU_IDCODE register *****************/\r
-#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */\r
-\r
-#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */\r
-#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
-#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
-#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
-#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
-#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
-#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */\r
-#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */\r
-#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */\r
-#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */\r
-#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */\r
-#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */\r
-#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */\r
-#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */\r
-#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */\r
-#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */\r
-#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */\r
-\r
-/****************** Bit definition for DBGMCU_CR register *******************/\r
-#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */\r
-#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */\r
-#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */\r
-#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */\r
-\r
-#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */\r
-#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
-#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
-\r
-/****************** Bit definition for DBGMCU_APB1_FZ register **************/\r
-\r
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */\r
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */\r
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) /*!< TIM4 counter stopped when core is halted */\r
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */\r
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */\r
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */\r
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */\r
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< SMBUS timeout mode stopped when Core is halted */\r
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) /*!< SMBUS timeout mode stopped when Core is halted */\r
-\r
-/****************** Bit definition for DBGMCU_APB2_FZ register **************/\r
-\r
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) /*!< TIM9 counter stopped when core is halted */\r
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) /*!< TIM10 counter stopped when core is halted */\r
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) /*!< TIM11 counter stopped when core is halted */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* DMA Controller (DMA) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for DMA_ISR register ********************/\r
-#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */\r
-#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */\r
-#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */\r
-#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */\r
-#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */\r
-#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */\r
-#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */\r
-#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */\r
-#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */\r
-#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */\r
-#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */\r
-#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */\r
-#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */\r
-#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */\r
-#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */\r
-#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */\r
-#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */\r
-#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */\r
-#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */\r
-#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */\r
-#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */\r
-#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */\r
-#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */\r
-#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */\r
-#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */\r
-#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */\r
-#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */\r
-#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */\r
-\r
-/******************* Bit definition for DMA_IFCR register *******************/\r
-#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */\r
-#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */\r
-#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */\r
-#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */\r
-#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */\r
-#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */\r
-#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */\r
-#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */\r
-\r
-/******************* Bit definition for DMA_CCR1 register *******************/\r
-#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/\r
-#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
-#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
-#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
-#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
-#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
-#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
-#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
-\r
-#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
-#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
-#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
-\r
-#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
-#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
-#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
-\r
-#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */\r
-#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
-#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
-\r
-#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
-\r
-/******************* Bit definition for DMA_CCR2 register *******************/\r
-#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */\r
-#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */\r
-#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
-#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
-#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
-#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
-#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
-#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
-\r
-#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
-#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
-#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
-\r
-#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
-#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
-#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
-\r
-#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
-#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
-#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
-\r
-#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
-\r
-/******************* Bit definition for DMA_CCR3 register *******************/\r
-#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */\r
-#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
-#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
-#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
-#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
-#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
-#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
-#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
-\r
-#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
-#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
-#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
-\r
-#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
-#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
-#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
-\r
-#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
-#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
-#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
-\r
-#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
-\r
-/*!<****************** Bit definition for DMA_CCR4 register *******************/\r
-#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */\r
-#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
-#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
-#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
-#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
-#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
-#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
-#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
-\r
-#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
-#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
-#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
-\r
-#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
-#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
-#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
-\r
-#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
-#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
-#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
-\r
-#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
-\r
-/****************** Bit definition for DMA_CCR5 register *******************/\r
-#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */\r
-#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
-#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
-#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
-#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
-#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
-#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
-#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
-\r
-#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
-#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
-#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
-\r
-#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
-#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
-#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
-\r
-#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
-#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
-#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
-\r
-#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */\r
-\r
-/******************* Bit definition for DMA_CCR6 register *******************/\r
-#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */\r
-#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
-#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
-#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
-#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
-#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
-#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
-#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
-\r
-#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
-#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
-#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
-\r
-#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
-#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
-#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
-\r
-#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
-#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
-#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
-\r
-#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
-\r
-/******************* Bit definition for DMA_CCR7 register *******************/\r
-#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */\r
-#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
-#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
-#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
-#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
-#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
-#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
-#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
-\r
-#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
-#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
-#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
-\r
-#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
-#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
-#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
-\r
-#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
-#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
-#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
-\r
-#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */\r
-\r
-/****************** Bit definition for DMA_CNDTR1 register ******************/\r
-#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
-\r
-/****************** Bit definition for DMA_CNDTR2 register ******************/\r
-#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
-\r
-/****************** Bit definition for DMA_CNDTR3 register ******************/\r
-#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
-\r
-/****************** Bit definition for DMA_CNDTR4 register ******************/\r
-#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
-\r
-/****************** Bit definition for DMA_CNDTR5 register ******************/\r
-#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
-\r
-/****************** Bit definition for DMA_CNDTR6 register ******************/\r
-#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
-\r
-/****************** Bit definition for DMA_CNDTR7 register ******************/\r
-#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
-\r
-/****************** Bit definition for DMA_CPAR1 register *******************/\r
-#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
-\r
-/****************** Bit definition for DMA_CPAR2 register *******************/\r
-#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
-\r
-/****************** Bit definition for DMA_CPAR3 register *******************/\r
-#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
-\r
-\r
-/****************** Bit definition for DMA_CPAR4 register *******************/\r
-#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
-\r
-/****************** Bit definition for DMA_CPAR5 register *******************/\r
-#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
-\r
-/****************** Bit definition for DMA_CPAR6 register *******************/\r
-#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
-\r
-\r
-/****************** Bit definition for DMA_CPAR7 register *******************/\r
-#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
-\r
-/****************** Bit definition for DMA_CMAR1 register *******************/\r
-#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
-\r
-/****************** Bit definition for DMA_CMAR2 register *******************/\r
-#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
-\r
-/****************** Bit definition for DMA_CMAR3 register *******************/\r
-#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
-\r
-\r
-/****************** Bit definition for DMA_CMAR4 register *******************/\r
-#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
-\r
-/****************** Bit definition for DMA_CMAR5 register *******************/\r
-#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
-\r
-/****************** Bit definition for DMA_CMAR6 register *******************/\r
-#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
-\r
-/****************** Bit definition for DMA_CMAR7 register *******************/\r
-#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* External Interrupt/Event Controller (EXTI) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for EXTI_IMR register *******************/\r
-#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */\r
-#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */\r
-#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */\r
-#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */\r
-#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */\r
-#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */\r
-#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */\r
-#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */\r
-#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */\r
-#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */\r
-#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */\r
-#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */\r
-#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */\r
-#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */\r
-#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */\r
-#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */\r
-#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */\r
-#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */\r
-#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */\r
-#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */\r
-#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */\r
-#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */\r
-#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */\r
-\r
-/******************* Bit definition for EXTI_EMR register *******************/\r
-#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */\r
-#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */\r
-#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */\r
-#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */\r
-#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */\r
-#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */\r
-#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */\r
-#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */\r
-#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */\r
-#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */\r
-#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */\r
-#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */\r
-#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */\r
-#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */\r
-#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */\r
-#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */\r
-#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */\r
-#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */\r
-#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */\r
-#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */\r
-#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */\r
-#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */\r
-#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */\r
-\r
-/****************** Bit definition for EXTI_RTSR register *******************/\r
-#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */\r
-#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */\r
-#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */\r
-#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */\r
-#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */\r
-#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */\r
-#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */\r
-#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */\r
-#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */\r
-#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */\r
-#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */\r
-#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */\r
-#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */\r
-#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */\r
-#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */\r
-#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */\r
-#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */\r
-#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */\r
-#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */\r
-#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */\r
-#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */\r
-#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */\r
-#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */\r
-\r
-/****************** Bit definition for EXTI_FTSR register *******************/\r
-#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */\r
-#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */\r
-#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */\r
-#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */\r
-#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */\r
-#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */\r
-#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */\r
-#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */\r
-#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */\r
-#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */\r
-#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */\r
-#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */\r
-#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */\r
-#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */\r
-#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */\r
-#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */\r
-#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */\r
-#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */\r
-#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */\r
-#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */\r
-#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */\r
-#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */\r
-#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */\r
-\r
-/****************** Bit definition for EXTI_SWIER register ******************/\r
-#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */\r
-#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */\r
-#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */\r
-#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */\r
-#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */\r
-#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */\r
-#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */\r
-#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */\r
-#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */\r
-#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */\r
-#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */\r
-#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */\r
-#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */\r
-#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */\r
-#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */\r
-#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */\r
-#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */\r
-#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */\r
-#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */\r
-#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */\r
-#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */\r
-#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */\r
-#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */\r
-\r
-/******************* Bit definition for EXTI_PR register ********************/\r
-#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */\r
-#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */\r
-#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */\r
-#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */\r
-#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */\r
-#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */\r
-#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */\r
-#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */\r
-#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */\r
-#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */\r
-#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */\r
-#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */\r
-#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */\r
-#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */\r
-#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */\r
-#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */\r
-#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */\r
-#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */\r
-#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit 18 */\r
-#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */\r
-#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */\r
-#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */\r
-#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* FLASH, DATA EEPROM and Option Bytes Registers */\r
-/* (FLASH, DATA_EEPROM, OB) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for FLASH_ACR register ******************/\r
-#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< Latency */\r
-#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */\r
-#define FLASH_ACR_ACC64 ((uint32_t)0x00000004) /*!< Access 64 bits */\r
-#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */\r
-#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */\r
-\r
-/******************* Bit definition for FLASH_PECR register ******************/\r
-#define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */\r
-#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */\r
-#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */\r
-#define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */\r
-#define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */\r
-#define FLASH_PECR_FTDW ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */\r
-#define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */\r
-#define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */\r
-#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */ \r
-#define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */ \r
-#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */ \r
-\r
-/****************** Bit definition for FLASH_PDKEYR register ******************/\r
-#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */\r
-\r
-/****************** Bit definition for FLASH_PEKEYR register ******************/\r
-#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */\r
-\r
-/****************** Bit definition for FLASH_PRGKEYR register ******************/\r
-#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */\r
-\r
-/****************** Bit definition for FLASH_OPTKEYR register ******************/\r
-#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */\r
-\r
-/****************** Bit definition for FLASH_SR register *******************/\r
-#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */\r
-#define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/\r
-#define FLASH_SR_ENHV ((uint32_t)0x00000004) /*!< End of high voltage */\r
-#define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */\r
-\r
-#define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protected error */\r
-#define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */\r
-#define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */\r
-#define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option validity error */\r
-\r
-/****************** Bit definition for FLASH_OBR register *******************/\r
-#define FLASH_OBR_RDPRT ((uint16_t)0x000000AA) /*!< Read Protection */\r
-#define FLASH_OBR_BOR_LEV ((uint16_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/\r
-#define FLASH_OBR_USER ((uint32_t)0x00700000) /*!< User Option Bytes */\r
-#define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */\r
-#define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */\r
-#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */\r
-\r
-/****************** Bit definition for FLASH_WRPR register ******************/\r
-#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* General Purpose IOs (GPIO) */\r
-/* */\r
-/******************************************************************************/\r
-/******************* Bit definition for GPIO_MODER register *****************/ \r
-#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)\r
-#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)\r
-#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)\r
-#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)\r
-#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)\r
-#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)\r
-#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)\r
-#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)\r
-#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)\r
-#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)\r
-#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)\r
-#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)\r
-#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)\r
-#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)\r
-#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)\r
-#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)\r
-#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)\r
-#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)\r
-#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)\r
-#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)\r
-#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)\r
-#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)\r
-#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)\r
-#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)\r
-#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)\r
-#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)\r
-#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)\r
-#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)\r
-#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)\r
-#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)\r
-#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)\r
-#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)\r
-#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)\r
-#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)\r
-#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)\r
-#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)\r
-#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)\r
-#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)\r
-#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)\r
-#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)\r
-#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)\r
-#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)\r
-#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)\r
-#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)\r
-#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)\r
-#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)\r
-#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)\r
-#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)\r
-\r
-/******************* Bit definition for GPIO_OTYPER register ****************/ \r
-#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)\r
-#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)\r
-#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)\r
-#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)\r
-#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)\r
-#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)\r
-#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)\r
-#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)\r
-#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)\r
-#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)\r
-#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)\r
-#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)\r
-#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)\r
-#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)\r
-#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)\r
-#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)\r
-\r
-/******************* Bit definition for GPIO_OSPEEDR register ***************/ \r
-#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)\r
-#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)\r
-#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)\r
-#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)\r
-#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)\r
-#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)\r
-#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)\r
-#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)\r
-#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)\r
-#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)\r
-#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)\r
-#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)\r
-#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)\r
-#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)\r
-#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)\r
-#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)\r
-#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)\r
-#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)\r
-#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)\r
-#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)\r
-#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)\r
-#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)\r
-#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)\r
-#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)\r
-#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)\r
-#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)\r
-#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)\r
-#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)\r
-#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)\r
-#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)\r
-#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)\r
-#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)\r
-#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)\r
-#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)\r
-#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)\r
-#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)\r
-#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)\r
-#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)\r
-#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)\r
-#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)\r
-#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)\r
-#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)\r
-#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)\r
-#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)\r
-#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)\r
-#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)\r
-#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)\r
-#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)\r
-\r
-/******************* Bit definition for GPIO_PUPDR register *****************/ \r
-#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)\r
-#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)\r
-#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)\r
-#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)\r
-#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)\r
-#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)\r
-#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)\r
-#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)\r
-#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)\r
-#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)\r
-#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)\r
-#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)\r
-#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)\r
-#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)\r
-#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)\r
-#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)\r
-#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)\r
-#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)\r
-#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)\r
-#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)\r
-#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)\r
-#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)\r
-#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)\r
-#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)\r
-#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)\r
-#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)\r
-#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)\r
-#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)\r
-#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)\r
-#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)\r
-#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)\r
-#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)\r
-#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)\r
-#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)\r
-#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)\r
-#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)\r
-#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)\r
-#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)\r
-#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)\r
-#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)\r
-#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)\r
-#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)\r
-#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)\r
-#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)\r
-#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)\r
-#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)\r
-#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)\r
-#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)\r
-\r
-/******************* Bit definition for GPIO_IDR register *******************/ \r
-#define GPIO_OTYPER_IDR_0 ((uint32_t)0x00000001)\r
-#define GPIO_OTYPER_IDR_1 ((uint32_t)0x00000002)\r
-#define GPIO_OTYPER_IDR_2 ((uint32_t)0x00000004)\r
-#define GPIO_OTYPER_IDR_3 ((uint32_t)0x00000008)\r
-#define GPIO_OTYPER_IDR_4 ((uint32_t)0x00000010)\r
-#define GPIO_OTYPER_IDR_5 ((uint32_t)0x00000020)\r
-#define GPIO_OTYPER_IDR_6 ((uint32_t)0x00000040)\r
-#define GPIO_OTYPER_IDR_7 ((uint32_t)0x00000080)\r
-#define GPIO_OTYPER_IDR_8 ((uint32_t)0x00000100)\r
-#define GPIO_OTYPER_IDR_9 ((uint32_t)0x00000200)\r
-#define GPIO_OTYPER_IDR_10 ((uint32_t)0x00000400)\r
-#define GPIO_OTYPER_IDR_11 ((uint32_t)0x00000800)\r
-#define GPIO_OTYPER_IDR_12 ((uint32_t)0x00001000)\r
-#define GPIO_OTYPER_IDR_13 ((uint32_t)0x00002000)\r
-#define GPIO_OTYPER_IDR_14 ((uint32_t)0x00004000)\r
-#define GPIO_OTYPER_IDR_15 ((uint32_t)0x00008000)\r
-\r
-/******************* Bit definition for GPIO_ODR register *******************/ \r
-#define GPIO_OTYPER_ODR_0 ((uint32_t)0x00000001)\r
-#define GPIO_OTYPER_ODR_1 ((uint32_t)0x00000002)\r
-#define GPIO_OTYPER_ODR_2 ((uint32_t)0x00000004)\r
-#define GPIO_OTYPER_ODR_3 ((uint32_t)0x00000008)\r
-#define GPIO_OTYPER_ODR_4 ((uint32_t)0x00000010)\r
-#define GPIO_OTYPER_ODR_5 ((uint32_t)0x00000020)\r
-#define GPIO_OTYPER_ODR_6 ((uint32_t)0x00000040)\r
-#define GPIO_OTYPER_ODR_7 ((uint32_t)0x00000080)\r
-#define GPIO_OTYPER_ODR_8 ((uint32_t)0x00000100)\r
-#define GPIO_OTYPER_ODR_9 ((uint32_t)0x00000200)\r
-#define GPIO_OTYPER_ODR_10 ((uint32_t)0x00000400)\r
-#define GPIO_OTYPER_ODR_11 ((uint32_t)0x00000800)\r
-#define GPIO_OTYPER_ODR_12 ((uint32_t)0x00001000)\r
-#define GPIO_OTYPER_ODR_13 ((uint32_t)0x00002000)\r
-#define GPIO_OTYPER_ODR_14 ((uint32_t)0x00004000)\r
-#define GPIO_OTYPER_ODR_15 ((uint32_t)0x00008000)\r
-\r
-/******************* Bit definition for GPIO_BSRR register ******************/ \r
-#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)\r
-#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)\r
-#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)\r
-#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)\r
-#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)\r
-#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)\r
-#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)\r
-#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)\r
-#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)\r
-#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)\r
-#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)\r
-#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)\r
-#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)\r
-#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)\r
-#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)\r
-#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)\r
-#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)\r
-#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)\r
-#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)\r
-#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)\r
-#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)\r
-#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)\r
-#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)\r
-#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)\r
-#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)\r
-#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)\r
-#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)\r
-#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)\r
-#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)\r
-#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)\r
-#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)\r
-#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)\r
-\r
-/******************* Bit definition for GPIO_LCKR register ******************/\r
-#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)\r
-#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)\r
-#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)\r
-#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)\r
-#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)\r
-#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)\r
-#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)\r
-#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)\r
-#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)\r
-#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)\r
-#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)\r
-#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)\r
-#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)\r
-#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)\r
-#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)\r
-#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)\r
-#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)\r
-\r
-/******************* Bit definition for GPIO_AFRL register ******************/\r
-#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)\r
-#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)\r
-#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)\r
-#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)\r
-#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)\r
-#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)\r
-#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)\r
-#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)\r
-\r
-/******************* Bit definition for GPIO_AFRH register ******************/\r
-#define GPIO_AFRH_AFRH8 ((uint32_t)0x0000000F)\r
-#define GPIO_AFRH_AFRH9 ((uint32_t)0x000000F0)\r
-#define GPIO_AFRH_AFRH10 ((uint32_t)0x00000F00)\r
-#define GPIO_AFRH_AFRH11 ((uint32_t)0x0000F000)\r
-#define GPIO_AFRH_AFRH12 ((uint32_t)0x000F0000)\r
-#define GPIO_AFRH_AFRH13 ((uint32_t)0x00F00000)\r
-#define GPIO_AFRH_AFRH14 ((uint32_t)0x0F000000)\r
-#define GPIO_AFRH_AFRH15 ((uint32_t)0xF0000000)\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Inter-integrated Circuit Interface (I2C) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for I2C_CR1 register ********************/\r
-#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */\r
-#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */\r
-#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */\r
-#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */\r
-#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */\r
-#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */\r
-#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */\r
-#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */\r
-#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */\r
-#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */\r
-#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */\r
-#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */\r
-#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */\r
-#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */\r
-\r
-/******************* Bit definition for I2C_CR2 register ********************/\r
-#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */\r
-#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */\r
-#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */\r
-#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */\r
-#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */\r
-#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */\r
-#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */\r
-\r
-#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */\r
-#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */\r
-#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */\r
-#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */\r
-#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */\r
-\r
-/******************* Bit definition for I2C_OAR1 register *******************/\r
-#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */\r
-#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */\r
-\r
-#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */\r
-#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */\r
-#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */\r
-#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */\r
-#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */\r
-#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */\r
-#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */\r
-#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */\r
-#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */\r
-#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */\r
-\r
-#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */\r
-\r
-/******************* Bit definition for I2C_OAR2 register *******************/\r
-#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */\r
-#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */\r
-\r
-/******************** Bit definition for I2C_DR register ********************/\r
-#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */\r
-\r
-/******************* Bit definition for I2C_SR1 register ********************/\r
-#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */\r
-#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */\r
-#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */\r
-#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */\r
-#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */\r
-#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */\r
-#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */\r
-#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */\r
-#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */\r
-#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */\r
-#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */\r
-#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */\r
-#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */\r
-#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */\r
-\r
-/******************* Bit definition for I2C_SR2 register ********************/\r
-#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */\r
-#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */\r
-#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */\r
-#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */\r
-#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */\r
-#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */\r
-#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */\r
-#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */\r
-\r
-/******************* Bit definition for I2C_CCR register ********************/\r
-#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */\r
-#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */\r
-#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */\r
-\r
-/****************** Bit definition for I2C_TRISE register *******************/\r
-#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Independent WATCHDOG (IWDG) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for IWDG_KR register ********************/\r
-#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */\r
-\r
-/******************* Bit definition for IWDG_PR register ********************/\r
-#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */\r
-#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */\r
-#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */\r
-#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */\r
-\r
-/******************* Bit definition for IWDG_RLR register *******************/\r
-#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */\r
-\r
-/******************* Bit definition for IWDG_SR register ********************/\r
-#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */\r
-#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* LCD Controller (LCD) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for LCD_CR register *********************/\r
-#define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */\r
-#define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */\r
-\r
-#define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */\r
-#define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */\r
-#define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */\r
-#define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */\r
-\r
-#define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */\r
-#define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */\r
-#define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */\r
-\r
-#define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /*!< Mux Segment Enable Bit */\r
-\r
-/******************* Bit definition for LCD_FCR register ********************/\r
-#define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */\r
-#define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */\r
-#define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */\r
-\r
-#define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Puls ON Duration) */\r
-#define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
-#define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
-#define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
-\r
-#define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */\r
-#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */\r
-#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */\r
-#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */\r
-\r
-#define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */\r
-#define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-#define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
-\r
-#define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */\r
-#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */\r
-#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */\r
-#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */\r
-\r
-#define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */\r
-#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
-#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
-\r
-#define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */\r
-#define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */\r
-\r
-/******************* Bit definition for LCD_SR register *********************/\r
-#define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */\r
-#define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */\r
-#define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */\r
-#define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */\r
-#define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */\r
-#define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */\r
-\r
-/******************* Bit definition for LCD_CLR register ********************/\r
-#define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */\r
-#define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */\r
-\r
-/******************* Bit definition for LCD_RAM register ********************/\r
-#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Power Control (PWR) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************** Bit definition for PWR_CR register ********************/\r
-#define PWR_CR_LPSDSR ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep/low power run */\r
-#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */\r
-#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */\r
-#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */\r
-#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */\r
-\r
-#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */\r
-#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */\r
-#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */\r
-#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */\r
-\r
-/*!< PVD level configuration */\r
-#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */\r
-#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */\r
-#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */\r
-#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */\r
-#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */\r
-#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */\r
-#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */\r
-#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */\r
-\r
-#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */\r
-#define PWR_CR_ULP ((uint16_t)0x0200) /*!< Ultra Low Power mode */\r
-#define PWR_CR_FWU ((uint16_t)0x0400) /*!< Fast wakeup */\r
-\r
-#define PWR_CR_VOS ((uint16_t)0x1800) /*!< VOS[1:0] bits (Voltage scaling range selection) */\r
-#define PWR_CR_VOS_0 ((uint16_t)0x0800) /*!< Bit 0 */\r
-#define PWR_CR_VOS_1 ((uint16_t)0x1000) /*!< Bit 1 */\r
-#define PWR_CR_LPRUN ((uint16_t)0x4000) /*!< Low power run mode */\r
-\r
-/******************* Bit definition for PWR_CSR register ********************/\r
-#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */\r
-#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */\r
-#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */\r
-#define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready flag */\r
-#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */\r
-#define PWR_CSR_REGLPF ((uint16_t)0x0020) /*!< Regulator LP flag */\r
-\r
-#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */\r
-#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */\r
-#define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Reset and Clock Control (RCC) */\r
-/* */\r
-/******************************************************************************/\r
-/******************** Bit definition for RCC_CR register ********************/\r
-#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */\r
-#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */\r
-\r
-#define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */\r
-#define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */\r
-\r
-#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */\r
-#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */\r
-#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */\r
-\r
-#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */\r
-#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */\r
-#define RCC_CR_CSSON ((uint32_t)0x10000000) /*!< Clock Security System enable */\r
-\r
-#define RCC_CR_RTCPRE ((uint32_t)0x60000000) /*!< RTC/LCD Prescaler */\r
-#define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000) /*!< Bit0 */\r
-#define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000) /*!< Bit1 */\r
-\r
-/******************** Bit definition for RCC_ICSCR register *****************/\r
-#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */\r
-#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */\r
-\r
-#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */\r
-#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */\r
-#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */\r
-#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */\r
-#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */\r
-#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */\r
-#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */\r
-#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */\r
-#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */\r
-#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */\r
-\r
-/******************** Bit definition for RCC_CFGR register ******************/\r
-#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */\r
-#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-\r
-/*!< SW configuration */\r
-#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */\r
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */\r
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */\r
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */\r
-\r
-#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */\r
-#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
-#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
-\r
-/*!< SWS configuration */\r
-#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */\r
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */\r
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */\r
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */\r
-\r
-#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */\r
-#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
-#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
-#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
-#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
-\r
-/*!< HPRE configuration */\r
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */\r
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */\r
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */\r
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */\r
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */\r
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */\r
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */\r
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */\r
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */\r
-\r
-#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */\r
-#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
-#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
-#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
-\r
-/*!< PPRE1 configuration */\r
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */\r
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */\r
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */\r
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */\r
-\r
-#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */\r
-#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */\r
-#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */\r
-#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */\r
-\r
-/*!< PPRE2 configuration */\r
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */\r
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */\r
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */\r
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */\r
-\r
-/*!< PLL entry clock source*/\r
-#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */\r
-\r
-#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */\r
-#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */\r
-\r
-\r
-#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */\r
-#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
-#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
-#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
-#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */\r
-\r
-/*!< PLLMUL configuration */\r
-#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */\r
-#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */\r
-#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */\r
-#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */\r
-#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */\r
-#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */\r
-#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */\r
-#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */\r
-#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */\r
-\r
-/*!< PLLDIV configuration */\r
-#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */\r
-#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */\r
-#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */\r
-\r
-\r
-/*!< PLLDIV configuration */\r
-#define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock output = CKVCO / 1 */\r
-#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */\r
-#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */\r
-#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */\r
-\r
-\r
-#define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */\r
-#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
-#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
-#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
-\r
-/*!< MCO configuration */\r
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected */\r
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */\r
-#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */\r
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */\r
-#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */\r
-#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */\r
-#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */\r
-\r
-#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */\r
-#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
-#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
-#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */\r
-\r
-/*!< MCO Prescaler configuration */\r
-#define RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) /*!< MCO Clock divided by 1 */\r
-#define RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) /*!< MCO Clock divided by 2 */\r
-#define RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) /*!< MCO Clock divided by 4 */\r
-#define RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) /*!< MCO Clock divided by 8 */\r
-#define RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) /*!< MCO Clock divided by 16 */\r
-\r
-/*!<****************** Bit definition for RCC_CIR register ********************/\r
-#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */\r
-#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */\r
-#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */\r
-#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */\r
-#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */\r
-#define RCC_CIR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */\r
-#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */\r
-\r
-#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */\r
-#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */\r
-#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */\r
-#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */\r
-#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */\r
-#define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000) /*!< MSI Ready Interrupt Enable */\r
-\r
-#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */\r
-#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */\r
-#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */\r
-#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */\r
-#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */\r
-#define RCC_CIR_MSIRDYC ((uint32_t)0x00200000) /*!< MSI Ready Interrupt Clear */\r
-#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */\r
-\r
-\r
-/***************** Bit definition for RCC_AHBRSTR register ******************/\r
-#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */\r
-#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */\r
-#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */\r
-#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */\r
-#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) /*!< GPIO port E reset */\r
-#define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) /*!< GPIO port H reset */\r
-#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */\r
-#define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) /*!< FLITF reset */\r
-#define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) /*!< DMA1 reset */\r
- \r
-/***************** Bit definition for RCC_APB2RSTR register *****************/\r
-#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< System Configuration SYSCFG reset */\r
-#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) /*!< TIM9 reset */\r
-#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) /*!< TIM10 reset */\r
-#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) /*!< TIM11 reset */\r
-#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 reset */\r
-#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */\r
-#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */\r
-\r
-/***************** Bit definition for RCC_APB1RSTR register *****************/\r
-#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */\r
-#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */\r
-#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */\r
-#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */\r
-#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */\r
-#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /*!< LCD reset */\r
-#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */\r
-#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */\r
-#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */\r
-#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */\r
-#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */\r
-#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */\r
-#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */\r
-#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */\r
-#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */\r
-#define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) /*!< Comparator interface reset */\r
-\r
-/****************** Bit definition for RCC_AHBENR register ******************/\r
-#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */\r
-#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */\r
-#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */\r
-#define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */\r
-#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) /*!< GPIO port E clock enable */\r
-#define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) /*!< GPIO port H clock enable */\r
-#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */\r
-#define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) /*!< FLITF clock enable (has effect only when\r
- the Flash memory is in power down mode) */\r
-#define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) /*!< DMA1 clock enable */\r
-\r
-\r
-/****************** Bit definition for RCC_APB2ENR register *****************/\r
-#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enable */\r
-#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) /*!< TIM9 interface clock enable */\r
-#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) /*!< TIM10 interface clock enable */\r
-#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enable */\r
-#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */\r
-#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */\r
-#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */\r
-\r
-\r
-/***************** Bit definition for RCC_APB1ENR register ******************/\r
-#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/\r
-#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */\r
-#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */\r
-#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */\r
-#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */\r
-#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /*!< LCD clock enable */\r
-#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */\r
-#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */\r
-#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */\r
-#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */\r
-#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */\r
-#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */\r
-#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */\r
-#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */\r
-#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */\r
-#define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enable */\r
-\r
-/****************** Bit definition for RCC_AHBLPENR register ****************/\r
-#define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */\r
-#define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */\r
-#define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */\r
-#define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */\r
-#define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) /*!< GPIO port E clock enabled in sleep mode */\r
-#define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) /*!< GPIO port H clock enabled in sleep mode */\r
-#define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */\r
-#define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) /*!< Flash Interface clock enabled in sleep mode\r
- (has effect only when the Flash memory is\r
- in power down mode) */\r
-#define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) /*!< SRAM clock enabled in sleep mode */\r
-#define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) /*!< DMA1 clock enabled in sleep mode */\r
-\r
-/****************** Bit definition for RCC_APB2LPENR register ***************/\r
-#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enabled in sleep mode */\r
-#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) /*!< TIM9 interface clock enabled in sleep mode */\r
-#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) /*!< TIM10 interface clock enabled in sleep mode */\r
-#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enabled in sleep mode */\r
-#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */\r
-#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */\r
-#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */\r
-\r
-/***************** Bit definition for RCC_APB1LPENR register ****************/\r
-#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */\r
-#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) /*!< Timer 3 clock enabled in sleep mode */\r
-#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) /*!< Timer 4 clock enabled in sleep mode */\r
-#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */\r
-#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) /*!< Timer 7 clock enabled in sleep mode */\r
-#define RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200) /*!< LCD clock enabled in sleep mode */\r
-#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */\r
-#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) /*!< SPI 2 clock enabled in sleep mode */\r
-#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) /*!< USART 2 clock enabled in sleep mode */\r
-#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) /*!< USART 3 clock enabled in sleep mode */\r
-#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) /*!< I2C 1 clock enabled in sleep mode */\r
-#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) /*!< I2C 2 clock enabled in sleep mode */\r
-#define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */\r
-#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) /*!< Power interface clock enabled in sleep mode */\r
-#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) /*!< DAC interface clock enabled in sleep mode */\r
-#define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enabled in sleep mode*/\r
-\r
-/******************* Bit definition for RCC_CSR register ********************/\r
-#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */\r
-#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */\r
-\r
-#define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */\r
-#define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */\r
-#define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */\r
-\r
-#define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */\r
-#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
-#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
-\r
-/*!< RTC congiguration */\r
-#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
-#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */\r
-#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */\r
-#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */\r
-\r
-#define RCC_CSR_RTCEN ((uint32_t)0x00400000) /*!< RTC clock enable */\r
-#define RCC_CSR_RTCRST ((uint32_t)0x00800000) /*!< RTC reset */\r
- \r
-#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */\r
-#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< Option Bytes Loader reset flag */\r
-#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */\r
-#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */\r
-#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */\r
-#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */\r
-#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */\r
-#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */\r
-\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Real-Time Clock (RTC) */\r
-/* */\r
-/******************************************************************************/\r
-/******************** Bits definition for RTC_TR register *******************/\r
-#define RTC_TR_PM ((uint32_t)0x00400000)\r
-#define RTC_TR_HT ((uint32_t)0x00300000)\r
-#define RTC_TR_HT_0 ((uint32_t)0x00100000)\r
-#define RTC_TR_HT_1 ((uint32_t)0x00200000)\r
-#define RTC_TR_HU ((uint32_t)0x000F0000)\r
-#define RTC_TR_HU_0 ((uint32_t)0x00010000)\r
-#define RTC_TR_HU_1 ((uint32_t)0x00020000)\r
-#define RTC_TR_HU_2 ((uint32_t)0x00040000)\r
-#define RTC_TR_HU_3 ((uint32_t)0x00080000)\r
-#define RTC_TR_MNT ((uint32_t)0x00007000)\r
-#define RTC_TR_MNT_0 ((uint32_t)0x00001000)\r
-#define RTC_TR_MNT_1 ((uint32_t)0x00002000)\r
-#define RTC_TR_MNT_2 ((uint32_t)0x00004000)\r
-#define RTC_TR_MNU ((uint32_t)0x00000F00)\r
-#define RTC_TR_MNU_0 ((uint32_t)0x00000100)\r
-#define RTC_TR_MNU_1 ((uint32_t)0x00000200)\r
-#define RTC_TR_MNU_2 ((uint32_t)0x00000400)\r
-#define RTC_TR_MNU_3 ((uint32_t)0x00000800)\r
-#define RTC_TR_ST ((uint32_t)0x00000070)\r
-#define RTC_TR_ST_0 ((uint32_t)0x00000010)\r
-#define RTC_TR_ST_1 ((uint32_t)0x00000020)\r
-#define RTC_TR_ST_2 ((uint32_t)0x00000040)\r
-#define RTC_TR_SU ((uint32_t)0x0000000F)\r
-#define RTC_TR_SU_0 ((uint32_t)0x00000001)\r
-#define RTC_TR_SU_1 ((uint32_t)0x00000002)\r
-#define RTC_TR_SU_2 ((uint32_t)0x00000004)\r
-#define RTC_TR_SU_3 ((uint32_t)0x00000008)\r
-\r
-/******************** Bits definition for RTC_DR register *******************/\r
-#define RTC_DR_YT ((uint32_t)0x00F00000)\r
-#define RTC_DR_YT_0 ((uint32_t)0x00100000)\r
-#define RTC_DR_YT_1 ((uint32_t)0x00200000)\r
-#define RTC_DR_YT_2 ((uint32_t)0x00400000)\r
-#define RTC_DR_YT_3 ((uint32_t)0x00800000)\r
-#define RTC_DR_YU ((uint32_t)0x000F0000)\r
-#define RTC_DR_YU_0 ((uint32_t)0x00010000)\r
-#define RTC_DR_YU_1 ((uint32_t)0x00020000)\r
-#define RTC_DR_YU_2 ((uint32_t)0x00040000)\r
-#define RTC_DR_YU_3 ((uint32_t)0x00080000)\r
-#define RTC_DR_WDU ((uint32_t)0x0000E000)\r
-#define RTC_DR_WDU_0 ((uint32_t)0x00002000)\r
-#define RTC_DR_WDU_1 ((uint32_t)0x00004000)\r
-#define RTC_DR_WDU_2 ((uint32_t)0x00008000)\r
-#define RTC_DR_MT ((uint32_t)0x00001000)\r
-#define RTC_DR_MU ((uint32_t)0x00000F00)\r
-#define RTC_DR_MU_0 ((uint32_t)0x00000100)\r
-#define RTC_DR_MU_1 ((uint32_t)0x00000200)\r
-#define RTC_DR_MU_2 ((uint32_t)0x00000400)\r
-#define RTC_DR_MU_3 ((uint32_t)0x00000800)\r
-#define RTC_DR_DT ((uint32_t)0x00000030)\r
-#define RTC_DR_DT_0 ((uint32_t)0x00000010)\r
-#define RTC_DR_DT_1 ((uint32_t)0x00000020)\r
-#define RTC_DR_DU ((uint32_t)0x0000000F)\r
-#define RTC_DR_DU_0 ((uint32_t)0x00000001)\r
-#define RTC_DR_DU_1 ((uint32_t)0x00000002)\r
-#define RTC_DR_DU_2 ((uint32_t)0x00000004)\r
-#define RTC_DR_DU_3 ((uint32_t)0x00000008)\r
-\r
-/******************** Bits definition for RTC_CR register *******************/\r
-#define RTC_CR_COE ((uint32_t)0x00800000)\r
-#define RTC_CR_OSEL ((uint32_t)0x00600000)\r
-#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)\r
-#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)\r
-#define RTC_CR_POL ((uint32_t)0x00100000)\r
-#define RTC_CR_BCK ((uint32_t)0x00040000)\r
-#define RTC_CR_SUB1H ((uint32_t)0x00020000)\r
-#define RTC_CR_ADD1H ((uint32_t)0x00010000)\r
-#define RTC_CR_TSIE ((uint32_t)0x00008000)\r
-#define RTC_CR_WUTIE ((uint32_t)0x00004000)\r
-#define RTC_CR_ALRBIE ((uint32_t)0x00002000)\r
-#define RTC_CR_ALRAIE ((uint32_t)0x00001000)\r
-#define RTC_CR_TSE ((uint32_t)0x00000800)\r
-#define RTC_CR_WUTE ((uint32_t)0x00000400)\r
-#define RTC_CR_ALRBE ((uint32_t)0x00000200)\r
-#define RTC_CR_ALRAE ((uint32_t)0x00000100)\r
-#define RTC_CR_DCE ((uint32_t)0x00000080)\r
-#define RTC_CR_FMT ((uint32_t)0x00000040)\r
-#define RTC_CR_REFCKON ((uint32_t)0x00000010)\r
-#define RTC_CR_TSEDGE ((uint32_t)0x00000008)\r
-#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)\r
-#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)\r
-#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)\r
-#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)\r
-\r
-/******************** Bits definition for RTC_ISR register ******************/\r
-#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)\r
-#define RTC_ISR_TSOVF ((uint32_t)0x00001000)\r
-#define RTC_ISR_TSF ((uint32_t)0x00000800)\r
-#define RTC_ISR_WUTF ((uint32_t)0x00000400)\r
-#define RTC_ISR_ALRBF ((uint32_t)0x00000200)\r
-#define RTC_ISR_ALRAF ((uint32_t)0x00000100)\r
-#define RTC_ISR_INIT ((uint32_t)0x00000080)\r
-#define RTC_ISR_INITF ((uint32_t)0x00000040)\r
-#define RTC_ISR_RSF ((uint32_t)0x00000020)\r
-#define RTC_ISR_INITS ((uint32_t)0x00000010)\r
-#define RTC_ISR_WUTWF ((uint32_t)0x00000004)\r
-#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)\r
-#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)\r
-\r
-/******************** Bits definition for RTC_PRER register *****************/\r
-#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)\r
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)\r
-\r
-/******************** Bits definition for RTC_WUTR register *****************/\r
-#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)\r
-\r
-/******************** Bits definition for RTC_CALIBR register ***************/\r
-#define RTC_CALIBR_DCS ((uint32_t)0x00000080)\r
-#define RTC_CALIBR_DC ((uint32_t)0x0000001F)\r
-\r
-/******************** Bits definition for RTC_ALRMAR register ***************/\r
-#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)\r
-#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)\r
-#define RTC_ALRMAR_DT ((uint32_t)0x30000000)\r
-#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)\r
-#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)\r
-#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)\r
-#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)\r
-#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)\r
-#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)\r
-#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)\r
-#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)\r
-#define RTC_ALRMAR_PM ((uint32_t)0x00400000)\r
-#define RTC_ALRMAR_HT ((uint32_t)0x00300000)\r
-#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)\r
-#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)\r
-#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)\r
-#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)\r
-#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)\r
-#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)\r
-#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)\r
-#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)\r
-#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)\r
-#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)\r
-#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)\r
-#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)\r
-#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)\r
-#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)\r
-#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)\r
-#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)\r
-#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)\r
-#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)\r
-#define RTC_ALRMAR_ST ((uint32_t)0x00000070)\r
-#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)\r
-#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)\r
-#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)\r
-#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)\r
-#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)\r
-#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)\r
-#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)\r
-#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)\r
-\r
-/******************** Bits definition for RTC_ALRMBR register ***************/\r
-#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)\r
-#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)\r
-#define RTC_ALRMBR_DT ((uint32_t)0x30000000)\r
-#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)\r
-#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)\r
-#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)\r
-#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)\r
-#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)\r
-#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)\r
-#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)\r
-#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)\r
-#define RTC_ALRMBR_PM ((uint32_t)0x00400000)\r
-#define RTC_ALRMBR_HT ((uint32_t)0x00300000)\r
-#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)\r
-#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)\r
-#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)\r
-#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)\r
-#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)\r
-#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)\r
-#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)\r
-#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)\r
-#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)\r
-#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)\r
-#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)\r
-#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)\r
-#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)\r
-#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)\r
-#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)\r
-#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)\r
-#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)\r
-#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)\r
-#define RTC_ALRMBR_ST ((uint32_t)0x00000070)\r
-#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)\r
-#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)\r
-#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)\r
-#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)\r
-#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)\r
-#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)\r
-#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)\r
-#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)\r
-\r
-/******************** Bits definition for RTC_WPR register ******************/\r
-#define RTC_WPR_KEY ((uint32_t)0x000000FF)\r
-\r
-/******************** Bits definition for RTC_TSTR register *****************/\r
-#define RTC_TSTR_PM ((uint32_t)0x00400000)\r
-#define RTC_TSTR_HT ((uint32_t)0x00300000)\r
-#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)\r
-#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)\r
-#define RTC_TSTR_HU ((uint32_t)0x000F0000)\r
-#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)\r
-#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)\r
-#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)\r
-#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)\r
-#define RTC_TSTR_MNT ((uint32_t)0x00007000)\r
-#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)\r
-#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)\r
-#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)\r
-#define RTC_TSTR_MNU ((uint32_t)0x00000F00)\r
-#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)\r
-#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)\r
-#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)\r
-#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)\r
-#define RTC_TSTR_ST ((uint32_t)0x00000070)\r
-#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)\r
-#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)\r
-#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)\r
-#define RTC_TSTR_SU ((uint32_t)0x0000000F)\r
-#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)\r
-#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)\r
-#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)\r
-#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)\r
-\r
-/******************** Bits definition for RTC_TSDR register *****************/\r
-#define RTC_TSDR_WDU ((uint32_t)0x0000E000)\r
-#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)\r
-#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)\r
-#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)\r
-#define RTC_TSDR_MT ((uint32_t)0x00001000)\r
-#define RTC_TSDR_MU ((uint32_t)0x00000F00)\r
-#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)\r
-#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)\r
-#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)\r
-#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)\r
-#define RTC_TSDR_DT ((uint32_t)0x00000030)\r
-#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)\r
-#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)\r
-#define RTC_TSDR_DU ((uint32_t)0x0000000F)\r
-#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)\r
-#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)\r
-#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)\r
-#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)\r
-\r
-/******************** Bits definition for RTC_TAFCR register ****************/\r
-#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)\r
-#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)\r
-#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)\r
-#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)\r
-\r
-/******************** Bits definition for RTC_BKP0R register ****************/\r
-#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP1R register ****************/\r
-#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP2R register ****************/\r
-#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP3R register ****************/\r
-#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP4R register ****************/\r
-#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP5R register ****************/\r
-#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP6R register ****************/\r
-#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP7R register ****************/\r
-#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP8R register ****************/\r
-#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP9R register ****************/\r
-#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP10R register ***************/\r
-#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP11R register ***************/\r
-#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP12R register ***************/\r
-#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP13R register ***************/\r
-#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP14R register ***************/\r
-#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP15R register ***************/\r
-#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP16R register ***************/\r
-#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP17R register ***************/\r
-#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP18R register ***************/\r
-#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP19R register ***************/\r
-#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Serial Peripheral Interface (SPI) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for SPI_CR1 register ********************/\r
-#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */\r
-#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */\r
-#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */\r
-\r
-#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */\r
-#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */\r
-#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */\r
-#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */\r
-\r
-#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */\r
-#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */\r
-#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */\r
-#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */\r
-#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */\r
-#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */\r
-#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */\r
-#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */\r
-#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */\r
-#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */\r
-\r
-/******************* Bit definition for SPI_CR2 register ********************/\r
-#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */\r
-#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */\r
-#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */\r
-#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */\r
-#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */\r
-#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */\r
-\r
-/******************** Bit definition for SPI_SR register ********************/\r
-#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */\r
-#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */\r
-#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */\r
-#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */\r
-#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */\r
-#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */\r
-\r
-/******************** Bit definition for SPI_DR register ********************/\r
-#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */\r
-\r
-/******************* Bit definition for SPI_CRCPR register ******************/\r
-#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */\r
-\r
-/****************** Bit definition for SPI_RXCRCR register ******************/\r
-#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */\r
-\r
-/****************** Bit definition for SPI_TXCRCR register ******************/\r
-#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* System Configuration (SYSCFG) */\r
-/* */\r
-/******************************************************************************/\r
-/***************** Bit definition for SYSCFG_MEMRMP register ****************/\r
-#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */\r
-#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-\r
-/***************** Bit definition for SYSCFG_PMC register *******************/\r
-#define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) /*!< SYSCFG PMC */\r
-\r
-/***************** Bit definition for SYSCFG_EXTICR1 register ***************/\r
-#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */\r
-#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */\r
-#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */\r
-#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */\r
-\r
-/** \r
- * @brief EXTI0 configuration \r
- */ \r
-#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0005) /*!< PH[0] pin */\r
-\r
-/** \r
- * @brief EXTI1 configuration \r
- */ \r
-#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0050) /*!< PH[1] pin */\r
-\r
-/** \r
- * @brief EXTI2 configuration \r
- */ \r
-#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0500) /*!< PH[2] pin */\r
-\r
-/** \r
- * @brief EXTI3 configuration \r
- */ \r
-#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */\r
-\r
-/***************** Bit definition for SYSCFG_EXTICR2 register *****************/\r
-#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */\r
-#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */\r
-#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */\r
-#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */\r
-\r
-/** \r
- * @brief EXTI4 configuration \r
- */ \r
-#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */\r
-\r
-/** \r
- * @brief EXTI5 configuration \r
- */ \r
-#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */\r
-\r
-/** \r
- * @brief EXTI6 configuration \r
- */ \r
-#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */\r
-\r
-/** \r
- * @brief EXTI7 configuration \r
- */ \r
-#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */\r
-\r
-/***************** Bit definition for SYSCFG_EXTICR3 register *****************/\r
-#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */\r
-#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */\r
-#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */\r
-#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */\r
- \r
-/** \r
- * @brief EXTI8 configuration \r
- */ \r
-#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */\r
-#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */\r
-#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */\r
-#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */\r
-#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */\r
-\r
-/** \r
- * @brief EXTI9 configuration \r
- */ \r
-#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */\r
-#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */\r
-#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */\r
-#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */\r
-#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */\r
-\r
-/** \r
- * @brief EXTI10 configuration \r
- */ \r
-#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */\r
-#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */\r
-#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */\r
-#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */\r
-#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */\r
-\r
-/** \r
- * @brief EXTI11 configuration \r
- */ \r
-#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */\r
-#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */\r
-#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */\r
-#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */\r
-#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */\r
-\r
-/***************** Bit definition for SYSCFG_EXTICR4 register *****************/\r
-#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */\r
-#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */\r
-#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */\r
-#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */\r
-\r
-/** \r
- * @brief EXTI12 configuration \r
- */ \r
-#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */\r
-#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */\r
-#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */\r
-#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */\r
-#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */\r
-\r
-/** \r
- * @brief EXTI13 configuration \r
- */ \r
-#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */\r
-#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */\r
-#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */\r
-#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */\r
-#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */\r
-\r
-/** \r
- * @brief EXTI14 configuration \r
- */ \r
-#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */\r
-#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */\r
-#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */\r
-#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */\r
-#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */\r
-\r
-/** \r
- * @brief EXTI15 configuration \r
- */ \r
-#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */\r
-#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */\r
-#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */\r
-#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */\r
-#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */\r
- \r
-/******************************************************************************/\r
-/* */\r
-/* Routing Interface (RI) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************** Bit definition for RI_ICR register ********************/\r
-#define RI_ICR_IC1Z ((uint32_t)0x0000000F) /*!< IC1Z[3:0] bits (Input Capture 1 select bits) */\r
-#define RI_ICR_IC1Z_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define RI_ICR_IC1Z_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-#define RI_ICR_IC1Z_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
-#define RI_ICR_IC1Z_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
-\r
-#define RI_ICR_IC2Z ((uint32_t)0x000000F0) /*!< IC2Z[3:0] bits (Input Capture 2 select bits) */\r
-#define RI_ICR_IC2Z_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
-#define RI_ICR_IC2Z_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
-#define RI_ICR_IC2Z_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
-#define RI_ICR_IC2Z_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
-\r
-#define RI_ICR_IC3Z ((uint32_t)0x00000F00) /*!< IC3Z[3:0] bits (Input Capture 3 select bits) */\r
-#define RI_ICR_IC3Z_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
-#define RI_ICR_IC3Z_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
-#define RI_ICR_IC3Z_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
-#define RI_ICR_IC3Z_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
-\r
-#define RI_ICR_IC4Z ((uint32_t)0x0000F000) /*!< IC4Z[3:0] bits (Input Capture 4 select bits) */\r
-#define RI_ICR_IC4Z_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
-#define RI_ICR_IC4Z_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
-#define RI_ICR_IC4Z_2 ((uint32_t)0x00004000) /*!< Bit 2 */\r
-#define RI_ICR_IC4Z_3 ((uint32_t)0x00008000) /*!< Bit 3 */\r
-\r
-#define RI_ICR_TIM ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */\r
-#define RI_ICR_TIM_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
-#define RI_ICR_TIM_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
-\r
-#define RI_ICR_IC1 ((uint32_t)0x00040000) /*!< Input capture 1 */\r
-#define RI_ICR_IC2 ((uint32_t)0x00080000) /*!< Input capture 2 */\r
-#define RI_ICR_IC3 ((uint32_t)0x00100000) /*!< Input capture 3 */\r
-#define RI_ICR_IC4 ((uint32_t)0x00200000) /*!< Input capture 4 */\r
-\r
-/******************** Bit definition for RI_ASCR1 register ********************/\r
-#define RI_ASCR1_CH ((uint32_t)0x03FCFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */\r
-#define RI_ASCR1_CH_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define RI_ASCR1_CH_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-#define RI_ASCR1_CH_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
-#define RI_ASCR1_CH_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
-#define RI_ASCR1_CH_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
-#define RI_ASCR1_CH_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
-#define RI_ASCR1_CH_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
-#define RI_ASCR1_CH_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
-#define RI_ASCR1_CH_8 ((uint32_t)0x00000100) /*!< Bit 8 */\r
-#define RI_ASCR1_CH_9 ((uint32_t)0x00000200) /*!< Bit 9 */\r
-#define RI_ASCR1_CH_10 ((uint32_t)0x00000400) /*!< Bit 10 */\r
-#define RI_ASCR1_CH_11 ((uint32_t)0x00000800) /*!< Bit 11 */\r
-#define RI_ASCR1_CH_12 ((uint32_t)0x00001000) /*!< Bit 12 */\r
-#define RI_ASCR1_CH_13 ((uint32_t)0x00002000) /*!< Bit 13 */\r
-#define RI_ASCR1_CH_14 ((uint32_t)0x00004000) /*!< Bit 14 */\r
-#define RI_ASCR1_CH_15 ((uint32_t)0x00008000) /*!< Bit 15 */\r
-#define RI_ASCR1_CH_18 ((uint32_t)0x00040000) /*!< Bit 18 */\r
-#define RI_ASCR1_CH_19 ((uint32_t)0x00080000) /*!< Bit 19 */\r
-#define RI_ASCR1_CH_20 ((uint32_t)0x00100000) /*!< Bit 20 */\r
-#define RI_ASCR1_CH_21 ((uint32_t)0x00200000) /*!< Bit 21 */\r
-#define RI_ASCR1_CH_22 ((uint32_t)0x00400000) /*!< Bit 22 */\r
-#define RI_ASCR1_CH_23 ((uint32_t)0x00800000) /*!< Bit 23 */\r
-#define RI_ASCR1_CH_24 ((uint32_t)0x01000000) /*!< Bit 24 */\r
-#define RI_ASCR1_CH_25 ((uint32_t)0x02000000) /*!< Bit 25 */\r
-\r
-#define RI_ASCR1_VCOMP ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */\r
-#define RI_ASCR1_SCM ((uint32_t)0x80000000) /*!< I/O Switch control mode */\r
-\r
-/******************** Bit definition for RI_ASCR2 register ********************/\r
-#define RI_ASCR2_GR10_1 ((uint32_t)0x00000001) /*!< GR10-1 selection bit */\r
-#define RI_ASCR2_GR10_2 ((uint32_t)0x00000002) /*!< GR10-2 selection bit */\r
-#define RI_ASCR2_GR10_3 ((uint32_t)0x00000004) /*!< GR10-3 selection bit */\r
-#define RI_ASCR2_GR10_4 ((uint32_t)0x00000008) /*!< GR10-4 selection bit */\r
-#define RI_ASCR2_GR6_1 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */\r
-#define RI_ASCR2_GR6_2 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */\r
-#define RI_ASCR2_GR5_1 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */\r
-#define RI_ASCR2_GR5_2 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */\r
-#define RI_ASCR2_GR5_3 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */\r
-#define RI_ASCR2_GR4_1 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */\r
-#define RI_ASCR2_GR4_2 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */\r
-#define RI_ASCR2_GR4_3 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */\r
-\r
-\r
-/******************** Bit definition for RI_HYSCR1 register ********************/\r
-#define RI_HYSCR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */\r
-#define RI_HYSCR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define RI_HYSCR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-#define RI_HYSCR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
-#define RI_HYSCR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
-#define RI_HYSCR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
-#define RI_HYSCR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
-#define RI_HYSCR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
-#define RI_HYSCR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
-#define RI_HYSCR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */\r
-#define RI_HYSCR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */\r
-#define RI_HYSCR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */\r
-#define RI_HYSCR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */\r
-#define RI_HYSCR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */\r
-#define RI_HYSCR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */\r
-#define RI_HYSCR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */\r
-#define RI_HYSCR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */\r
-\r
-#define RI_HYSCR1_PB ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */\r
-#define RI_HYSCR1_PB_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
-#define RI_HYSCR1_PB_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
-#define RI_HYSCR1_PB_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
-#define RI_HYSCR1_PB_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
-#define RI_HYSCR1_PB_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
-#define RI_HYSCR1_PB_5 ((uint32_t)0x00200000) /*!< Bit 5 */\r
-#define RI_HYSCR1_PB_6 ((uint32_t)0x00400000) /*!< Bit 6 */\r
-#define RI_HYSCR1_PB_7 ((uint32_t)0x00800000) /*!< Bit 7 */\r
-#define RI_HYSCR1_PB_8 ((uint32_t)0x01000000) /*!< Bit 8 */\r
-#define RI_HYSCR1_PB_9 ((uint32_t)0x02000000) /*!< Bit 9 */\r
-#define RI_HYSCR1_PB_10 ((uint32_t)0x04000000) /*!< Bit 10 */\r
-#define RI_HYSCR1_PB_11 ((uint32_t)0x08000000) /*!< Bit 11 */\r
-#define RI_HYSCR1_PB_12 ((uint32_t)0x10000000) /*!< Bit 12 */\r
-#define RI_HYSCR1_PB_13 ((uint32_t)0x20000000) /*!< Bit 13 */\r
-#define RI_HYSCR1_PB_14 ((uint32_t)0x40000000) /*!< Bit 14 */\r
-#define RI_HYSCR1_PB_15 ((uint32_t)0x80000000) /*!< Bit 15 */\r
-\r
-/******************** Bit definition for RI_HYSCR2 register ********************/\r
-#define RI_HYSCR2_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */\r
-#define RI_HYSCR2_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define RI_HYSCR2_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-#define RI_HYSCR2_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
-#define RI_HYSCR2_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
-#define RI_HYSCR2_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
-#define RI_HYSCR2_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
-#define RI_HYSCR2_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
-#define RI_HYSCR2_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
-#define RI_HYSCR2_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */\r
-#define RI_HYSCR2_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */\r
-#define RI_HYSCR2_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */\r
-#define RI_HYSCR2_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */\r
-#define RI_HYSCR2_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */\r
-#define RI_HYSCR2_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */\r
-#define RI_HYSCR2_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */\r
-#define RI_HYSCR2_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */\r
-\r
-#define RI_HYSCR2_PD ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */\r
-#define RI_HYSCR2_PD_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
-#define RI_HYSCR2_PD_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
-#define RI_HYSCR2_PD_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
-#define RI_HYSCR2_PD_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
-#define RI_HYSCR2_PD_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
-#define RI_HYSCR2_PD_5 ((uint32_t)0x00200000) /*!< Bit 5 */\r
-#define RI_HYSCR2_PD_6 ((uint32_t)0x00400000) /*!< Bit 6 */\r
-#define RI_HYSCR2_PD_7 ((uint32_t)0x00800000) /*!< Bit 7 */\r
-#define RI_HYSCR2_PD_8 ((uint32_t)0x01000000) /*!< Bit 8 */\r
-#define RI_HYSCR2_PD_9 ((uint32_t)0x02000000) /*!< Bit 9 */\r
-#define RI_HYSCR2_PD_10 ((uint32_t)0x04000000) /*!< Bit 10 */\r
-#define RI_HYSCR2_PD_11 ((uint32_t)0x08000000) /*!< Bit 11 */\r
-#define RI_HYSCR2_PD_12 ((uint32_t)0x10000000) /*!< Bit 12 */\r
-#define RI_HYSCR2_PD_13 ((uint32_t)0x20000000) /*!< Bit 13 */\r
-#define RI_HYSCR2_PD_14 ((uint32_t)0x40000000) /*!< Bit 14 */\r
-#define RI_HYSCR2_PD_15 ((uint32_t)0x80000000) /*!< Bit 15 */\r
-\r
-/******************** Bit definition for RI_HYSCR3 register ********************/\r
-#define RI_HYSCR2_PE ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */\r
-#define RI_HYSCR2_PE_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define RI_HYSCR2_PE_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-#define RI_HYSCR2_PE_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
-#define RI_HYSCR2_PE_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
-#define RI_HYSCR2_PE_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
-#define RI_HYSCR2_PE_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
-#define RI_HYSCR2_PE_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
-#define RI_HYSCR2_PE_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
-#define RI_HYSCR2_PE_8 ((uint32_t)0x00000100) /*!< Bit 8 */\r
-#define RI_HYSCR2_PE_9 ((uint32_t)0x00000200) /*!< Bit 9 */\r
-#define RI_HYSCR2_PE_10 ((uint32_t)0x00000400) /*!< Bit 10 */\r
-#define RI_HYSCR2_PE_11 ((uint32_t)0x00000800) /*!< Bit 11 */\r
-#define RI_HYSCR2_PE_12 ((uint32_t)0x00001000) /*!< Bit 12 */\r
-#define RI_HYSCR2_PE_13 ((uint32_t)0x00002000) /*!< Bit 13 */\r
-#define RI_HYSCR2_PE_14 ((uint32_t)0x00004000) /*!< Bit 14 */\r
-#define RI_HYSCR2_PE_15 ((uint32_t)0x00008000) /*!< Bit 15 */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Timers (TIM) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for TIM_CR1 register ********************/\r
-#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */\r
-#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */\r
-#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */\r
-#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */\r
-#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */\r
-\r
-#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
-#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */\r
-#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */\r
-\r
-#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */\r
-\r
-#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */\r
-#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-\r
-/******************* Bit definition for TIM_CR2 register ********************/\r
-#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */\r
-#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */\r
-#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */\r
-\r
-#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */\r
-#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-\r
-#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */\r
-#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */\r
-#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */\r
-#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */\r
-#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */\r
-#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */\r
-#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */\r
-#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */\r
-\r
-/******************* Bit definition for TIM_SMCR register *******************/\r
-#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */\r
-#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
-\r
-#define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!<OCCS bits (OCref Clear Selection) */\r
-\r
-#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */\r
-#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-\r
-#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */\r
-\r
-#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */\r
-#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
-#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
-\r
-#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */\r
-#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */\r
-#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */\r
-\r
-/******************* Bit definition for TIM_DIER register *******************/\r
-#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */\r
-#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */\r
-#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */\r
-#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */\r
-#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */\r
-#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */\r
-#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */\r
-#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */\r
-#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */\r
-#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */\r
-#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */\r
-#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */\r
-#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */\r
-#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */\r
-#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */\r
-\r
-/******************** Bit definition for TIM_SR register ********************/\r
-#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */\r
-#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */\r
-#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */\r
-#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */\r
-#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */\r
-#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */\r
-#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */\r
-#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */\r
-#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */\r
-#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */\r
-#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */\r
-#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */\r
-\r
-/******************* Bit definition for TIM_EGR register ********************/\r
-#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */\r
-#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */\r
-#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */\r
-#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */\r
-#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */\r
-#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */\r
-#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */\r
-#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */\r
-\r
-/****************** Bit definition for TIM_CCMR1 register *******************/\r
-#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
-#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */\r
-#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */\r
-\r
-#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
-#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-\r
-#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */\r
-\r
-#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
-#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */\r
-#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */\r
-\r
-#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
-#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
-\r
-#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
-#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
-#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
-#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
-\r
-#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
-#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
-#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
-#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
-\r
-/****************** Bit definition for TIM_CCMR2 register *******************/\r
-#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
-#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */\r
-#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */\r
-\r
-#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
-#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-\r
-#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */\r
-\r
-#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
-#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */\r
-#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */\r
-\r
-#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
-#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
-\r
-#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
-#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
-#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
-#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
-\r
-#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
-#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
-#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
-#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
-\r
-/******************* Bit definition for TIM_CCER register *******************/\r
-#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */\r
-#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */\r
-#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */\r
-#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */\r
-#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */\r
-#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */\r
-#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */\r
-#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */\r
-#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */\r
-#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */\r
-#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */\r
-#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */\r
-#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */\r
-#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */\r
-#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */\r
-\r
-/******************* Bit definition for TIM_CNT register ********************/\r
-#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */\r
-\r
-/******************* Bit definition for TIM_PSC register ********************/\r
-#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */\r
-\r
-/******************* Bit definition for TIM_ARR register ********************/\r
-#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */\r
-\r
-/******************* Bit definition for TIM_RCR register ********************/\r
-#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */\r
-\r
-/******************* Bit definition for TIM_CCR1 register *******************/\r
-#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */\r
-\r
-/******************* Bit definition for TIM_CCR2 register *******************/\r
-#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */\r
-\r
-/******************* Bit definition for TIM_CCR3 register *******************/\r
-#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */\r
-\r
-/******************* Bit definition for TIM_CCR4 register *******************/\r
-#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */\r
-\r
-/******************* Bit definition for TIM_DCR register ********************/\r
-#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */\r
-#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
-#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
-#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
-\r
-#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */\r
-#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
-#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
-#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */\r
-\r
-/******************* Bit definition for TIM_DMAR register *******************/\r
-#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */\r
-\r
-/******************* Bit definition for TIM_OR register *********************/\r
-#define TIM_OR_TI1RMP ((uint16_t)0x0003) /*!<Option register for TI1 Remapping */\r
-#define TIM_OR_TI1RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define TIM_OR_TI1RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for USART_SR register *******************/\r
-#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */\r
-#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */\r
-#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */\r
-#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */\r
-#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */\r
-#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */\r
-#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */\r
-#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */\r
-#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */\r
-#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */\r
-\r
-/******************* Bit definition for USART_DR register *******************/\r
-#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */\r
-\r
-/****************** Bit definition for USART_BRR register *******************/\r
-#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */\r
-#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */\r
-\r
-/****************** Bit definition for USART_CR1 register *******************/\r
-#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */\r
-#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */\r
-#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */\r
-#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */\r
-#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */\r
-#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */\r
-#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */\r
-#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */\r
-#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */\r
-#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */\r
-#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */\r
-#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */\r
-#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */\r
-#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */\r
-#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< Oversampling by 8-bit mode */\r
-\r
-/****************** Bit definition for USART_CR2 register *******************/\r
-#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */\r
-#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */\r
-#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */\r
-#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */\r
-#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */\r
-#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */\r
-#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */\r
-\r
-#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */\r
-#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
-#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
-\r
-#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */\r
-\r
-/****************** Bit definition for USART_CR3 register *******************/\r
-#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */\r
-#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */\r
-#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */\r
-#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */\r
-#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */\r
-#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */\r
-#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */\r
-#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */\r
-#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */\r
-#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */\r
-#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */\r
-#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One sample bit method enable */\r
-\r
-/****************** Bit definition for USART_GTPR register ******************/\r
-#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */\r
-#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */\r
-#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */\r
-#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */\r
-#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */\r
-#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */\r
-#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */\r
-#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */\r
-#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */\r
-\r
-#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Universal Serial Bus (USB) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/*!<Endpoint-specific registers */\r
-/******************* Bit definition for USB_EP0R register *******************/\r
-#define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
-\r
-#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-\r
-#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
-#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
-#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
-\r
-#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
-#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
-\r
-#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
-\r
-#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
-#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP1R register *******************/\r
-#define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
-\r
-#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-\r
-#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
-#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
-#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
-\r
-#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
-#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
-\r
-#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
-\r
-#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
-#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP2R register *******************/\r
-#define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
-\r
-#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-\r
-#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
-#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
-#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
-\r
-#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
-#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
-\r
-#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
-\r
-#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
-#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP3R register *******************/\r
-#define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
-\r
-#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-\r
-#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
-#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
-#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
-\r
-#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
-#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
-\r
-#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
-\r
-#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
-#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP4R register *******************/\r
-#define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
-\r
-#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-\r
-#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
-#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
-#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
-\r
-#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
-#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
-\r
-#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
-\r
-#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
-#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP5R register *******************/\r
-#define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
-\r
-#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-\r
-#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
-#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
-#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
-\r
-#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
-#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
-\r
-#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
-\r
-#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
-#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP6R register *******************/\r
-#define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
-\r
-#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-\r
-#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
-#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
-#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
-\r
-#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
-#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
-\r
-#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
-\r
-#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
-#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP7R register *******************/\r
-#define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
-\r
-#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-\r
-#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
-#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
-#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
-\r
-#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
-#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
-\r
-#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
-\r
-#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
-#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
-\r
-/*!<Common registers */\r
-/******************* Bit definition for USB_CNTR register *******************/\r
-#define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */\r
-#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */\r
-#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */\r
-#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */\r
-#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */\r
-#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */\r
-#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */\r
-#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */\r
-#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */\r
-#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */\r
-#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */\r
-#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */\r
-#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */\r
-\r
-/******************* Bit definition for USB_ISTR register *******************/\r
-#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */\r
-#define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */\r
-#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */\r
-#define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */\r
-#define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */\r
-#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */\r
-#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */\r
-#define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */\r
-#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */\r
-#define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */\r
-\r
-/******************* Bit definition for USB_FNR register ********************/\r
-#define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */\r
-#define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */\r
-#define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */\r
-#define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */\r
-#define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */\r
-\r
-/****************** Bit definition for USB_DADDR register *******************/\r
-#define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */\r
-#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */\r
-#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */\r
-#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */\r
-#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */\r
-#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */\r
-#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */\r
-#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */\r
-\r
-#define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */\r
-\r
-/****************** Bit definition for USB_BTABLE register ******************/ \r
-#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */\r
-\r
-/*!< Buffer descriptor table */\r
-/***************** Bit definition for USB_ADDR0_TX register *****************/\r
-#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */\r
-\r
-/***************** Bit definition for USB_ADDR1_TX register *****************/\r
-#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */\r
-\r
-/***************** Bit definition for USB_ADDR2_TX register *****************/\r
-#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */\r
-\r
-/***************** Bit definition for USB_ADDR3_TX register *****************/\r
-#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */\r
-\r
-/***************** Bit definition for USB_ADDR4_TX register *****************/\r
-#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */\r
-\r
-/***************** Bit definition for USB_ADDR5_TX register *****************/\r
-#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */\r
-\r
-/***************** Bit definition for USB_ADDR6_TX register *****************/\r
-#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */\r
-\r
-/***************** Bit definition for USB_ADDR7_TX register *****************/\r
-#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/***************** Bit definition for USB_COUNT0_TX register ****************/\r
-#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */\r
-\r
-/***************** Bit definition for USB_COUNT1_TX register ****************/\r
-#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */\r
-\r
-/***************** Bit definition for USB_COUNT2_TX register ****************/\r
-#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */\r
-\r
-/***************** Bit definition for USB_COUNT3_TX register ****************/\r
-#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */\r
-\r
-/***************** Bit definition for USB_COUNT4_TX register ****************/\r
-#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */\r
-\r
-/***************** Bit definition for USB_COUNT5_TX register ****************/\r
-#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */\r
-\r
-/***************** Bit definition for USB_COUNT6_TX register ****************/\r
-#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */\r
-\r
-/***************** Bit definition for USB_COUNT7_TX register ****************/\r
-#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/**************** Bit definition for USB_COUNT0_TX_0 register ***************/\r
-#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT0_TX_1 register ***************/\r
-#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT1_TX_0 register ***************/\r
-#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT1_TX_1 register ***************/\r
-#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT2_TX_0 register ***************/\r
-#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT2_TX_1 register ***************/\r
-#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT3_TX_0 register ***************/\r
-#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT3_TX_1 register ***************/\r
-#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT4_TX_0 register ***************/\r
-#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT4_TX_1 register ***************/\r
-#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT5_TX_0 register ***************/\r
-#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT5_TX_1 register ***************/\r
-#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT6_TX_0 register ***************/\r
-#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT6_TX_1 register ***************/\r
-#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT7_TX_0 register ***************/\r
-#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT7_TX_1 register ***************/\r
-#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/***************** Bit definition for USB_ADDR0_RX register *****************/\r
-#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */\r
-\r
-/***************** Bit definition for USB_ADDR1_RX register *****************/\r
-#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */\r
-\r
-/***************** Bit definition for USB_ADDR2_RX register *****************/\r
-#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */\r
-\r
-/***************** Bit definition for USB_ADDR3_RX register *****************/\r
-#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */\r
-\r
-/***************** Bit definition for USB_ADDR4_RX register *****************/\r
-#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */\r
-\r
-/***************** Bit definition for USB_ADDR5_RX register *****************/\r
-#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */\r
-\r
-/***************** Bit definition for USB_ADDR6_RX register *****************/\r
-#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */\r
-\r
-/***************** Bit definition for USB_ADDR7_RX register *****************/\r
-#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/***************** Bit definition for USB_COUNT0_RX register ****************/\r
-#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
-\r
-#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
-#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
-#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
-#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
-#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT1_RX register ****************/\r
-#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
-\r
-#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
-#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
-#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
-#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
-#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT2_RX register ****************/\r
-#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
-\r
-#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
-#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
-#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
-#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
-#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT3_RX register ****************/\r
-#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
-\r
-#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
-#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
-#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
-#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
-#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT4_RX register ****************/\r
-#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
-\r
-#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
-#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
-#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
-#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
-#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT5_RX register ****************/\r
-#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
-\r
-#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
-#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
-#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
-#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
-#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT6_RX register ****************/\r
-#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
-\r
-#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
-#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
-#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
-#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
-#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT7_RX register ****************/\r
-#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
-\r
-#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
-#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
-#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
-#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
-#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/**************** Bit definition for USB_COUNT0_RX_0 register ***************/\r
-#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
-\r
-#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT0_RX_1 register ***************/\r
-#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
-\r
-#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */\r
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
-\r
-/**************** Bit definition for USB_COUNT1_RX_0 register ***************/\r
-#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
-\r
-#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT1_RX_1 register ***************/\r
-#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
-\r
-#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
-\r
-/**************** Bit definition for USB_COUNT2_RX_0 register ***************/\r
-#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
-\r
-#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT2_RX_1 register ***************/\r
-#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
-\r
-#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
-\r
-/**************** Bit definition for USB_COUNT3_RX_0 register ***************/\r
-#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
-\r
-#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT3_RX_1 register ***************/\r
-#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
-\r
-#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
-\r
-/**************** Bit definition for USB_COUNT4_RX_0 register ***************/\r
-#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
-\r
-#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT4_RX_1 register ***************/\r
-#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
-\r
-#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
-\r
-/**************** Bit definition for USB_COUNT5_RX_0 register ***************/\r
-#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
-\r
-#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT5_RX_1 register ***************/\r
-#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
-\r
-#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
-\r
-/*************** Bit definition for USB_COUNT6_RX_0 register ***************/\r
-#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
-\r
-#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT6_RX_1 register ***************/\r
-#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
-\r
-#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
-\r
-/*************** Bit definition for USB_COUNT7_RX_0 register ****************/\r
-#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
-\r
-#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
-\r
-/*************** Bit definition for USB_COUNT7_RX_1 register ****************/\r
-#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
-\r
-#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
-\r
-#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Window WATCHDOG (WWDG) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for WWDG_CR register ********************/\r
-#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
-#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */\r
-#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */\r
-#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */\r
-#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */\r
-#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */\r
-#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */\r
-#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */\r
-\r
-#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */\r
-\r
-/******************* Bit definition for WWDG_CFR register *******************/\r
-#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */\r
-#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */\r
-#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */\r
-#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */\r
-#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */\r
-#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */\r
-#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */\r
-#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */\r
-\r
-#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */\r
-#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */\r
-#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */\r
-\r
-#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */\r
-\r
-/******************* Bit definition for WWDG_SR register ********************/\r
-#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* SystemTick (SysTick) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/***************** Bit definition for SysTick_CTRL register *****************/\r
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */\r
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */\r
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */\r
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */\r
-\r
-/***************** Bit definition for SysTick_LOAD register *****************/\r
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */\r
-\r
-/***************** Bit definition for SysTick_VAL register ******************/\r
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */\r
-\r
-/***************** Bit definition for SysTick_CALIB register ****************/\r
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */\r
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */\r
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Nested Vectored Interrupt Controller (NVIC) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/****************** Bit definition for NVIC_ISER register *******************/\r
-#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */\r
-#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
-#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
-#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
-#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
-#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
-#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
-#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
-#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
-#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
-#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
-#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
-#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
-#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
-#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
-#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
-#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
-#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
-#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
-#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
-#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
-#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
-#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
-#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
-#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
-#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
-#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
-#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
-#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
-#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
-#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
-#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
-#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
-\r
-/****************** Bit definition for NVIC_ICER register *******************/\r
-#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */\r
-#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
-#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
-#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
-#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
-#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
-#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
-#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
-#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
-#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
-#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
-#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
-#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
-#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
-#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
-#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
-#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
-#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
-#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
-#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
-#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
-#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
-#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
-#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
-#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
-#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
-#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
-#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
-#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
-#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
-#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
-#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
-#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
-\r
-/****************** Bit definition for NVIC_ISPR register *******************/\r
-#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */\r
-#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
-#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
-#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
-#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
-#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
-#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
-#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
-#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
-#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
-#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
-#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
-#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
-#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
-#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
-#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
-#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
-#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
-#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
-#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
-#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
-#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
-#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
-#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
-#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
-#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
-#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
-#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
-#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
-#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
-#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
-#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
-#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
-\r
-/****************** Bit definition for NVIC_ICPR register *******************/\r
-#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */\r
-#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
-#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
-#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
-#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
-#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
-#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
-#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
-#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
-#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
-#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
-#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
-#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
-#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
-#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
-#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
-#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
-#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
-#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
-#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
-#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
-#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
-#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
-#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
-#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
-#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
-#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
-#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
-#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
-#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
-#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
-#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
-#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
-\r
-/****************** Bit definition for NVIC_IABR register *******************/\r
-#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */\r
-#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
-#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
-#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
-#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
-#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
-#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
-#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
-#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
-#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
-#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
-#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
-#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
-#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
-#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
-#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
-#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
-#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
-#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
-#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
-#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
-#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
-#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
-#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
-#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
-#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
-#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
-#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
-#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
-#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
-#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
-#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
-#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
-\r
-/****************** Bit definition for NVIC_PRI0 register *******************/\r
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */\r
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */\r
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */\r
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */\r
-\r
-/****************** Bit definition for NVIC_PRI1 register *******************/\r
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */\r
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */\r
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */\r
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */\r
-\r
-/****************** Bit definition for NVIC_PRI2 register *******************/\r
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */\r
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */\r
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */\r
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */\r
-\r
-/****************** Bit definition for NVIC_PRI3 register *******************/\r
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */\r
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */\r
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */\r
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */\r
-\r
-/****************** Bit definition for NVIC_PRI4 register *******************/\r
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */\r
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */\r
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */\r
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */\r
-\r
-/****************** Bit definition for NVIC_PRI5 register *******************/\r
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */\r
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */\r
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */\r
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */\r
-\r
-/****************** Bit definition for NVIC_PRI6 register *******************/\r
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */\r
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */\r
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */\r
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */\r
-\r
-/****************** Bit definition for NVIC_PRI7 register *******************/\r
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */\r
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */\r
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */\r
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */\r
-\r
-/****************** Bit definition for SCB_CPUID register *******************/\r
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */\r
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */\r
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */\r
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */\r
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */\r
-\r
-/******************* Bit definition for SCB_ICSR register *******************/\r
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */\r
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */\r
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */\r
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */\r
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */\r
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */\r
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */\r
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */\r
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */\r
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */\r
-\r
-/******************* Bit definition for SCB_VTOR register *******************/\r
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */\r
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */\r
-\r
-/*!<***************** Bit definition for SCB_AIRCR register *******************/\r
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */\r
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */\r
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */\r
-\r
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */\r
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
-\r
-/* prority group configuration */\r
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */\r
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */\r
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */\r
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */\r
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */\r
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */\r
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */\r
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */\r
-\r
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */\r
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */\r
-\r
-/******************* Bit definition for SCB_SCR register ********************/\r
-#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */\r
-#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */\r
-#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */\r
-\r
-/******************** Bit definition for SCB_CCR register *******************/\r
-#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */\r
-#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */\r
-#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */\r
-#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */\r
-#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */\r
-#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */\r
-\r
-/******************* Bit definition for SCB_SHPR register ********************/\r
-#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */\r
-#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */\r
-#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */\r
-#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */\r
-\r
-/****************** Bit definition for SCB_SHCSR register *******************/\r
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */\r
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */\r
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */\r
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */\r
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */\r
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */\r
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */\r
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */\r
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */\r
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */\r
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */\r
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */\r
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */\r
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */\r
-\r
-/******************* Bit definition for SCB_CFSR register *******************/\r
-/*!< MFSR */\r
-#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */\r
-#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */\r
-#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */\r
-#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */\r
-#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */\r
-/*!< BFSR */\r
-#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */\r
-#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */\r
-#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */\r
-#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */\r
-#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */\r
-#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */\r
-/*!< UFSR */\r
-#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */\r
-#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */\r
-#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */\r
-#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */\r
-#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */\r
-#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */\r
-\r
-/******************* Bit definition for SCB_HFSR register *******************/\r
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */\r
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */\r
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */\r
-\r
-/******************* Bit definition for SCB_DFSR register *******************/\r
-#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */\r
-#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */\r
-#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */\r
-#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */\r
-#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */\r
-\r
-/******************* Bit definition for SCB_MMFAR register ******************/\r
-#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */\r
-\r
-/******************* Bit definition for SCB_BFAR register *******************/\r
-#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */\r
-\r
-/******************* Bit definition for SCB_afsr register *******************/\r
-#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */\r
-/**\r
- * @}\r
- */\r
-\r
- /**\r
- * @}\r
- */ \r
-\r
-#ifdef USE_STDPERIPH_DRIVER\r
- #include "stm32l1xx_conf.h"\r
-#endif\r
-\r
-/** @addtogroup Exported_macro\r
- * @{\r
- */\r
-\r
-#define SET_BIT(REG, BIT) ((REG) |= (BIT))\r
-\r
-#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))\r
-\r
-#define READ_BIT(REG, BIT) ((REG) & (BIT))\r
-\r
-#define CLEAR_REG(REG) ((REG) = (0x0))\r
-\r
-#define WRITE_REG(REG, VAL) ((REG) = (VAL))\r
-\r
-#define READ_REG(REG) ((REG))\r
-\r
-#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L1XX_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
- /**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file system_stm32f10x.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.\r
- ****************************************************************************** \r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ******************************************************************************\r
- */\r
-\r
-/** @addtogroup CMSIS\r
- * @{\r
- */\r
-\r
-/** @addtogroup stm32f10x_system\r
- * @{\r
- */ \r
- \r
-/**\r
- * @brief Define to prevent recursive inclusion\r
- */\r
-#ifndef __SYSTEM_STM32F10X_H\r
-#define __SYSTEM_STM32F10X_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-/** @addtogroup STM32F10x_System_Includes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @addtogroup STM32F10x_System_Exported_types\r
- * @{\r
- */\r
-\r
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Exported_Constants\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Exported_Functions\r
- * @{\r
- */\r
- \r
-extern void SystemInit(void);\r
-extern void SystemCoreClockUpdate(void);\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__SYSTEM_STM32F10X_H */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/**\r
- * @}\r
- */ \r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file system_stm32l1xx.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.\r
- ****************************************************************************** \r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */\r
-\r
-/** @addtogroup CMSIS\r
- * @{\r
- */\r
-\r
-/** @addtogroup stm32l1xx_system\r
- * @{\r
- */ \r
- \r
-/**\r
- * @brief Define to prevent recursive inclusion\r
- */\r
-#ifndef __SYSTEM_STM32L1XX_H\r
-#define __SYSTEM_STM32L1XX_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-/** @addtogroup STM32L1xx_System_Includes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @addtogroup STM32L1xx_System_Exported_types\r
- * @{\r
- */\r
-\r
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32L1xx_System_Exported_Constants\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32L1xx_System_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32L1xx_System_Exported_Functions\r
- * @{\r
- */\r
- \r
-extern void SystemInit(void);\r
-extern void SystemCoreClockUpdate(void);\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__SYSTEM_STM32L1XX_H */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/**\r
- * @}\r
- */ \r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file misc.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the miscellaneous\r
- * firmware library functions (add-on to CMSIS functions).\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __MISC_H\r
-#define __MISC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup MISC\r
- * @{\r
- */\r
-\r
-/** @defgroup MISC_Exported_Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief NVIC Init Structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.\r
- This parameter can be a value of @ref IRQn_Type \r
- (For the complete STM32 Devices IRQ Channels list, please\r
- refer to stm32f10x.h file) */\r
-\r
- uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel\r
- specified in NVIC_IRQChannel. This parameter can be a value\r
- between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
-\r
- uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified\r
- in NVIC_IRQChannel. This parameter can be a value\r
- between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
-\r
- FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel\r
- will be enabled or disabled. \r
- This parameter can be set either to ENABLE or DISABLE */ \r
-} NVIC_InitTypeDef;\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup NVIC_Priority_Table \r
- * @{\r
- */\r
-\r
-/**\r
-@code \r
- The table below gives the allowed values of the pre-emption priority and subpriority according\r
- to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function\r
- ============================================================================================================================\r
- NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description\r
- ============================================================================================================================\r
- NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority\r
- | | | 4 bits for subpriority\r
- ----------------------------------------------------------------------------------------------------------------------------\r
- NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority\r
- | | | 3 bits for subpriority\r
- ---------------------------------------------------------------------------------------------------------------------------- \r
- NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority\r
- | | | 2 bits for subpriority\r
- ---------------------------------------------------------------------------------------------------------------------------- \r
- NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority\r
- | | | 1 bits for subpriority\r
- ---------------------------------------------------------------------------------------------------------------------------- \r
- NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority\r
- | | | 0 bits for subpriority \r
- ============================================================================================================================\r
-@endcode\r
-*/\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup Vector_Table_Base \r
- * @{\r
- */\r
-\r
-#define NVIC_VectTab_RAM ((uint32_t)0x20000000)\r
-#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)\r
-#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \\r
- ((VECTTAB) == NVIC_VectTab_FLASH))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup System_Low_Power \r
- * @{\r
- */\r
-\r
-#define NVIC_LP_SEVONPEND ((uint8_t)0x10)\r
-#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)\r
-#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)\r
-#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \\r
- ((LP) == NVIC_LP_SLEEPDEEP) || \\r
- ((LP) == NVIC_LP_SLEEPONEXIT))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Preemption_Priority_Group \r
- * @{\r
- */\r
-\r
-#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority\r
- 4 bits for subpriority */\r
-#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority\r
- 3 bits for subpriority */\r
-#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority\r
- 2 bits for subpriority */\r
-#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority\r
- 1 bits for subpriority */\r
-#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority\r
- 0 bits for subpriority */\r
-\r
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \\r
- ((GROUP) == NVIC_PriorityGroup_1) || \\r
- ((GROUP) == NVIC_PriorityGroup_2) || \\r
- ((GROUP) == NVIC_PriorityGroup_3) || \\r
- ((GROUP) == NVIC_PriorityGroup_4))\r
-\r
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
-\r
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
-\r
-#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SysTick_clock_source \r
- * @{\r
- */\r
-\r
-#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)\r
-#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)\r
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \\r
- ((SOURCE) == SysTick_CLKSource_HCLK_Div8))\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Exported_Functions\r
- * @{\r
- */\r
-\r
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);\r
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);\r
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);\r
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);\r
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __MISC_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_adc.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the ADC firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_ADC_H\r
-#define __STM32F10x_ADC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup ADC\r
- * @{\r
- */\r
-\r
-/** @defgroup ADC_Exported_Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief ADC Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or\r
- dual mode. \r
- This parameter can be a value of @ref ADC_mode */\r
-\r
- FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in\r
- Scan (multichannels) or Single (one channel) mode.\r
- This parameter can be set to ENABLE or DISABLE */\r
-\r
- FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in\r
- Continuous or Single mode.\r
- This parameter can be set to ENABLE or DISABLE. */\r
-\r
- uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog\r
- to digital conversion of regular channels. This parameter\r
- can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */\r
-\r
- uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.\r
- This parameter can be a value of @ref ADC_data_align */\r
-\r
- uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted\r
- using the sequencer for regular channel group.\r
- This parameter must range from 1 to 16. */\r
-}ADC_InitTypeDef;\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Exported_Constants\r
- * @{\r
- */\r
-\r
-#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \\r
- ((PERIPH) == ADC2) || \\r
- ((PERIPH) == ADC3))\r
-\r
-#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \\r
- ((PERIPH) == ADC3))\r
-\r
-/** @defgroup ADC_mode \r
- * @{\r
- */\r
-\r
-#define ADC_Mode_Independent ((uint32_t)0x00000000)\r
-#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)\r
-#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)\r
-#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)\r
-#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)\r
-#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)\r
-#define ADC_Mode_RegSimult ((uint32_t)0x00060000)\r
-#define ADC_Mode_FastInterl ((uint32_t)0x00070000)\r
-#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)\r
-#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)\r
-\r
-#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \\r
- ((MODE) == ADC_Mode_RegInjecSimult) || \\r
- ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \\r
- ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \\r
- ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \\r
- ((MODE) == ADC_Mode_InjecSimult) || \\r
- ((MODE) == ADC_Mode_RegSimult) || \\r
- ((MODE) == ADC_Mode_FastInterl) || \\r
- ((MODE) == ADC_Mode_SlowInterl) || \\r
- ((MODE) == ADC_Mode_AlterTrig))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion \r
- * @{\r
- */\r
-\r
-#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */\r
-#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */\r
-#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */\r
-#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */\r
-#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */\r
-#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */\r
-\r
-#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */\r
-#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */\r
-\r
-#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */\r
-#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */\r
-#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */\r
-#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */\r
-#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */\r
-#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */\r
-\r
-#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_None) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_data_align \r
- * @{\r
- */\r
-\r
-#define ADC_DataAlign_Right ((uint32_t)0x00000000)\r
-#define ADC_DataAlign_Left ((uint32_t)0x00000800)\r
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \\r
- ((ALIGN) == ADC_DataAlign_Left))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_channels \r
- * @{\r
- */\r
-\r
-#define ADC_Channel_0 ((uint8_t)0x00)\r
-#define ADC_Channel_1 ((uint8_t)0x01)\r
-#define ADC_Channel_2 ((uint8_t)0x02)\r
-#define ADC_Channel_3 ((uint8_t)0x03)\r
-#define ADC_Channel_4 ((uint8_t)0x04)\r
-#define ADC_Channel_5 ((uint8_t)0x05)\r
-#define ADC_Channel_6 ((uint8_t)0x06)\r
-#define ADC_Channel_7 ((uint8_t)0x07)\r
-#define ADC_Channel_8 ((uint8_t)0x08)\r
-#define ADC_Channel_9 ((uint8_t)0x09)\r
-#define ADC_Channel_10 ((uint8_t)0x0A)\r
-#define ADC_Channel_11 ((uint8_t)0x0B)\r
-#define ADC_Channel_12 ((uint8_t)0x0C)\r
-#define ADC_Channel_13 ((uint8_t)0x0D)\r
-#define ADC_Channel_14 ((uint8_t)0x0E)\r
-#define ADC_Channel_15 ((uint8_t)0x0F)\r
-#define ADC_Channel_16 ((uint8_t)0x10)\r
-#define ADC_Channel_17 ((uint8_t)0x11)\r
-\r
-#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)\r
-#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)\r
-\r
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \\r
- ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \\r
- ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \\r
- ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \\r
- ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \\r
- ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \\r
- ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \\r
- ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \\r
- ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_sampling_time \r
- * @{\r
- */\r
-\r
-#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)\r
-#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)\r
-#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)\r
-#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)\r
-#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)\r
-#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)\r
-#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)\r
-#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)\r
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \\r
- ((TIME) == ADC_SampleTime_7Cycles5) || \\r
- ((TIME) == ADC_SampleTime_13Cycles5) || \\r
- ((TIME) == ADC_SampleTime_28Cycles5) || \\r
- ((TIME) == ADC_SampleTime_41Cycles5) || \\r
- ((TIME) == ADC_SampleTime_55Cycles5) || \\r
- ((TIME) == ADC_SampleTime_71Cycles5) || \\r
- ((TIME) == ADC_SampleTime_239Cycles5))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion \r
- * @{\r
- */\r
-\r
-#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */\r
-#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */\r
-#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */\r
-#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */\r
-#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */\r
-\r
-#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */\r
-#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */\r
-#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */\r
-\r
-#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */\r
-#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */\r
-#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */\r
-#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */\r
-#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */\r
-\r
-#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_injected_channel_selection \r
- * @{\r
- */\r
-\r
-#define ADC_InjectedChannel_1 ((uint8_t)0x14)\r
-#define ADC_InjectedChannel_2 ((uint8_t)0x18)\r
-#define ADC_InjectedChannel_3 ((uint8_t)0x1C)\r
-#define ADC_InjectedChannel_4 ((uint8_t)0x20)\r
-#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \\r
- ((CHANNEL) == ADC_InjectedChannel_2) || \\r
- ((CHANNEL) == ADC_InjectedChannel_3) || \\r
- ((CHANNEL) == ADC_InjectedChannel_4))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_analog_watchdog_selection \r
- * @{\r
- */\r
-\r
-#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)\r
-#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)\r
-#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)\r
-#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)\r
-#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)\r
-#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)\r
-#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)\r
-\r
-#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_None))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_interrupts_definition \r
- * @{\r
- */\r
-\r
-#define ADC_IT_EOC ((uint16_t)0x0220)\r
-#define ADC_IT_AWD ((uint16_t)0x0140)\r
-#define ADC_IT_JEOC ((uint16_t)0x0480)\r
-\r
-#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))\r
-\r
-#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \\r
- ((IT) == ADC_IT_JEOC))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_flags_definition \r
- * @{\r
- */\r
-\r
-#define ADC_FLAG_AWD ((uint8_t)0x01)\r
-#define ADC_FLAG_EOC ((uint8_t)0x02)\r
-#define ADC_FLAG_JEOC ((uint8_t)0x04)\r
-#define ADC_FLAG_JSTRT ((uint8_t)0x08)\r
-#define ADC_FLAG_STRT ((uint8_t)0x10)\r
-#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))\r
-#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \\r
- ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \\r
- ((FLAG) == ADC_FLAG_STRT))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_thresholds \r
- * @{\r
- */\r
-\r
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_injected_offset \r
- * @{\r
- */\r
-\r
-#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_injected_length \r
- * @{\r
- */\r
-\r
-#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_injected_rank \r
- * @{\r
- */\r
-\r
-#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup ADC_regular_length \r
- * @{\r
- */\r
-\r
-#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_regular_rank \r
- * @{\r
- */\r
-\r
-#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_regular_discontinuous_mode_number \r
- * @{\r
- */\r
-\r
-#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Exported_Functions\r
- * @{\r
- */\r
-\r
-void ADC_DeInit(ADC_TypeDef* ADCx);\r
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);\r
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);\r
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);\r
-void ADC_ResetCalibration(ADC_TypeDef* ADCx);\r
-FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);\r
-void ADC_StartCalibration(ADC_TypeDef* ADCx);\r
-FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);\r
-void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);\r
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);\r
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
-void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);\r
-uint32_t ADC_GetDualModeConversionValue(void);\r
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);\r
-void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);\r
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);\r
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);\r
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);\r
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);\r
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);\r
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);\r
-void ADC_TempSensorVrefintCmd(FunctionalState NewState);\r
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);\r
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);\r
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32F10x_ADC_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_bkp.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the BKP firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_BKP_H\r
-#define __STM32F10x_BKP_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup BKP\r
- * @{\r
- */\r
-\r
-/** @defgroup BKP_Exported_Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup BKP_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup Tamper_Pin_active_level \r
- * @{\r
- */\r
-\r
-#define BKP_TamperPinLevel_High ((uint16_t)0x0000)\r
-#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)\r
-#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \\r
- ((LEVEL) == BKP_TamperPinLevel_Low))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin \r
- * @{\r
- */\r
-\r
-#define BKP_RTCOutputSource_None ((uint16_t)0x0000)\r
-#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)\r
-#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)\r
-#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)\r
-#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \\r
- ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \\r
- ((SOURCE) == BKP_RTCOutputSource_Alarm) || \\r
- ((SOURCE) == BKP_RTCOutputSource_Second))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Data_Backup_Register \r
- * @{\r
- */\r
-\r
-#define BKP_DR1 ((uint16_t)0x0004)\r
-#define BKP_DR2 ((uint16_t)0x0008)\r
-#define BKP_DR3 ((uint16_t)0x000C)\r
-#define BKP_DR4 ((uint16_t)0x0010)\r
-#define BKP_DR5 ((uint16_t)0x0014)\r
-#define BKP_DR6 ((uint16_t)0x0018)\r
-#define BKP_DR7 ((uint16_t)0x001C)\r
-#define BKP_DR8 ((uint16_t)0x0020)\r
-#define BKP_DR9 ((uint16_t)0x0024)\r
-#define BKP_DR10 ((uint16_t)0x0028)\r
-#define BKP_DR11 ((uint16_t)0x0040)\r
-#define BKP_DR12 ((uint16_t)0x0044)\r
-#define BKP_DR13 ((uint16_t)0x0048)\r
-#define BKP_DR14 ((uint16_t)0x004C)\r
-#define BKP_DR15 ((uint16_t)0x0050)\r
-#define BKP_DR16 ((uint16_t)0x0054)\r
-#define BKP_DR17 ((uint16_t)0x0058)\r
-#define BKP_DR18 ((uint16_t)0x005C)\r
-#define BKP_DR19 ((uint16_t)0x0060)\r
-#define BKP_DR20 ((uint16_t)0x0064)\r
-#define BKP_DR21 ((uint16_t)0x0068)\r
-#define BKP_DR22 ((uint16_t)0x006C)\r
-#define BKP_DR23 ((uint16_t)0x0070)\r
-#define BKP_DR24 ((uint16_t)0x0074)\r
-#define BKP_DR25 ((uint16_t)0x0078)\r
-#define BKP_DR26 ((uint16_t)0x007C)\r
-#define BKP_DR27 ((uint16_t)0x0080)\r
-#define BKP_DR28 ((uint16_t)0x0084)\r
-#define BKP_DR29 ((uint16_t)0x0088)\r
-#define BKP_DR30 ((uint16_t)0x008C)\r
-#define BKP_DR31 ((uint16_t)0x0090)\r
-#define BKP_DR32 ((uint16_t)0x0094)\r
-#define BKP_DR33 ((uint16_t)0x0098)\r
-#define BKP_DR34 ((uint16_t)0x009C)\r
-#define BKP_DR35 ((uint16_t)0x00A0)\r
-#define BKP_DR36 ((uint16_t)0x00A4)\r
-#define BKP_DR37 ((uint16_t)0x00A8)\r
-#define BKP_DR38 ((uint16_t)0x00AC)\r
-#define BKP_DR39 ((uint16_t)0x00B0)\r
-#define BKP_DR40 ((uint16_t)0x00B4)\r
-#define BKP_DR41 ((uint16_t)0x00B8)\r
-#define BKP_DR42 ((uint16_t)0x00BC)\r
-\r
-#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \\r
- ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \\r
- ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \\r
- ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \\r
- ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \\r
- ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \\r
- ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \\r
- ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \\r
- ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \\r
- ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \\r
- ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \\r
- ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \\r
- ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \\r
- ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))\r
-\r
-#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup BKP_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup BKP_Exported_Functions\r
- * @{\r
- */\r
-\r
-void BKP_DeInit(void);\r
-void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);\r
-void BKP_TamperPinCmd(FunctionalState NewState);\r
-void BKP_ITConfig(FunctionalState NewState);\r
-void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);\r
-void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);\r
-void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);\r
-uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);\r
-FlagStatus BKP_GetFlagStatus(void);\r
-void BKP_ClearFlag(void);\r
-ITStatus BKP_GetITStatus(void);\r
-void BKP_ClearITPendingBit(void);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_BKP_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_can.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the CAN firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_CAN_H\r
-#define __STM32F10x_CAN_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup CAN\r
- * @{\r
- */\r
-\r
-/** @defgroup CAN_Exported_Types\r
- * @{\r
- */\r
-\r
-#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \\r
- ((PERIPH) == CAN2))\r
-\r
-/** \r
- * @brief CAN init structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */\r
- \r
- uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.\r
- This parameter can be a value of @ref CAN_operating_mode */\r
-\r
- uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware\r
- is allowed to lengthen or shorten a bit to perform resynchronization.\r
- This parameter can be a value of @ref CAN_synchronisation_jump_width */\r
-\r
- uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1.\r
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */\r
-\r
- uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.\r
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */\r
- \r
- FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.\r
- This parameter can be set either to ENABLE or DISABLE. */\r
- \r
- FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.\r
- This parameter can be set either to ENABLE or DISABLE. */\r
-\r
- FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. \r
- This parameter can be set either to ENABLE or DISABLE. */\r
-\r
- FunctionalState CAN_NART; /*!< Enable or disable the no-automatic retransmission mode.\r
- This parameter can be set either to ENABLE or DISABLE. */\r
-\r
- FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.\r
- This parameter can be set either to ENABLE or DISABLE. */\r
-\r
- FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.\r
- This parameter can be set either to ENABLE or DISABLE. */\r
-} CAN_InitTypeDef;\r
-\r
-/** \r
- * @brief CAN filter init structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit\r
- configuration, first one for a 16-bit configuration).\r
- This parameter can be a value between 0x0000 and 0xFFFF */\r
-\r
- uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit\r
- configuration, second one for a 16-bit configuration).\r
- This parameter can be a value between 0x0000 and 0xFFFF */\r
-\r
- uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,\r
- according to the mode (MSBs for a 32-bit configuration,\r
- first one for a 16-bit configuration).\r
- This parameter can be a value between 0x0000 and 0xFFFF */\r
-\r
- uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,\r
- according to the mode (LSBs for a 32-bit configuration,\r
- second one for a 16-bit configuration).\r
- This parameter can be a value between 0x0000 and 0xFFFF */\r
-\r
- uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.\r
- This parameter can be a value of @ref CAN_filter_FIFO */\r
- \r
- uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */\r
-\r
- uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.\r
- This parameter can be a value of @ref CAN_filter_mode */\r
-\r
- uint8_t CAN_FilterScale; /*!< Specifies the filter scale.\r
- This parameter can be a value of @ref CAN_filter_scale */\r
-\r
- FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.\r
- This parameter can be set either to ENABLE or DISABLE. */\r
-} CAN_FilterInitTypeDef;\r
-\r
-/** \r
- * @brief CAN Tx message structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t StdId; /*!< Specifies the standard identifier.\r
- This parameter can be a value between 0 to 0x7FF. */\r
-\r
- uint32_t ExtId; /*!< Specifies the extended identifier.\r
- This parameter can be a value between 0 to 0x1FFFFFFF. */\r
-\r
- uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.\r
- This parameter can be a value of @ref CAN_identifier_type */\r
-\r
- uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.\r
- This parameter can be a value of @ref CAN_remote_transmission_request */\r
-\r
- uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted.\r
- This parameter can be a value between 0 to 8 */\r
-\r
- uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */\r
-} CanTxMsg;\r
-\r
-/** \r
- * @brief CAN Rx message structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t StdId; /*!< Specifies the standard identifier.\r
- This parameter can be a value between 0 to 0x7FF. */\r
-\r
- uint32_t ExtId; /*!< Specifies the extended identifier.\r
- This parameter can be a value between 0 to 0x1FFFFFFF. */\r
-\r
- uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received.\r
- This parameter can be a value of @ref CAN_identifier_type */\r
-\r
- uint8_t RTR; /*!< Specifies the type of frame for the received message.\r
- This parameter can be a value of @ref CAN_remote_transmission_request */\r
-\r
- uint8_t DLC; /*!< Specifies the length of the frame that will be received.\r
- This parameter can be a value between 0 to 8 */\r
-\r
- uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */\r
-\r
- uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.\r
- This parameter can be a value between 0 to 0xFF */\r
-} CanRxMsg;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup CAN_sleep_constants \r
- * @{\r
- */\r
-\r
-#define CANINITFAILED ((uint8_t)0x00) /*!< CAN initialization failed */\r
-#define CANINITOK ((uint8_t)0x01) /*!< CAN initialization failed */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_operating_mode \r
- * @{\r
- */\r
-\r
-#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */\r
-#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */\r
-#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */\r
-#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */\r
-\r
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \\r
- ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_synchronisation_jump_width \r
- * @{\r
- */\r
-\r
-#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */\r
-#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */\r
-#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */\r
-#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */\r
-\r
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \\r
- ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_time_quantum_in_bit_segment_1 \r
- * @{\r
- */\r
-\r
-#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */\r
-#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */\r
-#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */\r
-#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */\r
-#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */\r
-#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */\r
-#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */\r
-#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */\r
-#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */\r
-#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */\r
-#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */\r
-#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */\r
-#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */\r
-#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */\r
-#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */\r
-#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */\r
-\r
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_time_quantum_in_bit_segment_2 \r
- * @{\r
- */\r
-\r
-#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */\r
-#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */\r
-#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */\r
-#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */\r
-#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */\r
-#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */\r
-#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */\r
-#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */\r
-\r
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_clock_prescaler \r
- * @{\r
- */\r
-\r
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_filter_number \r
- * @{\r
- */\r
-#ifndef STM32F10X_CL\r
- #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)\r
-#else\r
- #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)\r
-#endif /* STM32F10X_CL */ \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_filter_mode \r
- * @{\r
- */\r
-\r
-#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< id/mask mode */\r
-#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */\r
-\r
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \\r
- ((MODE) == CAN_FilterMode_IdList))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_filter_scale \r
- * @{\r
- */\r
-\r
-#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */\r
-#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */\r
-\r
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \\r
- ((SCALE) == CAN_FilterScale_32bit))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_filter_FIFO\r
- * @{\r
- */\r
-\r
-#define CAN_FilterFIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */\r
-#define CAN_FilterFIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */\r
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \\r
- ((FIFO) == CAN_FilterFIFO1))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Start_bank_filter_for_slave_CAN \r
- * @{\r
- */\r
-#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_Tx \r
- * @{\r
- */\r
-\r
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))\r
-#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))\r
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))\r
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_identifier_type \r
- * @{\r
- */\r
-\r
-#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */\r
-#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */\r
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_remote_transmission_request \r
- * @{\r
- */\r
-\r
-#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */\r
-#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */\r
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_transmit_constants \r
- * @{\r
- */\r
-\r
-#define CANTXFAILED ((uint8_t)0x00) /*!< CAN transmission failed */\r
-#define CANTXOK ((uint8_t)0x01) /*!< CAN transmission succeeded */\r
-#define CANTXPENDING ((uint8_t)0x02) /*!< CAN transmission pending */\r
-#define CAN_NO_MB ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_receive_FIFO_number_constants \r
- * @{\r
- */\r
-\r
-#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO0 used to receive */\r
-#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO1 used to receive */\r
-\r
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_sleep_constants \r
- * @{\r
- */\r
-\r
-#define CANSLEEPFAILED ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */\r
-#define CANSLEEPOK ((uint8_t)0x01) /*!< CAN entered the sleep mode */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_wake_up_constants \r
- * @{\r
- */\r
-\r
-#define CANWAKEUPFAILED ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */\r
-#define CANWAKEUPOK ((uint8_t)0x01) /*!< CAN leaved the sleep mode */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_flags \r
- * @{\r
- */\r
-\r
-#define CAN_FLAG_EWG ((uint32_t)0x00000001) /*!< Error Warning Flag */\r
-#define CAN_FLAG_EPV ((uint32_t)0x00000002) /*!< Error Passive Flag */\r
-#define CAN_FLAG_BOF ((uint32_t)0x00000004) /*!< Bus-Off Flag */\r
-\r
-#define IS_CAN_FLAG(FLAG) (((FLAG) == CAN_FLAG_EWG) || ((FLAG) == CAN_FLAG_EPV) ||\\r
- ((FLAG) == CAN_FLAG_BOF))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_interrupts \r
- * @{\r
- */\r
-\r
-#define CAN_IT_RQCP0 ((uint32_t)0x00000005) /*!< Request completed mailbox 0 */\r
-#define CAN_IT_RQCP1 ((uint32_t)0x00000006) /*!< Request completed mailbox 1 */\r
-#define CAN_IT_RQCP2 ((uint32_t)0x00000007) /*!< Request completed mailbox 2 */\r
-#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty */\r
-#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending */\r
-#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full */\r
-#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun */\r
-#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending */\r
-#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full */\r
-#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun */\r
-#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning */\r
-#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive */\r
-#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off */\r
-#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code */\r
-#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error */\r
-#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up */\r
-#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep */\r
-\r
-#define IS_CAN_ITConfig(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\\r
- ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\\r
- ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\\r
- ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\\r
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\\r
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\\r
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))\r
-\r
-#define IS_CAN_ITStatus(IT) (((IT) == CAN_IT_RQCP0) || ((IT) == CAN_IT_RQCP1) ||\\r
- ((IT) == CAN_IT_RQCP2) || ((IT) == CAN_IT_FF0) ||\\r
- ((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\\r
- ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\\r
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\\r
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_Exported_Functions\r
- * @{\r
- */\r
-\r
-void CAN_DeInit(CAN_TypeDef* CANx);\r
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);\r
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);\r
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);\r
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber); \r
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);\r
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);\r
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);\r
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);\r
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);\r
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);\r
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);\r
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);\r
-uint8_t CAN_Sleep(CAN_TypeDef* CANx);\r
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx);\r
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);\r
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);\r
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);\r
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_CAN_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_cec.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the CEC firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_CEC_H\r
-#define __STM32F10x_CEC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup CEC\r
- * @{\r
- */\r
- \r
-\r
-/** @defgroup CEC_Exported_Types\r
- * @{\r
- */\r
- \r
-/** \r
- * @brief CEC Init structure definition \r
- */ \r
-typedef struct\r
-{\r
- uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. \r
- This parameter can be a value of @ref CEC_BitTiming_Mode */\r
- uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. \r
- This parameter can be a value of @ref CEC_BitPeriod_Mode */\r
-}CEC_InitTypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CEC_Exported_Constants\r
- * @{\r
- */ \r
- \r
-/** @defgroup CEC_BitTiming_Mode \r
- * @{\r
- */ \r
-#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */\r
-#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */\r
-\r
-#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \\r
- ((MODE) == CEC_BitTimingErrFreeMode))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CEC_BitPeriod_Mode \r
- * @{\r
- */ \r
-#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */\r
-#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */\r
-\r
-#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \\r
- ((MODE) == CEC_BitPeriodFlexibleMode))\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup CEC_interrupts_definition \r
- * @{\r
- */ \r
-#define CEC_IT_TERR CEC_CSR_TERR\r
-#define CEC_IT_TBTRF CEC_CSR_TBTRF\r
-#define CEC_IT_RERR CEC_CSR_RERR\r
-#define CEC_IT_RBTF CEC_CSR_RBTF\r
-#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \\r
- ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup CEC_Own_Addres \r
- * @{\r
- */ \r
-#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup CEC_Prescaler \r
- * @{\r
- */ \r
-#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CEC_flags_definition \r
- * @{\r
- */\r
- \r
-/** \r
- * @brief ESR register flags \r
- */ \r
-#define CEC_FLAG_BTE ((uint32_t)0x10010000)\r
-#define CEC_FLAG_BPE ((uint32_t)0x10020000)\r
-#define CEC_FLAG_RBTFE ((uint32_t)0x10040000)\r
-#define CEC_FLAG_SBE ((uint32_t)0x10080000)\r
-#define CEC_FLAG_ACKE ((uint32_t)0x10100000)\r
-#define CEC_FLAG_LINE ((uint32_t)0x10200000)\r
-#define CEC_FLAG_TBTFE ((uint32_t)0x10400000)\r
-\r
-/** \r
- * @brief CSR register flags \r
- */ \r
-#define CEC_FLAG_TEOM ((uint32_t)0x00000002) \r
-#define CEC_FLAG_TERR ((uint32_t)0x00000004)\r
-#define CEC_FLAG_TBTRF ((uint32_t)0x00000008)\r
-#define CEC_FLAG_RSOM ((uint32_t)0x00000010)\r
-#define CEC_FLAG_REOM ((uint32_t)0x00000020)\r
-#define CEC_FLAG_RERR ((uint32_t)0x00000040)\r
-#define CEC_FLAG_RBTF ((uint32_t)0x00000080)\r
-\r
-#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))\r
- \r
-#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \\r
- ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \\r
- ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \\r
- ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \\r
- ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \\r
- ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \\r
- ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup CEC_Exported_Macros\r
- * @{\r
- */\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CEC_Exported_Functions\r
- * @{\r
- */ \r
-void CEC_DeInit(void);\r
-void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);\r
-void CEC_Cmd(FunctionalState NewState);\r
-void CEC_ITConfig(FunctionalState NewState);\r
-void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);\r
-void CEC_SetPrescaler(uint16_t CEC_Prescaler);\r
-void CEC_SendDataByte(uint8_t Data);\r
-uint8_t CEC_ReceiveDataByte(void);\r
-void CEC_StartOfMessage(void);\r
-void CEC_EndOfMessageCmd(FunctionalState NewState);\r
-FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);\r
-void CEC_ClearFlag(uint32_t CEC_FLAG);\r
-ITStatus CEC_GetITStatus(uint8_t CEC_IT);\r
-void CEC_ClearITPendingBit(uint16_t CEC_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_CEC_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_crc.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the CRC firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_CRC_H\r
-#define __STM32F10x_CRC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup CRC\r
- * @{\r
- */\r
-\r
-/** @defgroup CRC_Exported_Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CRC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CRC_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CRC_Exported_Functions\r
- * @{\r
- */\r
-\r
-void CRC_ResetDR(void);\r
-uint32_t CRC_CalcCRC(uint32_t Data);\r
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);\r
-uint32_t CRC_GetCRC(void);\r
-void CRC_SetIDRegister(uint8_t IDValue);\r
-uint8_t CRC_GetIDRegister(void);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_CRC_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_dac.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the DAC firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_DAC_H\r
-#define __STM32F10x_DAC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup DAC\r
- * @{\r
- */\r
-\r
-/** @defgroup DAC_Exported_Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief DAC Init structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.\r
- This parameter can be a value of @ref DAC_trigger_selection */\r
-\r
- uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves\r
- are generated, or whether no wave is generated.\r
- This parameter can be a value of @ref DAC_wave_generation */\r
-\r
- uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or\r
- the maximum amplitude triangle generation for the DAC channel. \r
- This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */\r
-\r
- uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.\r
- This parameter can be a value of @ref DAC_output_buffer */\r
-}DAC_InitTypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup DAC_trigger_selection \r
- * @{\r
- */\r
-\r
-#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \r
- has been loaded, and not by external trigger */\r
-#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel\r
- only in High-density devices*/\r
-#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel\r
- only in Connectivity line, Medium-density and Low-density Value Line devices */\r
-#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel \r
- only in Medium-density and Low-density Value Line devices*/\r
-#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */\r
-\r
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \\r
- ((TRIGGER) == DAC_Trigger_T6_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_T8_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_T7_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_T5_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_T2_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_T4_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_Ext_IT9) || \\r
- ((TRIGGER) == DAC_Trigger_Software))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_wave_generation \r
- * @{\r
- */\r
-\r
-#define DAC_WaveGeneration_None ((uint32_t)0x00000000)\r
-#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)\r
-#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)\r
-#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \\r
- ((WAVE) == DAC_WaveGeneration_Noise) || \\r
- ((WAVE) == DAC_WaveGeneration_Triangle))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_lfsrunmask_triangleamplitude\r
- * @{\r
- */\r
-\r
-#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */\r
-#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */\r
-#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */\r
-#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */\r
-#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */\r
-#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */\r
-#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */\r
-#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */\r
-#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */\r
-#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */\r
-#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */\r
-#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */\r
-#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */\r
-\r
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \\r
- ((VALUE) == DAC_TriangleAmplitude_1) || \\r
- ((VALUE) == DAC_TriangleAmplitude_3) || \\r
- ((VALUE) == DAC_TriangleAmplitude_7) || \\r
- ((VALUE) == DAC_TriangleAmplitude_15) || \\r
- ((VALUE) == DAC_TriangleAmplitude_31) || \\r
- ((VALUE) == DAC_TriangleAmplitude_63) || \\r
- ((VALUE) == DAC_TriangleAmplitude_127) || \\r
- ((VALUE) == DAC_TriangleAmplitude_255) || \\r
- ((VALUE) == DAC_TriangleAmplitude_511) || \\r
- ((VALUE) == DAC_TriangleAmplitude_1023) || \\r
- ((VALUE) == DAC_TriangleAmplitude_2047) || \\r
- ((VALUE) == DAC_TriangleAmplitude_4095))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_output_buffer \r
- * @{\r
- */\r
-\r
-#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)\r
-#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)\r
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \\r
- ((STATE) == DAC_OutputBuffer_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Channel_selection \r
- * @{\r
- */\r
-\r
-#define DAC_Channel_1 ((uint32_t)0x00000000)\r
-#define DAC_Channel_2 ((uint32_t)0x00000010)\r
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \\r
- ((CHANNEL) == DAC_Channel_2))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_data_alignement \r
- * @{\r
- */\r
-\r
-#define DAC_Align_12b_R ((uint32_t)0x00000000)\r
-#define DAC_Align_12b_L ((uint32_t)0x00000004)\r
-#define DAC_Align_8b_R ((uint32_t)0x00000008)\r
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \\r
- ((ALIGN) == DAC_Align_12b_L) || \\r
- ((ALIGN) == DAC_Align_8b_R))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_wave_generation \r
- * @{\r
- */\r
-\r
-#define DAC_Wave_Noise ((uint32_t)0x00000040)\r
-#define DAC_Wave_Triangle ((uint32_t)0x00000080)\r
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \\r
- ((WAVE) == DAC_Wave_Triangle))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_data \r
- * @{\r
- */\r
-\r
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) \r
-/**\r
- * @}\r
- */\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) \r
-/** @defgroup DAC_interrupts_definition \r
- * @{\r
- */ \r
- \r
-#define DAC_IT_DMAUDR ((uint32_t)0x00002000) \r
-#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup DAC_flags_definition \r
- * @{\r
- */ \r
- \r
-#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) \r
-#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) \r
-\r
-/**\r
- * @}\r
- */\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Exported_Functions\r
- * @{\r
- */\r
-\r
-void DAC_DeInit(void);\r
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);\r
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);\r
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) \r
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);\r
-#endif\r
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);\r
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);\r
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);\r
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);\r
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);\r
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);\r
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);\r
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) \r
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);\r
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);\r
-#endif\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32F10x_DAC_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_dbgmcu.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the DBGMCU \r
- * firmware library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_DBGMCU_H\r
-#define __STM32F10x_DBGMCU_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup DBGMCU\r
- * @{\r
- */\r
-\r
-/** @defgroup DBGMCU_Exported_Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DBGMCU_Exported_Constants\r
- * @{\r
- */\r
-\r
-#define DBGMCU_SLEEP ((uint32_t)0x00000001)\r
-#define DBGMCU_STOP ((uint32_t)0x00000002)\r
-#define DBGMCU_STANDBY ((uint32_t)0x00000004)\r
-#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)\r
-#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)\r
-#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)\r
-#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)\r
-#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)\r
-#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)\r
-#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)\r
-#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)\r
-#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)\r
-#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)\r
-#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)\r
-#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)\r
-#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)\r
-#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)\r
-#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)\r
-#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)\r
-#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)\r
-#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)\r
-#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)\r
-#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)\r
-#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)\r
-#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)\r
-#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)\r
- \r
-#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup DBGMCU_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DBGMCU_Exported_Functions\r
- * @{\r
- */\r
-\r
-uint32_t DBGMCU_GetREVID(void);\r
-uint32_t DBGMCU_GetDEVID(void);\r
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_DBGMCU_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_dma.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the DMA firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_DMA_H\r
-#define __STM32F10x_DMA_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup DMA\r
- * @{\r
- */\r
-\r
-/** @defgroup DMA_Exported_Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief DMA Init structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */\r
-\r
- uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */\r
-\r
- uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.\r
- This parameter can be a value of @ref DMA_data_transfer_direction */\r
-\r
- uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. \r
- The data unit is equal to the configuration set in DMA_PeripheralDataSize\r
- or DMA_MemoryDataSize members depending in the transfer direction. */\r
-\r
- uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.\r
- This parameter can be a value of @ref DMA_peripheral_incremented_mode */\r
-\r
- uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.\r
- This parameter can be a value of @ref DMA_memory_incremented_mode */\r
-\r
- uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.\r
- This parameter can be a value of @ref DMA_peripheral_data_size */\r
-\r
- uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.\r
- This parameter can be a value of @ref DMA_memory_data_size */\r
-\r
- uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.\r
- This parameter can be a value of @ref DMA_circular_normal_mode.\r
- @note: The circular buffer mode cannot be used if the memory-to-memory\r
- data transfer is configured on the selected Channel */\r
-\r
- uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.\r
- This parameter can be a value of @ref DMA_priority_level */\r
-\r
- uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.\r
- This parameter can be a value of @ref DMA_memory_to_memory */\r
-}DMA_InitTypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Exported_Constants\r
- * @{\r
- */\r
-\r
-#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \\r
- ((PERIPH) == DMA1_Channel2) || \\r
- ((PERIPH) == DMA1_Channel3) || \\r
- ((PERIPH) == DMA1_Channel4) || \\r
- ((PERIPH) == DMA1_Channel5) || \\r
- ((PERIPH) == DMA1_Channel6) || \\r
- ((PERIPH) == DMA1_Channel7) || \\r
- ((PERIPH) == DMA2_Channel1) || \\r
- ((PERIPH) == DMA2_Channel2) || \\r
- ((PERIPH) == DMA2_Channel3) || \\r
- ((PERIPH) == DMA2_Channel4) || \\r
- ((PERIPH) == DMA2_Channel5))\r
-\r
-/** @defgroup DMA_data_transfer_direction \r
- * @{\r
- */\r
-\r
-#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)\r
-#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)\r
-#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \\r
- ((DIR) == DMA_DIR_PeripheralSRC))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_peripheral_incremented_mode \r
- * @{\r
- */\r
-\r
-#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)\r
-#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)\r
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \\r
- ((STATE) == DMA_PeripheralInc_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_memory_incremented_mode \r
- * @{\r
- */\r
-\r
-#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)\r
-#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)\r
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \\r
- ((STATE) == DMA_MemoryInc_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_peripheral_data_size \r
- * @{\r
- */\r
-\r
-#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)\r
-#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)\r
-#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)\r
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \\r
- ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \\r
- ((SIZE) == DMA_PeripheralDataSize_Word))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_memory_data_size \r
- * @{\r
- */\r
-\r
-#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)\r
-#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)\r
-#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)\r
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \\r
- ((SIZE) == DMA_MemoryDataSize_HalfWord) || \\r
- ((SIZE) == DMA_MemoryDataSize_Word))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_circular_normal_mode \r
- * @{\r
- */\r
-\r
-#define DMA_Mode_Circular ((uint32_t)0x00000020)\r
-#define DMA_Mode_Normal ((uint32_t)0x00000000)\r
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_priority_level \r
- * @{\r
- */\r
-\r
-#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)\r
-#define DMA_Priority_High ((uint32_t)0x00002000)\r
-#define DMA_Priority_Medium ((uint32_t)0x00001000)\r
-#define DMA_Priority_Low ((uint32_t)0x00000000)\r
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \\r
- ((PRIORITY) == DMA_Priority_High) || \\r
- ((PRIORITY) == DMA_Priority_Medium) || \\r
- ((PRIORITY) == DMA_Priority_Low))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_memory_to_memory \r
- * @{\r
- */\r
-\r
-#define DMA_M2M_Enable ((uint32_t)0x00004000)\r
-#define DMA_M2M_Disable ((uint32_t)0x00000000)\r
-#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_interrupts_definition \r
- * @{\r
- */\r
-\r
-#define DMA_IT_TC ((uint32_t)0x00000002)\r
-#define DMA_IT_HT ((uint32_t)0x00000004)\r
-#define DMA_IT_TE ((uint32_t)0x00000008)\r
-#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))\r
-\r
-#define DMA1_IT_GL1 ((uint32_t)0x00000001)\r
-#define DMA1_IT_TC1 ((uint32_t)0x00000002)\r
-#define DMA1_IT_HT1 ((uint32_t)0x00000004)\r
-#define DMA1_IT_TE1 ((uint32_t)0x00000008)\r
-#define DMA1_IT_GL2 ((uint32_t)0x00000010)\r
-#define DMA1_IT_TC2 ((uint32_t)0x00000020)\r
-#define DMA1_IT_HT2 ((uint32_t)0x00000040)\r
-#define DMA1_IT_TE2 ((uint32_t)0x00000080)\r
-#define DMA1_IT_GL3 ((uint32_t)0x00000100)\r
-#define DMA1_IT_TC3 ((uint32_t)0x00000200)\r
-#define DMA1_IT_HT3 ((uint32_t)0x00000400)\r
-#define DMA1_IT_TE3 ((uint32_t)0x00000800)\r
-#define DMA1_IT_GL4 ((uint32_t)0x00001000)\r
-#define DMA1_IT_TC4 ((uint32_t)0x00002000)\r
-#define DMA1_IT_HT4 ((uint32_t)0x00004000)\r
-#define DMA1_IT_TE4 ((uint32_t)0x00008000)\r
-#define DMA1_IT_GL5 ((uint32_t)0x00010000)\r
-#define DMA1_IT_TC5 ((uint32_t)0x00020000)\r
-#define DMA1_IT_HT5 ((uint32_t)0x00040000)\r
-#define DMA1_IT_TE5 ((uint32_t)0x00080000)\r
-#define DMA1_IT_GL6 ((uint32_t)0x00100000)\r
-#define DMA1_IT_TC6 ((uint32_t)0x00200000)\r
-#define DMA1_IT_HT6 ((uint32_t)0x00400000)\r
-#define DMA1_IT_TE6 ((uint32_t)0x00800000)\r
-#define DMA1_IT_GL7 ((uint32_t)0x01000000)\r
-#define DMA1_IT_TC7 ((uint32_t)0x02000000)\r
-#define DMA1_IT_HT7 ((uint32_t)0x04000000)\r
-#define DMA1_IT_TE7 ((uint32_t)0x08000000)\r
-\r
-#define DMA2_IT_GL1 ((uint32_t)0x10000001)\r
-#define DMA2_IT_TC1 ((uint32_t)0x10000002)\r
-#define DMA2_IT_HT1 ((uint32_t)0x10000004)\r
-#define DMA2_IT_TE1 ((uint32_t)0x10000008)\r
-#define DMA2_IT_GL2 ((uint32_t)0x10000010)\r
-#define DMA2_IT_TC2 ((uint32_t)0x10000020)\r
-#define DMA2_IT_HT2 ((uint32_t)0x10000040)\r
-#define DMA2_IT_TE2 ((uint32_t)0x10000080)\r
-#define DMA2_IT_GL3 ((uint32_t)0x10000100)\r
-#define DMA2_IT_TC3 ((uint32_t)0x10000200)\r
-#define DMA2_IT_HT3 ((uint32_t)0x10000400)\r
-#define DMA2_IT_TE3 ((uint32_t)0x10000800)\r
-#define DMA2_IT_GL4 ((uint32_t)0x10001000)\r
-#define DMA2_IT_TC4 ((uint32_t)0x10002000)\r
-#define DMA2_IT_HT4 ((uint32_t)0x10004000)\r
-#define DMA2_IT_TE4 ((uint32_t)0x10008000)\r
-#define DMA2_IT_GL5 ((uint32_t)0x10010000)\r
-#define DMA2_IT_TC5 ((uint32_t)0x10020000)\r
-#define DMA2_IT_HT5 ((uint32_t)0x10040000)\r
-#define DMA2_IT_TE5 ((uint32_t)0x10080000)\r
-\r
-#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))\r
-\r
-#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \\r
- ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \\r
- ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \\r
- ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \\r
- ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \\r
- ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \\r
- ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \\r
- ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \\r
- ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \\r
- ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \\r
- ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \\r
- ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \\r
- ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \\r
- ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \\r
- ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \\r
- ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \\r
- ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \\r
- ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \\r
- ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \\r
- ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \\r
- ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \\r
- ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \\r
- ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \\r
- ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_flags_definition \r
- * @{\r
- */\r
-#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)\r
-#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)\r
-#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)\r
-#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)\r
-#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)\r
-#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)\r
-#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)\r
-#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)\r
-#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)\r
-#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)\r
-#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)\r
-#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)\r
-#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)\r
-#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)\r
-#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)\r
-#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)\r
-#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)\r
-#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)\r
-#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)\r
-#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)\r
-#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)\r
-#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)\r
-#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)\r
-#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)\r
-#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)\r
-#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)\r
-#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)\r
-#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)\r
-\r
-#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)\r
-#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)\r
-#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)\r
-#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)\r
-#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)\r
-#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)\r
-#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)\r
-#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)\r
-#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)\r
-#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)\r
-#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)\r
-#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)\r
-#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)\r
-#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)\r
-#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)\r
-#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)\r
-#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)\r
-#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)\r
-#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)\r
-#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)\r
-\r
-#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))\r
-\r
-#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \\r
- ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \\r
- ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \\r
- ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \\r
- ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \\r
- ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \\r
- ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \\r
- ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \\r
- ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \\r
- ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \\r
- ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \\r
- ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \\r
- ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \\r
- ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \\r
- ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \\r
- ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \\r
- ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \\r
- ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \\r
- ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \\r
- ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \\r
- ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \\r
- ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \\r
- ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \\r
- ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Buffer_Size \r
- * @{\r
- */\r
-\r
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Exported_Functions\r
- * @{\r
- */\r
-\r
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);\r
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);\r
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);\r
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);\r
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);\r
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);\r
-FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);\r
-void DMA_ClearFlag(uint32_t DMA_FLAG);\r
-ITStatus DMA_GetITStatus(uint32_t DMA_IT);\r
-void DMA_ClearITPendingBit(uint32_t DMA_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32F10x_DMA_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_exti.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the EXTI firmware\r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_EXTI_H\r
-#define __STM32F10x_EXTI_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup EXTI\r
- * @{\r
- */\r
-\r
-/** @defgroup EXTI_Exported_Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief EXTI mode enumeration \r
- */\r
-\r
-typedef enum\r
-{\r
- EXTI_Mode_Interrupt = 0x00,\r
- EXTI_Mode_Event = 0x04\r
-}EXTIMode_TypeDef;\r
-\r
-#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))\r
-\r
-/** \r
- * @brief EXTI Trigger enumeration \r
- */\r
-\r
-typedef enum\r
-{\r
- EXTI_Trigger_Rising = 0x08,\r
- EXTI_Trigger_Falling = 0x0C, \r
- EXTI_Trigger_Rising_Falling = 0x10\r
-}EXTITrigger_TypeDef;\r
-\r
-#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \\r
- ((TRIGGER) == EXTI_Trigger_Falling) || \\r
- ((TRIGGER) == EXTI_Trigger_Rising_Falling))\r
-/** \r
- * @brief EXTI Init Structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.\r
- This parameter can be any combination of @ref EXTI_Lines */\r
- \r
- EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.\r
- This parameter can be a value of @ref EXTIMode_TypeDef */\r
-\r
- EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.\r
- This parameter can be a value of @ref EXTIMode_TypeDef */\r
-\r
- FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.\r
- This parameter can be set either to ENABLE or DISABLE */ \r
-}EXTI_InitTypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup EXTI_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup EXTI_Lines \r
- * @{\r
- */\r
-\r
-#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */\r
-#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */\r
-#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */\r
-#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */\r
-#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */\r
-#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */\r
-#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */\r
-#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */\r
-#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */\r
-#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */\r
-#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */\r
-#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */\r
-#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */\r
-#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */\r
-#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */\r
-#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */\r
-#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */\r
-#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */\r
-#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS\r
- Wakeup from suspend event */ \r
-#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */\r
- \r
-#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))\r
-#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \\r
- ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \\r
- ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \\r
- ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \\r
- ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \\r
- ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \\r
- ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \\r
- ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \\r
- ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \\r
- ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))\r
-\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup EXTI_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup EXTI_Exported_Functions\r
- * @{\r
- */\r
-\r
-void EXTI_DeInit(void);\r
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);\r
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);\r
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);\r
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);\r
-void EXTI_ClearFlag(uint32_t EXTI_Line);\r
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);\r
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_EXTI_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_flash.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the FLASH \r
- * firmware library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_FLASH_H\r
-#define __STM32F10x_FLASH_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup FLASH\r
- * @{\r
- */\r
-\r
-/** @defgroup FLASH_Exported_Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief FLASH Status \r
- */\r
-\r
-typedef enum\r
-{ \r
- FLASH_BUSY = 1,\r
- FLASH_ERROR_PG,\r
- FLASH_ERROR_WRP,\r
- FLASH_COMPLETE,\r
- FLASH_TIMEOUT\r
-}FLASH_Status;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASH_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup Flash_Latency \r
- * @{\r
- */\r
-\r
-#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */\r
-#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */\r
-#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */\r
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \\r
- ((LATENCY) == FLASH_Latency_1) || \\r
- ((LATENCY) == FLASH_Latency_2))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Half_Cycle_Enable_Disable \r
- * @{\r
- */\r
-\r
-#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */\r
-#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */\r
-#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \\r
- ((STATE) == FLASH_HalfCycleAccess_Disable)) \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Prefetch_Buffer_Enable_Disable \r
- * @{\r
- */\r
-\r
-#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */\r
-#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */\r
-#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \\r
- ((STATE) == FLASH_PrefetchBuffer_Disable)) \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Option_Bytes_Write_Protection \r
- * @{\r
- */\r
-\r
-/* Values to be used with STM32 Low and Medium density devices */\r
-#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */\r
-#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */\r
-#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */\r
-#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */\r
-#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */\r
-#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */\r
-#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */\r
-#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */\r
-\r
-/* Values to be used with STM32 Medium-density devices */\r
-#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */\r
-#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */\r
-#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */\r
-#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */\r
-#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */\r
-#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */\r
-#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */\r
-#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */\r
-#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */\r
-#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */\r
-#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */\r
-#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */\r
-#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */\r
-#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */\r
-#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */\r
-#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */\r
-#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */\r
-#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */\r
-#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */\r
-#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */\r
-#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */\r
-#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */\r
-#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */\r
-#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */\r
-\r
-/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */\r
-#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 0 to 1 */\r
-#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 2 to 3 */\r
-#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 4 to 5 */\r
-#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 6 to 7 */\r
-#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 8 to 9 */\r
-#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 10 to 11 */\r
-#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 12 to 13 */\r
-#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 14 to 15 */\r
-#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 16 to 17 */\r
-#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 18 to 19 */\r
-#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 20 to 21 */\r
-#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 22 to 23 */\r
-#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 24 to 25 */\r
-#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 26 to 27 */\r
-#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 28 to 29 */\r
-#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 30 to 31 */\r
-#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 32 to 33 */\r
-#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 34 to 35 */\r
-#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 36 to 37 */\r
-#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 38 to 39 */\r
-#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 40 to 41 */\r
-#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 42 to 43 */\r
-#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 44 to 45 */\r
-#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 46 to 47 */\r
-#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 48 to 49 */\r
-#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 50 to 51 */\r
-#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 52 to 53 */\r
-#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 54 to 55 */\r
-#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 56 to 57 */\r
-#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 58 to 59 */\r
-#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 60 to 61 */\r
-#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */\r
-#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */\r
-#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */\r
-\r
-#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */\r
-\r
-#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))\r
-\r
-#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))\r
-\r
-#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Option_Bytes_IWatchdog \r
- * @{\r
- */\r
-\r
-#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */\r
-#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */\r
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Option_Bytes_nRST_STOP \r
- * @{\r
- */\r
-\r
-#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */\r
-#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */\r
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Option_Bytes_nRST_STDBY \r
- * @{\r
- */\r
-\r
-#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */\r
-#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */\r
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))\r
-\r
-#ifdef STM32F10X_XL\r
-/**\r
- * @}\r
- */\r
-/** @defgroup FLASH_Boot\r
- * @{\r
- */\r
-#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position\r
- and this parameter is selected the device will boot from Bank1(Default) */\r
-#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position\r
- and this parameter is selected the device will boot from Bank 2 or Bank 1,\r
- depending on the activation of the bank */\r
-#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2))\r
-#endif\r
-/**\r
- * @}\r
- */\r
-/** @defgroup FLASH_Interrupts \r
- * @{\r
- */\r
-#ifdef STM32F10X_XL\r
-#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */\r
-#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */\r
-\r
-#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */\r
-#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */\r
-\r
-#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */\r
-#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */\r
-#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))\r
-#else\r
-#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */\r
-#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */\r
-#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */\r
-#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */\r
-\r
-#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASH_Flags \r
- * @{\r
- */\r
-#ifdef STM32F10X_XL\r
-#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */\r
-#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */\r
-#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */\r
-#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */\r
-\r
-#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/\r
-#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */\r
-#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */\r
-#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */\r
-\r
-#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */\r
-#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */\r
-#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */\r
-#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */\r
-#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */\r
- \r
-#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))\r
-#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \\r
- ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \\r
- ((FLAG) == FLASH_FLAG_OPTERR)|| \\r
- ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \\r
- ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \\r
- ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \\r
- ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR))\r
-#else\r
-#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */\r
-#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */\r
-#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */\r
-#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */\r
-#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */\r
-\r
-#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/\r
-#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */\r
-#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */\r
-#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */\r
- \r
-#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))\r
-#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \\r
- ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \\r
- ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \\r
- ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \\r
- ((FLAG) == FLASH_FLAG_OPTERR))\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASH_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASH_Exported_Functions\r
- * @{\r
- */\r
-\r
-/*------------ Functions used for all STM32F10x devices -----*/\r
-void FLASH_SetLatency(uint32_t FLASH_Latency);\r
-void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);\r
-void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);\r
-void FLASH_Unlock(void);\r
-void FLASH_Lock(void);\r
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address);\r
-FLASH_Status FLASH_EraseAllPages(void);\r
-FLASH_Status FLASH_EraseOptionBytes(void);\r
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);\r
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
-FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);\r
-FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);\r
-FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);\r
-FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);\r
-uint32_t FLASH_GetUserOptionByte(void);\r
-uint32_t FLASH_GetWriteProtectionOptionByte(void);\r
-FlagStatus FLASH_GetReadOutProtectionStatus(void);\r
-FlagStatus FLASH_GetPrefetchBufferStatus(void);\r
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);\r
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);\r
-void FLASH_ClearFlag(uint32_t FLASH_FLAG);\r
-FLASH_Status FLASH_GetStatus(void);\r
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);\r
-\r
-/*------------ New function used for all STM32F10x devices -----*/\r
-void FLASH_UnlockBank1(void);\r
-void FLASH_LockBank1(void);\r
-FLASH_Status FLASH_EraseAllBank1Pages(void);\r
-FLASH_Status FLASH_GetBank1Status(void);\r
-FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);\r
-\r
-#ifdef STM32F10X_XL\r
-/*---- New Functions used only with STM32F10x_XL density devices -----*/\r
-void FLASH_UnlockBank2(void);\r
-void FLASH_LockBank2(void);\r
-FLASH_Status FLASH_EraseAllBank2Pages(void);\r
-FLASH_Status FLASH_GetBank2Status(void);\r
-FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout);\r
-FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT);\r
-#endif\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_FLASH_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_fsmc.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the FSMC firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_FSMC_H\r
-#define __STM32F10x_FSMC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup FSMC\r
- * @{\r
- */\r
-\r
-/** @defgroup FSMC_Exported_Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief Timing parameters For NOR/SRAM Banks \r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure\r
- the duration of the address setup time. \r
- This parameter can be a value between 0 and 0xF.\r
- @note: It is not used with synchronous NOR Flash memories. */\r
-\r
- uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure\r
- the duration of the address hold time.\r
- This parameter can be a value between 0 and 0xF. \r
- @note: It is not used with synchronous NOR Flash memories.*/\r
-\r
- uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure\r
- the duration of the data setup time.\r
- This parameter can be a value between 0 and 0xFF.\r
- @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */\r
-\r
- uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure\r
- the duration of the bus turnaround.\r
- This parameter can be a value between 0 and 0xF.\r
- @note: It is only used for multiplexed NOR Flash memories. */\r
-\r
- uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.\r
- This parameter can be a value between 1 and 0xF.\r
- @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */\r
-\r
- uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue\r
- to the memory before getting the first data.\r
- The value of this parameter depends on the memory type as shown below:\r
- - It must be set to 0 in case of a CRAM\r
- - It is don\92t care in asynchronous NOR, SRAM or ROM accesses\r
- - It may assume a value between 0 and 0xF in NOR Flash memories\r
- with synchronous burst mode enable */\r
-\r
- uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. \r
- This parameter can be a value of @ref FSMC_Access_Mode */\r
-}FSMC_NORSRAMTimingInitTypeDef;\r
-\r
-/** \r
- * @brief FSMC NOR/SRAM Init structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.\r
- This parameter can be a value of @ref FSMC_NORSRAM_Bank */\r
-\r
- uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are\r
- multiplexed on the databus or not. \r
- This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */\r
-\r
- uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to\r
- the corresponding memory bank.\r
- This parameter can be a value of @ref FSMC_Memory_Type */\r
-\r
- uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.\r
- This parameter can be a value of @ref FSMC_Data_Width */\r
-\r
- uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,\r
- valid only with synchronous burst Flash memories.\r
- This parameter can be a value of @ref FSMC_Burst_Access_Mode */\r
-\r
- uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing\r
- the Flash memory in burst mode.\r
- This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */\r
-\r
- uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash\r
- memory, valid only when accessing Flash memories in burst mode.\r
- This parameter can be a value of @ref FSMC_Wrap_Mode */\r
-\r
- uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one\r
- clock cycle before the wait state or during the wait state,\r
- valid only when accessing memories in burst mode. \r
- This parameter can be a value of @ref FSMC_Wait_Timing */\r
-\r
- uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. \r
- This parameter can be a value of @ref FSMC_Write_Operation */\r
-\r
- uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait\r
- signal, valid for Flash memory access in burst mode. \r
- This parameter can be a value of @ref FSMC_Wait_Signal */\r
-\r
- uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.\r
- This parameter can be a value of @ref FSMC_Extended_Mode */\r
-\r
- uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.\r
- This parameter can be a value of @ref FSMC_Write_Burst */ \r
-\r
- FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ \r
-\r
- FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ \r
-}FSMC_NORSRAMInitTypeDef;\r
-\r
-/** \r
- * @brief Timing parameters For FSMC NAND and PCCARD Banks\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before\r
- the command assertion for NAND-Flash read or write access\r
- to common/Attribute or I/O memory space (depending on\r
- the memory space timing to be configured).\r
- This parameter can be a value between 0 and 0xFF.*/\r
-\r
- uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the\r
- command for NAND-Flash read or write access to\r
- common/Attribute or I/O memory space (depending on the\r
- memory space timing to be configured). \r
- This parameter can be a number between 0x00 and 0xFF */\r
-\r
- uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address\r
- (and data for write access) after the command deassertion\r
- for NAND-Flash read or write access to common/Attribute\r
- or I/O memory space (depending on the memory space timing\r
- to be configured).\r
- This parameter can be a number between 0x00 and 0xFF */\r
-\r
- uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the\r
- databus is kept in HiZ after the start of a NAND-Flash\r
- write access to common/Attribute or I/O memory space (depending\r
- on the memory space timing to be configured).\r
- This parameter can be a number between 0x00 and 0xFF */\r
-}FSMC_NAND_PCCARDTimingInitTypeDef;\r
-\r
-/** \r
- * @brief FSMC NAND Init structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.\r
- This parameter can be a value of @ref FSMC_NAND_Bank */\r
-\r
- uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.\r
- This parameter can be any value of @ref FSMC_Wait_feature */\r
-\r
- uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.\r
- This parameter can be any value of @ref FSMC_Data_Width */\r
-\r
- uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.\r
- This parameter can be any value of @ref FSMC_ECC */\r
-\r
- uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.\r
- This parameter can be any value of @ref FSMC_ECC_Page_Size */\r
-\r
- uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
- delay between CLE low and RE low.\r
- This parameter can be a value between 0 and 0xFF. */\r
-\r
- uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
- delay between ALE low and RE low.\r
- This parameter can be a number between 0x0 and 0xFF */ \r
-\r
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ \r
-\r
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */\r
-}FSMC_NANDInitTypeDef;\r
-\r
-/** \r
- * @brief FSMC PCCARD Init structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.\r
- This parameter can be any value of @ref FSMC_Wait_feature */\r
-\r
- uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
- delay between CLE low and RE low.\r
- This parameter can be a value between 0 and 0xFF. */\r
-\r
- uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
- delay between ALE low and RE low.\r
- This parameter can be a number between 0x0 and 0xFF */ \r
-\r
- \r
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */\r
-\r
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ \r
- \r
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ \r
-}FSMC_PCCARDInitTypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup FSMC_NORSRAM_Bank \r
- * @{\r
- */\r
-#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)\r
-#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)\r
-#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)\r
-#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_NAND_Bank \r
- * @{\r
- */ \r
-#define FSMC_Bank2_NAND ((uint32_t)0x00000010)\r
-#define FSMC_Bank3_NAND ((uint32_t)0x00000100)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_PCCARD_Bank \r
- * @{\r
- */ \r
-#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)\r
-/**\r
- * @}\r
- */\r
-\r
-#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \\r
- ((BANK) == FSMC_Bank1_NORSRAM2) || \\r
- ((BANK) == FSMC_Bank1_NORSRAM3) || \\r
- ((BANK) == FSMC_Bank1_NORSRAM4))\r
-\r
-#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
- ((BANK) == FSMC_Bank3_NAND))\r
-\r
-#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
- ((BANK) == FSMC_Bank3_NAND) || \\r
- ((BANK) == FSMC_Bank4_PCCARD))\r
-\r
-#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
- ((BANK) == FSMC_Bank3_NAND) || \\r
- ((BANK) == FSMC_Bank4_PCCARD))\r
-\r
-/** @defgroup NOR_SRAM_Controller \r
- * @{\r
- */\r
-\r
-/** @defgroup FSMC_Data_Address_Bus_Multiplexing \r
- * @{\r
- */\r
-\r
-#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)\r
-#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)\r
-#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \\r
- ((MUX) == FSMC_DataAddressMux_Enable))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Memory_Type \r
- * @{\r
- */\r
-\r
-#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)\r
-#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)\r
-#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)\r
-#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \\r
- ((MEMORY) == FSMC_MemoryType_PSRAM)|| \\r
- ((MEMORY) == FSMC_MemoryType_NOR))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Data_Width \r
- * @{\r
- */\r
-\r
-#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)\r
-#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)\r
-#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \\r
- ((WIDTH) == FSMC_MemoryDataWidth_16b))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Burst_Access_Mode \r
- * @{\r
- */\r
-\r
-#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) \r
-#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)\r
-#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \\r
- ((STATE) == FSMC_BurstAccessMode_Enable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Wait_Signal_Polarity \r
- * @{\r
- */\r
-\r
-#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)\r
-#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)\r
-#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \\r
- ((POLARITY) == FSMC_WaitSignalPolarity_High)) \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Wrap_Mode \r
- * @{\r
- */\r
-\r
-#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)\r
-#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) \r
-#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \\r
- ((MODE) == FSMC_WrapMode_Enable))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Wait_Timing \r
- * @{\r
- */\r
-\r
-#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)\r
-#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) \r
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \\r
- ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Write_Operation \r
- * @{\r
- */\r
-\r
-#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)\r
-#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)\r
-#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \\r
- ((OPERATION) == FSMC_WriteOperation_Enable))\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Wait_Signal \r
- * @{\r
- */\r
-\r
-#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)\r
-#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) \r
-#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \\r
- ((SIGNAL) == FSMC_WaitSignal_Enable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Extended_Mode \r
- * @{\r
- */\r
-\r
-#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)\r
-#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)\r
-\r
-#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \\r
- ((MODE) == FSMC_ExtendedMode_Enable)) \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Write_Burst \r
- * @{\r
- */\r
-\r
-#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)\r
-#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) \r
-#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \\r
- ((BURST) == FSMC_WriteBurst_Enable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Address_Setup_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Address_Hold_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Data_Setup_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Bus_Turn_around_Duration \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_CLK_Division \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Data_Latency \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Access_Mode \r
- * @{\r
- */\r
-\r
-#define FSMC_AccessMode_A ((uint32_t)0x00000000)\r
-#define FSMC_AccessMode_B ((uint32_t)0x10000000) \r
-#define FSMC_AccessMode_C ((uint32_t)0x20000000)\r
-#define FSMC_AccessMode_D ((uint32_t)0x30000000)\r
-#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \\r
- ((MODE) == FSMC_AccessMode_B) || \\r
- ((MODE) == FSMC_AccessMode_C) || \\r
- ((MODE) == FSMC_AccessMode_D)) \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup NAND_PCCARD_Controller \r
- * @{\r
- */\r
-\r
-/** @defgroup FSMC_Wait_feature \r
- * @{\r
- */\r
-\r
-#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)\r
-#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)\r
-#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \\r
- ((FEATURE) == FSMC_Waitfeature_Enable))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup FSMC_ECC \r
- * @{\r
- */\r
-\r
-#define FSMC_ECC_Disable ((uint32_t)0x00000000)\r
-#define FSMC_ECC_Enable ((uint32_t)0x00000040)\r
-#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \\r
- ((STATE) == FSMC_ECC_Enable))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_ECC_Page_Size \r
- * @{\r
- */\r
-\r
-#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)\r
-#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)\r
-#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)\r
-#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)\r
-#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)\r
-#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)\r
-#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \\r
- ((SIZE) == FSMC_ECCPageSize_512Bytes) || \\r
- ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \\r
- ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \\r
- ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \\r
- ((SIZE) == FSMC_ECCPageSize_8192Bytes))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_TCLR_Setup_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_TAR_Setup_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Setup_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Wait_Setup_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Hold_Setup_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_HiZ_Setup_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Interrupt_sources \r
- * @{\r
- */\r
-\r
-#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)\r
-#define FSMC_IT_Level ((uint32_t)0x00000010)\r
-#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)\r
-#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))\r
-#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \\r
- ((IT) == FSMC_IT_Level) || \\r
- ((IT) == FSMC_IT_FallingEdge)) \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Flags \r
- * @{\r
- */\r
-\r
-#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)\r
-#define FSMC_FLAG_Level ((uint32_t)0x00000002)\r
-#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)\r
-#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)\r
-#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \\r
- ((FLAG) == FSMC_FLAG_Level) || \\r
- ((FLAG) == FSMC_FLAG_FallingEdge) || \\r
- ((FLAG) == FSMC_FLAG_FEMPT))\r
-\r
-#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Exported_Functions\r
- * @{\r
- */\r
-\r
-void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);\r
-void FSMC_NANDDeInit(uint32_t FSMC_Bank);\r
-void FSMC_PCCARDDeInit(void);\r
-void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
-void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);\r
-void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);\r
-void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
-void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);\r
-void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);\r
-void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
-void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
-void FSMC_PCCARDCmd(FunctionalState NewState);\r
-void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
-uint32_t FSMC_GetECC(uint32_t FSMC_Bank);\r
-void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);\r
-FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);\r
-void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);\r
-ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);\r
-void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32F10x_FSMC_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_gpio.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the GPIO \r
- * firmware library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_GPIO_H\r
-#define __STM32F10x_GPIO_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup GPIO\r
- * @{\r
- */\r
-\r
-/** @defgroup GPIO_Exported_Types\r
- * @{\r
- */\r
-\r
-#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \\r
- ((PERIPH) == GPIOB) || \\r
- ((PERIPH) == GPIOC) || \\r
- ((PERIPH) == GPIOD) || \\r
- ((PERIPH) == GPIOE) || \\r
- ((PERIPH) == GPIOF) || \\r
- ((PERIPH) == GPIOG))\r
- \r
-/** \r
- * @brief Output Maximum frequency selection \r
- */\r
-\r
-typedef enum\r
-{ \r
- GPIO_Speed_10MHz = 1,\r
- GPIO_Speed_2MHz, \r
- GPIO_Speed_50MHz\r
-}GPIOSpeed_TypeDef;\r
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \\r
- ((SPEED) == GPIO_Speed_50MHz))\r
-\r
-/** \r
- * @brief Configuration Mode enumeration \r
- */\r
-\r
-typedef enum\r
-{ GPIO_Mode_AIN = 0x0,\r
- GPIO_Mode_IN_FLOATING = 0x04,\r
- GPIO_Mode_IPD = 0x28,\r
- GPIO_Mode_IPU = 0x48,\r
- GPIO_Mode_Out_OD = 0x14,\r
- GPIO_Mode_Out_PP = 0x10,\r
- GPIO_Mode_AF_OD = 0x1C,\r
- GPIO_Mode_AF_PP = 0x18\r
-}GPIOMode_TypeDef;\r
-\r
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \\r
- ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \\r
- ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \\r
- ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))\r
-\r
-/** \r
- * @brief GPIO Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.\r
- This parameter can be any value of @ref GPIO_pins_define */\r
-\r
- GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.\r
- This parameter can be a value of @ref GPIOSpeed_TypeDef */\r
-\r
- GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.\r
- This parameter can be a value of @ref GPIOMode_TypeDef */\r
-}GPIO_InitTypeDef;\r
-\r
-\r
-/** \r
- * @brief Bit_SET and Bit_RESET enumeration \r
- */\r
-\r
-typedef enum\r
-{ Bit_RESET = 0,\r
- Bit_SET\r
-}BitAction;\r
-\r
-#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup GPIO_pins_define \r
- * @{\r
- */\r
-\r
-#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */\r
-#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */\r
-#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */\r
-#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */\r
-#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */\r
-#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */\r
-#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */\r
-#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */\r
-#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */\r
-#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */\r
-#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */\r
-#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */\r
-#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */\r
-#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */\r
-#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */\r
-#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */\r
-#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */\r
-\r
-#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))\r
-\r
-#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \\r
- ((PIN) == GPIO_Pin_1) || \\r
- ((PIN) == GPIO_Pin_2) || \\r
- ((PIN) == GPIO_Pin_3) || \\r
- ((PIN) == GPIO_Pin_4) || \\r
- ((PIN) == GPIO_Pin_5) || \\r
- ((PIN) == GPIO_Pin_6) || \\r
- ((PIN) == GPIO_Pin_7) || \\r
- ((PIN) == GPIO_Pin_8) || \\r
- ((PIN) == GPIO_Pin_9) || \\r
- ((PIN) == GPIO_Pin_10) || \\r
- ((PIN) == GPIO_Pin_11) || \\r
- ((PIN) == GPIO_Pin_12) || \\r
- ((PIN) == GPIO_Pin_13) || \\r
- ((PIN) == GPIO_Pin_14) || \\r
- ((PIN) == GPIO_Pin_15))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_Remap_define \r
- * @{\r
- */\r
-\r
-#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */\r
-#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */\r
-#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */\r
-#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */\r
-#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */\r
-#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */\r
-#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */\r
-#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */\r
-#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */\r
-#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */\r
-#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */\r
-#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */\r
-#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */\r
-#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */\r
-#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */\r
-#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */\r
-#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */\r
-#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */\r
-#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */\r
-#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */\r
-#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */\r
-#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */\r
-#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */\r
-#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */\r
-#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */\r
-#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */\r
-#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */\r
-#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */\r
-#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected\r
- to TIM2 Internal Trigger 1 for calibration\r
- (only for Connectivity line devices) */\r
-#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */\r
-\r
-#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */\r
-#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */\r
-#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */\r
-#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */\r
-#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */\r
-\r
-#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */\r
-#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */\r
-#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */\r
-#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for XL-density devices) */\r
-#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for XL-density devices) */\r
-#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for XL-density devices) */\r
- \r
-\r
-#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \\r
- ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \\r
- ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \\r
- ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \\r
- ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \\r
- ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \\r
- ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \\r
- ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \\r
- ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \\r
- ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \\r
- ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \\r
- ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \\r
- ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \\r
- ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \\r
- ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \\r
- ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \\r
- ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \\r
- ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \\r
- ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \\r
- ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \\r
- ((REMAP) == GPIO_Remap_FSMC_NADV))\r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup GPIO_Port_Sources \r
- * @{\r
- */\r
-\r
-#define GPIO_PortSourceGPIOA ((uint8_t)0x00)\r
-#define GPIO_PortSourceGPIOB ((uint8_t)0x01)\r
-#define GPIO_PortSourceGPIOC ((uint8_t)0x02)\r
-#define GPIO_PortSourceGPIOD ((uint8_t)0x03)\r
-#define GPIO_PortSourceGPIOE ((uint8_t)0x04)\r
-#define GPIO_PortSourceGPIOF ((uint8_t)0x05)\r
-#define GPIO_PortSourceGPIOG ((uint8_t)0x06)\r
-#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \\r
- ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \\r
- ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \\r
- ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \\r
- ((PORTSOURCE) == GPIO_PortSourceGPIOE))\r
-\r
-#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \\r
- ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \\r
- ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \\r
- ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \\r
- ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \\r
- ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \\r
- ((PORTSOURCE) == GPIO_PortSourceGPIOG))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_Pin_sources \r
- * @{\r
- */\r
-\r
-#define GPIO_PinSource0 ((uint8_t)0x00)\r
-#define GPIO_PinSource1 ((uint8_t)0x01)\r
-#define GPIO_PinSource2 ((uint8_t)0x02)\r
-#define GPIO_PinSource3 ((uint8_t)0x03)\r
-#define GPIO_PinSource4 ((uint8_t)0x04)\r
-#define GPIO_PinSource5 ((uint8_t)0x05)\r
-#define GPIO_PinSource6 ((uint8_t)0x06)\r
-#define GPIO_PinSource7 ((uint8_t)0x07)\r
-#define GPIO_PinSource8 ((uint8_t)0x08)\r
-#define GPIO_PinSource9 ((uint8_t)0x09)\r
-#define GPIO_PinSource10 ((uint8_t)0x0A)\r
-#define GPIO_PinSource11 ((uint8_t)0x0B)\r
-#define GPIO_PinSource12 ((uint8_t)0x0C)\r
-#define GPIO_PinSource13 ((uint8_t)0x0D)\r
-#define GPIO_PinSource14 ((uint8_t)0x0E)\r
-#define GPIO_PinSource15 ((uint8_t)0x0F)\r
-\r
-#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \\r
- ((PINSOURCE) == GPIO_PinSource1) || \\r
- ((PINSOURCE) == GPIO_PinSource2) || \\r
- ((PINSOURCE) == GPIO_PinSource3) || \\r
- ((PINSOURCE) == GPIO_PinSource4) || \\r
- ((PINSOURCE) == GPIO_PinSource5) || \\r
- ((PINSOURCE) == GPIO_PinSource6) || \\r
- ((PINSOURCE) == GPIO_PinSource7) || \\r
- ((PINSOURCE) == GPIO_PinSource8) || \\r
- ((PINSOURCE) == GPIO_PinSource9) || \\r
- ((PINSOURCE) == GPIO_PinSource10) || \\r
- ((PINSOURCE) == GPIO_PinSource11) || \\r
- ((PINSOURCE) == GPIO_PinSource12) || \\r
- ((PINSOURCE) == GPIO_PinSource13) || \\r
- ((PINSOURCE) == GPIO_PinSource14) || \\r
- ((PINSOURCE) == GPIO_PinSource15))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Ethernet_Media_Interface \r
- * @{\r
- */ \r
-#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) \r
-#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) \r
-\r
-#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \\r
- ((INTERFACE) == GPIO_ETH_MediaInterface_RMII))\r
-\r
-/**\r
- * @}\r
- */ \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_Exported_Functions\r
- * @{\r
- */\r
-\r
-void GPIO_DeInit(GPIO_TypeDef* GPIOx);\r
-void GPIO_AFIODeInit(void);\r
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);\r
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);\r
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);\r
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);\r
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);\r
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);\r
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
-void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);\r
-void GPIO_EventOutputCmd(FunctionalState NewState);\r
-void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);\r
-void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);\r
-void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_GPIO_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_i2c.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the I2C firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_I2C_H\r
-#define __STM32F10x_I2C_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup I2C\r
- * @{\r
- */\r
-\r
-/** @defgroup I2C_Exported_Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief I2C Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.\r
- This parameter must be set to a value lower than 400kHz */\r
-\r
- uint16_t I2C_Mode; /*!< Specifies the I2C mode.\r
- This parameter can be a value of @ref I2C_mode */\r
-\r
- uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.\r
- This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */\r
-\r
- uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.\r
- This parameter can be a 7-bit or 10-bit address. */\r
-\r
- uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.\r
- This parameter can be a value of @ref I2C_acknowledgement */\r
-\r
- uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.\r
- This parameter can be a value of @ref I2C_acknowledged_address */\r
-}I2C_InitTypeDef;\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup I2C_Exported_Constants\r
- * @{\r
- */\r
-\r
-#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \\r
- ((PERIPH) == I2C2))\r
-/** @defgroup I2C_mode \r
- * @{\r
- */\r
-\r
-#define I2C_Mode_I2C ((uint16_t)0x0000)\r
-#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) \r
-#define I2C_Mode_SMBusHost ((uint16_t)0x000A)\r
-#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \\r
- ((MODE) == I2C_Mode_SMBusDevice) || \\r
- ((MODE) == I2C_Mode_SMBusHost))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_duty_cycle_in_fast_mode \r
- * @{\r
- */\r
-\r
-#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */\r
-#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */\r
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \\r
- ((CYCLE) == I2C_DutyCycle_2))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2C_acknowledgement\r
- * @{\r
- */\r
-\r
-#define I2C_Ack_Enable ((uint16_t)0x0400)\r
-#define I2C_Ack_Disable ((uint16_t)0x0000)\r
-#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \\r
- ((STATE) == I2C_Ack_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_transfer_direction \r
- * @{\r
- */\r
-\r
-#define I2C_Direction_Transmitter ((uint8_t)0x00)\r
-#define I2C_Direction_Receiver ((uint8_t)0x01)\r
-#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \\r
- ((DIRECTION) == I2C_Direction_Receiver))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_acknowledged_address \r
- * @{\r
- */\r
-\r
-#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)\r
-#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)\r
-#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \\r
- ((ADDRESS) == I2C_AcknowledgedAddress_10bit))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2C_registers \r
- * @{\r
- */\r
-\r
-#define I2C_Register_CR1 ((uint8_t)0x00)\r
-#define I2C_Register_CR2 ((uint8_t)0x04)\r
-#define I2C_Register_OAR1 ((uint8_t)0x08)\r
-#define I2C_Register_OAR2 ((uint8_t)0x0C)\r
-#define I2C_Register_DR ((uint8_t)0x10)\r
-#define I2C_Register_SR1 ((uint8_t)0x14)\r
-#define I2C_Register_SR2 ((uint8_t)0x18)\r
-#define I2C_Register_CCR ((uint8_t)0x1C)\r
-#define I2C_Register_TRISE ((uint8_t)0x20)\r
-#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \\r
- ((REGISTER) == I2C_Register_CR2) || \\r
- ((REGISTER) == I2C_Register_OAR1) || \\r
- ((REGISTER) == I2C_Register_OAR2) || \\r
- ((REGISTER) == I2C_Register_DR) || \\r
- ((REGISTER) == I2C_Register_SR1) || \\r
- ((REGISTER) == I2C_Register_SR2) || \\r
- ((REGISTER) == I2C_Register_CCR) || \\r
- ((REGISTER) == I2C_Register_TRISE))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_SMBus_alert_pin_level \r
- * @{\r
- */\r
-\r
-#define I2C_SMBusAlert_Low ((uint16_t)0x2000)\r
-#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)\r
-#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \\r
- ((ALERT) == I2C_SMBusAlert_High))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_PEC_position \r
- * @{\r
- */\r
-\r
-#define I2C_PECPosition_Next ((uint16_t)0x0800)\r
-#define I2C_PECPosition_Current ((uint16_t)0xF7FF)\r
-#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \\r
- ((POSITION) == I2C_PECPosition_Current))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2C_interrupts_definition \r
- * @{\r
- */\r
-\r
-#define I2C_IT_BUF ((uint16_t)0x0400)\r
-#define I2C_IT_EVT ((uint16_t)0x0200)\r
-#define I2C_IT_ERR ((uint16_t)0x0100)\r
-#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2C_interrupts_definition \r
- * @{\r
- */\r
-\r
-#define I2C_IT_SMBALERT ((uint32_t)0x01008000)\r
-#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)\r
-#define I2C_IT_PECERR ((uint32_t)0x01001000)\r
-#define I2C_IT_OVR ((uint32_t)0x01000800)\r
-#define I2C_IT_AF ((uint32_t)0x01000400)\r
-#define I2C_IT_ARLO ((uint32_t)0x01000200)\r
-#define I2C_IT_BERR ((uint32_t)0x01000100)\r
-#define I2C_IT_TXE ((uint32_t)0x06000080)\r
-#define I2C_IT_RXNE ((uint32_t)0x06000040)\r
-#define I2C_IT_STOPF ((uint32_t)0x02000010)\r
-#define I2C_IT_ADD10 ((uint32_t)0x02000008)\r
-#define I2C_IT_BTF ((uint32_t)0x02000004)\r
-#define I2C_IT_ADDR ((uint32_t)0x02000002)\r
-#define I2C_IT_SB ((uint32_t)0x02000001)\r
-\r
-#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))\r
-\r
-#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \\r
- ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \\r
- ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \\r
- ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \\r
- ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \\r
- ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \\r
- ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_flags_definition \r
- * @{\r
- */\r
-\r
-/** \r
- * @brief SR2 register flags \r
- */\r
-\r
-#define I2C_FLAG_DUALF ((uint32_t)0x00800000)\r
-#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)\r
-#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)\r
-#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)\r
-#define I2C_FLAG_TRA ((uint32_t)0x00040000)\r
-#define I2C_FLAG_BUSY ((uint32_t)0x00020000)\r
-#define I2C_FLAG_MSL ((uint32_t)0x00010000)\r
-\r
-/** \r
- * @brief SR1 register flags \r
- */\r
-\r
-#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)\r
-#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)\r
-#define I2C_FLAG_PECERR ((uint32_t)0x10001000)\r
-#define I2C_FLAG_OVR ((uint32_t)0x10000800)\r
-#define I2C_FLAG_AF ((uint32_t)0x10000400)\r
-#define I2C_FLAG_ARLO ((uint32_t)0x10000200)\r
-#define I2C_FLAG_BERR ((uint32_t)0x10000100)\r
-#define I2C_FLAG_TXE ((uint32_t)0x10000080)\r
-#define I2C_FLAG_RXNE ((uint32_t)0x10000040)\r
-#define I2C_FLAG_STOPF ((uint32_t)0x10000010)\r
-#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)\r
-#define I2C_FLAG_BTF ((uint32_t)0x10000004)\r
-#define I2C_FLAG_ADDR ((uint32_t)0x10000002)\r
-#define I2C_FLAG_SB ((uint32_t)0x10000001)\r
-\r
-#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
-\r
-#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \\r
- ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \\r
- ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \\r
- ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \\r
- ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \\r
- ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \\r
- ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \\r
- ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \\r
- ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \\r
- ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \\r
- ((FLAG) == I2C_FLAG_SB))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Events \r
- * @{\r
- */\r
-\r
-/*========================================\r
- \r
- I2C Master Events (Events grouped in order of communication)\r
- ==========================================*/\r
-/** \r
- * @brief Communication start\r
- * \r
- * After sending the START condition (I2C_GenerateSTART() function) the master \r
- * has to wait for this event. It means that the Start condition has been correctly \r
- * released on the I2C bus (the bus is free, no other devices is communicating).\r
- * \r
- */\r
-/* --EV5 */\r
-#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */\r
-\r
-/** \r
- * @brief Address Acknowledge\r
- * \r
- * After checking on EV5 (start condition correctly released on the bus), the \r
- * master sends the address of the slave(s) with which it will communicate \r
- * (I2C_Send7bitAddress() function, it also determines the direction of the communication: \r
- * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges \r
- * his address. If an acknowledge is sent on the bus, one of the following events will \r
- * be set:\r
- * \r
- * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED \r
- * event is set.\r
- * \r
- * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED \r
- * is set\r
- * \r
- * 3) In case of 10-Bit addressing mode, the master (just after generating the START \r
- * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() \r
- * function). Then master should wait on EV9. It means that the 10-bit addressing \r
- * header has been correctly sent on the bus. Then master should send the second part of \r
- * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master \r
- * should wait for event EV6. \r
- * \r
- */\r
-\r
-/* --EV6 */\r
-#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */\r
-#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */\r
-/* --EV9 */\r
-#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */\r
-\r
-/** \r
- * @brief Communication events\r
- * \r
- * If a communication is established (START condition generated and slave address \r
- * acknowledged) then the master has to check on one of the following events for \r
- * communication procedures:\r
- * \r
- * 1) Master Receiver mode: The master has to wait on the event EV7 then to read \r
- * the data received from the slave (I2C_ReceiveData() function).\r
- * \r
- * 2) Master Transmitter mode: The master has to send data (I2C_SendData() \r
- * function) then to wait on event EV8 or EV8_2.\r
- * These two events are similar: \r
- * - EV8 means that the data has been written in the data register and is \r
- * being shifted out.\r
- * - EV8_2 means that the data has been physically shifted out and output \r
- * on the bus.\r
- * In most cases, using EV8 is sufficient for the application.\r
- * Using EV8_2 leads to a slower communication but ensure more reliable test.\r
- * EV8_2 is also more suitable than EV8 for testing on the last data transmission \r
- * (before Stop condition generation).\r
- * \r
- * @note In case the user software does not guarantee that this event EV7 is \r
- * managed before the current byte end of transfer, then user may check on EV7 \r
- * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
- * In this case the communication may be slower.\r
- * \r
- */\r
-\r
-/* Master RECEIVER mode -----------------------------*/ \r
-/* --EV7 */\r
-#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */\r
-\r
-/* Master TRANSMITTER mode --------------------------*/\r
-/* --EV8 */\r
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */\r
-/* --EV8_2 */\r
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */\r
-\r
-\r
-/*========================================\r
- \r
- I2C Slave Events (Events grouped in order of communication)\r
- ==========================================*/\r
-\r
-/** \r
- * @brief Communication start events\r
- * \r
- * Wait on one of these events at the start of the communication. It means that \r
- * the I2C peripheral detected a Start condition on the bus (generated by master \r
- * device) followed by the peripheral address. The peripheral generates an ACK \r
- * condition on the bus (if the acknowledge feature is enabled through function \r
- * I2C_AcknowledgeConfig()) and the events listed above are set :\r
- * \r
- * 1) In normal case (only one address managed by the slave), when the address \r
- * sent by the master matches the own address of the peripheral (configured by \r
- * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set \r
- * (where XXX could be TRANSMITTER or RECEIVER).\r
- * \r
- * 2) In case the address sent by the master matches the second address of the \r
- * peripheral (configured by the function I2C_OwnAddress2Config() and enabled \r
- * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED \r
- * (where XXX could be TRANSMITTER or RECEIVER) are set.\r
- * \r
- * 3) In case the address sent by the master is General Call (address 0x00) and \r
- * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) \r
- * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. \r
- * \r
- */\r
-\r
-/* --EV1 (all the events below are variants of EV1) */ \r
-/* 1) Case of One Single Address managed by the slave */\r
-#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */\r
-#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */\r
-\r
-/* 2) Case of Dual address managed by the slave */\r
-#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */\r
-#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */\r
-\r
-/* 3) Case of General Call enabled for the slave */\r
-#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */\r
-\r
-/** \r
- * @brief Communication events\r
- * \r
- * Wait on one of these events when EV1 has already been checked and: \r
- * \r
- * - Slave RECEIVER mode:\r
- * - EV2: When the application is expecting a data byte to be received. \r
- * - EV4: When the application is expecting the end of the communication: master \r
- * sends a stop condition and data transmission is stopped.\r
- * \r
- * - Slave Transmitter mode:\r
- * - EV3: When a byte has been transmitted by the slave and the application is expecting \r
- * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and\r
- * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be \r
- * used when the user software doesn't guarantee the EV3 is managed before the\r
- * current byte end of tranfer.\r
- * - EV3_2: When the master sends a NACK in order to tell slave that data transmission \r
- * shall end (before sending the STOP condition). In this case slave has to stop sending \r
- * data bytes and expect a Stop condition on the bus.\r
- * \r
- * @note In case the user software does not guarantee that the event EV2 is \r
- * managed before the current byte end of transfer, then user may check on EV2 \r
- * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
- * In this case the communication may be slower.\r
- *\r
- */\r
-\r
-/* Slave RECEIVER mode --------------------------*/ \r
-/* --EV2 */\r
-#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */\r
-/* --EV4 */\r
-#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */\r
-\r
-/* Slave TRANSMITTER mode -----------------------*/\r
-/* --EV3 */\r
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */\r
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */\r
-/* --EV3_2 */\r
-#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */\r
-\r
-/*=========================== End of Events Description ==========================================*/\r
-\r
-#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \\r
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \\r
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \\r
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \\r
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \\r
- ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \\r
- ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_own_address1 \r
- * @{\r
- */\r
-\r
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_clock_speed \r
- * @{\r
- */\r
-\r
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Exported_Functions\r
- * @{\r
- */\r
-\r
-void I2C_DeInit(I2C_TypeDef* I2Cx);\r
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);\r
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);\r
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);\r
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);\r
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);\r
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);\r
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);\r
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);\r
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);\r
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);\r
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);\r
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);\r
-\r
-/**\r
- * @brief\r
- ****************************************************************************************\r
- *\r
- * I2C State Monitoring Functions\r
- * \r
- **************************************************************************************** \r
- * This I2C driver provides three different ways for I2C state monitoring\r
- * depending on the application requirements and constraints:\r
- * \r
- * \r
- * 1) Basic state monitoring:\r
- * Using I2C_CheckEvent() function:\r
- * It compares the status registers (SR1 and SR2) content to a given event\r
- * (can be the combination of one or more flags).\r
- * It returns SUCCESS if the current status includes the given flags \r
- * and returns ERROR if one or more flags are missing in the current status.\r
- * - When to use:\r
- * - This function is suitable for most applications as well as for startup \r
- * activity since the events are fully described in the product reference manual \r
- * (RM0008).\r
- * - It is also suitable for users who need to define their own events.\r
- * - Limitations:\r
- * - If an error occurs (ie. error flags are set besides to the monitored flags),\r
- * the I2C_CheckEvent() function may return SUCCESS despite the communication\r
- * hold or corrupted real state. \r
- * In this case, it is advised to use error interrupts to monitor the error\r
- * events and handle them in the interrupt IRQ handler.\r
- * \r
- * @note \r
- * For error management, it is advised to use the following functions:\r
- * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
- * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.\r
- * Where x is the peripheral instance (I2C1, I2C2 ...)\r
- * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()\r
- * in order to determine which error occured.\r
- * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()\r
- * and/or I2C_GenerateStop() in order to clear the error flag and source,\r
- * and return to correct communication status.\r
- * \r
- *\r
- * 2) Advanced state monitoring:\r
- * Using the function I2C_GetLastEvent() which returns the image of both status \r
- * registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
- * by 16 bits and concatenated to Status Register 1).\r
- * - When to use:\r
- * - This function is suitable for the same applications above but it allows to\r
- * overcome the limitations of I2C_GetFlagStatus() function (see below).\r
- * The returned value could be compared to events already defined in the \r
- * library (stm32f10x_i2c.h) or to custom values defined by user.\r
- * - This function is suitable when multiple flags are monitored at the same time.\r
- * - At the opposite of I2C_CheckEvent() function, this function allows user to\r
- * choose when an event is accepted (when all events flags are set and no \r
- * other flags are set or just when the needed flags are set like \r
- * I2C_CheckEvent() function).\r
- * - Limitations:\r
- * - User may need to define his own events.\r
- * - Same remark concerning the error management is applicable for this \r
- * function if user decides to check only regular communication flags (and \r
- * ignores error flags).\r
- * \r
- *\r
- * 3) Flag-based state monitoring:\r
- * Using the function I2C_GetFlagStatus() which simply returns the status of \r
- * one single flag (ie. I2C_FLAG_RXNE ...). \r
- * - When to use:\r
- * - This function could be used for specific applications or in debug phase.\r
- * - It is suitable when only one flag checking is needed (most I2C events \r
- * are monitored through multiple flags).\r
- * - Limitations: \r
- * - When calling this function, the Status register is accessed. Some flags are\r
- * cleared when the status register is accessed. So checking the status\r
- * of one Flag, may clear other ones.\r
- * - Function may need to be called twice or more in order to monitor one \r
- * single event.\r
- * \r
- */\r
-\r
-/**\r
- * \r
- * 1) Basic state monitoring\r
- *******************************************************************************\r
- */\r
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);\r
-/**\r
- * \r
- * 2) Advanced state monitoring\r
- *******************************************************************************\r
- */\r
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);\r
-/**\r
- * \r
- * 3) Flag-based state monitoring\r
- *******************************************************************************\r
- */\r
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
-/**\r
- *\r
- *******************************************************************************\r
- */\r
-\r
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32F10x_I2C_H */\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_iwdg.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the IWDG \r
- * firmware library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_IWDG_H\r
-#define __STM32F10x_IWDG_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup IWDG\r
- * @{\r
- */\r
-\r
-/** @defgroup IWDG_Exported_Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup IWDG_WriteAccess\r
- * @{\r
- */\r
-\r
-#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)\r
-#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)\r
-#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \\r
- ((ACCESS) == IWDG_WriteAccess_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_prescaler \r
- * @{\r
- */\r
-\r
-#define IWDG_Prescaler_4 ((uint8_t)0x00)\r
-#define IWDG_Prescaler_8 ((uint8_t)0x01)\r
-#define IWDG_Prescaler_16 ((uint8_t)0x02)\r
-#define IWDG_Prescaler_32 ((uint8_t)0x03)\r
-#define IWDG_Prescaler_64 ((uint8_t)0x04)\r
-#define IWDG_Prescaler_128 ((uint8_t)0x05)\r
-#define IWDG_Prescaler_256 ((uint8_t)0x06)\r
-#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \\r
- ((PRESCALER) == IWDG_Prescaler_8) || \\r
- ((PRESCALER) == IWDG_Prescaler_16) || \\r
- ((PRESCALER) == IWDG_Prescaler_32) || \\r
- ((PRESCALER) == IWDG_Prescaler_64) || \\r
- ((PRESCALER) == IWDG_Prescaler_128)|| \\r
- ((PRESCALER) == IWDG_Prescaler_256))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Flag \r
- * @{\r
- */\r
-\r
-#define IWDG_FLAG_PVU ((uint16_t)0x0001)\r
-#define IWDG_FLAG_RVU ((uint16_t)0x0002)\r
-#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))\r
-#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Exported_Functions\r
- * @{\r
- */\r
-\r
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);\r
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);\r
-void IWDG_SetReload(uint16_t Reload);\r
-void IWDG_ReloadCounter(void);\r
-void IWDG_Enable(void);\r
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_IWDG_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_pwr.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the PWR firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_PWR_H\r
-#define __STM32F10x_PWR_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup PWR\r
- * @{\r
- */ \r
-\r
-/** @defgroup PWR_Exported_Types\r
- * @{\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup PWR_Exported_Constants\r
- * @{\r
- */ \r
-\r
-/** @defgroup PVD_detection_level \r
- * @{\r
- */ \r
-\r
-#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)\r
-#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)\r
-#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)\r
-#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)\r
-#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)\r
-#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)\r
-#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)\r
-#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)\r
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \\r
- ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \\r
- ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \\r
- ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Regulator_state_is_STOP_mode \r
- * @{\r
- */\r
-\r
-#define PWR_Regulator_ON ((uint32_t)0x00000000)\r
-#define PWR_Regulator_LowPower ((uint32_t)0x00000001)\r
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \\r
- ((REGULATOR) == PWR_Regulator_LowPower))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup STOP_mode_entry \r
- * @{\r
- */\r
-\r
-#define PWR_STOPEntry_WFI ((uint8_t)0x01)\r
-#define PWR_STOPEntry_WFE ((uint8_t)0x02)\r
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Flag \r
- * @{\r
- */\r
-\r
-#define PWR_FLAG_WU ((uint32_t)0x00000001)\r
-#define PWR_FLAG_SB ((uint32_t)0x00000002)\r
-#define PWR_FLAG_PVDO ((uint32_t)0x00000004)\r
-#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \\r
- ((FLAG) == PWR_FLAG_PVDO))\r
-\r
-#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Exported_Functions\r
- * @{\r
- */\r
-\r
-void PWR_DeInit(void);\r
-void PWR_BackupAccessCmd(FunctionalState NewState);\r
-void PWR_PVDCmd(FunctionalState NewState);\r
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);\r
-void PWR_WakeUpPinCmd(FunctionalState NewState);\r
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);\r
-void PWR_EnterSTANDBYMode(void);\r
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);\r
-void PWR_ClearFlag(uint32_t PWR_FLAG);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_PWR_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_rcc.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the RCC firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_RCC_H\r
-#define __STM32F10x_RCC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup RCC\r
- * @{\r
- */\r
-\r
-/** @defgroup RCC_Exported_Types\r
- * @{\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */\r
- uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */\r
- uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */\r
- uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */\r
- uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */\r
-}RCC_ClocksTypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup HSE_configuration \r
- * @{\r
- */\r
-\r
-#define RCC_HSE_OFF ((uint32_t)0x00000000)\r
-#define RCC_HSE_ON ((uint32_t)0x00010000)\r
-#define RCC_HSE_Bypass ((uint32_t)0x00040000)\r
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\r
- ((HSE) == RCC_HSE_Bypass))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup PLL_entry_clock_source \r
- * @{\r
- */\r
-\r
-#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)\r
-\r
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_CL)\r
- #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)\r
- #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)\r
- #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \\r
- ((SOURCE) == RCC_PLLSource_HSE_Div1) || \\r
- ((SOURCE) == RCC_PLLSource_HSE_Div2))\r
-#else\r
- #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)\r
- #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \\r
- ((SOURCE) == RCC_PLLSource_PREDIV1))\r
-#endif /* STM32F10X_CL */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup PLL_multiplication_factor \r
- * @{\r
- */\r
-#ifndef STM32F10X_CL\r
- #define RCC_PLLMul_2 ((uint32_t)0x00000000)\r
- #define RCC_PLLMul_3 ((uint32_t)0x00040000)\r
- #define RCC_PLLMul_4 ((uint32_t)0x00080000)\r
- #define RCC_PLLMul_5 ((uint32_t)0x000C0000)\r
- #define RCC_PLLMul_6 ((uint32_t)0x00100000)\r
- #define RCC_PLLMul_7 ((uint32_t)0x00140000)\r
- #define RCC_PLLMul_8 ((uint32_t)0x00180000)\r
- #define RCC_PLLMul_9 ((uint32_t)0x001C0000)\r
- #define RCC_PLLMul_10 ((uint32_t)0x00200000)\r
- #define RCC_PLLMul_11 ((uint32_t)0x00240000)\r
- #define RCC_PLLMul_12 ((uint32_t)0x00280000)\r
- #define RCC_PLLMul_13 ((uint32_t)0x002C0000)\r
- #define RCC_PLLMul_14 ((uint32_t)0x00300000)\r
- #define RCC_PLLMul_15 ((uint32_t)0x00340000)\r
- #define RCC_PLLMul_16 ((uint32_t)0x00380000)\r
- #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \\r
- ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \\r
- ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \\r
- ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \\r
- ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \\r
- ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \\r
- ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \\r
- ((MUL) == RCC_PLLMul_16))\r
-\r
-#else\r
- #define RCC_PLLMul_4 ((uint32_t)0x00080000)\r
- #define RCC_PLLMul_5 ((uint32_t)0x000C0000)\r
- #define RCC_PLLMul_6 ((uint32_t)0x00100000)\r
- #define RCC_PLLMul_7 ((uint32_t)0x00140000)\r
- #define RCC_PLLMul_8 ((uint32_t)0x00180000)\r
- #define RCC_PLLMul_9 ((uint32_t)0x001C0000)\r
- #define RCC_PLLMul_6_5 ((uint32_t)0x00340000)\r
-\r
- #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \\r
- ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \\r
- ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \\r
- ((MUL) == RCC_PLLMul_6_5))\r
-#endif /* STM32F10X_CL */ \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PREDIV1_division_factor\r
- * @{\r
- */\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL)\r
- #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)\r
- #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)\r
- #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)\r
- #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)\r
- #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)\r
- #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)\r
- #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)\r
- #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)\r
- #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)\r
- #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)\r
- #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)\r
- #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)\r
- #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)\r
- #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)\r
- #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)\r
- #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)\r
-\r
- #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \\r
- ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \\r
- ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \\r
- ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \\r
- ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \\r
- ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \\r
- ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \\r
- ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))\r
-#endif\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup PREDIV1_clock_source\r
- * @{\r
- */\r
-#ifdef STM32F10X_CL\r
-/* PREDIV1 clock source (for STM32 connectivity line devices) */\r
- #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) \r
- #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) \r
-\r
- #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \\r
- ((SOURCE) == RCC_PREDIV1_Source_PLL2)) \r
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
-/* PREDIV1 clock source (for STM32 Value line devices) */\r
- #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) \r
-\r
- #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) \r
-#endif\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef STM32F10X_CL\r
-/** @defgroup PREDIV2_division_factor\r
- * @{\r
- */\r
- \r
- #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)\r
- #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)\r
- #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)\r
- #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)\r
- #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)\r
- #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)\r
- #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)\r
- #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)\r
- #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)\r
- #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)\r
- #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)\r
- #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)\r
- #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)\r
- #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)\r
- #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)\r
- #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)\r
-\r
- #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \\r
- ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \\r
- ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \\r
- ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \\r
- ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \\r
- ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \\r
- ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \\r
- ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup PLL2_multiplication_factor\r
- * @{\r
- */\r
- \r
- #define RCC_PLL2Mul_8 ((uint32_t)0x00000600)\r
- #define RCC_PLL2Mul_9 ((uint32_t)0x00000700)\r
- #define RCC_PLL2Mul_10 ((uint32_t)0x00000800)\r
- #define RCC_PLL2Mul_11 ((uint32_t)0x00000900)\r
- #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)\r
- #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)\r
- #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)\r
- #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)\r
- #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)\r
-\r
- #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \\r
- ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \\r
- ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \\r
- ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \\r
- ((MUL) == RCC_PLL2Mul_20))\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup PLL3_multiplication_factor\r
- * @{\r
- */\r
-\r
- #define RCC_PLL3Mul_8 ((uint32_t)0x00006000)\r
- #define RCC_PLL3Mul_9 ((uint32_t)0x00007000)\r
- #define RCC_PLL3Mul_10 ((uint32_t)0x00008000)\r
- #define RCC_PLL3Mul_11 ((uint32_t)0x00009000)\r
- #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)\r
- #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)\r
- #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)\r
- #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)\r
- #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)\r
-\r
- #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \\r
- ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \\r
- ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \\r
- ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \\r
- ((MUL) == RCC_PLL3Mul_20))\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* STM32F10X_CL */\r
-\r
-\r
-/** @defgroup System_clock_source \r
- * @{\r
- */\r
-\r
-#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)\r
-#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)\r
-#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)\r
-#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \\r
- ((SOURCE) == RCC_SYSCLKSource_HSE) || \\r
- ((SOURCE) == RCC_SYSCLKSource_PLLCLK))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup AHB_clock_source \r
- * @{\r
- */\r
-\r
-#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)\r
-#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)\r
-#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)\r
-#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)\r
-#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)\r
-#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)\r
-#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)\r
-#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)\r
-#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)\r
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \\r
- ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \\r
- ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \\r
- ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \\r
- ((HCLK) == RCC_SYSCLK_Div512))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup APB1_APB2_clock_source \r
- * @{\r
- */\r
-\r
-#define RCC_HCLK_Div1 ((uint32_t)0x00000000)\r
-#define RCC_HCLK_Div2 ((uint32_t)0x00000400)\r
-#define RCC_HCLK_Div4 ((uint32_t)0x00000500)\r
-#define RCC_HCLK_Div8 ((uint32_t)0x00000600)\r
-#define RCC_HCLK_Div16 ((uint32_t)0x00000700)\r
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \\r
- ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \\r
- ((PCLK) == RCC_HCLK_Div16))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Interrupt_source \r
- * @{\r
- */\r
-\r
-#define RCC_IT_LSIRDY ((uint8_t)0x01)\r
-#define RCC_IT_LSERDY ((uint8_t)0x02)\r
-#define RCC_IT_HSIRDY ((uint8_t)0x04)\r
-#define RCC_IT_HSERDY ((uint8_t)0x08)\r
-#define RCC_IT_PLLRDY ((uint8_t)0x10)\r
-#define RCC_IT_CSS ((uint8_t)0x80)\r
-\r
-#ifndef STM32F10X_CL\r
- #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))\r
- #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \\r
- ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \\r
- ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))\r
- #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))\r
-#else\r
- #define RCC_IT_PLL2RDY ((uint8_t)0x20)\r
- #define RCC_IT_PLL3RDY ((uint8_t)0x40)\r
- #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))\r
- #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \\r
- ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \\r
- ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \\r
- ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))\r
- #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)\r
-#endif /* STM32F10X_CL */ \r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifndef STM32F10X_CL\r
-/** @defgroup USB_Device_clock_source \r
- * @{\r
- */\r
-\r
- #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)\r
- #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)\r
-\r
- #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \\r
- ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))\r
-/**\r
- * @}\r
- */\r
-#else\r
-/** @defgroup USB_OTG_FS_clock_source \r
- * @{\r
- */\r
- #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00)\r
- #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01)\r
-\r
- #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \\r
- ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))\r
-/**\r
- * @}\r
- */\r
-#endif /* STM32F10X_CL */ \r
-\r
-\r
-#ifdef STM32F10X_CL\r
-/** @defgroup I2S2_clock_source \r
- * @{\r
- */\r
- #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)\r
- #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)\r
-\r
- #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \\r
- ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2S3_clock_source \r
- * @{\r
- */\r
- #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)\r
- #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)\r
-\r
- #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \\r
- ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) \r
-/**\r
- * @}\r
- */\r
-#endif /* STM32F10X_CL */ \r
- \r
-\r
-/** @defgroup ADC_clock_source \r
- * @{\r
- */\r
-\r
-#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)\r
-#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)\r
-#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)\r
-#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)\r
-#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \\r
- ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup LSE_configuration \r
- * @{\r
- */\r
-\r
-#define RCC_LSE_OFF ((uint8_t)0x00)\r
-#define RCC_LSE_ON ((uint8_t)0x01)\r
-#define RCC_LSE_Bypass ((uint8_t)0x04)\r
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\r
- ((LSE) == RCC_LSE_Bypass))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_clock_source \r
- * @{\r
- */\r
-\r
-#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)\r
-#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)\r
-#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)\r
-#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \\r
- ((SOURCE) == RCC_RTCCLKSource_LSI) || \\r
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup AHB_peripheral \r
- * @{\r
- */\r
-\r
-#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)\r
-#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)\r
-#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)\r
-#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)\r
-#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)\r
-\r
-#ifndef STM32F10X_CL\r
- #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)\r
- #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)\r
- #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))\r
-#else\r
- #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)\r
- #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)\r
- #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)\r
- #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)\r
-\r
- #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))\r
- #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))\r
-#endif /* STM32F10X_CL */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup APB2_peripheral \r
- * @{\r
- */\r
-\r
-#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)\r
-#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)\r
-#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)\r
-#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)\r
-#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)\r
-#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)\r
-#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)\r
-#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)\r
-#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)\r
-#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)\r
-#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)\r
-#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)\r
-#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)\r
-#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)\r
-#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)\r
-#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)\r
-#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)\r
-#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)\r
-#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)\r
-#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)\r
-#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)\r
-\r
-#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup APB1_peripheral \r
- * @{\r
- */\r
-\r
-#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)\r
-#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)\r
-#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)\r
-#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)\r
-#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)\r
-#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)\r
-#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)\r
-#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)\r
-#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)\r
-#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)\r
-#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)\r
-#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)\r
-#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)\r
-#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)\r
-#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)\r
-#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)\r
-#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)\r
-#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)\r
-#define RCC_APB1Periph_USB ((uint32_t)0x00800000)\r
-#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)\r
-#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)\r
-#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)\r
-#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)\r
-#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)\r
-#define RCC_APB1Periph_CEC ((uint32_t)0x40000000)\r
- \r
-#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Clock_source_to_output_on_MCO_pin \r
- * @{\r
- */\r
-\r
-#define RCC_MCO_NoClock ((uint8_t)0x00)\r
-#define RCC_MCO_SYSCLK ((uint8_t)0x04)\r
-#define RCC_MCO_HSI ((uint8_t)0x05)\r
-#define RCC_MCO_HSE ((uint8_t)0x06)\r
-#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)\r
-\r
-#ifndef STM32F10X_CL\r
- #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \\r
- ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \\r
- ((MCO) == RCC_MCO_PLLCLK_Div2))\r
-#else\r
- #define RCC_MCO_PLL2CLK ((uint8_t)0x08)\r
- #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)\r
- #define RCC_MCO_XT1 ((uint8_t)0x0A)\r
- #define RCC_MCO_PLL3CLK ((uint8_t)0x0B)\r
-\r
- #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \\r
- ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \\r
- ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \\r
- ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \\r
- ((MCO) == RCC_MCO_PLL3CLK))\r
-#endif /* STM32F10X_CL */ \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Flag \r
- * @{\r
- */\r
-\r
-#define RCC_FLAG_HSIRDY ((uint8_t)0x21)\r
-#define RCC_FLAG_HSERDY ((uint8_t)0x31)\r
-#define RCC_FLAG_PLLRDY ((uint8_t)0x39)\r
-#define RCC_FLAG_LSERDY ((uint8_t)0x41)\r
-#define RCC_FLAG_LSIRDY ((uint8_t)0x61)\r
-#define RCC_FLAG_PINRST ((uint8_t)0x7A)\r
-#define RCC_FLAG_PORRST ((uint8_t)0x7B)\r
-#define RCC_FLAG_SFTRST ((uint8_t)0x7C)\r
-#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)\r
-#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)\r
-#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)\r
-\r
-#ifndef STM32F10X_CL\r
- #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\r
- ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \\r
- ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \\r
- ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \\r
- ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \\r
- ((FLAG) == RCC_FLAG_LPWRRST))\r
-#else\r
- #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) \r
- #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) \r
- #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\r
- ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \\r
- ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \\r
- ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \\r
- ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \\r
- ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \\r
- ((FLAG) == RCC_FLAG_LPWRRST))\r
-#endif /* STM32F10X_CL */ \r
-\r
-#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Exported_Functions\r
- * @{\r
- */\r
-\r
-void RCC_DeInit(void);\r
-void RCC_HSEConfig(uint32_t RCC_HSE);\r
-ErrorStatus RCC_WaitForHSEStartUp(void);\r
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);\r
-void RCC_HSICmd(FunctionalState NewState);\r
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);\r
-void RCC_PLLCmd(FunctionalState NewState);\r
-\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL)\r
- void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);\r
-#endif\r
-\r
-#ifdef STM32F10X_CL\r
- void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);\r
- void RCC_PLL2Config(uint32_t RCC_PLL2Mul);\r
- void RCC_PLL2Cmd(FunctionalState NewState);\r
- void RCC_PLL3Config(uint32_t RCC_PLL3Mul);\r
- void RCC_PLL3Cmd(FunctionalState NewState);\r
-#endif /* STM32F10X_CL */ \r
-\r
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);\r
-uint8_t RCC_GetSYSCLKSource(void);\r
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK);\r
-void RCC_PCLK1Config(uint32_t RCC_HCLK);\r
-void RCC_PCLK2Config(uint32_t RCC_HCLK);\r
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);\r
-\r
-#ifndef STM32F10X_CL\r
- void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);\r
-#else\r
- void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);\r
-#endif /* STM32F10X_CL */ \r
-\r
-void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);\r
-\r
-#ifdef STM32F10X_CL\r
- void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); \r
- void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);\r
-#endif /* STM32F10X_CL */ \r
-\r
-void RCC_LSEConfig(uint8_t RCC_LSE);\r
-void RCC_LSICmd(FunctionalState NewState);\r
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);\r
-void RCC_RTCCLKCmd(FunctionalState NewState);\r
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);\r
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
-\r
-#ifdef STM32F10X_CL\r
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
-#endif /* STM32F10X_CL */ \r
-\r
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
-void RCC_BackupResetCmd(FunctionalState NewState);\r
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState);\r
-void RCC_MCOConfig(uint8_t RCC_MCO);\r
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);\r
-void RCC_ClearFlag(void);\r
-ITStatus RCC_GetITStatus(uint8_t RCC_IT);\r
-void RCC_ClearITPendingBit(uint8_t RCC_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_RCC_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_rtc.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the RTC firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_RTC_H\r
-#define __STM32F10x_RTC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup RTC\r
- * @{\r
- */ \r
-\r
-/** @defgroup RTC_Exported_Types\r
- * @{\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup RTC_interrupts_define \r
- * @{\r
- */\r
-\r
-#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */\r
-#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */\r
-#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */\r
-#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))\r
-#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \\r
- ((IT) == RTC_IT_SEC))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_interrupts_flags \r
- * @{\r
- */\r
-\r
-#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */\r
-#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */\r
-#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */\r
-#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */\r
-#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */\r
-#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))\r
-#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \\r
- ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \\r
- ((FLAG) == RTC_FLAG_SEC))\r
-#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Exported_Functions\r
- * @{\r
- */\r
-\r
-void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);\r
-void RTC_EnterConfigMode(void);\r
-void RTC_ExitConfigMode(void);\r
-uint32_t RTC_GetCounter(void);\r
-void RTC_SetCounter(uint32_t CounterValue);\r
-void RTC_SetPrescaler(uint32_t PrescalerValue);\r
-void RTC_SetAlarm(uint32_t AlarmValue);\r
-uint32_t RTC_GetDivider(void);\r
-void RTC_WaitForLastTask(void);\r
-void RTC_WaitForSynchro(void);\r
-FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);\r
-void RTC_ClearFlag(uint16_t RTC_FLAG);\r
-ITStatus RTC_GetITStatus(uint16_t RTC_IT);\r
-void RTC_ClearITPendingBit(uint16_t RTC_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_RTC_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_sdio.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the SDIO firmware\r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_SDIO_H\r
-#define __STM32F10x_SDIO_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup SDIO\r
- * @{\r
- */\r
-\r
-/** @defgroup SDIO_Exported_Types\r
- * @{\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.\r
- This parameter can be a value of @ref SDIO_Clock_Edge */\r
-\r
- uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is\r
- enabled or disabled.\r
- This parameter can be a value of @ref SDIO_Clock_Bypass */\r
-\r
- uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or\r
- disabled when the bus is idle.\r
- This parameter can be a value of @ref SDIO_Clock_Power_Save */\r
-\r
- uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.\r
- This parameter can be a value of @ref SDIO_Bus_Wide */\r
-\r
- uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.\r
- This parameter can be a value of @ref SDIO_Hardware_Flow_Control */\r
-\r
- uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.\r
- This parameter can be a value between 0x00 and 0xFF. */\r
- \r
-} SDIO_InitTypeDef;\r
-\r
-typedef struct\r
-{\r
- uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent\r
- to a card as part of a command message. If a command\r
- contains an argument, it must be loaded into this register\r
- before writing the command to the command register */\r
-\r
- uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */\r
-\r
- uint32_t SDIO_Response; /*!< Specifies the SDIO response type.\r
- This parameter can be a value of @ref SDIO_Response_Type */\r
-\r
- uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.\r
- This parameter can be a value of @ref SDIO_Wait_Interrupt_State */\r
-\r
- uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)\r
- is enabled or disabled.\r
- This parameter can be a value of @ref SDIO_CPSM_State */\r
-} SDIO_CmdInitTypeDef;\r
-\r
-typedef struct\r
-{\r
- uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */\r
-\r
- uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */\r
- \r
- uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.\r
- This parameter can be a value of @ref SDIO_Data_Block_Size */\r
- \r
- uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer\r
- is a read or write.\r
- This parameter can be a value of @ref SDIO_Transfer_Direction */\r
- \r
- uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.\r
- This parameter can be a value of @ref SDIO_Transfer_Type */\r
- \r
- uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)\r
- is enabled or disabled.\r
- This parameter can be a value of @ref SDIO_DPSM_State */\r
-} SDIO_DataInitTypeDef;\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SDIO_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup SDIO_Clock_Edge \r
- * @{\r
- */\r
-\r
-#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)\r
-#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)\r
-#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \\r
- ((EDGE) == SDIO_ClockEdge_Falling))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Clock_Bypass \r
- * @{\r
- */\r
-\r
-#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)\r
-#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) \r
-#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \\r
- ((BYPASS) == SDIO_ClockBypass_Enable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SDIO_Clock_Power_Save \r
- * @{\r
- */\r
-\r
-#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)\r
-#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) \r
-#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \\r
- ((SAVE) == SDIO_ClockPowerSave_Enable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Bus_Wide \r
- * @{\r
- */\r
-\r
-#define SDIO_BusWide_1b ((uint32_t)0x00000000)\r
-#define SDIO_BusWide_4b ((uint32_t)0x00000800)\r
-#define SDIO_BusWide_8b ((uint32_t)0x00001000)\r
-#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \\r
- ((WIDE) == SDIO_BusWide_8b))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Hardware_Flow_Control \r
- * @{\r
- */\r
-\r
-#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)\r
-#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)\r
-#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \\r
- ((CONTROL) == SDIO_HardwareFlowControl_Enable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Power_State \r
- * @{\r
- */\r
-\r
-#define SDIO_PowerState_OFF ((uint32_t)0x00000000)\r
-#define SDIO_PowerState_ON ((uint32_t)0x00000003)\r
-#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) \r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup SDIO_Interrupt_soucres \r
- * @{\r
- */\r
-\r
-#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)\r
-#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)\r
-#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)\r
-#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)\r
-#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)\r
-#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)\r
-#define SDIO_IT_CMDREND ((uint32_t)0x00000040)\r
-#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)\r
-#define SDIO_IT_DATAEND ((uint32_t)0x00000100)\r
-#define SDIO_IT_STBITERR ((uint32_t)0x00000200)\r
-#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)\r
-#define SDIO_IT_CMDACT ((uint32_t)0x00000800)\r
-#define SDIO_IT_TXACT ((uint32_t)0x00001000)\r
-#define SDIO_IT_RXACT ((uint32_t)0x00002000)\r
-#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)\r
-#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)\r
-#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)\r
-#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)\r
-#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)\r
-#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)\r
-#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)\r
-#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)\r
-#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)\r
-#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)\r
-#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SDIO_Command_Index\r
- * @{\r
- */\r
-\r
-#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Response_Type \r
- * @{\r
- */\r
-\r
-#define SDIO_Response_No ((uint32_t)0x00000000)\r
-#define SDIO_Response_Short ((uint32_t)0x00000040)\r
-#define SDIO_Response_Long ((uint32_t)0x000000C0)\r
-#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \\r
- ((RESPONSE) == SDIO_Response_Short) || \\r
- ((RESPONSE) == SDIO_Response_Long))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Wait_Interrupt_State \r
- * @{\r
- */\r
-\r
-#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */\r
-#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */\r
-#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */\r
-#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \\r
- ((WAIT) == SDIO_Wait_Pend))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_CPSM_State \r
- * @{\r
- */\r
-\r
-#define SDIO_CPSM_Disable ((uint32_t)0x00000000)\r
-#define SDIO_CPSM_Enable ((uint32_t)0x00000400)\r
-#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SDIO_Response_Registers \r
- * @{\r
- */\r
-\r
-#define SDIO_RESP1 ((uint32_t)0x00000000)\r
-#define SDIO_RESP2 ((uint32_t)0x00000004)\r
-#define SDIO_RESP3 ((uint32_t)0x00000008)\r
-#define SDIO_RESP4 ((uint32_t)0x0000000C)\r
-#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \\r
- ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Data_Length \r
- * @{\r
- */\r
-\r
-#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Data_Block_Size \r
- * @{\r
- */\r
-\r
-#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)\r
-#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)\r
-#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)\r
-#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)\r
-#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)\r
-#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)\r
-#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)\r
-#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)\r
-#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)\r
-#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)\r
-#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)\r
-#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)\r
-#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)\r
-#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)\r
-#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)\r
-#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \\r
- ((SIZE) == SDIO_DataBlockSize_2b) || \\r
- ((SIZE) == SDIO_DataBlockSize_4b) || \\r
- ((SIZE) == SDIO_DataBlockSize_8b) || \\r
- ((SIZE) == SDIO_DataBlockSize_16b) || \\r
- ((SIZE) == SDIO_DataBlockSize_32b) || \\r
- ((SIZE) == SDIO_DataBlockSize_64b) || \\r
- ((SIZE) == SDIO_DataBlockSize_128b) || \\r
- ((SIZE) == SDIO_DataBlockSize_256b) || \\r
- ((SIZE) == SDIO_DataBlockSize_512b) || \\r
- ((SIZE) == SDIO_DataBlockSize_1024b) || \\r
- ((SIZE) == SDIO_DataBlockSize_2048b) || \\r
- ((SIZE) == SDIO_DataBlockSize_4096b) || \\r
- ((SIZE) == SDIO_DataBlockSize_8192b) || \\r
- ((SIZE) == SDIO_DataBlockSize_16384b)) \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Transfer_Direction \r
- * @{\r
- */\r
-\r
-#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)\r
-#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)\r
-#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \\r
- ((DIR) == SDIO_TransferDir_ToSDIO))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Transfer_Type \r
- * @{\r
- */\r
-\r
-#define SDIO_TransferMode_Block ((uint32_t)0x00000000)\r
-#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)\r
-#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \\r
- ((MODE) == SDIO_TransferMode_Block))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_DPSM_State \r
- * @{\r
- */\r
-\r
-#define SDIO_DPSM_Disable ((uint32_t)0x00000000)\r
-#define SDIO_DPSM_Enable ((uint32_t)0x00000001)\r
-#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Flags \r
- * @{\r
- */\r
-\r
-#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)\r
-#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)\r
-#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)\r
-#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)\r
-#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)\r
-#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)\r
-#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)\r
-#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)\r
-#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)\r
-#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)\r
-#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)\r
-#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)\r
-#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)\r
-#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)\r
-#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)\r
-#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)\r
-#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)\r
-#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)\r
-#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)\r
-#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)\r
-#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)\r
-#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)\r
-#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)\r
-#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)\r
-#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \\r
- ((FLAG) == SDIO_FLAG_DCRCFAIL) || \\r
- ((FLAG) == SDIO_FLAG_CTIMEOUT) || \\r
- ((FLAG) == SDIO_FLAG_DTIMEOUT) || \\r
- ((FLAG) == SDIO_FLAG_TXUNDERR) || \\r
- ((FLAG) == SDIO_FLAG_RXOVERR) || \\r
- ((FLAG) == SDIO_FLAG_CMDREND) || \\r
- ((FLAG) == SDIO_FLAG_CMDSENT) || \\r
- ((FLAG) == SDIO_FLAG_DATAEND) || \\r
- ((FLAG) == SDIO_FLAG_STBITERR) || \\r
- ((FLAG) == SDIO_FLAG_DBCKEND) || \\r
- ((FLAG) == SDIO_FLAG_CMDACT) || \\r
- ((FLAG) == SDIO_FLAG_TXACT) || \\r
- ((FLAG) == SDIO_FLAG_RXACT) || \\r
- ((FLAG) == SDIO_FLAG_TXFIFOHE) || \\r
- ((FLAG) == SDIO_FLAG_RXFIFOHF) || \\r
- ((FLAG) == SDIO_FLAG_TXFIFOF) || \\r
- ((FLAG) == SDIO_FLAG_RXFIFOF) || \\r
- ((FLAG) == SDIO_FLAG_TXFIFOE) || \\r
- ((FLAG) == SDIO_FLAG_RXFIFOE) || \\r
- ((FLAG) == SDIO_FLAG_TXDAVL) || \\r
- ((FLAG) == SDIO_FLAG_RXDAVL) || \\r
- ((FLAG) == SDIO_FLAG_SDIOIT) || \\r
- ((FLAG) == SDIO_FLAG_CEATAEND))\r
-\r
-#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))\r
-\r
-#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \\r
- ((IT) == SDIO_IT_DCRCFAIL) || \\r
- ((IT) == SDIO_IT_CTIMEOUT) || \\r
- ((IT) == SDIO_IT_DTIMEOUT) || \\r
- ((IT) == SDIO_IT_TXUNDERR) || \\r
- ((IT) == SDIO_IT_RXOVERR) || \\r
- ((IT) == SDIO_IT_CMDREND) || \\r
- ((IT) == SDIO_IT_CMDSENT) || \\r
- ((IT) == SDIO_IT_DATAEND) || \\r
- ((IT) == SDIO_IT_STBITERR) || \\r
- ((IT) == SDIO_IT_DBCKEND) || \\r
- ((IT) == SDIO_IT_CMDACT) || \\r
- ((IT) == SDIO_IT_TXACT) || \\r
- ((IT) == SDIO_IT_RXACT) || \\r
- ((IT) == SDIO_IT_TXFIFOHE) || \\r
- ((IT) == SDIO_IT_RXFIFOHF) || \\r
- ((IT) == SDIO_IT_TXFIFOF) || \\r
- ((IT) == SDIO_IT_RXFIFOF) || \\r
- ((IT) == SDIO_IT_TXFIFOE) || \\r
- ((IT) == SDIO_IT_RXFIFOE) || \\r
- ((IT) == SDIO_IT_TXDAVL) || \\r
- ((IT) == SDIO_IT_RXDAVL) || \\r
- ((IT) == SDIO_IT_SDIOIT) || \\r
- ((IT) == SDIO_IT_CEATAEND))\r
-\r
-#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Read_Wait_Mode \r
- * @{\r
- */\r
-\r
-#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)\r
-#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)\r
-#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \\r
- ((MODE) == SDIO_ReadWaitMode_DATA2))\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Exported_Functions\r
- * @{\r
- */\r
-\r
-void SDIO_DeInit(void);\r
-void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);\r
-void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);\r
-void SDIO_ClockCmd(FunctionalState NewState);\r
-void SDIO_SetPowerState(uint32_t SDIO_PowerState);\r
-uint32_t SDIO_GetPowerState(void);\r
-void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);\r
-void SDIO_DMACmd(FunctionalState NewState);\r
-void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);\r
-void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);\r
-uint8_t SDIO_GetCommandResponse(void);\r
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);\r
-void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r
-void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r
-uint32_t SDIO_GetDataCounter(void);\r
-uint32_t SDIO_ReadData(void);\r
-void SDIO_WriteData(uint32_t Data);\r
-uint32_t SDIO_GetFIFOCount(void);\r
-void SDIO_StartSDIOReadWait(FunctionalState NewState);\r
-void SDIO_StopSDIOReadWait(FunctionalState NewState);\r
-void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);\r
-void SDIO_SetSDIOOperation(FunctionalState NewState);\r
-void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);\r
-void SDIO_CommandCompletionCmd(FunctionalState NewState);\r
-void SDIO_CEATAITCmd(FunctionalState NewState);\r
-void SDIO_SendCEATACmd(FunctionalState NewState);\r
-FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);\r
-void SDIO_ClearFlag(uint32_t SDIO_FLAG);\r
-ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);\r
-void SDIO_ClearITPendingBit(uint32_t SDIO_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_SDIO_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_spi.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the SPI firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_SPI_H\r
-#define __STM32F10x_SPI_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup SPI\r
- * @{\r
- */ \r
-\r
-/** @defgroup SPI_Exported_Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief SPI Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.\r
- This parameter can be a value of @ref SPI_data_direction */\r
-\r
- uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.\r
- This parameter can be a value of @ref SPI_mode */\r
-\r
- uint16_t SPI_DataSize; /*!< Specifies the SPI data size.\r
- This parameter can be a value of @ref SPI_data_size */\r
-\r
- uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.\r
- This parameter can be a value of @ref SPI_Clock_Polarity */\r
-\r
- uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.\r
- This parameter can be a value of @ref SPI_Clock_Phase */\r
-\r
- uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by\r
- hardware (NSS pin) or by software using the SSI bit.\r
- This parameter can be a value of @ref SPI_Slave_Select_management */\r
- \r
- uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be\r
- used to configure the transmit and receive SCK clock.\r
- This parameter can be a value of @ref SPI_BaudRate_Prescaler.\r
- @note The communication clock is derived from the master\r
- clock. The slave clock does not need to be set. */\r
-\r
- uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.\r
- This parameter can be a value of @ref SPI_MSB_LSB_transmission */\r
-\r
- uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */\r
-}SPI_InitTypeDef;\r
-\r
-/** \r
- * @brief I2S Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
-\r
- uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.\r
- This parameter can be a value of @ref I2S_Mode */\r
-\r
- uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.\r
- This parameter can be a value of @ref I2S_Standard */\r
-\r
- uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.\r
- This parameter can be a value of @ref I2S_Data_Format */\r
-\r
- uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.\r
- This parameter can be a value of @ref I2S_MCLK_Output */\r
-\r
- uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.\r
- This parameter can be a value of @ref I2S_Audio_Frequency */\r
-\r
- uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.\r
- This parameter can be a value of @ref I2S_Clock_Polarity */\r
-}I2S_InitTypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Exported_Constants\r
- * @{\r
- */\r
-\r
-#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \\r
- ((PERIPH) == SPI2) || \\r
- ((PERIPH) == SPI3))\r
-\r
-#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \\r
- ((PERIPH) == SPI3))\r
-\r
-/** @defgroup SPI_data_direction \r
- * @{\r
- */\r
- \r
-#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)\r
-#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)\r
-#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)\r
-#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)\r
-#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \\r
- ((MODE) == SPI_Direction_2Lines_RxOnly) || \\r
- ((MODE) == SPI_Direction_1Line_Rx) || \\r
- ((MODE) == SPI_Direction_1Line_Tx))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_mode \r
- * @{\r
- */\r
-\r
-#define SPI_Mode_Master ((uint16_t)0x0104)\r
-#define SPI_Mode_Slave ((uint16_t)0x0000)\r
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \\r
- ((MODE) == SPI_Mode_Slave))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_data_size \r
- * @{\r
- */\r
-\r
-#define SPI_DataSize_16b ((uint16_t)0x0800)\r
-#define SPI_DataSize_8b ((uint16_t)0x0000)\r
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \\r
- ((DATASIZE) == SPI_DataSize_8b))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SPI_Clock_Polarity \r
- * @{\r
- */\r
-\r
-#define SPI_CPOL_Low ((uint16_t)0x0000)\r
-#define SPI_CPOL_High ((uint16_t)0x0002)\r
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \\r
- ((CPOL) == SPI_CPOL_High))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Clock_Phase \r
- * @{\r
- */\r
-\r
-#define SPI_CPHA_1Edge ((uint16_t)0x0000)\r
-#define SPI_CPHA_2Edge ((uint16_t)0x0001)\r
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \\r
- ((CPHA) == SPI_CPHA_2Edge))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Slave_Select_management \r
- * @{\r
- */\r
-\r
-#define SPI_NSS_Soft ((uint16_t)0x0200)\r
-#define SPI_NSS_Hard ((uint16_t)0x0000)\r
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \\r
- ((NSS) == SPI_NSS_Hard))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SPI_BaudRate_Prescaler \r
- * @{\r
- */\r
-\r
-#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)\r
-#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)\r
-#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)\r
-#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)\r
-#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)\r
-#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)\r
-#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)\r
-#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)\r
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_4) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_8) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_16) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_32) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_64) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_128) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_256))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SPI_MSB_LSB_transmission \r
- * @{\r
- */\r
-\r
-#define SPI_FirstBit_MSB ((uint16_t)0x0000)\r
-#define SPI_FirstBit_LSB ((uint16_t)0x0080)\r
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \\r
- ((BIT) == SPI_FirstBit_LSB))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2S_Mode \r
- * @{\r
- */\r
-\r
-#define I2S_Mode_SlaveTx ((uint16_t)0x0000)\r
-#define I2S_Mode_SlaveRx ((uint16_t)0x0100)\r
-#define I2S_Mode_MasterTx ((uint16_t)0x0200)\r
-#define I2S_Mode_MasterRx ((uint16_t)0x0300)\r
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \\r
- ((MODE) == I2S_Mode_SlaveRx) || \\r
- ((MODE) == I2S_Mode_MasterTx) || \\r
- ((MODE) == I2S_Mode_MasterRx) )\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2S_Standard \r
- * @{\r
- */\r
-\r
-#define I2S_Standard_Phillips ((uint16_t)0x0000)\r
-#define I2S_Standard_MSB ((uint16_t)0x0010)\r
-#define I2S_Standard_LSB ((uint16_t)0x0020)\r
-#define I2S_Standard_PCMShort ((uint16_t)0x0030)\r
-#define I2S_Standard_PCMLong ((uint16_t)0x00B0)\r
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \\r
- ((STANDARD) == I2S_Standard_MSB) || \\r
- ((STANDARD) == I2S_Standard_LSB) || \\r
- ((STANDARD) == I2S_Standard_PCMShort) || \\r
- ((STANDARD) == I2S_Standard_PCMLong))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2S_Data_Format \r
- * @{\r
- */\r
-\r
-#define I2S_DataFormat_16b ((uint16_t)0x0000)\r
-#define I2S_DataFormat_16bextended ((uint16_t)0x0001)\r
-#define I2S_DataFormat_24b ((uint16_t)0x0003)\r
-#define I2S_DataFormat_32b ((uint16_t)0x0005)\r
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \\r
- ((FORMAT) == I2S_DataFormat_16bextended) || \\r
- ((FORMAT) == I2S_DataFormat_24b) || \\r
- ((FORMAT) == I2S_DataFormat_32b))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2S_MCLK_Output \r
- * @{\r
- */\r
-\r
-#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)\r
-#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)\r
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \\r
- ((OUTPUT) == I2S_MCLKOutput_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2S_Audio_Frequency \r
- * @{\r
- */\r
-\r
-#define I2S_AudioFreq_96k ((uint32_t)96000)\r
-#define I2S_AudioFreq_48k ((uint32_t)48000)\r
-#define I2S_AudioFreq_44k ((uint32_t)44100)\r
-#define I2S_AudioFreq_32k ((uint32_t)32000)\r
-#define I2S_AudioFreq_22k ((uint32_t)22050)\r
-#define I2S_AudioFreq_16k ((uint32_t)16000)\r
-#define I2S_AudioFreq_11k ((uint32_t)11025)\r
-#define I2S_AudioFreq_8k ((uint32_t)8000)\r
-#define I2S_AudioFreq_Default ((uint32_t)2)\r
-#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_96k) || \\r
- ((FREQ) == I2S_AudioFreq_48k) || \\r
- ((FREQ) == I2S_AudioFreq_44k) || \\r
- ((FREQ) == I2S_AudioFreq_32k) || \\r
- ((FREQ) == I2S_AudioFreq_22k) || \\r
- ((FREQ) == I2S_AudioFreq_16k) || \\r
- ((FREQ) == I2S_AudioFreq_11k) || \\r
- ((FREQ) == I2S_AudioFreq_8k) || \\r
- ((FREQ) == I2S_AudioFreq_Default))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2S_Clock_Polarity \r
- * @{\r
- */\r
-\r
-#define I2S_CPOL_Low ((uint16_t)0x0000)\r
-#define I2S_CPOL_High ((uint16_t)0x0008)\r
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \\r
- ((CPOL) == I2S_CPOL_High))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_I2S_DMA_transfer_requests \r
- * @{\r
- */\r
-\r
-#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)\r
-#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)\r
-#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_NSS_internal_software_mangement \r
- * @{\r
- */\r
-\r
-#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)\r
-#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)\r
-#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \\r
- ((INTERNAL) == SPI_NSSInternalSoft_Reset))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_CRC_Transmit_Receive \r
- * @{\r
- */\r
-\r
-#define SPI_CRC_Tx ((uint8_t)0x00)\r
-#define SPI_CRC_Rx ((uint8_t)0x01)\r
-#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_direction_transmit_receive \r
- * @{\r
- */\r
-\r
-#define SPI_Direction_Rx ((uint16_t)0xBFFF)\r
-#define SPI_Direction_Tx ((uint16_t)0x4000)\r
-#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \\r
- ((DIRECTION) == SPI_Direction_Tx))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_I2S_interrupts_definition \r
- * @{\r
- */\r
-\r
-#define SPI_I2S_IT_TXE ((uint8_t)0x71)\r
-#define SPI_I2S_IT_RXNE ((uint8_t)0x60)\r
-#define SPI_I2S_IT_ERR ((uint8_t)0x50)\r
-#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \\r
- ((IT) == SPI_I2S_IT_RXNE) || \\r
- ((IT) == SPI_I2S_IT_ERR))\r
-#define SPI_I2S_IT_OVR ((uint8_t)0x56)\r
-#define SPI_IT_MODF ((uint8_t)0x55)\r
-#define SPI_IT_CRCERR ((uint8_t)0x54)\r
-#define I2S_IT_UDR ((uint8_t)0x53)\r
-#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))\r
-#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \\r
- ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \\r
- ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_I2S_flags_definition \r
- * @{\r
- */\r
-\r
-#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)\r
-#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)\r
-#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)\r
-#define I2S_FLAG_UDR ((uint16_t)0x0008)\r
-#define SPI_FLAG_CRCERR ((uint16_t)0x0010)\r
-#define SPI_FLAG_MODF ((uint16_t)0x0020)\r
-#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)\r
-#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)\r
-#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))\r
-#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \\r
- ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \\r
- ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \\r
- ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_CRC_polynomial \r
- * @{\r
- */\r
-\r
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Exported_Functions\r
- * @{\r
- */\r
-\r
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx);\r
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);\r
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);\r
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);\r
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);\r
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);\r
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);\r
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);\r
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);\r
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);\r
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);\r
-void SPI_TransmitCRC(SPI_TypeDef* SPIx);\r
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);\r
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);\r
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);\r
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);\r
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32F10x_SPI_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_tim.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the TIM firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_TIM_H\r
-#define __STM32F10x_TIM_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup TIM\r
- * @{\r
- */ \r
-\r
-/** @defgroup TIM_Exported_Types\r
- * @{\r
- */ \r
-\r
-/** \r
- * @brief TIM Time Base Init structure definition\r
- * @note This sturcture is used with all TIMx except for TIM6 and TIM7. \r
- */\r
-\r
-typedef struct\r
-{\r
- uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.\r
- This parameter can be a number between 0x0000 and 0xFFFF */\r
-\r
- uint16_t TIM_CounterMode; /*!< Specifies the counter mode.\r
- This parameter can be a value of @ref TIM_Counter_Mode */\r
-\r
- uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active\r
- Auto-Reload Register at the next update event.\r
- This parameter must be a number between 0x0000 and 0xFFFF. */ \r
-\r
- uint16_t TIM_ClockDivision; /*!< Specifies the clock division.\r
- This parameter can be a value of @ref TIM_Clock_Division_CKD */\r
-\r
- uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter\r
- reaches zero, an update event is generated and counting restarts\r
- from the RCR value (N).\r
- This means in PWM mode that (N+1) corresponds to:\r
- - the number of PWM periods in edge-aligned mode\r
- - the number of half PWM period in center-aligned mode\r
- This parameter must be a number between 0x00 and 0xFF. \r
- @note This parameter is valid only for TIM1 and TIM8. */\r
-} TIM_TimeBaseInitTypeDef; \r
-\r
-/** \r
- * @brief TIM Output Compare Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint16_t TIM_OCMode; /*!< Specifies the TIM mode.\r
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
-\r
- uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.\r
- This parameter can be a value of @ref TIM_Output_Compare_state */\r
-\r
- uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.\r
- This parameter can be a value of @ref TIM_Output_Compare_N_state\r
- @note This parameter is valid only for TIM1 and TIM8. */\r
-\r
- uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r
- This parameter can be a number between 0x0000 and 0xFFFF */\r
-\r
- uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.\r
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
-\r
- uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.\r
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
- @note This parameter is valid only for TIM1 and TIM8. */\r
-\r
- uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
- @note This parameter is valid only for TIM1 and TIM8. */\r
-\r
- uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
- @note This parameter is valid only for TIM1 and TIM8. */\r
-} TIM_OCInitTypeDef;\r
-\r
-/** \r
- * @brief TIM Input Capture Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
-\r
- uint16_t TIM_Channel; /*!< Specifies the TIM channel.\r
- This parameter can be a value of @ref TIM_Channel */\r
-\r
- uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.\r
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
-\r
- uint16_t TIM_ICSelection; /*!< Specifies the input.\r
- This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
-\r
- uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.\r
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
-\r
- uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.\r
- This parameter can be a number between 0x0 and 0xF */\r
-} TIM_ICInitTypeDef;\r
-\r
-/** \r
- * @brief BDTR structure definition \r
- * @note This sturcture is used only with TIM1 and TIM8. \r
- */\r
-\r
-typedef struct\r
-{\r
-\r
- uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.\r
- This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */\r
-\r
- uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.\r
- This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */\r
-\r
- uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.\r
- This parameter can be a value of @ref Lock_level */ \r
-\r
- uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the\r
- switching-on of the outputs.\r
- This parameter can be a number between 0x00 and 0xFF */\r
-\r
- uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. \r
- This parameter can be a value of @ref Break_Input_enable_disable */\r
-\r
- uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.\r
- This parameter can be a value of @ref Break_Polarity */\r
-\r
- uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. \r
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */\r
-} TIM_BDTRInitTypeDef;\r
-\r
-/** @defgroup TIM_Exported_constants \r
- * @{\r
- */\r
-\r
-#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) || \\r
- ((PERIPH) == TIM5) || \\r
- ((PERIPH) == TIM6) || \\r
- ((PERIPH) == TIM7) || \\r
- ((PERIPH) == TIM8) || \\r
- ((PERIPH) == TIM9) || \\r
- ((PERIPH) == TIM10)|| \\r
- ((PERIPH) == TIM11)|| \\r
- ((PERIPH) == TIM12)|| \\r
- ((PERIPH) == TIM13)|| \\r
- ((PERIPH) == TIM14)|| \\r
- ((PERIPH) == TIM15)|| \\r
- ((PERIPH) == TIM16)|| \\r
- ((PERIPH) == TIM17))\r
-\r
-/* LIST1: TIM 1 and 8 */\r
-#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM8))\r
-\r
-/* LIST2: TIM 1, 8, 15 16 and 17 */\r
-#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM8) || \\r
- ((PERIPH) == TIM15)|| \\r
- ((PERIPH) == TIM16)|| \\r
- ((PERIPH) == TIM17)) \r
-\r
-/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */\r
-#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) || \\r
- ((PERIPH) == TIM5) || \\r
- ((PERIPH) == TIM8)) \r
- \r
-/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */\r
-#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) || \\r
- ((PERIPH) == TIM5) || \\r
- ((PERIPH) == TIM8) || \\r
- ((PERIPH) == TIM15)|| \\r
- ((PERIPH) == TIM16)|| \\r
- ((PERIPH) == TIM17))\r
-\r
-/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */ \r
-#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) || \\r
- ((PERIPH) == TIM5) || \\r
- ((PERIPH) == TIM8) || \\r
- ((PERIPH) == TIM15)) \r
-\r
-/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */\r
-#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) || \\r
- ((PERIPH) == TIM5) || \\r
- ((PERIPH) == TIM8) || \\r
- ((PERIPH) == TIM9) || \\r
- ((PERIPH) == TIM12)|| \\r
- ((PERIPH) == TIM15))\r
-\r
-/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */\r
-#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) || \\r
- ((PERIPH) == TIM5) || \\r
- ((PERIPH) == TIM6) || \\r
- ((PERIPH) == TIM7) || \\r
- ((PERIPH) == TIM8) || \\r
- ((PERIPH) == TIM9) || \\r
- ((PERIPH) == TIM12)|| \\r
- ((PERIPH) == TIM15)) \r
-\r
-/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */ \r
-#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) || \\r
- ((PERIPH) == TIM5) || \\r
- ((PERIPH) == TIM8) || \\r
- ((PERIPH) == TIM9) || \\r
- ((PERIPH) == TIM10)|| \\r
- ((PERIPH) == TIM11)|| \\r
- ((PERIPH) == TIM12)|| \\r
- ((PERIPH) == TIM13)|| \\r
- ((PERIPH) == TIM14)|| \\r
- ((PERIPH) == TIM15)|| \\r
- ((PERIPH) == TIM16)|| \\r
- ((PERIPH) == TIM17))\r
-\r
-/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */\r
-#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) || \\r
- ((PERIPH) == TIM5) || \\r
- ((PERIPH) == TIM6) || \\r
- ((PERIPH) == TIM7) || \\r
- ((PERIPH) == TIM8) || \\r
- ((PERIPH) == TIM15)|| \\r
- ((PERIPH) == TIM16)|| \\r
- ((PERIPH) == TIM17)) \r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Output_Compare_and_PWM_modes \r
- * @{\r
- */\r
-\r
-#define TIM_OCMode_Timing ((uint16_t)0x0000)\r
-#define TIM_OCMode_Active ((uint16_t)0x0010)\r
-#define TIM_OCMode_Inactive ((uint16_t)0x0020)\r
-#define TIM_OCMode_Toggle ((uint16_t)0x0030)\r
-#define TIM_OCMode_PWM1 ((uint16_t)0x0060)\r
-#define TIM_OCMode_PWM2 ((uint16_t)0x0070)\r
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
- ((MODE) == TIM_OCMode_Active) || \\r
- ((MODE) == TIM_OCMode_Inactive) || \\r
- ((MODE) == TIM_OCMode_Toggle)|| \\r
- ((MODE) == TIM_OCMode_PWM1) || \\r
- ((MODE) == TIM_OCMode_PWM2))\r
-#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
- ((MODE) == TIM_OCMode_Active) || \\r
- ((MODE) == TIM_OCMode_Inactive) || \\r
- ((MODE) == TIM_OCMode_Toggle)|| \\r
- ((MODE) == TIM_OCMode_PWM1) || \\r
- ((MODE) == TIM_OCMode_PWM2) || \\r
- ((MODE) == TIM_ForcedAction_Active) || \\r
- ((MODE) == TIM_ForcedAction_InActive))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_One_Pulse_Mode \r
- * @{\r
- */\r
-\r
-#define TIM_OPMode_Single ((uint16_t)0x0008)\r
-#define TIM_OPMode_Repetitive ((uint16_t)0x0000)\r
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \\r
- ((MODE) == TIM_OPMode_Repetitive))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Channel \r
- * @{\r
- */\r
-\r
-#define TIM_Channel_1 ((uint16_t)0x0000)\r
-#define TIM_Channel_2 ((uint16_t)0x0004)\r
-#define TIM_Channel_3 ((uint16_t)0x0008)\r
-#define TIM_Channel_4 ((uint16_t)0x000C)\r
-#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
- ((CHANNEL) == TIM_Channel_2) || \\r
- ((CHANNEL) == TIM_Channel_3) || \\r
- ((CHANNEL) == TIM_Channel_4))\r
-#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
- ((CHANNEL) == TIM_Channel_2))\r
-#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
- ((CHANNEL) == TIM_Channel_2) || \\r
- ((CHANNEL) == TIM_Channel_3))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Clock_Division_CKD \r
- * @{\r
- */\r
-\r
-#define TIM_CKD_DIV1 ((uint16_t)0x0000)\r
-#define TIM_CKD_DIV2 ((uint16_t)0x0100)\r
-#define TIM_CKD_DIV4 ((uint16_t)0x0200)\r
-#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \\r
- ((DIV) == TIM_CKD_DIV2) || \\r
- ((DIV) == TIM_CKD_DIV4))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Counter_Mode \r
- * @{\r
- */\r
-\r
-#define TIM_CounterMode_Up ((uint16_t)0x0000)\r
-#define TIM_CounterMode_Down ((uint16_t)0x0010)\r
-#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)\r
-#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)\r
-#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)\r
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \\r
- ((MODE) == TIM_CounterMode_Down) || \\r
- ((MODE) == TIM_CounterMode_CenterAligned1) || \\r
- ((MODE) == TIM_CounterMode_CenterAligned2) || \\r
- ((MODE) == TIM_CounterMode_CenterAligned3))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Output_Compare_Polarity \r
- * @{\r
- */\r
-\r
-#define TIM_OCPolarity_High ((uint16_t)0x0000)\r
-#define TIM_OCPolarity_Low ((uint16_t)0x0002)\r
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \\r
- ((POLARITY) == TIM_OCPolarity_Low))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Output_Compare_N_Polarity \r
- * @{\r
- */\r
- \r
-#define TIM_OCNPolarity_High ((uint16_t)0x0000)\r
-#define TIM_OCNPolarity_Low ((uint16_t)0x0008)\r
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \\r
- ((POLARITY) == TIM_OCNPolarity_Low))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Output_Compare_state \r
- * @{\r
- */\r
-\r
-#define TIM_OutputState_Disable ((uint16_t)0x0000)\r
-#define TIM_OutputState_Enable ((uint16_t)0x0001)\r
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \\r
- ((STATE) == TIM_OutputState_Enable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Output_Compare_N_state \r
- * @{\r
- */\r
-\r
-#define TIM_OutputNState_Disable ((uint16_t)0x0000)\r
-#define TIM_OutputNState_Enable ((uint16_t)0x0004)\r
-#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \\r
- ((STATE) == TIM_OutputNState_Enable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Capture_Compare_state \r
- * @{\r
- */\r
-\r
-#define TIM_CCx_Enable ((uint16_t)0x0001)\r
-#define TIM_CCx_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \\r
- ((CCX) == TIM_CCx_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Capture_Compare_N_state \r
- * @{\r
- */\r
-\r
-#define TIM_CCxN_Enable ((uint16_t)0x0004)\r
-#define TIM_CCxN_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \\r
- ((CCXN) == TIM_CCxN_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup Break_Input_enable_disable \r
- * @{\r
- */\r
-\r
-#define TIM_Break_Enable ((uint16_t)0x1000)\r
-#define TIM_Break_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \\r
- ((STATE) == TIM_Break_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup Break_Polarity \r
- * @{\r
- */\r
-\r
-#define TIM_BreakPolarity_Low ((uint16_t)0x0000)\r
-#define TIM_BreakPolarity_High ((uint16_t)0x2000)\r
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \\r
- ((POLARITY) == TIM_BreakPolarity_High))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_AOE_Bit_Set_Reset \r
- * @{\r
- */\r
-\r
-#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)\r
-#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \\r
- ((STATE) == TIM_AutomaticOutput_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup Lock_level \r
- * @{\r
- */\r
-\r
-#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)\r
-#define TIM_LOCKLevel_1 ((uint16_t)0x0100)\r
-#define TIM_LOCKLevel_2 ((uint16_t)0x0200)\r
-#define TIM_LOCKLevel_3 ((uint16_t)0x0300)\r
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \\r
- ((LEVEL) == TIM_LOCKLevel_1) || \\r
- ((LEVEL) == TIM_LOCKLevel_2) || \\r
- ((LEVEL) == TIM_LOCKLevel_3))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state \r
- * @{\r
- */\r
-\r
-#define TIM_OSSIState_Enable ((uint16_t)0x0400)\r
-#define TIM_OSSIState_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \\r
- ((STATE) == TIM_OSSIState_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state \r
- * @{\r
- */\r
-\r
-#define TIM_OSSRState_Enable ((uint16_t)0x0800)\r
-#define TIM_OSSRState_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \\r
- ((STATE) == TIM_OSSRState_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Output_Compare_Idle_State \r
- * @{\r
- */\r
-\r
-#define TIM_OCIdleState_Set ((uint16_t)0x0100)\r
-#define TIM_OCIdleState_Reset ((uint16_t)0x0000)\r
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \\r
- ((STATE) == TIM_OCIdleState_Reset))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Output_Compare_N_Idle_State \r
- * @{\r
- */\r
-\r
-#define TIM_OCNIdleState_Set ((uint16_t)0x0200)\r
-#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)\r
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \\r
- ((STATE) == TIM_OCNIdleState_Reset))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Input_Capture_Polarity \r
- * @{\r
- */\r
-\r
-#define TIM_ICPolarity_Rising ((uint16_t)0x0000)\r
-#define TIM_ICPolarity_Falling ((uint16_t)0x0002)\r
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \\r
- ((POLARITY) == TIM_ICPolarity_Falling))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Input_Capture_Selection \r
- * @{\r
- */\r
-\r
-#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \r
- connected to IC1, IC2, IC3 or IC4, respectively */\r
-#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
- connected to IC2, IC1, IC4 or IC3, respectively. */\r
-#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */\r
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \\r
- ((SELECTION) == TIM_ICSelection_IndirectTI) || \\r
- ((SELECTION) == TIM_ICSelection_TRC))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Input_Capture_Prescaler \r
- * @{\r
- */\r
-\r
-#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */\r
-#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */\r
-#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */\r
-#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */\r
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \\r
- ((PRESCALER) == TIM_ICPSC_DIV2) || \\r
- ((PRESCALER) == TIM_ICPSC_DIV4) || \\r
- ((PRESCALER) == TIM_ICPSC_DIV8))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_interrupt_sources \r
- * @{\r
- */\r
-\r
-#define TIM_IT_Update ((uint16_t)0x0001)\r
-#define TIM_IT_CC1 ((uint16_t)0x0002)\r
-#define TIM_IT_CC2 ((uint16_t)0x0004)\r
-#define TIM_IT_CC3 ((uint16_t)0x0008)\r
-#define TIM_IT_CC4 ((uint16_t)0x0010)\r
-#define TIM_IT_COM ((uint16_t)0x0020)\r
-#define TIM_IT_Trigger ((uint16_t)0x0040)\r
-#define TIM_IT_Break ((uint16_t)0x0080)\r
-#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))\r
-\r
-#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \\r
- ((IT) == TIM_IT_CC1) || \\r
- ((IT) == TIM_IT_CC2) || \\r
- ((IT) == TIM_IT_CC3) || \\r
- ((IT) == TIM_IT_CC4) || \\r
- ((IT) == TIM_IT_COM) || \\r
- ((IT) == TIM_IT_Trigger) || \\r
- ((IT) == TIM_IT_Break))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_DMA_Base_address \r
- * @{\r
- */\r
-\r
-#define TIM_DMABase_CR1 ((uint16_t)0x0000)\r
-#define TIM_DMABase_CR2 ((uint16_t)0x0001)\r
-#define TIM_DMABase_SMCR ((uint16_t)0x0002)\r
-#define TIM_DMABase_DIER ((uint16_t)0x0003)\r
-#define TIM_DMABase_SR ((uint16_t)0x0004)\r
-#define TIM_DMABase_EGR ((uint16_t)0x0005)\r
-#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)\r
-#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)\r
-#define TIM_DMABase_CCER ((uint16_t)0x0008)\r
-#define TIM_DMABase_CNT ((uint16_t)0x0009)\r
-#define TIM_DMABase_PSC ((uint16_t)0x000A)\r
-#define TIM_DMABase_ARR ((uint16_t)0x000B)\r
-#define TIM_DMABase_RCR ((uint16_t)0x000C)\r
-#define TIM_DMABase_CCR1 ((uint16_t)0x000D)\r
-#define TIM_DMABase_CCR2 ((uint16_t)0x000E)\r
-#define TIM_DMABase_CCR3 ((uint16_t)0x000F)\r
-#define TIM_DMABase_CCR4 ((uint16_t)0x0010)\r
-#define TIM_DMABase_BDTR ((uint16_t)0x0011)\r
-#define TIM_DMABase_DCR ((uint16_t)0x0012)\r
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \\r
- ((BASE) == TIM_DMABase_CR2) || \\r
- ((BASE) == TIM_DMABase_SMCR) || \\r
- ((BASE) == TIM_DMABase_DIER) || \\r
- ((BASE) == TIM_DMABase_SR) || \\r
- ((BASE) == TIM_DMABase_EGR) || \\r
- ((BASE) == TIM_DMABase_CCMR1) || \\r
- ((BASE) == TIM_DMABase_CCMR2) || \\r
- ((BASE) == TIM_DMABase_CCER) || \\r
- ((BASE) == TIM_DMABase_CNT) || \\r
- ((BASE) == TIM_DMABase_PSC) || \\r
- ((BASE) == TIM_DMABase_ARR) || \\r
- ((BASE) == TIM_DMABase_RCR) || \\r
- ((BASE) == TIM_DMABase_CCR1) || \\r
- ((BASE) == TIM_DMABase_CCR2) || \\r
- ((BASE) == TIM_DMABase_CCR3) || \\r
- ((BASE) == TIM_DMABase_CCR4) || \\r
- ((BASE) == TIM_DMABase_BDTR) || \\r
- ((BASE) == TIM_DMABase_DCR))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_DMA_Burst_Length \r
- * @{\r
- */\r
-\r
-#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000)\r
-#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100)\r
-#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200)\r
-#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300)\r
-#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400)\r
-#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500)\r
-#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600)\r
-#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700)\r
-#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800)\r
-#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900)\r
-#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00)\r
-#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00)\r
-#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00)\r
-#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00)\r
-#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00)\r
-#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00)\r
-#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000)\r
-#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100)\r
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \\r
- ((LENGTH) == TIM_DMABurstLength_2Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_3Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_4Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_5Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_6Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_7Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_8Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_9Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_10Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_11Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_12Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_13Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_14Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_15Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_16Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_17Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_18Bytes))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_DMA_sources \r
- * @{\r
- */\r
-\r
-#define TIM_DMA_Update ((uint16_t)0x0100)\r
-#define TIM_DMA_CC1 ((uint16_t)0x0200)\r
-#define TIM_DMA_CC2 ((uint16_t)0x0400)\r
-#define TIM_DMA_CC3 ((uint16_t)0x0800)\r
-#define TIM_DMA_CC4 ((uint16_t)0x1000)\r
-#define TIM_DMA_COM ((uint16_t)0x2000)\r
-#define TIM_DMA_Trigger ((uint16_t)0x4000)\r
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_External_Trigger_Prescaler \r
- * @{\r
- */\r
-\r
-#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)\r
-#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)\r
-#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)\r
-#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)\r
-#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \\r
- ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \\r
- ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \\r
- ((PRESCALER) == TIM_ExtTRGPSC_DIV8))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Internal_Trigger_Selection \r
- * @{\r
- */\r
-\r
-#define TIM_TS_ITR0 ((uint16_t)0x0000)\r
-#define TIM_TS_ITR1 ((uint16_t)0x0010)\r
-#define TIM_TS_ITR2 ((uint16_t)0x0020)\r
-#define TIM_TS_ITR3 ((uint16_t)0x0030)\r
-#define TIM_TS_TI1F_ED ((uint16_t)0x0040)\r
-#define TIM_TS_TI1FP1 ((uint16_t)0x0050)\r
-#define TIM_TS_TI2FP2 ((uint16_t)0x0060)\r
-#define TIM_TS_ETRF ((uint16_t)0x0070)\r
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
- ((SELECTION) == TIM_TS_ITR1) || \\r
- ((SELECTION) == TIM_TS_ITR2) || \\r
- ((SELECTION) == TIM_TS_ITR3) || \\r
- ((SELECTION) == TIM_TS_TI1F_ED) || \\r
- ((SELECTION) == TIM_TS_TI1FP1) || \\r
- ((SELECTION) == TIM_TS_TI2FP2) || \\r
- ((SELECTION) == TIM_TS_ETRF))\r
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
- ((SELECTION) == TIM_TS_ITR1) || \\r
- ((SELECTION) == TIM_TS_ITR2) || \\r
- ((SELECTION) == TIM_TS_ITR3))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_TIx_External_Clock_Source \r
- * @{\r
- */\r
-\r
-#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)\r
-#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)\r
-#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)\r
-#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \\r
- ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \\r
- ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_External_Trigger_Polarity \r
- * @{\r
- */ \r
-#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)\r
-#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)\r
-#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \\r
- ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Prescaler_Reload_Mode \r
- * @{\r
- */\r
-\r
-#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)\r
-#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)\r
-#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \\r
- ((RELOAD) == TIM_PSCReloadMode_Immediate))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Forced_Action \r
- * @{\r
- */\r
-\r
-#define TIM_ForcedAction_Active ((uint16_t)0x0050)\r
-#define TIM_ForcedAction_InActive ((uint16_t)0x0040)\r
-#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \\r
- ((ACTION) == TIM_ForcedAction_InActive))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Encoder_Mode \r
- * @{\r
- */\r
-\r
-#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)\r
-#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)\r
-#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)\r
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \\r
- ((MODE) == TIM_EncoderMode_TI2) || \\r
- ((MODE) == TIM_EncoderMode_TI12))\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup TIM_Event_Source \r
- * @{\r
- */\r
-\r
-#define TIM_EventSource_Update ((uint16_t)0x0001)\r
-#define TIM_EventSource_CC1 ((uint16_t)0x0002)\r
-#define TIM_EventSource_CC2 ((uint16_t)0x0004)\r
-#define TIM_EventSource_CC3 ((uint16_t)0x0008)\r
-#define TIM_EventSource_CC4 ((uint16_t)0x0010)\r
-#define TIM_EventSource_COM ((uint16_t)0x0020)\r
-#define TIM_EventSource_Trigger ((uint16_t)0x0040)\r
-#define TIM_EventSource_Break ((uint16_t)0x0080)\r
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Update_Source \r
- * @{\r
- */\r
-\r
-#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow\r
- or the setting of UG bit, or an update generation\r
- through the slave mode controller. */\r
-#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */\r
-#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \\r
- ((SOURCE) == TIM_UpdateSource_Regular))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Ouput_Compare_Preload_State \r
- * @{\r
- */\r
-\r
-#define TIM_OCPreload_Enable ((uint16_t)0x0008)\r
-#define TIM_OCPreload_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \\r
- ((STATE) == TIM_OCPreload_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Ouput_Compare_Fast_State \r
- * @{\r
- */\r
-\r
-#define TIM_OCFast_Enable ((uint16_t)0x0004)\r
-#define TIM_OCFast_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \\r
- ((STATE) == TIM_OCFast_Disable))\r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Ouput_Compare_Clear_State \r
- * @{\r
- */\r
-\r
-#define TIM_OCClear_Enable ((uint16_t)0x0080)\r
-#define TIM_OCClear_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \\r
- ((STATE) == TIM_OCClear_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Trigger_Output_Source \r
- * @{\r
- */\r
-\r
-#define TIM_TRGOSource_Reset ((uint16_t)0x0000)\r
-#define TIM_TRGOSource_Enable ((uint16_t)0x0010)\r
-#define TIM_TRGOSource_Update ((uint16_t)0x0020)\r
-#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)\r
-#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)\r
-#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)\r
-#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)\r
-#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)\r
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \\r
- ((SOURCE) == TIM_TRGOSource_Enable) || \\r
- ((SOURCE) == TIM_TRGOSource_Update) || \\r
- ((SOURCE) == TIM_TRGOSource_OC1) || \\r
- ((SOURCE) == TIM_TRGOSource_OC1Ref) || \\r
- ((SOURCE) == TIM_TRGOSource_OC2Ref) || \\r
- ((SOURCE) == TIM_TRGOSource_OC3Ref) || \\r
- ((SOURCE) == TIM_TRGOSource_OC4Ref))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Slave_Mode \r
- * @{\r
- */\r
-\r
-#define TIM_SlaveMode_Reset ((uint16_t)0x0004)\r
-#define TIM_SlaveMode_Gated ((uint16_t)0x0005)\r
-#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)\r
-#define TIM_SlaveMode_External1 ((uint16_t)0x0007)\r
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \\r
- ((MODE) == TIM_SlaveMode_Gated) || \\r
- ((MODE) == TIM_SlaveMode_Trigger) || \\r
- ((MODE) == TIM_SlaveMode_External1))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Master_Slave_Mode \r
- * @{\r
- */\r
-\r
-#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)\r
-#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \\r
- ((STATE) == TIM_MasterSlaveMode_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Flags \r
- * @{\r
- */\r
-\r
-#define TIM_FLAG_Update ((uint16_t)0x0001)\r
-#define TIM_FLAG_CC1 ((uint16_t)0x0002)\r
-#define TIM_FLAG_CC2 ((uint16_t)0x0004)\r
-#define TIM_FLAG_CC3 ((uint16_t)0x0008)\r
-#define TIM_FLAG_CC4 ((uint16_t)0x0010)\r
-#define TIM_FLAG_COM ((uint16_t)0x0020)\r
-#define TIM_FLAG_Trigger ((uint16_t)0x0040)\r
-#define TIM_FLAG_Break ((uint16_t)0x0080)\r
-#define TIM_FLAG_CC1OF ((uint16_t)0x0200)\r
-#define TIM_FLAG_CC2OF ((uint16_t)0x0400)\r
-#define TIM_FLAG_CC3OF ((uint16_t)0x0800)\r
-#define TIM_FLAG_CC4OF ((uint16_t)0x1000)\r
-#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \\r
- ((FLAG) == TIM_FLAG_CC1) || \\r
- ((FLAG) == TIM_FLAG_CC2) || \\r
- ((FLAG) == TIM_FLAG_CC3) || \\r
- ((FLAG) == TIM_FLAG_CC4) || \\r
- ((FLAG) == TIM_FLAG_COM) || \\r
- ((FLAG) == TIM_FLAG_Trigger) || \\r
- ((FLAG) == TIM_FLAG_Break) || \\r
- ((FLAG) == TIM_FLAG_CC1OF) || \\r
- ((FLAG) == TIM_FLAG_CC2OF) || \\r
- ((FLAG) == TIM_FLAG_CC3OF) || \\r
- ((FLAG) == TIM_FLAG_CC4OF))\r
- \r
- \r
-#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Input_Capture_Filer_Value \r
- * @{\r
- */\r
-\r
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_External_Trigger_Filter \r
- * @{\r
- */\r
-\r
-#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Exported_Functions\r
- * @{\r
- */\r
-\r
-void TIM_DeInit(TIM_TypeDef* TIMx);\r
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);\r
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);\r
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);\r
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);\r
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);\r
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);\r
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);\r
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);\r
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx);\r
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
- uint16_t TIM_ICPolarity, uint16_t ICFilter);\r
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
- uint16_t ExtTRGFilter);\r
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);\r
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
- uint16_t ExtTRGFilter);\r
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);\r
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);\r
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);\r
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);\r
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);\r
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);\r
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);\r
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);\r
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);\r
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);\r
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);\r
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);\r
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);\r
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);\r
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);\r
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);\r
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);\r
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);\r
-uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);\r
-uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);\r
-uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);\r
-uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);\r
-uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);\r
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);\r
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32F10x_TIM_H */\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_usart.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the USART \r
- * firmware library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_USART_H\r
-#define __STM32F10x_USART_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup USART\r
- * @{\r
- */ \r
-\r
-/** @defgroup USART_Exported_Types\r
- * @{\r
- */ \r
-\r
-/** \r
- * @brief USART Init Structure definition \r
- */ \r
- \r
-typedef struct\r
-{\r
- uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.\r
- The baud rate is computed using the following formula:\r
- - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))\r
- - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */\r
-\r
- uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
- This parameter can be a value of @ref USART_Word_Length */\r
-\r
- uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.\r
- This parameter can be a value of @ref USART_Stop_Bits */\r
-\r
- uint16_t USART_Parity; /*!< Specifies the parity mode.\r
- This parameter can be a value of @ref USART_Parity\r
- @note When parity is enabled, the computed parity is inserted\r
- at the MSB position of the transmitted data (9th bit when\r
- the word length is set to 9 data bits; 8th bit when the\r
- word length is set to 8 data bits). */\r
- \r
- uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.\r
- This parameter can be a value of @ref USART_Mode */\r
-\r
- uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled\r
- or disabled.\r
- This parameter can be a value of @ref USART_Hardware_Flow_Control */\r
-} USART_InitTypeDef;\r
-\r
-/** \r
- * @brief USART Clock Init Structure definition \r
- */ \r
- \r
-typedef struct\r
-{\r
-\r
- uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.\r
- This parameter can be a value of @ref USART_Clock */\r
-\r
- uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.\r
- This parameter can be a value of @ref USART_Clock_Polarity */\r
-\r
- uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.\r
- This parameter can be a value of @ref USART_Clock_Phase */\r
-\r
- uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted\r
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r
- This parameter can be a value of @ref USART_Last_Bit */\r
-} USART_ClockInitTypeDef;\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Exported_Constants\r
- * @{\r
- */ \r
- \r
-#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
- ((PERIPH) == USART2) || \\r
- ((PERIPH) == USART3) || \\r
- ((PERIPH) == UART4) || \\r
- ((PERIPH) == UART5))\r
-\r
-#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
- ((PERIPH) == USART2) || \\r
- ((PERIPH) == USART3))\r
-\r
-#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
- ((PERIPH) == USART2) || \\r
- ((PERIPH) == USART3) || \\r
- ((PERIPH) == UART4))\r
-/** @defgroup USART_Word_Length \r
- * @{\r
- */ \r
- \r
-#define USART_WordLength_8b ((uint16_t)0x0000)\r
-#define USART_WordLength_9b ((uint16_t)0x1000)\r
- \r
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \\r
- ((LENGTH) == USART_WordLength_9b))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Stop_Bits \r
- * @{\r
- */ \r
- \r
-#define USART_StopBits_1 ((uint16_t)0x0000)\r
-#define USART_StopBits_0_5 ((uint16_t)0x1000)\r
-#define USART_StopBits_2 ((uint16_t)0x2000)\r
-#define USART_StopBits_1_5 ((uint16_t)0x3000)\r
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \\r
- ((STOPBITS) == USART_StopBits_0_5) || \\r
- ((STOPBITS) == USART_StopBits_2) || \\r
- ((STOPBITS) == USART_StopBits_1_5))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Parity \r
- * @{\r
- */ \r
- \r
-#define USART_Parity_No ((uint16_t)0x0000)\r
-#define USART_Parity_Even ((uint16_t)0x0400)\r
-#define USART_Parity_Odd ((uint16_t)0x0600) \r
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \\r
- ((PARITY) == USART_Parity_Even) || \\r
- ((PARITY) == USART_Parity_Odd))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Mode \r
- * @{\r
- */ \r
- \r
-#define USART_Mode_Rx ((uint16_t)0x0004)\r
-#define USART_Mode_Tx ((uint16_t)0x0008)\r
-#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Hardware_Flow_Control \r
- * @{\r
- */ \r
-#define USART_HardwareFlowControl_None ((uint16_t)0x0000)\r
-#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)\r
-#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)\r
-#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)\r
-#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\\r
- (((CONTROL) == USART_HardwareFlowControl_None) || \\r
- ((CONTROL) == USART_HardwareFlowControl_RTS) || \\r
- ((CONTROL) == USART_HardwareFlowControl_CTS) || \\r
- ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Clock \r
- * @{\r
- */ \r
-#define USART_Clock_Disable ((uint16_t)0x0000)\r
-#define USART_Clock_Enable ((uint16_t)0x0800)\r
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \\r
- ((CLOCK) == USART_Clock_Enable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Clock_Polarity \r
- * @{\r
- */\r
- \r
-#define USART_CPOL_Low ((uint16_t)0x0000)\r
-#define USART_CPOL_High ((uint16_t)0x0400)\r
-#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Clock_Phase\r
- * @{\r
- */\r
-\r
-#define USART_CPHA_1Edge ((uint16_t)0x0000)\r
-#define USART_CPHA_2Edge ((uint16_t)0x0200)\r
-#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Last_Bit\r
- * @{\r
- */\r
-\r
-#define USART_LastBit_Disable ((uint16_t)0x0000)\r
-#define USART_LastBit_Enable ((uint16_t)0x0100)\r
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \\r
- ((LASTBIT) == USART_LastBit_Enable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Interrupt_definition \r
- * @{\r
- */\r
- \r
-#define USART_IT_PE ((uint16_t)0x0028)\r
-#define USART_IT_TXE ((uint16_t)0x0727)\r
-#define USART_IT_TC ((uint16_t)0x0626)\r
-#define USART_IT_RXNE ((uint16_t)0x0525)\r
-#define USART_IT_IDLE ((uint16_t)0x0424)\r
-#define USART_IT_LBD ((uint16_t)0x0846)\r
-#define USART_IT_CTS ((uint16_t)0x096A)\r
-#define USART_IT_ERR ((uint16_t)0x0060)\r
-#define USART_IT_ORE ((uint16_t)0x0360)\r
-#define USART_IT_NE ((uint16_t)0x0260)\r
-#define USART_IT_FE ((uint16_t)0x0160)\r
-#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))\r
-#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \\r
- ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))\r
-#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
- ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_DMA_Requests \r
- * @{\r
- */\r
-\r
-#define USART_DMAReq_Tx ((uint16_t)0x0080)\r
-#define USART_DMAReq_Rx ((uint16_t)0x0040)\r
-#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_WakeUp_methods\r
- * @{\r
- */\r
-\r
-#define USART_WakeUp_IdleLine ((uint16_t)0x0000)\r
-#define USART_WakeUp_AddressMark ((uint16_t)0x0800)\r
-#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \\r
- ((WAKEUP) == USART_WakeUp_AddressMark))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_LIN_Break_Detection_Length \r
- * @{\r
- */\r
- \r
-#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)\r
-#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)\r
-#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \\r
- (((LENGTH) == USART_LINBreakDetectLength_10b) || \\r
- ((LENGTH) == USART_LINBreakDetectLength_11b))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_IrDA_Low_Power \r
- * @{\r
- */\r
-\r
-#define USART_IrDAMode_LowPower ((uint16_t)0x0004)\r
-#define USART_IrDAMode_Normal ((uint16_t)0x0000)\r
-#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \\r
- ((MODE) == USART_IrDAMode_Normal))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Flags \r
- * @{\r
- */\r
-\r
-#define USART_FLAG_CTS ((uint16_t)0x0200)\r
-#define USART_FLAG_LBD ((uint16_t)0x0100)\r
-#define USART_FLAG_TXE ((uint16_t)0x0080)\r
-#define USART_FLAG_TC ((uint16_t)0x0040)\r
-#define USART_FLAG_RXNE ((uint16_t)0x0020)\r
-#define USART_FLAG_IDLE ((uint16_t)0x0010)\r
-#define USART_FLAG_ORE ((uint16_t)0x0008)\r
-#define USART_FLAG_NE ((uint16_t)0x0004)\r
-#define USART_FLAG_FE ((uint16_t)0x0002)\r
-#define USART_FLAG_PE ((uint16_t)0x0001)\r
-#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \\r
- ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \\r
- ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \\r
- ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \\r
- ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))\r
- \r
-#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
-#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\\r
- ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \\r
- || ((USART_FLAG) != USART_FLAG_CTS)) \r
-#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))\r
-#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)\r
-#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Exported_Macros\r
- * @{\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Exported_Functions\r
- * @{\r
- */\r
-\r
-void USART_DeInit(USART_TypeDef* USARTx);\r
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);\r
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct);\r
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);\r
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);\r
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);\r
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);\r
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);\r
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);\r
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);\r
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);\r
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx);\r
-void USART_SendBreak(USART_TypeDef* USARTx);\r
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);\r
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);\r
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);\r
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);\r
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_USART_H */\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_wwdg.h\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file contains all the functions prototypes for the WWDG firmware\r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_WWDG_H\r
-#define __STM32F10x_WWDG_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup WWDG\r
- * @{\r
- */ \r
-\r
-/** @defgroup WWDG_Exported_Types\r
- * @{\r
- */ \r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup WWDG_Exported_Constants\r
- * @{\r
- */ \r
- \r
-/** @defgroup WWDG_Prescaler \r
- * @{\r
- */ \r
- \r
-#define WWDG_Prescaler_1 ((uint32_t)0x00000000)\r
-#define WWDG_Prescaler_2 ((uint32_t)0x00000080)\r
-#define WWDG_Prescaler_4 ((uint32_t)0x00000100)\r
-#define WWDG_Prescaler_8 ((uint32_t)0x00000180)\r
-#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \\r
- ((PRESCALER) == WWDG_Prescaler_2) || \\r
- ((PRESCALER) == WWDG_Prescaler_4) || \\r
- ((PRESCALER) == WWDG_Prescaler_8))\r
-#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)\r
-#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup WWDG_Exported_Macros\r
- * @{\r
- */ \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup WWDG_Exported_Functions\r
- * @{\r
- */ \r
- \r
-void WWDG_DeInit(void);\r
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);\r
-void WWDG_SetWindowValue(uint8_t WindowValue);\r
-void WWDG_EnableIT(void);\r
-void WWDG_SetCounter(uint8_t Counter);\r
-void WWDG_Enable(uint8_t Counter);\r
-FlagStatus WWDG_GetFlagStatus(void);\r
-void WWDG_ClearFlag(void);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_WWDG_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file misc.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the miscellaneous\r
- * firmware library functions (add-on to CMSIS functions).\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __MISC_H\r
-#define __MISC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup MISC\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief NVIC Init Structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.\r
- This parameter can be a value of @ref IRQn_Type \r
- (For the complete STM32 Devices IRQ Channels list, please\r
- refer to stm32l1xx.h file) */\r
-\r
- uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel\r
- specified in NVIC_IRQChannel. This parameter can be a value\r
- between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
-\r
- uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified\r
- in NVIC_IRQChannel. This parameter can be a value\r
- between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
-\r
- FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel\r
- will be enabled or disabled. \r
- This parameter can be set either to ENABLE or DISABLE */ \r
-} NVIC_InitTypeDef;\r
-\r
-/** \r
- *\r
-@verbatim \r
- The table below gives the allowed values of the pre-emption priority and subpriority according\r
- to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function\r
- ============================================================================================================================\r
- NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description\r
- ============================================================================================================================\r
- NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority\r
- | | | 4 bits for subpriority\r
- ----------------------------------------------------------------------------------------------------------------------------\r
- NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority\r
- | | | 3 bits for subpriority\r
- ---------------------------------------------------------------------------------------------------------------------------- \r
- NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority\r
- | | | 2 bits for subpriority\r
- ---------------------------------------------------------------------------------------------------------------------------- \r
- NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority\r
- | | | 1 bits for subpriority\r
- ---------------------------------------------------------------------------------------------------------------------------- \r
- NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority\r
- | | | 0 bits for subpriority \r
- ============================================================================================================================\r
-@endverbatim\r
-*/\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup MISC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup Vector_Table_Base \r
- * @{\r
- */\r
-\r
-#define NVIC_VectTab_RAM ((uint32_t)0x20000000)\r
-#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)\r
-#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \\r
- ((VECTTAB) == NVIC_VectTab_FLASH))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup System_Low_Power \r
- * @{\r
- */\r
-\r
-#define NVIC_LP_SEVONPEND ((uint8_t)0x10)\r
-#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)\r
-#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)\r
-#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \\r
- ((LP) == NVIC_LP_SLEEPDEEP) || \\r
- ((LP) == NVIC_LP_SLEEPONEXIT))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Preemption_Priority_Group \r
- * @{\r
- */\r
-\r
-#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority\r
- 4 bits for subpriority */\r
-#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority\r
- 3 bits for subpriority */\r
-#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority\r
- 2 bits for subpriority */\r
-#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority\r
- 1 bits for subpriority */\r
-#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority\r
- 0 bits for subpriority */\r
-\r
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \\r
- ((GROUP) == NVIC_PriorityGroup_1) || \\r
- ((GROUP) == NVIC_PriorityGroup_2) || \\r
- ((GROUP) == NVIC_PriorityGroup_3) || \\r
- ((GROUP) == NVIC_PriorityGroup_4))\r
-\r
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
-\r
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
-\r
-#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0001FFFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SysTick_clock_source \r
- * @{\r
- */\r
-\r
-#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)\r
-#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)\r
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \\r
- ((SOURCE) == SysTick_CLKSource_HCLK_Div8))\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */ \r
-\r
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);\r
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);\r
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);\r
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);\r
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __MISC_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_adc.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the ADC firmware \r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_ADC_H\r
-#define __STM32L1xx_ADC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup ADC\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief ADC Init structure definition \r
- */\r
- \r
-typedef struct\r
-{\r
- uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion.\r
- This parameter can be a value of @ref ADC_Resolution */\r
- \r
- FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in\r
- Scan (multichannel) or Single (one channel) mode.\r
- This parameter can be set to ENABLE or DISABLE */\r
- \r
- FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in\r
- Continuous or Single mode.\r
- This parameter can be set to ENABLE or DISABLE. */\r
- \r
- uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the\r
- trigger of a regular group. This parameter can be a value\r
- of @ref ADC_external_trigger_edge_for_regular_channels_conversion */\r
- \r
- uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog\r
- to digital conversion of regular channels. This parameter\r
- can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */\r
- \r
- uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.\r
- This parameter can be a value of @ref ADC_data_align */\r
- \r
- uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done\r
- using the sequencer for regular channel group.\r
- This parameter must range from 1 to 27. */\r
-}ADC_InitTypeDef;\r
-\r
-typedef struct \r
-{ \r
- uint32_t ADC_Prescaler; /*!< Selects the ADC prescaler.\r
- This parameter can be a value \r
- of @ref ADC_Prescaler */\r
-}ADC_CommonInitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup ADC_Exported_Constants\r
- * @{\r
- */ \r
-#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)\r
-#define IS_ADC_DMA_PERIPH(PERIPH) ((PERIPH) == ADC1)\r
-\r
-/** @defgroup ADC_Power_down_during_Idle_and_or_Delay_phase \r
- * @{\r
- */ \r
-#define ADC_PowerDown_Delay ((uint32_t)0x00010000)\r
-#define ADC_PowerDown_Idle ((uint32_t)0x00020000)\r
-#define ADC_PowerDown_Idle_Delay ((uint32_t)0x00030000)\r
-\r
-#define IS_ADC_POWER_DOWN(DWON) (((DWON) == ADC_PowerDown_Delay) || \\r
- ((DWON) == ADC_PowerDown_Idle) || \\r
- ((DWON) == ADC_PowerDown_Idle_Delay))\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup ADC_Prescaler \r
- * @{\r
- */ \r
-#define ADC_Prescaler_Div1 ((uint32_t)0x00000000)\r
-#define ADC_Prescaler_Div2 ((uint32_t)0x00010000)\r
-#define ADC_Prescaler_Div4 ((uint32_t)0x00020000)\r
-\r
-#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div1) || \\r
- ((PRESCALER) == ADC_Prescaler_Div2) || \\r
- ((PRESCALER) == ADC_Prescaler_Div4))\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-\r
-/** @defgroup ADC_resolution \r
- * @{\r
- */ \r
-#define ADC_Resolution_12b ((uint32_t)0x00000000)\r
-#define ADC_Resolution_10b ((uint32_t)0x01000000)\r
-#define ADC_Resolution_8b ((uint32_t)0x02000000)\r
-#define ADC_Resolution_6b ((uint32_t)0x03000000)\r
-\r
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \\r
- ((RESOLUTION) == ADC_Resolution_10b) || \\r
- ((RESOLUTION) == ADC_Resolution_8b) || \\r
- ((RESOLUTION) == ADC_Resolution_6b))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion \r
- * @{\r
- */ \r
-#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)\r
-#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)\r
-#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)\r
-#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)\r
-\r
-#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \\r
- ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \\r
- ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \\r
- ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion\r
- * @{\r
- */ \r
-\r
-/* TIM2 */\r
-#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x02000000)\r
-#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)\r
-#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)\r
-\r
-/* TIM3 */\r
-#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)\r
-#define ADC_ExternalTrigConv_T3_CC3 ((uint32_t)0x08000000)\r
-#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x04000000)\r
-\r
-/* TIM4 */\r
-#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x05000000)\r
-#define ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x09000000)\r
-\r
-/* TIM6 */\r
-#define ADC_ExternalTrigConv_T6_TRGO ((uint32_t)0x0A000000)\r
-\r
-/* TIM9 */\r
-#define ADC_ExternalTrigConv_T9_CC2 ((uint32_t)0x00000000)\r
-#define ADC_ExternalTrigConv_T9_TRGO ((uint32_t)0x01000000)\r
-\r
-/* EXTI */\r
-#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)\r
-\r
-#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T9_CC2) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T9_TRGO) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T3_CC3) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T6_TRGO) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_data_align \r
- * @{\r
- */ \r
- \r
-#define ADC_DataAlign_Right ((uint32_t)0x00000000)\r
-#define ADC_DataAlign_Left ((uint32_t)0x00000800)\r
-\r
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \\r
- ((ALIGN) == ADC_DataAlign_Left))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_channels \r
- * @{\r
- */ \r
- \r
-#define ADC_Channel_0 ((uint8_t)0x00)\r
-#define ADC_Channel_1 ((uint8_t)0x01)\r
-#define ADC_Channel_2 ((uint8_t)0x02)\r
-#define ADC_Channel_3 ((uint8_t)0x03)\r
-#define ADC_Channel_4 ((uint8_t)0x04)\r
-#define ADC_Channel_5 ((uint8_t)0x05)\r
-#define ADC_Channel_6 ((uint8_t)0x06)\r
-#define ADC_Channel_7 ((uint8_t)0x07)\r
-#define ADC_Channel_8 ((uint8_t)0x08)\r
-#define ADC_Channel_9 ((uint8_t)0x09)\r
-#define ADC_Channel_10 ((uint8_t)0x0A)\r
-#define ADC_Channel_11 ((uint8_t)0x0B)\r
-#define ADC_Channel_12 ((uint8_t)0x0C)\r
-#define ADC_Channel_13 ((uint8_t)0x0D)\r
-#define ADC_Channel_14 ((uint8_t)0x0E)\r
-#define ADC_Channel_15 ((uint8_t)0x0F)\r
-#define ADC_Channel_16 ((uint8_t)0x10)\r
-#define ADC_Channel_17 ((uint8_t)0x11)\r
-#define ADC_Channel_18 ((uint8_t)0x12)\r
-#define ADC_Channel_19 ((uint8_t)0x13)\r
-#define ADC_Channel_20 ((uint8_t)0x14)\r
-#define ADC_Channel_21 ((uint8_t)0x15)\r
-#define ADC_Channel_22 ((uint8_t)0x16)\r
-#define ADC_Channel_23 ((uint8_t)0x17)\r
-#define ADC_Channel_24 ((uint8_t)0x18)\r
-#define ADC_Channel_25 ((uint8_t)0x19)\r
-\r
-#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)\r
-#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)\r
-\r
-\r
-\r
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \\r
- ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \\r
- ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \\r
- ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \\r
- ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \\r
- ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \\r
- ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \\r
- ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \\r
- ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17) || \\r
- ((CHANNEL) == ADC_Channel_18) || ((CHANNEL) == ADC_Channel_19) || \\r
- ((CHANNEL) == ADC_Channel_20) || ((CHANNEL) == ADC_Channel_21) || \\r
- ((CHANNEL) == ADC_Channel_22) || ((CHANNEL) == ADC_Channel_23) || \\r
- ((CHANNEL) == ADC_Channel_24) || ((CHANNEL) == ADC_Channel_25) )\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_sampling_times \r
- * @{\r
- */ \r
-\r
-#define ADC_SampleTime_4Cycles ((uint8_t)0x00)\r
-#define ADC_SampleTime_9Cycles ((uint8_t)0x01)\r
-#define ADC_SampleTime_16Cycles ((uint8_t)0x02)\r
-#define ADC_SampleTime_24Cycles ((uint8_t)0x03)\r
-#define ADC_SampleTime_48Cycles ((uint8_t)0x04)\r
-#define ADC_SampleTime_96Cycles ((uint8_t)0x05)\r
-#define ADC_SampleTime_192Cycles ((uint8_t)0x06)\r
-#define ADC_SampleTime_384Cycles ((uint8_t)0x07)\r
-\r
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_4Cycles) || \\r
- ((TIME) == ADC_SampleTime_9Cycles) || \\r
- ((TIME) == ADC_SampleTime_16Cycles) || \\r
- ((TIME) == ADC_SampleTime_24Cycles) || \\r
- ((TIME) == ADC_SampleTime_48Cycles) || \\r
- ((TIME) == ADC_SampleTime_96Cycles) || \\r
- ((TIME) == ADC_SampleTime_192Cycles) || \\r
- ((TIME) == ADC_SampleTime_384Cycles))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_Delay_length \r
- * @{\r
- */ \r
-\r
-#define ADC_DelayLength_None ((uint8_t)0x00)\r
-#define ADC_DelayLength_Freeze ((uint8_t)0x10)\r
-#define ADC_DelayLength_7Cycles ((uint8_t)0x20)\r
-#define ADC_DelayLength_15Cycles ((uint8_t)0x30)\r
-#define ADC_DelayLength_31Cycles ((uint8_t)0x40)\r
-#define ADC_DelayLength_63Cycles ((uint8_t)0x50)\r
-#define ADC_DelayLength_127Cycles ((uint8_t)0x60)\r
-#define ADC_DelayLength_255Cycles ((uint8_t)0x70)\r
-\r
-#define IS_ADC_DELAY_LENGTH(LENGTH) (((LENGTH) == ADC_DelayLength_None) || \\r
- ((LENGTH) == ADC_DelayLength_Freeze) || \\r
- ((LENGTH) == ADC_DelayLength_7Cycles) || \\r
- ((LENGTH) == ADC_DelayLength_15Cycles) || \\r
- ((LENGTH) == ADC_DelayLength_31Cycles) || \\r
- ((LENGTH) == ADC_DelayLength_63Cycles) || \\r
- ((LENGTH) == ADC_DelayLength_127Cycles) || \\r
- ((LENGTH) == ADC_DelayLength_255Cycles))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion \r
- * @{\r
- */ \r
-#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)\r
-#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)\r
-#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)\r
-#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)\r
-\r
-#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \\r
- ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \\r
- ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \\r
- ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion \r
- * @{\r
- */ \r
-\r
-\r
-/* TIM2 */\r
-#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00020000)\r
-#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00030000)\r
-\r
-/* TIM3 */\r
-#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00040000)\r
-\r
-/* TIM4 */\r
-#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00050000)\r
-#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)\r
-#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)\r
-#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)\r
-\r
-/* TIM7 */\r
-#define ADC_ExternalTrigInjecConv_T7_TRGO ((uint32_t)0x000A0000)\r
-\r
-/* TIM9 */\r
-#define ADC_ExternalTrigInjecConv_T9_CC1 ((uint32_t)0x00000000)\r
-#define ADC_ExternalTrigInjecConv_T9_TRGO ((uint32_t)0x00010000)\r
-\r
-/* TIM10 */\r
-#define ADC_ExternalTrigInjecConv_T10_CC1 ((uint32_t)0x00090000)\r
-\r
-/* EXTI */\r
-#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)\r
-\r
-#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T9_CC1) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T9_TRGO) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T10_CC1) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T7_TRGO) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_injected_channel_selection \r
- * @{\r
- */ \r
-#define ADC_InjectedChannel_1 ((uint8_t)0x18)\r
-#define ADC_InjectedChannel_2 ((uint8_t)0x1C)\r
-#define ADC_InjectedChannel_3 ((uint8_t)0x20)\r
-#define ADC_InjectedChannel_4 ((uint8_t)0x24)\r
-\r
-#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \\r
- ((CHANNEL) == ADC_InjectedChannel_2) || \\r
- ((CHANNEL) == ADC_InjectedChannel_3) || \\r
- ((CHANNEL) == ADC_InjectedChannel_4))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_analog_watchdog_selection \r
- * @{\r
- */ \r
- \r
-#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)\r
-#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)\r
-#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) \r
-#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)\r
-#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)\r
-#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)\r
-#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)\r
-\r
-#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_None))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_interrupts_definition \r
- * @{\r
- */ \r
- \r
-#define ADC_IT_AWD ((uint16_t)0x0106) \r
-#define ADC_IT_EOC ((uint16_t)0x0205) \r
-#define ADC_IT_JEOC ((uint16_t)0x0407) \r
-#define ADC_IT_OVR ((uint16_t)0x201A) \r
- \r
-#define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_EOC) || \\r
- ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_flags_definition \r
- * @{\r
- */ \r
- \r
-#define ADC_FLAG_AWD ((uint16_t)0x0001)\r
-#define ADC_FLAG_EOC ((uint16_t)0x0002)\r
-#define ADC_FLAG_JEOC ((uint16_t)0x0004)\r
-#define ADC_FLAG_JSTRT ((uint16_t)0x0008)\r
-#define ADC_FLAG_STRT ((uint16_t)0x0010)\r
-#define ADC_FLAG_OVR ((uint16_t)0x0020)\r
-#define ADC_FLAG_ADONS ((uint16_t)0x0040)\r
-#define ADC_FLAG_RCNR ((uint16_t)0x0100)\r
-#define ADC_FLAG_JCNR ((uint16_t)0x0200) \r
- \r
-#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFC0) == 0x00) && ((FLAG) != 0x00))\r
- \r
-#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \\r
- ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \\r
- ((FLAG) == ADC_FLAG_STRT) || ((FLAG)== ADC_FLAG_OVR) || \\r
- ((FLAG) == ADC_FLAG_ADONS) || ((FLAG)== ADC_FLAG_RCNR) || \\r
- ((FLAG) == ADC_FLAG_JCNR))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_thresholds \r
- * @{\r
- */ \r
- \r
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_injected_offset \r
- * @{\r
- */\r
- \r
-#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_injected_length \r
- * @{\r
- */\r
- \r
-#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_injected_rank \r
- * @{\r
- */ \r
- \r
-#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_regular_length \r
- * @{\r
- */\r
- \r
-#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 27))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_regular_rank \r
- * @{\r
- */ \r
- \r
-#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x1B))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_regular_discontinuous_mode_number \r
- * @{\r
- */\r
- \r
-#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */ \r
-\r
-/* Function used to set the ADC configuration to the default reset state *****/ \r
-void ADC_DeInit(ADC_TypeDef* ADCx); \r
-\r
-/* Initialization and Configuration functions *********************************/ \r
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);\r
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);\r
-void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);\r
-void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);\r
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-\r
-/* Power saving functions *****************************************************/\r
-void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState);\r
-void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength);\r
-\r
-/* Analog Watchdog configuration functions ************************************/\r
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);\r
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);\r
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);\r
-\r
-/* Temperature Sensor & Vrefint (Voltage Reference internal) management function */\r
-void ADC_TempSensorVrefintCmd(FunctionalState NewState);\r
-\r
-/* Regular Channels Configuration functions ***********************************/\r
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
-void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);\r
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);\r
-void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);\r
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);\r
-\r
-/* Regular Channels DMA Configuration functions *******************************/\r
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-\r
-/* Injected channels Configuration functions **********************************/\r
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);\r
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);\r
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);\r
-void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);\r
-void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);\r
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);\r
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);\r
-\r
-/* Interrupts and flags management functions **********************************/\r
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);\r
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);\r
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);\r
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_ADC_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_comp.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the COMP firmware \r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_COMP_H\r
-#define __STM32L1xx_COMP_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup COMP\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief COMP Init structure definition \r
- */\r
- \r
-typedef struct\r
-{\r
- uint32_t COMP_Speed; /*!< Defines the speed of comparator 2.\r
- This parameter can be a value of @ref COMP_Speed */\r
- uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator 2.\r
- This parameter can be a value of @ref COMP_InvertingInput */\r
- uint32_t COMP_OutputSelect; /*!< Selects the output redirection of the comparator 2.\r
- This parameter can be a value of @ref COMP_OutputSelect */\r
- \r
-}COMP_InitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
- \r
-/** @defgroup COMP_Exported_Constants\r
- * @{\r
- */ \r
-\r
-#define COMP_OutputLevel_High ((uint32_t)0x00000001)\r
-#define COMP_OutputLevel_Low ((uint32_t)0x00000000)\r
-\r
-/** @defgroup COMP_Selection\r
- * @{\r
- */\r
-\r
-#define COMP_Selection_COMP1 ((uint32_t)0x00000001)\r
-#define COMP_Selection_COMP2 ((uint32_t)0x00000002)\r
-\r
-#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \\r
- ((PERIPH) == COMP_Selection_COMP2))\r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup COMP_InvertingInput\r
- * @{\r
- */\r
-\r
-#define COMP_InvertingInput_None ((uint32_t)0x00000000) /* COMP2 is disabled when this parameter is selected */\r
-#define COMP_InvertingInput_IO ((uint32_t)0x00040000)\r
-#define COMP_InvertingInput_VREFINT ((uint32_t)0x00080000)\r
-#define COMP_InvertingInput_3_4VREFINT ((uint32_t)0x000C0000)\r
-#define COMP_InvertingInput_1_2VREFINT ((uint32_t)0x00100000)\r
-#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00140000)\r
-#define COMP_InvertingInput_DAC1 ((uint32_t)0x00180000)\r
-#define COMP_InvertingInput_DAC2 ((uint32_t)0x001C0000)\r
-\r
-#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_None) || \\r
- ((INPUT) == COMP_InvertingInput_IO) || \\r
- ((INPUT) == COMP_InvertingInput_VREFINT) || \\r
- ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \\r
- ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \\r
- ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \\r
- ((INPUT) == COMP_InvertingInput_DAC1) || \\r
- ((INPUT) == COMP_InvertingInput_DAC2))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup COMP_OutputSelect\r
- * @{\r
- */\r
-\r
-#define COMP_OutputSelect_TIM2IC4 ((uint32_t)0x00000000)\r
-#define COMP_OutputSelect_TIM2OCREFCLR ((uint32_t)0x00200000)\r
-#define COMP_OutputSelect_TIM3IC4 ((uint32_t)0x00400000)\r
-#define COMP_OutputSelect_TIM3OCREFCLR ((uint32_t)0x00600000)\r
-#define COMP_OutputSelect_TIM4IC4 ((uint32_t)0x00800000)\r
-#define COMP_OutputSelect_TIM4OCREFCLR ((uint32_t)0x00A00000)\r
-#define COMP_OutputSelect_TIM10IC1 ((uint32_t)0x00C00000)\r
-#define COMP_OutputSelect_None ((uint32_t)0x00E00000)\r
-\r
-#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OutputSelect_TIM2IC4) || \\r
- ((OUTPUT) == COMP_OutputSelect_TIM2OCREFCLR) || \\r
- ((OUTPUT) == COMP_OutputSelect_TIM3IC4) || \\r
- ((OUTPUT) == COMP_OutputSelect_TIM3OCREFCLR) || \\r
- ((OUTPUT) == COMP_OutputSelect_TIM4IC4) || \\r
- ((OUTPUT) == COMP_OutputSelect_TIM4OCREFCLR) || \\r
- ((OUTPUT) == COMP_OutputSelect_TIM10IC1) || \\r
- ((OUTPUT) == COMP_OutputSelect_None))\r
-/**\r
- * @}\r
- */ \r
- \r
-/** @defgroup COMP_Speed\r
- * @{\r
- */\r
-\r
-#define COMP_Speed_Slow ((uint32_t)0x00000000)\r
-#define COMP_Speed_Fast ((uint32_t)0x00001000)\r
-\r
-#define IS_COMP_SPEED(SPEED) (((SPEED) == COMP_Speed_Slow) || \\r
- ((SPEED) == COMP_Speed_Fast))\r
-/**\r
- * @}\r
- */\r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-/* Function used to set the COMP configuration to the default reset state ****/\r
-void COMP_DeInit(void);\r
-\r
-/* Initialization and Configuration functions *********************************/\r
-void COMP_Init(COMP_InitTypeDef* COMP_InitStruct);\r
-void COMP_Cmd(FunctionalState NewState);\r
-uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection);\r
-\r
-/* Window mode control function ***********************************************/\r
-void COMP_WindowCmd(FunctionalState NewState);\r
-\r
-/* Internal Reference Voltage (VREFINT) output function ***********************/\r
-void COMP_VrefintOutputCmd(FunctionalState NewState);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_COMP_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_crc.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the CRC firmware \r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_CRC_H\r
-#define __STM32L1xx_CRC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup CRC\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup CRC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */ \r
-\r
-void CRC_ResetDR(void);\r
-uint32_t CRC_CalcCRC(uint32_t Data);\r
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);\r
-uint32_t CRC_GetCRC(void);\r
-void CRC_SetIDRegister(uint8_t IDValue);\r
-uint8_t CRC_GetIDRegister(void);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L1xx_CRC_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_dac.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the DAC firmware \r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_DAC_H\r
-#define __STM32L1xx_DAC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
- \r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup DAC\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief DAC Init structure definition\r
- */\r
- \r
-typedef struct\r
-{\r
- uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.\r
- This parameter can be a value of @ref DAC_trigger_selection */\r
-\r
- uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves\r
- are generated, or whether no wave is generated.\r
- This parameter can be a value of @ref DAC_wave_generation */\r
-\r
- uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or\r
- the maximum amplitude triangle generation for the DAC channel. \r
- This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */\r
-\r
- uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.\r
- This parameter can be a value of @ref DAC_output_buffer */\r
-}DAC_InitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup DAC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup DAC_trigger_selection \r
- * @{\r
- */\r
- \r
-#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \r
- has been loaded, and not by external trigger */\r
-#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_T9_TRGO ((uint32_t)0x0000001C) /*!< TIM9 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */\r
-\r
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \\r
- ((TRIGGER) == DAC_Trigger_T6_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_T7_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_T9_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_T2_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_T4_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_Ext_IT9) || \\r
- ((TRIGGER) == DAC_Trigger_Software))\r
- \r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup DAC_wave_generation \r
- * @{\r
- */\r
-\r
-#define DAC_WaveGeneration_None ((uint32_t)0x00000000)\r
-#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)\r
-#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)\r
-#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \\r
- ((WAVE) == DAC_WaveGeneration_Noise) || \\r
- ((WAVE) == DAC_WaveGeneration_Triangle))\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup DAC_lfsrunmask_triangleamplitude\r
- * @{\r
- */\r
-\r
-#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */\r
-#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */\r
-#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */\r
-#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */\r
-#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */\r
-#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */\r
-#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */\r
-#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */\r
-#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */\r
-#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */\r
-#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */\r
-#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */\r
-#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */\r
-\r
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \\r
- ((VALUE) == DAC_TriangleAmplitude_1) || \\r
- ((VALUE) == DAC_TriangleAmplitude_3) || \\r
- ((VALUE) == DAC_TriangleAmplitude_7) || \\r
- ((VALUE) == DAC_TriangleAmplitude_15) || \\r
- ((VALUE) == DAC_TriangleAmplitude_31) || \\r
- ((VALUE) == DAC_TriangleAmplitude_63) || \\r
- ((VALUE) == DAC_TriangleAmplitude_127) || \\r
- ((VALUE) == DAC_TriangleAmplitude_255) || \\r
- ((VALUE) == DAC_TriangleAmplitude_511) || \\r
- ((VALUE) == DAC_TriangleAmplitude_1023) || \\r
- ((VALUE) == DAC_TriangleAmplitude_2047) || \\r
- ((VALUE) == DAC_TriangleAmplitude_4095))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_output_buffer \r
- * @{\r
- */\r
-\r
-#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)\r
-#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)\r
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \\r
- ((STATE) == DAC_OutputBuffer_Disable))\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup DAC_Channel_selection \r
- * @{\r
- */\r
-\r
-#define DAC_Channel_1 ((uint32_t)0x00000000)\r
-#define DAC_Channel_2 ((uint32_t)0x00000010)\r
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \\r
- ((CHANNEL) == DAC_Channel_2))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_data_alignment \r
- * @{\r
- */\r
-\r
-#define DAC_Align_12b_R ((uint32_t)0x00000000)\r
-#define DAC_Align_12b_L ((uint32_t)0x00000004)\r
-#define DAC_Align_8b_R ((uint32_t)0x00000008)\r
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \\r
- ((ALIGN) == DAC_Align_12b_L) || \\r
- ((ALIGN) == DAC_Align_8b_R))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_wave_generation \r
- * @{\r
- */\r
-\r
-#define DAC_Wave_Noise ((uint32_t)0x00000040)\r
-#define DAC_Wave_Triangle ((uint32_t)0x00000080)\r
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \\r
- ((WAVE) == DAC_Wave_Triangle))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_data \r
- * @{\r
- */\r
-\r
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_interrupts_definition \r
- * @{\r
- */ \r
- \r
-#define DAC_IT_DMAUDR ((uint32_t)0x00002000) \r
-#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup DAC_flags_definition \r
- * @{\r
- */ \r
- \r
-#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) \r
- \r
-#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */ \r
-\r
-/* Function used to set the DAC configuration to the default reset state *****/ \r
-void DAC_DeInit(void);\r
-\r
-/* DAC channels configuration: trigger, output buffer, data format functions */\r
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);\r
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);\r
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);\r
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);\r
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);\r
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);\r
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);\r
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);\r
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);\r
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);\r
-\r
-/* DMA management functions ***************************************************/\r
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);\r
-\r
-/* Interrupts and flags management functions **********************************/\r
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);\r
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);\r
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_DAC_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_dbgmcu.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the DBGMCU \r
- * firmware library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_DBGMCU_H\r
-#define __STM32L1xx_DBGMCU_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup DBGMCU\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup DBGMCU_Exported_Constants\r
- * @{\r
- */\r
-\r
-#define DBGMCU_SLEEP ((uint32_t)0x00000001)\r
-#define DBGMCU_STOP ((uint32_t)0x00000002)\r
-#define DBGMCU_STANDBY ((uint32_t)0x00000004)\r
-#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))\r
-\r
-#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)\r
-#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)\r
-#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)\r
-#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)\r
-#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)\r
-#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)\r
-#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)\r
-#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)\r
-#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)\r
-#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)\r
-#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFF9FE3C8) == 0x00) && ((PERIPH) != 0x00))\r
-\r
-#define DBGMCU_TIM9_STOP ((uint32_t)0x00000004)\r
-#define DBGMCU_TIM10_STOP ((uint32_t)0x00000008)\r
-#define DBGMCU_TIM11_STOP ((uint32_t)0x00000010)\r
-#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE3) == 0x00) && ((PERIPH) != 0x00))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-uint32_t DBGMCU_GetREVID(void);\r
-uint32_t DBGMCU_GetDEVID(void);\r
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L1xx_DBGMCU_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_dma.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the DMA firmware \r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_DMA_H\r
-#define __STM32L1xx_DMA_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup DMA\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief DMA Init structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */\r
-\r
- uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */\r
-\r
- uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.\r
- This parameter can be a value of @ref DMA_data_transfer_direction */\r
-\r
- uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. \r
- The data unit is equal to the configuration set in DMA_PeripheralDataSize\r
- or DMA_MemoryDataSize members depending in the transfer direction. */\r
-\r
- uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.\r
- This parameter can be a value of @ref DMA_peripheral_incremented_mode */\r
-\r
- uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.\r
- This parameter can be a value of @ref DMA_memory_incremented_mode */\r
-\r
- uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.\r
- This parameter can be a value of @ref DMA_peripheral_data_size */\r
-\r
- uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.\r
- This parameter can be a value of @ref DMA_memory_data_size */\r
-\r
- uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.\r
- This parameter can be a value of @ref DMA_circular_normal_mode.\r
- @note: The circular buffer mode cannot be used if the memory-to-memory\r
- data transfer is configured on the selected Channel */\r
-\r
- uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.\r
- This parameter can be a value of @ref DMA_priority_level */\r
-\r
- uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.\r
- This parameter can be a value of @ref DMA_memory_to_memory */\r
-}DMA_InitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup DMA_Exported_Constants\r
- * @{\r
- */\r
-\r
-#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \\r
- ((PERIPH) == DMA1_Channel2) || \\r
- ((PERIPH) == DMA1_Channel3) || \\r
- ((PERIPH) == DMA1_Channel4) || \\r
- ((PERIPH) == DMA1_Channel5) || \\r
- ((PERIPH) == DMA1_Channel6) || \\r
- ((PERIPH) == DMA1_Channel7))\r
-\r
-/** @defgroup DMA_data_transfer_direction \r
- * @{\r
- */\r
-\r
-#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)\r
-#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)\r
-#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \\r
- ((DIR) == DMA_DIR_PeripheralSRC))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_peripheral_incremented_mode \r
- * @{\r
- */\r
-\r
-#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)\r
-#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)\r
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \\r
- ((STATE) == DMA_PeripheralInc_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_memory_incremented_mode \r
- * @{\r
- */\r
-\r
-#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)\r
-#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)\r
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \\r
- ((STATE) == DMA_MemoryInc_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_peripheral_data_size \r
- * @{\r
- */\r
-\r
-#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)\r
-#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)\r
-#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)\r
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \\r
- ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \\r
- ((SIZE) == DMA_PeripheralDataSize_Word))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_memory_data_size \r
- * @{\r
- */\r
-\r
-#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)\r
-#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)\r
-#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)\r
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \\r
- ((SIZE) == DMA_MemoryDataSize_HalfWord) || \\r
- ((SIZE) == DMA_MemoryDataSize_Word))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_circular_normal_mode \r
- * @{\r
- */\r
-\r
-#define DMA_Mode_Circular ((uint32_t)0x00000020)\r
-#define DMA_Mode_Normal ((uint32_t)0x00000000)\r
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_priority_level \r
- * @{\r
- */\r
-\r
-#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)\r
-#define DMA_Priority_High ((uint32_t)0x00002000)\r
-#define DMA_Priority_Medium ((uint32_t)0x00001000)\r
-#define DMA_Priority_Low ((uint32_t)0x00000000)\r
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \\r
- ((PRIORITY) == DMA_Priority_High) || \\r
- ((PRIORITY) == DMA_Priority_Medium) || \\r
- ((PRIORITY) == DMA_Priority_Low))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_memory_to_memory \r
- * @{\r
- */\r
-\r
-#define DMA_M2M_Enable ((uint32_t)0x00004000)\r
-#define DMA_M2M_Disable ((uint32_t)0x00000000)\r
-#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_interrupts_definition \r
- * @{\r
- */\r
-\r
-#define DMA_IT_TC ((uint32_t)0x00000002)\r
-#define DMA_IT_HT ((uint32_t)0x00000004)\r
-#define DMA_IT_TE ((uint32_t)0x00000008)\r
-#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))\r
-\r
-#define DMA1_IT_GL1 ((uint32_t)0x00000001)\r
-#define DMA1_IT_TC1 ((uint32_t)0x00000002)\r
-#define DMA1_IT_HT1 ((uint32_t)0x00000004)\r
-#define DMA1_IT_TE1 ((uint32_t)0x00000008)\r
-#define DMA1_IT_GL2 ((uint32_t)0x00000010)\r
-#define DMA1_IT_TC2 ((uint32_t)0x00000020)\r
-#define DMA1_IT_HT2 ((uint32_t)0x00000040)\r
-#define DMA1_IT_TE2 ((uint32_t)0x00000080)\r
-#define DMA1_IT_GL3 ((uint32_t)0x00000100)\r
-#define DMA1_IT_TC3 ((uint32_t)0x00000200)\r
-#define DMA1_IT_HT3 ((uint32_t)0x00000400)\r
-#define DMA1_IT_TE3 ((uint32_t)0x00000800)\r
-#define DMA1_IT_GL4 ((uint32_t)0x00001000)\r
-#define DMA1_IT_TC4 ((uint32_t)0x00002000)\r
-#define DMA1_IT_HT4 ((uint32_t)0x00004000)\r
-#define DMA1_IT_TE4 ((uint32_t)0x00008000)\r
-#define DMA1_IT_GL5 ((uint32_t)0x00010000)\r
-#define DMA1_IT_TC5 ((uint32_t)0x00020000)\r
-#define DMA1_IT_HT5 ((uint32_t)0x00040000)\r
-#define DMA1_IT_TE5 ((uint32_t)0x00080000)\r
-#define DMA1_IT_GL6 ((uint32_t)0x00100000)\r
-#define DMA1_IT_TC6 ((uint32_t)0x00200000)\r
-#define DMA1_IT_HT6 ((uint32_t)0x00400000)\r
-#define DMA1_IT_TE6 ((uint32_t)0x00800000)\r
-#define DMA1_IT_GL7 ((uint32_t)0x01000000)\r
-#define DMA1_IT_TC7 ((uint32_t)0x02000000)\r
-#define DMA1_IT_HT7 ((uint32_t)0x04000000)\r
-#define DMA1_IT_TE7 ((uint32_t)0x08000000)\r
-\r
-#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xF0000000) == 0x00) && ((IT) != 0x00))\r
-\r
-#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \\r
- ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \\r
- ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \\r
- ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \\r
- ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \\r
- ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \\r
- ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \\r
- ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \\r
- ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \\r
- ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \\r
- ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \\r
- ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \\r
- ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \\r
- ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_flags_definition \r
- * @{\r
- */\r
-#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)\r
-#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)\r
-#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)\r
-#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)\r
-#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)\r
-#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)\r
-#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)\r
-#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)\r
-#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)\r
-#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)\r
-#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)\r
-#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)\r
-#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)\r
-#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)\r
-#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)\r
-#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)\r
-#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)\r
-#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)\r
-#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)\r
-#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)\r
-#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)\r
-#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)\r
-#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)\r
-#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)\r
-#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)\r
-#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)\r
-#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)\r
-#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)\r
-\r
-#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0xF0000000) == 0x00) && ((FLAG) != 0x00))\r
-\r
-#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \\r
- ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \\r
- ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \\r
- ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \\r
- ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \\r
- ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \\r
- ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \\r
- ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \\r
- ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \\r
- ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \\r
- ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \\r
- ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \\r
- ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \\r
- ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Buffer_Size \r
- * @{\r
- */\r
-\r
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-/* Function used to set the DMA configuration to the default reset state *****/ \r
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);\r
-\r
-/* Initialization and Configuration functions *********************************/\r
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);\r
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);\r
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);\r
-\r
-/* Data Counter functions *****************************************************/\r
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);\r
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);\r
-\r
-/* Interrupts and flags management functions **********************************/\r
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);\r
-FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);\r
-void DMA_ClearFlag(uint32_t DMA_FLAG);\r
-ITStatus DMA_GetITStatus(uint32_t DMA_IT);\r
-void DMA_ClearITPendingBit(uint32_t DMA_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_DMA_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_exti.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the EXTI firmware\r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_EXTI_H\r
-#define __STM32L1xx_EXTI_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup EXTI\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief EXTI mode enumeration \r
- */\r
-\r
-typedef enum\r
-{\r
- EXTI_Mode_Interrupt = 0x00,\r
- EXTI_Mode_Event = 0x04\r
-}EXTIMode_TypeDef;\r
-\r
-#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))\r
-\r
-/** \r
- * @brief EXTI Trigger enumeration \r
- */\r
-\r
-typedef enum\r
-{\r
- EXTI_Trigger_Rising = 0x08,\r
- EXTI_Trigger_Falling = 0x0C, \r
- EXTI_Trigger_Rising_Falling = 0x10\r
-}EXTITrigger_TypeDef;\r
-\r
-#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \\r
- ((TRIGGER) == EXTI_Trigger_Falling) || \\r
- ((TRIGGER) == EXTI_Trigger_Rising_Falling))\r
-/** \r
- * @brief EXTI Init Structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.\r
- This parameter can be any combination of @ref EXTI_Lines */\r
- \r
- EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.\r
- This parameter can be a value of @ref EXTIMode_TypeDef */\r
-\r
- EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.\r
- This parameter can be a value of @ref EXTIMode_TypeDef */\r
-\r
- FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.\r
- This parameter can be set either to ENABLE or DISABLE */ \r
-}EXTI_InitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup EXTI_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup EXTI_Lines \r
- * @{\r
- */\r
-\r
-#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */\r
-#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */\r
-#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */\r
-#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */\r
-#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */\r
-#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */\r
-#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */\r
-#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */\r
-#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */\r
-#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */\r
-#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */\r
-#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */\r
-#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */\r
-#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */\r
-#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */\r
-#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */\r
-#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16 \r
- Connected to the PVD Output */\r
-#define EXTI_Line17 ((uint32_t)0x00020000) /*!< External interrupt line 17 \r
- Connected to the RTC Alarm \r
- event */\r
-#define EXTI_Line18 ((uint32_t)0x00040000) /*!< External interrupt line 18 \r
- Connected to the USB Device \r
- FS Wakeup from suspend event */\r
-#define EXTI_Line19 ((uint32_t)0x00080000) /*!< External interrupt line 19 \r
- Connected to the RTC Tamper \r
- and Time Stamp events */ \r
-#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 \r
- Connected to the RTC Wakeup \r
- event */\r
-#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 \r
- Connected to the Comparator 1 \r
- event */\r
-\r
-#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 \r
- Connected to the Comparator 2\r
- event */\r
- \r
-#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))\r
-\r
-#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \\r
- ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \\r
- ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \\r
- ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \\r
- ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \\r
- ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \\r
- ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \\r
- ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \\r
- ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \\r
- ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \\r
- ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \\r
- ((LINE) == EXTI_Line22))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-/* Function used to set the EXTI configuration to the default reset state *****/\r
-void EXTI_DeInit(void);\r
-\r
-/* Initialization and Configuration functions *********************************/\r
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);\r
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);\r
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);\r
-\r
-/* Interrupts and flags management functions **********************************/\r
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);\r
-void EXTI_ClearFlag(uint32_t EXTI_Line);\r
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);\r
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L1xx_EXTI_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_flash.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the FLASH \r
- * firmware library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_FLASH_H\r
-#define __STM32L1xx_FLASH_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup FLASH\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief FLASH Status \r
- */ \r
-typedef enum\r
-{ \r
- FLASH_BUSY = 1,\r
- FLASH_ERROR_WRP,\r
- FLASH_ERROR_PROGRAM,\r
- FLASH_COMPLETE,\r
- FLASH_TIMEOUT\r
-}FLASH_Status;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
- \r
-/** @defgroup FLASH_Exported_Constants\r
- * @{\r
- */ \r
- \r
-/** @defgroup FLASH_Latency \r
- * @{\r
- */ \r
-#define FLASH_Latency_0 ((uint8_t)0x00) /*!< FLASH Zero Latency cycle */\r
-#define FLASH_Latency_1 ((uint8_t)0x01) /*!< FLASH One Latency cycle */\r
-\r
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \\r
- ((LATENCY) == FLASH_Latency_1))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup FLASH_Interrupts \r
- * @{\r
- */\r
- \r
-#define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */\r
-#define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */\r
-#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFCFFFF) == 0x00000000) && (((IT) != 0x00000000)))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup FLASH_Address \r
- * @{\r
- */\r
- \r
-#define IS_FLASH_DATA_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08080000) && ((ADDRESS) <= 0x08080FFF))\r
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF)) \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup Option_Bytes_Write_Protection \r
- * @{\r
- */\r
- \r
-\r
-#define OB_WRP_Pages0to15 ((uint32_t)0x00000001) /* Write protection of Sector0 */\r
-#define OB_WRP_Pages16to31 ((uint32_t)0x00000002) /* Write protection of Sector1 */\r
-#define OB_WRP_Pages32to47 ((uint32_t)0x00000004) /* Write protection of Sector2 */\r
-#define OB_WRP_Pages48to63 ((uint32_t)0x00000008) /* Write protection of Sector3 */\r
-#define OB_WRP_Pages64to79 ((uint32_t)0x00000010) /* Write protection of Sector4 */\r
-#define OB_WRP_Pages80to95 ((uint32_t)0x00000020) /* Write protection of Sector5 */\r
-#define OB_WRP_Pages96to111 ((uint32_t)0x00000040) /* Write protection of Sector6 */\r
-#define OB_WRP_Pages112to127 ((uint32_t)0x00000080) /* Write protection of Sector7 */\r
-#define OB_WRP_Pages128to143 ((uint32_t)0x00000100) /* Write protection of Sector8 */\r
-#define OB_WRP_Pages144to159 ((uint32_t)0x00000200) /* Write protection of Sector9 */\r
-#define OB_WRP_Pages160to175 ((uint32_t)0x00000400) /* Write protection of Sector10 */\r
-#define OB_WRP_Pages176to191 ((uint32_t)0x00000800) /* Write protection of Sector11 */\r
-#define OB_WRP_Pages192to207 ((uint32_t)0x00001000) /* Write protection of Sector12 */\r
-#define OB_WRP_Pages208to223 ((uint32_t)0x00002000) /* Write protection of Sector13 */\r
-#define OB_WRP_Pages224to239 ((uint32_t)0x00004000) /* Write protection of Sector14 */\r
-#define OB_WRP_Pages240to255 ((uint32_t)0x00008000) /* Write protection of Sector15 */\r
-#define OB_WRP_Pages256to271 ((uint32_t)0x00010000) /* Write protection of Sector16 */\r
-#define OB_WRP_Pages272to287 ((uint32_t)0x00020000) /* Write protection of Sector17 */\r
-#define OB_WRP_Pages288to303 ((uint32_t)0x00040000) /* Write protection of Sector18 */\r
-#define OB_WRP_Pages304to319 ((uint32_t)0x00080000) /* Write protection of Sector19 */\r
-#define OB_WRP_Pages320to335 ((uint32_t)0x00100000) /* Write protection of Sector20 */\r
-#define OB_WRP_Pages336to351 ((uint32_t)0x00200000) /* Write protection of Sector21 */\r
-#define OB_WRP_Pages352to367 ((uint32_t)0x00400000) /* Write protection of Sector22 */\r
-#define OB_WRP_Pages368to383 ((uint32_t)0x00800000) /* Write protection of Sector23 */\r
-#define OB_WRP_Pages384to399 ((uint32_t)0x01000000) /* Write protection of Sector24 */\r
-#define OB_WRP_Pages400to415 ((uint32_t)0x02000000) /* Write protection of Sector25 */\r
-#define OB_WRP_Pages416to431 ((uint32_t)0x04000000) /* Write protection of Sector26 */\r
-#define OB_WRP_Pages432to447 ((uint32_t)0x08000000) /* Write protection of Sector27 */\r
-#define OB_WRP_Pages448to463 ((uint32_t)0x10000000) /* Write protection of Sector28 */\r
-#define OB_WRP_Pages464to479 ((uint32_t)0x20000000) /* Write protection of Sector29 */\r
-#define OB_WRP_Pages480to495 ((uint32_t)0x40000000) /* Write protection of Sector30 */\r
-#define OB_WRP_Pages496to511 ((uint32_t)0x80000000) /* Write protection of Sector31 */\r
-\r
-#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */\r
-\r
-#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Option_Bytes_Read_Protection \r
- * @{\r
- */ \r
-\r
-/** \r
- * @brief Read Protection Level \r
- */ \r
-#define OB_RDP_Level_0 ((uint8_t)0xAA)\r
-#define OB_RDP_Level_1 ((uint8_t)0xBB)\r
-/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 \r
- it's no more possible to go back to level 1 or 0 */\r
-\r
-#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\\r
- ((LEVEL) == OB_RDP_Level_1))/*||\\r
- ((LEVEL) == OB_RDP_Level_2))*/\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup Option_Bytes_IWatchdog \r
- * @{\r
- */\r
-\r
-#define OB_IWDG_SW ((uint8_t)0x10) /*!< Software WDG selected */\r
-#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */\r
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Option_Bytes_nRST_STOP \r
- * @{\r
- */\r
-\r
-#define OB_STOP_NoRST ((uint8_t)0x20) /*!< No reset generated when entering in STOP */\r
-#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */\r
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Option_Bytes_nRST_STDBY \r
- * @{\r
- */\r
-\r
-#define OB_STDBY_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */\r
-#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */\r
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Option_Bytes_BOR_Level \r
- * @{\r
- */\r
-\r
-#define OB_BOR_OFF ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD \r
- power supply reaches the PDR(Power Down Reset) threshold (1.5V) */\r
-#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */\r
-#define OB_BOR_LEVEL2 ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */\r
-#define OB_BOR_LEVEL3 ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */\r
-#define OB_BOR_LEVEL4 ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */\r
-#define OB_BOR_LEVEL5 ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */\r
-\r
-#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_OFF) || \\r
- ((LEVEL) == OB_BOR_LEVEL1) || \\r
- ((LEVEL) == OB_BOR_LEVEL2) || \\r
- ((LEVEL) == OB_BOR_LEVEL3) || \\r
- ((LEVEL) == OB_BOR_LEVEL4) || \\r
- ((LEVEL) == OB_BOR_LEVEL5))\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup FLASH_Flags \r
- * @{\r
- */ \r
-\r
-#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */\r
-#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */\r
-#define FLASH_FLAG_ENDHV FLASH_SR_ENHV /*!< FLASH End of High Voltage flag */\r
-#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */\r
-#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */\r
-#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */\r
-#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */\r
-#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */\r
- \r
-#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFF0FD) == 0x00000000) && ((FLAG) != 0x00000000))\r
-\r
-#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \\r
- ((FLAG) == FLASH_FLAG_ENDHV) || ((FLAG) == FLASH_FLAG_READY ) || \\r
- ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR ) || \\r
- ((FLAG) == FLASH_FLAG_SIZERR) || ((FLAG) == FLASH_FLAG_OPTVERR))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup FLASH_Keys \r
- * @{\r
- */ \r
-\r
-#define FLASH_PDKEY1 ((uint32_t)0x04152637) /*!< Flash power down key1 */\r
-#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1 \r
- to unlock the RUN_PD bit in FLASH_ACR */\r
-\r
-#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */\r
-#define FLASH_PEKEY2 ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2\r
- to unlock the write access to the FLASH_PECR register and\r
- data EEPROM */\r
-\r
-#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */\r
-#define FLASH_PRGKEY2 ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2\r
- to unlock the program memory */\r
-\r
-#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */\r
-#define FLASH_OPTKEY2 ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to\r
- unlock the write access to the option byte block */\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup Timeout_definition \r
- * @{\r
- */ \r
-#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x8000)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
- \r
-/** \r
- * @brief FLASH memory functions that can be executed from FLASH. \r
- */ \r
-/* FLASH Interface configuration functions ************************************/ \r
-void FLASH_SetLatency(uint32_t FLASH_Latency);\r
-void FLASH_PrefetchBufferCmd(FunctionalState NewState);\r
-void FLASH_ReadAccess64Cmd(FunctionalState NewState);\r
-void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);\r
-\r
-/* FLASH Memory Programming functions *****************************************/ \r
-void FLASH_Unlock(void);\r
-void FLASH_Lock(void);\r
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address);\r
-FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);\r
-\r
-/* DATA EEPROM Programming functions ******************************************/ \r
-void DATA_EEPROM_Unlock(void);\r
-void DATA_EEPROM_Lock(void);\r
-void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState);\r
-FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);\r
-FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);\r
-FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);\r
-FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);\r
-FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);\r
-FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
-FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);\r
-\r
-/* Option Bytes Programming functions *****************************************/\r
-void FLASH_OB_Unlock(void);\r
-void FLASH_OB_Lock(void);\r
-void FLASH_OB_Launch(void);\r
-FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);\r
-FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);\r
-FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);\r
-FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);\r
-uint8_t FLASH_OB_GetUser(void);\r
-uint32_t FLASH_OB_GetWRP(void);\r
-FlagStatus FLASH_OB_GetRDP(void);\r
-uint8_t FLASH_OB_GetBOR(void);\r
-\r
-/* Interrupts and flags management functions **********************************/ \r
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);\r
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);\r
-void FLASH_ClearFlag(uint32_t FLASH_FLAG);\r
-FLASH_Status FLASH_GetStatus(void);\r
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);\r
-\r
-/** \r
- * @brief FLASH memory functions that should be executed from internal SRAM.\r
- * These functions are defined inside the "stm32l1xx_flash_ramfunc.c"\r
- * file.\r
- */ \r
-FLASH_Status FLASH_RUNPowerDownCmd(FunctionalState NewState);\r
-FLASH_Status FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer);\r
-FLASH_Status DATA_EEPROM_EraseDoubleWord(uint32_t Address);\r
-FLASH_Status DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data);\r
- \r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L1xx_FLASH_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_gpio.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the GPIO \r
- * firmware library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_GPIO_H\r
-#define __STM32L1xx_GPIO_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup GPIO\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \\r
- ((PERIPH) == GPIOB) || \\r
- ((PERIPH) == GPIOC) || \\r
- ((PERIPH) == GPIOD) || \\r
- ((PERIPH) == GPIOE) || \\r
- ((PERIPH) == GPIOH))\r
-\r
-/** @defgroup Configuration_Mode_enumeration \r
- * @{\r
- */ \r
-typedef enum\r
-{ \r
- GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */\r
- GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */\r
- GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */\r
- GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */\r
-}GPIOMode_TypeDef;\r
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \\r
- ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Output_type_enumeration\r
- * @{\r
- */ \r
-typedef enum\r
-{ GPIO_OType_PP = 0x00,\r
- GPIO_OType_OD = 0x01\r
-}GPIOOType_TypeDef;\r
-#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Output_Maximum_frequency_enumeration \r
- * @{\r
- */ \r
-typedef enum\r
-{ \r
- GPIO_Speed_400KHz = 0x00, /*!< Very Low Speed */\r
- GPIO_Speed_2MHz = 0x01, /*!< Low Speed */\r
- GPIO_Speed_10MHz = 0x02, /*!< Medium Speed */\r
- GPIO_Speed_40MHz = 0x03 /*!< High Speed */\r
-}GPIOSpeed_TypeDef;\r
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_400KHz) || ((SPEED) == GPIO_Speed_2MHz) || \\r
- ((SPEED) == GPIO_Speed_10MHz)|| ((SPEED) == GPIO_Speed_40MHz))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration \r
- * @{\r
- */ \r
-typedef enum\r
-{ GPIO_PuPd_NOPULL = 0x00,\r
- GPIO_PuPd_UP = 0x01,\r
- GPIO_PuPd_DOWN = 0x02\r
-}GPIOPuPd_TypeDef;\r
-#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \\r
- ((PUPD) == GPIO_PuPd_DOWN))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Bit_SET_and_Bit_RESET_enumeration\r
- * @{\r
- */\r
-typedef enum\r
-{ Bit_RESET = 0,\r
- Bit_SET\r
-}BitAction;\r
-#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** \r
- * @brief GPIO Init structure definition\r
- */ \r
-typedef struct\r
-{\r
- uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.\r
- This parameter can be any value of @ref GPIO_pins_define */\r
-\r
- GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.\r
- This parameter can be a value of @ref GPIOMode_TypeDef */\r
-\r
- GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.\r
- This parameter can be a value of @ref GPIOSpeed_TypeDef */\r
-\r
- GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.\r
- This parameter can be a value of @ref GPIOOType_TypeDef */\r
-\r
- GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.\r
- This parameter can be a value of @ref GPIOPuPd_TypeDef */\r
-}GPIO_InitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup GPIO_Exported_Constants\r
- * @{\r
- */\r
- \r
-/** @defgroup GPIO_pins_define \r
- * @{\r
- */\r
-#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */\r
-#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */\r
-#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */\r
-#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */\r
-#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */\r
-#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */\r
-#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */\r
-#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */\r
-#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */\r
-#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */\r
-#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */\r
-#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */\r
-#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */\r
-#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */\r
-#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */\r
-#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */\r
-#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */\r
-\r
-#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)\r
-#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \\r
- ((PIN) == GPIO_Pin_1) || \\r
- ((PIN) == GPIO_Pin_2) || \\r
- ((PIN) == GPIO_Pin_3) || \\r
- ((PIN) == GPIO_Pin_4) || \\r
- ((PIN) == GPIO_Pin_5) || \\r
- ((PIN) == GPIO_Pin_6) || \\r
- ((PIN) == GPIO_Pin_7) || \\r
- ((PIN) == GPIO_Pin_8) || \\r
- ((PIN) == GPIO_Pin_9) || \\r
- ((PIN) == GPIO_Pin_10) || \\r
- ((PIN) == GPIO_Pin_11) || \\r
- ((PIN) == GPIO_Pin_12) || \\r
- ((PIN) == GPIO_Pin_13) || \\r
- ((PIN) == GPIO_Pin_14) || \\r
- ((PIN) == GPIO_Pin_15))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_Pin_sources \r
- * @{\r
- */ \r
-#define GPIO_PinSource0 ((uint8_t)0x00)\r
-#define GPIO_PinSource1 ((uint8_t)0x01)\r
-#define GPIO_PinSource2 ((uint8_t)0x02)\r
-#define GPIO_PinSource3 ((uint8_t)0x03)\r
-#define GPIO_PinSource4 ((uint8_t)0x04)\r
-#define GPIO_PinSource5 ((uint8_t)0x05)\r
-#define GPIO_PinSource6 ((uint8_t)0x06)\r
-#define GPIO_PinSource7 ((uint8_t)0x07)\r
-#define GPIO_PinSource8 ((uint8_t)0x08)\r
-#define GPIO_PinSource9 ((uint8_t)0x09)\r
-#define GPIO_PinSource10 ((uint8_t)0x0A)\r
-#define GPIO_PinSource11 ((uint8_t)0x0B)\r
-#define GPIO_PinSource12 ((uint8_t)0x0C)\r
-#define GPIO_PinSource13 ((uint8_t)0x0D)\r
-#define GPIO_PinSource14 ((uint8_t)0x0E)\r
-#define GPIO_PinSource15 ((uint8_t)0x0F)\r
-\r
-#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \\r
- ((PINSOURCE) == GPIO_PinSource1) || \\r
- ((PINSOURCE) == GPIO_PinSource2) || \\r
- ((PINSOURCE) == GPIO_PinSource3) || \\r
- ((PINSOURCE) == GPIO_PinSource4) || \\r
- ((PINSOURCE) == GPIO_PinSource5) || \\r
- ((PINSOURCE) == GPIO_PinSource6) || \\r
- ((PINSOURCE) == GPIO_PinSource7) || \\r
- ((PINSOURCE) == GPIO_PinSource8) || \\r
- ((PINSOURCE) == GPIO_PinSource9) || \\r
- ((PINSOURCE) == GPIO_PinSource10) || \\r
- ((PINSOURCE) == GPIO_PinSource11) || \\r
- ((PINSOURCE) == GPIO_PinSource12) || \\r
- ((PINSOURCE) == GPIO_PinSource13) || \\r
- ((PINSOURCE) == GPIO_PinSource14) || \\r
- ((PINSOURCE) == GPIO_PinSource15))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_Alternat_function_selection_define \r
- * @{\r
- */\r
-\r
-/** \r
- * @brief AF 0 selection \r
- */ \r
-#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /*!< RTC 50/60 Hz Alternate Function mapping */\r
-#define GPIO_AF_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */\r
-#define GPIO_AF_RTC_AF1 ((uint8_t)0x00) /*!< RTC_AF1 Alternate Function mapping */\r
-#define GPIO_AF_WKUP ((uint8_t)0x00) /*!< Wakeup (WKUP1, WKUP2 and WKUP3) Alternate Function mapping */\r
-#define GPIO_AF_SWJ ((uint8_t)0x00) /*!< SWJ (SW and JTAG) Alternate Function mapping */\r
-#define GPIO_AF_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */\r
-\r
-/** \r
- * @brief AF 1 selection \r
- */ \r
-#define GPIO_AF_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */\r
-/** \r
- * @brief AF 2 selection \r
- */ \r
-#define GPIO_AF_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */\r
-#define GPIO_AF_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */\r
-/** \r
- * @brief AF 3 selection \r
- */ \r
-#define GPIO_AF_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */\r
-#define GPIO_AF_TIM10 ((uint8_t)0x03) /*!< TIM10 Alternate Function mapping */\r
-#define GPIO_AF_TIM11 ((uint8_t)0x03) /*!< TIM11 Alternate Function mapping */\r
-/** \r
- * @brief AF 4 selection \r
- */ \r
-#define GPIO_AF_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */\r
-#define GPIO_AF_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */\r
-/** \r
- * @brief AF 5 selection \r
- */ \r
-#define GPIO_AF_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */\r
-#define GPIO_AF_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */\r
-/** \r
- * @brief AF 7 selection \r
- */ \r
-#define GPIO_AF_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */\r
-#define GPIO_AF_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */\r
-#define GPIO_AF_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */\r
-/** \r
- * @brief AF 10 selection \r
- */ \r
-#define GPIO_AF_USB ((uint8_t)0xA) /*!< USB Full speed device Alternate Function mapping */\r
-/** \r
- * @brief AF 11 selection \r
- */ \r
-#define GPIO_AF_LCD ((uint8_t)0x0B) /*!< LCD Alternate Function mapping */\r
-/** \r
- * @brief AF 14 selection \r
- */ \r
-#define GPIO_AF_RI ((uint8_t)0x0E) /*!< RI Alternate Function mapping */\r
-\r
-/** \r
- * @brief AF 15 selection \r
- */ \r
-#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */\r
-\r
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_MCO) || \\r
- ((AF) == GPIO_AF_RTC_AF1) || ((AF) == GPIO_AF_WKUP) || \\r
- ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \\r
- ((AF) == GPIO_AF_TIM2) || ((AF)== GPIO_AF_TIM3) || \\r
- ((AF) == GPIO_AF_TIM4) || ((AF)== GPIO_AF_TIM9) || \\r
- ((AF) == GPIO_AF_TIM10) || ((AF)== GPIO_AF_TIM11) || \\r
- ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \\r
- ((AF) == GPIO_AF_SPI1) || ((AF) == GPIO_AF_SPI2) || \\r
- ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \\r
- ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_USB) || \\r
- ((AF) == GPIO_AF_LCD) || ((AF) == GPIO_AF_RI) || \\r
- ((AF) == GPIO_AF_EVENTOUT))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_Legacy \r
- * @{\r
- */\r
- \r
-#define GPIO_Mode_AIN GPIO_Mode_AN\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
- \r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-/* Function used to set the GPIO configuration to the default reset state ****/\r
-void GPIO_DeInit(GPIO_TypeDef* GPIOx);\r
-\r
-/* Initialization and Configuration functions *********************************/\r
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);\r
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);\r
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
-\r
-/* GPIO Read and Write functions **********************************************/\r
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);\r
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);\r
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);\r
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);\r
-\r
-/* GPIO Alternate functions configuration functions ***************************/\r
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_GPIO_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_i2c.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the I2C firmware \r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_I2C_H\r
-#define __STM32L1xx_I2C_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup I2C\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief I2C Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.\r
- This parameter must be set to a value lower than 400kHz */\r
-\r
- uint16_t I2C_Mode; /*!< Specifies the I2C mode.\r
- This parameter can be a value of @ref I2C_mode */\r
-\r
- uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.\r
- This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */\r
-\r
- uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.\r
- This parameter can be a 7-bit or 10-bit address. */\r
-\r
- uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.\r
- This parameter can be a value of @ref I2C_acknowledgement */\r
-\r
- uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.\r
- This parameter can be a value of @ref I2C_acknowledged_address */\r
-}I2C_InitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-\r
-/** @defgroup I2C_Exported_Constants\r
- * @{\r
- */\r
-\r
-#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \\r
- ((PERIPH) == I2C2))\r
-/** @defgroup I2C_mode \r
- * @{\r
- */\r
-\r
-#define I2C_Mode_I2C ((uint16_t)0x0000)\r
-#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) \r
-#define I2C_Mode_SMBusHost ((uint16_t)0x000A)\r
-#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \\r
- ((MODE) == I2C_Mode_SMBusDevice) || \\r
- ((MODE) == I2C_Mode_SMBusHost))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_duty_cycle_in_fast_mode \r
- * @{\r
- */\r
-\r
-#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */\r
-#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */\r
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \\r
- ((CYCLE) == I2C_DutyCycle_2))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2C_acknowledgement\r
- * @{\r
- */\r
-\r
-#define I2C_Ack_Enable ((uint16_t)0x0400)\r
-#define I2C_Ack_Disable ((uint16_t)0x0000)\r
-#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \\r
- ((STATE) == I2C_Ack_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_transfer_direction \r
- * @{\r
- */\r
-\r
-#define I2C_Direction_Transmitter ((uint8_t)0x00)\r
-#define I2C_Direction_Receiver ((uint8_t)0x01)\r
-#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \\r
- ((DIRECTION) == I2C_Direction_Receiver))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_acknowledged_address \r
- * @{\r
- */\r
-\r
-#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)\r
-#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)\r
-#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \\r
- ((ADDRESS) == I2C_AcknowledgedAddress_10bit))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2C_registers \r
- * @{\r
- */\r
-\r
-#define I2C_Register_CR1 ((uint8_t)0x00)\r
-#define I2C_Register_CR2 ((uint8_t)0x04)\r
-#define I2C_Register_OAR1 ((uint8_t)0x08)\r
-#define I2C_Register_OAR2 ((uint8_t)0x0C)\r
-#define I2C_Register_DR ((uint8_t)0x10)\r
-#define I2C_Register_SR1 ((uint8_t)0x14)\r
-#define I2C_Register_SR2 ((uint8_t)0x18)\r
-#define I2C_Register_CCR ((uint8_t)0x1C)\r
-#define I2C_Register_TRISE ((uint8_t)0x20)\r
-#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \\r
- ((REGISTER) == I2C_Register_CR2) || \\r
- ((REGISTER) == I2C_Register_OAR1) || \\r
- ((REGISTER) == I2C_Register_OAR2) || \\r
- ((REGISTER) == I2C_Register_DR) || \\r
- ((REGISTER) == I2C_Register_SR1) || \\r
- ((REGISTER) == I2C_Register_SR2) || \\r
- ((REGISTER) == I2C_Register_CCR) || \\r
- ((REGISTER) == I2C_Register_TRISE))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_SMBus_alert_pin_level \r
- * @{\r
- */\r
-\r
-#define I2C_SMBusAlert_Low ((uint16_t)0x2000)\r
-#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)\r
-#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \\r
- ((ALERT) == I2C_SMBusAlert_High))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_PEC_position \r
- * @{\r
- */\r
-\r
-#define I2C_PECPosition_Next ((uint16_t)0x0800)\r
-#define I2C_PECPosition_Current ((uint16_t)0xF7FF)\r
-#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \\r
- ((POSITION) == I2C_PECPosition_Current))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2C_interrupts_definition \r
- * @{\r
- */\r
-\r
-#define I2C_IT_BUF ((uint16_t)0x0400)\r
-#define I2C_IT_EVT ((uint16_t)0x0200)\r
-#define I2C_IT_ERR ((uint16_t)0x0100)\r
-#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2C_interrupts_definition \r
- * @{\r
- */\r
-\r
-#define I2C_IT_SMBALERT ((uint32_t)0x01008000)\r
-#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)\r
-#define I2C_IT_PECERR ((uint32_t)0x01001000)\r
-#define I2C_IT_OVR ((uint32_t)0x01000800)\r
-#define I2C_IT_AF ((uint32_t)0x01000400)\r
-#define I2C_IT_ARLO ((uint32_t)0x01000200)\r
-#define I2C_IT_BERR ((uint32_t)0x01000100)\r
-#define I2C_IT_TXE ((uint32_t)0x06000080)\r
-#define I2C_IT_RXNE ((uint32_t)0x06000040)\r
-#define I2C_IT_STOPF ((uint32_t)0x02000010)\r
-#define I2C_IT_ADD10 ((uint32_t)0x02000008)\r
-#define I2C_IT_BTF ((uint32_t)0x02000004)\r
-#define I2C_IT_ADDR ((uint32_t)0x02000002)\r
-#define I2C_IT_SB ((uint32_t)0x02000001)\r
-\r
-#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))\r
-\r
-#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \\r
- ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \\r
- ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \\r
- ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \\r
- ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \\r
- ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \\r
- ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_flags_definition \r
- * @{\r
- */\r
-\r
-/** \r
- * @brief SR2 register flags \r
- */\r
-\r
-#define I2C_FLAG_DUALF ((uint32_t)0x00800000)\r
-#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)\r
-#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)\r
-#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)\r
-#define I2C_FLAG_TRA ((uint32_t)0x00040000)\r
-#define I2C_FLAG_BUSY ((uint32_t)0x00020000)\r
-#define I2C_FLAG_MSL ((uint32_t)0x00010000)\r
-\r
-/** \r
- * @brief SR1 register flags \r
- */\r
-\r
-#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)\r
-#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)\r
-#define I2C_FLAG_PECERR ((uint32_t)0x10001000)\r
-#define I2C_FLAG_OVR ((uint32_t)0x10000800)\r
-#define I2C_FLAG_AF ((uint32_t)0x10000400)\r
-#define I2C_FLAG_ARLO ((uint32_t)0x10000200)\r
-#define I2C_FLAG_BERR ((uint32_t)0x10000100)\r
-#define I2C_FLAG_TXE ((uint32_t)0x10000080)\r
-#define I2C_FLAG_RXNE ((uint32_t)0x10000040)\r
-#define I2C_FLAG_STOPF ((uint32_t)0x10000010)\r
-#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)\r
-#define I2C_FLAG_BTF ((uint32_t)0x10000004)\r
-#define I2C_FLAG_ADDR ((uint32_t)0x10000002)\r
-#define I2C_FLAG_SB ((uint32_t)0x10000001)\r
-\r
-#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
-\r
-#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \\r
- ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \\r
- ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \\r
- ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \\r
- ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \\r
- ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \\r
- ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \\r
- ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \\r
- ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \\r
- ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \\r
- ((FLAG) == I2C_FLAG_SB))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Events \r
- * @{\r
- */\r
-\r
-/**\r
- ===============================================================================\r
- I2C Master Events (Events grouped in order of communication) \r
- =============================================================================== \r
- */\r
-\r
-/** \r
- * @brief Communication start\r
- * \r
- * After sending the START condition (I2C_GenerateSTART() function) the master \r
- * has to wait for this event. It means that the Start condition has been correctly \r
- * released on the I2C bus (the bus is free, no other devices is communicating).\r
- * \r
- */\r
-/* --EV5 */\r
-#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */\r
-\r
-/** \r
- * @brief Address Acknowledge\r
- * \r
- * After checking on EV5 (start condition correctly released on the bus), the \r
- * master sends the address of the slave(s) with which it will communicate \r
- * (I2C_Send7bitAddress() function, it also determines the direction of the communication: \r
- * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges \r
- * his address. If an acknowledge is sent on the bus, one of the following events will \r
- * be set:\r
- * \r
- * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED \r
- * event is set.\r
- * \r
- * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED \r
- * is set\r
- * \r
- * 3) In case of 10-Bit addressing mode, the master (just after generating the START \r
- * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() \r
- * function). Then master should wait on EV9. It means that the 10-bit addressing \r
- * header has been correctly sent on the bus. Then master should send the second part of \r
- * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master \r
- * should wait for event EV6. \r
- * \r
- */\r
-\r
-/* --EV6 */\r
-#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */\r
-#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */\r
-/* --EV9 */\r
-#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */\r
-\r
-/** \r
- * @brief Communication events\r
- * \r
- * If a communication is established (START condition generated and slave address \r
- * acknowledged) then the master has to check on one of the following events for \r
- * communication procedures:\r
- * \r
- * 1) Master Receiver mode: The master has to wait on the event EV7 then to read \r
- * the data received from the slave (I2C_ReceiveData() function).\r
- * \r
- * 2) Master Transmitter mode: The master has to send data (I2C_SendData() \r
- * function) then to wait on event EV8 or EV8_2.\r
- * These two events are similar: \r
- * - EV8 means that the data has been written in the data register and is \r
- * being shifted out.\r
- * - EV8_2 means that the data has been physically shifted out and output \r
- * on the bus.\r
- * In most cases, using EV8 is sufficient for the application.\r
- * Using EV8_2 leads to a slower communication but ensure more reliable test.\r
- * EV8_2 is also more suitable than EV8 for testing on the last data transmission \r
- * (before Stop condition generation).\r
- * \r
- * @note In case the user software does not guarantee that this event EV7 is \r
- * managed before the current byte end of transfer, then user may check on EV7 \r
- * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
- * In this case the communication may be slower.\r
- * \r
- */\r
-\r
-/* Master RECEIVER mode -----------------------------*/ \r
-/* --EV7 */\r
-#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */\r
-\r
-/* Master TRANSMITTER mode --------------------------*/\r
-/* --EV8 */\r
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */\r
-/* --EV8_2 */\r
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */\r
-\r
-\r
-/**\r
- ===============================================================================\r
- I2C Slave Events (Events grouped in order of communication) \r
- =============================================================================== \r
- */\r
-\r
-\r
-/** \r
- * @brief Communication start events\r
- * \r
- * Wait on one of these events at the start of the communication. It means that \r
- * the I2C peripheral detected a Start condition on the bus (generated by master \r
- * device) followed by the peripheral address. The peripheral generates an ACK \r
- * condition on the bus (if the acknowledge feature is enabled through function \r
- * I2C_AcknowledgeConfig()) and the events listed above are set :\r
- * \r
- * 1) In normal case (only one address managed by the slave), when the address \r
- * sent by the master matches the own address of the peripheral (configured by \r
- * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set \r
- * (where XXX could be TRANSMITTER or RECEIVER).\r
- * \r
- * 2) In case the address sent by the master matches the second address of the \r
- * peripheral (configured by the function I2C_OwnAddress2Config() and enabled \r
- * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED \r
- * (where XXX could be TRANSMITTER or RECEIVER) are set.\r
- * \r
- * 3) In case the address sent by the master is General Call (address 0x00) and \r
- * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) \r
- * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. \r
- * \r
- */\r
-\r
-/* --EV1 (all the events below are variants of EV1) */ \r
-/* 1) Case of One Single Address managed by the slave */\r
-#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */\r
-#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */\r
-\r
-/* 2) Case of Dual address managed by the slave */\r
-#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */\r
-#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */\r
-\r
-/* 3) Case of General Call enabled for the slave */\r
-#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */\r
-\r
-/** \r
- * @brief Communication events\r
- * \r
- * Wait on one of these events when EV1 has already been checked and: \r
- * \r
- * - Slave RECEIVER mode:\r
- * - EV2: When the application is expecting a data byte to be received. \r
- * - EV4: When the application is expecting the end of the communication: master \r
- * sends a stop condition and data transmission is stopped.\r
- * \r
- * - Slave Transmitter mode:\r
- * - EV3: When a byte has been transmitted by the slave and the application is expecting \r
- * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and\r
- * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be \r
- * used when the user software doesn't guarantee the EV3 is managed before the\r
- * current byte end of transfer.\r
- * - EV3_2: When the master sends a NACK in order to tell slave that data transmission \r
- * shall end (before sending the STOP condition). In this case slave has to stop sending \r
- * data bytes and expect a Stop condition on the bus.\r
- * \r
- * @note In case the user software does not guarantee that the event EV2 is \r
- * managed before the current byte end of transfer, then user may check on EV2 \r
- * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
- * In this case the communication may be slower.\r
- *\r
- */\r
-\r
-/* Slave RECEIVER mode --------------------------*/ \r
-/* --EV2 */\r
-#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */\r
-/* --EV4 */\r
-#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */\r
-\r
-/* Slave TRANSMITTER mode -----------------------*/\r
-/* --EV3 */\r
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */\r
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */\r
-/* --EV3_2 */\r
-#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */\r
-\r
-/**\r
- ===============================================================================\r
- End of Events Description \r
- =============================================================================== \r
- */\r
-\r
-#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \\r
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \\r
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \\r
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \\r
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \\r
- ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \\r
- ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_own_address1 \r
- * @{\r
- */\r
-\r
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_clock_speed \r
- * @{\r
- */\r
-\r
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-/* Function used to set the I2C configuration to the default reset state *****/\r
-void I2C_DeInit(I2C_TypeDef* I2Cx);\r
-\r
-/* Initialization and Configuration functions *********************************/\r
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);\r
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);\r
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);\r
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);\r
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);\r
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);\r
-\r
-/* Data transfers functions ***************************************************/ \r
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);\r
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);\r
-\r
-/* PEC management functions ***************************************************/ \r
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);\r
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);\r
-\r
-/* DMA transfers management functions *****************************************/\r
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-\r
-\r
-/* Interrupts, events and flags management functions **************************/\r
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);\r
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);\r
-\r
-/**\r
- * @brief\r
- * \r
-@verbatim \r
- ===============================================================================\r
- I2C State Monitoring Functions \r
- =============================================================================== \r
- This I2C driver provides three different ways for I2C state monitoring\r
- depending on the application requirements and constraints:\r
- \r
- \r
- 1. Basic state monitoring (Using I2C_CheckEvent() function)\r
- -----------------------------------------------------------\r
- It compares the status registers (SR1 and SR2) content to a given event\r
- (can be the combination of one or more flags).\r
- It returns SUCCESS if the current status includes the given flags \r
- and returns ERROR if one or more flags are missing in the current status.\r
-\r
- - When to use\r
- - This function is suitable for most applications as well as for startup \r
- activity since the events are fully described in the product reference \r
- manual (RM0038).\r
- - It is also suitable for users who need to define their own events.\r
-\r
- - Limitations\r
- - If an error occurs (ie. error flags are set besides to the monitored \r
- flags), the I2C_CheckEvent() function may return SUCCESS despite \r
- the communication hold or corrupted real state. \r
- In this case, it is advised to use error interrupts to monitor \r
- the error events and handle them in the interrupt IRQ handler.\r
- \r
- @note \r
- For error management, it is advised to use the following functions:\r
- - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
- - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.\r
- Where x is the peripheral instance (I2C1, I2C2 ...)\r
- - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the \r
- I2Cx_ER_IRQHandler() function in order to determine which error occurred.\r
- - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() \r
- and/or I2C_GenerateStop() in order to clear the error flag and source \r
- and return to correct communciation status.\r
- \r
- \r
- 2. Advanced state monitoring (Using the function I2C_GetLastEvent())\r
- -------------------------------------------------------------------- \r
- Using the function I2C_GetLastEvent() which returns the image of both status \r
- registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
- by 16 bits and concatenated to Status Register 1).\r
-\r
- - When to use\r
- - This function is suitable for the same applications above but it \r
- allows to overcome the mentioned limitation of I2C_GetFlagStatus() \r
- function.\r
- - The returned value could be compared to events already defined in \r
- the library (stm32l1xx_i2c.h) or to custom values defined by user.\r
- This function is suitable when multiple flags are monitored at the \r
- same time.\r
- - At the opposite of I2C_CheckEvent() function, this function allows \r
- user to choose when an event is accepted (when all events flags are \r
- set and no other flags are set or just when the needed flags are set \r
- like I2C_CheckEvent() function.\r
-\r
- - Limitations\r
- - User may need to define his own events.\r
- - Same remark concerning the error management is applicable for this \r
- function if user decides to check only regular communication flags \r
- (and ignores error flags).\r
- \r
- \r
- 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())\r
- -----------------------------------------------------------------------\r
- \r
- Using the function I2C_GetFlagStatus() which simply returns the status of \r
- one single flag (ie. I2C_FLAG_RXNE ...). \r
-\r
- - When to use\r
- - This function could be used for specific applications or in debug \r
- phase.\r
- - It is suitable when only one flag checking is needed (most I2C \r
- events are monitored through multiple flags).\r
- - Limitations: \r
- - When calling this function, the Status register is accessed. \r
- Some flags are cleared when the status register is accessed. \r
- So checking the status of one Flag, may clear other ones.\r
- - Function may need to be called twice or more in order to monitor \r
- one single event.\r
- \r
- For detailed description of Events, please refer to section I2C_Events in \r
- stm32l1xx_i2c.h file.\r
- \r
-@endverbatim\r
- * \r
- */\r
-\r
-/**\r
- ===============================================================================\r
- 1. Basic state monitoring \r
- =============================================================================== \r
- */\r
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);\r
-/**\r
- ===============================================================================\r
- 2. Advanced state monitoring \r
- =============================================================================== \r
- */\r
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);\r
-/**\r
- ===============================================================================\r
- 3. Flag-based state monitoring \r
- =============================================================================== \r
- */\r
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
-\r
-\r
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_I2C_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_iwdg.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the IWDG \r
- * firmware library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_IWDG_H\r
-#define __STM32L1xx_IWDG_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup IWDG\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup IWDG_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup IWDG_WriteAccess\r
- * @{\r
- */\r
-\r
-#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)\r
-#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)\r
-#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \\r
- ((ACCESS) == IWDG_WriteAccess_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_prescaler \r
- * @{\r
- */\r
-\r
-#define IWDG_Prescaler_4 ((uint8_t)0x00)\r
-#define IWDG_Prescaler_8 ((uint8_t)0x01)\r
-#define IWDG_Prescaler_16 ((uint8_t)0x02)\r
-#define IWDG_Prescaler_32 ((uint8_t)0x03)\r
-#define IWDG_Prescaler_64 ((uint8_t)0x04)\r
-#define IWDG_Prescaler_128 ((uint8_t)0x05)\r
-#define IWDG_Prescaler_256 ((uint8_t)0x06)\r
-#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \\r
- ((PRESCALER) == IWDG_Prescaler_8) || \\r
- ((PRESCALER) == IWDG_Prescaler_16) || \\r
- ((PRESCALER) == IWDG_Prescaler_32) || \\r
- ((PRESCALER) == IWDG_Prescaler_64) || \\r
- ((PRESCALER) == IWDG_Prescaler_128)|| \\r
- ((PRESCALER) == IWDG_Prescaler_256))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Flag \r
- * @{\r
- */\r
-\r
-#define IWDG_FLAG_PVU ((uint16_t)0x0001)\r
-#define IWDG_FLAG_RVU ((uint16_t)0x0002)\r
-#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))\r
-#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-/* Prescaler and Counter configuration functions ******************************/\r
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);\r
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);\r
-void IWDG_SetReload(uint16_t Reload);\r
-void IWDG_ReloadCounter(void);\r
-\r
-/* IWDG activation function ***************************************************/\r
-void IWDG_Enable(void);\r
-\r
-/* Flag management function ***************************************************/\r
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L1xx_IWDG_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_lcd.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the LCD firmware \r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_LCD_H\r
-#define __STM32L1xx_LCD_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup LCD\r
- * @{\r
- */ \r
-\r
-/* Exported types ------------------------------------------------------------*/\r
- \r
-/** \r
- * @brief LCD Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t LCD_Prescaler; /*!< Configures the LCD Prescaler. \r
- This parameter can be one value of @ref LCD_Prescaler */\r
- uint32_t LCD_Divider; /*!< Configures the LCD Divider.\r
- This parameter can be one value of @ref LCD_Divider */\r
- uint32_t LCD_Duty; /*!< Configures the LCD Duty.\r
- This parameter can be one value of @ref LCD_Duty */\r
- uint32_t LCD_Bias; /*!< Configures the LCD Bias.\r
- This parameter can be one value of @ref LCD_Bias */ \r
- uint32_t LCD_VoltageSource; /*!< Selects the LCD Voltage source.\r
- This parameter can be one value of @ref LCD_Voltage_Source */\r
-}LCD_InitTypeDef;\r
-\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup LCD_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup LCD_Prescaler \r
- * @{\r
- */\r
-\r
-#define LCD_Prescaler_1 ((uint32_t)0x00000000) /*!< CLKPS = LCDCLK */\r
-#define LCD_Prescaler_2 ((uint32_t)0x00400000) /*!< CLKPS = LCDCLK/2 */\r
-#define LCD_Prescaler_4 ((uint32_t)0x00800000) /*!< CLKPS = LCDCLK/4 */\r
-#define LCD_Prescaler_8 ((uint32_t)0x00C00000) /*!< CLKPS = LCDCLK/8 */\r
-#define LCD_Prescaler_16 ((uint32_t)0x01000000) /*!< CLKPS = LCDCLK/16 */\r
-#define LCD_Prescaler_32 ((uint32_t)0x01400000) /*!< CLKPS = LCDCLK/32 */\r
-#define LCD_Prescaler_64 ((uint32_t)0x01800000) /*!< CLKPS = LCDCLK/64 */\r
-#define LCD_Prescaler_128 ((uint32_t)0x01C00000) /*!< CLKPS = LCDCLK/128 */\r
-#define LCD_Prescaler_256 ((uint32_t)0x02000000) /*!< CLKPS = LCDCLK/256 */\r
-#define LCD_Prescaler_512 ((uint32_t)0x02400000) /*!< CLKPS = LCDCLK/512 */\r
-#define LCD_Prescaler_1024 ((uint32_t)0x02800000) /*!< CLKPS = LCDCLK/1024 */\r
-#define LCD_Prescaler_2048 ((uint32_t)0x02C00000) /*!< CLKPS = LCDCLK/2048 */\r
-#define LCD_Prescaler_4096 ((uint32_t)0x03000000) /*!< CLKPS = LCDCLK/4096 */\r
-#define LCD_Prescaler_8192 ((uint32_t)0x03400000) /*!< CLKPS = LCDCLK/8192 */\r
-#define LCD_Prescaler_16384 ((uint32_t)0x03800000) /*!< CLKPS = LCDCLK/16384 */\r
-#define LCD_Prescaler_32768 ((uint32_t)0x03C00000) /*!< CLKPS = LCDCLK/32768 */\r
-\r
-#define IS_LCD_PRESCALER(PRESCALER) (((PRESCALER) == LCD_Prescaler_1) || \\r
- ((PRESCALER) == LCD_Prescaler_2) || \\r
- ((PRESCALER) == LCD_Prescaler_4) || \\r
- ((PRESCALER) == LCD_Prescaler_8) || \\r
- ((PRESCALER) == LCD_Prescaler_16) || \\r
- ((PRESCALER) == LCD_Prescaler_32) || \\r
- ((PRESCALER) == LCD_Prescaler_64) || \\r
- ((PRESCALER) == LCD_Prescaler_128) || \\r
- ((PRESCALER) == LCD_Prescaler_256) || \\r
- ((PRESCALER) == LCD_Prescaler_512) || \\r
- ((PRESCALER) == LCD_Prescaler_1024) || \\r
- ((PRESCALER) == LCD_Prescaler_2048) || \\r
- ((PRESCALER) == LCD_Prescaler_4096) || \\r
- ((PRESCALER) == LCD_Prescaler_8192) || \\r
- ((PRESCALER) == LCD_Prescaler_16384) || \\r
- ((PRESCALER) == LCD_Prescaler_32768))\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup LCD_Divider \r
- * @{\r
- */\r
-\r
-#define LCD_Divider_16 ((uint32_t)0x00000000) /*!< LCD frequency = CLKPS/16 */\r
-#define LCD_Divider_17 ((uint32_t)0x00040000) /*!< LCD frequency = CLKPS/17 */\r
-#define LCD_Divider_18 ((uint32_t)0x00080000) /*!< LCD frequency = CLKPS/18 */\r
-#define LCD_Divider_19 ((uint32_t)0x000C0000) /*!< LCD frequency = CLKPS/19 */\r
-#define LCD_Divider_20 ((uint32_t)0x00100000) /*!< LCD frequency = CLKPS/20 */\r
-#define LCD_Divider_21 ((uint32_t)0x00140000) /*!< LCD frequency = CLKPS/21 */\r
-#define LCD_Divider_22 ((uint32_t)0x00180000) /*!< LCD frequency = CLKPS/22 */\r
-#define LCD_Divider_23 ((uint32_t)0x001C0000) /*!< LCD frequency = CLKPS/23 */\r
-#define LCD_Divider_24 ((uint32_t)0x00200000) /*!< LCD frequency = CLKPS/24 */\r
-#define LCD_Divider_25 ((uint32_t)0x00240000) /*!< LCD frequency = CLKPS/25 */\r
-#define LCD_Divider_26 ((uint32_t)0x00280000) /*!< LCD frequency = CLKPS/26 */\r
-#define LCD_Divider_27 ((uint32_t)0x002C0000) /*!< LCD frequency = CLKPS/27 */\r
-#define LCD_Divider_28 ((uint32_t)0x00300000) /*!< LCD frequency = CLKPS/28 */\r
-#define LCD_Divider_29 ((uint32_t)0x00340000) /*!< LCD frequency = CLKPS/29 */\r
-#define LCD_Divider_30 ((uint32_t)0x00380000) /*!< LCD frequency = CLKPS/30 */\r
-#define LCD_Divider_31 ((uint32_t)0x003C0000) /*!< LCD frequency = CLKPS/31 */\r
-\r
-#define IS_LCD_DIVIDER(DIVIDER) (((DIVIDER) == LCD_Divider_16) || \\r
- ((DIVIDER) == LCD_Divider_17) || \\r
- ((DIVIDER) == LCD_Divider_18) || \\r
- ((DIVIDER) == LCD_Divider_19) || \\r
- ((DIVIDER) == LCD_Divider_20) || \\r
- ((DIVIDER) == LCD_Divider_21) || \\r
- ((DIVIDER) == LCD_Divider_22) || \\r
- ((DIVIDER) == LCD_Divider_23) || \\r
- ((DIVIDER) == LCD_Divider_24) || \\r
- ((DIVIDER) == LCD_Divider_25) || \\r
- ((DIVIDER) == LCD_Divider_26) || \\r
- ((DIVIDER) == LCD_Divider_27) || \\r
- ((DIVIDER) == LCD_Divider_28) || \\r
- ((DIVIDER) == LCD_Divider_29) || \\r
- ((DIVIDER) == LCD_Divider_30) || \\r
- ((DIVIDER) == LCD_Divider_31))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup LCD_Duty \r
- * @{\r
- */\r
- \r
-#define LCD_Duty_Static ((uint32_t)0x00000000) /*!< Static duty */\r
-#define LCD_Duty_1_2 ((uint32_t)0x00000004) /*!< 1/2 duty */\r
-#define LCD_Duty_1_3 ((uint32_t)0x00000008) /*!< 1/3 duty */\r
-#define LCD_Duty_1_4 ((uint32_t)0x0000000C) /*!< 1/4 duty */\r
-#define LCD_Duty_1_8 ((uint32_t)0x00000010) /*!< 1/4 duty */\r
-\r
-#define IS_LCD_DUTY(DUTY) (((DUTY) == LCD_Duty_Static) || \\r
- ((DUTY) == LCD_Duty_1_2) || \\r
- ((DUTY) == LCD_Duty_1_3) || \\r
- ((DUTY) == LCD_Duty_1_4) || \\r
- ((DUTY) == LCD_Duty_1_8))\r
-\r
-/**\r
- * @}\r
- */ \r
- \r
-\r
-/** @defgroup LCD_Bias \r
- * @{\r
- */\r
- \r
-#define LCD_Bias_1_4 ((uint32_t)0x00000000) /*!< 1/4 Bias */\r
-#define LCD_Bias_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */\r
-#define LCD_Bias_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */\r
-\r
-#define IS_LCD_BIAS(BIAS) (((BIAS) == LCD_Bias_1_4) || \\r
- ((BIAS) == LCD_Bias_1_2) || \\r
- ((BIAS) == LCD_Bias_1_3))\r
-/**\r
- * @}\r
- */ \r
- \r
-/** @defgroup LCD_Voltage_Source \r
- * @{\r
- */\r
- \r
-#define LCD_VoltageSource_Internal ((uint32_t)0x00000000) /*!< Internal voltage source for the LCD */\r
-#define LCD_VoltageSource_External LCD_CR_VSEL /*!< External voltage source for the LCD */\r
-\r
-#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VoltageSource_Internal) || \\r
- ((SOURCE) == LCD_VoltageSource_External))\r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup LCD_Interrupts \r
- * @{\r
- */\r
-#define LCD_IT_SOF LCD_FCR_SOFIE\r
-#define LCD_IT_UDD LCD_FCR_UDDIE\r
-\r
-#define IS_LCD_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF5) == 0x00) && ((IT) != 0x00))\r
-\r
-#define IS_LCD_GET_IT(IT) (((IT) == LCD_IT_SOF) || ((IT) == LCD_IT_UDD))\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup LCD_PulseOnDuration \r
- * @{\r
- */\r
-\r
-#define LCD_PulseOnDuration_0 ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse */\r
-#define LCD_PulseOnDuration_1 ((uint32_t)0x00000010) /*!< Pulse ON duration = 1/CK_PS */\r
-#define LCD_PulseOnDuration_2 ((uint32_t)0x00000020) /*!< Pulse ON duration = 2/CK_PS */\r
-#define LCD_PulseOnDuration_3 ((uint32_t)0x00000030) /*!< Pulse ON duration = 3/CK_PS */\r
-#define LCD_PulseOnDuration_4 ((uint32_t)0x00000040) /*!< Pulse ON duration = 4/CK_PS */\r
-#define LCD_PulseOnDuration_5 ((uint32_t)0x00000050) /*!< Pulse ON duration = 5/CK_PS */\r
-#define LCD_PulseOnDuration_6 ((uint32_t)0x00000060) /*!< Pulse ON duration = 6/CK_PS */\r
-#define LCD_PulseOnDuration_7 ((uint32_t)0x00000070) /*!< Pulse ON duration = 7/CK_PS */\r
-\r
-#define IS_LCD_PULSE_ON_DURATION(DURATION) (((DURATION) == LCD_PulseOnDuration_0) || \\r
- ((DURATION) == LCD_PulseOnDuration_1) || \\r
- ((DURATION) == LCD_PulseOnDuration_2) || \\r
- ((DURATION) == LCD_PulseOnDuration_3) || \\r
- ((DURATION) == LCD_PulseOnDuration_4) || \\r
- ((DURATION) == LCD_PulseOnDuration_5) || \\r
- ((DURATION) == LCD_PulseOnDuration_6) || \\r
- ((DURATION) == LCD_PulseOnDuration_7))\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup LCD_DeadTime \r
- * @{\r
- */\r
-\r
-#define LCD_DeadTime_0 ((uint32_t)0x00000000) /*!< No dead Time */\r
-#define LCD_DeadTime_1 ((uint32_t)0x00000080) /*!< One Phase between different couple of Frame */\r
-#define LCD_DeadTime_2 ((uint32_t)0x00000100) /*!< Two Phase between different couple of Frame */\r
-#define LCD_DeadTime_3 ((uint32_t)0x00000180) /*!< Three Phase between different couple of Frame */\r
-#define LCD_DeadTime_4 ((uint32_t)0x00000200) /*!< Four Phase between different couple of Frame */\r
-#define LCD_DeadTime_5 ((uint32_t)0x00000280) /*!< Five Phase between different couple of Frame */\r
-#define LCD_DeadTime_6 ((uint32_t)0x00000300) /*!< Six Phase between different couple of Frame */\r
-#define LCD_DeadTime_7 ((uint32_t)0x00000380) /*!< Seven Phase between different couple of Frame */\r
-\r
-#define IS_LCD_DEAD_TIME(TIME) (((TIME) == LCD_DeadTime_0) || \\r
- ((TIME) == LCD_DeadTime_1) || \\r
- ((TIME) == LCD_DeadTime_2) || \\r
- ((TIME) == LCD_DeadTime_3) || \\r
- ((TIME) == LCD_DeadTime_4) || \\r
- ((TIME) == LCD_DeadTime_5) || \\r
- ((TIME) == LCD_DeadTime_6) || \\r
- ((TIME) == LCD_DeadTime_7))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup LCD_BlinkMode \r
- * @{\r
- */\r
-\r
-#define LCD_BlinkMode_Off ((uint32_t)0x00000000) /*!< Blink disabled */\r
-#define LCD_BlinkMode_SEG0_COM0 ((uint32_t)0x00010000) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */\r
-#define LCD_BlinkMode_SEG0_AllCOM ((uint32_t)0x00020000) /*!< Blink enabled on SEG[0], all COM (up to \r
- 8 pixels according to the programmed duty) */\r
-#define LCD_BlinkMode_AllSEG_AllCOM ((uint32_t)0x00030000) /*!< Blink enabled on all SEG and all COM (all pixels) */\r
-\r
-#define IS_LCD_BLINK_MODE(MODE) (((MODE) == LCD_BlinkMode_Off) || \\r
- ((MODE) == LCD_BlinkMode_SEG0_COM0) || \\r
- ((MODE) == LCD_BlinkMode_SEG0_AllCOM) || \\r
- ((MODE) == LCD_BlinkMode_AllSEG_AllCOM))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup LCD_BlinkFrequency \r
- * @{\r
- */\r
-\r
-#define LCD_BlinkFrequency_Div8 ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8 */\r
-#define LCD_BlinkFrequency_Div16 ((uint32_t)0x00002000) /*!< The Blink frequency = fLCD/16 */\r
-#define LCD_BlinkFrequency_Div32 ((uint32_t)0x00004000) /*!< The Blink frequency = fLCD/32 */\r
-#define LCD_BlinkFrequency_Div64 ((uint32_t)0x00006000) /*!< The Blink frequency = fLCD/64 */\r
-#define LCD_BlinkFrequency_Div128 ((uint32_t)0x00008000) /*!< The Blink frequency = fLCD/128 */\r
-#define LCD_BlinkFrequency_Div256 ((uint32_t)0x0000A000) /*!< The Blink frequency = fLCD/256 */\r
-#define LCD_BlinkFrequency_Div512 ((uint32_t)0x0000C000) /*!< The Blink frequency = fLCD/512 */\r
-#define LCD_BlinkFrequency_Div1024 ((uint32_t)0x0000E000) /*!< The Blink frequency = fLCD/1024 */\r
-\r
-#define IS_LCD_BLINK_FREQUENCY(FREQUENCY) (((FREQUENCY) == LCD_BlinkFrequency_Div8) || \\r
- ((FREQUENCY) == LCD_BlinkFrequency_Div16) || \\r
- ((FREQUENCY) == LCD_BlinkFrequency_Div32) || \\r
- ((FREQUENCY) == LCD_BlinkFrequency_Div64) || \\r
- ((FREQUENCY) == LCD_BlinkFrequency_Div128) || \\r
- ((FREQUENCY) == LCD_BlinkFrequency_Div256) || \\r
- ((FREQUENCY) == LCD_BlinkFrequency_Div512) || \\r
- ((FREQUENCY) == LCD_BlinkFrequency_Div1024))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup LCD_Contrast \r
- * @{\r
- */\r
-\r
-#define LCD_Contrast_Level_0 ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V */\r
-#define LCD_Contrast_Level_1 ((uint32_t)0x00000400) /*!< Maximum Voltage = 2.73V */\r
-#define LCD_Contrast_Level_2 ((uint32_t)0x00000800) /*!< Maximum Voltage = 2.86V */\r
-#define LCD_Contrast_Level_3 ((uint32_t)0x00000C00) /*!< Maximum Voltage = 2.99V */\r
-#define LCD_Contrast_Level_4 ((uint32_t)0x00001000) /*!< Maximum Voltage = 3.12V */\r
-#define LCD_Contrast_Level_5 ((uint32_t)0x00001400) /*!< Maximum Voltage = 3.25V */\r
-#define LCD_Contrast_Level_6 ((uint32_t)0x00001800) /*!< Maximum Voltage = 3.38V */\r
-#define LCD_Contrast_Level_7 ((uint32_t)0x00001C00) /*!< Maximum Voltage = 3.51V */\r
-\r
-#define IS_LCD_CONTRAST(CONTRAST) (((CONTRAST) == LCD_Contrast_Level_0) || \\r
- ((CONTRAST) == LCD_Contrast_Level_1) || \\r
- ((CONTRAST) == LCD_Contrast_Level_2) || \\r
- ((CONTRAST) == LCD_Contrast_Level_3) || \\r
- ((CONTRAST) == LCD_Contrast_Level_4) || \\r
- ((CONTRAST) == LCD_Contrast_Level_5) || \\r
- ((CONTRAST) == LCD_Contrast_Level_6) || \\r
- ((CONTRAST) == LCD_Contrast_Level_7))\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup LCD_Flag \r
- * @{\r
- */\r
-\r
-#define LCD_FLAG_ENS LCD_SR_ENS\r
-#define LCD_FLAG_SOF LCD_SR_SOF\r
-#define LCD_FLAG_UDR LCD_SR_UDR\r
-#define LCD_FLAG_UDD LCD_SR_UDD\r
-#define LCD_FLAG_RDY LCD_SR_RDY\r
-#define LCD_FLAG_FCRSF LCD_SR_FCRSR\r
-\r
-#define IS_LCD_GET_FLAG(FLAG) (((FLAG) == LCD_FLAG_ENS) || ((FLAG) == LCD_FLAG_SOF) || \\r
- ((FLAG) == LCD_FLAG_UDR) || ((FLAG) == LCD_FLAG_UDD) || \\r
- ((FLAG) == LCD_FLAG_RDY) || ((FLAG) == LCD_FLAG_FCRSF))\r
-\r
-#define IS_LCD_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF5) == 0x00) && ((FLAG) != 0x00))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup LCD_RAMRegister \r
- * @{\r
- */\r
-\r
-#define LCD_RAMRegister_0 ((uint32_t)0x00000000) /*!< LCD RAM Register 0 */\r
-#define LCD_RAMRegister_1 ((uint32_t)0x00000001) /*!< LCD RAM Register 1 */\r
-#define LCD_RAMRegister_2 ((uint32_t)0x00000002) /*!< LCD RAM Register 2 */\r
-#define LCD_RAMRegister_3 ((uint32_t)0x00000003) /*!< LCD RAM Register 3 */\r
-#define LCD_RAMRegister_4 ((uint32_t)0x00000004) /*!< LCD RAM Register 4 */\r
-#define LCD_RAMRegister_5 ((uint32_t)0x00000005) /*!< LCD RAM Register 5 */\r
-#define LCD_RAMRegister_6 ((uint32_t)0x00000006) /*!< LCD RAM Register 6 */\r
-#define LCD_RAMRegister_7 ((uint32_t)0x00000007) /*!< LCD RAM Register 7 */\r
-#define LCD_RAMRegister_8 ((uint32_t)0x00000008) /*!< LCD RAM Register 8 */\r
-#define LCD_RAMRegister_9 ((uint32_t)0x00000009) /*!< LCD RAM Register 9 */\r
-#define LCD_RAMRegister_10 ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */\r
-#define LCD_RAMRegister_11 ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */\r
-#define LCD_RAMRegister_12 ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */\r
-#define LCD_RAMRegister_13 ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */\r
-#define LCD_RAMRegister_14 ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */\r
-#define LCD_RAMRegister_15 ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */\r
-\r
-#define IS_LCD_RAM_REGISTER(REGISTER) (((REGISTER) == LCD_RAMRegister_0) || \\r
- ((REGISTER) == LCD_RAMRegister_1) || \\r
- ((REGISTER) == LCD_RAMRegister_2) || \\r
- ((REGISTER) == LCD_RAMRegister_3) || \\r
- ((REGISTER) == LCD_RAMRegister_4) || \\r
- ((REGISTER) == LCD_RAMRegister_5) || \\r
- ((REGISTER) == LCD_RAMRegister_6) || \\r
- ((REGISTER) == LCD_RAMRegister_7) || \\r
- ((REGISTER) == LCD_RAMRegister_8) || \\r
- ((REGISTER) == LCD_RAMRegister_9) || \\r
- ((REGISTER) == LCD_RAMRegister_10) || \\r
- ((REGISTER) == LCD_RAMRegister_11) || \\r
- ((REGISTER) == LCD_RAMRegister_12) || \\r
- ((REGISTER) == LCD_RAMRegister_13) || \\r
- ((REGISTER) == LCD_RAMRegister_14) || \\r
- ((REGISTER) == LCD_RAMRegister_15))\r
-\r
-/**\r
- * @}\r
- */ \r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-/* Function used to set the LCD configuration to the default reset state *****/\r
-void LCD_DeInit(void);\r
-\r
-/* Initialization and Configuration functions *********************************/\r
-void LCD_Init(LCD_InitTypeDef* LCD_InitStruct);\r
-void LCD_StructInit(LCD_InitTypeDef* LCD_InitStruct);\r
-void LCD_Cmd(FunctionalState NewState);\r
-void LCD_WaitForSynchro(void);\r
-void LCD_HighDriveCmd(FunctionalState NewState);\r
-void LCD_MuxSegmentCmd(FunctionalState NewState);\r
-void LCD_PulseOnDurationConfig(uint32_t LCD_PulseOnDuration);\r
-void LCD_DeadTimeConfig(uint32_t LCD_DeadTime);\r
-void LCD_BlinkConfig(uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency);\r
-void LCD_ContrastConfig(uint32_t LCD_Contrast);\r
-\r
-/* LCD RAM memory write functions *********************************************/\r
-void LCD_Write(uint32_t LCD_RAMRegister, uint32_t LCD_Data);\r
-void LCD_UpdateDisplayRequest(void);\r
-\r
-/* Interrupts and flags management functions **********************************/\r
-void LCD_ITConfig(uint32_t LCD_IT, FunctionalState NewState);\r
-FlagStatus LCD_GetFlagStatus(uint32_t LCD_FLAG);\r
-void LCD_ClearFlag(uint32_t LCD_FLAG);\r
-ITStatus LCD_GetITStatus(uint32_t LCD_IT);\r
-void LCD_ClearITPendingBit(uint32_t LCD_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L1xx_LCD_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_pwr.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the PWR firmware \r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_PWR_H\r
-#define __STM32L1xx_PWR_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup PWR\r
- * @{\r
- */ \r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup PWR_Exported_Constants\r
- * @{\r
- */ \r
-\r
-/** @defgroup PVD_detection_level \r
- * @{\r
- */ \r
-\r
-#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0\r
-#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1\r
-#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2\r
-#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3\r
-#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4\r
-#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5\r
-#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6\r
-#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 /* External input analog voltage \r
- (Compare internally to VREFINT) */\r
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \\r
- ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \\r
- ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \\r
- ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup WakeUp_Pins \r
- * @{\r
- */\r
-\r
-#define PWR_WakeUpPin_1 ((uint32_t)0x00000000)\r
-#define PWR_WakeUpPin_2 ((uint32_t)0x00000004)\r
-#define PWR_WakeUpPin_3 ((uint32_t)0x00000008)\r
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \\r
- ((PIN) == PWR_WakeUpPin_2) || \\r
- ((PIN) == PWR_WakeUpPin_3))\r
-/**\r
- * @}\r
- */\r
-\r
- \r
-/** @defgroup Voltage_Scaling_Ranges\r
- * @{\r
- */\r
-\r
-#define PWR_VoltageScaling_Range1 PWR_CR_VOS_0\r
-#define PWR_VoltageScaling_Range2 PWR_CR_VOS_1\r
-#define PWR_VoltageScaling_Range3 PWR_CR_VOS\r
-\r
-#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_VoltageScaling_Range1) || \\r
- ((RANGE) == PWR_VoltageScaling_Range2) || \\r
- ((RANGE) == PWR_VoltageScaling_Range3))\r
-/**\r
- * @}\r
- */ \r
- \r
-/** @defgroup Regulator_state_is_Sleep_STOP_mode \r
- * @{\r
- */\r
-\r
-#define PWR_Regulator_ON ((uint32_t)0x00000000)\r
-#define PWR_Regulator_LowPower PWR_CR_LPSDSR\r
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \\r
- ((REGULATOR) == PWR_Regulator_LowPower))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SLEEP_mode_entry \r
- * @{\r
- */\r
-\r
-#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)\r
-#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)\r
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))\r
- \r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup STOP_mode_entry \r
- * @{\r
- */\r
-\r
-#define PWR_STOPEntry_WFI ((uint8_t)0x01)\r
-#define PWR_STOPEntry_WFE ((uint8_t)0x02)\r
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Flag \r
- * @{\r
- */\r
-\r
-#define PWR_FLAG_WU PWR_CSR_WUF\r
-#define PWR_FLAG_SB PWR_CSR_SBF\r
-#define PWR_FLAG_PVDO PWR_CSR_PVDO\r
-#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF\r
-#define PWR_FLAG_VOS PWR_CSR_VOSF\r
-#define PWR_FLAG_REGLP PWR_CSR_REGLPF\r
-\r
-#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \\r
- ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \\r
- ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP))\r
-\r
-#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-/* Function used to set the PWR configuration to the default reset state ******/ \r
-void PWR_DeInit(void);\r
-\r
-/* RTC Domain Access function *************************************************/ \r
-void PWR_RTCAccessCmd(FunctionalState NewState);\r
-\r
-/* PVD configuration functions ************************************************/ \r
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);\r
-void PWR_PVDCmd(FunctionalState NewState);\r
-\r
-/* WakeUp pins configuration functions ****************************************/ \r
-void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);\r
-\r
-/* Ultra Low Power mode configuration functions *******************************/ \r
-void PWR_FastWakeUpCmd(FunctionalState NewState);\r
-void PWR_UltraLowPowerCmd(FunctionalState NewState);\r
-\r
-/* Voltage Scaling configuration functions ************************************/ \r
-void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling);\r
-\r
-/* Low Power modes configuration functions ************************************/ \r
-void PWR_EnterLowPowerRunMode(FunctionalState NewState);\r
-void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry);\r
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);\r
-void PWR_EnterSTANDBYMode(void);\r
-\r
-/* Flags management functions *************************************************/ \r
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);\r
-void PWR_ClearFlag(uint32_t PWR_FLAG);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L1xx_PWR_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_rcc.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the RCC \r
- * firmware library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_RCC_H\r
-#define __STM32L1xx_RCC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup RCC\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-typedef struct\r
-{\r
- uint32_t SYSCLK_Frequency;\r
- uint32_t HCLK_Frequency;\r
- uint32_t PCLK1_Frequency;\r
- uint32_t PCLK2_Frequency;\r
-}RCC_ClocksTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup RCC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup HSE_configuration \r
- * @{\r
- */\r
-\r
-#define RCC_HSE_OFF ((uint8_t)0x00)\r
-#define RCC_HSE_ON ((uint8_t)0x01)\r
-#define RCC_HSE_Bypass ((uint8_t)0x05)\r
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\r
- ((HSE) == RCC_HSE_Bypass))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup MSI_Clock_Range \r
- * @{\r
- */\r
-\r
-#define RCC_MSIRange_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */\r
-#define RCC_MSIRange_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */\r
-#define RCC_MSIRange_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */\r
-#define RCC_MSIRange_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */\r
-#define RCC_MSIRange_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */\r
-#define RCC_MSIRange_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */\r
-#define RCC_MSIRange_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */\r
-\r
-#define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_0) || \\r
- ((RANGE) == RCC_MSIRange_1) || \\r
- ((RANGE) == RCC_MSIRange_2) || \\r
- ((RANGE) == RCC_MSIRange_3) || \\r
- ((RANGE) == RCC_MSIRange_4) || \\r
- ((RANGE) == RCC_MSIRange_5) || \\r
- ((RANGE) == RCC_MSIRange_6))\r
-\r
-/**\r
- * @}\r
- */ \r
- \r
-/** @defgroup PLL_Clock_Source \r
- * @{\r
- */\r
-\r
-#define RCC_PLLSource_HSI ((uint8_t)0x00)\r
-#define RCC_PLLSource_HSE ((uint8_t)0x01)\r
-\r
-#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \\r
- ((SOURCE) == RCC_PLLSource_HSE))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup PLL_Multiplication_Factor \r
- * @{\r
- */\r
-\r
-#define RCC_PLLMul_3 ((uint8_t)0x00)\r
-#define RCC_PLLMul_4 ((uint8_t)0x04)\r
-#define RCC_PLLMul_6 ((uint8_t)0x08)\r
-#define RCC_PLLMul_8 ((uint8_t)0x0C)\r
-#define RCC_PLLMul_12 ((uint8_t)0x10)\r
-#define RCC_PLLMul_16 ((uint8_t)0x14)\r
-#define RCC_PLLMul_24 ((uint8_t)0x18)\r
-#define RCC_PLLMul_32 ((uint8_t)0x1C)\r
-#define RCC_PLLMul_48 ((uint8_t)0x20)\r
-\r
-\r
-#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || \\r
- ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_8) || \\r
- ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_16) || \\r
- ((MUL) == RCC_PLLMul_24) || ((MUL) == RCC_PLLMul_32) || \\r
- ((MUL) == RCC_PLLMul_48))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PLL_Divider_Factor \r
- * @{\r
- */\r
-\r
-#define RCC_PLLDiv_2 ((uint8_t)0x40)\r
-#define RCC_PLLDiv_3 ((uint8_t)0x80)\r
-#define RCC_PLLDiv_4 ((uint8_t)0xC0)\r
-\r
-\r
-#define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) || ((DIV) == RCC_PLLDiv_3) || \\r
- ((DIV) == RCC_PLLDiv_4))\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup System_Clock_Source \r
- * @{\r
- */\r
-\r
-#define RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI\r
-#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI\r
-#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE\r
-#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL\r
-#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) || \\r
- ((SOURCE) == RCC_SYSCLKSource_HSI) || \\r
- ((SOURCE) == RCC_SYSCLKSource_HSE) || \\r
- ((SOURCE) == RCC_SYSCLKSource_PLLCLK))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup AHB_Clock_Source\r
- * @{\r
- */\r
-\r
-#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1\r
-#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2\r
-#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4\r
-#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8\r
-#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16\r
-#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64\r
-#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128\r
-#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256\r
-#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512\r
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \\r
- ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \\r
- ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \\r
- ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \\r
- ((HCLK) == RCC_SYSCLK_Div512))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup APB1_APB2_Clock_Source\r
- * @{\r
- */\r
-\r
-#define RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1\r
-#define RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2\r
-#define RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4\r
-#define RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8\r
-#define RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16\r
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \\r
- ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \\r
- ((PCLK) == RCC_HCLK_Div16))\r
-/**\r
- * @}\r
- */\r
- \r
-\r
-/** @defgroup RCC_Interrupt_Source \r
- * @{\r
- */\r
-\r
-#define RCC_IT_LSIRDY ((uint8_t)0x01)\r
-#define RCC_IT_LSERDY ((uint8_t)0x02)\r
-#define RCC_IT_HSIRDY ((uint8_t)0x04)\r
-#define RCC_IT_HSERDY ((uint8_t)0x08)\r
-#define RCC_IT_PLLRDY ((uint8_t)0x10)\r
-#define RCC_IT_MSIRDY ((uint8_t)0x20)\r
-#define RCC_IT_CSS ((uint8_t)0x80)\r
-\r
-#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))\r
-\r
-#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \\r
- ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \\r
- ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \\r
- ((IT) == RCC_IT_CSS))\r
-\r
-#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup LSE_Configuration \r
- * @{\r
- */\r
-\r
-#define RCC_LSE_OFF ((uint8_t)0x00)\r
-#define RCC_LSE_ON ((uint8_t)0x01)\r
-#define RCC_LSE_Bypass ((uint8_t)0x05)\r
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\r
- ((LSE) == RCC_LSE_Bypass))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Clock_Source\r
- * @{\r
- */\r
-\r
-#define RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE\r
-#define RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI\r
-#define RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE\r
-#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)\r
-#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)\r
-#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)\r
-#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \\r
- ((SOURCE) == RCC_RTCCLKSource_LSI) || \\r
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \\r
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \\r
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \\r
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div16))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup AHB_Peripherals \r
- * @{\r
- */\r
-\r
-#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN\r
-#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN\r
-#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN\r
-#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN\r
-#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN\r
-#define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN\r
-#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN\r
-#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN\r
-#define RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN\r
-#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN\r
-\r
-#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFEFF6FC0) == 0x00) && ((PERIPH) != 0x00))\r
-#define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xFEFE6FC0) == 0x00) && ((PERIPH) != 0x00))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup APB2_Peripherals \r
- * @{\r
- */\r
-\r
-#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN\r
-#define RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN\r
-#define RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN\r
-#define RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN\r
-#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN\r
-#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN\r
-#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN\r
-\r
-#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFADE2) == 0x00) && ((PERIPH) != 0x00))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup APB1_Peripherals \r
- * @{\r
- */\r
-\r
-#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN\r
-#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN\r
-#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN\r
-#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN\r
-#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN\r
-#define RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN\r
-#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN\r
-#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN\r
-#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN\r
-#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN\r
-#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN\r
-#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN\r
-#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN\r
-#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN\r
-#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN\r
-#define RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN\r
-\r
-#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F19B5C8) == 0x00) && ((PERIPH) != 0x00))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MCO_Clock_Source\r
- * @{\r
- */\r
-\r
-#define RCC_MCOSource_NoClock ((uint8_t)0x00)\r
-#define RCC_MCOSource_SYSCLK ((uint8_t)0x01)\r
-#define RCC_MCOSource_HSI ((uint8_t)0x02)\r
-#define RCC_MCOSource_MSI ((uint8_t)0x03)\r
-#define RCC_MCOSource_HSE ((uint8_t)0x04)\r
-#define RCC_MCOSource_PLLCLK ((uint8_t)0x05)\r
-#define RCC_MCOSource_LSI ((uint8_t)0x06)\r
-#define RCC_MCOSource_LSE ((uint8_t)0x07)\r
-\r
-#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \\r
- ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_MSI) || \\r
- ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK) || \\r
- ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MCO_Output_Divider \r
- * @{\r
- */\r
-\r
-#define RCC_MCODiv_1 ((uint8_t)0x00)\r
-#define RCC_MCODiv_2 ((uint8_t)0x10)\r
-#define RCC_MCODiv_4 ((uint8_t)0x20)\r
-#define RCC_MCODiv_8 ((uint8_t)0x30)\r
-#define RCC_MCODiv_16 ((uint8_t)0x40)\r
-\r
-#define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) || ((DIV) == RCC_MCODiv_2) || \\r
- ((DIV) == RCC_MCODiv_4) || ((DIV) == RCC_MCODiv_8) || \\r
- ((DIV) == RCC_MCODiv_16))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RCC_Flag \r
- * @{\r
- */\r
-\r
-#define RCC_FLAG_HSIRDY ((uint8_t)0x21)\r
-#define RCC_FLAG_MSIRDY ((uint8_t)0x29)\r
-#define RCC_FLAG_HSERDY ((uint8_t)0x31)\r
-#define RCC_FLAG_PLLRDY ((uint8_t)0x39)\r
-#define RCC_FLAG_LSERDY ((uint8_t)0x49)\r
-#define RCC_FLAG_LSIRDY ((uint8_t)0x41)\r
-#define RCC_FLAG_OBLRST ((uint8_t)0x59)\r
-#define RCC_FLAG_PINRST ((uint8_t)0x5A)\r
-#define RCC_FLAG_PORRST ((uint8_t)0x5B)\r
-#define RCC_FLAG_SFTRST ((uint8_t)0x5C)\r
-#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)\r
-#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)\r
-#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)\r
-\r
-#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\r
- ((FLAG) == RCC_FLAG_MSIRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \\r
- ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || \\r
- ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \\r
- ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \\r
- ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \\r
- ((FLAG) == RCC_FLAG_WWDGRST))\r
-\r
-#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r
-#define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-/* Function used to set the RCC clock configuration to the default reset state */\r
-void RCC_DeInit(void);\r
-\r
-/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/\r
-void RCC_HSEConfig(uint8_t RCC_HSE);\r
-ErrorStatus RCC_WaitForHSEStartUp(void);\r
-void RCC_MSIRangeConfig(uint32_t RCC_MSIRange);\r
-void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue);\r
-void RCC_MSICmd(FunctionalState NewState);\r
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);\r
-void RCC_HSICmd(FunctionalState NewState);\r
-void RCC_LSEConfig(uint8_t RCC_LSE);\r
-void RCC_LSICmd(FunctionalState NewState);\r
-void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv);\r
-void RCC_PLLCmd(FunctionalState NewState);\r
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState);\r
-void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv);\r
-\r
-/* System, AHB and APB busses clocks configuration functions ******************/\r
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);\r
-uint8_t RCC_GetSYSCLKSource(void);\r
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK);\r
-void RCC_PCLK1Config(uint32_t RCC_HCLK);\r
-void RCC_PCLK2Config(uint32_t RCC_HCLK);\r
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);\r
-\r
-/* Peripheral clocks configuration functions **********************************/\r
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);\r
-void RCC_RTCCLKCmd(FunctionalState NewState);\r
-void RCC_RTCResetCmd(FunctionalState NewState);\r
-\r
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
-\r
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
-\r
-void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
-void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
-void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
-\r
-/* Interrupts and flags management functions **********************************/\r
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);\r
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);\r
-void RCC_ClearFlag(void);\r
-ITStatus RCC_GetITStatus(uint8_t RCC_IT);\r
-void RCC_ClearITPendingBit(uint8_t RCC_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L1xx_RCC_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_rtc.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the RTC firmware \r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_RTC_H\r
-#define __STM32L1xx_RTC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup RTC\r
- * @{\r
- */ \r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief RTC Init structures definition \r
- */ \r
-typedef struct\r
-{\r
- uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.\r
- This parameter can be a value of @ref RTC_Hour_Formats */\r
- \r
- uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.\r
- This parameter must be set to a value lower than 0x7F */\r
- \r
- uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.\r
- This parameter must be set to a value lower than 0x1FFF */ \r
-}RTC_InitTypeDef;\r
-\r
-/** \r
- * @brief RTC Time structure definition \r
- */\r
-typedef struct\r
-{\r
- uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.\r
- This parameter must be set to a value in the 0-12 range\r
- if the RTC_HourFormat_12 is selected or 0-23 range if\r
- the RTC_HourFormat_24 is selected. */\r
-\r
- uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.\r
- This parameter must be set to a value in the 0-59 range. */\r
- \r
- uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.\r
- This parameter must be set to a value in the 0-59 range. */\r
-\r
- uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.\r
- This parameter can be a value of @ref RTC_AM_PM_Definitions */\r
-}RTC_TimeTypeDef; \r
-\r
-/** \r
- * @brief RTC Date structure definition \r
- */\r
-typedef struct\r
-{\r
- uint32_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.\r
- This parameter can be a value of @ref RTC_WeekDay_Definitions */\r
- \r
- uint32_t RTC_Month; /*!< Specifies the RTC Date Month.\r
- This parameter can be a value of @ref RTC_Month_Date_Definitions */\r
-\r
- uint8_t RTC_Date; /*!< Specifies the RTC Date.\r
- This parameter must be set to a value in the 1-31 range. */\r
- \r
- uint8_t RTC_Year; /*!< Specifies the RTC Date Year.\r
- This parameter must be set to a value in the 0-99 range. */\r
-}RTC_DateTypeDef;\r
-\r
-/** \r
- * @brief RTC Alarm structure definition \r
- */\r
-typedef struct\r
-{\r
- RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */\r
-\r
- uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.\r
- This parameter can be a value of @ref RTC_AlarmMask_Definitions */\r
-\r
- uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.\r
- This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */\r
- \r
- uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.\r
- This parameter must be set to a value in the 1-31 range \r
- if the Alarm Date is selected.\r
- This parameter can be a value of @ref RTC_WeekDay_Definitions \r
- if the Alarm WeekDay is selected. */\r
-}RTC_AlarmTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup RTC_Exported_Constants\r
- * @{\r
- */ \r
-\r
-\r
-/** @defgroup RTC_Hour_Formats \r
- * @{\r
- */ \r
-#define RTC_HourFormat_24 ((uint32_t)0x00000000)\r
-#define RTC_HourFormat_12 ((uint32_t)0x00000040)\r
-#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \\r
- ((FORMAT) == RTC_HourFormat_24))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_Asynchronous_Predivider \r
- * @{\r
- */ \r
-#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)\r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup RTC_Synchronous_Predivider \r
- * @{\r
- */ \r
-#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x1FFF)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_Time_Definitions \r
- * @{\r
- */ \r
-#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))\r
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)\r
-#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)\r
-#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_AM_PM_Definitions \r
- * @{\r
- */ \r
-#define RTC_H12_AM ((uint8_t)0x00)\r
-#define RTC_H12_PM ((uint8_t)0x40)\r
-#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_Year_Date_Definitions \r
- * @{\r
- */ \r
-#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_Month_Date_Definitions \r
- * @{\r
- */ \r
-#define RTC_Month_January ((uint32_t)0x00000001)\r
-#define RTC_Month_February ((uint32_t)0x00000002)\r
-#define RTC_Month_March ((uint32_t)0x00000003)\r
-#define RTC_Month_April ((uint32_t)0x00000004)\r
-#define RTC_Month_May ((uint32_t)0x00000005)\r
-#define RTC_Month_June ((uint32_t)0x00000006)\r
-#define RTC_Month_July ((uint32_t)0x00000007)\r
-#define RTC_Month_August ((uint32_t)0x00000008)\r
-#define RTC_Month_September ((uint32_t)0x00000009)\r
-#define RTC_Month_October ((uint32_t)0x00000010)\r
-#define RTC_Month_November ((uint32_t)0x00000011)\r
-#define RTC_Month_December ((uint32_t)0x00000012)\r
-#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))\r
-#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_WeekDay_Definitions \r
- * @{\r
- */ \r
- \r
-#define RTC_Weekday_Monday ((uint32_t)0x00000001)\r
-#define RTC_Weekday_Tuesday ((uint32_t)0x00000002)\r
-#define RTC_Weekday_Wednesday ((uint32_t)0x00000003)\r
-#define RTC_Weekday_Thursday ((uint32_t)0x00000004)\r
-#define RTC_Weekday_Friday ((uint32_t)0x00000005)\r
-#define RTC_Weekday_Saturday ((uint32_t)0x00000006)\r
-#define RTC_Weekday_Sunday ((uint32_t)0x00000007)\r
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \\r
- ((WEEKDAY) == RTC_Weekday_Tuesday) || \\r
- ((WEEKDAY) == RTC_Weekday_Wednesday) || \\r
- ((WEEKDAY) == RTC_Weekday_Thursday) || \\r
- ((WEEKDAY) == RTC_Weekday_Friday) || \\r
- ((WEEKDAY) == RTC_Weekday_Saturday) || \\r
- ((WEEKDAY) == RTC_Weekday_Sunday))\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup RTC_Alarm_Definitions \r
- * @{\r
- */ \r
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))\r
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \\r
- ((WEEKDAY) == RTC_Weekday_Tuesday) || \\r
- ((WEEKDAY) == RTC_Weekday_Wednesday) || \\r
- ((WEEKDAY) == RTC_Weekday_Thursday) || \\r
- ((WEEKDAY) == RTC_Weekday_Friday) || \\r
- ((WEEKDAY) == RTC_Weekday_Saturday) || \\r
- ((WEEKDAY) == RTC_Weekday_Sunday))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup RTC_AlarmDateWeekDay_Definitions \r
- * @{\r
- */ \r
-#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) \r
-#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) \r
-\r
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \\r
- ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup RTC_AlarmMask_Definitions \r
- * @{\r
- */ \r
-#define RTC_AlarmMask_None ((uint32_t)0x00000000)\r
-#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) \r
-#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)\r
-#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)\r
-#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)\r
-#define RTC_AlarmMask_All ((uint32_t)0x80808080)\r
-#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_Alarms_Definitions \r
- * @{\r
- */ \r
-#define RTC_Alarm_A ((uint32_t)0x00000100)\r
-#define RTC_Alarm_B ((uint32_t)0x00000200)\r
-#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))\r
-#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_Wakeup_Timer_Definitions \r
- * @{\r
- */ \r
-#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)\r
-#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)\r
-#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)\r
-#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)\r
-#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)\r
-#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)\r
-#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \\r
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \\r
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \\r
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \\r
- ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \\r
- ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))\r
-#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_Time_Stamp_Edges_definitions \r
- * @{\r
- */ \r
-#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)\r
-#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)\r
-#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \\r
- ((EDGE) == RTC_TimeStampEdge_Falling))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_Output_selection_Definitions \r
- * @{\r
- */ \r
-#define RTC_Output_Disable ((uint32_t)0x00000000)\r
-#define RTC_Output_AlarmA ((uint32_t)0x00200000)\r
-#define RTC_Output_AlarmB ((uint32_t)0x00400000)\r
-#define RTC_Output_WakeUp ((uint32_t)0x00600000)\r
- \r
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \\r
- ((OUTPUT) == RTC_Output_AlarmA) || \\r
- ((OUTPUT) == RTC_Output_AlarmB) || \\r
- ((OUTPUT) == RTC_Output_WakeUp))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_Output_Polarity_Definitions \r
- * @{\r
- */ \r
-#define RTC_OutputPolarity_High ((uint32_t)0x00000000)\r
-#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)\r
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \\r
- ((POL) == RTC_OutputPolarity_Low))\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup RTC_Digital_Calibration_Definitions \r
- * @{\r
- */ \r
-#define RTC_CalibSign_Positive ((uint32_t)0x00000000) \r
-#define RTC_CalibSign_Negative ((uint32_t)0x00000080)\r
-#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \\r
- ((SIGN) == RTC_CalibSign_Negative))\r
-#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup RTC_DayLightSaving_Definitions \r
- * @{\r
- */ \r
-#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)\r
-#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)\r
-#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \\r
- ((SAVE) == RTC_DayLightSaving_ADD1H))\r
-\r
-#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)\r
-#define RTC_StoreOperation_Set ((uint32_t)0x00040000)\r
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \\r
- ((OPERATION) == RTC_StoreOperation_Set))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_Tamper_Trigger_Definitions \r
- * @{\r
- */ \r
-#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)\r
-#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)\r
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \\r
- ((TRIGGER) == RTC_TamperTrigger_FallingEdge))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_Tamper_Pins_Definitions \r
- * @{\r
- */ \r
-#define RTC_Tamper_1 RTC_TAFCR_TAMP1E\r
-#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1))\r
-\r
-/**\r
- * @}\r
- */ \r
- \r
-/** @defgroup RTC_Output_Type_ALARM_OUT \r
- * @{\r
- */ \r
-#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)\r
-#define RTC_OutputType_PushPull ((uint32_t)0x00040000)\r
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \\r
- ((TYPE) == RTC_OutputType_PushPull)) \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_Backup_Registers_Definitions \r
- * @{\r
- */ \r
-\r
-#define RTC_BKP_DR0 ((uint32_t)0x00000000)\r
-#define RTC_BKP_DR1 ((uint32_t)0x00000001)\r
-#define RTC_BKP_DR2 ((uint32_t)0x00000002)\r
-#define RTC_BKP_DR3 ((uint32_t)0x00000003)\r
-#define RTC_BKP_DR4 ((uint32_t)0x00000004)\r
-#define RTC_BKP_DR5 ((uint32_t)0x00000005)\r
-#define RTC_BKP_DR6 ((uint32_t)0x00000006)\r
-#define RTC_BKP_DR7 ((uint32_t)0x00000007)\r
-#define RTC_BKP_DR8 ((uint32_t)0x00000008)\r
-#define RTC_BKP_DR9 ((uint32_t)0x00000009)\r
-#define RTC_BKP_DR10 ((uint32_t)0x0000000A)\r
-#define RTC_BKP_DR11 ((uint32_t)0x0000000B)\r
-#define RTC_BKP_DR12 ((uint32_t)0x0000000C)\r
-#define RTC_BKP_DR13 ((uint32_t)0x0000000D)\r
-#define RTC_BKP_DR14 ((uint32_t)0x0000000E)\r
-#define RTC_BKP_DR15 ((uint32_t)0x0000000F)\r
-#define RTC_BKP_DR16 ((uint32_t)0x00000010)\r
-#define RTC_BKP_DR17 ((uint32_t)0x00000011)\r
-#define RTC_BKP_DR18 ((uint32_t)0x00000012)\r
-#define RTC_BKP_DR19 ((uint32_t)0x00000013)\r
-#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \\r
- ((BKP) == RTC_BKP_DR1) || \\r
- ((BKP) == RTC_BKP_DR2) || \\r
- ((BKP) == RTC_BKP_DR3) || \\r
- ((BKP) == RTC_BKP_DR4) || \\r
- ((BKP) == RTC_BKP_DR5) || \\r
- ((BKP) == RTC_BKP_DR6) || \\r
- ((BKP) == RTC_BKP_DR7) || \\r
- ((BKP) == RTC_BKP_DR8) || \\r
- ((BKP) == RTC_BKP_DR9) || \\r
- ((BKP) == RTC_BKP_DR10) || \\r
- ((BKP) == RTC_BKP_DR11) || \\r
- ((BKP) == RTC_BKP_DR12) || \\r
- ((BKP) == RTC_BKP_DR13) || \\r
- ((BKP) == RTC_BKP_DR14) || \\r
- ((BKP) == RTC_BKP_DR15) || \\r
- ((BKP) == RTC_BKP_DR16) || \\r
- ((BKP) == RTC_BKP_DR17) || \\r
- ((BKP) == RTC_BKP_DR18) || \\r
- ((BKP) == RTC_BKP_DR19))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_Input_parameter_format_definitions \r
- * @{\r
- */ \r
-#define RTC_Format_BIN ((uint32_t)0x000000000)\r
-#define RTC_Format_BCD ((uint32_t)0x000000001)\r
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_Flags_Definitions \r
- * @{\r
- */ \r
-#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)\r
-#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)\r
-#define RTC_FLAG_TSF ((uint32_t)0x00000800)\r
-#define RTC_FLAG_WUTF ((uint32_t)0x00000400)\r
-#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)\r
-#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)\r
-#define RTC_FLAG_INITF ((uint32_t)0x00000040)\r
-#define RTC_FLAG_RSF ((uint32_t)0x00000020)\r
-#define RTC_FLAG_INITS ((uint32_t)0x00000010)\r
-#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)\r
-#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)\r
-#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)\r
-#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \\r
- ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \\r
- ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \\r
- ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \\r
- ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \\r
- ((FLAG) == RTC_FLAG_TAMP1F))\r
-#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFC0DF) == (uint32_t)RESET))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_Interrupts_Definitions \r
- * @{\r
- */ \r
-#define RTC_IT_TS ((uint32_t)0x00008000)\r
-#define RTC_IT_WUT ((uint32_t)0x00004000)\r
-#define RTC_IT_ALRB ((uint32_t)0x00002000)\r
-#define RTC_IT_ALRA ((uint32_t)0x00001000)\r
-#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */\r
-#define RTC_IT_TAMP1 ((uint32_t)0x00020000)\r
-\r
-#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))\r
-#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \\r
- ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \\r
- ((IT) == RTC_IT_TAMP1))\r
-#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */ \r
-\r
-/* Function used to set the RTC configuration to the default reset state *****/ \r
-ErrorStatus RTC_DeInit(void);\r
-\r
-\r
-/* Initialization and Configuration functions *********************************/ \r
-ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);\r
-void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);\r
-void RTC_WriteProtectionCmd(FunctionalState NewState);\r
-ErrorStatus RTC_EnterInitMode(void);\r
-void RTC_ExitInitMode(void);\r
-ErrorStatus RTC_WaitForSynchro(void);\r
-ErrorStatus RTC_RefClockCmd(FunctionalState NewState);\r
-\r
-/* Time and Date configuration functions **************************************/ \r
-ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);\r
-void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);\r
-void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);\r
-ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);\r
-void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);\r
-void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);\r
-\r
-/* Alarms (Alarm A and Alarm B) configuration functions **********************/ \r
-void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);\r
-void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);\r
-void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);\r
-ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);\r
-\r
-/* WakeUp Timer configuration functions ***************************************/ \r
-void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);\r
-void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);\r
-uint32_t RTC_GetWakeUpCounter(void);\r
-ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);\r
-\r
-/* Daylight Saving configuration functions ************************************/ \r
-void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);\r
-uint32_t RTC_GetStoreOperation(void);\r
-\r
-/* Output pin Configuration function ******************************************/ \r
-void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);\r
-\r
-/* Digital Calibration configuration functions ********************************/ \r
-ErrorStatus RTC_DigitalCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);\r
-ErrorStatus RTC_DigitalCalibCmd(FunctionalState NewState);\r
-void RTC_CalibOutputCmd(FunctionalState NewState);\r
-\r
-/* TimeStamp configuration functions ******************************************/ \r
-void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);\r
-void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, \r
- RTC_DateTypeDef* RTC_StampDateStruct);\r
- \r
-\r
-/* Tampers configuration functions ********************************************/ \r
-void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);\r
-void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);\r
-\r
-/* Backup Data Registers configuration functions ******************************/ \r
-void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);\r
-uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);\r
-\r
-/* Output Type Config configuration functions *********************************/ \r
-void RTC_OutputTypeConfig(uint32_t RTC_OutputType);\r
-\r
-\r
-/* Interrupts and flags management functions **********************************/ \r
-void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);\r
-FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);\r
-void RTC_ClearFlag(uint32_t RTC_FLAG);\r
-ITStatus RTC_GetITStatus(uint32_t RTC_IT);\r
-void RTC_ClearITPendingBit(uint32_t RTC_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_RTC_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_spi.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the SPI \r
- * firmware library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_SPI_H\r
-#define __STM32L1xx_SPI_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup SPI\r
- * @{\r
- */ \r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief SPI Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.\r
- This parameter can be any combination of @ref SPI_data_direction */\r
-\r
- uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.\r
- This parameter can be any combination of @ref SPI_mode */\r
-\r
- uint16_t SPI_DataSize; /*!< Specifies the SPI data size.\r
- This parameter can be any combination of @ref SPI_data_size */\r
-\r
- uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.\r
- This parameter can be any combination of @ref SPI_Clock_Polarity */\r
-\r
- uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.\r
- This parameter can be any combination of @ref SPI_Clock_Phase */\r
-\r
- uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by\r
- hardware (NSS pin) or by software using the SSI bit.\r
- This parameter can be any combination of @ref SPI_Slave_Select_management */\r
- \r
- uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be\r
- used to configure the transmit and receive SCK clock.\r
- This parameter can be any combination of @ref SPI_BaudRate_Prescaler.\r
- @note The communication clock is derived from the master\r
- clock. The slave clock does not need to be set. */\r
-\r
- uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.\r
- This parameter can be any combination of @ref SPI_MSB_LSB_transmission */\r
-\r
- uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */\r
-}SPI_InitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup SPI_Exported_Constants\r
- * @{\r
- */\r
-\r
-#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \\r
- ((PERIPH) == SPI2))\r
-\r
-/** @defgroup SPI_data_direction \r
- * @{\r
- */\r
- \r
-#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)\r
-#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)\r
-#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)\r
-#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)\r
-#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \\r
- ((MODE) == SPI_Direction_2Lines_RxOnly) || \\r
- ((MODE) == SPI_Direction_1Line_Rx) || \\r
- ((MODE) == SPI_Direction_1Line_Tx))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_mode \r
- * @{\r
- */\r
-\r
-#define SPI_Mode_Master ((uint16_t)0x0104)\r
-#define SPI_Mode_Slave ((uint16_t)0x0000)\r
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \\r
- ((MODE) == SPI_Mode_Slave))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_data_size \r
- * @{\r
- */\r
-\r
-#define SPI_DataSize_16b ((uint16_t)0x0800)\r
-#define SPI_DataSize_8b ((uint16_t)0x0000)\r
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \\r
- ((DATASIZE) == SPI_DataSize_8b))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SPI_Clock_Polarity \r
- * @{\r
- */\r
-\r
-#define SPI_CPOL_Low ((uint16_t)0x0000)\r
-#define SPI_CPOL_High ((uint16_t)0x0002)\r
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \\r
- ((CPOL) == SPI_CPOL_High))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Clock_Phase \r
- * @{\r
- */\r
-\r
-#define SPI_CPHA_1Edge ((uint16_t)0x0000)\r
-#define SPI_CPHA_2Edge ((uint16_t)0x0001)\r
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \\r
- ((CPHA) == SPI_CPHA_2Edge))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Slave_Select_management \r
- * @{\r
- */\r
-\r
-#define SPI_NSS_Soft ((uint16_t)0x0200)\r
-#define SPI_NSS_Hard ((uint16_t)0x0000)\r
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \\r
- ((NSS) == SPI_NSS_Hard))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SPI_BaudRate_Prescaler \r
- * @{\r
- */\r
-\r
-#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)\r
-#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)\r
-#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)\r
-#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)\r
-#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)\r
-#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)\r
-#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)\r
-#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)\r
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_4) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_8) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_16) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_32) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_64) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_128) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_256))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SPI_MSB_LSB_transmission \r
- * @{\r
- */\r
-\r
-#define SPI_FirstBit_MSB ((uint16_t)0x0000)\r
-#define SPI_FirstBit_LSB ((uint16_t)0x0080)\r
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \\r
- ((BIT) == SPI_FirstBit_LSB))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_I2S_DMA_transfer_requests \r
- * @{\r
- */\r
-\r
-#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)\r
-#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)\r
-#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_NSS_internal_software_management \r
- * @{\r
- */\r
-\r
-#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)\r
-#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)\r
-#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \\r
- ((INTERNAL) == SPI_NSSInternalSoft_Reset))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_CRC_Transmit_Receive \r
- * @{\r
- */\r
-\r
-#define SPI_CRC_Tx ((uint8_t)0x00)\r
-#define SPI_CRC_Rx ((uint8_t)0x01)\r
-#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_direction_transmit_receive \r
- * @{\r
- */\r
-\r
-#define SPI_Direction_Rx ((uint16_t)0xBFFF)\r
-#define SPI_Direction_Tx ((uint16_t)0x4000)\r
-#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \\r
- ((DIRECTION) == SPI_Direction_Tx))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_I2S_interrupts_definition \r
- * @{\r
- */\r
-\r
-#define SPI_I2S_IT_TXE ((uint8_t)0x71)\r
-#define SPI_I2S_IT_RXNE ((uint8_t)0x60)\r
-#define SPI_I2S_IT_ERR ((uint8_t)0x50)\r
-#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \\r
- ((IT) == SPI_I2S_IT_RXNE) || \\r
- ((IT) == SPI_I2S_IT_ERR))\r
-\r
-#define SPI_I2S_IT_OVR ((uint8_t)0x56)\r
-#define SPI_IT_MODF ((uint8_t)0x55)\r
-#define SPI_IT_CRCERR ((uint8_t)0x54)\r
-\r
-#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))\r
-\r
-#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \\r
- ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \\r
- ((IT) == SPI_I2S_IT_OVR))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_I2S_flags_definition \r
- * @{\r
- */\r
-\r
-#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)\r
-#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)\r
-#define SPI_FLAG_CRCERR ((uint16_t)0x0010)\r
-#define SPI_FLAG_MODF ((uint16_t)0x0020)\r
-#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)\r
-#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)\r
-#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))\r
-#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \\r
- ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \\r
- ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_CRC_polynomial \r
- * @{\r
- */\r
-\r
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_I2S_Legacy \r
- * @{\r
- */\r
-\r
-#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx\r
-#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx\r
-#define SPI_IT_TXE SPI_I2S_IT_TXE\r
-#define SPI_IT_RXNE SPI_I2S_IT_RXNE\r
-#define SPI_IT_ERR SPI_I2S_IT_ERR\r
-#define SPI_IT_OVR SPI_I2S_IT_OVR\r
-#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE\r
-#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE\r
-#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR\r
-#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY\r
-#define SPI_DeInit SPI_I2S_DeInit\r
-#define SPI_ITConfig SPI_I2S_ITConfig\r
-#define SPI_DMACmd SPI_I2S_DMACmd\r
-#define SPI_SendData SPI_I2S_SendData\r
-#define SPI_ReceiveData SPI_I2S_ReceiveData\r
-#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus\r
-#define SPI_ClearFlag SPI_I2S_ClearFlag\r
-#define SPI_GetITStatus SPI_I2S_GetITStatus\r
-#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit\r
-/**\r
- * @}\r
- */\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-/* Function used to set the SPI configuration to the default reset state *****/ \r
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx);\r
-\r
-/* Initialization and Configuration functions *********************************/\r
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);\r
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);\r
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);\r
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);\r
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);\r
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
-\r
-/* Data transfers functions ***************************************************/ \r
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);\r
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);\r
-\r
-/* Hardware CRC Calculation functions *****************************************/\r
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);\r
-void SPI_TransmitCRC(SPI_TypeDef* SPIx);\r
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);\r
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);\r
-\r
-/* DMA transfers management functions *****************************************/\r
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);\r
-\r
-/* Interrupts and flags management functions **********************************/\r
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);\r
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_SPI_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_syscfg.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the SYSCFG \r
- * firmware library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/*!< Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_SYSCFG_H\r
-#define __STM32L1xx_SYSCFG_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/*!< Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup SYSCFG\r
- * @{\r
- */ \r
- \r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup SYSCFG_Exported_Constants\r
- * @{\r
- */ \r
- \r
-/** @defgroup EXTI_Port_Sources \r
- * @{\r
- */ \r
-#define EXTI_PortSourceGPIOA ((uint8_t)0x00)\r
-#define EXTI_PortSourceGPIOB ((uint8_t)0x01)\r
-#define EXTI_PortSourceGPIOC ((uint8_t)0x02)\r
-#define EXTI_PortSourceGPIOD ((uint8_t)0x03)\r
-#define EXTI_PortSourceGPIOE ((uint8_t)0x04)\r
-#define EXTI_PortSourceGPIOH ((uint8_t)0x05)\r
- \r
-#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \\r
- ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \\r
- ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \\r
- ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \\r
- ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \\r
- ((PORTSOURCE) == EXTI_PortSourceGPIOH)) \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup EXTI_Pin_sources \r
- * @{\r
- */ \r
-#define EXTI_PinSource0 ((uint8_t)0x00)\r
-#define EXTI_PinSource1 ((uint8_t)0x01)\r
-#define EXTI_PinSource2 ((uint8_t)0x02)\r
-#define EXTI_PinSource3 ((uint8_t)0x03)\r
-#define EXTI_PinSource4 ((uint8_t)0x04)\r
-#define EXTI_PinSource5 ((uint8_t)0x05)\r
-#define EXTI_PinSource6 ((uint8_t)0x06)\r
-#define EXTI_PinSource7 ((uint8_t)0x07)\r
-#define EXTI_PinSource8 ((uint8_t)0x08)\r
-#define EXTI_PinSource9 ((uint8_t)0x09)\r
-#define EXTI_PinSource10 ((uint8_t)0x0A)\r
-#define EXTI_PinSource11 ((uint8_t)0x0B)\r
-#define EXTI_PinSource12 ((uint8_t)0x0C)\r
-#define EXTI_PinSource13 ((uint8_t)0x0D)\r
-#define EXTI_PinSource14 ((uint8_t)0x0E)\r
-#define EXTI_PinSource15 ((uint8_t)0x0F)\r
-#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \\r
- ((PINSOURCE) == EXTI_PinSource1) || \\r
- ((PINSOURCE) == EXTI_PinSource2) || \\r
- ((PINSOURCE) == EXTI_PinSource3) || \\r
- ((PINSOURCE) == EXTI_PinSource4) || \\r
- ((PINSOURCE) == EXTI_PinSource5) || \\r
- ((PINSOURCE) == EXTI_PinSource6) || \\r
- ((PINSOURCE) == EXTI_PinSource7) || \\r
- ((PINSOURCE) == EXTI_PinSource8) || \\r
- ((PINSOURCE) == EXTI_PinSource9) || \\r
- ((PINSOURCE) == EXTI_PinSource10) || \\r
- ((PINSOURCE) == EXTI_PinSource11) || \\r
- ((PINSOURCE) == EXTI_PinSource12) || \\r
- ((PINSOURCE) == EXTI_PinSource13) || \\r
- ((PINSOURCE) == EXTI_PinSource14) || \\r
- ((PINSOURCE) == EXTI_PinSource15))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SYSCFG_Memory_Remap_Config \r
- * @{\r
- */ \r
-#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)\r
-#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)\r
-#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)\r
- \r
-#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \\r
- ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \\r
- ((REMAP) == SYSCFG_MemoryRemap_SRAM))\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup RI_Resistor\r
- * @{\r
- */\r
-\r
-#define RI_Resistor_10KPU COMP_CSR_10KPU\r
-#define RI_Resistor_400KPU COMP_CSR_400KPU\r
-#define RI_Resistor_10KPD COMP_CSR_10KPD\r
-#define RI_Resistor_400KPD COMP_CSR_400KPD\r
-\r
-#define IS_RI_RESISTOR(RESISTOR) (((RESISTOR) == COMP_CSR_10KPU) || \\r
- ((RESISTOR) == COMP_CSR_400KPU) || \\r
- ((RESISTOR) == COMP_CSR_10KPD) || \\r
- ((RESISTOR) == COMP_CSR_400KPD))\r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RI_InputCapture\r
- * @{\r
- */ \r
- \r
-#define RI_InputCapture_IC1 RI_ICR_IC1 /*!< Input Capture 1 */\r
-#define RI_InputCapture_IC2 RI_ICR_IC2 /*!< Input Capture 2 */\r
-#define RI_InputCapture_IC3 RI_ICR_IC3 /*!< Input Capture 3 */\r
-#define RI_InputCapture_IC4 RI_ICR_IC4 /*!< Input Capture 4 */\r
-\r
-#define IS_RI_INPUTCAPTURE(INPUTCAPTURE) ((((INPUTCAPTURE) & (uint32_t)0xFFC2FFFF) == 0x00) && ((INPUTCAPTURE) != (uint32_t)0x00))\r
-/**\r
- * @}\r
- */ \r
- \r
-/** @defgroup TIM_Select\r
- * @{\r
- */ \r
- \r
-#define TIM_Select_None ((uint32_t)0x00000000) /*!< None selected */\r
-#define TIM_Select_TIM2 ((uint32_t)0x00010000) /*!< Timer 2 selected */\r
-#define TIM_Select_TIM3 ((uint32_t)0x00020000) /*!< Timer 3 selected */\r
-#define TIM_Select_TIM4 ((uint32_t)0x00030000) /*!< Timer 4 selected */\r
-\r
-#define IS_RI_TIM(TIM) (((TIM) == TIM_Select_None) || \\r
- ((TIM) == TIM_Select_TIM2) || \\r
- ((TIM) == TIM_Select_TIM3) || \\r
- ((TIM) == TIM_Select_TIM4))\r
-\r
-/**\r
- * @}\r
- */ \r
- \r
-/** @defgroup RI_InputCaptureRouting\r
- * @{\r
- */ \r
- /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */ \r
-#define RI_InputCaptureRouting_0 ((uint32_t)0x00000000) /* PA0 PA1 PA2 PA3 */\r
-#define RI_InputCaptureRouting_1 ((uint32_t)0x00000001) /* PA4 PA5 PA6 PA7 */\r
-#define RI_InputCaptureRouting_2 ((uint32_t)0x00000002) /* PA8 PA9 PA10 PA11 */\r
-#define RI_InputCaptureRouting_3 ((uint32_t)0x00000003) /* PA12 PA13 PA14 PA15 */\r
-#define RI_InputCaptureRouting_4 ((uint32_t)0x00000004) /* PC0 PC1 PC2 PC3 */\r
-#define RI_InputCaptureRouting_5 ((uint32_t)0x00000005) /* PC4 PC5 PC6 PC7 */\r
-#define RI_InputCaptureRouting_6 ((uint32_t)0x00000006) /* PC8 PC9 PC10 PC11 */\r
-#define RI_InputCaptureRouting_7 ((uint32_t)0x00000007) /* PC12 PC13 PC14 PC15 */\r
-#define RI_InputCaptureRouting_8 ((uint32_t)0x00000008) /* PD0 PD1 PD2 PD3 */\r
-#define RI_InputCaptureRouting_9 ((uint32_t)0x00000009) /* PD4 PD5 PD6 PD7 */\r
-#define RI_InputCaptureRouting_10 ((uint32_t)0x0000000A) /* PD8 PD9 PD10 PD11 */\r
-#define RI_InputCaptureRouting_11 ((uint32_t)0x0000000B) /* PD12 PD13 PD14 PD15 */\r
-#define RI_InputCaptureRouting_12 ((uint32_t)0x0000000C) /* PE0 PE1 PE2 PE3 */\r
-#define RI_InputCaptureRouting_13 ((uint32_t)0x0000000D) /* PE4 PE5 PE6 PE7 */\r
-#define RI_InputCaptureRouting_14 ((uint32_t)0x0000000E) /* PE8 PE9 PE10 PE11 */\r
-#define RI_InputCaptureRouting_15 ((uint32_t)0x0000000F) /* PE12 PE13 PE14 PE15 */\r
-\r
-#define IS_RI_INPUTCAPTURE_ROUTING(ROUTING) (((ROUTING) == RI_InputCaptureRouting_0) || \\r
- ((ROUTING) == RI_InputCaptureRouting_1) || \\r
- ((ROUTING) == RI_InputCaptureRouting_2) || \\r
- ((ROUTING) == RI_InputCaptureRouting_3) || \\r
- ((ROUTING) == RI_InputCaptureRouting_4) || \\r
- ((ROUTING) == RI_InputCaptureRouting_5) || \\r
- ((ROUTING) == RI_InputCaptureRouting_6) || \\r
- ((ROUTING) == RI_InputCaptureRouting_7) || \\r
- ((ROUTING) == RI_InputCaptureRouting_8) || \\r
- ((ROUTING) == RI_InputCaptureRouting_9) || \\r
- ((ROUTING) == RI_InputCaptureRouting_10) || \\r
- ((ROUTING) == RI_InputCaptureRouting_11) || \\r
- ((ROUTING) == RI_InputCaptureRouting_12) || \\r
- ((ROUTING) == RI_InputCaptureRouting_13) || \\r
- ((ROUTING) == RI_InputCaptureRouting_14) || \\r
- ((ROUTING) == RI_InputCaptureRouting_15))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RI_IOSwitch\r
- * @{\r
- */ \r
- \r
-/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */\r
-#define RI_IOSwitch_CH0 ((uint32_t)0x80000001)\r
-#define RI_IOSwitch_CH1 ((uint32_t)0x80000002)\r
-#define RI_IOSwitch_CH2 ((uint32_t)0x80000004)\r
-#define RI_IOSwitch_CH3 ((uint32_t)0x80000008)\r
-#define RI_IOSwitch_CH4 ((uint32_t)0x80000010)\r
-#define RI_IOSwitch_CH5 ((uint32_t)0x80000020)\r
-#define RI_IOSwitch_CH6 ((uint32_t)0x80000040)\r
-#define RI_IOSwitch_CH7 ((uint32_t)0x80000080)\r
-#define RI_IOSwitch_CH8 ((uint32_t)0x80000100)\r
-#define RI_IOSwitch_CH9 ((uint32_t)0x80000200)\r
-#define RI_IOSwitch_CH10 ((uint32_t)0x80000400)\r
-#define RI_IOSwitch_CH11 ((uint32_t)0x80000800)\r
-#define RI_IOSwitch_CH12 ((uint32_t)0x80001000)\r
-#define RI_IOSwitch_CH13 ((uint32_t)0x80002000)\r
-#define RI_IOSwitch_CH14 ((uint32_t)0x80004000)\r
-#define RI_IOSwitch_CH15 ((uint32_t)0x80008000)\r
-#define RI_IOSwitch_CH18 ((uint32_t)0x80040000)\r
-#define RI_IOSwitch_CH19 ((uint32_t)0x80080000)\r
-#define RI_IOSwitch_CH20 ((uint32_t)0x80100000)\r
-#define RI_IOSwitch_CH21 ((uint32_t)0x80200000)\r
-#define RI_IOSwitch_CH22 ((uint32_t)0x80400000)\r
-#define RI_IOSwitch_CH23 ((uint32_t)0x80800000)\r
-#define RI_IOSwitch_CH24 ((uint32_t)0x81000000)\r
-#define RI_IOSwitch_CH25 ((uint32_t)0x82000000)\r
-#define RI_IOSwitch_VCOMP ((uint32_t)0x84000000) /* VCOMP is an internal switch used to connect \r
- selected channel to COMP1 non inverting input */\r
-\r
-/* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */ \r
-#define RI_IOSwitch_GR10_1 ((uint32_t)0x00000001)\r
-#define RI_IOSwitch_GR10_2 ((uint32_t)0x00000002)\r
-#define RI_IOSwitch_GR10_3 ((uint32_t)0x00000004)\r
-#define RI_IOSwitch_GR10_4 ((uint32_t)0x00000008)\r
-#define RI_IOSwitch_GR6_1 ((uint32_t)0x00000010)\r
-#define RI_IOSwitch_GR6_2 ((uint32_t)0x00000020)\r
-#define RI_IOSwitch_GR5_1 ((uint32_t)0x00000040)\r
-#define RI_IOSwitch_GR5_2 ((uint32_t)0x00000080)\r
-#define RI_IOSwitch_GR5_3 ((uint32_t)0x00000100)\r
-#define RI_IOSwitch_GR4_1 ((uint32_t)0x00000200)\r
-#define RI_IOSwitch_GR4_2 ((uint32_t)0x00000400)\r
-#define RI_IOSwitch_GR4_3 ((uint32_t)0x00000800)\r
-\r
-#define IS_RI_IOSWITCH(IOSWITCH) (((IOSWITCH) == RI_IOSwitch_CH0) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH1) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH2) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH3) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH4) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH5) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH6) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH7) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH8) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH9) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH10) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH11) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH12) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH13) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH14) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH15) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH18) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH19) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH20) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH21) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH22) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH23) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH24) || \\r
- ((IOSWITCH) == RI_IOSwitch_CH25) || \\r
- ((IOSWITCH) == RI_IOSwitch_VCOMP) || \\r
- ((IOSWITCH) == RI_IOSwitch_GR10_1) || \\r
- ((IOSWITCH) == RI_IOSwitch_GR10_2) || \\r
- ((IOSWITCH) == RI_IOSwitch_GR10_3) || \\r
- ((IOSWITCH) == RI_IOSwitch_GR10_4) || \\r
- ((IOSWITCH) == RI_IOSwitch_GR6_1) || \\r
- ((IOSWITCH) == RI_IOSwitch_GR6_2) || \\r
- ((IOSWITCH) == RI_IOSwitch_GR5_1) || \\r
- ((IOSWITCH) == RI_IOSwitch_GR5_2) || \\r
- ((IOSWITCH) == RI_IOSwitch_GR5_3) || \\r
- ((IOSWITCH) == RI_IOSwitch_GR4_1) || \\r
- ((IOSWITCH) == RI_IOSwitch_GR4_2) || \\r
- ((IOSWITCH) == RI_IOSwitch_GR4_3))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RI_Port\r
- * @{\r
- */\r
-\r
-#define RI_PortA ((uint8_t)0x01) /*!< GPIOA selected */\r
-#define RI_PortB ((uint8_t)0x02) /*!< GPIOB selected */\r
-#define RI_PortC ((uint8_t)0x03) /*!< GPIOC selected */\r
-#define RI_PortD ((uint8_t)0x04) /*!< GPIOD selected */\r
-#define RI_PortE ((uint8_t)0x05) /*!< GPIOE selected */\r
-\r
-#define IS_RI_PORT(PORT) (((PORT) == RI_PortA) || \\r
- ((PORT) == RI_PortB) || \\r
- ((PORT) == RI_PortC) || \\r
- ((PORT) == RI_PortD) || \\r
- ((PORT) == RI_PortE))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RI_Pin define \r
- * @{\r
- */\r
-#define RI_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */\r
-#define RI_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */\r
-#define RI_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */\r
-#define RI_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */\r
-#define RI_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */\r
-#define RI_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */\r
-#define RI_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */\r
-#define RI_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */\r
-#define RI_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */\r
-#define RI_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */\r
-#define RI_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */\r
-#define RI_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */\r
-#define RI_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */\r
-#define RI_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */\r
-#define RI_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */\r
-#define RI_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */\r
-#define RI_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */\r
-\r
-#define IS_RI_PIN(PIN) ((PIN) != (uint16_t)0x00)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-/* Function used to set the RTC configuration to the default reset state *****/\r
-void SYSCFG_DeInit(void);\r
-void SYSCFG_RIDeInit(void);\r
-\r
-/* SYSCFG Initialization and Configuration functions **************************/ \r
-void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);\r
-void SYSCFG_USBPuCmd(FunctionalState NewState);\r
-void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);\r
-\r
-/* RI Initialization and Configuration functions ******************************/ \r
-void SYSCFG_RITIMSelect(uint32_t TIM_Select);\r
-void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting);\r
-void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState);\r
-void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState);\r
-void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState);\r
-void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin,\r
- FunctionalState NewState);\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_SYSCFG_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_tim.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the TIM firmware \r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_TIM_H\r
-#define __STM32L1xx_TIM_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup TIM\r
- * @{\r
- */ \r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief TIM Time Base Init structure definition\r
- * @note This structure is used with all TIMx except for TIM6 and TIM7. \r
- */\r
-\r
-typedef struct\r
-{\r
- uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.\r
- This parameter can be a number between 0x0000 and 0xFFFF */\r
-\r
- uint16_t TIM_CounterMode; /*!< Specifies the counter mode.\r
- This parameter can be a value of @ref TIM_Counter_Mode */\r
-\r
- uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active\r
- Auto-Reload Register at the next update event.\r
- This parameter must be a number between 0x0000 and 0xFFFF. */ \r
-\r
- uint16_t TIM_ClockDivision; /*!< Specifies the clock division.\r
- This parameter can be a value of @ref TIM_Clock_Division_CKD */\r
-\r
-} TIM_TimeBaseInitTypeDef; \r
-\r
-/** \r
- * @brief TIM Output Compare Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint16_t TIM_OCMode; /*!< Specifies the TIM mode.\r
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
-\r
- uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.\r
- This parameter can be a value of @ref TIM_Output_Compare_state */\r
-\r
- uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r
- This parameter can be a number between 0x0000 and 0xFFFF */\r
-\r
- uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.\r
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
-\r
-} TIM_OCInitTypeDef;\r
-\r
-/** \r
- * @brief TIM Input Capture Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
-\r
- uint16_t TIM_Channel; /*!< Specifies the TIM channel.\r
- This parameter can be a value of @ref TIM_Channel */\r
-\r
- uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.\r
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
-\r
- uint16_t TIM_ICSelection; /*!< Specifies the input.\r
- This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
-\r
- uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.\r
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
-\r
- uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.\r
- This parameter can be a number between 0x0 and 0xF */\r
-} TIM_ICInitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
- \r
-/** @defgroup TIM_Exported_constants \r
- * @{\r
- */\r
-\r
-#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) || \\r
- ((PERIPH) == TIM6) || \\r
- ((PERIPH) == TIM7) || \\r
- ((PERIPH) == TIM9) || \\r
- ((PERIPH) == TIM10) || \\r
- ((PERIPH) == TIM11))\r
-\r
-/* LIST1: TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11 */\r
-#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) || \\r
- ((PERIPH) == TIM9) || \\r
- ((PERIPH) == TIM10) || \\r
- ((PERIPH) == TIM11))\r
-\r
-/* LIST3: TIM2, TIM3 and TIM4 */\r
-#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4))\r
-\r
-/* LIST2: TIM2, TIM3, TIM4 and TIM9 */\r
-#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) ||\\r
- ((PERIPH) == TIM9))\r
-\r
-/* LIST5: TIM2, TIM3, TIM4, TIM6, TIM7 and TIM9 */\r
-#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) ||\\r
- ((PERIPH) == TIM6) || \\r
- ((PERIPH) == TIM7) ||\\r
- ((PERIPH) == TIM9))\r
-\r
-/* LIST4: TIM2, TIM3, TIM4, TIM6 and TIM7 */\r
-#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) ||\\r
- ((PERIPH) == TIM6) || \\r
- ((PERIPH) == TIM7))\r
-\r
-/* LIST6: TIM9, TIM10 and TIM11 */\r
-#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM9) || \\r
- ((PERIPH) == TIM10) ||\\r
- ((PERIPH) == TIM11))\r
-\r
-\r
-\r
-/** @defgroup TIM_Output_Compare_and_PWM_modes \r
- * @{\r
- */\r
-\r
-#define TIM_OCMode_Timing ((uint16_t)0x0000)\r
-#define TIM_OCMode_Active ((uint16_t)0x0010)\r
-#define TIM_OCMode_Inactive ((uint16_t)0x0020)\r
-#define TIM_OCMode_Toggle ((uint16_t)0x0030)\r
-#define TIM_OCMode_PWM1 ((uint16_t)0x0060)\r
-#define TIM_OCMode_PWM2 ((uint16_t)0x0070)\r
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
- ((MODE) == TIM_OCMode_Active) || \\r
- ((MODE) == TIM_OCMode_Inactive) || \\r
- ((MODE) == TIM_OCMode_Toggle)|| \\r
- ((MODE) == TIM_OCMode_PWM1) || \\r
- ((MODE) == TIM_OCMode_PWM2))\r
-#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
- ((MODE) == TIM_OCMode_Active) || \\r
- ((MODE) == TIM_OCMode_Inactive) || \\r
- ((MODE) == TIM_OCMode_Toggle)|| \\r
- ((MODE) == TIM_OCMode_PWM1) || \\r
- ((MODE) == TIM_OCMode_PWM2) || \\r
- ((MODE) == TIM_ForcedAction_Active) || \\r
- ((MODE) == TIM_ForcedAction_InActive))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_One_Pulse_Mode \r
- * @{\r
- */\r
-\r
-#define TIM_OPMode_Single ((uint16_t)0x0008)\r
-#define TIM_OPMode_Repetitive ((uint16_t)0x0000)\r
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \\r
- ((MODE) == TIM_OPMode_Repetitive))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Channel \r
- * @{\r
- */\r
-\r
-#define TIM_Channel_1 ((uint16_t)0x0000)\r
-#define TIM_Channel_2 ((uint16_t)0x0004)\r
-#define TIM_Channel_3 ((uint16_t)0x0008)\r
-#define TIM_Channel_4 ((uint16_t)0x000C)\r
-\r
-#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
- ((CHANNEL) == TIM_Channel_2) || \\r
- ((CHANNEL) == TIM_Channel_3) || \\r
- ((CHANNEL) == TIM_Channel_4))\r
- \r
-#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
- ((CHANNEL) == TIM_Channel_2))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Clock_Division_CKD \r
- * @{\r
- */\r
-\r
-#define TIM_CKD_DIV1 ((uint16_t)0x0000)\r
-#define TIM_CKD_DIV2 ((uint16_t)0x0100)\r
-#define TIM_CKD_DIV4 ((uint16_t)0x0200)\r
-#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \\r
- ((DIV) == TIM_CKD_DIV2) || \\r
- ((DIV) == TIM_CKD_DIV4))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Counter_Mode \r
- * @{\r
- */\r
-\r
-#define TIM_CounterMode_Up ((uint16_t)0x0000)\r
-#define TIM_CounterMode_Down ((uint16_t)0x0010)\r
-#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)\r
-#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)\r
-#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)\r
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \\r
- ((MODE) == TIM_CounterMode_Down) || \\r
- ((MODE) == TIM_CounterMode_CenterAligned1) || \\r
- ((MODE) == TIM_CounterMode_CenterAligned2) || \\r
- ((MODE) == TIM_CounterMode_CenterAligned3))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Output_Compare_Polarity \r
- * @{\r
- */\r
-\r
-#define TIM_OCPolarity_High ((uint16_t)0x0000)\r
-#define TIM_OCPolarity_Low ((uint16_t)0x0002)\r
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \\r
- ((POLARITY) == TIM_OCPolarity_Low))\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup TIM_Output_Compare_state\r
- * @{\r
- */\r
-\r
-#define TIM_OutputState_Disable ((uint16_t)0x0000)\r
-#define TIM_OutputState_Enable ((uint16_t)0x0001)\r
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \\r
- ((STATE) == TIM_OutputState_Enable))\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup TIM_Capture_Compare_state \r
- * @{\r
- */\r
-\r
-#define TIM_CCx_Enable ((uint16_t)0x0001)\r
-#define TIM_CCx_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \\r
- ((CCX) == TIM_CCx_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Input_Capture_Polarity \r
- * @{\r
- */\r
-\r
-#define TIM_ICPolarity_Rising ((uint16_t)0x0000)\r
-#define TIM_ICPolarity_Falling ((uint16_t)0x0002)\r
-#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)\r
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \\r
- ((POLARITY) == TIM_ICPolarity_Falling)|| \\r
- ((POLARITY) == TIM_ICPolarity_BothEdge))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Input_Capture_Selection \r
- * @{\r
- */\r
-\r
-#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \r
- connected to IC1, IC2, IC3 or IC4, respectively */\r
-#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
- connected to IC2, IC1, IC4 or IC3, respectively. */\r
-#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */\r
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \\r
- ((SELECTION) == TIM_ICSelection_IndirectTI) || \\r
- ((SELECTION) == TIM_ICSelection_TRC))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Input_Capture_Prescaler \r
- * @{\r
- */\r
-\r
-#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */\r
-#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */\r
-#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */\r
-#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */\r
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \\r
- ((PRESCALER) == TIM_ICPSC_DIV2) || \\r
- ((PRESCALER) == TIM_ICPSC_DIV4) || \\r
- ((PRESCALER) == TIM_ICPSC_DIV8))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_interrupt_sources \r
- * @{\r
- */\r
-\r
-#define TIM_IT_Update ((uint16_t)0x0001)\r
-#define TIM_IT_CC1 ((uint16_t)0x0002)\r
-#define TIM_IT_CC2 ((uint16_t)0x0004)\r
-#define TIM_IT_CC3 ((uint16_t)0x0008)\r
-#define TIM_IT_CC4 ((uint16_t)0x0010)\r
-#define TIM_IT_Trigger ((uint16_t)0x0040)\r
-#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x0000) && ((IT) != 0x0000))\r
-\r
-#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \\r
- ((IT) == TIM_IT_CC1) || \\r
- ((IT) == TIM_IT_CC2) || \\r
- ((IT) == TIM_IT_CC3) || \\r
- ((IT) == TIM_IT_CC4) || \\r
- ((IT) == TIM_IT_Trigger))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_DMA_Base_address \r
- * @{\r
- */\r
-\r
-#define TIM_DMABase_CR1 ((uint16_t)0x0000)\r
-#define TIM_DMABase_CR2 ((uint16_t)0x0001)\r
-#define TIM_DMABase_SMCR ((uint16_t)0x0002)\r
-#define TIM_DMABase_DIER ((uint16_t)0x0003)\r
-#define TIM_DMABase_SR ((uint16_t)0x0004)\r
-#define TIM_DMABase_EGR ((uint16_t)0x0005)\r
-#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)\r
-#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)\r
-#define TIM_DMABase_CCER ((uint16_t)0x0008)\r
-#define TIM_DMABase_CNT ((uint16_t)0x0009)\r
-#define TIM_DMABase_PSC ((uint16_t)0x000A)\r
-#define TIM_DMABase_ARR ((uint16_t)0x000B)\r
-#define TIM_DMABase_RCR ((uint16_t)0x000C)\r
-#define TIM_DMABase_CCR1 ((uint16_t)0x000D)\r
-#define TIM_DMABase_CCR2 ((uint16_t)0x000E)\r
-#define TIM_DMABase_CCR3 ((uint16_t)0x000F)\r
-#define TIM_DMABase_CCR4 ((uint16_t)0x0010)\r
-#define TIM_DMABase_DCR ((uint16_t)0x0012)\r
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \\r
- ((BASE) == TIM_DMABase_CR2) || \\r
- ((BASE) == TIM_DMABase_SMCR) || \\r
- ((BASE) == TIM_DMABase_DIER) || \\r
- ((BASE) == TIM_DMABase_SR) || \\r
- ((BASE) == TIM_DMABase_EGR) || \\r
- ((BASE) == TIM_DMABase_CCMR1) || \\r
- ((BASE) == TIM_DMABase_CCMR2) || \\r
- ((BASE) == TIM_DMABase_CCER) || \\r
- ((BASE) == TIM_DMABase_CNT) || \\r
- ((BASE) == TIM_DMABase_PSC) || \\r
- ((BASE) == TIM_DMABase_ARR) || \\r
- ((BASE) == TIM_DMABase_CCR1) || \\r
- ((BASE) == TIM_DMABase_CCR2) || \\r
- ((BASE) == TIM_DMABase_CCR3) || \\r
- ((BASE) == TIM_DMABase_CCR4) || \\r
- ((BASE) == TIM_DMABase_DCR)) \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_DMA_Burst_Length \r
- * @{\r
- */\r
-\r
-#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000)\r
-#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100)\r
-#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200)\r
-#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300)\r
-#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400)\r
-#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500)\r
-#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600)\r
-#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700)\r
-#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800)\r
-#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900)\r
-#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00)\r
-#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00)\r
-#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00)\r
-#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00)\r
-#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00)\r
-#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00)\r
-#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000)\r
-#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100)\r
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \\r
- ((LENGTH) == TIM_DMABurstLength_2Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_3Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_4Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_5Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_6Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_7Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_8Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_9Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_10Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_11Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_12Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_13Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_14Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_15Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_16Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_17Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_18Bytes))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_DMA_sources \r
- * @{\r
- */\r
-\r
-#define TIM_DMA_Update ((uint16_t)0x0100)\r
-#define TIM_DMA_CC1 ((uint16_t)0x0200)\r
-#define TIM_DMA_CC2 ((uint16_t)0x0400)\r
-#define TIM_DMA_CC3 ((uint16_t)0x0800)\r
-#define TIM_DMA_CC4 ((uint16_t)0x1000)\r
-#define TIM_DMA_Trigger ((uint16_t)0x4000)\r
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_External_Trigger_Prescaler \r
- * @{\r
- */\r
-\r
-#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)\r
-#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)\r
-#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)\r
-#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)\r
-#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \\r
- ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \\r
- ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \\r
- ((PRESCALER) == TIM_ExtTRGPSC_DIV8))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Internal_Trigger_Selection \r
- * @{\r
- */\r
-\r
-#define TIM_TS_ITR0 ((uint16_t)0x0000)\r
-#define TIM_TS_ITR1 ((uint16_t)0x0010)\r
-#define TIM_TS_ITR2 ((uint16_t)0x0020)\r
-#define TIM_TS_ITR3 ((uint16_t)0x0030)\r
-#define TIM_TS_TI1F_ED ((uint16_t)0x0040)\r
-#define TIM_TS_TI1FP1 ((uint16_t)0x0050)\r
-#define TIM_TS_TI2FP2 ((uint16_t)0x0060)\r
-#define TIM_TS_ETRF ((uint16_t)0x0070)\r
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
- ((SELECTION) == TIM_TS_ITR1) || \\r
- ((SELECTION) == TIM_TS_ITR2) || \\r
- ((SELECTION) == TIM_TS_ITR3) || \\r
- ((SELECTION) == TIM_TS_TI1F_ED) || \\r
- ((SELECTION) == TIM_TS_TI1FP1) || \\r
- ((SELECTION) == TIM_TS_TI2FP2) || \\r
- ((SELECTION) == TIM_TS_ETRF))\r
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
- ((SELECTION) == TIM_TS_ITR1) || \\r
- ((SELECTION) == TIM_TS_ITR2) || \\r
- ((SELECTION) == TIM_TS_ITR3))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_TIx_External_Clock_Source \r
- * @{\r
- */\r
-\r
-#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)\r
-#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)\r
-#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_External_Trigger_Polarity \r
- * @{\r
- */ \r
-#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)\r
-#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)\r
-#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \\r
- ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Prescaler_Reload_Mode \r
- * @{\r
- */\r
-\r
-#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)\r
-#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)\r
-#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \\r
- ((RELOAD) == TIM_PSCReloadMode_Immediate))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Forced_Action \r
- * @{\r
- */\r
-\r
-#define TIM_ForcedAction_Active ((uint16_t)0x0050)\r
-#define TIM_ForcedAction_InActive ((uint16_t)0x0040)\r
-#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \\r
- ((ACTION) == TIM_ForcedAction_InActive))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Encoder_Mode \r
- * @{\r
- */\r
-\r
-#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)\r
-#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)\r
-#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)\r
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \\r
- ((MODE) == TIM_EncoderMode_TI2) || \\r
- ((MODE) == TIM_EncoderMode_TI12))\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup TIM_Event_Source \r
- * @{\r
- */\r
-\r
-#define TIM_EventSource_Update ((uint16_t)0x0001)\r
-#define TIM_EventSource_CC1 ((uint16_t)0x0002)\r
-#define TIM_EventSource_CC2 ((uint16_t)0x0004)\r
-#define TIM_EventSource_CC3 ((uint16_t)0x0008)\r
-#define TIM_EventSource_CC4 ((uint16_t)0x0010)\r
-#define TIM_EventSource_Trigger ((uint16_t)0x0040)\r
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFFA0) == 0x0000) && ((SOURCE) != 0x0000)) \r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Update_Source \r
- * @{\r
- */\r
-\r
-#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow\r
- or the setting of UG bit, or an update generation\r
- through the slave mode controller. */\r
-#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */\r
-#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \\r
- ((SOURCE) == TIM_UpdateSource_Regular))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Output_Compare_Preload_State \r
- * @{\r
- */\r
-\r
-#define TIM_OCPreload_Enable ((uint16_t)0x0008)\r
-#define TIM_OCPreload_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \\r
- ((STATE) == TIM_OCPreload_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Output_Compare_Fast_State \r
- * @{\r
- */\r
-\r
-#define TIM_OCFast_Enable ((uint16_t)0x0004)\r
-#define TIM_OCFast_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \\r
- ((STATE) == TIM_OCFast_Disable))\r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Output_Compare_Clear_State \r
- * @{\r
- */\r
-\r
-#define TIM_OCClear_Enable ((uint16_t)0x0080)\r
-#define TIM_OCClear_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \\r
- ((STATE) == TIM_OCClear_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Trigger_Output_Source \r
- * @{\r
- */\r
-\r
-#define TIM_TRGOSource_Reset ((uint16_t)0x0000)\r
-#define TIM_TRGOSource_Enable ((uint16_t)0x0010)\r
-#define TIM_TRGOSource_Update ((uint16_t)0x0020)\r
-#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)\r
-#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)\r
-#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)\r
-#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)\r
-#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)\r
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \\r
- ((SOURCE) == TIM_TRGOSource_Enable) || \\r
- ((SOURCE) == TIM_TRGOSource_Update) || \\r
- ((SOURCE) == TIM_TRGOSource_OC1) || \\r
- ((SOURCE) == TIM_TRGOSource_OC1Ref) || \\r
- ((SOURCE) == TIM_TRGOSource_OC2Ref) || \\r
- ((SOURCE) == TIM_TRGOSource_OC3Ref) || \\r
- ((SOURCE) == TIM_TRGOSource_OC4Ref))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Slave_Mode \r
- * @{\r
- */\r
-\r
-#define TIM_SlaveMode_Reset ((uint16_t)0x0004)\r
-#define TIM_SlaveMode_Gated ((uint16_t)0x0005)\r
-#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)\r
-#define TIM_SlaveMode_External1 ((uint16_t)0x0007)\r
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \\r
- ((MODE) == TIM_SlaveMode_Gated) || \\r
- ((MODE) == TIM_SlaveMode_Trigger) || \\r
- ((MODE) == TIM_SlaveMode_External1))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Master_Slave_Mode \r
- * @{\r
- */\r
-\r
-#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)\r
-#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \\r
- ((STATE) == TIM_MasterSlaveMode_Disable))\r
-/**\r
- * @}\r
- */ \r
- \r
-/** @defgroup TIM_Flags \r
- * @{\r
- */\r
-\r
-#define TIM_FLAG_Update ((uint16_t)0x0001)\r
-#define TIM_FLAG_CC1 ((uint16_t)0x0002)\r
-#define TIM_FLAG_CC2 ((uint16_t)0x0004)\r
-#define TIM_FLAG_CC3 ((uint16_t)0x0008)\r
-#define TIM_FLAG_CC4 ((uint16_t)0x0010)\r
-#define TIM_FLAG_Trigger ((uint16_t)0x0040)\r
-#define TIM_FLAG_CC1OF ((uint16_t)0x0200)\r
-#define TIM_FLAG_CC2OF ((uint16_t)0x0400)\r
-#define TIM_FLAG_CC3OF ((uint16_t)0x0800)\r
-#define TIM_FLAG_CC4OF ((uint16_t)0x1000)\r
-#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \\r
- ((FLAG) == TIM_FLAG_CC1) || \\r
- ((FLAG) == TIM_FLAG_CC2) || \\r
- ((FLAG) == TIM_FLAG_CC3) || \\r
- ((FLAG) == TIM_FLAG_CC4) || \\r
- ((FLAG) == TIM_FLAG_Trigger) || \\r
- ((FLAG) == TIM_FLAG_CC1OF) || \\r
- ((FLAG) == TIM_FLAG_CC2OF) || \\r
- ((FLAG) == TIM_FLAG_CC3OF) || \\r
- ((FLAG) == TIM_FLAG_CC4OF))\r
-#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Input_Capture_Filer_Value \r
- * @{\r
- */\r
-\r
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_External_Trigger_Filter \r
- * @{\r
- */\r
-\r
-#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_OCReferenceClear \r
- * @{\r
- */\r
-#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)\r
-#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)\r
-#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \\r
- ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Remap \r
- * @{\r
- */\r
-\r
-#define TIM9_GPIO ((uint16_t)0x0000)\r
-#define TIM9_LSE ((uint16_t)0x0001)\r
-\r
-#define TIM10_GPIO ((uint16_t)0x0000)\r
-#define TIM10_LSI ((uint16_t)0x0001)\r
-#define TIM10_LSE ((uint16_t)0x0002)\r
-#define TIM10_RTC ((uint16_t)0x0003)\r
-\r
-#define TIM11_GPIO ((uint16_t)0x0000)\r
-#define TIM11_MSI ((uint16_t)0x0001)\r
-#define TIM11_HSE_RTC ((uint16_t)0x0002)\r
-\r
-#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM9_GPIO)||\\r
- ((TIM_REMAP) == TIM9_LSE)||\\r
- ((TIM_REMAP) == TIM10_GPIO)||\\r
- ((TIM_REMAP) == TIM10_LSI)||\\r
- ((TIM_REMAP) == TIM10_LSE)||\\r
- ((TIM_REMAP) == TIM10_RTC)||\\r
- ((TIM_REMAP) == TIM11_GPIO)||\\r
- ((TIM_REMAP) == TIM11_MSI)||\\r
- ((TIM_REMAP) == TIM11_HSE_RTC)) \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */ \r
-\r
-/* TimeBase management ********************************************************/\r
-void TIM_DeInit(TIM_TypeDef* TIMx);\r
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);\r
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);\r
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);\r
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);\r
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);\r
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);\r
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);\r
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);\r
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);\r
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-\r
-/* Output Compare management **************************************************/\r
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);\r
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);\r
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);\r
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);\r
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);\r
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);\r
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
-void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);\r
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);\r
-\r
-/* Input Capture management ***************************************************/\r
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);\r
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);\r
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);\r
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);\r
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);\r
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
-\r
-/* Interrupts, DMA and flags management ***************************************/\r
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);\r
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);\r
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);\r
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);\r
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-\r
-/* Clocks management **********************************************************/\r
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx);\r
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
- uint16_t TIM_ICPolarity, uint16_t ICFilter);\r
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
- uint16_t ExtTRGFilter);\r
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);\r
-\r
-\r
-/* Synchronization management *************************************************/\r
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);\r
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);\r
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);\r
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
- uint16_t ExtTRGFilter);\r
-\r
-/* Specific interface management **********************************************/ \r
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);\r
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-\r
-/* Specific remapping management **********************************************/\r
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_TIM_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_usart.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the USART \r
- * firmware library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_USART_H\r
-#define __STM32L1xx_USART_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup USART\r
- * @{\r
- */ \r
-\r
-/* Exported types ------------------------------------------------------------*/ \r
-\r
-/** \r
- * @brief USART Init Structure definition \r
- */ \r
- \r
-typedef struct\r
-{\r
- uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.\r
- The baud rate is computed using the following formula:\r
- - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))\r
- - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */\r
-\r
- uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
- This parameter can be a value of @ref USART_Word_Length */\r
-\r
- uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.\r
- This parameter can be a value of @ref USART_Stop_Bits */\r
-\r
- uint16_t USART_Parity; /*!< Specifies the parity mode.\r
- This parameter can be a value of @ref USART_Parity\r
- @note When parity is enabled, the computed parity is inserted\r
- at the MSB position of the transmitted data (9th bit when\r
- the word length is set to 9 data bits; 8th bit when the\r
- word length is set to 8 data bits). */\r
- \r
- uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.\r
- This parameter can be a value of @ref USART_Mode */\r
-\r
- uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled\r
- or disabled.\r
- This parameter can be a value of @ref USART_Hardware_Flow_Control */\r
-} USART_InitTypeDef;\r
-\r
-/** \r
- * @brief USART Clock Init Structure definition \r
- */ \r
- \r
-typedef struct\r
-{\r
-\r
- uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.\r
- This parameter can be a value of @ref USART_Clock */\r
-\r
- uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.\r
- This parameter can be a value of @ref USART_Clock_Polarity */\r
-\r
- uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.\r
- This parameter can be a value of @ref USART_Clock_Phase */\r
-\r
- uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted\r
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r
- This parameter can be a value of @ref USART_Last_Bit */\r
-} USART_ClockInitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup USART_Exported_Constants\r
- * @{\r
- */ \r
- \r
-#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
- ((PERIPH) == USART2) || \\r
- ((PERIPH) == USART3))\r
-\r
-/** @defgroup USART_Word_Length \r
- * @{\r
- */ \r
- \r
-#define USART_WordLength_8b ((uint16_t)0x0000)\r
-#define USART_WordLength_9b ((uint16_t)0x1000)\r
- \r
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \\r
- ((LENGTH) == USART_WordLength_9b))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Stop_Bits \r
- * @{\r
- */ \r
- \r
-#define USART_StopBits_1 ((uint16_t)0x0000)\r
-#define USART_StopBits_0_5 ((uint16_t)0x1000)\r
-#define USART_StopBits_2 ((uint16_t)0x2000)\r
-#define USART_StopBits_1_5 ((uint16_t)0x3000)\r
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \\r
- ((STOPBITS) == USART_StopBits_0_5) || \\r
- ((STOPBITS) == USART_StopBits_2) || \\r
- ((STOPBITS) == USART_StopBits_1_5))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Parity \r
- * @{\r
- */ \r
- \r
-#define USART_Parity_No ((uint16_t)0x0000)\r
-#define USART_Parity_Even ((uint16_t)0x0400)\r
-#define USART_Parity_Odd ((uint16_t)0x0600) \r
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \\r
- ((PARITY) == USART_Parity_Even) || \\r
- ((PARITY) == USART_Parity_Odd))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Mode \r
- * @{\r
- */ \r
- \r
-#define USART_Mode_Rx ((uint16_t)0x0004)\r
-#define USART_Mode_Tx ((uint16_t)0x0008)\r
-#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Hardware_Flow_Control \r
- * @{\r
- */ \r
-#define USART_HardwareFlowControl_None ((uint16_t)0x0000)\r
-#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)\r
-#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)\r
-#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)\r
-#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\\r
- (((CONTROL) == USART_HardwareFlowControl_None) || \\r
- ((CONTROL) == USART_HardwareFlowControl_RTS) || \\r
- ((CONTROL) == USART_HardwareFlowControl_CTS) || \\r
- ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Clock \r
- * @{\r
- */ \r
-#define USART_Clock_Disable ((uint16_t)0x0000)\r
-#define USART_Clock_Enable ((uint16_t)0x0800)\r
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \\r
- ((CLOCK) == USART_Clock_Enable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Clock_Polarity \r
- * @{\r
- */\r
- \r
-#define USART_CPOL_Low ((uint16_t)0x0000)\r
-#define USART_CPOL_High ((uint16_t)0x0400)\r
-#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Clock_Phase\r
- * @{\r
- */\r
-\r
-#define USART_CPHA_1Edge ((uint16_t)0x0000)\r
-#define USART_CPHA_2Edge ((uint16_t)0x0200)\r
-#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Last_Bit\r
- * @{\r
- */\r
-\r
-#define USART_LastBit_Disable ((uint16_t)0x0000)\r
-#define USART_LastBit_Enable ((uint16_t)0x0100)\r
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \\r
- ((LASTBIT) == USART_LastBit_Enable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Interrupt_definition \r
- * @{\r
- */\r
- \r
-#define USART_IT_PE ((uint16_t)0x0028)\r
-#define USART_IT_TXE ((uint16_t)0x0727)\r
-#define USART_IT_TC ((uint16_t)0x0626)\r
-#define USART_IT_RXNE ((uint16_t)0x0525)\r
-#define USART_IT_IDLE ((uint16_t)0x0424)\r
-#define USART_IT_LBD ((uint16_t)0x0846)\r
-#define USART_IT_CTS ((uint16_t)0x096A)\r
-#define USART_IT_ERR ((uint16_t)0x0060)\r
-#define USART_IT_ORE ((uint16_t)0x0360)\r
-#define USART_IT_NE ((uint16_t)0x0260)\r
-#define USART_IT_FE ((uint16_t)0x0160)\r
-#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))\r
-#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \\r
- ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))\r
-#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
- ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_DMA_Requests \r
- * @{\r
- */\r
-\r
-#define USART_DMAReq_Tx ((uint16_t)0x0080)\r
-#define USART_DMAReq_Rx ((uint16_t)0x0040)\r
-#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_WakeUp_methods\r
- * @{\r
- */\r
-\r
-#define USART_WakeUp_IdleLine ((uint16_t)0x0000)\r
-#define USART_WakeUp_AddressMark ((uint16_t)0x0800)\r
-#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \\r
- ((WAKEUP) == USART_WakeUp_AddressMark))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_LIN_Break_Detection_Length \r
- * @{\r
- */\r
- \r
-#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)\r
-#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)\r
-#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \\r
- (((LENGTH) == USART_LINBreakDetectLength_10b) || \\r
- ((LENGTH) == USART_LINBreakDetectLength_11b))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_IrDA_Low_Power \r
- * @{\r
- */\r
-\r
-#define USART_IrDAMode_LowPower ((uint16_t)0x0004)\r
-#define USART_IrDAMode_Normal ((uint16_t)0x0000)\r
-#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \\r
- ((MODE) == USART_IrDAMode_Normal))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Flags \r
- * @{\r
- */\r
-\r
-#define USART_FLAG_CTS ((uint16_t)0x0200)\r
-#define USART_FLAG_LBD ((uint16_t)0x0100)\r
-#define USART_FLAG_TXE ((uint16_t)0x0080)\r
-#define USART_FLAG_TC ((uint16_t)0x0040)\r
-#define USART_FLAG_RXNE ((uint16_t)0x0020)\r
-#define USART_FLAG_IDLE ((uint16_t)0x0010)\r
-#define USART_FLAG_ORE ((uint16_t)0x0008)\r
-#define USART_FLAG_NE ((uint16_t)0x0004)\r
-#define USART_FLAG_FE ((uint16_t)0x0002)\r
-#define USART_FLAG_PE ((uint16_t)0x0001)\r
-#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \\r
- ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \\r
- ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \\r
- ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \\r
- ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))\r
- \r
-#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
-\r
-#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x003D0901))\r
-#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)\r
-#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */ \r
-\r
-/* Function used to set the USART configuration to the default reset state ***/ \r
-void USART_DeInit(USART_TypeDef* USARTx);\r
-\r
-/* Initialization and Configuration functions *********************************/\r
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);\r
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct);\r
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);\r
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);\r
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);\r
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-\r
-/* Data transfers functions ***************************************************/ \r
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);\r
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx);\r
-\r
-/* Multi-Processor Communication functions ************************************/\r
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);\r
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);\r
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-\r
-/* LIN mode functions *********************************************************/\r
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);\r
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_SendBreak(USART_TypeDef* USARTx);\r
-\r
-/* Half-duplex mode function **************************************************/\r
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-\r
-/* Smartcard mode functions ***************************************************/\r
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);\r
-\r
-/* IrDA mode functions ********************************************************/\r
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);\r
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-\r
-/* DMA transfers management functions *****************************************/\r
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);\r
-\r
-/* Interrupts and flags management functions **********************************/\r
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);\r
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);\r
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L1xx_USART_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_wwdg.h\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file contains all the functions prototypes for the WWDG \r
- * firmware library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_WWDG_H\r
-#define __STM32L1xx_WWDG_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup WWDG\r
- * @{\r
- */ \r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup WWDG_Exported_Constants\r
- * @{\r
- */ \r
- \r
-/** @defgroup WWDG_Prescaler \r
- * @{\r
- */ \r
- \r
-#define WWDG_Prescaler_1 ((uint32_t)0x00000000)\r
-#define WWDG_Prescaler_2 ((uint32_t)0x00000080)\r
-#define WWDG_Prescaler_4 ((uint32_t)0x00000100)\r
-#define WWDG_Prescaler_8 ((uint32_t)0x00000180)\r
-#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \\r
- ((PRESCALER) == WWDG_Prescaler_2) || \\r
- ((PRESCALER) == WWDG_Prescaler_4) || \\r
- ((PRESCALER) == WWDG_Prescaler_8))\r
-#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)\r
-#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-/* Function used to set the WWDG configuration to the default reset state ****/ \r
-void WWDG_DeInit(void);\r
-\r
-/* Prescaler, Refresh window and Counter configuration functions **************/\r
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);\r
-void WWDG_SetWindowValue(uint8_t WindowValue);\r
-void WWDG_EnableIT(void);\r
-void WWDG_SetCounter(uint8_t Counter);\r
-\r
-/* WWDG activation functions **************************************************/\r
-void WWDG_Enable(uint8_t Counter);\r
-\r
-/* Interrupts and flags management functions **********************************/\r
-FlagStatus WWDG_GetFlagStatus(void);\r
-void WWDG_ClearFlag(void);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L1xx_WWDG_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
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- <td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a></span></td>\r
- </tr>\r
-<tr style="">\r
-<td style="padding: 1.5pt;">\r
-<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release\r
-Notes for STM32F10x Standard Peripherals Library Drivers\r
-(StdPeriph_Driver)</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>\r
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2010 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>\r
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
-</td>\r
-</tr>\r
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-</table>\r
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-<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">\r
-<tbody>\r
-<tr style="">\r
-<td style="padding: 0cm;" valign="top">\r
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>\r
-<ol style="margin-top: 0cm;" start="1" type="1">\r
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F10x Standard Peripherals Library\r
-Drivers update History</a><o:p></o:p></span></li>\r
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>\r
-</ol>\r
-<span style="font-family: "Times New Roman";">\r
-</span>\r
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x Standard\r
-Peripherals Library Drivers update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.3.0\r
-- 04/16/2010</span></h3>\r
-<ol style="margin-top: 0in;" start="1" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li></ol>\r
-<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x XL-density </span>devices.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">I2C driver: events description and management enhancement.</span></li></ul>\r
-<ol style="margin-top: 0in;" start="2" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li></ol>\r
-<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dbgmcu.h/.c</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">DBGMCU_Config()</span> function: add new values <span style="font-style: italic;">DBGMCU_TIMx_STOP</span> (x: 9..14) for <span style="font-style: italic;">DBGMCU_Periph</span> parameter.</span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.h/.c:\r
-updated to support Bank2 of XL-density devices (up to 1MByte of Flash\r
-memory). For more details, refer to the description provided within\r
-stm32f10x_flash.c file.</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_gpio.h/.c</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_PinRemapConfig()</span> function: add new values for <span style="font-style: italic;">GPIO_Remap</span> parameter, to support new <span style="font-style: italic;">remap for FSMC_NADV pin and TIM9..11,13,14.</span></span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_i2c.h/.c: I2C events description and management enhancement. <br></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">I2C_CheckEvent()</span>\r
-function: updated to check whether the last event contains the\r
-I2C_EVENT (instead of check whether the last event is equal to\r
-I2C_EVENT)<br></span></li></ul><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add\r
-detailed description of I2C events and how to manage them using the\r
-functions provided by this driver. For more information, refer to\r
-stm32f10x_i2c.h and stm32f10x_i2c.c files.</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_sdio.h: </span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SDIO_SetSDIOReadWaitMode() function: correct values of SDIO_ReadWaitMode parameter<br>change <br> \r
-#define\r
-SDIO_ReadWaitMode_CLK \r
- ((uint32_t)0x00000000)<br> #define\r
-SDIO_ReadWaitMode_DATA2 \r
-((uint32_t)0x00000001)<br>by<br> #define\r
-SDIO_ReadWaitMode_CLK \r
- ((uint32_t)0x00000001)<br> #define\r
-SDIO_ReadWaitMode_DATA2 \r
-((uint32_t)0x00000000)</span></li></ul></ul>\r
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0\r
-- 03/01/2010</span></h3>\r
-<ol style="margin-top: 0in;" start="1" type="1">\r
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>\r
-</ol>\r
-<ul style="margin-top: 0in;" type="disc">\r
-\r
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support\r
-for <b>STM32 Low-density Value line (STM32F100x4/6) and\r
-Medium-density Value line (STM32F100x8/B) devices</b>.</span></li>\r
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Almost\r
-peripherals drivers were updated to support Value\r
-line devices features</span></li>\r
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Drivers limitations fix and enhancements. </span><span style="font-size: 10pt;"><o:p></o:p></span></li>\r
-\r
-</ul>\r
-<ol style="margin-top: 0in;" start="2" type="1">\r
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>\r
-</ol>\r
-<ul style="margin-top: 0in;" type="disc">\r
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new\r
-firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c</span></li>\r
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.</span></li>\r
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.</span></li>\r
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: </span><span style="font-size: 10pt; font-family: Verdana;">GPIO_Remap_TIM1_DMA, </span><span style="font-size: 10pt; font-family: Verdana;">GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.</span></li>\r
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">USART\r
-driver: add support for Oversampling by 8 mode and onebit method. 2\r
-functions has been added: USART_OverSampling8Cmd() and\r
-USART_OneBitMethodCmd().<br>\r
- </span></li>\r
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">DAC\r
-driver: add new functions handling the DAC under run feature:\r
-DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus()\r
-and DAC_ClearITPendingBit().</span></li>\r
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.<br>\r
- </span></li>\r
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">FLASH\r
-driver: the FLASH_EraseOptionBytes() function updated. This is now just\r
-erasing the option bytes without modifying the RDP status either\r
-enabled or disabled.</span></li>\r
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">PWR\r
-driver: the PWR_EnterSTOPMode() function updated. When woken up from\r
-STOP mode, this function resets again the SLEEPDEEP bit in the\r
-Cortex-M3 System Control register to allow Sleep mode entering.</span></li>\r
- \r
-\r
-</ul>\r
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>\r
-<p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The\r
-enclosed firmware and all the related documentation are not covered by\r
-a License Agreement, if you need such License you can contact your\r
-local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>\r
-<p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE\r
-PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
-WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO\r
-SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR\r
-ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY\r
-CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY\r
-CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH\r
-THEIR PRODUCTS. <o:p></o:p></span></b></p>\r
-<p class="MsoNormal"><span style="color: black;"><o:p> </o:p></span></p>\r
-<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">\r
-<hr align="center" size="2" width="100%"></span></div>\r
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For\r
-complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers\r
-visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>\r
-</td>\r
-</tr>\r
-</tbody>\r
-</table>\r
-<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
-</td>\r
-</tr>\r
-</tbody>\r
-</table>\r
-</div>\r
-<p class="MsoNormal"><o:p> </o:p></p>\r
-</div>\r
-</body></html>
\ No newline at end of file
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file misc.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the miscellaneous firmware functions (add-on\r
- * to CMSIS functions).\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "misc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup MISC \r
- * @brief MISC driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup MISC_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup MISC_Private_Defines\r
- * @{\r
- */\r
-\r
-#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the priority grouping: pre-emption priority and subpriority.\r
- * @param NVIC_PriorityGroup: specifies the priority grouping bits length. \r
- * This parameter can be one of the following values:\r
- * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority\r
- * 4 bits for subpriority\r
- * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority\r
- * 3 bits for subpriority\r
- * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority\r
- * 2 bits for subpriority\r
- * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority\r
- * 1 bits for subpriority\r
- * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority\r
- * 0 bits for subpriority\r
- * @retval None\r
- */\r
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));\r
- \r
- /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */\r
- SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;\r
-}\r
-\r
-/**\r
- * @brief Initializes the NVIC peripheral according to the specified\r
- * parameters in the NVIC_InitStruct.\r
- * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains\r
- * the configuration information for the specified NVIC peripheral.\r
- * @retval None\r
- */\r
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)\r
-{\r
- uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));\r
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); \r
- assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));\r
- \r
- if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)\r
- {\r
- /* Compute the Corresponding IRQ Priority --------------------------------*/ \r
- tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;\r
- tmppre = (0x4 - tmppriority);\r
- tmpsub = tmpsub >> tmppriority;\r
-\r
- tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;\r
- tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;\r
- tmppriority = tmppriority << 0x04;\r
- \r
- NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;\r
- \r
- /* Enable the Selected IRQ Channels --------------------------------------*/\r
- NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
- }\r
- else\r
- {\r
- /* Disable the Selected IRQ Channels -------------------------------------*/\r
- NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Sets the vector table location and Offset.\r
- * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.\r
- * This parameter can be one of the following values:\r
- * @arg NVIC_VectTab_RAM\r
- * @arg NVIC_VectTab_FLASH\r
- * @param Offset: Vector Table base offset field. This value must be a multiple of 0x100.\r
- * @retval None\r
- */\r
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));\r
- assert_param(IS_NVIC_OFFSET(Offset)); \r
- \r
- SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);\r
-}\r
-\r
-/**\r
- * @brief Selects the condition for the system to enter low power mode.\r
- * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.\r
- * This parameter can be one of the following values:\r
- * @arg NVIC_LP_SEVONPEND\r
- * @arg NVIC_LP_SLEEPDEEP\r
- * @arg NVIC_LP_SLEEPONEXIT\r
- * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_NVIC_LP(LowPowerMode));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
- \r
- if (NewState != DISABLE)\r
- {\r
- SCB->SCR |= LowPowerMode;\r
- }\r
- else\r
- {\r
- SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the SysTick clock source.\r
- * @param SysTick_CLKSource: specifies the SysTick clock source.\r
- * This parameter can be one of the following values:\r
- * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.\r
- * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.\r
- * @retval None\r
- */\r
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));\r
- if (SysTick_CLKSource == SysTick_CLKSource_HCLK)\r
- {\r
- SysTick->CTRL |= SysTick_CLKSource_HCLK;\r
- }\r
- else\r
- {\r
- SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_adc.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the ADC firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_adc.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup ADC \r
- * @brief ADC driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup ADC_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Private_Defines\r
- * @{\r
- */\r
-\r
-/* ADC DISCNUM mask */\r
-#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)\r
-\r
-/* ADC DISCEN mask */\r
-#define CR1_DISCEN_Set ((uint32_t)0x00000800)\r
-#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF)\r
-\r
-/* ADC JAUTO mask */\r
-#define CR1_JAUTO_Set ((uint32_t)0x00000400)\r
-#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)\r
-\r
-/* ADC JDISCEN mask */\r
-#define CR1_JDISCEN_Set ((uint32_t)0x00001000)\r
-#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF)\r
-\r
-/* ADC AWDCH mask */\r
-#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0)\r
-\r
-/* ADC Analog watchdog enable mode mask */\r
-#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF)\r
-\r
-/* CR1 register Mask */\r
-#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF)\r
-\r
-/* ADC ADON mask */\r
-#define CR2_ADON_Set ((uint32_t)0x00000001)\r
-#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE)\r
-\r
-/* ADC DMA mask */\r
-#define CR2_DMA_Set ((uint32_t)0x00000100)\r
-#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF)\r
-\r
-/* ADC RSTCAL mask */\r
-#define CR2_RSTCAL_Set ((uint32_t)0x00000008)\r
-\r
-/* ADC CAL mask */\r
-#define CR2_CAL_Set ((uint32_t)0x00000004)\r
-\r
-/* ADC SWSTART mask */\r
-#define CR2_SWSTART_Set ((uint32_t)0x00400000)\r
-\r
-/* ADC EXTTRIG mask */\r
-#define CR2_EXTTRIG_Set ((uint32_t)0x00100000)\r
-#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF)\r
-\r
-/* ADC Software start mask */\r
-#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000)\r
-#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF)\r
-\r
-/* ADC JEXTSEL mask */\r
-#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF)\r
-\r
-/* ADC JEXTTRIG mask */\r
-#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000)\r
-#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF)\r
-\r
-/* ADC JSWSTART mask */\r
-#define CR2_JSWSTART_Set ((uint32_t)0x00200000)\r
-\r
-/* ADC injected software start mask */\r
-#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000)\r
-#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)\r
-\r
-/* ADC TSPD mask */\r
-#define CR2_TSVREFE_Set ((uint32_t)0x00800000)\r
-#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF)\r
-\r
-/* CR2 register Mask */\r
-#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD)\r
-\r
-/* ADC SQx mask */\r
-#define SQR3_SQ_Set ((uint32_t)0x0000001F)\r
-#define SQR2_SQ_Set ((uint32_t)0x0000001F)\r
-#define SQR1_SQ_Set ((uint32_t)0x0000001F)\r
-\r
-/* SQR1 register Mask */\r
-#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF)\r
-\r
-/* ADC JSQx mask */\r
-#define JSQR_JSQ_Set ((uint32_t)0x0000001F)\r
-\r
-/* ADC JL mask */\r
-#define JSQR_JL_Set ((uint32_t)0x00300000)\r
-#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF)\r
-\r
-/* ADC SMPx mask */\r
-#define SMPR1_SMP_Set ((uint32_t)0x00000007)\r
-#define SMPR2_SMP_Set ((uint32_t)0x00000007)\r
-\r
-/* ADC JDRx registers offset */\r
-#define JDR_Offset ((uint8_t)0x28)\r
-\r
-/* ADC1 DR register base address */\r
-#define DR_ADDRESS ((uint32_t)0x4001244C)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the ADCx peripheral registers to their default reset values.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @retval None\r
- */\r
-void ADC_DeInit(ADC_TypeDef* ADCx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- \r
- if (ADCx == ADC1)\r
- {\r
- /* Enable ADC1 reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);\r
- /* Release ADC1 from reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);\r
- }\r
- else if (ADCx == ADC2)\r
- {\r
- /* Enable ADC2 reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);\r
- /* Release ADC2 from reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);\r
- }\r
- else\r
- {\r
- if (ADCx == ADC3)\r
- {\r
- /* Enable ADC3 reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);\r
- /* Release ADC3 from reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the ADCx peripheral according to the specified parameters\r
- * in the ADC_InitStruct.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains\r
- * the configuration information for the specified ADC peripheral.\r
- * @retval None\r
- */\r
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)\r
-{\r
- uint32_t tmpreg1 = 0;\r
- uint8_t tmpreg2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));\r
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));\r
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));\r
- assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); \r
- assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); \r
- assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));\r
-\r
- /*---------------------------- ADCx CR1 Configuration -----------------*/\r
- /* Get the ADCx CR1 value */\r
- tmpreg1 = ADCx->CR1;\r
- /* Clear DUALMOD and SCAN bits */\r
- tmpreg1 &= CR1_CLEAR_Mask;\r
- /* Configure ADCx: Dual mode and scan conversion mode */\r
- /* Set DUALMOD bits according to ADC_Mode value */\r
- /* Set SCAN bit according to ADC_ScanConvMode value */\r
- tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));\r
- /* Write to ADCx CR1 */\r
- ADCx->CR1 = tmpreg1;\r
-\r
- /*---------------------------- ADCx CR2 Configuration -----------------*/\r
- /* Get the ADCx CR2 value */\r
- tmpreg1 = ADCx->CR2;\r
- /* Clear CONT, ALIGN and EXTSEL bits */\r
- tmpreg1 &= CR2_CLEAR_Mask;\r
- /* Configure ADCx: external trigger event and continuous conversion mode */\r
- /* Set ALIGN bit according to ADC_DataAlign value */\r
- /* Set EXTSEL bits according to ADC_ExternalTrigConv value */\r
- /* Set CONT bit according to ADC_ContinuousConvMode value */\r
- tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |\r
- ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));\r
- /* Write to ADCx CR2 */\r
- ADCx->CR2 = tmpreg1;\r
-\r
- /*---------------------------- ADCx SQR1 Configuration -----------------*/\r
- /* Get the ADCx SQR1 value */\r
- tmpreg1 = ADCx->SQR1;\r
- /* Clear L bits */\r
- tmpreg1 &= SQR1_CLEAR_Mask;\r
- /* Configure ADCx: regular channel sequence length */\r
- /* Set L bits according to ADC_NbrOfChannel value */\r
- tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);\r
- tmpreg1 |= (uint32_t)tmpreg2 << 20;\r
- /* Write to ADCx SQR1 */\r
- ADCx->SQR1 = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Fills each ADC_InitStruct member with its default value.\r
- * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.\r
- * @retval None\r
- */\r
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)\r
-{\r
- /* Reset ADC init structure parameters values */\r
- /* Initialize the ADC_Mode member */\r
- ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;\r
- /* initialize the ADC_ScanConvMode member */\r
- ADC_InitStruct->ADC_ScanConvMode = DISABLE;\r
- /* Initialize the ADC_ContinuousConvMode member */\r
- ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;\r
- /* Initialize the ADC_ExternalTrigConv member */\r
- ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;\r
- /* Initialize the ADC_DataAlign member */\r
- ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;\r
- /* Initialize the ADC_NbrOfChannel member */\r
- ADC_InitStruct->ADC_NbrOfChannel = 1;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified ADC peripheral.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param NewState: new state of the ADCx peripheral.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Set the ADON bit to wake up the ADC from power down mode */\r
- ADCx->CR2 |= CR2_ADON_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC peripheral */\r
- ADCx->CR2 &= CR2_ADON_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified ADC DMA request.\r
- * @param ADCx: where x can be 1 or 3 to select the ADC peripheral.\r
- * Note: ADC2 hasn't a DMA capability.\r
- * @param NewState: new state of the selected ADC DMA transfer.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_DMA_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC DMA request */\r
- ADCx->CR2 |= CR2_DMA_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC DMA request */\r
- ADCx->CR2 &= CR2_DMA_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified ADC interrupts.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. \r
- * This parameter can be any combination of the following values:\r
- * @arg ADC_IT_EOC: End of conversion interrupt mask\r
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask\r
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask\r
- * @param NewState: new state of the specified ADC interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)\r
-{\r
- uint8_t itmask = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_ADC_IT(ADC_IT));\r
- /* Get the ADC IT index */\r
- itmask = (uint8_t)ADC_IT;\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC interrupts */\r
- ADCx->CR1 |= itmask;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC interrupts */\r
- ADCx->CR1 &= (~(uint32_t)itmask);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Resets the selected ADC calibration registers.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @retval None\r
- */\r
-void ADC_ResetCalibration(ADC_TypeDef* ADCx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- /* Resets the selected ADC calibartion registers */ \r
- ADCx->CR2 |= CR2_RSTCAL_Set;\r
-}\r
-\r
-/**\r
- * @brief Gets the selected ADC reset calibration registers status.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @retval The new state of ADC reset calibration registers (SET or RESET).\r
- */\r
-FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- /* Check the status of RSTCAL bit */\r
- if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET)\r
- {\r
- /* RSTCAL bit is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* RSTCAL bit is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the RSTCAL bit status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Starts the selected ADC calibration process.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @retval None\r
- */\r
-void ADC_StartCalibration(ADC_TypeDef* ADCx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- /* Enable the selected ADC calibration process */ \r
- ADCx->CR2 |= CR2_CAL_Set;\r
-}\r
-\r
-/**\r
- * @brief Gets the selected ADC calibration status.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @retval The new state of ADC calibration (SET or RESET).\r
- */\r
-FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- /* Check the status of CAL bit */\r
- if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET)\r
- {\r
- /* CAL bit is set: calibration on going */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* CAL bit is reset: end of calibration */\r
- bitstatus = RESET;\r
- }\r
- /* Return the CAL bit status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the selected ADC software start conversion .\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param NewState: new state of the selected ADC software start conversion.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC conversion on external event and start the selected\r
- ADC conversion */\r
- ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC conversion on external event and stop the selected\r
- ADC conversion */\r
- ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Gets the selected ADC Software start conversion Status.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @retval The new state of ADC software start conversion (SET or RESET).\r
- */\r
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- /* Check the status of SWSTART bit */\r
- if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET)\r
- {\r
- /* SWSTART bit is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* SWSTART bit is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the SWSTART bit status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Configures the discontinuous mode for the selected ADC regular\r
- * group channel.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param Number: specifies the discontinuous mode regular channel\r
- * count value. This number must be between 1 and 8.\r
- * @retval None\r
- */\r
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)\r
-{\r
- uint32_t tmpreg1 = 0;\r
- uint32_t tmpreg2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->CR1;\r
- /* Clear the old discontinuous mode channel count */\r
- tmpreg1 &= CR1_DISCNUM_Reset;\r
- /* Set the discontinuous mode channel count */\r
- tmpreg2 = Number - 1;\r
- tmpreg1 |= tmpreg2 << 13;\r
- /* Store the new register value */\r
- ADCx->CR1 = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the discontinuous mode on regular group\r
- * channel for the specified ADC\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param NewState: new state of the selected ADC discontinuous mode\r
- * on regular group channel.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC regular discontinuous mode */\r
- ADCx->CR1 |= CR1_DISCEN_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC regular discontinuous mode */\r
- ADCx->CR1 &= CR1_DISCEN_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures for the selected ADC regular channel its corresponding\r
- * rank in the sequencer and its sample time.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_Channel: the ADC channel to configure. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_Channel_0: ADC Channel0 selected\r
- * @arg ADC_Channel_1: ADC Channel1 selected\r
- * @arg ADC_Channel_2: ADC Channel2 selected\r
- * @arg ADC_Channel_3: ADC Channel3 selected\r
- * @arg ADC_Channel_4: ADC Channel4 selected\r
- * @arg ADC_Channel_5: ADC Channel5 selected\r
- * @arg ADC_Channel_6: ADC Channel6 selected\r
- * @arg ADC_Channel_7: ADC Channel7 selected\r
- * @arg ADC_Channel_8: ADC Channel8 selected\r
- * @arg ADC_Channel_9: ADC Channel9 selected\r
- * @arg ADC_Channel_10: ADC Channel10 selected\r
- * @arg ADC_Channel_11: ADC Channel11 selected\r
- * @arg ADC_Channel_12: ADC Channel12 selected\r
- * @arg ADC_Channel_13: ADC Channel13 selected\r
- * @arg ADC_Channel_14: ADC Channel14 selected\r
- * @arg ADC_Channel_15: ADC Channel15 selected\r
- * @arg ADC_Channel_16: ADC Channel16 selected\r
- * @arg ADC_Channel_17: ADC Channel17 selected\r
- * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.\r
- * @param ADC_SampleTime: The sample time value to be set for the selected channel. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles\r
- * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles\r
- * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles\r
- * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles \r
- * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles \r
- * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles \r
- * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles \r
- * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles \r
- * @retval None\r
- */\r
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
-{\r
- uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
- assert_param(IS_ADC_REGULAR_RANK(Rank));\r
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
- /* if ADC_Channel_10 ... ADC_Channel_17 is selected */\r
- if (ADC_Channel > ADC_Channel_9)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR1;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));\r
- /* Clear the old channel sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));\r
- /* Set the new channel sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR1 = tmpreg1;\r
- }\r
- else /* ADC_Channel include in ADC_Channel_[0..9] */\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR2;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);\r
- /* Clear the old channel sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
- /* Set the new channel sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR2 = tmpreg1;\r
- }\r
- /* For Rank 1 to 6 */\r
- if (Rank < 7)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SQR3;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));\r
- /* Clear the old SQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));\r
- /* Set the SQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SQR3 = tmpreg1;\r
- }\r
- /* For Rank 7 to 12 */\r
- else if (Rank < 13)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SQR2;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));\r
- /* Clear the old SQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));\r
- /* Set the SQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SQR2 = tmpreg1;\r
- }\r
- /* For Rank 13 to 16 */\r
- else\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SQR1;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13));\r
- /* Clear the old SQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));\r
- /* Set the SQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SQR1 = tmpreg1;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the ADCx conversion through external trigger.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param NewState: new state of the selected ADC external trigger start of conversion.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC conversion on external event */\r
- ADCx->CR2 |= CR2_EXTTRIG_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC conversion on external event */\r
- ADCx->CR2 &= CR2_EXTTRIG_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Returns the last ADCx conversion result data for regular channel.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @retval The Data conversion value.\r
- */\r
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- /* Return the selected ADC conversion value */\r
- return (uint16_t) ADCx->DR;\r
-}\r
-\r
-/**\r
- * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode.\r
- * @retval The Data conversion value.\r
- */\r
-uint32_t ADC_GetDualModeConversionValue(void)\r
-{\r
- /* Return the dual mode conversion value */\r
- return (*(__IO uint32_t *) DR_ADDRESS);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the selected ADC automatic injected group\r
- * conversion after regular one.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param NewState: new state of the selected ADC auto injected conversion\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC automatic injected group conversion */\r
- ADCx->CR1 |= CR1_JAUTO_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC automatic injected group conversion */\r
- ADCx->CR1 &= CR1_JAUTO_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the discontinuous mode for injected group\r
- * channel for the specified ADC\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param NewState: new state of the selected ADC discontinuous mode\r
- * on injected group channel.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC injected discontinuous mode */\r
- ADCx->CR1 |= CR1_JDISCEN_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC injected discontinuous mode */\r
- ADCx->CR1 &= CR1_JDISCEN_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the ADCx external trigger for injected channels conversion.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)\r
- * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)\r
- * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2)\r
- * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2)\r
- * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2)\r
- * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2)\r
- * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8\r
- * capture compare4 event selected (for ADC1 and ADC2) \r
- * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only)\r
- * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only) \r
- * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only)\r
- * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only) \r
- * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only) \r
- * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not\r
- * by external trigger (for ADC1, ADC2 and ADC3)\r
- * @retval None\r
- */\r
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));\r
- /* Get the old register value */\r
- tmpreg = ADCx->CR2;\r
- /* Clear the old external event selection for injected group */\r
- tmpreg &= CR2_JEXTSEL_Reset;\r
- /* Set the external event selection for injected group */\r
- tmpreg |= ADC_ExternalTrigInjecConv;\r
- /* Store the new register value */\r
- ADCx->CR2 = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the ADCx injected channels conversion through\r
- * external trigger\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param NewState: new state of the selected ADC external trigger start of\r
- * injected conversion.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC external event selection for injected group */\r
- ADCx->CR2 |= CR2_JEXTTRIG_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC external event selection for injected group */\r
- ADCx->CR2 &= CR2_JEXTTRIG_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the selected ADC start of the injected \r
- * channels conversion.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param NewState: new state of the selected ADC software start injected conversion.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC conversion for injected group on external event and start the selected\r
- ADC injected conversion */\r
- ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC conversion on external event for injected group and stop the selected\r
- ADC injected conversion */\r
- ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Gets the selected ADC Software start injected conversion Status.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @retval The new state of ADC software start injected conversion (SET or RESET).\r
- */\r
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- /* Check the status of JSWSTART bit */\r
- if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET)\r
- {\r
- /* JSWSTART bit is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* JSWSTART bit is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the JSWSTART bit status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Configures for the selected ADC injected channel its corresponding\r
- * rank in the sequencer and its sample time.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_Channel: the ADC channel to configure. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_Channel_0: ADC Channel0 selected\r
- * @arg ADC_Channel_1: ADC Channel1 selected\r
- * @arg ADC_Channel_2: ADC Channel2 selected\r
- * @arg ADC_Channel_3: ADC Channel3 selected\r
- * @arg ADC_Channel_4: ADC Channel4 selected\r
- * @arg ADC_Channel_5: ADC Channel5 selected\r
- * @arg ADC_Channel_6: ADC Channel6 selected\r
- * @arg ADC_Channel_7: ADC Channel7 selected\r
- * @arg ADC_Channel_8: ADC Channel8 selected\r
- * @arg ADC_Channel_9: ADC Channel9 selected\r
- * @arg ADC_Channel_10: ADC Channel10 selected\r
- * @arg ADC_Channel_11: ADC Channel11 selected\r
- * @arg ADC_Channel_12: ADC Channel12 selected\r
- * @arg ADC_Channel_13: ADC Channel13 selected\r
- * @arg ADC_Channel_14: ADC Channel14 selected\r
- * @arg ADC_Channel_15: ADC Channel15 selected\r
- * @arg ADC_Channel_16: ADC Channel16 selected\r
- * @arg ADC_Channel_17: ADC Channel17 selected\r
- * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4.\r
- * @param ADC_SampleTime: The sample time value to be set for the selected channel. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles\r
- * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles\r
- * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles\r
- * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles \r
- * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles \r
- * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles \r
- * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles \r
- * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles \r
- * @retval None\r
- */\r
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
-{\r
- uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
- assert_param(IS_ADC_INJECTED_RANK(Rank));\r
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
- /* if ADC_Channel_10 ... ADC_Channel_17 is selected */\r
- if (ADC_Channel > ADC_Channel_9)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR1;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10));\r
- /* Clear the old channel sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));\r
- /* Set the new channel sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR1 = tmpreg1;\r
- }\r
- else /* ADC_Channel include in ADC_Channel_[0..9] */\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR2;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);\r
- /* Clear the old channel sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
- /* Set the new channel sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR2 = tmpreg1;\r
- }\r
- /* Rank configuration */\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->JSQR;\r
- /* Get JL value: Number = JL+1 */\r
- tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20;\r
- /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */\r
- tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));\r
- /* Clear the old JSQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */\r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));\r
- /* Set the JSQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->JSQR = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Configures the sequencer length for injected channels\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param Length: The sequencer length. \r
- * This parameter must be a number between 1 to 4.\r
- * @retval None\r
- */\r
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)\r
-{\r
- uint32_t tmpreg1 = 0;\r
- uint32_t tmpreg2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_INJECTED_LENGTH(Length));\r
- \r
- /* Get the old register value */\r
- tmpreg1 = ADCx->JSQR;\r
- /* Clear the old injected sequnence lenght JL bits */\r
- tmpreg1 &= JSQR_JL_Reset;\r
- /* Set the injected sequnence lenght JL bits */\r
- tmpreg2 = Length - 1; \r
- tmpreg1 |= tmpreg2 << 20;\r
- /* Store the new register value */\r
- ADCx->JSQR = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Set the injected channels conversion value offset\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_InjectedChannel: the ADC injected channel to set its offset. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r
- * @param Offset: the offset value for the selected ADC injected channel\r
- * This parameter must be a 12bit value.\r
- * @retval None\r
- */\r
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)\r
-{\r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
- assert_param(IS_ADC_OFFSET(Offset)); \r
- \r
- tmp = (uint32_t)ADCx;\r
- tmp += ADC_InjectedChannel;\r
- \r
- /* Set the selected injected channel data offset */\r
- *(__IO uint32_t *) tmp = (uint32_t)Offset;\r
-}\r
-\r
-/**\r
- * @brief Returns the ADC injected channel conversion result\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_InjectedChannel: the converted ADC injected channel.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r
- * @retval The Data conversion value.\r
- */\r
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)\r
-{\r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
-\r
- tmp = (uint32_t)ADCx;\r
- tmp += ADC_InjectedChannel + JDR_Offset;\r
- \r
- /* Returns the selected injected channel conversion data value */\r
- return (uint16_t) (*(__IO uint32_t*) tmp); \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the analog watchdog on single/all regular\r
- * or injected channels\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel\r
- * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel\r
- * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel\r
- * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel\r
- * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel\r
- * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels\r
- * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog\r
- * @retval None \r
- */\r
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));\r
- /* Get the old register value */\r
- tmpreg = ADCx->CR1;\r
- /* Clear AWDEN, AWDENJ and AWDSGL bits */\r
- tmpreg &= CR1_AWDMode_Reset;\r
- /* Set the analog watchdog enable mode */\r
- tmpreg |= ADC_AnalogWatchdog;\r
- /* Store the new register value */\r
- ADCx->CR1 = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Configures the high and low thresholds of the analog watchdog.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param HighThreshold: the ADC analog watchdog High threshold value.\r
- * This parameter must be a 12bit value.\r
- * @param LowThreshold: the ADC analog watchdog Low threshold value.\r
- * This parameter must be a 12bit value.\r
- * @retval None\r
- */\r
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,\r
- uint16_t LowThreshold)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_THRESHOLD(HighThreshold));\r
- assert_param(IS_ADC_THRESHOLD(LowThreshold));\r
- /* Set the ADCx high threshold */\r
- ADCx->HTR = HighThreshold;\r
- /* Set the ADCx low threshold */\r
- ADCx->LTR = LowThreshold;\r
-}\r
-\r
-/**\r
- * @brief Configures the analog watchdog guarded single channel\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_Channel: the ADC channel to configure for the analog watchdog. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_Channel_0: ADC Channel0 selected\r
- * @arg ADC_Channel_1: ADC Channel1 selected\r
- * @arg ADC_Channel_2: ADC Channel2 selected\r
- * @arg ADC_Channel_3: ADC Channel3 selected\r
- * @arg ADC_Channel_4: ADC Channel4 selected\r
- * @arg ADC_Channel_5: ADC Channel5 selected\r
- * @arg ADC_Channel_6: ADC Channel6 selected\r
- * @arg ADC_Channel_7: ADC Channel7 selected\r
- * @arg ADC_Channel_8: ADC Channel8 selected\r
- * @arg ADC_Channel_9: ADC Channel9 selected\r
- * @arg ADC_Channel_10: ADC Channel10 selected\r
- * @arg ADC_Channel_11: ADC Channel11 selected\r
- * @arg ADC_Channel_12: ADC Channel12 selected\r
- * @arg ADC_Channel_13: ADC Channel13 selected\r
- * @arg ADC_Channel_14: ADC Channel14 selected\r
- * @arg ADC_Channel_15: ADC Channel15 selected\r
- * @arg ADC_Channel_16: ADC Channel16 selected\r
- * @arg ADC_Channel_17: ADC Channel17 selected\r
- * @retval None\r
- */\r
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
- /* Get the old register value */\r
- tmpreg = ADCx->CR1;\r
- /* Clear the Analog watchdog channel select bits */\r
- tmpreg &= CR1_AWDCH_Reset;\r
- /* Set the Analog watchdog channel */\r
- tmpreg |= ADC_Channel;\r
- /* Store the new register value */\r
- ADCx->CR1 = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the temperature sensor and Vrefint channel.\r
- * @param NewState: new state of the temperature sensor.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_TempSensorVrefintCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the temperature sensor and Vrefint channel*/\r
- ADC1->CR2 |= CR2_TSVREFE_Set;\r
- }\r
- else\r
- {\r
- /* Disable the temperature sensor and Vrefint channel*/\r
- ADC1->CR2 &= CR2_TSVREFE_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified ADC flag is set or not.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_FLAG: specifies the flag to check. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_FLAG_AWD: Analog watchdog flag\r
- * @arg ADC_FLAG_EOC: End of conversion flag\r
- * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
- * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
- * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
- * @retval The new state of ADC_FLAG (SET or RESET).\r
- */\r
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_GET_FLAG(ADC_FLAG));\r
- /* Check the status of the specified ADC flag */\r
- if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)\r
- {\r
- /* ADC_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* ADC_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the ADC_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the ADCx's pending flags.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_FLAG: specifies the flag to clear. \r
- * This parameter can be any combination of the following values:\r
- * @arg ADC_FLAG_AWD: Analog watchdog flag\r
- * @arg ADC_FLAG_EOC: End of conversion flag\r
- * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
- * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
- * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
- * @retval None\r
- */\r
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));\r
- /* Clear the selected ADC flags */\r
- ADCx->SR = ~(uint32_t)ADC_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified ADC interrupt has occurred or not.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_IT: specifies the ADC interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_IT_EOC: End of conversion interrupt mask\r
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask\r
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask\r
- * @retval The new state of ADC_IT (SET or RESET).\r
- */\r
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t itmask = 0, enablestatus = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_GET_IT(ADC_IT));\r
- /* Get the ADC IT index */\r
- itmask = ADC_IT >> 8;\r
- /* Get the ADC_IT enable bit status */\r
- enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ;\r
- /* Check the status of the specified ADC interrupt */\r
- if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)\r
- {\r
- /* ADC_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* ADC_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the ADC_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the ADCx\92s interrupt pending bits.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_IT: specifies the ADC interrupt pending bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg ADC_IT_EOC: End of conversion interrupt mask\r
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask\r
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask\r
- * @retval None\r
- */\r
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
-{\r
- uint8_t itmask = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_IT(ADC_IT));\r
- /* Get the ADC IT index */\r
- itmask = (uint8_t)(ADC_IT >> 8);\r
- /* Clear the selected ADC interrupt pending bits */\r
- ADCx->SR = ~(uint32_t)itmask;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_bkp.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the BKP firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_bkp.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup BKP \r
- * @brief BKP driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup BKP_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup BKP_Private_Defines\r
- * @{\r
- */\r
-\r
-/* ------------ BKP registers bit address in the alias region --------------- */\r
-#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)\r
-\r
-/* --- CR Register ----*/\r
-\r
-/* Alias word address of TPAL bit */\r
-#define CR_OFFSET (BKP_OFFSET + 0x30)\r
-#define TPAL_BitNumber 0x01\r
-#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))\r
-\r
-/* Alias word address of TPE bit */\r
-#define TPE_BitNumber 0x00\r
-#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))\r
-\r
-/* --- CSR Register ---*/\r
-\r
-/* Alias word address of TPIE bit */\r
-#define CSR_OFFSET (BKP_OFFSET + 0x34)\r
-#define TPIE_BitNumber 0x02\r
-#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))\r
-\r
-/* Alias word address of TIF bit */\r
-#define TIF_BitNumber 0x09\r
-#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))\r
-\r
-/* Alias word address of TEF bit */\r
-#define TEF_BitNumber 0x08\r
-#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))\r
-\r
-/* ---------------------- BKP registers bit mask ------------------------ */\r
-\r
-/* RTCCR register bit mask */\r
-#define RTCCR_CAL_Mask ((uint16_t)0xFF80)\r
-#define RTCCR_Mask ((uint16_t)0xFC7F)\r
-\r
-/* CSR register bit mask */\r
-#define CSR_CTE_Set ((uint16_t)0x0001)\r
-#define CSR_CTI_Set ((uint16_t)0x0002)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup BKP_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup BKP_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup BKP_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup BKP_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the BKP peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void BKP_DeInit(void)\r
-{\r
- RCC_BackupResetCmd(ENABLE);\r
- RCC_BackupResetCmd(DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Configures the Tamper Pin active level.\r
- * @param BKP_TamperPinLevel: specifies the Tamper Pin active level.\r
- * This parameter can be one of the following values:\r
- * @arg BKP_TamperPinLevel_High: Tamper pin active on high level\r
- * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level\r
- * @retval None\r
- */\r
-void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));\r
- *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Tamper Pin activation.\r
- * @param NewState: new state of the Tamper Pin activation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void BKP_TamperPinCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Tamper Pin Interrupt.\r
- * @param NewState: new state of the Tamper Pin Interrupt.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void BKP_ITConfig(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Select the RTC output source to output on the Tamper pin.\r
- * @param BKP_RTCOutputSource: specifies the RTC output source.\r
- * This parameter can be one of the following values:\r
- * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.\r
- * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency\r
- * divided by 64 on the Tamper pin.\r
- * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on\r
- * the Tamper pin.\r
- * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on\r
- * the Tamper pin. \r
- * @retval None\r
- */\r
-void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)\r
-{\r
- uint16_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));\r
- tmpreg = BKP->RTCCR;\r
- /* Clear CCO, ASOE and ASOS bits */\r
- tmpreg &= RTCCR_Mask;\r
- \r
- /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */\r
- tmpreg |= BKP_RTCOutputSource;\r
- /* Store the new value */\r
- BKP->RTCCR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Sets RTC Clock Calibration value.\r
- * @param CalibrationValue: specifies the RTC Clock Calibration value.\r
- * This parameter must be a number between 0 and 0x7F.\r
- * @retval None\r
- */\r
-void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)\r
-{\r
- uint16_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));\r
- tmpreg = BKP->RTCCR;\r
- /* Clear CAL[6:0] bits */\r
- tmpreg &= RTCCR_CAL_Mask;\r
- /* Set CAL[6:0] bits according to CalibrationValue value */\r
- tmpreg |= CalibrationValue;\r
- /* Store the new value */\r
- BKP->RTCCR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Writes user data to the specified Data Backup Register.\r
- * @param BKP_DR: specifies the Data Backup Register.\r
- * This parameter can be BKP_DRx where x:[1, 42]\r
- * @param Data: data to write\r
- * @retval None\r
- */\r
-void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)\r
-{\r
- __IO uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_BKP_DR(BKP_DR));\r
-\r
- tmp = (uint32_t)BKP_BASE; \r
- tmp += BKP_DR;\r
-\r
- *(__IO uint32_t *) tmp = Data;\r
-}\r
-\r
-/**\r
- * @brief Reads data from the specified Data Backup Register.\r
- * @param BKP_DR: specifies the Data Backup Register.\r
- * This parameter can be BKP_DRx where x:[1, 42]\r
- * @retval The content of the specified Data Backup Register\r
- */\r
-uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)\r
-{\r
- __IO uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_BKP_DR(BKP_DR));\r
-\r
- tmp = (uint32_t)BKP_BASE; \r
- tmp += BKP_DR;\r
-\r
- return (*(__IO uint16_t *) tmp);\r
-}\r
-\r
-/**\r
- * @brief Checks whether the Tamper Pin Event flag is set or not.\r
- * @param None\r
- * @retval The new state of the Tamper Pin Event flag (SET or RESET).\r
- */\r
-FlagStatus BKP_GetFlagStatus(void)\r
-{\r
- return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);\r
-}\r
-\r
-/**\r
- * @brief Clears Tamper Pin Event pending flag.\r
- * @param None\r
- * @retval None\r
- */\r
-void BKP_ClearFlag(void)\r
-{\r
- /* Set CTE bit to clear Tamper Pin Event flag */\r
- BKP->CSR |= CSR_CTE_Set;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the Tamper Pin Interrupt has occurred or not.\r
- * @param None\r
- * @retval The new state of the Tamper Pin Interrupt (SET or RESET).\r
- */\r
-ITStatus BKP_GetITStatus(void)\r
-{\r
- return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);\r
-}\r
-\r
-/**\r
- * @brief Clears Tamper Pin Interrupt pending bit.\r
- * @param None\r
- * @retval None\r
- */\r
-void BKP_ClearITPendingBit(void)\r
-{\r
- /* Set CTI bit to clear Tamper Pin Interrupt pending bit */\r
- BKP->CSR |= CSR_CTI_Set;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_can.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the CAN firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_can.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup CAN \r
- * @brief CAN driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup CAN_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_Private_Defines\r
- * @{\r
- */\r
-\r
-/* CAN Master Control Register bits */\r
-#define MCR_INRQ ((uint32_t)0x00000001) /* Initialization request */\r
-#define MCR_SLEEP ((uint32_t)0x00000002) /* Sleep mode request */\r
-#define MCR_TXFP ((uint32_t)0x00000004) /* Transmit FIFO priority */\r
-#define MCR_RFLM ((uint32_t)0x00000008) /* Receive FIFO locked mode */\r
-#define MCR_NART ((uint32_t)0x00000010) /* No automatic retransmission */\r
-#define MCR_AWUM ((uint32_t)0x00000020) /* Automatic wake up mode */\r
-#define MCR_ABOM ((uint32_t)0x00000040) /* Automatic bus-off management */\r
-#define MCR_TTCM ((uint32_t)0x00000080) /* time triggered communication */\r
-#define MCR_RESET ((uint32_t)0x00008000) /* time triggered communication */\r
-#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */\r
-\r
-/* CAN Master Status Register bits */\r
-#define MSR_INAK ((uint32_t)0x00000001) /* Initialization acknowledge */\r
-#define MSR_WKUI ((uint32_t)0x00000008) /* Wake-up interrupt */\r
-#define MSR_SLAKI ((uint32_t)0x00000010) /* Sleep acknowledge interrupt */\r
-\r
-/* CAN Transmit Status Register bits */\r
-#define TSR_RQCP0 ((uint32_t)0x00000001) /* Request completed mailbox0 */\r
-#define TSR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of mailbox0 */\r
-#define TSR_ABRQ0 ((uint32_t)0x00000080) /* Abort request for mailbox0 */\r
-#define TSR_RQCP1 ((uint32_t)0x00000100) /* Request completed mailbox1 */\r
-#define TSR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of mailbox1 */\r
-#define TSR_ABRQ1 ((uint32_t)0x00008000) /* Abort request for mailbox1 */\r
-#define TSR_RQCP2 ((uint32_t)0x00010000) /* Request completed mailbox2 */\r
-#define TSR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of mailbox2 */\r
-#define TSR_ABRQ2 ((uint32_t)0x00800000) /* Abort request for mailbox2 */\r
-#define TSR_TME0 ((uint32_t)0x04000000) /* Transmit mailbox 0 empty */\r
-#define TSR_TME1 ((uint32_t)0x08000000) /* Transmit mailbox 1 empty */\r
-#define TSR_TME2 ((uint32_t)0x10000000) /* Transmit mailbox 2 empty */\r
-\r
-/* CAN Receive FIFO 0 Register bits */\r
-#define RF0R_FULL0 ((uint32_t)0x00000008) /* FIFO 0 full */\r
-#define RF0R_FOVR0 ((uint32_t)0x00000010) /* FIFO 0 overrun */\r
-#define RF0R_RFOM0 ((uint32_t)0x00000020) /* Release FIFO 0 output mailbox */\r
-\r
-/* CAN Receive FIFO 1 Register bits */\r
-#define RF1R_FULL1 ((uint32_t)0x00000008) /* FIFO 1 full */\r
-#define RF1R_FOVR1 ((uint32_t)0x00000010) /* FIFO 1 overrun */\r
-#define RF1R_RFOM1 ((uint32_t)0x00000020) /* Release FIFO 1 output mailbox */\r
-\r
-/* CAN Error Status Register bits */\r
-#define ESR_EWGF ((uint32_t)0x00000001) /* Error warning flag */\r
-#define ESR_EPVF ((uint32_t)0x00000002) /* Error passive flag */\r
-#define ESR_BOFF ((uint32_t)0x00000004) /* Bus-off flag */\r
-\r
-/* CAN Mailbox Transmit Request */\r
-#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */\r
-\r
-/* CAN Filter Master Register bits */\r
-#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */\r
-\r
-/* Time out for INAK bit */\r
-#define INAK_TimeOut ((uint32_t)0x0000FFFF)\r
-\r
-/* Time out for SLAK bit */\r
-#define SLAK_TimeOut ((uint32_t)0x0000FFFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the CAN peripheral registers to their default reset values.\r
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.\r
- * @retval None.\r
- */\r
-void CAN_DeInit(CAN_TypeDef* CANx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- \r
- if (CANx == CAN1)\r
- {\r
- /* Enable CAN1 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);\r
- /* Release CAN1 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);\r
- }\r
- else\r
- { \r
- /* Enable CAN2 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);\r
- /* Release CAN2 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the CAN peripheral according to the specified\r
- * parameters in the CAN_InitStruct.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that\r
- * contains the configuration information for the CAN peripheral.\r
- * @retval Constant indicates initialization succeed which will be \r
- * CANINITFAILED or CANINITOK.\r
- */\r
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)\r
-{\r
- uint8_t InitStatus = CANINITFAILED;\r
- uint32_t wait_ack = 0x00000000;\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));\r
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));\r
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));\r
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));\r
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));\r
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));\r
- assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));\r
- assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));\r
- assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));\r
- assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));\r
- assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));\r
-\r
- /* exit from sleep mode */\r
- CANx->MCR &= ~MCR_SLEEP;\r
-\r
- /* Request initialisation */\r
- CANx->MCR |= MCR_INRQ ;\r
-\r
- /* Wait the acknowledge */\r
- while (((CANx->MSR & MSR_INAK) != MSR_INAK) && (wait_ack != INAK_TimeOut))\r
- {\r
- wait_ack++;\r
- }\r
-\r
- /* ...and check acknowledged */\r
- if ((CANx->MSR & MSR_INAK) != MSR_INAK)\r
- {\r
- InitStatus = CANINITFAILED;\r
- }\r
- else \r
- {\r
- /* Set the time triggered communication mode */\r
- if (CAN_InitStruct->CAN_TTCM == ENABLE)\r
- {\r
- CANx->MCR |= MCR_TTCM;\r
- }\r
- else\r
- {\r
- CANx->MCR &= ~MCR_TTCM;\r
- }\r
-\r
- /* Set the automatic bus-off management */\r
- if (CAN_InitStruct->CAN_ABOM == ENABLE)\r
- {\r
- CANx->MCR |= MCR_ABOM;\r
- }\r
- else\r
- {\r
- CANx->MCR &= ~MCR_ABOM;\r
- }\r
-\r
- /* Set the automatic wake-up mode */\r
- if (CAN_InitStruct->CAN_AWUM == ENABLE)\r
- {\r
- CANx->MCR |= MCR_AWUM;\r
- }\r
- else\r
- {\r
- CANx->MCR &= ~MCR_AWUM;\r
- }\r
-\r
- /* Set the no automatic retransmission */\r
- if (CAN_InitStruct->CAN_NART == ENABLE)\r
- {\r
- CANx->MCR |= MCR_NART;\r
- }\r
- else\r
- {\r
- CANx->MCR &= ~MCR_NART;\r
- }\r
-\r
- /* Set the receive FIFO locked mode */\r
- if (CAN_InitStruct->CAN_RFLM == ENABLE)\r
- {\r
- CANx->MCR |= MCR_RFLM;\r
- }\r
- else\r
- {\r
- CANx->MCR &= ~MCR_RFLM;\r
- }\r
-\r
- /* Set the transmit FIFO priority */\r
- if (CAN_InitStruct->CAN_TXFP == ENABLE)\r
- {\r
- CANx->MCR |= MCR_TXFP;\r
- }\r
- else\r
- {\r
- CANx->MCR &= ~MCR_TXFP;\r
- }\r
-\r
- /* Set the bit timing register */\r
- CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) |\r
- ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) |\r
- ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);\r
-\r
- /* Request leave initialisation */\r
- CANx->MCR &= ~MCR_INRQ;\r
-\r
- /* Wait the acknowledge */\r
- wait_ack = 0x00;\r
-\r
- while (((CANx->MSR & MSR_INAK) == MSR_INAK) && (wait_ack != INAK_TimeOut))\r
- {\r
- wait_ack++;\r
- }\r
-\r
- /* ...and check acknowledged */\r
- if ((CANx->MSR & MSR_INAK) == MSR_INAK)\r
- {\r
- InitStatus = CANINITFAILED;\r
- }\r
- else\r
- {\r
- InitStatus = CANINITOK ;\r
- }\r
- }\r
-\r
- /* At this step, return the status of initialization */\r
- return InitStatus;\r
-}\r
-\r
-/**\r
- * @brief Initializes the CAN peripheral according to the specified\r
- * parameters in the CAN_FilterInitStruct.\r
- * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef\r
- * structure that contains the configuration information.\r
- * @retval None.\r
- */\r
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)\r
-{\r
- uint32_t filter_number_bit_pos = 0;\r
- /* Check the parameters */\r
- assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));\r
- assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));\r
- assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));\r
- assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));\r
- assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));\r
-\r
- filter_number_bit_pos = ((uint32_t)0x00000001) << CAN_FilterInitStruct->CAN_FilterNumber;\r
-\r
- /* Initialisation mode for the filter */\r
- CAN1->FMR |= FMR_FINIT;\r
-\r
- /* Filter Deactivation */\r
- CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;\r
-\r
- /* Filter Scale */\r
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)\r
- {\r
- /* 16-bit scale for the filter */\r
- CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;\r
-\r
- /* First 16-bit identifier and First 16-bit mask */\r
- /* Or First 16-bit identifier and Second 16-bit identifier */\r
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = \r
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |\r
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);\r
-\r
- /* Second 16-bit identifier and Second 16-bit mask */\r
- /* Or Third 16-bit identifier and Fourth 16-bit identifier */\r
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = \r
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |\r
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);\r
- }\r
-\r
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)\r
- {\r
- /* 32-bit scale for the filter */\r
- CAN1->FS1R |= filter_number_bit_pos;\r
- /* 32-bit identifier or First 32-bit identifier */\r
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = \r
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |\r
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);\r
- /* 32-bit mask or Second 32-bit identifier */\r
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = \r
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |\r
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);\r
- }\r
-\r
- /* Filter Mode */\r
- if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)\r
- {\r
- /*Id/Mask mode for the filter*/\r
- CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;\r
- }\r
- else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */\r
- {\r
- /*Identifier list mode for the filter*/\r
- CAN1->FM1R |= (uint32_t)filter_number_bit_pos;\r
- }\r
-\r
- /* Filter FIFO assignment */\r
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0)\r
- {\r
- /* FIFO 0 assignation for the filter */\r
- CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;\r
- }\r
-\r
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1)\r
- {\r
- /* FIFO 1 assignation for the filter */\r
- CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;\r
- }\r
- \r
- /* Filter activation */\r
- if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)\r
- {\r
- CAN1->FA1R |= filter_number_bit_pos;\r
- }\r
-\r
- /* Leave the initialisation mode for the filter */\r
- CAN1->FMR &= ~FMR_FINIT;\r
-}\r
-\r
-/**\r
- * @brief Fills each CAN_InitStruct member with its default value.\r
- * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which\r
- * will be initialized.\r
- * @retval None.\r
- */\r
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)\r
-{\r
- /* Reset CAN init structure parameters values */\r
- /* Initialize the time triggered communication mode */\r
- CAN_InitStruct->CAN_TTCM = DISABLE;\r
- /* Initialize the automatic bus-off management */\r
- CAN_InitStruct->CAN_ABOM = DISABLE;\r
- /* Initialize the automatic wake-up mode */\r
- CAN_InitStruct->CAN_AWUM = DISABLE;\r
- /* Initialize the no automatic retransmission */\r
- CAN_InitStruct->CAN_NART = DISABLE;\r
- /* Initialize the receive FIFO locked mode */\r
- CAN_InitStruct->CAN_RFLM = DISABLE;\r
- /* Initialize the transmit FIFO priority */\r
- CAN_InitStruct->CAN_TXFP = DISABLE;\r
- /* Initialize the CAN_Mode member */\r
- CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;\r
- /* Initialize the CAN_SJW member */\r
- CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;\r
- /* Initialize the CAN_BS1 member */\r
- CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;\r
- /* Initialize the CAN_BS2 member */\r
- CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;\r
- /* Initialize the CAN_Prescaler member */\r
- CAN_InitStruct->CAN_Prescaler = 1;\r
-}\r
-\r
-/**\r
- * @brief Select the start bank filter for slave CAN.\r
- * @note This function applies only to STM32 Connectivity line devices.\r
- * @param CAN_BankNumber: Select the start slave bank filter from 1..27.\r
- * @retval None.\r
- */\r
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber) \r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));\r
- /* enter Initialisation mode for the filter */\r
- CAN1->FMR |= FMR_FINIT;\r
- /* Select the start slave bank */\r
- CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;\r
- CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;\r
- /* Leave Initialisation mode for the filter */\r
- CAN1->FMR &= ~FMR_FINIT;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified CAN interrupts.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.\r
- * This parameter can be: CAN_IT_TME, CAN_IT_FMP0, CAN_IT_FF0,\r
- * CAN_IT_FOV0, CAN_IT_FMP1, CAN_IT_FF1,\r
- * CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV,\r
- * CAN_IT_LEC, CAN_IT_ERR, CAN_IT_WKU or\r
- * CAN_IT_SLK.\r
- * @param NewState: new state of the CAN interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_ITConfig(CAN_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected CAN interrupt */\r
- CANx->IER |= CAN_IT;\r
- }\r
- else\r
- {\r
- /* Disable the selected CAN interrupt */\r
- CANx->IER &= ~CAN_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initiates the transmission of a message.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param TxMessage: pointer to a structure which contains CAN Id, CAN\r
- * DLC and CAN datas.\r
- * @retval The number of the mailbox that is used for transmission\r
- * or CAN_NO_MB if there is no empty mailbox.\r
- */\r
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)\r
-{\r
- uint8_t transmit_mailbox = 0;\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_IDTYPE(TxMessage->IDE));\r
- assert_param(IS_CAN_RTR(TxMessage->RTR));\r
- assert_param(IS_CAN_DLC(TxMessage->DLC));\r
-\r
- /* Select one empty transmit mailbox */\r
- if ((CANx->TSR&TSR_TME0) == TSR_TME0)\r
- {\r
- transmit_mailbox = 0;\r
- }\r
- else if ((CANx->TSR&TSR_TME1) == TSR_TME1)\r
- {\r
- transmit_mailbox = 1;\r
- }\r
- else if ((CANx->TSR&TSR_TME2) == TSR_TME2)\r
- {\r
- transmit_mailbox = 2;\r
- }\r
- else\r
- {\r
- transmit_mailbox = CAN_NO_MB;\r
- }\r
-\r
- if (transmit_mailbox != CAN_NO_MB)\r
- {\r
- /* Set up the Id */\r
- CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;\r
- if (TxMessage->IDE == CAN_ID_STD)\r
- {\r
- assert_param(IS_CAN_STDID(TxMessage->StdId)); \r
- CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | TxMessage->RTR);\r
- }\r
- else\r
- {\r
- assert_param(IS_CAN_EXTID(TxMessage->ExtId));\r
- CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId<<3) | TxMessage->IDE | \r
- TxMessage->RTR);\r
- }\r
- \r
-\r
- /* Set up the DLC */\r
- TxMessage->DLC &= (uint8_t)0x0000000F;\r
- CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;\r
- CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;\r
-\r
- /* Set up the data field */\r
- CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | \r
- ((uint32_t)TxMessage->Data[2] << 16) |\r
- ((uint32_t)TxMessage->Data[1] << 8) | \r
- ((uint32_t)TxMessage->Data[0]));\r
- CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | \r
- ((uint32_t)TxMessage->Data[6] << 16) |\r
- ((uint32_t)TxMessage->Data[5] << 8) |\r
- ((uint32_t)TxMessage->Data[4]));\r
- /* Request transmission */\r
- CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;\r
- }\r
- return transmit_mailbox;\r
-}\r
-\r
-/**\r
- * @brief Checks the transmission of a message.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param TransmitMailbox: the number of the mailbox that is used for transmission.\r
- * @retval CANTXOK if the CAN driver transmits the message, CANTXFAILED in an other case.\r
- */\r
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)\r
-{\r
- /* RQCP, TXOK and TME bits */\r
- uint8_t state = 0;\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));\r
- switch (TransmitMailbox)\r
- {\r
- case (0): state |= (uint8_t)((CANx->TSR & TSR_RQCP0) << 2);\r
- state |= (uint8_t)((CANx->TSR & TSR_TXOK0) >> 0);\r
- state |= (uint8_t)((CANx->TSR & TSR_TME0) >> 26);\r
- break;\r
- case (1): state |= (uint8_t)((CANx->TSR & TSR_RQCP1) >> 6);\r
- state |= (uint8_t)((CANx->TSR & TSR_TXOK1) >> 8);\r
- state |= (uint8_t)((CANx->TSR & TSR_TME1) >> 27);\r
- break;\r
- case (2): state |= (uint8_t)((CANx->TSR & TSR_RQCP2) >> 14);\r
- state |= (uint8_t)((CANx->TSR & TSR_TXOK2) >> 16);\r
- state |= (uint8_t)((CANx->TSR & TSR_TME2) >> 28);\r
- break;\r
- default:\r
- state = CANTXFAILED;\r
- break;\r
- }\r
- switch (state)\r
- {\r
- /* transmit pending */\r
- case (0x0): state = CANTXPENDING;\r
- break;\r
- /* transmit failed */\r
- case (0x5): state = CANTXFAILED;\r
- break;\r
- /* transmit succedeed */\r
- case (0x7): state = CANTXOK;\r
- break;\r
- default:\r
- state = CANTXFAILED;\r
- break;\r
- }\r
- return state;\r
-}\r
-\r
-/**\r
- * @brief Cancels a transmit request.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. \r
- * @param Mailbox: Mailbox number.\r
- * @retval None.\r
- */\r
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));\r
- /* abort transmission */\r
- switch (Mailbox)\r
- {\r
- case (0): CANx->TSR |= TSR_ABRQ0;\r
- break;\r
- case (1): CANx->TSR |= TSR_ABRQ1;\r
- break;\r
- case (2): CANx->TSR |= TSR_ABRQ2;\r
- break;\r
- default:\r
- break;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Releases a FIFO.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. \r
- * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.\r
- * @retval None.\r
- */\r
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_FIFO(FIFONumber));\r
- /* Release FIFO0 */\r
- if (FIFONumber == CAN_FIFO0)\r
- {\r
- CANx->RF0R = RF0R_RFOM0;\r
- }\r
- /* Release FIFO1 */\r
- else /* FIFONumber == CAN_FIFO1 */\r
- {\r
- CANx->RF1R = RF1R_RFOM1;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Returns the number of pending messages.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r
- * @retval NbMessage which is the number of pending message.\r
- */\r
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)\r
-{\r
- uint8_t message_pending=0;\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_FIFO(FIFONumber));\r
- if (FIFONumber == CAN_FIFO0)\r
- {\r
- message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);\r
- }\r
- else if (FIFONumber == CAN_FIFO1)\r
- {\r
- message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);\r
- }\r
- else\r
- {\r
- message_pending = 0;\r
- }\r
- return message_pending;\r
-}\r
-\r
-/**\r
- * @brief Receives a message.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r
- * @param RxMessage: pointer to a structure receive message which \r
- * contains CAN Id, CAN DLC, CAN datas and FMI number.\r
- * @retval None.\r
- */\r
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_FIFO(FIFONumber));\r
- /* Get the Id */\r
- RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;\r
- if (RxMessage->IDE == CAN_ID_STD)\r
- {\r
- RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);\r
- }\r
- else\r
- {\r
- RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);\r
- }\r
- \r
- RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;\r
- /* Get the DLC */\r
- RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;\r
- /* Get the FMI */\r
- RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);\r
- /* Get the data field */\r
- RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;\r
- RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);\r
- RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);\r
- RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);\r
- RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;\r
- RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);\r
- RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);\r
- RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);\r
- /* Release the FIFO */\r
- CAN_FIFORelease(CANx, FIFONumber);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the DBG Freeze for CAN.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param NewState: new state of the CAN peripheral.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable Debug Freeze */\r
- CANx->MCR |= MCR_DBF;\r
- }\r
- else\r
- {\r
- /* Disable Debug Freeze */\r
- CANx->MCR &= ~MCR_DBF;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enters the low power mode.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @retval CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case.\r
- */\r
-uint8_t CAN_Sleep(CAN_TypeDef* CANx)\r
-{\r
- uint8_t sleepstatus = CANSLEEPFAILED;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- \r
- /* Request Sleep mode */\r
- CANx->MCR = (((CANx->MCR) & (uint32_t)(~MCR_INRQ)) | MCR_SLEEP);\r
- \r
- /* Sleep mode status */\r
- if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)\r
- {\r
- /* Sleep mode not entered */\r
- sleepstatus = CANSLEEPOK;\r
- }\r
- /* At this step, sleep mode status */\r
- return (uint8_t)sleepstatus;\r
-}\r
-\r
-/**\r
- * @brief Wakes the CAN up.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case.\r
- */\r
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx)\r
-{\r
- uint32_t wait_slak = SLAK_TimeOut ;\r
- uint8_t wakeupstatus = CANWAKEUPFAILED;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- \r
- /* Wake up request */\r
- CANx->MCR &= ~MCR_SLEEP;\r
- \r
- /* Sleep mode status */\r
- while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))\r
- {\r
- wait_slak--;\r
- }\r
- if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)\r
- {\r
- /* Sleep mode exited */\r
- wakeupstatus = CANWAKEUPOK;\r
- }\r
- /* At this step, sleep mode status */\r
- return (uint8_t)wakeupstatus;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified CAN flag is set or not.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param CAN_FLAG: specifies the flag to check.\r
- * This parameter can be: CAN_FLAG_EWG, CAN_FLAG_EPV or CAN_FLAG_BOF.\r
- * @retval The new state of CAN_FLAG (SET or RESET).\r
- */\r
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_FLAG(CAN_FLAG));\r
- /* Check the status of the specified CAN flag */\r
- if ((CANx->ESR & CAN_FLAG) != (uint32_t)RESET)\r
- {\r
- /* CAN_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* CAN_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the CAN_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the CAN's pending flags.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param CAN_FLAG: specifies the flag to clear.\r
- * @retval None.\r
- */\r
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_FLAG(CAN_FLAG));\r
- /* Clear the selected CAN flags */\r
- CANx->ESR &= ~CAN_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified CAN interrupt has occurred or not.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param CAN_IT: specifies the CAN interrupt source to check.\r
- * This parameter can be: CAN_IT_RQCP0, CAN_IT_RQCP1, CAN_IT_RQCP2,\r
- * CAN_IT_FF0, CAN_IT_FOV0, CAN_IT_FF1,\r
- * CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV, \r
- * CAN_IT_BOF, CAN_IT_WKU or CAN_IT_SLK.\r
- * @retval The new state of CAN_IT (SET or RESET).\r
- */\r
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)\r
-{\r
- ITStatus pendingbitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_ITStatus(CAN_IT));\r
- switch (CAN_IT)\r
- {\r
- case CAN_IT_RQCP0:\r
- pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP0);\r
- break;\r
- case CAN_IT_RQCP1:\r
- pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP1);\r
- break;\r
- case CAN_IT_RQCP2:\r
- pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP2);\r
- break;\r
- case CAN_IT_FF0:\r
- pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FULL0);\r
- break;\r
- case CAN_IT_FOV0:\r
- pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FOVR0);\r
- break;\r
- case CAN_IT_FF1:\r
- pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FULL1);\r
- break;\r
- case CAN_IT_FOV1:\r
- pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FOVR1);\r
- break;\r
- case CAN_IT_EWG:\r
- pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EWGF);\r
- break;\r
- case CAN_IT_EPV:\r
- pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EPVF);\r
- break;\r
- case CAN_IT_BOF:\r
- pendingbitstatus = CheckITStatus(CANx->ESR, ESR_BOFF);\r
- break;\r
- case CAN_IT_SLK:\r
- pendingbitstatus = CheckITStatus(CANx->MSR, MSR_SLAKI);\r
- break;\r
- case CAN_IT_WKU:\r
- pendingbitstatus = CheckITStatus(CANx->MSR, MSR_WKUI);\r
- break;\r
- default :\r
- pendingbitstatus = RESET;\r
- break;\r
- }\r
- /* Return the CAN_IT status */\r
- return pendingbitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the CAN\92s interrupt pending bits.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param CAN_IT: specifies the interrupt pending bit to clear.\r
- * @retval None.\r
- */\r
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_ITStatus(CAN_IT));\r
- switch (CAN_IT)\r
- {\r
- case CAN_IT_RQCP0:\r
- CANx->TSR = TSR_RQCP0; /* rc_w1*/\r
- break;\r
- case CAN_IT_RQCP1:\r
- CANx->TSR = TSR_RQCP1; /* rc_w1*/\r
- break;\r
- case CAN_IT_RQCP2:\r
- CANx->TSR = TSR_RQCP2; /* rc_w1*/\r
- break;\r
- case CAN_IT_FF0:\r
- CANx->RF0R = RF0R_FULL0; /* rc_w1*/\r
- break;\r
- case CAN_IT_FOV0:\r
- CANx->RF0R = RF0R_FOVR0; /* rc_w1*/\r
- break;\r
- case CAN_IT_FF1:\r
- CANx->RF1R = RF1R_FULL1; /* rc_w1*/\r
- break;\r
- case CAN_IT_FOV1:\r
- CANx->RF1R = RF1R_FOVR1; /* rc_w1*/\r
- break;\r
- case CAN_IT_EWG:\r
- CANx->ESR &= ~ ESR_EWGF; /* rw */\r
- break;\r
- case CAN_IT_EPV:\r
- CANx->ESR &= ~ ESR_EPVF; /* rw */\r
- break;\r
- case CAN_IT_BOF:\r
- CANx->ESR &= ~ ESR_BOFF; /* rw */\r
- break;\r
- case CAN_IT_WKU:\r
- CANx->MSR = MSR_WKUI; /* rc_w1*/\r
- break;\r
- case CAN_IT_SLK:\r
- CANx->MSR = MSR_SLAKI; /* rc_w1*/\r
- break;\r
- default :\r
- break;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the CAN interrupt has occurred or not.\r
- * @param CAN_Reg: specifies the CAN interrupt register to check.\r
- * @param It_Bit: specifies the interrupt source bit to check.\r
- * @retval The new state of the CAN Interrupt (SET or RESET).\r
- */\r
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)\r
-{\r
- ITStatus pendingbitstatus = RESET;\r
- \r
- if ((CAN_Reg & It_Bit) != (uint32_t)RESET)\r
- {\r
- /* CAN_IT is set */\r
- pendingbitstatus = SET;\r
- }\r
- else\r
- {\r
- /* CAN_IT is reset */\r
- pendingbitstatus = RESET;\r
- }\r
- return pendingbitstatus;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_cec.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the CEC firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_cec.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup CEC \r
- * @brief CEC driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup CEC_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup CEC_Private_Defines\r
- * @{\r
- */ \r
-\r
-/* ------------ CEC registers bit address in the alias region ----------- */\r
-#define CEC_OFFSET (CEC_BASE - PERIPH_BASE)\r
-\r
-/* --- CFGR Register ---*/\r
-\r
-/* Alias word address of PE bit */\r
-#define CFGR_OFFSET (CEC_OFFSET + 0x00)\r
-#define PE_BitNumber 0x00\r
-#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))\r
-\r
-/* Alias word address of IE bit */\r
-#define IE_BitNumber 0x01\r
-#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))\r
-\r
-/* --- CSR Register ---*/\r
-\r
-/* Alias word address of TSOM bit */\r
-#define CSR_OFFSET (CEC_OFFSET + 0x10)\r
-#define TSOM_BitNumber 0x00\r
-#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))\r
-\r
-/* Alias word address of TEOM bit */\r
-#define TEOM_BitNumber 0x01\r
-#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))\r
- \r
-#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */\r
-#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */\r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup CEC_Private_Macros\r
- * @{\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup CEC_Private_Variables\r
- * @{\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup CEC_Private_FunctionPrototypes\r
- * @{\r
- */\r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup CEC_Private_Functions\r
- * @{\r
- */ \r
-\r
-/**\r
- * @brief Deinitializes the CEC peripheral registers to their default reset \r
- * values.\r
- * @param None\r
- * @retval None\r
- */\r
-void CEC_DeInit(void)\r
-{\r
- /* Enable CEC reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); \r
- /* Release CEC from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); \r
-}\r
-\r
-\r
-/**\r
- * @brief Initializes the CEC peripheral according to the specified \r
- * parameters in the CEC_InitStruct.\r
- * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that\r
- * contains the configuration information for the specified\r
- * CEC peripheral.\r
- * @retval None\r
- */\r
-void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)\r
-{\r
- uint16_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); \r
- assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));\r
- \r
- /*---------------------------- CEC CFGR Configuration -----------------*/\r
- /* Get the CEC CFGR value */\r
- tmpreg = CEC->CFGR;\r
- \r
- /* Clear BTEM and BPEM bits */\r
- tmpreg &= CFGR_CLEAR_Mask;\r
- \r
- /* Configure CEC: Bit Timing Error and Bit Period Error */\r
- tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);\r
-\r
- /* Write to CEC CFGR register*/\r
- CEC->CFGR = tmpreg;\r
- \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified CEC peripheral.\r
- * @param NewState: new state of the CEC peripheral. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void CEC_Cmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;\r
-\r
- if(NewState == DISABLE)\r
- {\r
- /* Wait until the PE bit is cleared by hardware (Idle Line detected) */\r
- while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)\r
- {\r
- } \r
- } \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the CEC interrupt.\r
- * @param NewState: new state of the CEC interrupt.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void CEC_ITConfig(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Defines the Own Address of the CEC device.\r
- * @param CEC_OwnAddress: The CEC own address\r
- * @retval None\r
- */\r
-void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));\r
-\r
- /* Set the CEC own address */\r
- CEC->OAR = CEC_OwnAddress;\r
-}\r
-\r
-/**\r
- * @brief Sets the CEC prescaler value.\r
- * @param CEC_Prescaler: CEC prescaler new value\r
- * @retval None\r
- */\r
-void CEC_SetPrescaler(uint16_t CEC_Prescaler)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CEC_PRESCALER(CEC_Prescaler));\r
-\r
- /* Set the Prescaler value*/\r
- CEC->PRES = CEC_Prescaler;\r
-}\r
-\r
-/**\r
- * @brief Transmits single data through the CEC peripheral.\r
- * @param Data: the data to transmit.\r
- * @retval None\r
- */\r
-void CEC_SendDataByte(uint8_t Data)\r
-{ \r
- /* Transmit Data */\r
- CEC->TXD = Data ;\r
-}\r
-\r
-\r
-/**\r
- * @brief Returns the most recent received data by the CEC peripheral.\r
- * @param None\r
- * @retval The received data.\r
- */\r
-uint8_t CEC_ReceiveDataByte(void)\r
-{\r
- /* Receive Data */\r
- return (uint8_t)(CEC->RXD);\r
-}\r
-\r
-/**\r
- * @brief Starts a new message.\r
- * @param None\r
- * @retval None\r
- */\r
-void CEC_StartOfMessage(void)\r
-{ \r
- /* Starts of new message */\r
- *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;\r
-}\r
-\r
-/**\r
- * @brief Transmits message with or without an EOM bit.\r
- * @param NewState: new state of the CEC Tx End Of Message. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void CEC_EndOfMessageCmd(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- /* The data byte will be transmitted with or without an EOM bit*/\r
- *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Gets the CEC flag status\r
- * @param CEC_FLAG: specifies the CEC flag to check. \r
- * This parameter can be one of the following values:\r
- * @arg CEC_FLAG_BTE: Bit Timing Error\r
- * @arg CEC_FLAG_BPE: Bit Period Error\r
- * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error\r
- * @arg CEC_FLAG_SBE: Start Bit Error\r
- * @arg CEC_FLAG_ACKE: Block Acknowledge Error\r
- * @arg CEC_FLAG_LINE: Line Error\r
- * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error\r
- * @arg CEC_FLAG_TEOM: Tx End Of Message \r
- * @arg CEC_FLAG_TERR: Tx Error\r
- * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished\r
- * @arg CEC_FLAG_RSOM: Rx Start Of Message\r
- * @arg CEC_FLAG_REOM: Rx End Of Message\r
- * @arg CEC_FLAG_RERR: Rx Error\r
- * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished\r
- * @retval The new state of CEC_FLAG (SET or RESET)\r
- */\r
-FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) \r
-{\r
- FlagStatus bitstatus = RESET;\r
- uint32_t cecreg = 0, cecbase = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_CEC_GET_FLAG(CEC_FLAG));\r
- \r
- /* Get the CEC peripheral base address */\r
- cecbase = (uint32_t)(CEC_BASE);\r
- \r
- /* Read flag register index */\r
- cecreg = CEC_FLAG >> 28;\r
- \r
- /* Get bit[23:0] of the flag */\r
- CEC_FLAG &= FLAG_Mask;\r
- \r
- if(cecreg != 0)\r
- {\r
- /* Flag in CEC ESR Register */\r
- CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);\r
- \r
- /* Get the CEC ESR register address */\r
- cecbase += 0xC;\r
- }\r
- else\r
- {\r
- /* Get the CEC CSR register address */\r
- cecbase += 0x10;\r
- }\r
- \r
- if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)\r
- {\r
- /* CEC_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* CEC_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- \r
- /* Return the CEC_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the CEC's pending flags.\r
- * @param CEC_FLAG: specifies the flag to clear. \r
- * This parameter can be any combination of the following values:\r
- * @arg CEC_FLAG_TERR: Tx Error\r
- * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished\r
- * @arg CEC_FLAG_RSOM: Rx Start Of Message\r
- * @arg CEC_FLAG_REOM: Rx End Of Message\r
- * @arg CEC_FLAG_RERR: Rx Error\r
- * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished\r
- * @retval None\r
- */\r
-void CEC_ClearFlag(uint32_t CEC_FLAG)\r
-{ \r
- uint32_t tmp = 0x0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));\r
-\r
- tmp = CEC->CSR & 0x2;\r
- \r
- /* Clear the selected CEC flags */\r
- CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified CEC interrupt has occurred or not.\r
- * @param CEC_IT: specifies the CEC interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg CEC_IT_TERR: Tx Error\r
- * @arg CEC_IT_TBTF: Tx Block Transfer Finished\r
- * @arg CEC_IT_RERR: Rx Error\r
- * @arg CEC_IT_RBTF: Rx Block Transfer Finished\r
- * @retval The new state of CEC_IT (SET or RESET).\r
- */\r
-ITStatus CEC_GetITStatus(uint8_t CEC_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t enablestatus = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_CEC_GET_IT(CEC_IT));\r
- \r
- /* Get the CEC IT enable bit status */\r
- enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;\r
- \r
- /* Check the status of the specified CEC interrupt */\r
- if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)\r
- {\r
- /* CEC_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* CEC_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the CEC_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the CEC's interrupt pending bits.\r
- * @param CEC_IT: specifies the CEC interrupt pending bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg CEC_IT_TERR: Tx Error\r
- * @arg CEC_IT_TBTF: Tx Block Transfer Finished\r
- * @arg CEC_IT_RERR: Rx Error\r
- * @arg CEC_IT_RBTF: Rx Block Transfer Finished\r
- * @retval None\r
- */\r
-void CEC_ClearITPendingBit(uint16_t CEC_IT)\r
-{\r
- uint32_t tmp = 0x0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_CEC_GET_IT(CEC_IT));\r
- \r
- tmp = CEC->CSR & 0x2;\r
- \r
- /* Clear the selected CEC interrupt pending bits */\r
- CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);\r
-}\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_crc.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the CRC firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_crc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup CRC \r
- * @brief CRC driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup CRC_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CRC_Private_Defines\r
- * @{\r
- */\r
-\r
-/* CR register bit mask */\r
-\r
-#define CR_RESET_Set ((uint32_t)0x00000001)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CRC_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CRC_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CRC_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CRC_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Resets the CRC Data register (DR).\r
- * @param None\r
- * @retval None\r
- */\r
-void CRC_ResetDR(void)\r
-{\r
- /* Reset CRC generator */\r
- CRC->CR = CR_RESET_Set;\r
-}\r
-\r
-/**\r
- * @brief Computes the 32-bit CRC of a given data word(32-bit).\r
- * @param Data: data word(32-bit) to compute its CRC\r
- * @retval 32-bit CRC\r
- */\r
-uint32_t CRC_CalcCRC(uint32_t Data)\r
-{\r
- CRC->DR = Data;\r
- \r
- return (CRC->DR);\r
-}\r
-\r
-/**\r
- * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).\r
- * @param pBuffer: pointer to the buffer containing the data to be computed\r
- * @param BufferLength: length of the buffer to be computed \r
- * @retval 32-bit CRC\r
- */\r
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)\r
-{\r
- uint32_t index = 0;\r
- \r
- for(index = 0; index < BufferLength; index++)\r
- {\r
- CRC->DR = pBuffer[index];\r
- }\r
- return (CRC->DR);\r
-}\r
-\r
-/**\r
- * @brief Returns the current CRC value.\r
- * @param None\r
- * @retval 32-bit CRC\r
- */\r
-uint32_t CRC_GetCRC(void)\r
-{\r
- return (CRC->DR);\r
-}\r
-\r
-/**\r
- * @brief Stores a 8-bit data in the Independent Data(ID) register.\r
- * @param IDValue: 8-bit value to be stored in the ID register \r
- * @retval None\r
- */\r
-void CRC_SetIDRegister(uint8_t IDValue)\r
-{\r
- CRC->IDR = IDValue;\r
-}\r
-\r
-/**\r
- * @brief Returns the 8-bit data stored in the Independent Data(ID) register\r
- * @param None\r
- * @retval 8-bit value of the ID register \r
- */\r
-uint8_t CRC_GetIDRegister(void)\r
-{\r
- return (CRC->IDR);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_dac.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the DAC firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_dac.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup DAC \r
- * @brief DAC driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup DAC_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Private_Defines\r
- * @{\r
- */\r
-\r
-/* DAC EN mask */\r
-#define CR_EN_Set ((uint32_t)0x00000001)\r
-\r
-/* DAC DMAEN mask */\r
-#define CR_DMAEN_Set ((uint32_t)0x00001000)\r
-\r
-/* CR register Mask */\r
-#define CR_CLEAR_Mask ((uint32_t)0x00000FFE)\r
-\r
-/* DAC SWTRIG mask */\r
-#define SWTRIGR_SWTRIG_Set ((uint32_t)0x00000001)\r
-\r
-/* DAC Dual Channels SWTRIG masks */\r
-#define DUAL_SWTRIG_Set ((uint32_t)0x00000003)\r
-#define DUAL_SWTRIG_Reset ((uint32_t)0xFFFFFFFC)\r
-\r
-/* DHR registers offsets */\r
-#define DHR12R1_Offset ((uint32_t)0x00000008)\r
-#define DHR12R2_Offset ((uint32_t)0x00000014)\r
-#define DHR12RD_Offset ((uint32_t)0x00000020)\r
-\r
-/* DOR register offset */\r
-#define DOR_Offset ((uint32_t)0x0000002C)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the DAC peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void DAC_DeInit(void)\r
-{\r
- /* Enable DAC reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);\r
- /* Release DAC from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Initializes the DAC peripheral according to the specified \r
- * parameters in the DAC_InitStruct.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that\r
- * contains the configuration information for the specified DAC channel.\r
- * @retval None\r
- */\r
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)\r
-{\r
- uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
- /* Check the DAC parameters */\r
- assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));\r
- assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));\r
- assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));\r
- assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));\r
-/*---------------------------- DAC CR Configuration --------------------------*/\r
- /* Get the DAC CR value */\r
- tmpreg1 = DAC->CR;\r
- /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */\r
- tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel);\r
- /* Configure for the selected DAC channel: buffer output, trigger, wave genration,\r
- mask/amplitude for wave genration */\r
- /* Set TSELx and TENx bits according to DAC_Trigger value */\r
- /* Set WAVEx bits according to DAC_WaveGeneration value */\r
- /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ \r
- /* Set BOFFx bit according to DAC_OutputBuffer value */ \r
- tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |\r
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);\r
- /* Calculate CR register value depending on DAC_Channel */\r
- tmpreg1 |= tmpreg2 << DAC_Channel;\r
- /* Write to DAC CR */\r
- DAC->CR = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Fills each DAC_InitStruct member with its default value.\r
- * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will\r
- * be initialized.\r
- * @retval None\r
- */\r
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)\r
-{\r
-/*--------------- Reset DAC init structure parameters values -----------------*/\r
- /* Initialize the DAC_Trigger member */\r
- DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;\r
- /* Initialize the DAC_WaveGeneration member */\r
- DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;\r
- /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */\r
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;\r
- /* Initialize the DAC_OutputBuffer member */\r
- DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified DAC channel.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param NewState: new state of the DAC channel. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DAC channel */\r
- DAC->CR |= CR_EN_Set << DAC_Channel;\r
- }\r
- else\r
- {\r
- /* Disable the selected DAC channel */\r
- DAC->CR &= ~(CR_EN_Set << DAC_Channel);\r
- }\r
-}\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
-/**\r
- * @brief Enables or disables the specified DAC interrupts.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. \r
- * This parameter can be the following values:\r
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r
- * @param NewState: new state of the specified DAC interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */ \r
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) \r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_DAC_IT(DAC_IT)); \r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DAC interrupts */\r
- DAC->CR |= (DAC_IT << DAC_Channel);\r
- }\r
- else\r
- {\r
- /* Disable the selected DAC interrupts */\r
- DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));\r
- }\r
-}\r
-#endif\r
-\r
-/**\r
- * @brief Enables or disables the specified DAC channel DMA request.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param NewState: new state of the selected DAC channel DMA request.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DAC channel DMA request */\r
- DAC->CR |= CR_DMAEN_Set << DAC_Channel;\r
- }\r
- else\r
- {\r
- /* Disable the selected DAC channel DMA request */\r
- DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the selected DAC channel software trigger.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param NewState: new state of the selected DAC channel software trigger.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable software trigger for the selected DAC channel */\r
- DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4);\r
- }\r
- else\r
- {\r
- /* Disable software trigger for the selected DAC channel */\r
- DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4));\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables simultaneously the two DAC channels software\r
- * triggers.\r
- * @param NewState: new state of the DAC channels software triggers.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable software trigger for both DAC channels */\r
- DAC->SWTRIGR |= DUAL_SWTRIG_Set ;\r
- }\r
- else\r
- {\r
- /* Disable software trigger for both DAC channels */\r
- DAC->SWTRIGR &= DUAL_SWTRIG_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the selected DAC channel wave generation.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_Wave: Specifies the wave type to enable or disable.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Wave_Noise: noise wave generation\r
- * @arg DAC_Wave_Triangle: triangle wave generation\r
- * @param NewState: new state of the selected DAC channel wave generation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_WAVE(DAC_Wave)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected wave generation for the selected DAC channel */\r
- DAC->CR |= DAC_Wave << DAC_Channel;\r
- }\r
- else\r
- {\r
- /* Disable the selected wave generation for the selected DAC channel */\r
- DAC->CR &= ~(DAC_Wave << DAC_Channel);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Set the specified data holding register value for DAC channel1.\r
- * @param DAC_Align: Specifies the data alignement for DAC channel1.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Align_8b_R: 8bit right data alignement selected\r
- * @arg DAC_Align_12b_L: 12bit left data alignement selected\r
- * @arg DAC_Align_12b_R: 12bit right data alignement selected\r
- * @param Data : Data to be loaded in the selected data holding register.\r
- * @retval None\r
- */\r
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)\r
-{ \r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DAC_ALIGN(DAC_Align));\r
- assert_param(IS_DAC_DATA(Data));\r
- \r
- tmp = (uint32_t)DAC_BASE; \r
- tmp += DHR12R1_Offset + DAC_Align;\r
-\r
- /* Set the DAC channel1 selected data holding register */\r
- *(__IO uint32_t *) tmp = Data;\r
-}\r
-\r
-/**\r
- * @brief Set the specified data holding register value for DAC channel2.\r
- * @param DAC_Align: Specifies the data alignement for DAC channel2.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Align_8b_R: 8bit right data alignement selected\r
- * @arg DAC_Align_12b_L: 12bit left data alignement selected\r
- * @arg DAC_Align_12b_R: 12bit right data alignement selected\r
- * @param Data : Data to be loaded in the selected data holding register.\r
- * @retval None\r
- */\r
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)\r
-{\r
- __IO uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_DAC_ALIGN(DAC_Align));\r
- assert_param(IS_DAC_DATA(Data));\r
- \r
- tmp = (uint32_t)DAC_BASE;\r
- tmp += DHR12R2_Offset + DAC_Align;\r
-\r
- /* Set the DAC channel2 selected data holding register */\r
- *(__IO uint32_t *)tmp = Data;\r
-}\r
-\r
-/**\r
- * @brief Set the specified data holding register value for dual channel\r
- * DAC.\r
- * @param DAC_Align: Specifies the data alignement for dual channel DAC.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Align_8b_R: 8bit right data alignement selected\r
- * @arg DAC_Align_12b_L: 12bit left data alignement selected\r
- * @arg DAC_Align_12b_R: 12bit right data alignement selected\r
- * @param Data2: Data for DAC Channel2 to be loaded in the selected data \r
- * holding register.\r
- * @param Data1: Data for DAC Channel1 to be loaded in the selected data \r
- * holding register.\r
- * @retval None\r
- */\r
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)\r
-{\r
- uint32_t data = 0, tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DAC_ALIGN(DAC_Align));\r
- assert_param(IS_DAC_DATA(Data1));\r
- assert_param(IS_DAC_DATA(Data2));\r
- \r
- /* Calculate and set dual DAC data holding register value */\r
- if (DAC_Align == DAC_Align_8b_R)\r
- {\r
- data = ((uint32_t)Data2 << 8) | Data1; \r
- }\r
- else\r
- {\r
- data = ((uint32_t)Data2 << 16) | Data1;\r
- }\r
- \r
- tmp = (uint32_t)DAC_BASE;\r
- tmp += DHR12RD_Offset + DAC_Align;\r
-\r
- /* Set the dual DAC selected data holding register */\r
- *(__IO uint32_t *)tmp = data;\r
-}\r
-\r
-/**\r
- * @brief Returns the last data output value of the selected DAC cahnnel.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @retval The selected DAC channel data output value.\r
- */\r
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)\r
-{\r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- \r
- tmp = (uint32_t) DAC_BASE ;\r
- tmp += DOR_Offset + ((uint32_t)DAC_Channel >> 2);\r
- \r
- /* Returns the DAC channel data output register value */\r
- return (uint16_t) (*(__IO uint32_t*) tmp);\r
-}\r
-\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
-/**\r
- * @brief Checks whether the specified DAC flag is set or not.\r
- * @param DAC_Channel: thee selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_FLAG: specifies the flag to check. \r
- * This parameter can be only of the following value:\r
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag \r
- * @retval The new state of DAC_FLAG (SET or RESET).\r
- */\r
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_FLAG(DAC_FLAG));\r
-\r
- /* Check the status of the specified DAC flag */\r
- if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)\r
- {\r
- /* DAC_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* DAC_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the DAC_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the DAC channelx's pending flags.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_FLAG: specifies the flag to clear. \r
- * This parameter can be of the following value:\r
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag \r
- * @retval None\r
- */\r
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_FLAG(DAC_FLAG));\r
-\r
- /* Clear the selected DAC flags */\r
- DAC->SR = (DAC_FLAG << DAC_Channel);\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified DAC interrupt has occurred or not.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_IT: specifies the DAC interrupt source to check. \r
- * This parameter can be the following values:\r
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r
- * @retval The new state of DAC_IT (SET or RESET).\r
- */\r
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t enablestatus = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_IT(DAC_IT));\r
-\r
- /* Get the DAC_IT enable bit status */\r
- enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;\r
- \r
- /* Check the status of the specified DAC interrupt */\r
- if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)\r
- {\r
- /* DAC_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* DAC_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the DAC_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the DAC channelx\92s interrupt pending bits.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_IT: specifies the DAC interrupt pending bit to clear.\r
- * This parameter can be the following values:\r
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r
- * @retval None\r
- */\r
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_IT(DAC_IT)); \r
-\r
- /* Clear the selected DAC interrupt pending bits */\r
- DAC->SR = (DAC_IT << DAC_Channel);\r
-}\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_dbgmcu.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the DBGMCU firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_dbgmcu.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup DBGMCU \r
- * @brief DBGMCU driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup DBGMCU_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DBGMCU_Private_Defines\r
- * @{\r
- */\r
-\r
-#define IDCODE_DEVID_Mask ((uint32_t)0x00000FFF)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DBGMCU_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DBGMCU_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DBGMCU_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DBGMCU_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Returns the device revision identifier.\r
- * @param None\r
- * @retval Device revision identifier\r
- */\r
-uint32_t DBGMCU_GetREVID(void)\r
-{\r
- return(DBGMCU->IDCODE >> 16);\r
-}\r
-\r
-/**\r
- * @brief Returns the device identifier.\r
- * @param None\r
- * @retval Device identifier\r
- */\r
-uint32_t DBGMCU_GetDEVID(void)\r
-{\r
- return(DBGMCU->IDCODE & IDCODE_DEVID_Mask);\r
-}\r
-\r
-/**\r
- * @brief Configures the specified peripheral and low power mode behavior\r
- * when the MCU under Debug mode.\r
- * @param DBGMCU_Periph: specifies the peripheral and low power mode.\r
- * This parameter can be any combination of the following values:\r
- * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode \r
- * @arg DBGMCU_STOP: Keep debugger connection during STOP mode \r
- * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode \r
- * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted \r
- * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted \r
- * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted \r
- * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted \r
- * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted\r
- * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted\r
- * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted\r
- * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted \r
- * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted\r
- * @param NewState: new state of the specified peripheral in Debug mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- DBGMCU->CR |= DBGMCU_Periph;\r
- }\r
- else\r
- {\r
- DBGMCU->CR &= ~DBGMCU_Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_dma.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the DMA firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_dma.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup DMA \r
- * @brief DMA driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup DMA_Private_TypesDefinitions\r
- * @{\r
- */ \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Private_Defines\r
- * @{\r
- */\r
-\r
-/* DMA ENABLE mask */\r
-#define CCR_ENABLE_Set ((uint32_t)0x00000001)\r
-#define CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE)\r
-\r
-/* DMA1 Channelx interrupt pending bit masks */\r
-#define DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F)\r
-#define DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0)\r
-#define DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00)\r
-#define DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000)\r
-#define DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000)\r
-#define DMA1_Channel6_IT_Mask ((uint32_t)0x00F00000)\r
-#define DMA1_Channel7_IT_Mask ((uint32_t)0x0F000000)\r
-\r
-/* DMA2 Channelx interrupt pending bit masks */\r
-#define DMA2_Channel1_IT_Mask ((uint32_t)0x0000000F)\r
-#define DMA2_Channel2_IT_Mask ((uint32_t)0x000000F0)\r
-#define DMA2_Channel3_IT_Mask ((uint32_t)0x00000F00)\r
-#define DMA2_Channel4_IT_Mask ((uint32_t)0x0000F000)\r
-#define DMA2_Channel5_IT_Mask ((uint32_t)0x000F0000)\r
-\r
-/* DMA2 FLAG mask */\r
-#define FLAG_Mask ((uint32_t)0x10000000)\r
-\r
-/* DMA registers Masks */\r
-#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the DMAy Channelx registers to their default reset\r
- * values.\r
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and\r
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
- * @retval None\r
- */\r
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- /* Disable the selected DMAy Channelx */\r
- DMAy_Channelx->CCR &= CCR_ENABLE_Reset;\r
- /* Reset DMAy Channelx control register */\r
- DMAy_Channelx->CCR = 0;\r
- \r
- /* Reset DMAy Channelx remaining bytes register */\r
- DMAy_Channelx->CNDTR = 0;\r
- \r
- /* Reset DMAy Channelx peripheral address register */\r
- DMAy_Channelx->CPAR = 0;\r
- \r
- /* Reset DMAy Channelx memory address register */\r
- DMAy_Channelx->CMAR = 0;\r
- \r
- if (DMAy_Channelx == DMA1_Channel1)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel1 */\r
- DMA1->IFCR |= DMA1_Channel1_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel2)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel2 */\r
- DMA1->IFCR |= DMA1_Channel2_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel3)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel3 */\r
- DMA1->IFCR |= DMA1_Channel3_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel4)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel4 */\r
- DMA1->IFCR |= DMA1_Channel4_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel5)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel5 */\r
- DMA1->IFCR |= DMA1_Channel5_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel6)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel6 */\r
- DMA1->IFCR |= DMA1_Channel6_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel7)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel7 */\r
- DMA1->IFCR |= DMA1_Channel7_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA2_Channel1)\r
- {\r
- /* Reset interrupt pending bits for DMA2 Channel1 */\r
- DMA2->IFCR |= DMA2_Channel1_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA2_Channel2)\r
- {\r
- /* Reset interrupt pending bits for DMA2 Channel2 */\r
- DMA2->IFCR |= DMA2_Channel2_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA2_Channel3)\r
- {\r
- /* Reset interrupt pending bits for DMA2 Channel3 */\r
- DMA2->IFCR |= DMA2_Channel3_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA2_Channel4)\r
- {\r
- /* Reset interrupt pending bits for DMA2 Channel4 */\r
- DMA2->IFCR |= DMA2_Channel4_IT_Mask;\r
- }\r
- else\r
- { \r
- if (DMAy_Channelx == DMA2_Channel5)\r
- {\r
- /* Reset interrupt pending bits for DMA2 Channel5 */\r
- DMA2->IFCR |= DMA2_Channel5_IT_Mask;\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the DMAy Channelx according to the specified\r
- * parameters in the DMA_InitStruct.\r
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that\r
- * contains the configuration information for the specified DMA Channel.\r
- * @retval None\r
- */\r
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));\r
- assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));\r
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));\r
- assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); \r
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));\r
- assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));\r
- assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));\r
- assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));\r
- assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));\r
-\r
-/*--------------------------- DMAy Channelx CCR Configuration -----------------*/\r
- /* Get the DMAy_Channelx CCR value */\r
- tmpreg = DMAy_Channelx->CCR;\r
- /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */\r
- tmpreg &= CCR_CLEAR_Mask;\r
- /* Configure DMAy Channelx: data transfer, data size, priority level and mode */\r
- /* Set DIR bit according to DMA_DIR value */\r
- /* Set CIRC bit according to DMA_Mode value */\r
- /* Set PINC bit according to DMA_PeripheralInc value */\r
- /* Set MINC bit according to DMA_MemoryInc value */\r
- /* Set PSIZE bits according to DMA_PeripheralDataSize value */\r
- /* Set MSIZE bits according to DMA_MemoryDataSize value */\r
- /* Set PL bits according to DMA_Priority value */\r
- /* Set the MEM2MEM bit according to DMA_M2M value */\r
- tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |\r
- DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |\r
- DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |\r
- DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;\r
-\r
- /* Write to DMAy Channelx CCR */\r
- DMAy_Channelx->CCR = tmpreg;\r
-\r
-/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
- /* Write to DMAy Channelx CNDTR */\r
- DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;\r
-\r
-/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/\r
- /* Write to DMAy Channelx CPAR */\r
- DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;\r
-\r
-/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/\r
- /* Write to DMAy Channelx CMAR */\r
- DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;\r
-}\r
-\r
-/**\r
- * @brief Fills each DMA_InitStruct member with its default value.\r
- * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will\r
- * be initialized.\r
- * @retval None\r
- */\r
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)\r
-{\r
-/*-------------- Reset DMA init structure parameters values ------------------*/\r
- /* Initialize the DMA_PeripheralBaseAddr member */\r
- DMA_InitStruct->DMA_PeripheralBaseAddr = 0;\r
- /* Initialize the DMA_MemoryBaseAddr member */\r
- DMA_InitStruct->DMA_MemoryBaseAddr = 0;\r
- /* Initialize the DMA_DIR member */\r
- DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;\r
- /* Initialize the DMA_BufferSize member */\r
- DMA_InitStruct->DMA_BufferSize = 0;\r
- /* Initialize the DMA_PeripheralInc member */\r
- DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;\r
- /* Initialize the DMA_MemoryInc member */\r
- DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;\r
- /* Initialize the DMA_PeripheralDataSize member */\r
- DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;\r
- /* Initialize the DMA_MemoryDataSize member */\r
- DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;\r
- /* Initialize the DMA_Mode member */\r
- DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;\r
- /* Initialize the DMA_Priority member */\r
- DMA_InitStruct->DMA_Priority = DMA_Priority_Low;\r
- /* Initialize the DMA_M2M member */\r
- DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified DMAy Channelx.\r
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
- * @param NewState: new state of the DMAy Channelx. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DMAy Channelx */\r
- DMAy_Channelx->CCR |= CCR_ENABLE_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected DMAy Channelx */\r
- DMAy_Channelx->CCR &= CCR_ENABLE_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified DMAy Channelx interrupts.\r
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
- * @param DMA_IT: specifies the DMA interrupts sources to be enabled\r
- * or disabled. \r
- * This parameter can be any combination of the following values:\r
- * @arg DMA_IT_TC: Transfer complete interrupt mask\r
- * @arg DMA_IT_HT: Half transfer interrupt mask\r
- * @arg DMA_IT_TE: Transfer error interrupt mask\r
- * @param NewState: new state of the specified DMA interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- assert_param(IS_DMA_CONFIG_IT(DMA_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DMA interrupts */\r
- DMAy_Channelx->CCR |= DMA_IT;\r
- }\r
- else\r
- {\r
- /* Disable the selected DMA interrupts */\r
- DMAy_Channelx->CCR &= ~DMA_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Returns the number of remaining data units in the current\r
- * DMAy Channelx transfer.\r
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
- * @retval The number of remaining data units in the current DMAy Channelx\r
- * transfer.\r
- */\r
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- /* Return the number of remaining data units for DMAy Channelx */\r
- return ((uint16_t)(DMAy_Channelx->CNDTR));\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified DMAy Channelx flag is set or not.\r
- * @param DMA_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
- * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.\r
- * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.\r
- * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.\r
- * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.\r
- * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.\r
- * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.\r
- * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.\r
- * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.\r
- * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.\r
- * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.\r
- * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.\r
- * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.\r
- * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.\r
- * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.\r
- * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.\r
- * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.\r
- * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.\r
- * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.\r
- * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.\r
- * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.\r
- * @retval The new state of DMA_FLAG (SET or RESET).\r
- */\r
-FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_DMA_GET_FLAG(DMA_FLAG));\r
-\r
- /* Calculate the used DMA */\r
- if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)\r
- {\r
- /* Get DMA2 ISR register value */\r
- tmpreg = DMA2->ISR ;\r
- }\r
- else\r
- {\r
- /* Get DMA1 ISR register value */\r
- tmpreg = DMA1->ISR ;\r
- }\r
-\r
- /* Check the status of the specified DMA flag */\r
- if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)\r
- {\r
- /* DMA_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* DMA_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- \r
- /* Return the DMA_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the DMAy Channelx's pending flags.\r
- * @param DMA_FLAG: specifies the flag to clear.\r
- * This parameter can be any combination (for the same DMA) of the following values:\r
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
- * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.\r
- * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.\r
- * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.\r
- * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.\r
- * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.\r
- * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.\r
- * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.\r
- * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.\r
- * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.\r
- * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.\r
- * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.\r
- * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.\r
- * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.\r
- * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.\r
- * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.\r
- * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.\r
- * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.\r
- * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.\r
- * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.\r
- * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.\r
- * @retval None\r
- */\r
-void DMA_ClearFlag(uint32_t DMA_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));\r
- /* Calculate the used DMA */\r
-\r
- if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)\r
- {\r
- /* Clear the selected DMA flags */\r
- DMA2->IFCR = DMA_FLAG;\r
- }\r
- else\r
- {\r
- /* Clear the selected DMA flags */\r
- DMA1->IFCR = DMA_FLAG;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.\r
- * @param DMA_IT: specifies the DMA interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
- * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
- * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
- * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
- * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
- * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
- * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
- * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
- * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
- * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
- * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
- * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
- * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
- * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
- * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
- * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
- * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
- * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
- * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
- * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
- * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
- * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
- * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
- * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
- * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
- * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
- * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
- * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
- * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.\r
- * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.\r
- * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.\r
- * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.\r
- * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.\r
- * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.\r
- * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.\r
- * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.\r
- * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.\r
- * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.\r
- * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.\r
- * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.\r
- * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.\r
- * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.\r
- * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.\r
- * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.\r
- * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.\r
- * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.\r
- * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.\r
- * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.\r
- * @retval The new state of DMA_IT (SET or RESET).\r
- */\r
-ITStatus DMA_GetITStatus(uint32_t DMA_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_DMA_GET_IT(DMA_IT));\r
-\r
- /* Calculate the used DMA */\r
- if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)\r
- {\r
- /* Get DMA2 ISR register value */\r
- tmpreg = DMA2->ISR ;\r
- }\r
- else\r
- {\r
- /* Get DMA1 ISR register value */\r
- tmpreg = DMA1->ISR ;\r
- }\r
-\r
- /* Check the status of the specified DMA interrupt */\r
- if ((tmpreg & DMA_IT) != (uint32_t)RESET)\r
- {\r
- /* DMA_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* DMA_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the DMA_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the DMAy Channelx\92s interrupt pending bits.\r
- * @param DMA_IT: specifies the DMA interrupt pending bit to clear.\r
- * This parameter can be any combination (for the same DMA) of the following values:\r
- * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
- * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
- * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
- * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
- * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
- * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
- * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
- * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
- * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
- * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
- * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
- * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
- * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
- * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
- * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
- * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
- * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
- * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
- * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
- * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
- * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
- * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
- * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
- * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
- * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
- * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
- * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
- * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
- * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.\r
- * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.\r
- * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.\r
- * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.\r
- * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.\r
- * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.\r
- * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.\r
- * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.\r
- * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.\r
- * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.\r
- * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.\r
- * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.\r
- * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.\r
- * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.\r
- * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.\r
- * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.\r
- * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.\r
- * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.\r
- * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.\r
- * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.\r
- * @retval None\r
- */\r
-void DMA_ClearITPendingBit(uint32_t DMA_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_CLEAR_IT(DMA_IT));\r
-\r
- /* Calculate the used DMA */\r
- if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)\r
- {\r
- /* Clear the selected DMA interrupt pending bits */\r
- DMA2->IFCR = DMA_IT;\r
- }\r
- else\r
- {\r
- /* Clear the selected DMA interrupt pending bits */\r
- DMA1->IFCR = DMA_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_exti.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the EXTI firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_exti.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup EXTI \r
- * @brief EXTI driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup EXTI_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup EXTI_Private_Defines\r
- * @{\r
- */\r
-\r
-#define EXTI_LineNone ((uint32_t)0x00000) /* No interrupt selected */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup EXTI_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup EXTI_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup EXTI_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup EXTI_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the EXTI peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void EXTI_DeInit(void)\r
-{\r
- EXTI->IMR = 0x00000000;\r
- EXTI->EMR = 0x00000000;\r
- EXTI->RTSR = 0x00000000; \r
- EXTI->FTSR = 0x00000000; \r
- EXTI->PR = 0x000FFFFF;\r
-}\r
-\r
-/**\r
- * @brief Initializes the EXTI peripheral according to the specified\r
- * parameters in the EXTI_InitStruct.\r
- * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure\r
- * that contains the configuration information for the EXTI peripheral.\r
- * @retval None\r
- */\r
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)\r
-{\r
- uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));\r
- assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));\r
- assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); \r
- assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));\r
-\r
- tmp = (uint32_t)EXTI_BASE;\r
- \r
- if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)\r
- {\r
- /* Clear EXTI line configuration */\r
- EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;\r
- EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;\r
- \r
- tmp += EXTI_InitStruct->EXTI_Mode;\r
-\r
- *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
-\r
- /* Clear Rising Falling edge configuration */\r
- EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;\r
- EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;\r
- \r
- /* Select the trigger for the selected external interrupts */\r
- if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)\r
- {\r
- /* Rising Falling edge */\r
- EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;\r
- EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;\r
- }\r
- else\r
- {\r
- tmp = (uint32_t)EXTI_BASE;\r
- tmp += EXTI_InitStruct->EXTI_Trigger;\r
-\r
- *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
- }\r
- }\r
- else\r
- {\r
- tmp += EXTI_InitStruct->EXTI_Mode;\r
-\r
- /* Disable the selected external lines */\r
- *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Fills each EXTI_InitStruct member with its reset value.\r
- * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will\r
- * be initialized.\r
- * @retval None\r
- */\r
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)\r
-{\r
- EXTI_InitStruct->EXTI_Line = EXTI_LineNone;\r
- EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;\r
- EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;\r
- EXTI_InitStruct->EXTI_LineCmd = DISABLE;\r
-}\r
-\r
-/**\r
- * @brief Generates a Software interrupt.\r
- * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled.\r
- * This parameter can be any combination of EXTI_Linex where x can be (0..19).\r
- * @retval None\r
- */\r
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_EXTI_LINE(EXTI_Line));\r
- \r
- EXTI->SWIER |= EXTI_Line;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified EXTI line flag is set or not.\r
- * @param EXTI_Line: specifies the EXTI line flag to check.\r
- * This parameter can be:\r
- * @arg EXTI_Linex: External interrupt line x where x(0..19)\r
- * @retval The new state of EXTI_Line (SET or RESET).\r
- */\r
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
- \r
- if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the EXTI\92s line pending flags.\r
- * @param EXTI_Line: specifies the EXTI lines flags to clear.\r
- * This parameter can be any combination of EXTI_Linex where x can be (0..19).\r
- * @retval None\r
- */\r
-void EXTI_ClearFlag(uint32_t EXTI_Line)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_EXTI_LINE(EXTI_Line));\r
- \r
- EXTI->PR = EXTI_Line;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified EXTI line is asserted or not.\r
- * @param EXTI_Line: specifies the EXTI line to check.\r
- * This parameter can be:\r
- * @arg EXTI_Linex: External interrupt line x where x(0..19)\r
- * @retval The new state of EXTI_Line (SET or RESET).\r
- */\r
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t enablestatus = 0;\r
- /* Check the parameters */\r
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
- \r
- enablestatus = EXTI->IMR & EXTI_Line;\r
- if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the EXTI\92s line pending bits.\r
- * @param EXTI_Line: specifies the EXTI lines to clear.\r
- * This parameter can be any combination of EXTI_Linex where x can be (0..19).\r
- * @retval None\r
- */\r
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_EXTI_LINE(EXTI_Line));\r
- \r
- EXTI->PR = EXTI_Line;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_flash.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the FLASH firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_flash.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup FLASH \r
- * @brief FLASH driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup FLASH_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup FLASH_Private_Defines\r
- * @{\r
- */ \r
-\r
-/* Flash Access Control Register bits */\r
-#define ACR_LATENCY_Mask ((uint32_t)0x00000038)\r
-#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)\r
-#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)\r
-\r
-/* Flash Access Control Register bits */\r
-#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) \r
-\r
-/* Flash Control Register bits */\r
-#define CR_PG_Set ((uint32_t)0x00000001)\r
-#define CR_PG_Reset ((uint32_t)0x00001FFE) \r
-#define CR_PER_Set ((uint32_t)0x00000002)\r
-#define CR_PER_Reset ((uint32_t)0x00001FFD)\r
-#define CR_MER_Set ((uint32_t)0x00000004)\r
-#define CR_MER_Reset ((uint32_t)0x00001FFB)\r
-#define CR_OPTPG_Set ((uint32_t)0x00000010)\r
-#define CR_OPTPG_Reset ((uint32_t)0x00001FEF)\r
-#define CR_OPTER_Set ((uint32_t)0x00000020)\r
-#define CR_OPTER_Reset ((uint32_t)0x00001FDF)\r
-#define CR_STRT_Set ((uint32_t)0x00000040)\r
-#define CR_LOCK_Set ((uint32_t)0x00000080)\r
-\r
-/* FLASH Mask */\r
-#define RDPRT_Mask ((uint32_t)0x00000002)\r
-#define WRP0_Mask ((uint32_t)0x000000FF)\r
-#define WRP1_Mask ((uint32_t)0x0000FF00)\r
-#define WRP2_Mask ((uint32_t)0x00FF0000)\r
-#define WRP3_Mask ((uint32_t)0xFF000000)\r
-#define OB_USER_BFB2 ((uint16_t)0x0008)\r
-\r
-/* FLASH Keys */\r
-#define RDP_Key ((uint16_t)0x00A5)\r
-#define FLASH_KEY1 ((uint32_t)0x45670123)\r
-#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)\r
-\r
-/* FLASH BANK address */\r
-#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)\r
-\r
-/* Delay definition */ \r
-#define EraseTimeout ((uint32_t)0x000B0000)\r
-#define ProgramTimeout ((uint32_t)0x00002000)\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup FLASH_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup FLASH_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup FLASH_Private_FunctionPrototypes\r
- * @{\r
- */\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASH_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
-@code \r
- \r
- This driver provides functions to configure and program the Flash memory of all STM32F10x devices,\r
- including the latest STM32F10x_XL density devices. \r
-\r
- STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability:\r
- - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each)\r
- - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each)\r
- While other STM32F10x devices features only one bank with memory up to 512 Kbytes.\r
-\r
- In version V3.3.0, some functions were updated and new ones were added to support\r
- STM32F10x_XL devices. Thus some functions manages all devices, while other are \r
- dedicated for XL devices only.\r
- \r
- The table below presents the list of available functions depending on the used STM32F10x devices. \r
- \r
- ***************************************************\r
- * Legacy functions used for all STM32F10x devices *\r
- ***************************************************\r
- +----------------------------------------------------------------------------------------------------------------------------------+\r
- | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |\r
- | | devices | devices | |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_SetLatency | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_HalfCycleAccessCmd | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_PrefetchBufferCmd | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. |\r
- | | | | - For other devices: unlock Bank1 and it is equivalent |\r
- | | | | to FLASH_UnlockBank1 function. |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. |\r
- | | | | - For other devices: lock Bank1 and it is equivalent |\r
- | | | | to FLASH_LockBank1 function. |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 |\r
- | | | | - For other devices: erase a page in Bank1 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 |\r
- | | | | - For other devices: erase all pages in Bank1 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_EraseOptionBytes | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_ProgramOptionByteData | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_EnableWriteProtection | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_ReadOutProtection | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_UserOptionByteConfig | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_GetUserOptionByte | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_GetReadOutProtectionStatus | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_GetPrefetchBufferStatus | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts|\r
- | | | | - For other devices: enable Bank1's interrupts |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status|\r
- | | | | - For other devices: return Bank1's flag status |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag |\r
- | | | | - For other devices: clear Bank1's flag |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) |\r
- | | | | equivalent to FLASH_GetBank1Status function |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) |\r
- | | | | equivalent to: FLASH_WaitForLastBank1Operation function |\r
- +----------------------------------------------------------------------------------------------------------------------------------+\r
-\r
- ************************************************************************************************************************\r
- * New functions used for all STM32F10x devices to manage Bank1: *\r
- * - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 *\r
- * - For other devices, these functions are optional (covered by functions listed above) *\r
- ************************************************************************************************************************\r
- +----------------------------------------------------------------------------------------------------------------------------------+\r
- | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |\r
- | | devices | devices | |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- | FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_LockBank1 | Yes | Yes | - Lock Bank1 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- | FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- | FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- | FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation |\r
- +----------------------------------------------------------------------------------------------------------------------------------+\r
-\r
- *****************************************************************************\r
- * New Functions used only with STM32F10x_XL density devices to manage Bank2 *\r
- *****************************************************************************\r
- +----------------------------------------------------------------------------------------------------------------------------------+\r
- | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |\r
- | | devices | devices | |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- | FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_LockBank2 | Yes | No | - Lock Bank2 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- | FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- | FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- | FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- | FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 |\r
- +----------------------------------------------------------------------------------------------------------------------------------+\r
-@endcode\r
-*/\r
-\r
-\r
-/**\r
- * @brief Sets the code latency value.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param FLASH_Latency: specifies the FLASH Latency value.\r
- * This parameter can be one of the following values:\r
- * @arg FLASH_Latency_0: FLASH Zero Latency cycle\r
- * @arg FLASH_Latency_1: FLASH One Latency cycle\r
- * @arg FLASH_Latency_2: FLASH Two Latency cycles\r
- * @retval None\r
- */\r
-void FLASH_SetLatency(uint32_t FLASH_Latency)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_LATENCY(FLASH_Latency));\r
- \r
- /* Read the ACR register */\r
- tmpreg = FLASH->ACR; \r
- \r
- /* Sets the Latency value */\r
- tmpreg &= ACR_LATENCY_Mask;\r
- tmpreg |= FLASH_Latency;\r
- \r
- /* Write the ACR register */\r
- FLASH->ACR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Half cycle flash access.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.\r
- * This parameter can be one of the following values:\r
- * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable\r
- * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable\r
- * @retval None\r
- */\r
-void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));\r
- \r
- /* Enable or disable the Half cycle access */\r
- FLASH->ACR &= ACR_HLFCYA_Mask;\r
- FLASH->ACR |= FLASH_HalfCycleAccess;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Prefetch Buffer.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status.\r
- * This parameter can be one of the following values:\r
- * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable\r
- * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable\r
- * @retval None\r
- */\r
-void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));\r
- \r
- /* Enable or disable the Prefetch Buffer */\r
- FLASH->ACR &= ACR_PRFTBE_Mask;\r
- FLASH->ACR |= FLASH_PrefetchBuffer;\r
-}\r
-\r
-/**\r
- * @brief Unlocks the FLASH Program Erase Controller.\r
- * @note This function can be used for all STM32F10x devices.\r
- * - For STM32F10X_XL devices this function unlocks Bank1 and Bank2.\r
- * - For all other devices it unlocks Bank1 and it is equivalent \r
- * to FLASH_UnlockBank1 function.. \r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_Unlock(void)\r
-{\r
- /* Authorize the FPEC of Bank1 Access */\r
- FLASH->KEYR = FLASH_KEY1;\r
- FLASH->KEYR = FLASH_KEY2;\r
-\r
-#ifdef STM32F10X_XL\r
- /* Authorize the FPEC of Bank2 Access */\r
- FLASH->KEYR2 = FLASH_KEY1;\r
- FLASH->KEYR2 = FLASH_KEY2;\r
-#endif /* STM32F10X_XL */\r
-}\r
-/**\r
- * @brief Unlocks the FLASH Bank1 Program Erase Controller.\r
- * @note This function can be used for all STM32F10x devices.\r
- * - For STM32F10X_XL devices this function unlocks Bank1.\r
- * - For all other devices it unlocks Bank1 and it is \r
- * equivalent to FLASH_Unlock function.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_UnlockBank1(void)\r
-{\r
- /* Authorize the FPEC of Bank1 Access */\r
- FLASH->KEYR = FLASH_KEY1;\r
- FLASH->KEYR = FLASH_KEY2;\r
-}\r
-\r
-#ifdef STM32F10X_XL\r
-/**\r
- * @brief Unlocks the FLASH Bank2 Program Erase Controller.\r
- * @note This function can be used only for STM32F10X_XL density devices.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_UnlockBank2(void)\r
-{\r
- /* Authorize the FPEC of Bank2 Access */\r
- FLASH->KEYR2 = FLASH_KEY1;\r
- FLASH->KEYR2 = FLASH_KEY2;\r
-\r
-}\r
-#endif /* STM32F10X_XL */\r
-\r
-/**\r
- * @brief Locks the FLASH Program Erase Controller.\r
- * @note This function can be used for all STM32F10x devices.\r
- * - For STM32F10X_XL devices this function Locks Bank1 and Bank2.\r
- * - For all other devices it Locks Bank1 and it is equivalent \r
- * to FLASH_LockBank1 function.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_Lock(void)\r
-{\r
- /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */\r
- FLASH->CR |= CR_LOCK_Set;\r
-\r
-#ifdef STM32F10X_XL\r
- /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */\r
- FLASH->CR2 |= CR_LOCK_Set;\r
-#endif /* STM32F10X_XL */\r
-}\r
-\r
-/**\r
- * @brief Locks the FLASH Bank1 Program Erase Controller.\r
- * @note this function can be used for all STM32F10x devices.\r
- * - For STM32F10X_XL devices this function Locks Bank1.\r
- * - For all other devices it Locks Bank1 and it is equivalent \r
- * to FLASH_Lock function.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_LockBank1(void)\r
-{\r
- /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */\r
- FLASH->CR |= CR_LOCK_Set;\r
-}\r
-\r
-#ifdef STM32F10X_XL\r
-/**\r
- * @brief Locks the FLASH Bank2 Program Erase Controller.\r
- * @note This function can be used only for STM32F10X_XL density devices.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_LockBank2(void)\r
-{\r
- /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */\r
- FLASH->CR2 |= CR_LOCK_Set;\r
-}\r
-#endif /* STM32F10X_XL */\r
-\r
-/**\r
- * @brief Erases a specified FLASH page.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param Page_Address: The page address to be erased.\r
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_ADDRESS(Page_Address));\r
-\r
-#ifdef STM32F10X_XL\r
- if(Page_Address < FLASH_BANK1_END_ADDRESS) \r
- {\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
- if(status == FLASH_COMPLETE)\r
- { \r
- /* if the previous operation is completed, proceed to erase the page */\r
- FLASH->CR|= CR_PER_Set;\r
- FLASH->AR = Page_Address; \r
- FLASH->CR|= CR_STRT_Set;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the erase operation is completed, disable the PER Bit */\r
- FLASH->CR &= CR_PER_Reset;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
- if(status == FLASH_COMPLETE)\r
- { \r
- /* if the previous operation is completed, proceed to erase the page */\r
- FLASH->CR2|= CR_PER_Set;\r
- FLASH->AR2 = Page_Address; \r
- FLASH->CR2|= CR_STRT_Set;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the erase operation is completed, disable the PER Bit */\r
- FLASH->CR2 &= CR_PER_Reset;\r
- }\r
- }\r
- }\r
-#else\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(EraseTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- { \r
- /* if the previous operation is completed, proceed to erase the page */\r
- FLASH->CR|= CR_PER_Set;\r
- FLASH->AR = Page_Address; \r
- FLASH->CR|= CR_STRT_Set;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(EraseTimeout);\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the erase operation is completed, disable the PER Bit */\r
- FLASH->CR &= CR_PER_Reset;\r
- }\r
- }\r
-#endif /* STM32F10X_XL */\r
-\r
- /* Return the Erase Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Erases all FLASH pages.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param None\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_EraseAllPages(void)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
-\r
-#ifdef STM32F10X_XL\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to erase all pages */\r
- FLASH->CR |= CR_MER_Set;\r
- FLASH->CR |= CR_STRT_Set;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the erase operation is completed, disable the MER Bit */\r
- FLASH->CR &= CR_MER_Reset;\r
- }\r
- } \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to erase all pages */\r
- FLASH->CR2 |= CR_MER_Set;\r
- FLASH->CR2 |= CR_STRT_Set;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the erase operation is completed, disable the MER Bit */\r
- FLASH->CR2 &= CR_MER_Reset;\r
- }\r
- }\r
-#else\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(EraseTimeout);\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to erase all pages */\r
- FLASH->CR |= CR_MER_Set;\r
- FLASH->CR |= CR_STRT_Set;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(EraseTimeout);\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the erase operation is completed, disable the MER Bit */\r
- FLASH->CR &= CR_MER_Reset;\r
- }\r
- }\r
-#endif /* STM32F10X_XL */\r
-\r
- /* Return the Erase Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Erases all Bank1 FLASH pages.\r
- * @note This function can be used for all STM32F10x devices.\r
- * - For STM32F10X_XL devices this function erases all Bank1 pages.\r
- * - For all other devices it erases all Bank1 pages and it is equivalent \r
- * to FLASH_EraseAllPages function.\r
- * @param None\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_EraseAllBank1Pages(void)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to erase all pages */\r
- FLASH->CR |= CR_MER_Set;\r
- FLASH->CR |= CR_STRT_Set;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the erase operation is completed, disable the MER Bit */\r
- FLASH->CR &= CR_MER_Reset;\r
- }\r
- } \r
- /* Return the Erase Status */\r
- return status;\r
-}\r
-\r
-#ifdef STM32F10X_XL\r
-/**\r
- * @brief Erases all Bank2 FLASH pages.\r
- * @note This function can be used only for STM32F10x_XL density devices.\r
- * @param None\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_EraseAllBank2Pages(void)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to erase all pages */\r
- FLASH->CR2 |= CR_MER_Set;\r
- FLASH->CR2 |= CR_STRT_Set;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the erase operation is completed, disable the MER Bit */\r
- FLASH->CR2 &= CR_MER_Reset;\r
- }\r
- } \r
- /* Return the Erase Status */\r
- return status;\r
-}\r
-#endif /* STM32F10X_XL */\r
-\r
-/**\r
- * @brief Erases the FLASH option bytes.\r
- * @note This functions erases all option bytes except the Read protection (RDP). \r
- * @note This function can be used for all STM32F10x devices.\r
- * @param None\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_EraseOptionBytes(void)\r
-{\r
- uint16_t rdptmp = RDP_Key;\r
-\r
- FLASH_Status status = FLASH_COMPLETE;\r
-\r
- /* Get the actual read protection Option Byte value */ \r
- if(FLASH_GetReadOutProtectionStatus() != RESET)\r
- {\r
- rdptmp = 0x00; \r
- }\r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(EraseTimeout);\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* Authorize the small information block programming */\r
- FLASH->OPTKEYR = FLASH_KEY1;\r
- FLASH->OPTKEYR = FLASH_KEY2;\r
- \r
- /* if the previous operation is completed, proceed to erase the option bytes */\r
- FLASH->CR |= CR_OPTER_Set;\r
- FLASH->CR |= CR_STRT_Set;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(EraseTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the erase operation is completed, disable the OPTER Bit */\r
- FLASH->CR &= CR_OPTER_Reset;\r
- \r
- /* Enable the Option Bytes Programming operation */\r
- FLASH->CR |= CR_OPTPG_Set;\r
- /* Restore the last read protection Option Byte value */\r
- OB->RDP = (uint16_t)rdptmp; \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the program operation is completed, disable the OPTPG Bit */\r
- FLASH->CR &= CR_OPTPG_Reset;\r
- }\r
- }\r
- else\r
- {\r
- if (status != FLASH_TIMEOUT)\r
- {\r
- /* Disable the OPTPG Bit */\r
- FLASH->CR &= CR_OPTPG_Reset;\r
- }\r
- } \r
- }\r
- /* Return the erase status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Programs a word at a specified address.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param Address: specifies the address to be programmed.\r
- * @param Data: specifies the data to be programmed.\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- __IO uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_ADDRESS(Address));\r
-\r
-#ifdef STM32F10X_XL\r
- if(Address < FLASH_BANK1_END_ADDRESS - 2)\r
- { \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(ProgramTimeout); \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new first \r
- half word */\r
- FLASH->CR |= CR_PG_Set;\r
- \r
- *(__IO uint16_t*)Address = (uint16_t)Data;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new second \r
- half word */\r
- tmp = Address + 2;\r
-\r
- *(__IO uint16_t*) tmp = Data >> 16;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* Disable the PG Bit */\r
- FLASH->CR &= CR_PG_Reset;\r
- }\r
- }\r
- else\r
- {\r
- if (status != FLASH_TIMEOUT)\r
- {\r
- /* Disable the PG Bit */\r
- FLASH->CR &= CR_PG_Reset;\r
- }\r
- }\r
- }\r
- }\r
- else if(Address == (FLASH_BANK1_END_ADDRESS - 1))\r
- {\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(ProgramTimeout);\r
-\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new first \r
- half word */\r
- FLASH->CR |= CR_PG_Set;\r
- \r
- *(__IO uint16_t*)Address = (uint16_t)Data;\r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(ProgramTimeout);\r
-\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* Disable the PG Bit */\r
- FLASH->CR &= CR_PG_Reset;\r
- }\r
- }\r
- else\r
- {\r
- if (status != FLASH_TIMEOUT)\r
- {\r
- /* Disable the PG Bit */\r
- FLASH->CR &= CR_PG_Reset;\r
- }\r
- }\r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
-\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new second \r
- half word */\r
- FLASH->CR2 |= CR_PG_Set;\r
- tmp = Address + 2;\r
-\r
- *(__IO uint16_t*) tmp = Data >> 16;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
- \r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* Disable the PG Bit */\r
- FLASH->CR2 &= CR_PG_Reset;\r
- }\r
- }\r
- else\r
- {\r
- if (status != FLASH_TIMEOUT)\r
- {\r
- /* Disable the PG Bit */\r
- FLASH->CR2 &= CR_PG_Reset;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
-\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new first \r
- half word */\r
- FLASH->CR2 |= CR_PG_Set;\r
- \r
- *(__IO uint16_t*)Address = (uint16_t)Data;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new second \r
- half word */\r
- tmp = Address + 2;\r
-\r
- *(__IO uint16_t*) tmp = Data >> 16;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
- \r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* Disable the PG Bit */\r
- FLASH->CR2 &= CR_PG_Reset;\r
- }\r
- }\r
- else\r
- {\r
- if (status != FLASH_TIMEOUT)\r
- {\r
- /* Disable the PG Bit */\r
- FLASH->CR2 &= CR_PG_Reset;\r
- }\r
- }\r
- }\r
- }\r
-#else\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new first \r
- half word */\r
- FLASH->CR |= CR_PG_Set;\r
- \r
- *(__IO uint16_t*)Address = (uint16_t)Data;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new second \r
- half word */\r
- tmp = Address + 2;\r
-\r
- *(__IO uint16_t*) tmp = Data >> 16;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* Disable the PG Bit */\r
- FLASH->CR &= CR_PG_Reset;\r
- }\r
- }\r
- else\r
- {\r
- if (status != FLASH_TIMEOUT)\r
- {\r
- /* Disable the PG Bit */\r
- FLASH->CR &= CR_PG_Reset;\r
- }\r
- }\r
- } \r
-#endif /* STM32F10X_XL */\r
- \r
- /* Return the Program Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Programs a half word at a specified address.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param Address: specifies the address to be programmed.\r
- * @param Data: specifies the data to be programmed.\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_ADDRESS(Address));\r
-\r
-#ifdef STM32F10X_XL\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(Address < FLASH_BANK1_END_ADDRESS)\r
- {\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new data */\r
- FLASH->CR |= CR_PG_Set;\r
- \r
- *(__IO uint16_t*)Address = Data;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(ProgramTimeout);\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the program operation is completed, disable the PG Bit */\r
- FLASH->CR &= CR_PG_Reset;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new data */\r
- FLASH->CR2 |= CR_PG_Set;\r
- \r
- *(__IO uint16_t*)Address = Data;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the program operation is completed, disable the PG Bit */\r
- FLASH->CR2 &= CR_PG_Reset;\r
- }\r
- }\r
- }\r
-#else\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new data */\r
- FLASH->CR |= CR_PG_Set;\r
- \r
- *(__IO uint16_t*)Address = Data;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the program operation is completed, disable the PG Bit */\r
- FLASH->CR &= CR_PG_Reset;\r
- }\r
- } \r
-#endif /* STM32F10X_XL */\r
- \r
- /* Return the Program Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Programs a half word at a specified Option Byte Data address.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param Address: specifies the address to be programmed.\r
- * This parameter can be 0x1FFFF804 or 0x1FFFF806. \r
- * @param Data: specifies the data to be programmed.\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- /* Check the parameters */\r
- assert_param(IS_OB_DATA_ADDRESS(Address));\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
-\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* Authorize the small information block programming */\r
- FLASH->OPTKEYR = FLASH_KEY1;\r
- FLASH->OPTKEYR = FLASH_KEY2;\r
- /* Enables the Option Bytes Programming operation */\r
- FLASH->CR |= CR_OPTPG_Set; \r
- *(__IO uint16_t*)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the program operation is completed, disable the OPTPG Bit */\r
- FLASH->CR &= CR_OPTPG_Reset;\r
- }\r
- }\r
- /* Return the Option Byte Data Program Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Write protects the desired pages\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param FLASH_Pages: specifies the address of the pages to be write protected.\r
- * This parameter can be:\r
- * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31 \r
- * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3\r
- * and FLASH_WRProt_Pages124to127\r
- * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and\r
- * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255\r
- * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and\r
- * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127 \r
- * @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and\r
- * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511\r
- * @arg FLASH_WRProt_AllPages\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)\r
-{\r
- uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;\r
- \r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));\r
- \r
- FLASH_Pages = (uint32_t)(~FLASH_Pages);\r
- WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);\r
- WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);\r
- WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);\r
- WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* Authorizes the small information block programming */\r
- FLASH->OPTKEYR = FLASH_KEY1;\r
- FLASH->OPTKEYR = FLASH_KEY2;\r
- FLASH->CR |= CR_OPTPG_Set;\r
- if(WRP0_Data != 0xFF)\r
- {\r
- OB->WRP0 = WRP0_Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- }\r
- if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))\r
- {\r
- OB->WRP1 = WRP1_Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- }\r
- if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))\r
- {\r
- OB->WRP2 = WRP2_Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- }\r
- \r
- if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))\r
- {\r
- OB->WRP3 = WRP3_Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- }\r
- \r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the program operation is completed, disable the OPTPG Bit */\r
- FLASH->CR &= CR_OPTPG_Reset;\r
- }\r
- } \r
- /* Return the write protection operation Status */\r
- return status; \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the read out protection.\r
- * @note If the user has already programmed the other option bytes before calling \r
- * this function, he must re-program them since this function erases all option bytes.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param Newstate: new state of the ReadOut Protection.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- status = FLASH_WaitForLastOperation(EraseTimeout);\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* Authorizes the small information block programming */\r
- FLASH->OPTKEYR = FLASH_KEY1;\r
- FLASH->OPTKEYR = FLASH_KEY2;\r
- FLASH->CR |= CR_OPTER_Set;\r
- FLASH->CR |= CR_STRT_Set;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(EraseTimeout);\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the erase operation is completed, disable the OPTER Bit */\r
- FLASH->CR &= CR_OPTER_Reset;\r
- /* Enable the Option Bytes Programming operation */\r
- FLASH->CR |= CR_OPTPG_Set; \r
- if(NewState != DISABLE)\r
- {\r
- OB->RDP = 0x00;\r
- }\r
- else\r
- {\r
- OB->RDP = RDP_Key; \r
- }\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(EraseTimeout); \r
- \r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the program operation is completed, disable the OPTPG Bit */\r
- FLASH->CR &= CR_OPTPG_Reset;\r
- }\r
- }\r
- else \r
- {\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* Disable the OPTER Bit */\r
- FLASH->CR &= CR_OPTER_Reset;\r
- }\r
- }\r
- }\r
- /* Return the protection operation Status */\r
- return status; \r
-}\r
-\r
-/**\r
- * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param OB_IWDG: Selects the IWDG mode\r
- * This parameter can be one of the following values:\r
- * @arg OB_IWDG_SW: Software IWDG selected\r
- * @arg OB_IWDG_HW: Hardware IWDG selected\r
- * @param OB_STOP: Reset event when entering STOP mode.\r
- * This parameter can be one of the following values:\r
- * @arg OB_STOP_NoRST: No reset generated when entering in STOP\r
- * @arg OB_STOP_RST: Reset generated when entering in STOP\r
- * @param OB_STDBY: Reset event when entering Standby mode.\r
- * This parameter can be one of the following values:\r
- * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY\r
- * @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, \r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE; \r
-\r
- /* Check the parameters */\r
- assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));\r
- assert_param(IS_OB_STOP_SOURCE(OB_STOP));\r
- assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));\r
-\r
- /* Authorize the small information block programming */\r
- FLASH->OPTKEYR = FLASH_KEY1;\r
- FLASH->OPTKEYR = FLASH_KEY2;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- { \r
- /* Enable the Option Bytes Programming operation */\r
- FLASH->CR |= CR_OPTPG_Set; \r
- \r
- OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); \r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the program operation is completed, disable the OPTPG Bit */\r
- FLASH->CR &= CR_OPTPG_Reset;\r
- }\r
- } \r
- /* Return the Option Byte program Status */\r
- return status;\r
-}\r
-\r
-#ifdef STM32F10X_XL\r
-/**\r
- * @brief Configures to boot from Bank1 or Bank2. \r
- * @note This function can be used only for STM32F10x_XL density devices.\r
- * @param FLASH_BOOT: select the FLASH Bank to boot from.\r
- * This parameter can be one of the following values:\r
- * @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash\r
- * position and this parameter is selected the device will boot from Bank1(Default).\r
- * @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash\r
- * position and this parameter is selected the device will boot from Bank2 or Bank1,\r
- * depending on the activation of the bank. The active banks are checked in\r
- * the following order: Bank2, followed by Bank1.\r
- * The active bank is recognized by the value programmed at the base address\r
- * of the respective bank (corresponding to the initial stack pointer value\r
- * in the interrupt vector table).\r
- * For more information, please refer to AN2606 from www.st.com. \r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, \r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT)\r
-{ \r
- FLASH_Status status = FLASH_COMPLETE; \r
- assert_param(IS_FLASH_BOOT(FLASH_BOOT));\r
- /* Authorize the small information block programming */\r
- FLASH->OPTKEYR = FLASH_KEY1;\r
- FLASH->OPTKEYR = FLASH_KEY2;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- { \r
- /* Enable the Option Bytes Programming operation */\r
- FLASH->CR |= CR_OPTPG_Set; \r
-\r
- if(FLASH_BOOT == FLASH_BOOT_Bank1)\r
- {\r
- OB->USER |= OB_USER_BFB2;\r
- }\r
- else\r
- {\r
- OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2));\r
- }\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the program operation is completed, disable the OPTPG Bit */\r
- FLASH->CR &= CR_OPTPG_Reset;\r
- }\r
- } \r
- /* Return the Option Byte program Status */\r
- return status;\r
-}\r
-#endif /* STM32F10X_XL */\r
-\r
-/**\r
- * @brief Returns the FLASH User Option Bytes values.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param None\r
- * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)\r
- * and RST_STDBY(Bit2).\r
- */\r
-uint32_t FLASH_GetUserOptionByte(void)\r
-{\r
- /* Return the User Option Byte */\r
- return (uint32_t)(FLASH->OBR >> 2);\r
-}\r
-\r
-/**\r
- * @brief Returns the FLASH Write Protection Option Bytes Register value.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param None\r
- * @retval The FLASH Write Protection Option Bytes Register value\r
- */\r
-uint32_t FLASH_GetWriteProtectionOptionByte(void)\r
-{\r
- /* Return the Falsh write protection Register value */\r
- return (uint32_t)(FLASH->WRPR);\r
-}\r
-\r
-/**\r
- * @brief Checks whether the FLASH Read Out Protection Status is set or not.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param None\r
- * @retval FLASH ReadOut Protection Status(SET or RESET)\r
- */\r
-FlagStatus FLASH_GetReadOutProtectionStatus(void)\r
-{\r
- FlagStatus readoutstatus = RESET;\r
- if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)\r
- {\r
- readoutstatus = SET;\r
- }\r
- else\r
- {\r
- readoutstatus = RESET;\r
- }\r
- return readoutstatus;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the FLASH Prefetch Buffer status is set or not.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param None\r
- * @retval FLASH Prefetch Buffer Status (SET or RESET).\r
- */\r
-FlagStatus FLASH_GetPrefetchBufferStatus(void)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- \r
- if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */\r
- return bitstatus; \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified FLASH interrupts.\r
- * @note This function can be used for all STM32F10x devices.\r
- * - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts\r
- for Bank1 and Bank2.\r
- * - For other devices it enables or disables the specified FLASH interrupts for Bank1.\r
- * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg FLASH_IT_ERROR: FLASH Error Interrupt\r
- * @arg FLASH_IT_EOP: FLASH end of operation Interrupt\r
- * @param NewState: new state of the specified Flash interrupts.\r
- * This parameter can be: ENABLE or DISABLE. \r
- * @retval None \r
- */\r
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)\r
-{\r
-#ifdef STM32F10X_XL\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_IT(FLASH_IT)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if((FLASH_IT & 0x80000000) != 0x0)\r
- {\r
- if(NewState != DISABLE)\r
- {\r
- /* Enable the interrupt sources */\r
- FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF);\r
- }\r
- else\r
- {\r
- /* Disable the interrupt sources */\r
- FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF);\r
- }\r
- }\r
- else\r
- {\r
- if(NewState != DISABLE)\r
- {\r
- /* Enable the interrupt sources */\r
- FLASH->CR |= FLASH_IT;\r
- }\r
- else\r
- {\r
- /* Disable the interrupt sources */\r
- FLASH->CR &= ~(uint32_t)FLASH_IT;\r
- }\r
- }\r
-#else\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_IT(FLASH_IT)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if(NewState != DISABLE)\r
- {\r
- /* Enable the interrupt sources */\r
- FLASH->CR |= FLASH_IT;\r
- }\r
- else\r
- {\r
- /* Disable the interrupt sources */\r
- FLASH->CR &= ~(uint32_t)FLASH_IT;\r
- }\r
-#endif /* STM32F10X_XL */\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified FLASH flag is set or not.\r
- * @note This function can be used for all STM32F10x devices.\r
- * - For STM32F10X_XL devices, this function checks whether the specified \r
- * Bank1 or Bank2 flag is set or not.\r
- * - For other devices, it checks whether the specified Bank1 flag is \r
- * set or not.\r
- * @param FLASH_FLAG: specifies the FLASH flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg FLASH_FLAG_BSY: FLASH Busy flag \r
- * @arg FLASH_FLAG_PGERR: FLASH Program error flag \r
- * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag \r
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag \r
- * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag \r
- * @retval The new state of FLASH_FLAG (SET or RESET).\r
- */\r
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
-\r
-#ifdef STM32F10X_XL\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;\r
- if(FLASH_FLAG == FLASH_FLAG_OPTERR) \r
- {\r
- if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- }\r
- else\r
- {\r
- if((FLASH_FLAG & 0x80000000) != 0x0)\r
- {\r
- if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- }\r
- else\r
- {\r
- if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- }\r
- }\r
-#else\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;\r
- if(FLASH_FLAG == FLASH_FLAG_OPTERR) \r
- {\r
- if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- }\r
- else\r
- {\r
- if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- }\r
-#endif /* STM32F10X_XL */\r
-\r
- /* Return the new state of FLASH_FLAG (SET or RESET) */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the FLASH\92s pending flags.\r
- * @note This function can be used for all STM32F10x devices.\r
- * - For STM32F10X_XL devices, this function clears Bank1 or Bank2\92s pending flags\r
- * - For other devices, it clears Bank1\92s pending flags.\r
- * @param FLASH_FLAG: specifies the FLASH flags to clear.\r
- * This parameter can be any combination of the following values: \r
- * @arg FLASH_FLAG_PGERR: FLASH Program error flag \r
- * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag \r
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag \r
- * @retval None\r
- */\r
-void FLASH_ClearFlag(uint32_t FLASH_FLAG)\r
-{\r
-#ifdef STM32F10X_XL\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;\r
-\r
- if((FLASH_FLAG & 0x80000000) != 0x0)\r
- {\r
- /* Clear the flags */\r
- FLASH->SR2 = FLASH_FLAG;\r
- }\r
- else\r
- {\r
- /* Clear the flags */\r
- FLASH->SR = FLASH_FLAG;\r
- } \r
-\r
-#else\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;\r
- \r
- /* Clear the flags */\r
- FLASH->SR = FLASH_FLAG;\r
-#endif /* STM32F10X_XL */\r
-}\r
-\r
-/**\r
- * @brief Returns the FLASH Status.\r
- * @note This function can be used for all STM32F10x devices, it is equivalent\r
- * to FLASH_GetBank1Status function.\r
- * @param None\r
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP or FLASH_COMPLETE\r
- */\r
-FLASH_Status FLASH_GetStatus(void)\r
-{\r
- FLASH_Status flashstatus = FLASH_COMPLETE;\r
- \r
- if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) \r
- {\r
- flashstatus = FLASH_BUSY;\r
- }\r
- else \r
- { \r
- if((FLASH->SR & FLASH_FLAG_PGERR) != 0)\r
- { \r
- flashstatus = FLASH_ERROR_PG;\r
- }\r
- else \r
- {\r
- if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 )\r
- {\r
- flashstatus = FLASH_ERROR_WRP;\r
- }\r
- else\r
- {\r
- flashstatus = FLASH_COMPLETE;\r
- }\r
- }\r
- }\r
- /* Return the Flash Status */\r
- return flashstatus;\r
-}\r
-\r
-/**\r
- * @brief Returns the FLASH Bank1 Status.\r
- * @note This function can be used for all STM32F10x devices, it is equivalent\r
- * to FLASH_GetStatus function.\r
- * @param None\r
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP or FLASH_COMPLETE\r
- */\r
-FLASH_Status FLASH_GetBank1Status(void)\r
-{\r
- FLASH_Status flashstatus = FLASH_COMPLETE;\r
- \r
- if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) \r
- {\r
- flashstatus = FLASH_BUSY;\r
- }\r
- else \r
- { \r
- if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0)\r
- { \r
- flashstatus = FLASH_ERROR_PG;\r
- }\r
- else \r
- {\r
- if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 )\r
- {\r
- flashstatus = FLASH_ERROR_WRP;\r
- }\r
- else\r
- {\r
- flashstatus = FLASH_COMPLETE;\r
- }\r
- }\r
- }\r
- /* Return the Flash Status */\r
- return flashstatus;\r
-}\r
-\r
-#ifdef STM32F10X_XL\r
-/**\r
- * @brief Returns the FLASH Bank2 Status.\r
- * @note This function can be used for STM32F10x_XL density devices.\r
- * @param None\r
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP or FLASH_COMPLETE\r
- */\r
-FLASH_Status FLASH_GetBank2Status(void)\r
-{\r
- FLASH_Status flashstatus = FLASH_COMPLETE;\r
- \r
- if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) \r
- {\r
- flashstatus = FLASH_BUSY;\r
- }\r
- else \r
- { \r
- if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0)\r
- { \r
- flashstatus = FLASH_ERROR_PG;\r
- }\r
- else \r
- {\r
- if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 )\r
- {\r
- flashstatus = FLASH_ERROR_WRP;\r
- }\r
- else\r
- {\r
- flashstatus = FLASH_COMPLETE;\r
- }\r
- }\r
- }\r
- /* Return the Flash Status */\r
- return flashstatus;\r
-}\r
-#endif /* STM32F10X_XL */\r
-/**\r
- * @brief Waits for a Flash operation to complete or a TIMEOUT to occur.\r
- * @note This function can be used for all STM32F10x devices, \r
- * it is equivalent to FLASH_WaitForLastBank1Operation.\r
- * - For STM32F10X_XL devices this function waits for a Bank1 Flash operation\r
- * to complete or a TIMEOUT to occur.\r
- * - For all other devices it waits for a Flash operation to complete \r
- * or a TIMEOUT to occur.\r
- * @param Timeout: FLASH progamming Timeout\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)\r
-{ \r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Check for the Flash Status */\r
- status = FLASH_GetBank1Status();\r
- /* Wait for a Flash operation to complete or a TIMEOUT to occur */\r
- while((status == FLASH_BUSY) && (Timeout != 0x00))\r
- {\r
- status = FLASH_GetBank1Status();\r
- Timeout--;\r
- }\r
- if(Timeout == 0x00 )\r
- {\r
- status = FLASH_TIMEOUT;\r
- }\r
- /* Return the operation status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.\r
- * @note This function can be used for all STM32F10x devices, \r
- * it is equivalent to FLASH_WaitForLastOperation.\r
- * @param Timeout: FLASH progamming Timeout\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)\r
-{ \r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Check for the Flash Status */\r
- status = FLASH_GetBank1Status();\r
- /* Wait for a Flash operation to complete or a TIMEOUT to occur */\r
- while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))\r
- {\r
- status = FLASH_GetBank1Status();\r
- Timeout--;\r
- }\r
- if(Timeout == 0x00 )\r
- {\r
- status = FLASH_TIMEOUT;\r
- }\r
- /* Return the operation status */\r
- return status;\r
-}\r
-\r
-#ifdef STM32F10X_XL\r
-/**\r
- * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur.\r
- * @note This function can be used only for STM32F10x_XL density devices.\r
- * @param Timeout: FLASH progamming Timeout\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout)\r
-{ \r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Check for the Flash Status */\r
- status = FLASH_GetBank2Status();\r
- /* Wait for a Flash operation to complete or a TIMEOUT to occur */\r
- while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00))\r
- {\r
- status = FLASH_GetBank2Status();\r
- Timeout--;\r
- }\r
- if(Timeout == 0x00 )\r
- {\r
- status = FLASH_TIMEOUT;\r
- }\r
- /* Return the operation status */\r
- return status;\r
-}\r
-#endif /* STM32F10X_XL */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_fsmc.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the FSMC firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_fsmc.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup FSMC \r
- * @brief FSMC driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup FSMC_Private_TypesDefinitions\r
- * @{\r
- */ \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Private_Defines\r
- * @{\r
- */\r
-\r
-/* --------------------- FSMC registers bit mask ---------------------------- */\r
-\r
-/* FSMC BCRx Mask */\r
-#define BCR_MBKEN_Set ((uint32_t)0x00000001)\r
-#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)\r
-#define BCR_FACCEN_Set ((uint32_t)0x00000040)\r
-\r
-/* FSMC PCRx Mask */\r
-#define PCR_PBKEN_Set ((uint32_t)0x00000004)\r
-#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)\r
-#define PCR_ECCEN_Set ((uint32_t)0x00000040)\r
-#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)\r
-#define PCR_MemoryType_NAND ((uint32_t)0x00000008)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default \r
- * reset values.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 \r
- * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
- * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
- * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
- * @retval None\r
- */\r
-void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)\r
-{\r
- /* Check the parameter */\r
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
- \r
- /* FSMC_Bank1_NORSRAM1 */\r
- if(FSMC_Bank == FSMC_Bank1_NORSRAM1)\r
- {\r
- FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; \r
- }\r
- /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */\r
- else\r
- { \r
- FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; \r
- }\r
- FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;\r
- FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; \r
-}\r
-\r
-/**\r
- * @brief Deinitializes the FSMC NAND Banks registers to their default reset values.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND \r
- * @retval None\r
- */\r
-void FSMC_NANDDeInit(uint32_t FSMC_Bank)\r
-{\r
- /* Check the parameter */\r
- assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
- \r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- /* Set the FSMC_Bank2 registers to their reset values */\r
- FSMC_Bank2->PCR2 = 0x00000018;\r
- FSMC_Bank2->SR2 = 0x00000040;\r
- FSMC_Bank2->PMEM2 = 0xFCFCFCFC;\r
- FSMC_Bank2->PATT2 = 0xFCFCFCFC; \r
- }\r
- /* FSMC_Bank3_NAND */ \r
- else\r
- {\r
- /* Set the FSMC_Bank3 registers to their reset values */\r
- FSMC_Bank3->PCR3 = 0x00000018;\r
- FSMC_Bank3->SR3 = 0x00000040;\r
- FSMC_Bank3->PMEM3 = 0xFCFCFCFC;\r
- FSMC_Bank3->PATT3 = 0xFCFCFCFC; \r
- } \r
-}\r
-\r
-/**\r
- * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.\r
- * @param None \r
- * @retval None\r
- */\r
-void FSMC_PCCARDDeInit(void)\r
-{\r
- /* Set the FSMC_Bank4 registers to their reset values */\r
- FSMC_Bank4->PCR4 = 0x00000018; \r
- FSMC_Bank4->SR4 = 0x00000000; \r
- FSMC_Bank4->PMEM4 = 0xFCFCFCFC;\r
- FSMC_Bank4->PATT4 = 0xFCFCFCFC;\r
- FSMC_Bank4->PIO4 = 0xFCFCFCFC;\r
-}\r
-\r
-/**\r
- * @brief Initializes the FSMC NOR/SRAM Banks according to the specified\r
- * parameters in the FSMC_NORSRAMInitStruct.\r
- * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef\r
- * structure that contains the configuration information for \r
- * the FSMC NOR/SRAM specified Banks. \r
- * @retval None\r
- */\r
-void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));\r
- assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));\r
- assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));\r
- assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));\r
- assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));\r
- assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));\r
- assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));\r
- assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));\r
- assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));\r
- assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));\r
- assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));\r
- assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); \r
- assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));\r
- assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));\r
- assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));\r
- assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));\r
- assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));\r
- assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));\r
- assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); \r
- \r
- /* Bank1 NOR/SRAM control register configuration */ \r
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
- (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |\r
- FSMC_NORSRAMInitStruct->FSMC_MemoryType |\r
- FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |\r
- FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |\r
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |\r
- FSMC_NORSRAMInitStruct->FSMC_WrapMode |\r
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |\r
- FSMC_NORSRAMInitStruct->FSMC_WriteOperation |\r
- FSMC_NORSRAMInitStruct->FSMC_WaitSignal |\r
- FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |\r
- FSMC_NORSRAMInitStruct->FSMC_WriteBurst;\r
- if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)\r
- {\r
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;\r
- }\r
- /* Bank1 NOR/SRAM timing register configuration */\r
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = \r
- (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |\r
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |\r
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |\r
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |\r
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |\r
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;\r
- \r
- \r
- /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */\r
- if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)\r
- {\r
- assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));\r
- assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));\r
- assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));\r
- assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));\r
- assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));\r
- assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));\r
- FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
- (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |\r
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|\r
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |\r
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |\r
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;\r
- }\r
- else\r
- {\r
- FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the FSMC NAND Banks according to the specified \r
- * parameters in the FSMC_NANDInitStruct.\r
- * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef \r
- * structure that contains the configuration information for the FSMC NAND specified Banks. \r
- * @retval None\r
- */\r
-void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)\r
-{\r
- uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; \r
- \r
- /* Check the parameters */\r
- assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));\r
- assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));\r
- assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));\r
- assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));\r
- assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));\r
- assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));\r
- assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));\r
- assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));\r
- assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));\r
- assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));\r
- assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));\r
- assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));\r
- assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));\r
- assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));\r
- assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));\r
- \r
- /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */\r
- tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |\r
- PCR_MemoryType_NAND |\r
- FSMC_NANDInitStruct->FSMC_MemoryDataWidth |\r
- FSMC_NANDInitStruct->FSMC_ECC |\r
- FSMC_NANDInitStruct->FSMC_ECCPageSize |\r
- (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|\r
- (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);\r
- \r
- /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */\r
- tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |\r
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
- \r
- /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */\r
- tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |\r
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);\r
- \r
- if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- /* FSMC_Bank2_NAND registers configuration */\r
- FSMC_Bank2->PCR2 = tmppcr;\r
- FSMC_Bank2->PMEM2 = tmppmem;\r
- FSMC_Bank2->PATT2 = tmppatt;\r
- }\r
- else\r
- {\r
- /* FSMC_Bank3_NAND registers configuration */\r
- FSMC_Bank3->PCR3 = tmppcr;\r
- FSMC_Bank3->PMEM3 = tmppmem;\r
- FSMC_Bank3->PATT3 = tmppatt;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the FSMC PCCARD Bank according to the specified \r
- * parameters in the FSMC_PCCARDInitStruct.\r
- * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef\r
- * structure that contains the configuration information for the FSMC PCCARD Bank. \r
- * @retval None\r
- */\r
-void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));\r
- assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));\r
- assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));\r
- \r
- assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));\r
- assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));\r
- assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));\r
- assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));\r
- \r
- assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));\r
- assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));\r
- assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));\r
- assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));\r
- assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));\r
- assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));\r
- assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));\r
- assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));\r
- \r
- /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */\r
- FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |\r
- FSMC_MemoryDataWidth_16b | \r
- (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |\r
- (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);\r
- \r
- /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */\r
- FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |\r
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
- \r
- /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */\r
- FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |\r
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
- \r
- /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */\r
- FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |\r
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
-}\r
-\r
-/**\r
- * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.\r
- * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef \r
- * structure which will be initialized.\r
- * @retval None\r
- */\r
-void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
-{ \r
- /* Reset NOR/SRAM Init structure parameters values */\r
- FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;\r
- FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;\r
- FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;\r
- FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
- FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;\r
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;\r
- FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;\r
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;\r
- FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;\r
- FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; \r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;\r
-}\r
-\r
-/**\r
- * @brief Fills each FSMC_NANDInitStruct member with its default value.\r
- * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef \r
- * structure which will be initialized.\r
- * @retval None\r
- */\r
-void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)\r
-{ \r
- /* Reset NAND Init structure parameters values */\r
- FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;\r
- FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;\r
- FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
- FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;\r
- FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;\r
- FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;\r
- FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;\r
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; \r
-}\r
-\r
-/**\r
- * @brief Fills each FSMC_PCCARDInitStruct member with its default value.\r
- * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef \r
- * structure which will be initialized.\r
- * @retval None\r
- */\r
-void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)\r
-{\r
- /* Reset PCCARD Init structure parameters values */\r
- FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;\r
- FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;\r
- FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;\r
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; \r
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified NOR/SRAM Memory Bank.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 \r
- * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
- * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
- * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
- * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
-{\r
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */\r
- FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */\r
- FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified NAND Memory Bank.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
- * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
-{\r
- assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */\r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;\r
- }\r
- else\r
- {\r
- FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;\r
- }\r
- }\r
- else\r
- {\r
- /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */\r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;\r
- }\r
- else\r
- {\r
- FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the PCCARD Memory Bank.\r
- * @param NewState: new state of the PCCARD Memory Bank. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void FSMC_PCCARDCmd(FunctionalState NewState)\r
-{\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */\r
- FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;\r
- }\r
- else\r
- {\r
- /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */\r
- FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the FSMC NAND ECC feature.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
- * @param NewState: new state of the FSMC NAND ECC feature. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
-{\r
- assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */\r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;\r
- }\r
- else\r
- {\r
- FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;\r
- }\r
- }\r
- else\r
- {\r
- /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */\r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;\r
- }\r
- else\r
- {\r
- FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Returns the error correction code register value.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
- * @retval The Error Correction Code (ECC) value.\r
- */\r
-uint32_t FSMC_GetECC(uint32_t FSMC_Bank)\r
-{\r
- uint32_t eccval = 0x00000000;\r
- \r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- /* Get the ECCR2 register value */\r
- eccval = FSMC_Bank2->ECCR2;\r
- }\r
- else\r
- {\r
- /* Get the ECCR3 register value */\r
- eccval = FSMC_Bank3->ECCR3;\r
- }\r
- /* Return the error correction code value */\r
- return(eccval);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified FSMC interrupts.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
- * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
- * @arg FSMC_IT_Level: Level edge detection interrupt.\r
- * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.\r
- * @param NewState: new state of the specified FSMC interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)\r
-{\r
- assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
- assert_param(IS_FSMC_IT(FSMC_IT)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected FSMC_Bank2 interrupts */\r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- FSMC_Bank2->SR2 |= FSMC_IT;\r
- }\r
- /* Enable the selected FSMC_Bank3 interrupts */\r
- else if (FSMC_Bank == FSMC_Bank3_NAND)\r
- {\r
- FSMC_Bank3->SR3 |= FSMC_IT;\r
- }\r
- /* Enable the selected FSMC_Bank4 interrupts */\r
- else\r
- {\r
- FSMC_Bank4->SR4 |= FSMC_IT; \r
- }\r
- }\r
- else\r
- {\r
- /* Disable the selected FSMC_Bank2 interrupts */\r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- \r
- FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;\r
- }\r
- /* Disable the selected FSMC_Bank3 interrupts */\r
- else if (FSMC_Bank == FSMC_Bank3_NAND)\r
- {\r
- FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;\r
- }\r
- /* Disable the selected FSMC_Bank4 interrupts */\r
- else\r
- {\r
- FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; \r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified FSMC flag is set or not.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
- * @param FSMC_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.\r
- * @arg FSMC_FLAG_Level: Level detection Flag.\r
- * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.\r
- * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. \r
- * @retval The new state of FSMC_FLAG (SET or RESET).\r
- */\r
-FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- uint32_t tmpsr = 0x00000000;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));\r
- assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));\r
- \r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- tmpsr = FSMC_Bank2->SR2;\r
- } \r
- else if(FSMC_Bank == FSMC_Bank3_NAND)\r
- {\r
- tmpsr = FSMC_Bank3->SR3;\r
- }\r
- /* FSMC_Bank4_PCCARD*/\r
- else\r
- {\r
- tmpsr = FSMC_Bank4->SR4;\r
- } \r
- \r
- /* Get the flag status */\r
- if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- /* Return the flag status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the FSMC\92s pending flags.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
- * @param FSMC_FLAG: specifies the flag to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.\r
- * @arg FSMC_FLAG_Level: Level detection Flag.\r
- * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.\r
- * @retval None\r
- */\r
-void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));\r
- assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;\r
- \r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- FSMC_Bank2->SR2 &= ~FSMC_FLAG; \r
- } \r
- else if(FSMC_Bank == FSMC_Bank3_NAND)\r
- {\r
- FSMC_Bank3->SR3 &= ~FSMC_FLAG;\r
- }\r
- /* FSMC_Bank4_PCCARD*/\r
- else\r
- {\r
- FSMC_Bank4->SR4 &= ~FSMC_FLAG;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified FSMC interrupt has occurred or not.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
- * @param FSMC_IT: specifies the FSMC interrupt source to check.\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
- * @arg FSMC_IT_Level: Level edge detection interrupt.\r
- * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. \r
- * @retval The new state of FSMC_IT (SET or RESET).\r
- */\r
-ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; \r
- \r
- /* Check the parameters */\r
- assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
- assert_param(IS_FSMC_GET_IT(FSMC_IT));\r
- \r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- tmpsr = FSMC_Bank2->SR2;\r
- } \r
- else if(FSMC_Bank == FSMC_Bank3_NAND)\r
- {\r
- tmpsr = FSMC_Bank3->SR3;\r
- }\r
- /* FSMC_Bank4_PCCARD*/\r
- else\r
- {\r
- tmpsr = FSMC_Bank4->SR4;\r
- } \r
- \r
- itstatus = tmpsr & FSMC_IT;\r
- \r
- itenable = tmpsr & (FSMC_IT >> 3);\r
- if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus; \r
-}\r
-\r
-/**\r
- * @brief Clears the FSMC\92s interrupt pending bits.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
- * @param FSMC_IT: specifies the interrupt pending bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
- * @arg FSMC_IT_Level: Level edge detection interrupt.\r
- * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.\r
- * @retval None\r
- */\r
-void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
- assert_param(IS_FSMC_IT(FSMC_IT));\r
- \r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); \r
- } \r
- else if(FSMC_Bank == FSMC_Bank3_NAND)\r
- {\r
- FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);\r
- }\r
- /* FSMC_Bank4_PCCARD*/\r
- else\r
- {\r
- FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_gpio.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the GPIO firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_gpio.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup GPIO \r
- * @brief GPIO driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup GPIO_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_Private_Defines\r
- * @{\r
- */\r
-\r
-/* ------------ RCC registers bit address in the alias region ----------------*/\r
-#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)\r
-\r
-/* --- EVENTCR Register -----*/\r
-\r
-/* Alias word address of EVOE bit */\r
-#define EVCR_OFFSET (AFIO_OFFSET + 0x00)\r
-#define EVOE_BitNumber ((uint8_t)0x07)\r
-#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))\r
-\r
-\r
-/* --- MAPR Register ---*/ \r
-/* Alias word address of MII_RMII_SEL bit */ \r
-#define MAPR_OFFSET (AFIO_OFFSET + 0x04) \r
-#define MII_RMII_SEL_BitNumber ((u8)0x17) \r
-#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))\r
-\r
-\r
-#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)\r
-#define LSB_MASK ((uint16_t)0xFFFF)\r
-#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)\r
-#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)\r
-#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)\r
-#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the GPIOx peripheral registers to their default reset values.\r
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
- * @retval None\r
- */\r
-void GPIO_DeInit(GPIO_TypeDef* GPIOx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- \r
- if (GPIOx == GPIOA)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);\r
- }\r
- else if (GPIOx == GPIOB)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);\r
- }\r
- else if (GPIOx == GPIOC)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);\r
- }\r
- else if (GPIOx == GPIOD)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);\r
- } \r
- else if (GPIOx == GPIOE)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);\r
- } \r
- else if (GPIOx == GPIOF)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);\r
- }\r
- else\r
- {\r
- if (GPIOx == GPIOG)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Deinitializes the Alternate Functions (remap, event control\r
- * and EXTI configuration) registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void GPIO_AFIODeInit(void)\r
-{\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Initializes the GPIOx peripheral according to the specified\r
- * parameters in the GPIO_InitStruct.\r
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
- * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that\r
- * contains the configuration information for the specified GPIO peripheral.\r
- * @retval None\r
- */\r
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)\r
-{\r
- uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;\r
- uint32_t tmpreg = 0x00, pinmask = 0x00;\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));\r
- assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); \r
- \r
-/*---------------------------- GPIO Mode Configuration -----------------------*/\r
- currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);\r
- if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)\r
- { \r
- /* Check the parameters */\r
- assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));\r
- /* Output mode */\r
- currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;\r
- }\r
-/*---------------------------- GPIO CRL Configuration ------------------------*/\r
- /* Configure the eight low port pins */\r
- if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)\r
- {\r
- tmpreg = GPIOx->CRL;\r
- for (pinpos = 0x00; pinpos < 0x08; pinpos++)\r
- {\r
- pos = ((uint32_t)0x01) << pinpos;\r
- /* Get the port pins position */\r
- currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;\r
- if (currentpin == pos)\r
- {\r
- pos = pinpos << 2;\r
- /* Clear the corresponding low control register bits */\r
- pinmask = ((uint32_t)0x0F) << pos;\r
- tmpreg &= ~pinmask;\r
- /* Write the mode configuration in the corresponding bits */\r
- tmpreg |= (currentmode << pos);\r
- /* Reset the corresponding ODR bit */\r
- if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)\r
- {\r
- GPIOx->BRR = (((uint32_t)0x01) << pinpos);\r
- }\r
- else\r
- {\r
- /* Set the corresponding ODR bit */\r
- if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)\r
- {\r
- GPIOx->BSRR = (((uint32_t)0x01) << pinpos);\r
- }\r
- }\r
- }\r
- }\r
- GPIOx->CRL = tmpreg;\r
- }\r
-/*---------------------------- GPIO CRH Configuration ------------------------*/\r
- /* Configure the eight high port pins */\r
- if (GPIO_InitStruct->GPIO_Pin > 0x00FF)\r
- {\r
- tmpreg = GPIOx->CRH;\r
- for (pinpos = 0x00; pinpos < 0x08; pinpos++)\r
- {\r
- pos = (((uint32_t)0x01) << (pinpos + 0x08));\r
- /* Get the port pins position */\r
- currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);\r
- if (currentpin == pos)\r
- {\r
- pos = pinpos << 2;\r
- /* Clear the corresponding high control register bits */\r
- pinmask = ((uint32_t)0x0F) << pos;\r
- tmpreg &= ~pinmask;\r
- /* Write the mode configuration in the corresponding bits */\r
- tmpreg |= (currentmode << pos);\r
- /* Reset the corresponding ODR bit */\r
- if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)\r
- {\r
- GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));\r
- }\r
- /* Set the corresponding ODR bit */\r
- if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)\r
- {\r
- GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));\r
- }\r
- }\r
- }\r
- GPIOx->CRH = tmpreg;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Fills each GPIO_InitStruct member with its default value.\r
- * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will\r
- * be initialized.\r
- * @retval None\r
- */\r
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)\r
-{\r
- /* Reset GPIO init structure parameters values */\r
- GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;\r
- GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;\r
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;\r
-}\r
-\r
-/**\r
- * @brief Reads the specified input port pin.\r
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
- * @param GPIO_Pin: specifies the port bit to read.\r
- * This parameter can be GPIO_Pin_x where x can be (0..15).\r
- * @retval The input port pin value.\r
- */\r
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
-{\r
- uint8_t bitstatus = 0x00;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); \r
- \r
- if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
- {\r
- bitstatus = (uint8_t)Bit_SET;\r
- }\r
- else\r
- {\r
- bitstatus = (uint8_t)Bit_RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Reads the specified GPIO input data port.\r
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
- * @retval GPIO input data port value.\r
- */\r
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- \r
- return ((uint16_t)GPIOx->IDR);\r
-}\r
-\r
-/**\r
- * @brief Reads the specified output data port bit.\r
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
- * @param GPIO_Pin: specifies the port bit to read.\r
- * This parameter can be GPIO_Pin_x where x can be (0..15).\r
- * @retval The output port pin value.\r
- */\r
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
-{\r
- uint8_t bitstatus = 0x00;\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); \r
- \r
- if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
- {\r
- bitstatus = (uint8_t)Bit_SET;\r
- }\r
- else\r
- {\r
- bitstatus = (uint8_t)Bit_RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Reads the specified GPIO output data port.\r
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
- * @retval GPIO output data port value.\r
- */\r
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- \r
- return ((uint16_t)GPIOx->ODR);\r
-}\r
-\r
-/**\r
- * @brief Sets the selected data port bits.\r
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
- * @param GPIO_Pin: specifies the port bits to be written.\r
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
- * @retval None\r
- */\r
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- assert_param(IS_GPIO_PIN(GPIO_Pin));\r
- \r
- GPIOx->BSRR = GPIO_Pin;\r
-}\r
-\r
-/**\r
- * @brief Clears the selected data port bits.\r
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
- * @param GPIO_Pin: specifies the port bits to be written.\r
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
- * @retval None\r
- */\r
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- assert_param(IS_GPIO_PIN(GPIO_Pin));\r
- \r
- GPIOx->BRR = GPIO_Pin;\r
-}\r
-\r
-/**\r
- * @brief Sets or clears the selected data port bit.\r
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
- * @param GPIO_Pin: specifies the port bit to be written.\r
- * This parameter can be one of GPIO_Pin_x where x can be (0..15).\r
- * @param BitVal: specifies the value to be written to the selected bit.\r
- * This parameter can be one of the BitAction enum values:\r
- * @arg Bit_RESET: to clear the port pin\r
- * @arg Bit_SET: to set the port pin\r
- * @retval None\r
- */\r
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
- assert_param(IS_GPIO_BIT_ACTION(BitVal)); \r
- \r
- if (BitVal != Bit_RESET)\r
- {\r
- GPIOx->BSRR = GPIO_Pin;\r
- }\r
- else\r
- {\r
- GPIOx->BRR = GPIO_Pin;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Writes data to the specified GPIO data port.\r
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
- * @param PortVal: specifies the value to be written to the port output data register.\r
- * @retval None\r
- */\r
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- \r
- GPIOx->ODR = PortVal;\r
-}\r
-\r
-/**\r
- * @brief Locks GPIO Pins configuration registers.\r
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
- * @param GPIO_Pin: specifies the port bit to be written.\r
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
- * @retval None\r
- */\r
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
-{\r
- uint32_t tmp = 0x00010000;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- assert_param(IS_GPIO_PIN(GPIO_Pin));\r
- \r
- tmp |= GPIO_Pin;\r
- /* Set LCKK bit */\r
- GPIOx->LCKR = tmp;\r
- /* Reset LCKK bit */\r
- GPIOx->LCKR = GPIO_Pin;\r
- /* Set LCKK bit */\r
- GPIOx->LCKR = tmp;\r
- /* Read LCKK bit*/\r
- tmp = GPIOx->LCKR;\r
- /* Read LCKK bit*/\r
- tmp = GPIOx->LCKR;\r
-}\r
-\r
-/**\r
- * @brief Selects the GPIO pin used as Event output.\r
- * @param GPIO_PortSource: selects the GPIO port to be used as source\r
- * for Event output.\r
- * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).\r
- * @param GPIO_PinSource: specifies the pin for the Event output.\r
- * This parameter can be GPIO_PinSourcex where x can be (0..15).\r
- * @retval None\r
- */\r
-void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)\r
-{\r
- uint32_t tmpreg = 0x00;\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));\r
- assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
- \r
- tmpreg = AFIO->EVCR;\r
- /* Clear the PORT[6:4] and PIN[3:0] bits */\r
- tmpreg &= EVCR_PORTPINCONFIG_MASK;\r
- tmpreg |= (uint32_t)GPIO_PortSource << 0x04;\r
- tmpreg |= GPIO_PinSource;\r
- AFIO->EVCR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Event Output.\r
- * @param NewState: new state of the Event output.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void GPIO_EventOutputCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Changes the mapping of the specified pin.\r
- * @param GPIO_Remap: selects the pin to remap.\r
- * This parameter can be one of the following values:\r
- * @arg GPIO_Remap_SPI1\r
- * @arg GPIO_Remap_I2C1\r
- * @arg GPIO_Remap_USART1\r
- * @arg GPIO_Remap_USART2\r
- * @arg GPIO_PartialRemap_USART3\r
- * @arg GPIO_FullRemap_USART3\r
- * @arg GPIO_PartialRemap_TIM1\r
- * @arg GPIO_FullRemap_TIM1\r
- * @arg GPIO_PartialRemap1_TIM2\r
- * @arg GPIO_PartialRemap2_TIM2\r
- * @arg GPIO_FullRemap_TIM2\r
- * @arg GPIO_PartialRemap_TIM3\r
- * @arg GPIO_FullRemap_TIM3\r
- * @arg GPIO_Remap_TIM4\r
- * @arg GPIO_Remap1_CAN1\r
- * @arg GPIO_Remap2_CAN1\r
- * @arg GPIO_Remap_PD01\r
- * @arg GPIO_Remap_TIM5CH4_LSI\r
- * @arg GPIO_Remap_ADC1_ETRGINJ\r
- * @arg GPIO_Remap_ADC1_ETRGREG\r
- * @arg GPIO_Remap_ADC2_ETRGINJ\r
- * @arg GPIO_Remap_ADC2_ETRGREG\r
- * @arg GPIO_Remap_ETH\r
- * @arg GPIO_Remap_CAN2 \r
- * @arg GPIO_Remap_SWJ_NoJTRST\r
- * @arg GPIO_Remap_SWJ_JTAGDisable\r
- * @arg GPIO_Remap_SWJ_Disable\r
- * @arg GPIO_Remap_SPI3\r
- * @arg GPIO_Remap_TIM2ITR1_PTP_SOF\r
- * @arg GPIO_Remap_PTP_PPS\r
- * @arg GPIO_Remap_TIM15\r
- * @arg GPIO_Remap_TIM16\r
- * @arg GPIO_Remap_TIM17\r
- * @arg GPIO_Remap_CEC\r
- * @arg GPIO_Remap_TIM1_DMA \r
- * @arg GPIO_Remap_TIM9\r
- * @arg GPIO_Remap_TIM10\r
- * @arg GPIO_Remap_TIM11\r
- * @arg GPIO_Remap_TIM13\r
- * @arg GPIO_Remap_TIM14\r
- * @arg GPIO_Remap_FSMC_NADV \r
- * @note If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected \r
- * to Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output. \r
- * @param NewState: new state of the port pin remapping.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)\r
-{\r
- uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_REMAP(GPIO_Remap));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
- \r
- if((GPIO_Remap & 0x80000000) == 0x80000000)\r
- {\r
- tmpreg = AFIO->MAPR2;\r
- }\r
- else\r
- {\r
- tmpreg = AFIO->MAPR;\r
- }\r
-\r
- tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;\r
- tmp = GPIO_Remap & LSB_MASK;\r
-\r
- if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))\r
- {\r
- tmpreg &= DBGAFR_SWJCFG_MASK;\r
- AFIO->MAPR &= DBGAFR_SWJCFG_MASK;\r
- }\r
- else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)\r
- {\r
- tmp1 = ((uint32_t)0x03) << tmpmask;\r
- tmpreg &= ~tmp1;\r
- tmpreg |= ~DBGAFR_SWJCFG_MASK;\r
- }\r
- else\r
- {\r
- tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));\r
- tmpreg |= ~DBGAFR_SWJCFG_MASK;\r
- }\r
-\r
- if (NewState != DISABLE)\r
- {\r
- tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));\r
- }\r
-\r
- if((GPIO_Remap & 0x80000000) == 0x80000000)\r
- {\r
- AFIO->MAPR2 = tmpreg;\r
- }\r
- else\r
- {\r
- AFIO->MAPR = tmpreg;\r
- } \r
-}\r
-\r
-/**\r
- * @brief Selects the GPIO pin used as EXTI Line.\r
- * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.\r
- * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).\r
- * @param GPIO_PinSource: specifies the EXTI line to be configured.\r
- * This parameter can be GPIO_PinSourcex where x can be (0..15).\r
- * @retval None\r
- */\r
-void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)\r
-{\r
- uint32_t tmp = 0x00;\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));\r
- assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
- \r
- tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));\r
- AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;\r
- AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));\r
-}\r
-\r
-/**\r
- * @brief Selects the Ethernet media interface.\r
- * @note This function applies only to STM32 Connectivity line devices. \r
- * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode.\r
- * This parameter can be one of the following values:\r
- * @arg GPIO_ETH_MediaInterface_MII: MII mode\r
- * @arg GPIO_ETH_MediaInterface_RMII: RMII mode \r
- * @retval None\r
- */\r
-void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) \r
-{ \r
- assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); \r
-\r
- /* Configure MII_RMII selection bit */ \r
- *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; \r
-}\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_i2c.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the I2C firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_i2c.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup I2C \r
- * @brief I2C driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup I2C_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Private_Defines\r
- * @{\r
- */\r
-\r
-/* I2C SPE mask */\r
-#define CR1_PE_Set ((uint16_t)0x0001)\r
-#define CR1_PE_Reset ((uint16_t)0xFFFE)\r
-\r
-/* I2C START mask */\r
-#define CR1_START_Set ((uint16_t)0x0100)\r
-#define CR1_START_Reset ((uint16_t)0xFEFF)\r
-\r
-/* I2C STOP mask */\r
-#define CR1_STOP_Set ((uint16_t)0x0200)\r
-#define CR1_STOP_Reset ((uint16_t)0xFDFF)\r
-\r
-/* I2C ACK mask */\r
-#define CR1_ACK_Set ((uint16_t)0x0400)\r
-#define CR1_ACK_Reset ((uint16_t)0xFBFF)\r
-\r
-/* I2C ENGC mask */\r
-#define CR1_ENGC_Set ((uint16_t)0x0040)\r
-#define CR1_ENGC_Reset ((uint16_t)0xFFBF)\r
-\r
-/* I2C SWRST mask */\r
-#define CR1_SWRST_Set ((uint16_t)0x8000)\r
-#define CR1_SWRST_Reset ((uint16_t)0x7FFF)\r
-\r
-/* I2C PEC mask */\r
-#define CR1_PEC_Set ((uint16_t)0x1000)\r
-#define CR1_PEC_Reset ((uint16_t)0xEFFF)\r
-\r
-/* I2C ENPEC mask */\r
-#define CR1_ENPEC_Set ((uint16_t)0x0020)\r
-#define CR1_ENPEC_Reset ((uint16_t)0xFFDF)\r
-\r
-/* I2C ENARP mask */\r
-#define CR1_ENARP_Set ((uint16_t)0x0010)\r
-#define CR1_ENARP_Reset ((uint16_t)0xFFEF)\r
-\r
-/* I2C NOSTRETCH mask */\r
-#define CR1_NOSTRETCH_Set ((uint16_t)0x0080)\r
-#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)\r
-\r
-/* I2C registers Masks */\r
-#define CR1_CLEAR_Mask ((uint16_t)0xFBF5)\r
-\r
-/* I2C DMAEN mask */\r
-#define CR2_DMAEN_Set ((uint16_t)0x0800)\r
-#define CR2_DMAEN_Reset ((uint16_t)0xF7FF)\r
-\r
-/* I2C LAST mask */\r
-#define CR2_LAST_Set ((uint16_t)0x1000)\r
-#define CR2_LAST_Reset ((uint16_t)0xEFFF)\r
-\r
-/* I2C FREQ mask */\r
-#define CR2_FREQ_Reset ((uint16_t)0xFFC0)\r
-\r
-/* I2C ADD0 mask */\r
-#define OAR1_ADD0_Set ((uint16_t)0x0001)\r
-#define OAR1_ADD0_Reset ((uint16_t)0xFFFE)\r
-\r
-/* I2C ENDUAL mask */\r
-#define OAR2_ENDUAL_Set ((uint16_t)0x0001)\r
-#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE)\r
-\r
-/* I2C ADD2 mask */\r
-#define OAR2_ADD2_Reset ((uint16_t)0xFF01)\r
-\r
-/* I2C F/S mask */\r
-#define CCR_FS_Set ((uint16_t)0x8000)\r
-\r
-/* I2C CCR mask */\r
-#define CCR_CCR_Set ((uint16_t)0x0FFF)\r
-\r
-/* I2C FLAG mask */\r
-#define FLAG_Mask ((uint32_t)0x00FFFFFF)\r
-\r
-/* I2C Interrupt Enable mask */\r
-#define ITEN_Mask ((uint32_t)0x07000000)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the I2Cx peripheral registers to their default reset values.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @retval None\r
- */\r
-void I2C_DeInit(I2C_TypeDef* I2Cx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
-\r
- if (I2Cx == I2C1)\r
- {\r
- /* Enable I2C1 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);\r
- /* Release I2C1 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);\r
- }\r
- else\r
- {\r
- /* Enable I2C2 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);\r
- /* Release I2C2 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the I2Cx peripheral according to the specified \r
- * parameters in the I2C_InitStruct.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that\r
- * contains the configuration information for the specified I2C peripheral.\r
- * @retval None\r
- */\r
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)\r
-{\r
- uint16_t tmpreg = 0, freqrange = 0;\r
- uint16_t result = 0x04;\r
- uint32_t pclk1 = 8000000;\r
- RCC_ClocksTypeDef rcc_clocks;\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));\r
- assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));\r
- assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));\r
- assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));\r
- assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));\r
- assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));\r
-\r
-/*---------------------------- I2Cx CR2 Configuration ------------------------*/\r
- /* Get the I2Cx CR2 value */\r
- tmpreg = I2Cx->CR2;\r
- /* Clear frequency FREQ[5:0] bits */\r
- tmpreg &= CR2_FREQ_Reset;\r
- /* Get pclk1 frequency value */\r
- RCC_GetClocksFreq(&rcc_clocks);\r
- pclk1 = rcc_clocks.PCLK1_Frequency;\r
- /* Set frequency bits depending on pclk1 value */\r
- freqrange = (uint16_t)(pclk1 / 1000000);\r
- tmpreg |= freqrange;\r
- /* Write to I2Cx CR2 */\r
- I2Cx->CR2 = tmpreg;\r
-\r
-/*---------------------------- I2Cx CCR Configuration ------------------------*/\r
- /* Disable the selected I2C peripheral to configure TRISE */\r
- I2Cx->CR1 &= CR1_PE_Reset;\r
- /* Reset tmpreg value */\r
- /* Clear F/S, DUTY and CCR[11:0] bits */\r
- tmpreg = 0;\r
-\r
- /* Configure speed in standard mode */\r
- if (I2C_InitStruct->I2C_ClockSpeed <= 100000)\r
- {\r
- /* Standard mode speed calculate */\r
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));\r
- /* Test if CCR value is under 0x4*/\r
- if (result < 0x04)\r
- {\r
- /* Set minimum allowed value */\r
- result = 0x04; \r
- }\r
- /* Set speed value for standard mode */\r
- tmpreg |= result; \r
- /* Set Maximum Rise Time for standard mode */\r
- I2Cx->TRISE = freqrange + 1; \r
- }\r
- /* Configure speed in fast mode */\r
- else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/\r
- {\r
- if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)\r
- {\r
- /* Fast mode speed calculate: Tlow/Thigh = 2 */\r
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));\r
- }\r
- else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/\r
- {\r
- /* Fast mode speed calculate: Tlow/Thigh = 16/9 */\r
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));\r
- /* Set DUTY bit */\r
- result |= I2C_DutyCycle_16_9;\r
- }\r
-\r
- /* Test if CCR value is under 0x1*/\r
- if ((result & CCR_CCR_Set) == 0)\r
- {\r
- /* Set minimum allowed value */\r
- result |= (uint16_t)0x0001; \r
- }\r
- /* Set speed value and set F/S bit for fast mode */\r
- tmpreg |= (uint16_t)(result | CCR_FS_Set);\r
- /* Set Maximum Rise Time for fast mode */\r
- I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); \r
- }\r
-\r
- /* Write to I2Cx CCR */\r
- I2Cx->CCR = tmpreg;\r
- /* Enable the selected I2C peripheral */\r
- I2Cx->CR1 |= CR1_PE_Set;\r
-\r
-/*---------------------------- I2Cx CR1 Configuration ------------------------*/\r
- /* Get the I2Cx CR1 value */\r
- tmpreg = I2Cx->CR1;\r
- /* Clear ACK, SMBTYPE and SMBUS bits */\r
- tmpreg &= CR1_CLEAR_Mask;\r
- /* Configure I2Cx: mode and acknowledgement */\r
- /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */\r
- /* Set ACK bit according to I2C_Ack value */\r
- tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);\r
- /* Write to I2Cx CR1 */\r
- I2Cx->CR1 = tmpreg;\r
-\r
-/*---------------------------- I2Cx OAR1 Configuration -----------------------*/\r
- /* Set I2Cx Own Address1 and acknowledged address */\r
- I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);\r
-}\r
-\r
-/**\r
- * @brief Fills each I2C_InitStruct member with its default value.\r
- * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.\r
- * @retval None\r
- */\r
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)\r
-{\r
-/*---------------- Reset I2C init structure parameters values ----------------*/\r
- /* initialize the I2C_ClockSpeed member */\r
- I2C_InitStruct->I2C_ClockSpeed = 5000;\r
- /* Initialize the I2C_Mode member */\r
- I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;\r
- /* Initialize the I2C_DutyCycle member */\r
- I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;\r
- /* Initialize the I2C_OwnAddress1 member */\r
- I2C_InitStruct->I2C_OwnAddress1 = 0;\r
- /* Initialize the I2C_Ack member */\r
- I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;\r
- /* Initialize the I2C_AcknowledgedAddress member */\r
- I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C peripheral.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2Cx peripheral. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C peripheral */\r
- I2Cx->CR1 |= CR1_PE_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C peripheral */\r
- I2Cx->CR1 &= CR1_PE_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C DMA requests.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C DMA transfer.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C DMA requests */\r
- I2Cx->CR2 |= CR2_DMAEN_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C DMA requests */\r
- I2Cx->CR2 &= CR2_DMAEN_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Specifies if the next DMA transfer will be the last one.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C DMA last transfer.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Next DMA transfer is the last transfer */\r
- I2Cx->CR2 |= CR2_LAST_Set;\r
- }\r
- else\r
- {\r
- /* Next DMA transfer is not the last transfer */\r
- I2Cx->CR2 &= CR2_LAST_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Generates I2Cx communication START condition.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C START condition generation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Generate a START condition */\r
- I2Cx->CR1 |= CR1_START_Set;\r
- }\r
- else\r
- {\r
- /* Disable the START condition generation */\r
- I2Cx->CR1 &= CR1_START_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Generates I2Cx communication STOP condition.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C STOP condition generation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Generate a STOP condition */\r
- I2Cx->CR1 |= CR1_STOP_Set;\r
- }\r
- else\r
- {\r
- /* Disable the STOP condition generation */\r
- I2Cx->CR1 &= CR1_STOP_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C acknowledge feature.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C Acknowledgement.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the acknowledgement */\r
- I2Cx->CR1 |= CR1_ACK_Set;\r
- }\r
- else\r
- {\r
- /* Disable the acknowledgement */\r
- I2Cx->CR1 &= CR1_ACK_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the specified I2C own address2.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param Address: specifies the 7bit I2C own address2.\r
- * @retval None.\r
- */\r
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)\r
-{\r
- uint16_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
-\r
- /* Get the old register value */\r
- tmpreg = I2Cx->OAR2;\r
-\r
- /* Reset I2Cx Own address2 bit [7:1] */\r
- tmpreg &= OAR2_ADD2_Reset;\r
-\r
- /* Set I2Cx Own address2 */\r
- tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);\r
-\r
- /* Store the new register value */\r
- I2Cx->OAR2 = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C dual addressing mode.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C dual addressing mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable dual addressing mode */\r
- I2Cx->OAR2 |= OAR2_ENDUAL_Set;\r
- }\r
- else\r
- {\r
- /* Disable dual addressing mode */\r
- I2Cx->OAR2 &= OAR2_ENDUAL_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C general call feature.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C General call.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable generall call */\r
- I2Cx->CR1 |= CR1_ENGC_Set;\r
- }\r
- else\r
- {\r
- /* Disable generall call */\r
- I2Cx->CR1 &= CR1_ENGC_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C interrupts.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. \r
- * This parameter can be any combination of the following values:\r
- * @arg I2C_IT_BUF: Buffer interrupt mask\r
- * @arg I2C_IT_EVT: Event interrupt mask\r
- * @arg I2C_IT_ERR: Error interrupt mask\r
- * @param NewState: new state of the specified I2C interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_I2C_CONFIG_IT(I2C_IT));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C interrupts */\r
- I2Cx->CR2 |= I2C_IT;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C interrupts */\r
- I2Cx->CR2 &= (uint16_t)~I2C_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Sends a data byte through the I2Cx peripheral.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param Data: Byte to be transmitted..\r
- * @retval None\r
- */\r
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- /* Write in the DR register the data to be sent */\r
- I2Cx->DR = Data;\r
-}\r
-\r
-/**\r
- * @brief Returns the most recent received data by the I2Cx peripheral.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @retval The value of the received data.\r
- */\r
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- /* Return the data in the DR register */\r
- return (uint8_t)I2Cx->DR;\r
-}\r
-\r
-/**\r
- * @brief Transmits the address byte to select the slave device.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param Address: specifies the slave address which will be transmitted\r
- * @param I2C_Direction: specifies whether the I2C device will be a\r
- * Transmitter or a Receiver. This parameter can be one of the following values\r
- * @arg I2C_Direction_Transmitter: Transmitter mode\r
- * @arg I2C_Direction_Receiver: Receiver mode\r
- * @retval None.\r
- */\r
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_DIRECTION(I2C_Direction));\r
- /* Test on the direction to set/reset the read/write bit */\r
- if (I2C_Direction != I2C_Direction_Transmitter)\r
- {\r
- /* Set the address bit0 for read */\r
- Address |= OAR1_ADD0_Set;\r
- }\r
- else\r
- {\r
- /* Reset the address bit0 for write */\r
- Address &= OAR1_ADD0_Reset;\r
- }\r
- /* Send the address */\r
- I2Cx->DR = Address;\r
-}\r
-\r
-/**\r
- * @brief Reads the specified I2C register and returns its value.\r
- * @param I2C_Register: specifies the register to read.\r
- * This parameter can be one of the following values:\r
- * @arg I2C_Register_CR1: CR1 register.\r
- * @arg I2C_Register_CR2: CR2 register.\r
- * @arg I2C_Register_OAR1: OAR1 register.\r
- * @arg I2C_Register_OAR2: OAR2 register.\r
- * @arg I2C_Register_DR: DR register.\r
- * @arg I2C_Register_SR1: SR1 register.\r
- * @arg I2C_Register_SR2: SR2 register.\r
- * @arg I2C_Register_CCR: CCR register.\r
- * @arg I2C_Register_TRISE: TRISE register.\r
- * @retval The value of the read register.\r
- */\r
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)\r
-{\r
- __IO uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_REGISTER(I2C_Register));\r
-\r
- tmp = (uint32_t) I2Cx;\r
- tmp += I2C_Register;\r
-\r
- /* Return the selected register value */\r
- return (*(__IO uint16_t *) tmp);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C software reset.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C software reset.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Peripheral under reset */\r
- I2Cx->CR1 |= CR1_SWRST_Set;\r
- }\r
- else\r
- {\r
- /* Peripheral not under reset */\r
- I2Cx->CR1 &= CR1_SWRST_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Drives the SMBusAlert pin high or low for the specified I2C.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_SMBusAlert: specifies SMBAlert pin level. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low\r
- * @arg I2C_SMBusAlert_High: SMBAlert pin driven high\r
- * @retval None\r
- */\r
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));\r
- if (I2C_SMBusAlert == I2C_SMBusAlert_Low)\r
- {\r
- /* Drive the SMBusAlert pin Low */\r
- I2Cx->CR1 |= I2C_SMBusAlert_Low;\r
- }\r
- else\r
- {\r
- /* Drive the SMBusAlert pin High */\r
- I2Cx->CR1 &= I2C_SMBusAlert_High;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C PEC transfer.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C PEC transmission.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C PEC transmission */\r
- I2Cx->CR1 |= CR1_PEC_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C PEC transmission */\r
- I2Cx->CR1 &= CR1_PEC_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the specified I2C PEC position.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_PECPosition: specifies the PEC position. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_PECPosition_Next: indicates that the next byte is PEC\r
- * @arg I2C_PECPosition_Current: indicates that current byte is PEC\r
- * @retval None\r
- */\r
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));\r
- if (I2C_PECPosition == I2C_PECPosition_Next)\r
- {\r
- /* Next byte in shift register is PEC */\r
- I2Cx->CR1 |= I2C_PECPosition_Next;\r
- }\r
- else\r
- {\r
- /* Current byte in shift register is PEC */\r
- I2Cx->CR1 &= I2C_PECPosition_Current;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the PEC value calculation of the transfered bytes.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2Cx PEC value calculation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C PEC calculation */\r
- I2Cx->CR1 |= CR1_ENPEC_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C PEC calculation */\r
- I2Cx->CR1 &= CR1_ENPEC_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Returns the PEC value for the specified I2C.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @retval The PEC value.\r
- */\r
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- /* Return the selected I2C PEC value */\r
- return ((I2Cx->SR2) >> 8);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C ARP.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2Cx ARP. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C ARP */\r
- I2Cx->CR1 |= CR1_ENARP_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C ARP */\r
- I2Cx->CR1 &= CR1_ENARP_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C Clock stretching.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2Cx Clock stretching.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState == DISABLE)\r
- {\r
- /* Enable the selected I2C Clock stretching */\r
- I2Cx->CR1 |= CR1_NOSTRETCH_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C Clock stretching */\r
- I2Cx->CR1 &= CR1_NOSTRETCH_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the specified I2C fast mode duty cycle.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_DutyCycle: specifies the fast mode duty cycle.\r
- * This parameter can be one of the following values:\r
- * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2\r
- * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9\r
- * @retval None\r
- */\r
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));\r
- if (I2C_DutyCycle != I2C_DutyCycle_16_9)\r
- {\r
- /* I2C fast mode Tlow/Thigh=2 */\r
- I2Cx->CCR &= I2C_DutyCycle_2;\r
- }\r
- else\r
- {\r
- /* I2C fast mode Tlow/Thigh=16/9 */\r
- I2Cx->CCR |= I2C_DutyCycle_16_9;\r
- }\r
-}\r
-\r
-\r
-\r
-/**\r
- * @brief\r
- ****************************************************************************************\r
- *\r
- * I2C State Monitoring Functions\r
- * \r
- **************************************************************************************** \r
- * This I2C driver provides three different ways for I2C state monitoring\r
- * depending on the application requirements and constraints:\r
- * \r
- * \r
- * 1) Basic state monitoring:\r
- * Using I2C_CheckEvent() function:\r
- * It compares the status registers (SR1 and SR2) content to a given event\r
- * (can be the combination of one or more flags).\r
- * It returns SUCCESS if the current status includes the given flags \r
- * and returns ERROR if one or more flags are missing in the current status.\r
- * - When to use:\r
- * - This function is suitable for most applciations as well as for startup \r
- * activity since the events are fully described in the product reference manual \r
- * (RM0008).\r
- * - It is also suitable for users who need to define their own events.\r
- * - Limitations:\r
- * - If an error occurs (ie. error flags are set besides to the monitored flags),\r
- * the I2C_CheckEvent() function may return SUCCESS despite the communication\r
- * hold or corrupted real state. \r
- * In this case, it is advised to use error interrupts to monitor the error\r
- * events and handle them in the interrupt IRQ handler.\r
- * \r
- * @note \r
- * For error management, it is advised to use the following functions:\r
- * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
- * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.\r
- * Where x is the peripheral instance (I2C1, I2C2 ...)\r
- * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() \r
- * in order to determine which error occured.\r
- * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()\r
- * and/or I2C_GenerateStop() in order to clear the error flag and source,\r
- * and return to correct communication status.\r
- * \r
- *\r
- * 2) Advanced state monitoring:\r
- * Using the function I2C_GetLastEvent() which returns the image of both status \r
- * registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
- * by 16 bits and concatenated to Status Register 1).\r
- * - When to use:\r
- * - This function is suitable for the same applications above but it allows to\r
- * overcome the mentionned limitation of I2C_GetFlagStatus() function.\r
- * The returned value could be compared to events already defined in the \r
- * library (stm32f10x_i2c.h) or to custom values defiend by user.\r
- * - This function is suitable when multiple flags are monitored at the same time.\r
- * - At the opposite of I2C_CheckEvent() function, this function allows user to\r
- * choose when an event is accepted (when all events flags are set and no \r
- * other flags are set or just when the needed flags are set like \r
- * I2C_CheckEvent() function).\r
- * - Limitations:\r
- * - User may need to define his own events.\r
- * - Same remark concerning the error management is applicable for this \r
- * function if user decides to check only regular communication flags (and \r
- * ignores error flags).\r
- * \r
- *\r
- * 3) Flag-based state monitoring:\r
- * Using the function I2C_GetFlagStatus() which simply returns the status of \r
- * one single flag (ie. I2C_FLAG_RXNE ...). \r
- * - When to use:\r
- * - This function could be used for specific applications or in debug phase.\r
- * - It is suitable when only one flag checking is needed (most I2C events \r
- * are monitored through multiple flags).\r
- * - Limitations: \r
- * - When calling this function, the Status register is accessed. Some flags are\r
- * cleared when the status register is accessed. So checking the status\r
- * of one Flag, may clear other ones.\r
- * - Function may need to be called twice or more in order to monitor one \r
- * single event.\r
- *\r
- * For detailed description of Events, please refer to section I2C_Events in \r
- * stm32f10x_i2c.h file.\r
- * \r
- */\r
-\r
-/**\r
- * \r
- * 1) Basic state monitoring\r
- *******************************************************************************\r
- */\r
-\r
-/**\r
- * @brief Checks whether the last I2Cx Event is equal to the one passed\r
- * as parameter.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_EVENT: specifies the event to be checked. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1\r
- * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1\r
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1\r
- * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1\r
- * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1\r
- * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2\r
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2\r
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2\r
- * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3\r
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3\r
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3\r
- * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2\r
- * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4\r
- * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5\r
- * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 \r
- * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6\r
- * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7\r
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8\r
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2\r
- * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9\r
- * \r
- * @note: For detailed description of Events, please refer to section \r
- * I2C_Events in stm32f10x_i2c.h file.\r
- * \r
- * @retval An ErrorStatus enumuration value:\r
- * - SUCCESS: Last event is equal to the I2C_EVENT\r
- * - ERROR: Last event is different from the I2C_EVENT\r
- */\r
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)\r
-{\r
- uint32_t lastevent = 0;\r
- uint32_t flag1 = 0, flag2 = 0;\r
- ErrorStatus status = ERROR;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_EVENT(I2C_EVENT));\r
-\r
- /* Read the I2Cx status register */\r
- flag1 = I2Cx->SR1;\r
- flag2 = I2Cx->SR2;\r
- flag2 = flag2 << 16;\r
-\r
- /* Get the last event value from I2C status register */\r
- lastevent = (flag1 | flag2) & FLAG_Mask;\r
-\r
- /* Check whether the last event contains the I2C_EVENT */\r
- if ((lastevent & I2C_EVENT) == I2C_EVENT)\r
- {\r
- /* SUCCESS: last event is equal to I2C_EVENT */\r
- status = SUCCESS;\r
- }\r
- else\r
- {\r
- /* ERROR: last event is different from I2C_EVENT */\r
- status = ERROR;\r
- }\r
- /* Return status */\r
- return status;\r
-}\r
-\r
-/**\r
- * \r
- * 2) Advanced state monitoring\r
- *******************************************************************************\r
- */\r
-\r
-/**\r
- * @brief Returns the last I2Cx Event.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * \r
- * @note: For detailed description of Events, please refer to section \r
- * I2C_Events in stm32f10x_i2c.h file.\r
- * \r
- * @retval The last event\r
- */\r
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)\r
-{\r
- uint32_t lastevent = 0;\r
- uint32_t flag1 = 0, flag2 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
-\r
- /* Read the I2Cx status register */\r
- flag1 = I2Cx->SR1;\r
- flag2 = I2Cx->SR2;\r
- flag2 = flag2 << 16;\r
-\r
- /* Get the last event value from I2C status register */\r
- lastevent = (flag1 | flag2) & FLAG_Mask;\r
-\r
- /* Return status */\r
- return lastevent;\r
-}\r
-\r
-/**\r
- * \r
- * 3) Flag-based state monitoring\r
- *******************************************************************************\r
- */\r
-\r
-/**\r
- * @brief Checks whether the specified I2C flag is set or not.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_FLAG: specifies the flag to check. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)\r
- * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)\r
- * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)\r
- * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)\r
- * @arg I2C_FLAG_TRA: Transmitter/Receiver flag\r
- * @arg I2C_FLAG_BUSY: Bus busy flag\r
- * @arg I2C_FLAG_MSL: Master/Slave flag\r
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
- * @arg I2C_FLAG_PECERR: PEC error in reception flag\r
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
- * @arg I2C_FLAG_AF: Acknowledge failure flag\r
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
- * @arg I2C_FLAG_BERR: Bus error flag\r
- * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)\r
- * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag\r
- * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)\r
- * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)\r
- * @arg I2C_FLAG_BTF: Byte transfer finished flag\r
- * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) \93ADSL\94\r
- * Address matched flag (Slave mode)\94ENDAD\94\r
- * @arg I2C_FLAG_SB: Start bit flag (Master mode)\r
- * @retval The new state of I2C_FLAG (SET or RESET).\r
- */\r
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- __IO uint32_t i2creg = 0, i2cxbase = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_GET_FLAG(I2C_FLAG));\r
-\r
- /* Get the I2Cx peripheral base address */\r
- i2cxbase = (uint32_t)I2Cx;\r
- \r
- /* Read flag register index */\r
- i2creg = I2C_FLAG >> 28;\r
- \r
- /* Get bit[23:0] of the flag */\r
- I2C_FLAG &= FLAG_Mask;\r
- \r
- if(i2creg != 0)\r
- {\r
- /* Get the I2Cx SR1 register address */\r
- i2cxbase += 0x14;\r
- }\r
- else\r
- {\r
- /* Flag in I2Cx SR2 Register */\r
- I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);\r
- /* Get the I2Cx SR2 register address */\r
- i2cxbase += 0x18;\r
- }\r
- \r
- if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)\r
- {\r
- /* I2C_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* I2C_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- \r
- /* Return the I2C_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-\r
-\r
-/**\r
- * @brief Clears the I2Cx's pending flags.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_FLAG: specifies the flag to clear. \r
- * This parameter can be any combination of the following values:\r
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
- * @arg I2C_FLAG_PECERR: PEC error in reception flag\r
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
- * @arg I2C_FLAG_AF: Acknowledge failure flag\r
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
- * @arg I2C_FLAG_BERR: Bus error flag\r
- * \r
- * @note\r
- * - STOPF (STOP detection) is cleared by software sequence: a read operation \r
- * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation \r
- * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r
- * - ADD10 (10-bit header sent) is cleared by software sequence: a read \r
- * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the \r
- * second byte of the address in DR register.\r
- * - BTF (Byte Transfer Finished) is cleared by software sequence: a read \r
- * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a \r
- * read/write to I2C_DR register (I2C_SendData()).\r
- * - ADDR (Address sent) is cleared by software sequence: a read operation to \r
- * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to \r
- * I2C_SR2 register ((void)(I2Cx->SR2)).\r
- * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1\r
- * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR\r
- * register (I2C_SendData()).\r
- * @retval None\r
- */\r
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
-{\r
- uint32_t flagpos = 0;\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));\r
- /* Get the I2C flag position */\r
- flagpos = I2C_FLAG & FLAG_Mask;\r
- /* Clear the selected I2C flag */\r
- I2Cx->SR1 = (uint16_t)~flagpos;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified I2C interrupt has occurred or not.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_IT: specifies the interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_IT_SMBALERT: SMBus Alert flag\r
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag\r
- * @arg I2C_IT_PECERR: PEC error in reception flag\r
- * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)\r
- * @arg I2C_IT_AF: Acknowledge failure flag\r
- * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)\r
- * @arg I2C_IT_BERR: Bus error flag\r
- * @arg I2C_IT_TXE: Data register empty flag (Transmitter)\r
- * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag\r
- * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)\r
- * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)\r
- * @arg I2C_IT_BTF: Byte transfer finished flag\r
- * @arg I2C_IT_ADDR: Address sent flag (Master mode) \93ADSL\94\r
- * Address matched flag (Slave mode)\94ENDAD\94\r
- * @arg I2C_IT_SB: Start bit flag (Master mode)\r
- * @retval The new state of I2C_IT (SET or RESET).\r
- */\r
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t enablestatus = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_GET_IT(I2C_IT));\r
-\r
- /* Check if the interrupt source is enabled or not */\r
- enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;\r
- \r
- /* Get bit[23:0] of the flag */\r
- I2C_IT &= FLAG_Mask;\r
-\r
- /* Check the status of the specified I2C flag */\r
- if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)\r
- {\r
- /* I2C_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* I2C_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the I2C_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the I2Cx\92s interrupt pending bits.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_IT: specifies the interrupt pending bit to clear. \r
- * This parameter can be any combination of the following values:\r
- * @arg I2C_IT_SMBALERT: SMBus Alert interrupt\r
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt\r
- * @arg I2C_IT_PECERR: PEC error in reception interrupt\r
- * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)\r
- * @arg I2C_IT_AF: Acknowledge failure interrupt\r
- * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)\r
- * @arg I2C_IT_BERR: Bus error interrupt\r
- * \r
- * @note\r
- * - STOPF (STOP detection) is cleared by software sequence: a read operation \r
- * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r
- * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r
- * - ADD10 (10-bit header sent) is cleared by software sequence: a read \r
- * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second \r
- * byte of the address in I2C_DR register.\r
- * - BTF (Byte Transfer Finished) is cleared by software sequence: a read \r
- * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a \r
- * read/write to I2C_DR register (I2C_SendData()).\r
- * - ADDR (Address sent) is cleared by software sequence: a read operation to \r
- * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to \r
- * I2C_SR2 register ((void)(I2Cx->SR2)).\r
- * - SB (Start Bit) is cleared by software sequence: a read operation to \r
- * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r
- * I2C_DR register (I2C_SendData()).\r
- * @retval None\r
- */\r
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
-{\r
- uint32_t flagpos = 0;\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_CLEAR_IT(I2C_IT));\r
- /* Get the I2C flag position */\r
- flagpos = I2C_IT & FLAG_Mask;\r
- /* Clear the selected I2C flag */\r
- I2Cx->SR1 = (uint16_t)~flagpos;\r
-}\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_iwdg.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the IWDG firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_iwdg.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup IWDG \r
- * @brief IWDG driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup IWDG_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Private_Defines\r
- * @{\r
- */ \r
-\r
-/* ---------------------- IWDG registers bit mask ----------------------------*/\r
-\r
-/* KR register bit mask */\r
-#define KR_KEY_Reload ((uint16_t)0xAAAA)\r
-#define KR_KEY_Enable ((uint16_t)0xCCCC)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup IWDG_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.\r
- * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.\r
- * This parameter can be one of the following values:\r
- * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers\r
- * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers\r
- * @retval None\r
- */\r
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));\r
- IWDG->KR = IWDG_WriteAccess;\r
-}\r
-\r
-/**\r
- * @brief Sets IWDG Prescaler value.\r
- * @param IWDG_Prescaler: specifies the IWDG Prescaler value.\r
- * This parameter can be one of the following values:\r
- * @arg IWDG_Prescaler_4: IWDG prescaler set to 4\r
- * @arg IWDG_Prescaler_8: IWDG prescaler set to 8\r
- * @arg IWDG_Prescaler_16: IWDG prescaler set to 16\r
- * @arg IWDG_Prescaler_32: IWDG prescaler set to 32\r
- * @arg IWDG_Prescaler_64: IWDG prescaler set to 64\r
- * @arg IWDG_Prescaler_128: IWDG prescaler set to 128\r
- * @arg IWDG_Prescaler_256: IWDG prescaler set to 256\r
- * @retval None\r
- */\r
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));\r
- IWDG->PR = IWDG_Prescaler;\r
-}\r
-\r
-/**\r
- * @brief Sets IWDG Reload value.\r
- * @param Reload: specifies the IWDG Reload value.\r
- * This parameter must be a number between 0 and 0x0FFF.\r
- * @retval None\r
- */\r
-void IWDG_SetReload(uint16_t Reload)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_IWDG_RELOAD(Reload));\r
- IWDG->RLR = Reload;\r
-}\r
-\r
-/**\r
- * @brief Reloads IWDG counter with value defined in the reload register\r
- * (write access to IWDG_PR and IWDG_RLR registers disabled).\r
- * @param None\r
- * @retval None\r
- */\r
-void IWDG_ReloadCounter(void)\r
-{\r
- IWDG->KR = KR_KEY_Reload;\r
-}\r
-\r
-/**\r
- * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).\r
- * @param None\r
- * @retval None\r
- */\r
-void IWDG_Enable(void)\r
-{\r
- IWDG->KR = KR_KEY_Enable;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified IWDG flag is set or not.\r
- * @param IWDG_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg IWDG_FLAG_PVU: Prescaler Value Update on going\r
- * @arg IWDG_FLAG_RVU: Reload Value Update on going\r
- * @retval The new state of IWDG_FLAG (SET or RESET).\r
- */\r
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_IWDG_FLAG(IWDG_FLAG));\r
- if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- /* Return the flag status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_pwr.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the PWR firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_pwr.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup PWR \r
- * @brief PWR driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup PWR_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Private_Defines\r
- * @{\r
- */\r
-\r
-/* --------- PWR registers bit address in the alias region ---------- */\r
-#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)\r
-\r
-/* --- CR Register ---*/\r
-\r
-/* Alias word address of DBP bit */\r
-#define CR_OFFSET (PWR_OFFSET + 0x00)\r
-#define DBP_BitNumber 0x08\r
-#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))\r
-\r
-/* Alias word address of PVDE bit */\r
-#define PVDE_BitNumber 0x04\r
-#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))\r
-\r
-/* --- CSR Register ---*/\r
-\r
-/* Alias word address of EWUP bit */\r
-#define CSR_OFFSET (PWR_OFFSET + 0x04)\r
-#define EWUP_BitNumber 0x08\r
-#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))\r
-\r
-/* ------------------ PWR registers bit mask ------------------------ */\r
-\r
-/* CR register bit mask */\r
-#define CR_PDDS_Set ((uint32_t)0x00000002)\r
-#define CR_DS_Mask ((uint32_t)0xFFFFFFFC)\r
-#define CR_CWUF_Set ((uint32_t)0x00000004)\r
-#define CR_PLS_Mask ((uint32_t)0xFFFFFF1F)\r
-\r
-/* --------- Cortex System Control register bit mask ---------------- */\r
-\r
-/* Cortex System Control register address */\r
-#define SCB_SysCtrl ((uint32_t)0xE000ED10)\r
-\r
-/* SLEEPDEEP bit mask */\r
-#define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004)\r
-#define SysCtrl_SLEEPDEEP_Reset ((uint32_t)0xFFFFFFFB)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the PWR peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void PWR_DeInit(void)\r
-{\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables access to the RTC and backup registers.\r
- * @param NewState: new state of the access to the RTC and backup registers.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void PWR_BackupAccessCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Power Voltage Detector(PVD).\r
- * @param NewState: new state of the PVD.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void PWR_PVDCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r
- * @param PWR_PVDLevel: specifies the PVD detection level\r
- * This parameter can be one of the following values:\r
- * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V\r
- * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V\r
- * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V\r
- * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V\r
- * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V\r
- * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V\r
- * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V\r
- * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V\r
- * @retval None\r
- */\r
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));\r
- tmpreg = PWR->CR;\r
- /* Clear PLS[7:5] bits */\r
- tmpreg &= CR_PLS_Mask;\r
- /* Set PLS[7:5] bits according to PWR_PVDLevel value */\r
- tmpreg |= PWR_PVDLevel;\r
- /* Store the new value */\r
- PWR->CR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the WakeUp Pin functionality.\r
- * @param NewState: new state of the WakeUp Pin functionality.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void PWR_WakeUpPinCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enters STOP mode.\r
- * @param PWR_Regulator: specifies the regulator state in STOP mode.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_Regulator_ON: STOP mode with regulator ON\r
- * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode\r
- * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction\r
- * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction\r
- * @retval None\r
- */\r
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
- assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));\r
- \r
- /* Select the regulator state in STOP mode ---------------------------------*/\r
- tmpreg = PWR->CR;\r
- /* Clear PDDS and LPDS bits */\r
- tmpreg &= CR_DS_Mask;\r
- /* Set LPDS bit according to PWR_Regulator value */\r
- tmpreg |= PWR_Regulator;\r
- /* Store the new value */\r
- PWR->CR = tmpreg;\r
- /* Set SLEEPDEEP bit of Cortex System Control Register */\r
- *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;\r
- \r
- /* Select STOP mode entry --------------------------------------------------*/\r
- if(PWR_STOPEntry == PWR_STOPEntry_WFI)\r
- { \r
- /* Request Wait For Interrupt */\r
- __WFI();\r
- }\r
- else\r
- {\r
- /* Request Wait For Event */\r
- __WFE();\r
- }\r
- \r
- /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
- *(__IO uint32_t *) SCB_SysCtrl &= SysCtrl_SLEEPDEEP_Reset; \r
-}\r
-\r
-/**\r
- * @brief Enters STANDBY mode.\r
- * @param None\r
- * @retval None\r
- */\r
-void PWR_EnterSTANDBYMode(void)\r
-{\r
- /* Clear Wake-up flag */\r
- PWR->CR |= CR_CWUF_Set;\r
- /* Select STANDBY mode */\r
- PWR->CR |= CR_PDDS_Set;\r
- /* Set SLEEPDEEP bit of Cortex System Control Register */\r
- *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;\r
-/* This option is used to ensure that store operations are completed */\r
-#if defined ( __CC_ARM )\r
- __force_stores();\r
-#endif\r
- /* Request Wait For Interrupt */\r
- __WFI();\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified PWR flag is set or not.\r
- * @param PWR_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_FLAG_WU: Wake Up flag\r
- * @arg PWR_FLAG_SB: StandBy flag\r
- * @arg PWR_FLAG_PVDO: PVD Output\r
- * @retval The new state of PWR_FLAG (SET or RESET).\r
- */\r
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_PWR_GET_FLAG(PWR_FLAG));\r
- \r
- if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- /* Return the flag status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the PWR's pending flags.\r
- * @param PWR_FLAG: specifies the flag to clear.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_FLAG_WU: Wake Up flag\r
- * @arg PWR_FLAG_SB: StandBy flag\r
- * @retval None\r
- */\r
-void PWR_ClearFlag(uint32_t PWR_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));\r
- \r
- PWR->CR |= PWR_FLAG << 2;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_rcc.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the RCC firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup RCC \r
- * @brief RCC driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup RCC_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Private_Defines\r
- * @{\r
- */\r
-\r
-/* ------------ RCC registers bit address in the alias region ----------- */\r
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)\r
-\r
-/* --- CR Register ---*/\r
-\r
-/* Alias word address of HSION bit */\r
-#define CR_OFFSET (RCC_OFFSET + 0x00)\r
-#define HSION_BitNumber 0x00\r
-#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))\r
-\r
-/* Alias word address of PLLON bit */\r
-#define PLLON_BitNumber 0x18\r
-#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))\r
-\r
-#ifdef STM32F10X_CL\r
- /* Alias word address of PLL2ON bit */\r
- #define PLL2ON_BitNumber 0x1A\r
- #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))\r
-\r
- /* Alias word address of PLL3ON bit */\r
- #define PLL3ON_BitNumber 0x1C\r
- #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))\r
-#endif /* STM32F10X_CL */ \r
-\r
-/* Alias word address of CSSON bit */\r
-#define CSSON_BitNumber 0x13\r
-#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))\r
-\r
-/* --- CFGR Register ---*/\r
-\r
-/* Alias word address of USBPRE bit */\r
-#define CFGR_OFFSET (RCC_OFFSET + 0x04)\r
-\r
-#ifndef STM32F10X_CL\r
- #define USBPRE_BitNumber 0x16\r
- #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))\r
-#else\r
- #define OTGFSPRE_BitNumber 0x16\r
- #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))\r
-#endif /* STM32F10X_CL */ \r
-\r
-/* --- BDCR Register ---*/\r
-\r
-/* Alias word address of RTCEN bit */\r
-#define BDCR_OFFSET (RCC_OFFSET + 0x20)\r
-#define RTCEN_BitNumber 0x0F\r
-#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))\r
-\r
-/* Alias word address of BDRST bit */\r
-#define BDRST_BitNumber 0x10\r
-#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))\r
-\r
-/* --- CSR Register ---*/\r
-\r
-/* Alias word address of LSION bit */\r
-#define CSR_OFFSET (RCC_OFFSET + 0x24)\r
-#define LSION_BitNumber 0x00\r
-#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))\r
-\r
-#ifdef STM32F10X_CL\r
-/* --- CFGR2 Register ---*/\r
-\r
- /* Alias word address of I2S2SRC bit */\r
- #define CFGR2_OFFSET (RCC_OFFSET + 0x2C)\r
- #define I2S2SRC_BitNumber 0x11\r
- #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))\r
-\r
- /* Alias word address of I2S3SRC bit */\r
- #define I2S3SRC_BitNumber 0x12\r
- #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))\r
-#endif /* STM32F10X_CL */\r
-\r
-/* ---------------------- RCC registers bit mask ------------------------ */\r
-\r
-/* CR register bit mask */\r
-#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)\r
-#define CR_HSEBYP_Set ((uint32_t)0x00040000)\r
-#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)\r
-#define CR_HSEON_Set ((uint32_t)0x00010000)\r
-#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)\r
-\r
-/* CFGR register bit mask */\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) \r
- #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF)\r
-#else\r
- #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)\r
-#endif /* STM32F10X_CL */ \r
-\r
-#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)\r
-#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000)\r
-#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)\r
-#define CFGR_SWS_Mask ((uint32_t)0x0000000C)\r
-#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)\r
-#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)\r
-#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)\r
-#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)\r
-#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)\r
-#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)\r
-#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)\r
-#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)\r
-#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)\r
-\r
-/* CSR register bit mask */\r
-#define CSR_RMVF_Set ((uint32_t)0x01000000)\r
-\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) \r
-/* CFGR2 register bit mask */\r
- #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000)\r
- #define CFGR2_PREDIV1 ((uint32_t)0x0000000F)\r
-#endif\r
-#ifdef STM32F10X_CL\r
- #define CFGR2_PREDIV2 ((uint32_t)0x000000F0)\r
- #define CFGR2_PLL2MUL ((uint32_t)0x00000F00)\r
- #define CFGR2_PLL3MUL ((uint32_t)0x0000F000)\r
-#endif /* STM32F10X_CL */ \r
-\r
-/* RCC Flag Mask */\r
-#define FLAG_Mask ((uint8_t)0x1F)\r
-\r
-#ifndef HSI_Value\r
-/* Typical Value of the HSI in Hz */\r
- #define HSI_Value ((uint32_t)8000000)\r
-#endif /* HSI_Value */\r
-\r
-/* CIR register byte 2 (Bits[15:8]) base address */\r
-#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)\r
-\r
-/* CIR register byte 3 (Bits[23:16]) base address */\r
-#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)\r
-\r
-/* CFGR register byte 4 (Bits[31:24]) base address */\r
-#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)\r
-\r
-/* BDCR register base address */\r
-#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)\r
-\r
-#ifndef HSEStartUp_TimeOut\r
-/* Time out for HSE start up */\r
- #define HSEStartUp_TimeOut ((uint16_t)0x0500)\r
-#endif /* HSEStartUp_TimeOut */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RCC_Private_Macros\r
- * @{\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RCC_Private_Variables\r
- * @{\r
- */ \r
-\r
-static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\r
-static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Resets the RCC clock configuration to the default reset state.\r
- * @param None\r
- * @retval None\r
- */\r
-void RCC_DeInit(void)\r
-{\r
- /* Set HSION bit */\r
- RCC->CR |= (uint32_t)0x00000001;\r
-\r
- /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */\r
-#ifndef STM32F10X_CL\r
- RCC->CFGR &= (uint32_t)0xF8FF0000;\r
-#else\r
- RCC->CFGR &= (uint32_t)0xF0FF0000;\r
-#endif /* STM32F10X_CL */ \r
- \r
- /* Reset HSEON, CSSON and PLLON bits */\r
- RCC->CR &= (uint32_t)0xFEF6FFFF;\r
-\r
- /* Reset HSEBYP bit */\r
- RCC->CR &= (uint32_t)0xFFFBFFFF;\r
-\r
- /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */\r
- RCC->CFGR &= (uint32_t)0xFF80FFFF;\r
-\r
-#ifdef STM32F10X_CL\r
- /* Reset PLL2ON and PLL3ON bits */\r
- RCC->CR &= (uint32_t)0xEBFFFFFF;\r
-\r
- /* Disable all interrupts and clear pending bits */\r
- RCC->CIR = 0x00FF0000;\r
-\r
- /* Reset CFGR2 register */\r
- RCC->CFGR2 = 0x00000000;\r
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) \r
- /* Disable all interrupts and clear pending bits */\r
- RCC->CIR = 0x009F0000;\r
-\r
- /* Reset CFGR2 register */\r
- RCC->CFGR2 = 0x00000000; \r
-#else\r
- /* Disable all interrupts and clear pending bits */\r
- RCC->CIR = 0x009F0000;\r
-#endif /* STM32F10X_CL */\r
-\r
-}\r
-\r
-/**\r
- * @brief Configures the External High Speed oscillator (HSE).\r
- * @note HSE can not be stopped if it is used directly or through the PLL as system clock.\r
- * @param RCC_HSE: specifies the new state of the HSE.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_HSE_OFF: HSE oscillator OFF\r
- * @arg RCC_HSE_ON: HSE oscillator ON\r
- * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock\r
- * @retval None\r
- */\r
-void RCC_HSEConfig(uint32_t RCC_HSE)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_HSE(RCC_HSE));\r
- /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/\r
- /* Reset HSEON bit */\r
- RCC->CR &= CR_HSEON_Reset;\r
- /* Reset HSEBYP bit */\r
- RCC->CR &= CR_HSEBYP_Reset;\r
- /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */\r
- switch(RCC_HSE)\r
- {\r
- case RCC_HSE_ON:\r
- /* Set HSEON bit */\r
- RCC->CR |= CR_HSEON_Set;\r
- break;\r
- \r
- case RCC_HSE_Bypass:\r
- /* Set HSEBYP and HSEON bits */\r
- RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;\r
- break;\r
- \r
- default:\r
- break;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Waits for HSE start-up.\r
- * @param None\r
- * @retval An ErrorStatus enumuration value:\r
- * - SUCCESS: HSE oscillator is stable and ready to use\r
- * - ERROR: HSE oscillator not yet ready\r
- */\r
-ErrorStatus RCC_WaitForHSEStartUp(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0;\r
- ErrorStatus status = ERROR;\r
- FlagStatus HSEStatus = RESET;\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);\r
- StartUpCounter++; \r
- } while((StartUpCounter != HSEStartUp_TimeOut) && (HSEStatus == RESET));\r
- \r
- if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)\r
- {\r
- status = SUCCESS;\r
- }\r
- else\r
- {\r
- status = ERROR;\r
- } \r
- return (status);\r
-}\r
-\r
-/**\r
- * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.\r
- * @param HSICalibrationValue: specifies the calibration trimming value.\r
- * This parameter must be a number between 0 and 0x1F.\r
- * @retval None\r
- */\r
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));\r
- tmpreg = RCC->CR;\r
- /* Clear HSITRIM[4:0] bits */\r
- tmpreg &= CR_HSITRIM_Mask;\r
- /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */\r
- tmpreg |= (uint32_t)HSICalibrationValue << 3;\r
- /* Store the new value */\r
- RCC->CR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Internal High Speed oscillator (HSI).\r
- * @note HSI can not be stopped if it is used directly or through the PLL as system clock.\r
- * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_HSICmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Configures the PLL clock source and multiplication factor.\r
- * @note This function must be used only when the PLL is disabled.\r
- * @param RCC_PLLSource: specifies the PLL entry clock source.\r
- * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, \r
- * this parameter can be one of the following values:\r
- * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry\r
- * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry\r
- * For @b other_STM32_devices, this parameter can be one of the following values:\r
- * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry\r
- * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry\r
- * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry \r
- * @param RCC_PLLMul: specifies the PLL multiplication factor.\r
- * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}\r
- * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] \r
- * @retval None\r
- */\r
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));\r
- assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));\r
-\r
- tmpreg = RCC->CFGR;\r
- /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */\r
- tmpreg &= CFGR_PLL_Mask;\r
- /* Set the PLL configuration bits */\r
- tmpreg |= RCC_PLLSource | RCC_PLLMul;\r
- /* Store the new value */\r
- RCC->CFGR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the PLL.\r
- * @note The PLL can not be disabled if it is used as system clock.\r
- * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_PLLCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;\r
-}\r
-\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL)\r
-/**\r
- * @brief Configures the PREDIV1 division factor.\r
- * @note \r
- * - This function must be used only when the PLL is disabled.\r
- * - This function applies only to STM32 Connectivity line and Value line \r
- * devices.\r
- * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock\r
- * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock\r
- * @note \r
- * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE \r
- * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.\r
- * This parameter can be RCC_PREDIV1_Divx where x:[1,16]\r
- * @retval None\r
- */\r
-void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));\r
- assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));\r
-\r
- tmpreg = RCC->CFGR2;\r
- /* Clear PREDIV1[3:0] and PREDIV1SRC bits */\r
- tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);\r
- /* Set the PREDIV1 clock source and division factor */\r
- tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;\r
- /* Store the new value */\r
- RCC->CFGR2 = tmpreg;\r
-}\r
-#endif\r
-\r
-#ifdef STM32F10X_CL\r
-/**\r
- * @brief Configures the PREDIV2 division factor.\r
- * @note \r
- * - This function must be used only when both PLL2 and PLL3 are disabled.\r
- * - This function applies only to STM32 Connectivity line devices.\r
- * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.\r
- * This parameter can be RCC_PREDIV2_Divx where x:[1,16]\r
- * @retval None\r
- */\r
-void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));\r
-\r
- tmpreg = RCC->CFGR2;\r
- /* Clear PREDIV2[3:0] bits */\r
- tmpreg &= ~CFGR2_PREDIV2;\r
- /* Set the PREDIV2 division factor */\r
- tmpreg |= RCC_PREDIV2_Div;\r
- /* Store the new value */\r
- RCC->CFGR2 = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Configures the PLL2 multiplication factor.\r
- * @note\r
- * - This function must be used only when the PLL2 is disabled.\r
- * - This function applies only to STM32 Connectivity line devices.\r
- * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor.\r
- * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}\r
- * @retval None\r
- */\r
-void RCC_PLL2Config(uint32_t RCC_PLL2Mul)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));\r
-\r
- tmpreg = RCC->CFGR2;\r
- /* Clear PLL2Mul[3:0] bits */\r
- tmpreg &= ~CFGR2_PLL2MUL;\r
- /* Set the PLL2 configuration bits */\r
- tmpreg |= RCC_PLL2Mul;\r
- /* Store the new value */\r
- RCC->CFGR2 = tmpreg;\r
-}\r
-\r
-\r
-/**\r
- * @brief Enables or disables the PLL2.\r
- * @note \r
- * - The PLL2 can not be disabled if it is used indirectly as system clock\r
- * (i.e. it is used as PLL clock entry that is used as System clock).\r
- * - This function applies only to STM32 Connectivity line devices.\r
- * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_PLL2Cmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;\r
-}\r
-\r
-\r
-/**\r
- * @brief Configures the PLL3 multiplication factor.\r
- * @note \r
- * - This function must be used only when the PLL3 is disabled.\r
- * - This function applies only to STM32 Connectivity line devices.\r
- * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor.\r
- * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}\r
- * @retval None\r
- */\r
-void RCC_PLL3Config(uint32_t RCC_PLL3Mul)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));\r
-\r
- tmpreg = RCC->CFGR2;\r
- /* Clear PLL3Mul[3:0] bits */\r
- tmpreg &= ~CFGR2_PLL3MUL;\r
- /* Set the PLL3 configuration bits */\r
- tmpreg |= RCC_PLL3Mul;\r
- /* Store the new value */\r
- RCC->CFGR2 = tmpreg;\r
-}\r
-\r
-\r
-/**\r
- * @brief Enables or disables the PLL3.\r
- * @note This function applies only to STM32 Connectivity line devices.\r
- * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_PLL3Cmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
-\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;\r
-}\r
-#endif /* STM32F10X_CL */\r
-\r
-/**\r
- * @brief Configures the system clock (SYSCLK).\r
- * @param RCC_SYSCLKSource: specifies the clock source used as system clock.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock\r
- * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock\r
- * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock\r
- * @retval None\r
- */\r
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));\r
- tmpreg = RCC->CFGR;\r
- /* Clear SW[1:0] bits */\r
- tmpreg &= CFGR_SW_Mask;\r
- /* Set SW[1:0] bits according to RCC_SYSCLKSource value */\r
- tmpreg |= RCC_SYSCLKSource;\r
- /* Store the new value */\r
- RCC->CFGR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Returns the clock source used as system clock.\r
- * @param None\r
- * @retval The clock source used as system clock. The returned value can\r
- * be one of the following:\r
- * - 0x00: HSI used as system clock\r
- * - 0x04: HSE used as system clock\r
- * - 0x08: PLL used as system clock\r
- */\r
-uint8_t RCC_GetSYSCLKSource(void)\r
-{\r
- return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));\r
-}\r
-\r
-/**\r
- * @brief Configures the AHB clock (HCLK).\r
- * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from \r
- * the system clock (SYSCLK).\r
- * This parameter can be one of the following values:\r
- * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK\r
- * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2\r
- * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4\r
- * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8\r
- * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16\r
- * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64\r
- * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128\r
- * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256\r
- * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512\r
- * @retval None\r
- */\r
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_RCC_HCLK(RCC_SYSCLK));\r
- tmpreg = RCC->CFGR;\r
- /* Clear HPRE[3:0] bits */\r
- tmpreg &= CFGR_HPRE_Reset_Mask;\r
- /* Set HPRE[3:0] bits according to RCC_SYSCLK value */\r
- tmpreg |= RCC_SYSCLK;\r
- /* Store the new value */\r
- RCC->CFGR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Configures the Low Speed APB clock (PCLK1).\r
- * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from \r
- * the AHB clock (HCLK).\r
- * This parameter can be one of the following values:\r
- * @arg RCC_HCLK_Div1: APB1 clock = HCLK\r
- * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2\r
- * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4\r
- * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8\r
- * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16\r
- * @retval None\r
- */\r
-void RCC_PCLK1Config(uint32_t RCC_HCLK)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PCLK(RCC_HCLK));\r
- tmpreg = RCC->CFGR;\r
- /* Clear PPRE1[2:0] bits */\r
- tmpreg &= CFGR_PPRE1_Reset_Mask;\r
- /* Set PPRE1[2:0] bits according to RCC_HCLK value */\r
- tmpreg |= RCC_HCLK;\r
- /* Store the new value */\r
- RCC->CFGR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Configures the High Speed APB clock (PCLK2).\r
- * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from \r
- * the AHB clock (HCLK).\r
- * This parameter can be one of the following values:\r
- * @arg RCC_HCLK_Div1: APB2 clock = HCLK\r
- * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2\r
- * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4\r
- * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8\r
- * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16\r
- * @retval None\r
- */\r
-void RCC_PCLK2Config(uint32_t RCC_HCLK)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PCLK(RCC_HCLK));\r
- tmpreg = RCC->CFGR;\r
- /* Clear PPRE2[2:0] bits */\r
- tmpreg &= CFGR_PPRE2_Reset_Mask;\r
- /* Set PPRE2[2:0] bits according to RCC_HCLK value */\r
- tmpreg |= RCC_HCLK << 3;\r
- /* Store the new value */\r
- RCC->CFGR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified RCC interrupts.\r
- * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.\r
- * \r
- * For @b STM32_Connectivity_line_devices, this parameter can be any combination\r
- * of the following values \r
- * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
- * @arg RCC_IT_LSERDY: LSE ready interrupt\r
- * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
- * @arg RCC_IT_HSERDY: HSE ready interrupt\r
- * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
- * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt\r
- * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt\r
- * \r
- * For @b other_STM32_devices, this parameter can be any combination of the \r
- * following values \r
- * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
- * @arg RCC_IT_LSERDY: LSE ready interrupt\r
- * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
- * @arg RCC_IT_HSERDY: HSE ready interrupt\r
- * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
- * \r
- * @param NewState: new state of the specified RCC interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_IT(RCC_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */\r
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;\r
- }\r
- else\r
- {\r
- /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */\r
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;\r
- }\r
-}\r
-\r
-#ifndef STM32F10X_CL\r
-/**\r
- * @brief Configures the USB clock (USBCLK).\r
- * @param RCC_USBCLKSource: specifies the USB clock source. This clock is \r
- * derived from the PLL output.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB \r
- * clock source\r
- * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source\r
- * @retval None\r
- */\r
-void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));\r
-\r
- *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;\r
-}\r
-#else\r
-/**\r
- * @brief Configures the USB OTG FS clock (OTGFSCLK).\r
- * This function applies only to STM32 Connectivity line devices.\r
- * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.\r
- * This clock is derived from the PLL output.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source\r
- * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source\r
- * @retval None\r
- */\r
-void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));\r
-\r
- *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;\r
-}\r
-#endif /* STM32F10X_CL */ \r
-\r
-/**\r
- * @brief Configures the ADC clock (ADCCLK).\r
- * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from \r
- * the APB2 clock (PCLK2).\r
- * This parameter can be one of the following values:\r
- * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2\r
- * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4\r
- * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6\r
- * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8\r
- * @retval None\r
- */\r
-void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_RCC_ADCCLK(RCC_PCLK2));\r
- tmpreg = RCC->CFGR;\r
- /* Clear ADCPRE[1:0] bits */\r
- tmpreg &= CFGR_ADCPRE_Reset_Mask;\r
- /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */\r
- tmpreg |= RCC_PCLK2;\r
- /* Store the new value */\r
- RCC->CFGR = tmpreg;\r
-}\r
-\r
-#ifdef STM32F10X_CL\r
-/**\r
- * @brief Configures the I2S2 clock source(I2S2CLK).\r
- * @note\r
- * - This function must be called before enabling I2S2 APB clock.\r
- * - This function applies only to STM32 Connectivity line devices.\r
- * @param RCC_I2S2CLKSource: specifies the I2S2 clock source.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry\r
- * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry\r
- * @retval None\r
- */\r
-void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));\r
-\r
- *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;\r
-}\r
-\r
-/**\r
- * @brief Configures the I2S3 clock source(I2S2CLK).\r
- * @note\r
- * - This function must be called before enabling I2S3 APB clock.\r
- * - This function applies only to STM32 Connectivity line devices.\r
- * @param RCC_I2S3CLKSource: specifies the I2S3 clock source.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry\r
- * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry\r
- * @retval None\r
- */\r
-void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));\r
-\r
- *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;\r
-}\r
-#endif /* STM32F10X_CL */\r
-\r
-/**\r
- * @brief Configures the External Low Speed oscillator (LSE).\r
- * @param RCC_LSE: specifies the new state of the LSE.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_LSE_OFF: LSE oscillator OFF\r
- * @arg RCC_LSE_ON: LSE oscillator ON\r
- * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock\r
- * @retval None\r
- */\r
-void RCC_LSEConfig(uint8_t RCC_LSE)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_LSE(RCC_LSE));\r
- /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/\r
- /* Reset LSEON bit */\r
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;\r
- /* Reset LSEBYP bit */\r
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;\r
- /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */\r
- switch(RCC_LSE)\r
- {\r
- case RCC_LSE_ON:\r
- /* Set LSEON bit */\r
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;\r
- break;\r
- \r
- case RCC_LSE_Bypass:\r
- /* Set LSEBYP and LSEON bits */\r
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;\r
- break; \r
- \r
- default:\r
- break; \r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Internal Low Speed oscillator (LSI).\r
- * @note LSI can not be disabled if the IWDG is running.\r
- * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_LSICmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Configures the RTC clock (RTCCLK).\r
- * @note Once the RTC clock is selected it can\92t be changed unless the Backup domain is reset.\r
- * @param RCC_RTCCLKSource: specifies the RTC clock source.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock\r
- * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock\r
- * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock\r
- * @retval None\r
- */\r
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));\r
- /* Select the RTC clock source */\r
- RCC->BDCR |= RCC_RTCCLKSource;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the RTC clock.\r
- * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.\r
- * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_RTCCLKCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Returns the frequencies of different on chip clocks.\r
- * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold\r
- * the clocks frequencies.\r
- * @retval None\r
- */\r
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)\r
-{\r
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;\r
-\r
-#ifdef STM32F10X_CL\r
- uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;\r
-#endif /* STM32F10X_CL */\r
-\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
- uint32_t prediv1factor = 0;\r
-#endif\r
- \r
- /* Get SYSCLK source -------------------------------------------------------*/\r
- tmp = RCC->CFGR & CFGR_SWS_Mask;\r
- \r
- switch (tmp)\r
- {\r
- case 0x00: /* HSI used as system clock */\r
- RCC_Clocks->SYSCLK_Frequency = HSI_Value;\r
- break;\r
- case 0x04: /* HSE used as system clock */\r
- RCC_Clocks->SYSCLK_Frequency = HSE_Value;\r
- break;\r
- case 0x08: /* PLL used as system clock */\r
-\r
- /* Get PLL clock source and multiplication factor ----------------------*/\r
- pllmull = RCC->CFGR & CFGR_PLLMull_Mask;\r
- pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;\r
- \r
-#ifndef STM32F10X_CL \r
- pllmull = ( pllmull >> 18) + 2;\r
- \r
- if (pllsource == 0x00)\r
- {/* HSI oscillator clock divided by 2 selected as PLL clock entry */\r
- RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;\r
- }\r
- else\r
- {\r
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
- prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;\r
- /* HSE oscillator clock selected as PREDIV1 clock entry */\r
- RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull; \r
- #else\r
- /* HSE selected as PLL clock entry */\r
- if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)\r
- {/* HSE oscillator clock divided by 2 */\r
- RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;\r
- }\r
- else\r
- {\r
- RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;\r
- }\r
- #endif\r
- }\r
-#else\r
- pllmull = pllmull >> 18;\r
- \r
- if (pllmull != 0x0D)\r
- {\r
- pllmull += 2;\r
- }\r
- else\r
- { /* PLL multiplication factor = PLL input clock * 6.5 */\r
- pllmull = 13 / 2; \r
- }\r
- \r
- if (pllsource == 0x00)\r
- {/* HSI oscillator clock divided by 2 selected as PLL clock entry */\r
- RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;\r
- }\r
- else\r
- {/* PREDIV1 selected as PLL clock entry */\r
- \r
- /* Get PREDIV1 clock source and division factor */\r
- prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;\r
- prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;\r
- \r
- if (prediv1source == 0)\r
- { /* HSE oscillator clock selected as PREDIV1 clock entry */\r
- RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull; \r
- }\r
- else\r
- {/* PLL2 clock selected as PREDIV1 clock entry */\r
- \r
- /* Get PREDIV2 division factor and PLL2 multiplication factor */\r
- prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;\r
- pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; \r
- RCC_Clocks->SYSCLK_Frequency = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull; \r
- }\r
- }\r
-#endif /* STM32F10X_CL */ \r
- break;\r
-\r
- default:\r
- RCC_Clocks->SYSCLK_Frequency = HSI_Value;\r
- break;\r
- }\r
-\r
- /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/\r
- /* Get HCLK prescaler */\r
- tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;\r
- tmp = tmp >> 4;\r
- presc = APBAHBPrescTable[tmp];\r
- /* HCLK clock frequency */\r
- RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;\r
- /* Get PCLK1 prescaler */\r
- tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;\r
- tmp = tmp >> 8;\r
- presc = APBAHBPrescTable[tmp];\r
- /* PCLK1 clock frequency */\r
- RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
- /* Get PCLK2 prescaler */\r
- tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;\r
- tmp = tmp >> 11;\r
- presc = APBAHBPrescTable[tmp];\r
- /* PCLK2 clock frequency */\r
- RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
- /* Get ADCCLK prescaler */\r
- tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;\r
- tmp = tmp >> 14;\r
- presc = ADCPrescTable[tmp];\r
- /* ADCCLK clock frequency */\r
- RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the AHB peripheral clock.\r
- * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
- * \r
- * For @b STM32_Connectivity_line_devices, this parameter can be any combination\r
- * of the following values: \r
- * @arg RCC_AHBPeriph_DMA1\r
- * @arg RCC_AHBPeriph_DMA2\r
- * @arg RCC_AHBPeriph_SRAM\r
- * @arg RCC_AHBPeriph_FLITF\r
- * @arg RCC_AHBPeriph_CRC\r
- * @arg RCC_AHBPeriph_OTG_FS \r
- * @arg RCC_AHBPeriph_ETH_MAC \r
- * @arg RCC_AHBPeriph_ETH_MAC_Tx\r
- * @arg RCC_AHBPeriph_ETH_MAC_Rx\r
- * \r
- * For @b other_STM32_devices, this parameter can be any combination of the \r
- * following values: \r
- * @arg RCC_AHBPeriph_DMA1\r
- * @arg RCC_AHBPeriph_DMA2\r
- * @arg RCC_AHBPeriph_SRAM\r
- * @arg RCC_AHBPeriph_FLITF\r
- * @arg RCC_AHBPeriph_CRC\r
- * @arg RCC_AHBPeriph_FSMC\r
- * @arg RCC_AHBPeriph_SDIO\r
- * \r
- * @note SRAM and FLITF clock can be disabled only during sleep mode.\r
- * @param NewState: new state of the specified peripheral clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- RCC->AHBENR |= RCC_AHBPeriph;\r
- }\r
- else\r
- {\r
- RCC->AHBENR &= ~RCC_AHBPeriph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the High Speed APB (APB2) peripheral clock.\r
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,\r
- * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,\r
- * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,\r
- * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,\r
- * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,\r
- * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,\r
- * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 \r
- * @param NewState: new state of the specified peripheral clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- RCC->APB2ENR |= RCC_APB2Periph;\r
- }\r
- else\r
- {\r
- RCC->APB2ENR &= ~RCC_APB2Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.\r
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,\r
- * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,\r
- * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,\r
- * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, \r
- * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,\r
- * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,\r
- * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,\r
- * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14\r
- * @param NewState: new state of the specified peripheral clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- RCC->APB1ENR |= RCC_APB1Periph;\r
- }\r
- else\r
- {\r
- RCC->APB1ENR &= ~RCC_APB1Periph;\r
- }\r
-}\r
-\r
-#ifdef STM32F10X_CL\r
-/**\r
- * @brief Forces or releases AHB peripheral reset.\r
- * @note This function applies only to STM32 Connectivity line devices.\r
- * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_AHBPeriph_OTG_FS \r
- * @arg RCC_AHBPeriph_ETH_MAC\r
- * @param NewState: new state of the specified peripheral reset.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- RCC->AHBRSTR |= RCC_AHBPeriph;\r
- }\r
- else\r
- {\r
- RCC->AHBRSTR &= ~RCC_AHBPeriph;\r
- }\r
-}\r
-#endif /* STM32F10X_CL */ \r
-\r
-/**\r
- * @brief Forces or releases High Speed APB (APB2) peripheral reset.\r
- * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,\r
- * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,\r
- * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,\r
- * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,\r
- * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,\r
- * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,\r
- * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 \r
- * @param NewState: new state of the specified peripheral reset.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- RCC->APB2RSTR |= RCC_APB2Periph;\r
- }\r
- else\r
- {\r
- RCC->APB2RSTR &= ~RCC_APB2Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Forces or releases Low Speed APB (APB1) peripheral reset.\r
- * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,\r
- * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,\r
- * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,\r
- * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, \r
- * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,\r
- * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,\r
- * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,\r
- * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 \r
- * @param NewState: new state of the specified peripheral clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- RCC->APB1RSTR |= RCC_APB1Periph;\r
- }\r
- else\r
- {\r
- RCC->APB1RSTR &= ~RCC_APB1Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Forces or releases the Backup domain reset.\r
- * @param NewState: new state of the Backup domain reset.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_BackupResetCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Clock Security System.\r
- * @param NewState: new state of the Clock Security System..\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Selects the clock source to output on MCO pin.\r
- * @param RCC_MCO: specifies the clock source to output.\r
- * \r
- * For @b STM32_Connectivity_line_devices, this parameter can be one of the\r
- * following values: \r
- * @arg RCC_MCO_NoClock: No clock selected\r
- * @arg RCC_MCO_SYSCLK: System clock selected\r
- * @arg RCC_MCO_HSI: HSI oscillator clock selected\r
- * @arg RCC_MCO_HSE: HSE oscillator clock selected\r
- * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected\r
- * @arg RCC_MCO_PLL2CLK: PLL2 clock selected \r
- * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected \r
- * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected \r
- * @arg RCC_MCO_PLL3CLK: PLL3 clock selected \r
- * \r
- * For @b other_STM32_devices, this parameter can be one of the following values: \r
- * @arg RCC_MCO_NoClock: No clock selected\r
- * @arg RCC_MCO_SYSCLK: System clock selected\r
- * @arg RCC_MCO_HSI: HSI oscillator clock selected\r
- * @arg RCC_MCO_HSE: HSE oscillator clock selected\r
- * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected\r
- * \r
- * @retval None\r
- */\r
-void RCC_MCOConfig(uint8_t RCC_MCO)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_MCO(RCC_MCO));\r
-\r
- /* Perform Byte access to MCO bits to select the MCO source */\r
- *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified RCC flag is set or not.\r
- * @param RCC_FLAG: specifies the flag to check.\r
- * \r
- * For @b STM32_Connectivity_line_devices, this parameter can be one of the\r
- * following values:\r
- * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
- * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
- * @arg RCC_FLAG_PLLRDY: PLL clock ready\r
- * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready \r
- * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready \r
- * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
- * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
- * @arg RCC_FLAG_PINRST: Pin reset\r
- * @arg RCC_FLAG_PORRST: POR/PDR reset\r
- * @arg RCC_FLAG_SFTRST: Software reset\r
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset\r
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset\r
- * @arg RCC_FLAG_LPWRRST: Low Power reset\r
- * \r
- * For @b other_STM32_devices, this parameter can be one of the following values: \r
- * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
- * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
- * @arg RCC_FLAG_PLLRDY: PLL clock ready\r
- * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
- * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
- * @arg RCC_FLAG_PINRST: Pin reset\r
- * @arg RCC_FLAG_PORRST: POR/PDR reset\r
- * @arg RCC_FLAG_SFTRST: Software reset\r
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset\r
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset\r
- * @arg RCC_FLAG_LPWRRST: Low Power reset\r
- * \r
- * @retval The new state of RCC_FLAG (SET or RESET).\r
- */\r
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)\r
-{\r
- uint32_t tmp = 0;\r
- uint32_t statusreg = 0;\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_RCC_FLAG(RCC_FLAG));\r
-\r
- /* Get the RCC register index */\r
- tmp = RCC_FLAG >> 5;\r
- if (tmp == 1) /* The flag to check is in CR register */\r
- {\r
- statusreg = RCC->CR;\r
- }\r
- else if (tmp == 2) /* The flag to check is in BDCR register */\r
- {\r
- statusreg = RCC->BDCR;\r
- }\r
- else /* The flag to check is in CSR register */\r
- {\r
- statusreg = RCC->CSR;\r
- }\r
-\r
- /* Get the flag position */\r
- tmp = RCC_FLAG & FLAG_Mask;\r
- if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
-\r
- /* Return the flag status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the RCC reset flags.\r
- * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,\r
- * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST\r
- * @param None\r
- * @retval None\r
- */\r
-void RCC_ClearFlag(void)\r
-{\r
- /* Set RMVF bit to clear the reset flags */\r
- RCC->CSR |= CSR_RMVF_Set;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified RCC interrupt has occurred or not.\r
- * @param RCC_IT: specifies the RCC interrupt source to check.\r
- * \r
- * For @b STM32_Connectivity_line_devices, this parameter can be one of the\r
- * following values:\r
- * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
- * @arg RCC_IT_LSERDY: LSE ready interrupt\r
- * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
- * @arg RCC_IT_HSERDY: HSE ready interrupt\r
- * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
- * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt \r
- * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt \r
- * @arg RCC_IT_CSS: Clock Security System interrupt\r
- * \r
- * For @b other_STM32_devices, this parameter can be one of the following values: \r
- * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
- * @arg RCC_IT_LSERDY: LSE ready interrupt\r
- * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
- * @arg RCC_IT_HSERDY: HSE ready interrupt\r
- * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
- * @arg RCC_IT_CSS: Clock Security System interrupt\r
- * \r
- * @retval The new state of RCC_IT (SET or RESET).\r
- */\r
-ITStatus RCC_GetITStatus(uint8_t RCC_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_RCC_GET_IT(RCC_IT));\r
-\r
- /* Check the status of the specified RCC interrupt */\r
- if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
-\r
- /* Return the RCC_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the RCC\92s interrupt pending bits.\r
- * @param RCC_IT: specifies the interrupt pending bit to clear.\r
- * \r
- * For @b STM32_Connectivity_line_devices, this parameter can be any combination\r
- * of the following values:\r
- * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
- * @arg RCC_IT_LSERDY: LSE ready interrupt\r
- * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
- * @arg RCC_IT_HSERDY: HSE ready interrupt\r
- * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
- * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt \r
- * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt \r
- * @arg RCC_IT_CSS: Clock Security System interrupt\r
- * \r
- * For @b other_STM32_devices, this parameter can be any combination of the\r
- * following values: \r
- * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
- * @arg RCC_IT_LSERDY: LSE ready interrupt\r
- * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
- * @arg RCC_IT_HSERDY: HSE ready interrupt\r
- * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
- * \r
- * @arg RCC_IT_CSS: Clock Security System interrupt\r
- * @retval None\r
- */\r
-void RCC_ClearITPendingBit(uint8_t RCC_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_CLEAR_IT(RCC_IT));\r
-\r
- /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt\r
- pending bits */\r
- *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_rtc.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the RTC firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_rtc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup RTC \r
- * @brief RTC driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup RTC_Private_TypesDefinitions\r
- * @{\r
- */ \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Private_Defines\r
- * @{\r
- */\r
-\r
-#define CRL_CNF_Set ((uint16_t)0x0010) /*!< Configuration Flag Enable Mask */\r
-#define CRL_CNF_Reset ((uint16_t)0xFFEF) /*!< Configuration Flag Disable Mask */\r
-#define RTC_LSB_Mask ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */\r
-#define PRLH_MSB_Mask ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified RTC interrupts.\r
- * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg RTC_IT_OW: Overflow interrupt\r
- * @arg RTC_IT_ALR: Alarm interrupt\r
- * @arg RTC_IT_SEC: Second interrupt\r
- * @param NewState: new state of the specified RTC interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RTC_IT(RTC_IT)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- RTC->CRH |= RTC_IT;\r
- }\r
- else\r
- {\r
- RTC->CRH &= (uint16_t)~RTC_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enters the RTC configuration mode.\r
- * @param None\r
- * @retval None\r
- */\r
-void RTC_EnterConfigMode(void)\r
-{\r
- /* Set the CNF flag to enter in the Configuration Mode */\r
- RTC->CRL |= CRL_CNF_Set;\r
-}\r
-\r
-/**\r
- * @brief Exits from the RTC configuration mode.\r
- * @param None\r
- * @retval None\r
- */\r
-void RTC_ExitConfigMode(void)\r
-{\r
- /* Reset the CNF flag to exit from the Configuration Mode */\r
- RTC->CRL &= CRL_CNF_Reset;\r
-}\r
-\r
-/**\r
- * @brief Gets the RTC counter value.\r
- * @param None\r
- * @retval RTC counter value.\r
- */\r
-uint32_t RTC_GetCounter(void)\r
-{\r
- uint16_t tmp = 0;\r
- tmp = RTC->CNTL;\r
- return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;\r
-}\r
-\r
-/**\r
- * @brief Sets the RTC counter value.\r
- * @param CounterValue: RTC counter new value.\r
- * @retval None\r
- */\r
-void RTC_SetCounter(uint32_t CounterValue)\r
-{ \r
- RTC_EnterConfigMode();\r
- /* Set RTC COUNTER MSB word */\r
- RTC->CNTH = CounterValue >> 16;\r
- /* Set RTC COUNTER LSB word */\r
- RTC->CNTL = (CounterValue & RTC_LSB_Mask);\r
- RTC_ExitConfigMode();\r
-}\r
-\r
-/**\r
- * @brief Sets the RTC prescaler value.\r
- * @param PrescalerValue: RTC prescaler new value.\r
- * @retval None\r
- */\r
-void RTC_SetPrescaler(uint32_t PrescalerValue)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RTC_PRESCALER(PrescalerValue));\r
- \r
- RTC_EnterConfigMode();\r
- /* Set RTC PRESCALER MSB word */\r
- RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 16;\r
- /* Set RTC PRESCALER LSB word */\r
- RTC->PRLL = (PrescalerValue & RTC_LSB_Mask);\r
- RTC_ExitConfigMode();\r
-}\r
-\r
-/**\r
- * @brief Sets the RTC alarm value.\r
- * @param AlarmValue: RTC alarm new value.\r
- * @retval None\r
- */\r
-void RTC_SetAlarm(uint32_t AlarmValue)\r
-{ \r
- RTC_EnterConfigMode();\r
- /* Set the ALARM MSB word */\r
- RTC->ALRH = AlarmValue >> 16;\r
- /* Set the ALARM LSB word */\r
- RTC->ALRL = (AlarmValue & RTC_LSB_Mask);\r
- RTC_ExitConfigMode();\r
-}\r
-\r
-/**\r
- * @brief Gets the RTC divider value.\r
- * @param None\r
- * @retval RTC Divider value.\r
- */\r
-uint32_t RTC_GetDivider(void)\r
-{\r
- uint32_t tmp = 0x00;\r
- tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;\r
- tmp |= RTC->DIVL;\r
- return tmp;\r
-}\r
-\r
-/**\r
- * @brief Waits until last write operation on RTC registers has finished.\r
- * @note This function must be called before any write to RTC registers.\r
- * @param None\r
- * @retval None\r
- */\r
-void RTC_WaitForLastTask(void)\r
-{\r
- /* Loop until RTOFF flag is set */\r
- while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)\r
- {\r
- }\r
-}\r
-\r
-/**\r
- * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)\r
- * are synchronized with RTC APB clock.\r
- * @note This function must be called before any read operation after an APB reset\r
- * or an APB clock stop.\r
- * @param None\r
- * @retval None\r
- */\r
-void RTC_WaitForSynchro(void)\r
-{\r
- /* Clear RSF flag */\r
- RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;\r
- /* Loop until RSF flag is set */\r
- while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)\r
- {\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified RTC flag is set or not.\r
- * @param RTC_FLAG: specifies the flag to check.\r
- * This parameter can be one the following values:\r
- * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag\r
- * @arg RTC_FLAG_RSF: Registers Synchronized flag\r
- * @arg RTC_FLAG_OW: Overflow flag\r
- * @arg RTC_FLAG_ALR: Alarm flag\r
- * @arg RTC_FLAG_SEC: Second flag\r
- * @retval The new state of RTC_FLAG (SET or RESET).\r
- */\r
-FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); \r
- \r
- if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the RTC\92s pending flags.\r
- * @param RTC_FLAG: specifies the flag to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after\r
- * an APB reset or an APB Clock stop.\r
- * @arg RTC_FLAG_OW: Overflow flag\r
- * @arg RTC_FLAG_ALR: Alarm flag\r
- * @arg RTC_FLAG_SEC: Second flag\r
- * @retval None\r
- */\r
-void RTC_ClearFlag(uint16_t RTC_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); \r
- \r
- /* Clear the coressponding RTC flag */\r
- RTC->CRL &= (uint16_t)~RTC_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified RTC interrupt has occured or not.\r
- * @param RTC_IT: specifies the RTC interrupts sources to check.\r
- * This parameter can be one of the following values:\r
- * @arg RTC_IT_OW: Overflow interrupt\r
- * @arg RTC_IT_ALR: Alarm interrupt\r
- * @arg RTC_IT_SEC: Second interrupt\r
- * @retval The new state of the RTC_IT (SET or RESET).\r
- */\r
-ITStatus RTC_GetITStatus(uint16_t RTC_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_RTC_GET_IT(RTC_IT)); \r
- \r
- bitstatus = (ITStatus)(RTC->CRL & RTC_IT);\r
- if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the RTC\92s interrupt pending bits.\r
- * @param RTC_IT: specifies the interrupt pending bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg RTC_IT_OW: Overflow interrupt\r
- * @arg RTC_IT_ALR: Alarm interrupt\r
- * @arg RTC_IT_SEC: Second interrupt\r
- * @retval None\r
- */\r
-void RTC_ClearITPendingBit(uint16_t RTC_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RTC_IT(RTC_IT)); \r
- \r
- /* Clear the coressponding RTC pending bit */\r
- RTC->CRL &= (uint16_t)~RTC_IT;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_sdio.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the SDIO firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_sdio.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup SDIO \r
- * @brief SDIO driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup SDIO_Private_TypesDefinitions\r
- * @{\r
- */ \r
-\r
-/* ------------ SDIO registers bit address in the alias region ----------- */\r
-#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)\r
-\r
-/* --- CLKCR Register ---*/\r
-\r
-/* Alias word address of CLKEN bit */\r
-#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)\r
-#define CLKEN_BitNumber 0x08\r
-#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))\r
-\r
-/* --- CMD Register ---*/\r
-\r
-/* Alias word address of SDIOSUSPEND bit */\r
-#define CMD_OFFSET (SDIO_OFFSET + 0x0C)\r
-#define SDIOSUSPEND_BitNumber 0x0B\r
-#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))\r
-\r
-/* Alias word address of ENCMDCOMPL bit */\r
-#define ENCMDCOMPL_BitNumber 0x0C\r
-#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))\r
-\r
-/* Alias word address of NIEN bit */\r
-#define NIEN_BitNumber 0x0D\r
-#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))\r
-\r
-/* Alias word address of ATACMD bit */\r
-#define ATACMD_BitNumber 0x0E\r
-#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))\r
-\r
-/* --- DCTRL Register ---*/\r
-\r
-/* Alias word address of DMAEN bit */\r
-#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)\r
-#define DMAEN_BitNumber 0x03\r
-#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))\r
-\r
-/* Alias word address of RWSTART bit */\r
-#define RWSTART_BitNumber 0x08\r
-#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))\r
-\r
-/* Alias word address of RWSTOP bit */\r
-#define RWSTOP_BitNumber 0x09\r
-#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))\r
-\r
-/* Alias word address of RWMOD bit */\r
-#define RWMOD_BitNumber 0x0A\r
-#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))\r
-\r
-/* Alias word address of SDIOEN bit */\r
-#define SDIOEN_BitNumber 0x0B\r
-#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))\r
-\r
-/* ---------------------- SDIO registers bit mask ------------------------ */\r
-\r
-/* --- CLKCR Register ---*/\r
-\r
-/* CLKCR register clear mask */\r
-#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) \r
-\r
-/* --- PWRCTRL Register ---*/\r
-\r
-/* SDIO PWRCTRL Mask */\r
-#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)\r
-\r
-/* --- DCTRL Register ---*/\r
-\r
-/* SDIO DCTRL Clear Mask */\r
-#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)\r
-\r
-/* --- CMD Register ---*/\r
-\r
-/* CMD Register clear mask */\r
-#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)\r
-\r
-/* SDIO RESP Registers Address */\r
-#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Private_Defines\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the SDIO peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void SDIO_DeInit(void)\r
-{\r
- SDIO->POWER = 0x00000000;\r
- SDIO->CLKCR = 0x00000000;\r
- SDIO->ARG = 0x00000000;\r
- SDIO->CMD = 0x00000000;\r
- SDIO->DTIMER = 0x00000000;\r
- SDIO->DLEN = 0x00000000;\r
- SDIO->DCTRL = 0x00000000;\r
- SDIO->ICR = 0x00C007FF;\r
- SDIO->MASK = 0x00000000;\r
-}\r
-\r
-/**\r
- * @brief Initializes the SDIO peripheral according to the specified \r
- * parameters in the SDIO_InitStruct.\r
- * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure \r
- * that contains the configuration information for the SDIO peripheral.\r
- * @retval None\r
- */\r
-void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));\r
- assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));\r
- assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));\r
- assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));\r
- assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); \r
- \r
-/*---------------------------- SDIO CLKCR Configuration ------------------------*/ \r
- /* Get the SDIO CLKCR value */\r
- tmpreg = SDIO->CLKCR;\r
- \r
- /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */\r
- tmpreg &= CLKCR_CLEAR_MASK;\r
- \r
- /* Set CLKDIV bits according to SDIO_ClockDiv value */\r
- /* Set PWRSAV bit according to SDIO_ClockPowerSave value */\r
- /* Set BYPASS bit according to SDIO_ClockBypass value */\r
- /* Set WIDBUS bits according to SDIO_BusWide value */\r
- /* Set NEGEDGE bits according to SDIO_ClockEdge value */\r
- /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */\r
- tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |\r
- SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |\r
- SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); \r
- \r
- /* Write to SDIO CLKCR */\r
- SDIO->CLKCR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each SDIO_InitStruct member with its default value.\r
- * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which \r
- * will be initialized.\r
- * @retval None\r
- */\r
-void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)\r
-{\r
- /* SDIO_InitStruct members default value */\r
- SDIO_InitStruct->SDIO_ClockDiv = 0x00;\r
- SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;\r
- SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;\r
- SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;\r
- SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;\r
- SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SDIO Clock.\r
- * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_ClockCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Sets the power status of the controller.\r
- * @param SDIO_PowerState: new state of the Power state. \r
- * This parameter can be one of the following values:\r
- * @arg SDIO_PowerState_OFF\r
- * @arg SDIO_PowerState_ON\r
- * @retval None\r
- */\r
-void SDIO_SetPowerState(uint32_t SDIO_PowerState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));\r
- \r
- SDIO->POWER &= PWR_PWRCTRL_MASK;\r
- SDIO->POWER |= SDIO_PowerState;\r
-}\r
-\r
-/**\r
- * @brief Gets the power status of the controller.\r
- * @param None\r
- * @retval Power status of the controller. The returned value can\r
- * be one of the following:\r
- * - 0x00: Power OFF\r
- * - 0x02: Power UP\r
- * - 0x03: Power ON \r
- */\r
-uint32_t SDIO_GetPowerState(void)\r
-{\r
- return (SDIO->POWER & (~PWR_PWRCTRL_MASK));\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SDIO interrupts.\r
- * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.\r
- * This parameter can be one or a combination of the following values:\r
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r
- * bus mode interrupt\r
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt\r
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt\r
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt\r
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt\r
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt\r
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt\r
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt\r
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt\r
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt\r
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt\r
- * @param NewState: new state of the specified SDIO interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None \r
- */\r
-void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SDIO_IT(SDIO_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the SDIO interrupts */\r
- SDIO->MASK |= SDIO_IT;\r
- }\r
- else\r
- {\r
- /* Disable the SDIO interrupts */\r
- SDIO->MASK &= ~SDIO_IT;\r
- } \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SDIO DMA request.\r
- * @param NewState: new state of the selected SDIO DMA request.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_DMACmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Initializes the SDIO Command according to the specified \r
- * parameters in the SDIO_CmdInitStruct and send the command.\r
- * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef \r
- * structure that contains the configuration information for the SDIO command.\r
- * @retval None\r
- */\r
-void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));\r
- assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));\r
- assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));\r
- assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));\r
- \r
-/*---------------------------- SDIO ARG Configuration ------------------------*/\r
- /* Set the SDIO Argument value */\r
- SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;\r
- \r
-/*---------------------------- SDIO CMD Configuration ------------------------*/ \r
- /* Get the SDIO CMD value */\r
- tmpreg = SDIO->CMD;\r
- /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */\r
- tmpreg &= CMD_CLEAR_MASK;\r
- /* Set CMDINDEX bits according to SDIO_CmdIndex value */\r
- /* Set WAITRESP bits according to SDIO_Response value */\r
- /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */\r
- /* Set CPSMEN bits according to SDIO_CPSM value */\r
- tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response\r
- | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;\r
- \r
- /* Write to SDIO CMD */\r
- SDIO->CMD = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each SDIO_CmdInitStruct member with its default value.\r
- * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef \r
- * structure which will be initialized.\r
- * @retval None\r
- */\r
-void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)\r
-{\r
- /* SDIO_CmdInitStruct members default value */\r
- SDIO_CmdInitStruct->SDIO_Argument = 0x00;\r
- SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;\r
- SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;\r
- SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;\r
- SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;\r
-}\r
-\r
-/**\r
- * @brief Returns command index of last command for which response received.\r
- * @param None\r
- * @retval Returns the command index of the last command response received.\r
- */\r
-uint8_t SDIO_GetCommandResponse(void)\r
-{\r
- return (uint8_t)(SDIO->RESPCMD);\r
-}\r
-\r
-/**\r
- * @brief Returns response received from the card for the last command.\r
- * @param SDIO_RESP: Specifies the SDIO response register. \r
- * This parameter can be one of the following values:\r
- * @arg SDIO_RESP1: Response Register 1\r
- * @arg SDIO_RESP2: Response Register 2\r
- * @arg SDIO_RESP3: Response Register 3\r
- * @arg SDIO_RESP4: Response Register 4\r
- * @retval The Corresponding response register value.\r
- */\r
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)\r
-{\r
- __IO uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_SDIO_RESP(SDIO_RESP));\r
-\r
- tmp = SDIO_RESP_ADDR + SDIO_RESP;\r
- \r
- return (*(__IO uint32_t *) tmp); \r
-}\r
-\r
-/**\r
- * @brief Initializes the SDIO data path according to the specified \r
- * parameters in the SDIO_DataInitStruct.\r
- * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that\r
- * contains the configuration information for the SDIO command.\r
- * @retval None\r
- */\r
-void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));\r
- assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));\r
- assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));\r
- assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));\r
- assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));\r
-\r
-/*---------------------------- SDIO DTIMER Configuration ---------------------*/\r
- /* Set the SDIO Data TimeOut value */\r
- SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;\r
-\r
-/*---------------------------- SDIO DLEN Configuration -----------------------*/\r
- /* Set the SDIO DataLength value */\r
- SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;\r
-\r
-/*---------------------------- SDIO DCTRL Configuration ----------------------*/ \r
- /* Get the SDIO DCTRL value */\r
- tmpreg = SDIO->DCTRL;\r
- /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */\r
- tmpreg &= DCTRL_CLEAR_MASK;\r
- /* Set DEN bit according to SDIO_DPSM value */\r
- /* Set DTMODE bit according to SDIO_TransferMode value */\r
- /* Set DTDIR bit according to SDIO_TransferDir value */\r
- /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */\r
- tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir\r
- | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;\r
-\r
- /* Write to SDIO DCTRL */\r
- SDIO->DCTRL = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each SDIO_DataInitStruct member with its default value.\r
- * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which\r
- * will be initialized.\r
- * @retval None\r
- */\r
-void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)\r
-{\r
- /* SDIO_DataInitStruct members default value */\r
- SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;\r
- SDIO_DataInitStruct->SDIO_DataLength = 0x00;\r
- SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;\r
- SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;\r
- SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; \r
- SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;\r
-}\r
-\r
-/**\r
- * @brief Returns number of remaining data bytes to be transferred.\r
- * @param None\r
- * @retval Number of remaining data bytes to be transferred\r
- */\r
-uint32_t SDIO_GetDataCounter(void)\r
-{ \r
- return SDIO->DCOUNT;\r
-}\r
-\r
-/**\r
- * @brief Read one data word from Rx FIFO.\r
- * @param None\r
- * @retval Data received\r
- */\r
-uint32_t SDIO_ReadData(void)\r
-{ \r
- return SDIO->FIFO;\r
-}\r
-\r
-/**\r
- * @brief Write one data word to Tx FIFO.\r
- * @param Data: 32-bit data word to write.\r
- * @retval None\r
- */\r
-void SDIO_WriteData(uint32_t Data)\r
-{ \r
- SDIO->FIFO = Data;\r
-}\r
-\r
-/**\r
- * @brief Returns the number of words left to be written to or read from FIFO. \r
- * @param None\r
- * @retval Remaining number of words.\r
- */\r
-uint32_t SDIO_GetFIFOCount(void)\r
-{ \r
- return SDIO->FIFOCNT;\r
-}\r
-\r
-/**\r
- * @brief Starts the SD I/O Read Wait operation. \r
- * @param NewState: new state of the Start SDIO Read Wait operation. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_StartSDIOReadWait(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;\r
-}\r
-\r
-/**\r
- * @brief Stops the SD I/O Read Wait operation. \r
- * @param NewState: new state of the Stop SDIO Read Wait operation. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_StopSDIOReadWait(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;\r
-}\r
-\r
-/**\r
- * @brief Sets one of the two options of inserting read wait interval.\r
- * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.\r
- * This parametre can be:\r
- * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK\r
- * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2\r
- * @retval None\r
- */\r
-void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));\r
- \r
- *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SD I/O Mode Operation.\r
- * @param NewState: new state of SDIO specific operation. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_SetSDIOOperation(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SD I/O Mode suspend command sending.\r
- * @param NewState: new state of the SD I/O Mode suspend command.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the command completion signal.\r
- * @param NewState: new state of command completion signal. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_CommandCompletionCmd(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the CE-ATA interrupt.\r
- * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_CEATAITCmd(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));\r
-}\r
-\r
-/**\r
- * @brief Sends CE-ATA command (CMD61).\r
- * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_SendCEATACmd(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified SDIO flag is set or not.\r
- * @param SDIO_FLAG: specifies the flag to check. \r
- * This parameter can be one of the following values:\r
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)\r
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout\r
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout\r
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error\r
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error\r
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)\r
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)\r
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)\r
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide \r
- * bus mode.\r
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)\r
- * @arg SDIO_FLAG_CMDACT: Command transfer in progress\r
- * @arg SDIO_FLAG_TXACT: Data transmit in progress\r
- * @arg SDIO_FLAG_RXACT: Data receive in progress\r
- * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty\r
- * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full\r
- * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full\r
- * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full\r
- * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty\r
- * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty\r
- * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO\r
- * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO\r
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received\r
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61\r
- * @retval The new state of SDIO_FLAG (SET or RESET).\r
- */\r
-FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)\r
-{ \r
- FlagStatus bitstatus = RESET;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_FLAG(SDIO_FLAG));\r
- \r
- if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the SDIO's pending flags.\r
- * @param SDIO_FLAG: specifies the flag to clear. \r
- * This parameter can be one or a combination of the following values:\r
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)\r
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout\r
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout\r
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error\r
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error\r
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)\r
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)\r
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)\r
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide \r
- * bus mode\r
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)\r
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received\r
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61\r
- * @retval None\r
- */\r
-void SDIO_ClearFlag(uint32_t SDIO_FLAG)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));\r
- \r
- SDIO->ICR = SDIO_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified SDIO interrupt has occurred or not.\r
- * @param SDIO_IT: specifies the SDIO interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r
- * bus mode interrupt\r
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt\r
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt\r
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt\r
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt\r
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt\r
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt\r
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt\r
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt\r
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt\r
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt\r
- * @retval The new state of SDIO_IT (SET or RESET).\r
- */\r
-ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)\r
-{ \r
- ITStatus bitstatus = RESET;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_GET_IT(SDIO_IT));\r
- if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) \r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the SDIO\92s interrupt pending bits.\r
- * @param SDIO_IT: specifies the interrupt pending bit to clear. \r
- * This parameter can be one or a combination of the following values:\r
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r
- * bus mode interrupt\r
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61\r
- * @retval None\r
- */\r
-void SDIO_ClearITPendingBit(uint32_t SDIO_IT)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));\r
- \r
- SDIO->ICR = SDIO_IT;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_spi.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the SPI firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_spi.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup SPI \r
- * @brief SPI driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup SPI_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup SPI_Private_Defines\r
- * @{\r
- */\r
-\r
-/* SPI SPE mask */\r
-#define CR1_SPE_Set ((uint16_t)0x0040)\r
-#define CR1_SPE_Reset ((uint16_t)0xFFBF)\r
-\r
-/* I2S I2SE mask */\r
-#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)\r
-#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)\r
-\r
-/* SPI CRCNext mask */\r
-#define CR1_CRCNext_Set ((uint16_t)0x1000)\r
-\r
-/* SPI CRCEN mask */\r
-#define CR1_CRCEN_Set ((uint16_t)0x2000)\r
-#define CR1_CRCEN_Reset ((uint16_t)0xDFFF)\r
-\r
-/* SPI SSOE mask */\r
-#define CR2_SSOE_Set ((uint16_t)0x0004)\r
-#define CR2_SSOE_Reset ((uint16_t)0xFFFB)\r
-\r
-/* SPI registers Masks */\r
-#define CR1_CLEAR_Mask ((uint16_t)0x3040)\r
-#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)\r
-\r
-/* SPI or I2S mode selection masks */\r
-#define SPI_Mode_Select ((uint16_t)0xF7FF)\r
-#define I2S_Mode_Select ((uint16_t)0x0800) \r
-\r
-/* I2S clock source selection masks */\r
-#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))\r
-#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))\r
-#define I2S_MUL_MASK ((uint32_t)(0x0000F000))\r
-#define I2S_DIV_MASK ((uint32_t)(0x000000F0))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the SPIx peripheral registers to their default\r
- * reset values (Affects also the I2Ss).\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @retval None\r
- */\r
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
-\r
- if (SPIx == SPI1)\r
- {\r
- /* Enable SPI1 reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);\r
- /* Release SPI1 from reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);\r
- }\r
- else if (SPIx == SPI2)\r
- {\r
- /* Enable SPI2 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);\r
- /* Release SPI2 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);\r
- }\r
- else\r
- {\r
- if (SPIx == SPI3)\r
- {\r
- /* Enable SPI3 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);\r
- /* Release SPI3 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the SPIx peripheral according to the specified \r
- * parameters in the SPI_InitStruct.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that\r
- * contains the configuration information for the specified SPI peripheral.\r
- * @retval None\r
- */\r
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)\r
-{\r
- uint16_t tmpreg = 0;\r
- \r
- /* check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx)); \r
- \r
- /* Check the SPI parameters */\r
- assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));\r
- assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));\r
- assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));\r
- assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));\r
- assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));\r
- assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));\r
- assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));\r
- assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));\r
- assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));\r
-\r
-/*---------------------------- SPIx CR1 Configuration ------------------------*/\r
- /* Get the SPIx CR1 value */\r
- tmpreg = SPIx->CR1;\r
- /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */\r
- tmpreg &= CR1_CLEAR_Mask;\r
- /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler\r
- master/salve mode, CPOL and CPHA */\r
- /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */\r
- /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */\r
- /* Set LSBFirst bit according to SPI_FirstBit value */\r
- /* Set BR bits according to SPI_BaudRatePrescaler value */\r
- /* Set CPOL bit according to SPI_CPOL value */\r
- /* Set CPHA bit according to SPI_CPHA value */\r
- tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |\r
- SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | \r
- SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | \r
- SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);\r
- /* Write to SPIx CR1 */\r
- SPIx->CR1 = tmpreg;\r
- \r
- /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */\r
- SPIx->I2SCFGR &= SPI_Mode_Select; \r
-\r
-/*---------------------------- SPIx CRCPOLY Configuration --------------------*/\r
- /* Write to SPIx CRCPOLY */\r
- SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;\r
-}\r
-\r
-/**\r
- * @brief Initializes the SPIx peripheral according to the specified \r
- * parameters in the I2S_InitStruct.\r
- * @param SPIx: where x can be 2 or 3 to select the SPI peripheral\r
- * (configured in I2S mode).\r
- * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that\r
- * contains the configuration information for the specified SPI peripheral\r
- * configured in I2S mode.\r
- * @note\r
- * The function calculates the optimal prescaler needed to obtain the most \r
- * accurate audio frequency (depending on the I2S clock source, the PLL values \r
- * and the product configuration). But in case the prescaler value is greater \r
- * than 511, the default value (0x02) will be configured instead. * \r
- * @retval None\r
- */\r
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)\r
-{\r
- uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;\r
- uint32_t tmp = 0;\r
- RCC_ClocksTypeDef RCC_Clocks;\r
- uint32_t sourceclock = 0;\r
- \r
- /* Check the I2S parameters */\r
- assert_param(IS_SPI_23_PERIPH(SPIx));\r
- assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));\r
- assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));\r
- assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));\r
- assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));\r
- assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));\r
- assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); \r
-\r
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/\r
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */\r
- SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; \r
- SPIx->I2SPR = 0x0002;\r
- \r
- /* Get the I2SCFGR register value */\r
- tmpreg = SPIx->I2SCFGR;\r
- \r
- /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/\r
- if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)\r
- {\r
- i2sodd = (uint16_t)0;\r
- i2sdiv = (uint16_t)2; \r
- }\r
- /* If the requested audio frequency is not the default, compute the prescaler */\r
- else\r
- {\r
- /* Check the frame length (For the Prescaler computing) */\r
- if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)\r
- {\r
- /* Packet length is 16 bits */\r
- packetlength = 1;\r
- }\r
- else\r
- {\r
- /* Packet length is 32 bits */\r
- packetlength = 2;\r
- }\r
-\r
- /* Get the I2S clock source mask depending on the peripheral number */\r
- if(((uint32_t)SPIx) == SPI2_BASE)\r
- {\r
- /* The mask is relative to I2S2 */\r
- tmp = I2S2_CLOCK_SRC;\r
- }\r
- else \r
- {\r
- /* The mask is relative to I2S3 */ \r
- tmp = I2S3_CLOCK_SRC;\r
- }\r
-\r
- /* Check the I2S clock source configuration depending on the Device:\r
- Only Connectivity line devices have the PLL3 VCO clock */\r
-#ifdef STM32F10X_CL\r
- if((RCC->CFGR2 & tmp) != 0)\r
- {\r
- /* Get the configuration bits of RCC PLL3 multiplier */\r
- tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);\r
-\r
- /* Get the value of the PLL3 multiplier */ \r
- if((tmp > 5) && (tmp < 15))\r
- {\r
- /* Multplier is between 8 and 14 (value 15 is forbidden) */\r
- tmp += 2;\r
- }\r
- else\r
- {\r
- if (tmp == 15)\r
- {\r
- /* Multiplier is 20 */\r
- tmp = 20;\r
- }\r
- } \r
- /* Get the PREDIV2 value */\r
- sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);\r
- \r
- /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */\r
- sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); \r
- }\r
- else\r
- {\r
- /* I2S Clock source is System clock: Get System Clock frequency */\r
- RCC_GetClocksFreq(&RCC_Clocks); \r
- \r
- /* Get the source clock value: based on System Clock value */\r
- sourceclock = RCC_Clocks.SYSCLK_Frequency;\r
- } \r
-#else /* STM32F10X_HD */\r
- /* I2S Clock source is System clock: Get System Clock frequency */\r
- RCC_GetClocksFreq(&RCC_Clocks); \r
- \r
- /* Get the source clock value: based on System Clock value */\r
- sourceclock = RCC_Clocks.SYSCLK_Frequency; \r
-#endif /* STM32F10X_CL */ \r
-\r
- /* Compute the Real divider depending on the MCLK output state with a flaoting point */\r
- if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)\r
- {\r
- /* MCLK output is enabled */\r
- tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);\r
- }\r
- else\r
- {\r
- /* MCLK output is disabled */\r
- tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);\r
- }\r
- \r
- /* Remove the flaoting point */\r
- tmp = tmp / 10; \r
- \r
- /* Check the parity of the divider */\r
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);\r
- \r
- /* Compute the i2sdiv prescaler */\r
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2);\r
- \r
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */\r
- i2sodd = (uint16_t) (i2sodd << 8);\r
- }\r
- \r
- /* Test if the divider is 1 or 0 or greater than 0xFF */\r
- if ((i2sdiv < 2) || (i2sdiv > 0xFF))\r
- {\r
- /* Set the default values */\r
- i2sdiv = 2;\r
- i2sodd = 0;\r
- }\r
-\r
- /* Write to SPIx I2SPR register the computed value */\r
- SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); \r
- \r
- /* Configure the I2S with the SPI_InitStruct values */\r
- tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \\r
- (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \\r
- (uint16_t)I2S_InitStruct->I2S_CPOL))));\r
- \r
- /* Write to SPIx I2SCFGR */ \r
- SPIx->I2SCFGR = tmpreg; \r
-}\r
-\r
-/**\r
- * @brief Fills each SPI_InitStruct member with its default value.\r
- * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.\r
- * @retval None\r
- */\r
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)\r
-{\r
-/*--------------- Reset SPI init structure parameters values -----------------*/\r
- /* Initialize the SPI_Direction member */\r
- SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
- /* initialize the SPI_Mode member */\r
- SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;\r
- /* initialize the SPI_DataSize member */\r
- SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;\r
- /* Initialize the SPI_CPOL member */\r
- SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;\r
- /* Initialize the SPI_CPHA member */\r
- SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;\r
- /* Initialize the SPI_NSS member */\r
- SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;\r
- /* Initialize the SPI_BaudRatePrescaler member */\r
- SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
- /* Initialize the SPI_FirstBit member */\r
- SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;\r
- /* Initialize the SPI_CRCPolynomial member */\r
- SPI_InitStruct->SPI_CRCPolynomial = 7;\r
-}\r
-\r
-/**\r
- * @brief Fills each I2S_InitStruct member with its default value.\r
- * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.\r
- * @retval None\r
- */\r
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)\r
-{\r
-/*--------------- Reset I2S init structure parameters values -----------------*/\r
- /* Initialize the I2S_Mode member */\r
- I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;\r
- \r
- /* Initialize the I2S_Standard member */\r
- I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;\r
- \r
- /* Initialize the I2S_DataFormat member */\r
- I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;\r
- \r
- /* Initialize the I2S_MCLKOutput member */\r
- I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;\r
- \r
- /* Initialize the I2S_AudioFreq member */\r
- I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;\r
- \r
- /* Initialize the I2S_CPOL member */\r
- I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified SPI peripheral.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param NewState: new state of the SPIx peripheral. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI peripheral */\r
- SPIx->CR1 |= CR1_SPE_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI peripheral */\r
- SPIx->CR1 &= CR1_SPE_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified SPI peripheral (in I2S mode).\r
- * @param SPIx: where x can be 2 or 3 to select the SPI peripheral.\r
- * @param NewState: new state of the SPIx peripheral. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_23_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI peripheral (in I2S mode) */\r
- SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI peripheral (in I2S mode) */\r
- SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified SPI/I2S interrupts.\r
- * @param SPIx: where x can be\r
- * - 1, 2 or 3 in SPI mode \r
- * - 2 or 3 in I2S mode\r
- * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. \r
- * This parameter can be one of the following values:\r
- * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask\r
- * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask\r
- * @arg SPI_I2S_IT_ERR: Error interrupt mask\r
- * @param NewState: new state of the specified SPI/I2S interrupt.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)\r
-{\r
- uint16_t itpos = 0, itmask = 0 ;\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));\r
-\r
- /* Get the SPI/I2S IT index */\r
- itpos = SPI_I2S_IT >> 4;\r
-\r
- /* Set the IT mask */\r
- itmask = (uint16_t)1 << (uint16_t)itpos;\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI/I2S interrupt */\r
- SPIx->CR2 |= itmask;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI/I2S interrupt */\r
- SPIx->CR2 &= (uint16_t)~itmask;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SPIx/I2Sx DMA interface.\r
- * @param SPIx: where x can be\r
- * - 1, 2 or 3 in SPI mode \r
- * - 2 or 3 in I2S mode\r
- * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. \r
- * This parameter can be any combination of the following values:\r
- * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request\r
- * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request\r
- * @param NewState: new state of the selected SPI/I2S DMA transfer request.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI/I2S DMA requests */\r
- SPIx->CR2 |= SPI_I2S_DMAReq;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI/I2S DMA requests */\r
- SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Transmits a Data through the SPIx/I2Sx peripheral.\r
- * @param SPIx: where x can be\r
- * - 1, 2 or 3 in SPI mode \r
- * - 2 or 3 in I2S mode\r
- * @param Data : Data to be transmitted.\r
- * @retval None\r
- */\r
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- \r
- /* Write in the DR register the data to be sent */\r
- SPIx->DR = Data;\r
-}\r
-\r
-/**\r
- * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. \r
- * @param SPIx: where x can be\r
- * - 1, 2 or 3 in SPI mode \r
- * - 2 or 3 in I2S mode\r
- * @retval The value of the received data.\r
- */\r
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- \r
- /* Return the data in the DR register */\r
- return SPIx->DR;\r
-}\r
-\r
-/**\r
- * @brief Configures internally by software the NSS pin for the selected SPI.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.\r
- * This parameter can be one of the following values:\r
- * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally\r
- * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally\r
- * @retval None\r
- */\r
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));\r
- if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)\r
- {\r
- /* Set NSS pin internally by software */\r
- SPIx->CR1 |= SPI_NSSInternalSoft_Set;\r
- }\r
- else\r
- {\r
- /* Reset NSS pin internally by software */\r
- SPIx->CR1 &= SPI_NSSInternalSoft_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SS output for the selected SPI.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param NewState: new state of the SPIx SS output. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI SS output */\r
- SPIx->CR2 |= CR2_SSOE_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI SS output */\r
- SPIx->CR2 &= CR2_SSOE_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the data size for the selected SPI.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param SPI_DataSize: specifies the SPI data size.\r
- * This parameter can be one of the following values:\r
- * @arg SPI_DataSize_16b: Set data frame format to 16bit\r
- * @arg SPI_DataSize_8b: Set data frame format to 8bit\r
- * @retval None\r
- */\r
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_DATASIZE(SPI_DataSize));\r
- /* Clear DFF bit */\r
- SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;\r
- /* Set new DFF bit value */\r
- SPIx->CR1 |= SPI_DataSize;\r
-}\r
-\r
-/**\r
- * @brief Transmit the SPIx CRC value.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @retval None\r
- */\r
-void SPI_TransmitCRC(SPI_TypeDef* SPIx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- \r
- /* Enable the selected SPI CRC transmission */\r
- SPIx->CR1 |= CR1_CRCNext_Set;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the CRC value calculation of the transfered bytes.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param NewState: new state of the SPIx CRC value calculation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI CRC calculation */\r
- SPIx->CR1 |= CR1_CRCEN_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI CRC calculation */\r
- SPIx->CR1 &= CR1_CRCEN_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Returns the transmit or the receive CRC register value for the specified SPI.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param SPI_CRC: specifies the CRC register to be read.\r
- * This parameter can be one of the following values:\r
- * @arg SPI_CRC_Tx: Selects Tx CRC register\r
- * @arg SPI_CRC_Rx: Selects Rx CRC register\r
- * @retval The selected CRC register value..\r
- */\r
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)\r
-{\r
- uint16_t crcreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_CRC(SPI_CRC));\r
- if (SPI_CRC != SPI_CRC_Rx)\r
- {\r
- /* Get the Tx CRC register */\r
- crcreg = SPIx->TXCRCR;\r
- }\r
- else\r
- {\r
- /* Get the Rx CRC register */\r
- crcreg = SPIx->RXCRCR;\r
- }\r
- /* Return the selected CRC register */\r
- return crcreg;\r
-}\r
-\r
-/**\r
- * @brief Returns the CRC Polynomial register value for the specified SPI.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @retval The CRC Polynomial register value.\r
- */\r
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- \r
- /* Return the CRC polynomial register */\r
- return SPIx->CRCPR;\r
-}\r
-\r
-/**\r
- * @brief Selects the data transfer direction in bi-directional mode for the specified SPI.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param SPI_Direction: specifies the data transfer direction in bi-directional mode. \r
- * This parameter can be one of the following values:\r
- * @arg SPI_Direction_Tx: Selects Tx transmission direction\r
- * @arg SPI_Direction_Rx: Selects Rx receive direction\r
- * @retval None\r
- */\r
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_DIRECTION(SPI_Direction));\r
- if (SPI_Direction == SPI_Direction_Tx)\r
- {\r
- /* Set the Tx only mode */\r
- SPIx->CR1 |= SPI_Direction_Tx;\r
- }\r
- else\r
- {\r
- /* Set the Rx only mode */\r
- SPIx->CR1 &= SPI_Direction_Rx;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified SPI/I2S flag is set or not.\r
- * @param SPIx: where x can be\r
- * - 1, 2 or 3 in SPI mode \r
- * - 2 or 3 in I2S mode\r
- * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. \r
- * This parameter can be one of the following values:\r
- * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.\r
- * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.\r
- * @arg SPI_I2S_FLAG_BSY: Busy flag.\r
- * @arg SPI_I2S_FLAG_OVR: Overrun flag.\r
- * @arg SPI_FLAG_MODF: Mode Fault flag.\r
- * @arg SPI_FLAG_CRCERR: CRC Error flag.\r
- * @arg I2S_FLAG_UDR: Underrun Error flag.\r
- * @arg I2S_FLAG_CHSIDE: Channel Side flag.\r
- * @retval The new state of SPI_I2S_FLAG (SET or RESET).\r
- */\r
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));\r
- /* Check the status of the specified SPI/I2S flag */\r
- if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)\r
- {\r
- /* SPI_I2S_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* SPI_I2S_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the SPI_I2S_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the SPIx CRC Error (CRCERR) flag.\r
- * @param SPIx: where x can be\r
- * - 1, 2 or 3 in SPI mode \r
- * @param SPI_I2S_FLAG: specifies the SPI flag to clear. \r
- * This function clears only CRCERR flag.\r
- * @note\r
- * - OVR (OverRun error) flag is cleared by software sequence: a read \r
- * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read \r
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).\r
- * - UDR (UnderRun error) flag is cleared by a read operation to \r
- * SPI_SR register (SPI_I2S_GetFlagStatus()).\r
- * - MODF (Mode Fault) flag is cleared by software sequence: a read/write \r
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a \r
- * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).\r
- * @retval None\r
- */\r
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));\r
- \r
- /* Clear the selected SPI CRC Error (CRCERR) flag */\r
- SPIx->SR = (uint16_t)~SPI_I2S_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.\r
- * @param SPIx: where x can be\r
- * - 1, 2 or 3 in SPI mode \r
- * - 2 or 3 in I2S mode\r
- * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.\r
- * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.\r
- * @arg SPI_I2S_IT_OVR: Overrun interrupt.\r
- * @arg SPI_IT_MODF: Mode Fault interrupt.\r
- * @arg SPI_IT_CRCERR: CRC Error interrupt.\r
- * @arg I2S_IT_UDR: Underrun Error interrupt.\r
- * @retval The new state of SPI_I2S_IT (SET or RESET).\r
- */\r
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint16_t itpos = 0, itmask = 0, enablestatus = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));\r
-\r
- /* Get the SPI/I2S IT index */\r
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
-\r
- /* Get the SPI/I2S IT mask */\r
- itmask = SPI_I2S_IT >> 4;\r
-\r
- /* Set the IT mask */\r
- itmask = 0x01 << itmask;\r
-\r
- /* Get the SPI_I2S_IT enable bit status */\r
- enablestatus = (SPIx->CR2 & itmask) ;\r
-\r
- /* Check the status of the specified SPI/I2S interrupt */\r
- if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)\r
- {\r
- /* SPI_I2S_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* SPI_I2S_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the SPI_I2S_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.\r
- * @param SPIx: where x can be\r
- * - 1, 2 or 3 in SPI mode \r
- * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.\r
- * This function clears only CRCERR intetrrupt pending bit. \r
- * @note\r
- * - OVR (OverRun Error) interrupt pending bit is cleared by software \r
- * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) \r
- * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).\r
- * - UDR (UnderRun Error) interrupt pending bit is cleared by a read \r
- * operation to SPI_SR register (SPI_I2S_GetITStatus()).\r
- * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:\r
- * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) \r
- * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable \r
- * the SPI).\r
- * @retval None\r
- */\r
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
-{\r
- uint16_t itpos = 0;\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));\r
-\r
- /* Get the SPI IT index */\r
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
-\r
- /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */\r
- SPIx->SR = (uint16_t)~itpos;\r
-}\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_tim.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the TIM firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_tim.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup TIM \r
- * @brief TIM driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup TIM_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Private_Defines\r
- * @{\r
- */\r
-\r
-/* ---------------------- TIM registers bit mask ------------------------ */\r
-#define SMCR_ETR_Mask ((uint16_t)0x00FF) \r
-#define CCMR_Offset ((uint16_t)0x0018)\r
-#define CCER_CCE_Set ((uint16_t)0x0001) \r
-#define CCER_CCNE_Set ((uint16_t)0x0004) \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter);\r
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter);\r
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter);\r
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter);\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the TIMx peripheral registers to their default reset values.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_DeInit(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
- \r
- if (TIMx == TIM1)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); \r
- } \r
- else if (TIMx == TIM2)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);\r
- }\r
- else if (TIMx == TIM3)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);\r
- }\r
- else if (TIMx == TIM4)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);\r
- } \r
- else if (TIMx == TIM5)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);\r
- } \r
- else if (TIMx == TIM6)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);\r
- } \r
- else if (TIMx == TIM7)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);\r
- } \r
- else if (TIMx == TIM8)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);\r
- }\r
- else if (TIMx == TIM9)\r
- { \r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); \r
- } \r
- else if (TIMx == TIM10)\r
- { \r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); \r
- } \r
- else if (TIMx == TIM11) \r
- { \r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); \r
- } \r
- else if (TIMx == TIM12)\r
- { \r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); \r
- } \r
- else if (TIMx == TIM13) \r
- { \r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); \r
- }\r
- else if (TIMx == TIM14) \r
- { \r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); \r
- } \r
- else if (TIMx == TIM15)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);\r
- } \r
- else if (TIMx == TIM16)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);\r
- } \r
- else\r
- {\r
- if (TIMx == TIM17)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);\r
- } \r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIMx Time Base Unit peripheral according to \r
- * the specified parameters in the TIM_TimeBaseInitStruct.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef\r
- * structure that contains the configuration information for the specified TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
-{\r
- uint16_t tmpcr1 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
- assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));\r
- assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));\r
-\r
- tmpcr1 = TIMx->CR1; \r
-\r
- if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||\r
- (TIMx == TIM4) || (TIMx == TIM5)) \r
- {\r
- /* Select the Counter Mode */\r
- tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;\r
- }\r
- \r
- if((TIMx != TIM6) && (TIMx != TIM7))\r
- {\r
- /* Set the clock division */\r
- tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));\r
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;\r
- }\r
-\r
- TIMx->CR1 = tmpcr1;\r
-\r
- /* Set the Autoreload value */\r
- TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;\r
- \r
- /* Set the Prescaler value */\r
- TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;\r
- \r
- if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) \r
- {\r
- /* Set the Repetition Counter value */\r
- TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;\r
- }\r
-\r
- /* Generate an update event to reload the Prescaler and the Repetition counter\r
- values immediately */\r
- TIMx->EGR = TIM_PSCReloadMode_Immediate; \r
-}\r
-\r
-/**\r
- * @brief Initializes the TIMx Channel1 according to the specified\r
- * parameters in the TIM_OCInitStruct.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
- * that contains the configuration information for the specified TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
- /* Disable the Channel 1: Reset the CC1E Bit */\r
- TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);\r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- /* Get the TIMx CR2 register value */\r
- tmpcr2 = TIMx->CR2;\r
- \r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmrx = TIMx->CCMR1;\r
- \r
- /* Reset the Output Compare Mode Bits */\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));\r
-\r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
- \r
- /* Reset the Output Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;\r
- \r
- /* Set the Output State */\r
- tmpccer |= TIM_OCInitStruct->TIM_OutputState;\r
- \r
- if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||\r
- (TIMx == TIM16)|| (TIMx == TIM17))\r
- {\r
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));\r
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));\r
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));\r
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
- \r
- /* Reset the Output N Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));\r
- /* Set the Output N Polarity */\r
- tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;\r
- \r
- /* Reset the Output N State */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); \r
- /* Set the Output N State */\r
- tmpccer |= TIM_OCInitStruct->TIM_OutputNState;\r
- \r
- /* Reset the Ouput Compare and Output Compare N IDLE State */\r
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));\r
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));\r
- \r
- /* Set the Output Idle state */\r
- tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;\r
- /* Set the Output N Idle state */\r
- tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;\r
- }\r
- /* Write to TIMx CR2 */\r
- TIMx->CR2 = tmpcr2;\r
- \r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmrx;\r
-\r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; \r
- \r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIMx Channel2 according to the specified\r
- * parameters in the TIM_OCInitStruct.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select \r
- * the TIM peripheral.\r
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
- * that contains the configuration information for the specified TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx)); \r
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
- /* Disable the Channel 2: Reset the CC2E Bit */\r
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));\r
- \r
- /* Get the TIMx CCER register value */ \r
- tmpccer = TIMx->CCER;\r
- /* Get the TIMx CR2 register value */\r
- tmpcr2 = TIMx->CR2;\r
- \r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmrx = TIMx->CCMR1;\r
- \r
- /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));\r
- \r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
- \r
- /* Reset the Output Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);\r
- \r
- /* Set the Output State */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);\r
- \r
- if((TIMx == TIM1) || (TIMx == TIM8))\r
- {\r
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));\r
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));\r
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));\r
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
- \r
- /* Reset the Output N Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));\r
- /* Set the Output N Polarity */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);\r
- \r
- /* Reset the Output N State */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); \r
- /* Set the Output N State */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);\r
- \r
- /* Reset the Ouput Compare and Output Compare N IDLE State */\r
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));\r
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));\r
- \r
- /* Set the Output Idle state */\r
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);\r
- /* Set the Output N Idle state */\r
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);\r
- }\r
- /* Write to TIMx CR2 */\r
- TIMx->CR2 = tmpcr2;\r
- \r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmrx;\r
-\r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;\r
- \r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIMx Channel3 according to the specified\r
- * parameters in the TIM_OCInitStruct.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
- * that contains the configuration information for the specified TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
- /* Disable the Channel 2: Reset the CC2E Bit */\r
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));\r
- \r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- /* Get the TIMx CR2 register value */\r
- tmpcr2 = TIMx->CR2;\r
- \r
- /* Get the TIMx CCMR2 register value */\r
- tmpccmrx = TIMx->CCMR2;\r
- \r
- /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); \r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
- \r
- /* Reset the Output Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);\r
- \r
- /* Set the Output State */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);\r
- \r
- if((TIMx == TIM1) || (TIMx == TIM8))\r
- {\r
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));\r
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));\r
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));\r
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
- \r
- /* Reset the Output N Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));\r
- /* Set the Output N Polarity */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);\r
- /* Reset the Output N State */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));\r
- \r
- /* Set the Output N State */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);\r
- /* Reset the Ouput Compare and Output Compare N IDLE State */\r
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));\r
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));\r
- /* Set the Output Idle state */\r
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);\r
- /* Set the Output N Idle state */\r
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);\r
- }\r
- /* Write to TIMx CR2 */\r
- TIMx->CR2 = tmpcr2;\r
- \r
- /* Write to TIMx CCMR2 */\r
- TIMx->CCMR2 = tmpccmrx;\r
-\r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;\r
- \r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIMx Channel4 according to the specified\r
- * parameters in the TIM_OCInitStruct.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
- * that contains the configuration information for the specified TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
- /* Disable the Channel 2: Reset the CC4E Bit */\r
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));\r
- \r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- /* Get the TIMx CR2 register value */\r
- tmpcr2 = TIMx->CR2;\r
- \r
- /* Get the TIMx CCMR2 register value */\r
- tmpccmrx = TIMx->CCMR2;\r
- \r
- /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));\r
- \r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
- \r
- /* Reset the Output Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);\r
- \r
- /* Set the Output State */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);\r
- \r
- if((TIMx == TIM1) || (TIMx == TIM8))\r
- {\r
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
- /* Reset the Ouput Compare IDLE State */\r
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));\r
- /* Set the Output Idle state */\r
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);\r
- }\r
- /* Write to TIMx CR2 */\r
- TIMx->CR2 = tmpcr2;\r
- \r
- /* Write to TIMx CCMR2 */ \r
- TIMx->CCMR2 = tmpccmrx;\r
-\r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;\r
- \r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIM peripheral according to the specified\r
- * parameters in the TIM_ICInitStruct.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
- * that contains the configuration information for the specified TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));\r
- assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));\r
- assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));\r
- assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));\r
- \r
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
- {\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- /* TI1 Configuration */\r
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
- TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)\r
- {\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- /* TI2 Configuration */\r
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
- TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)\r
- {\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- /* TI3 Configuration */\r
- TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
- TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
- else\r
- {\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- /* TI4 Configuration */\r
- TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
- TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the TIM peripheral according to the specified\r
- * parameters in the TIM_ICInitStruct to measure an external PWM signal.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
- * that contains the configuration information for the specified TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
-{\r
- uint16_t icoppositepolarity = TIM_ICPolarity_Rising;\r
- uint16_t icoppositeselection = TIM_ICSelection_DirectTI;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- /* Select the Opposite Input Polarity */\r
- if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)\r
- {\r
- icoppositepolarity = TIM_ICPolarity_Falling;\r
- }\r
- else\r
- {\r
- icoppositepolarity = TIM_ICPolarity_Rising;\r
- }\r
- /* Select the Opposite Input */\r
- if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)\r
- {\r
- icoppositeselection = TIM_ICSelection_IndirectTI;\r
- }\r
- else\r
- {\r
- icoppositeselection = TIM_ICSelection_DirectTI;\r
- }\r
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
- {\r
- /* TI1 Configuration */\r
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- /* TI2 Configuration */\r
- TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
- else\r
- { \r
- /* TI2 Configuration */\r
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- /* TI1 Configuration */\r
- TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the: Break feature, dead time, Lock level, the OSSI,\r
- * the OSSR State and the AOE(automatic output enable).\r
- * @param TIMx: where x can be 1 or 8 to select the TIM \r
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that\r
- * contains the BDTR Register configuration information for the TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));\r
- assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));\r
- assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));\r
- assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));\r
- assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));\r
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));\r
- /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,\r
- the OSSI State, the dead time value and the Automatic Output Enable Bit */\r
- TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |\r
- TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |\r
- TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |\r
- TIM_BDTRInitStruct->TIM_AutomaticOutput;\r
-}\r
-\r
-/**\r
- * @brief Fills each TIM_TimeBaseInitStruct member with its default value.\r
- * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef\r
- * structure which will be initialized.\r
- * @retval None\r
- */\r
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
-{\r
- /* Set the default configuration */\r
- TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;\r
- TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;\r
- TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;\r
- TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;\r
- TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;\r
-}\r
-\r
-/**\r
- * @brief Fills each TIM_OCInitStruct member with its default value.\r
- * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will\r
- * be initialized.\r
- * @retval None\r
- */\r
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- /* Set the default configuration */\r
- TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;\r
- TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;\r
- TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;\r
- TIM_OCInitStruct->TIM_Pulse = 0x0000;\r
- TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;\r
- TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;\r
- TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;\r
- TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;\r
-}\r
-\r
-/**\r
- * @brief Fills each TIM_ICInitStruct member with its default value.\r
- * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will\r
- * be initialized.\r
- * @retval None\r
- */\r
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)\r
-{\r
- /* Set the default configuration */\r
- TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;\r
- TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;\r
- TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;\r
- TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;\r
- TIM_ICInitStruct->TIM_ICFilter = 0x00;\r
-}\r
-\r
-/**\r
- * @brief Fills each TIM_BDTRInitStruct member with its default value.\r
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which\r
- * will be initialized.\r
- * @retval None\r
- */\r
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)\r
-{\r
- /* Set the default configuration */\r
- TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;\r
- TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;\r
- TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;\r
- TIM_BDTRInitStruct->TIM_DeadTime = 0x00;\r
- TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;\r
- TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;\r
- TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified TIM peripheral.\r
- * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.\r
- * @param NewState: new state of the TIMx peripheral.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the TIM Counter */\r
- TIMx->CR1 |= TIM_CR1_CEN;\r
- }\r
- else\r
- {\r
- /* Disable the TIM Counter */\r
- TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIM peripheral Main Outputs.\r
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.\r
- * @param NewState: new state of the TIM peripheral Main Outputs.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the TIM Main Output */\r
- TIMx->BDTR |= TIM_BDTR_MOE;\r
- }\r
- else\r
- {\r
- /* Disable the TIM Main Output */\r
- TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));\r
- } \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified TIM interrupts.\r
- * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.\r
- * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg TIM_IT_Update: TIM update Interrupt source\r
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
- * @arg TIM_IT_COM: TIM Commutation Interrupt source\r
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
- * @arg TIM_IT_Break: TIM Break Interrupt source\r
- * @note \r
- * - TIM6 and TIM7 can only generate an update interrupt.\r
- * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,\r
- * TIM_IT_CC2 or TIM_IT_Trigger. \r
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. \r
- * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. \r
- * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
- * @param NewState: new state of the TIM interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_IT(TIM_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the Interrupt sources */\r
- TIMx->DIER |= TIM_IT;\r
- }\r
- else\r
- {\r
- /* Disable the Interrupt sources */\r
- TIMx->DIER &= (uint16_t)~TIM_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx event to be generate by software.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param TIM_EventSource: specifies the event source.\r
- * This parameter can be one or more of the following values: \r
- * @arg TIM_EventSource_Update: Timer update Event source\r
- * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source\r
- * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source\r
- * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source\r
- * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source\r
- * @arg TIM_EventSource_COM: Timer COM event source \r
- * @arg TIM_EventSource_Trigger: Timer Trigger Event source\r
- * @arg TIM_EventSource_Break: Timer Break event source\r
- * @note \r
- * - TIM6 and TIM7 can only generate an update event. \r
- * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. \r
- * @retval None\r
- */\r
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));\r
- \r
- /* Set the event sources */\r
- TIMx->EGR = TIM_EventSource;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx\92s DMA interface.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select \r
- * the TIM peripheral.\r
- * @param TIM_DMABase: DMA Base address.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,\r
- * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,\r
- * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,\r
- * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,\r
- * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,\r
- * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,\r
- * TIM_DMABase_DCR.\r
- * @param TIM_DMABurstLength: DMA Burst length.\r
- * This parameter can be one value between:\r
- * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.\r
- * @retval None\r
- */\r
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
- assert_param(IS_TIM_DMA_BASE(TIM_DMABase));\r
- assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));\r
- /* Set the DMA Base and the DMA Burst Length */\r
- TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx\92s DMA Requests.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 \r
- * to select the TIM peripheral. \r
- * @param TIM_DMASource: specifies the DMA Request sources.\r
- * This parameter can be any combination of the following values:\r
- * @arg TIM_DMA_Update: TIM update Interrupt source\r
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
- * @arg TIM_DMA_COM: TIM Commutation DMA source\r
- * @arg TIM_DMA_Trigger: TIM Trigger DMA source\r
- * @param NewState: new state of the DMA Request sources.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST9_PERIPH(TIMx));\r
- assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the DMA sources */\r
- TIMx->DIER |= TIM_DMASource; \r
- }\r
- else\r
- {\r
- /* Disable the DMA sources */\r
- TIMx->DIER &= (uint16_t)~TIM_DMASource;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx interrnal Clock\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15\r
- * to select the TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- /* Disable slave mode to clock the prescaler directly with the internal clock */\r
- TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Internal Trigger as External Clock\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_ITRSource: Trigger source.\r
- * This parameter can be one of the following values:\r
- * @param TIM_TS_ITR0: Internal Trigger 0\r
- * @param TIM_TS_ITR1: Internal Trigger 1\r
- * @param TIM_TS_ITR2: Internal Trigger 2\r
- * @param TIM_TS_ITR3: Internal Trigger 3\r
- * @retval None\r
- */\r
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
- /* Select the Internal Trigger */\r
- TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);\r
- /* Select the External clock mode1 */\r
- TIMx->SMCR |= TIM_SlaveMode_External1;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Trigger as External Clock\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_TIxExternalCLKSource: Trigger source.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector\r
- * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1\r
- * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2\r
- * @param TIM_ICPolarity: specifies the TIx Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param ICFilter : specifies the filter value.\r
- * This parameter must be a value between 0x0 and 0xF.\r
- * @retval None\r
- */\r
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
- uint16_t TIM_ICPolarity, uint16_t ICFilter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));\r
- assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));\r
- assert_param(IS_TIM_IC_FILTER(ICFilter));\r
- /* Configure the Timer Input Clock Source */\r
- if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)\r
- {\r
- TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
- }\r
- else\r
- {\r
- TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
- }\r
- /* Select the Trigger source */\r
- TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);\r
- /* Select the External clock mode1 */\r
- TIMx->SMCR |= TIM_SlaveMode_External1;\r
-}\r
-\r
-/**\r
- * @brief Configures the External clock Mode1\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
- * @param ExtTRGFilter: External Trigger Filter.\r
- * This parameter must be a value between 0x00 and 0x0F\r
- * @retval None\r
- */\r
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
- uint16_t ExtTRGFilter)\r
-{\r
- uint16_t tmpsmcr = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
- /* Configure the ETR Clock source */\r
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
- \r
- /* Get the TIMx SMCR register value */\r
- tmpsmcr = TIMx->SMCR;\r
- /* Reset the SMS Bits */\r
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
- /* Select the External clock mode1 */\r
- tmpsmcr |= TIM_SlaveMode_External1;\r
- /* Select the Trigger selection : ETRF */\r
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
- tmpsmcr |= TIM_TS_ETRF;\r
- /* Write to TIMx SMCR */\r
- TIMx->SMCR = tmpsmcr;\r
-}\r
-\r
-/**\r
- * @brief Configures the External clock Mode2\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
- * @param ExtTRGFilter: External Trigger Filter.\r
- * This parameter must be a value between 0x00 and 0x0F\r
- * @retval None\r
- */\r
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
- /* Configure the ETR Clock source */\r
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
- /* Enable the External clock mode2 */\r
- TIMx->SMCR |= TIM_SMCR_ECE;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx External Trigger (ETR).\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
- * @param ExtTRGFilter: External Trigger Filter.\r
- * This parameter must be a value between 0x00 and 0x0F\r
- * @retval None\r
- */\r
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
- uint16_t ExtTRGFilter)\r
-{\r
- uint16_t tmpsmcr = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
- tmpsmcr = TIMx->SMCR;\r
- /* Reset the ETR Bits */\r
- tmpsmcr &= SMCR_ETR_Mask;\r
- /* Set the Prescaler, the Filter value and the Polarity */\r
- tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));\r
- /* Write to TIMx SMCR */\r
- TIMx->SMCR = tmpsmcr;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Prescaler.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param Prescaler: specifies the Prescaler Register value\r
- * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode\r
- * This parameter can be one of the following values:\r
- * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.\r
- * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.\r
- * @retval None\r
- */\r
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));\r
- /* Set the Prescaler value */\r
- TIMx->PSC = Prescaler;\r
- /* Set or reset the UG Bit */\r
- TIMx->EGR = TIM_PSCReloadMode;\r
-}\r
-\r
-/**\r
- * @brief Specifies the TIMx Counter Mode to be used.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_CounterMode: specifies the Counter Mode to be used\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CounterMode_Up: TIM Up Counting Mode\r
- * @arg TIM_CounterMode_Down: TIM Down Counting Mode\r
- * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1\r
- * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2\r
- * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3\r
- * @retval None\r
- */\r
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)\r
-{\r
- uint16_t tmpcr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));\r
- tmpcr1 = TIMx->CR1;\r
- /* Reset the CMS and DIR Bits */\r
- tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
- /* Set the Counter Mode */\r
- tmpcr1 |= TIM_CounterMode;\r
- /* Write to TIMx CR1 register */\r
- TIMx->CR1 = tmpcr1;\r
-}\r
-\r
-/**\r
- * @brief Selects the Input Trigger source\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_InputTriggerSource: The Input Trigger source.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_TS_ITR0: Internal Trigger 0\r
- * @arg TIM_TS_ITR1: Internal Trigger 1\r
- * @arg TIM_TS_ITR2: Internal Trigger 2\r
- * @arg TIM_TS_ITR3: Internal Trigger 3\r
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r
- * @arg TIM_TS_ETRF: External Trigger input\r
- * @retval None\r
- */\r
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
-{\r
- uint16_t tmpsmcr = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
- /* Get the TIMx SMCR register value */\r
- tmpsmcr = TIMx->SMCR;\r
- /* Reset the TS Bits */\r
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
- /* Set the Input Trigger source */\r
- tmpsmcr |= TIM_InputTriggerSource;\r
- /* Write to TIMx SMCR */\r
- TIMx->SMCR = tmpsmcr;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Encoder Interface.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.\r
- * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.\r
- * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending\r
- * on the level of the other input.\r
- * @param TIM_IC1Polarity: specifies the IC1 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
- * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
- * @param TIM_IC2Polarity: specifies the IC2 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
- * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
- * @retval None\r
- */\r
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)\r
-{\r
- uint16_t tmpsmcr = 0;\r
- uint16_t tmpccmr1 = 0;\r
- uint16_t tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));\r
- assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));\r
- assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));\r
- assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));\r
-\r
- /* Get the TIMx SMCR register value */\r
- tmpsmcr = TIMx->SMCR;\r
- \r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmr1 = TIMx->CCMR1;\r
- \r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- \r
- /* Set the encoder Mode */\r
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
- tmpsmcr |= TIM_EncoderMode;\r
- \r
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));\r
- tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;\r
- \r
- /* Set the TI1 and the TI2 Polarities */\r
- tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));\r
- tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));\r
- \r
- /* Write to TIMx SMCR */\r
- TIMx->SMCR = tmpsmcr;\r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmr1;\r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Forces the TIMx output 1 waveform to active or inactive level.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ForcedAction_Active: Force active level on OC1REF\r
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.\r
- * @retval None\r
- */\r
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC1M Bits */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);\r
- /* Configure The Forced output Mode */\r
- tmpccmr1 |= TIM_ForcedAction;\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Forces the TIMx output 2 waveform to active or inactive level.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ForcedAction_Active: Force active level on OC2REF\r
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.\r
- * @retval None\r
- */\r
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC2M Bits */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);\r
- /* Configure The Forced output Mode */\r
- tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Forces the TIMx output 3 waveform to active or inactive level.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ForcedAction_Active: Force active level on OC3REF\r
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.\r
- * @retval None\r
- */\r
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC1M Bits */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);\r
- /* Configure The Forced output Mode */\r
- tmpccmr2 |= TIM_ForcedAction;\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Forces the TIMx output 4 waveform to active or inactive level.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ForcedAction_Active: Force active level on OC4REF\r
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.\r
- * @retval None\r
- */\r
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC2M Bits */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);\r
- /* Configure The Forced output Mode */\r
- tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables TIMx peripheral Preload register on ARR.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param NewState: new state of the TIMx peripheral Preload register\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Set the ARR Preload Bit */\r
- TIMx->CR1 |= TIM_CR1_ARPE;\r
- }\r
- else\r
- {\r
- /* Reset the ARR Preload Bit */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the TIM peripheral Commutation event.\r
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral\r
- * @param NewState: new state of the Commutation event.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Set the COM Bit */\r
- TIMx->CR2 |= TIM_CR2_CCUS;\r
- }\r
- else\r
- {\r
- /* Reset the COM Bit */\r
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the TIMx peripheral Capture Compare DMA source.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select \r
- * the TIM peripheral.\r
- * @param NewState: new state of the Capture Compare DMA source\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Set the CCDS Bit */\r
- TIMx->CR2 |= TIM_CR2_CCDS;\r
- }\r
- else\r
- {\r
- /* Reset the CCDS Bit */\r
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15 \r
- * to select the TIMx peripheral\r
- * @param NewState: new state of the Capture Compare Preload Control bit\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Set the CCPC Bit */\r
- TIMx->CR2 |= TIM_CR2_CCPC;\r
- }\r
- else\r
- {\r
- /* Reset the CCPC Bit */\r
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx peripheral Preload register on CCR1.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCPreload_Enable\r
- * @arg TIM_OCPreload_Disable\r
- * @retval None\r
- */\r
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC1PE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);\r
- /* Enable or Disable the Output Compare Preload feature */\r
- tmpccmr1 |= TIM_OCPreload;\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx peripheral Preload register on CCR2.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select \r
- * the TIM peripheral.\r
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCPreload_Enable\r
- * @arg TIM_OCPreload_Disable\r
- * @retval None\r
- */\r
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC2PE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);\r
- /* Enable or Disable the Output Compare Preload feature */\r
- tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx peripheral Preload register on CCR3.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCPreload_Enable\r
- * @arg TIM_OCPreload_Disable\r
- * @retval None\r
- */\r
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC3PE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);\r
- /* Enable or Disable the Output Compare Preload feature */\r
- tmpccmr2 |= TIM_OCPreload;\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx peripheral Preload register on CCR4.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCPreload_Enable\r
- * @arg TIM_OCPreload_Disable\r
- * @retval None\r
- */\r
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC4PE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);\r
- /* Enable or Disable the Output Compare Preload feature */\r
- tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Output Compare 1 Fast feature.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
- * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
- * @retval None\r
- */\r
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC1FE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);\r
- /* Enable or Disable the Output Compare Fast Bit */\r
- tmpccmr1 |= TIM_OCFast;\r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Output Compare 2 Fast feature.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select \r
- * the TIM peripheral.\r
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
- * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
- * @retval None\r
- */\r
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC2FE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);\r
- /* Enable or Disable the Output Compare Fast Bit */\r
- tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);\r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Output Compare 3 Fast feature.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
- * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
- * @retval None\r
- */\r
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
- /* Get the TIMx CCMR2 register value */\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC3FE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);\r
- /* Enable or Disable the Output Compare Fast Bit */\r
- tmpccmr2 |= TIM_OCFast;\r
- /* Write to TIMx CCMR2 */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Output Compare 4 Fast feature.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
- * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
- * @retval None\r
- */\r
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
- /* Get the TIMx CCMR2 register value */\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC4FE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);\r
- /* Enable or Disable the Output Compare Fast Bit */\r
- tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);\r
- /* Write to TIMx CCMR2 */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Clears or safeguards the OCREF1 signal on an external event\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCClear_Enable: TIM Output clear enable\r
- * @arg TIM_OCClear_Disable: TIM Output clear disable\r
- * @retval None\r
- */\r
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
-\r
- tmpccmr1 = TIMx->CCMR1;\r
-\r
- /* Reset the OC1CE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);\r
- /* Enable or Disable the Output Compare Clear Bit */\r
- tmpccmr1 |= TIM_OCClear;\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Clears or safeguards the OCREF2 signal on an external event\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCClear_Enable: TIM Output clear enable\r
- * @arg TIM_OCClear_Disable: TIM Output clear disable\r
- * @retval None\r
- */\r
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC2CE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);\r
- /* Enable or Disable the Output Compare Clear Bit */\r
- tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Clears or safeguards the OCREF3 signal on an external event\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCClear_Enable: TIM Output clear enable\r
- * @arg TIM_OCClear_Disable: TIM Output clear disable\r
- * @retval None\r
- */\r
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC3CE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);\r
- /* Enable or Disable the Output Compare Clear Bit */\r
- tmpccmr2 |= TIM_OCClear;\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Clears or safeguards the OCREF4 signal on an external event\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCClear_Enable: TIM Output clear enable\r
- * @arg TIM_OCClear_Disable: TIM Output clear disable\r
- * @retval None\r
- */\r
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC4CE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);\r
- /* Enable or Disable the Output Compare Clear Bit */\r
- tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx channel 1 polarity.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_OCPolarity: specifies the OC1 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCPolarity_High: Output Compare active high\r
- * @arg TIM_OCPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC1P Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);\r
- tmpccer |= TIM_OCPolarity;\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Channel 1N polarity.\r
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.\r
- * @param TIM_OCNPolarity: specifies the OC1N Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCNPolarity_High: Output Compare active high\r
- * @arg TIM_OCNPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));\r
- \r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC1NP Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);\r
- tmpccer |= TIM_OCNPolarity;\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx channel 2 polarity.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_OCPolarity: specifies the OC2 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCPolarity_High: Output Compare active high\r
- * @arg TIM_OCPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC2P Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);\r
- tmpccer |= (uint16_t)(TIM_OCPolarity << 4);\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Channel 2N polarity.\r
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.\r
- * @param TIM_OCNPolarity: specifies the OC2N Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCNPolarity_High: Output Compare active high\r
- * @arg TIM_OCNPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));\r
- \r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC2NP Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);\r
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx channel 3 polarity.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCPolarity: specifies the OC3 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCPolarity_High: Output Compare active high\r
- * @arg TIM_OCPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC3P Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);\r
- tmpccer |= (uint16_t)(TIM_OCPolarity << 8);\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Channel 3N polarity.\r
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.\r
- * @param TIM_OCNPolarity: specifies the OC3N Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCNPolarity_High: Output Compare active high\r
- * @arg TIM_OCNPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));\r
- \r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC3NP Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);\r
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx channel 4 polarity.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCPolarity: specifies the OC4 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCPolarity_High: Output Compare active high\r
- * @arg TIM_OCPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC4P Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);\r
- tmpccer |= (uint16_t)(TIM_OCPolarity << 12);\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIM Capture Compare Channel x.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_Channel: specifies the TIM Channel\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_Channel_1: TIM Channel 1\r
- * @arg TIM_Channel_2: TIM Channel 2\r
- * @arg TIM_Channel_3: TIM Channel 3\r
- * @arg TIM_Channel_4: TIM Channel 4\r
- * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.\r
- * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. \r
- * @retval None\r
- */\r
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)\r
-{\r
- uint16_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- assert_param(IS_TIM_CHANNEL(TIM_Channel));\r
- assert_param(IS_TIM_CCX(TIM_CCx));\r
-\r
- tmp = CCER_CCE_Set << TIM_Channel;\r
-\r
- /* Reset the CCxE Bit */\r
- TIMx->CCER &= (uint16_t)~ tmp;\r
-\r
- /* Set or reset the CCxE Bit */ \r
- TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIM Capture Compare Channel xN.\r
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.\r
- * @param TIM_Channel: specifies the TIM Channel\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_Channel_1: TIM Channel 1\r
- * @arg TIM_Channel_2: TIM Channel 2\r
- * @arg TIM_Channel_3: TIM Channel 3\r
- * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.\r
- * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. \r
- * @retval None\r
- */\r
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)\r
-{\r
- uint16_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));\r
- assert_param(IS_TIM_CCXN(TIM_CCxN));\r
-\r
- tmp = CCER_CCNE_Set << TIM_Channel;\r
-\r
- /* Reset the CCxNE Bit */\r
- TIMx->CCER &= (uint16_t) ~tmp;\r
-\r
- /* Set or reset the CCxNE Bit */ \r
- TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);\r
-}\r
-\r
-/**\r
- * @brief Selects the TIM Ouput Compare Mode.\r
- * @note This function disables the selected channel before changing the Ouput\r
- * Compare Mode.\r
- * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_Channel: specifies the TIM Channel\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_Channel_1: TIM Channel 1\r
- * @arg TIM_Channel_2: TIM Channel 2\r
- * @arg TIM_Channel_3: TIM Channel 3\r
- * @arg TIM_Channel_4: TIM Channel 4\r
- * @param TIM_OCMode: specifies the TIM Output Compare Mode.\r
- * This paramter can be one of the following values:\r
- * @arg TIM_OCMode_Timing\r
- * @arg TIM_OCMode_Active\r
- * @arg TIM_OCMode_Toggle\r
- * @arg TIM_OCMode_PWM1\r
- * @arg TIM_OCMode_PWM2\r
- * @arg TIM_ForcedAction_Active\r
- * @arg TIM_ForcedAction_InActive\r
- * @retval None\r
- */\r
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)\r
-{\r
- uint32_t tmp = 0;\r
- uint16_t tmp1 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- assert_param(IS_TIM_CHANNEL(TIM_Channel));\r
- assert_param(IS_TIM_OCM(TIM_OCMode));\r
-\r
- tmp = (uint32_t) TIMx;\r
- tmp += CCMR_Offset;\r
-\r
- tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;\r
-\r
- /* Disable the Channel: Reset the CCxE Bit */\r
- TIMx->CCER &= (uint16_t) ~tmp1;\r
-\r
- if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))\r
- {\r
- tmp += (TIM_Channel>>1);\r
-\r
- /* Reset the OCxM bits in the CCMRx register */\r
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);\r
- \r
- /* Configure the OCxM bits in the CCMRx register */\r
- *(__IO uint32_t *) tmp |= TIM_OCMode;\r
- }\r
- else\r
- {\r
- tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;\r
-\r
- /* Reset the OCxM bits in the CCMRx register */\r
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);\r
- \r
- /* Configure the OCxM bits in the CCMRx register */\r
- *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or Disables the TIMx Update event.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param NewState: new state of the TIMx UDIS bit\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Set the Update Disable Bit */\r
- TIMx->CR1 |= TIM_CR1_UDIS;\r
- }\r
- else\r
- {\r
- /* Reset the Update Disable Bit */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Update Request Interrupt source.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param TIM_UpdateSource: specifies the Update source.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow\r
- or the setting of UG bit, or an update generation\r
- through the slave mode controller.\r
- * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.\r
- * @retval None\r
- */\r
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));\r
- if (TIM_UpdateSource != TIM_UpdateSource_Global)\r
- {\r
- /* Set the URS Bit */\r
- TIMx->CR1 |= TIM_CR1_URS;\r
- }\r
- else\r
- {\r
- /* Reset the URS Bit */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx\92s Hall sensor interface.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param NewState: new state of the TIMx Hall sensor interface.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Set the TI1S Bit */\r
- TIMx->CR2 |= TIM_CR2_TI1S;\r
- }\r
- else\r
- {\r
- /* Reset the TI1S Bit */\r
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the TIMx\92s One Pulse Mode.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param TIM_OPMode: specifies the OPM Mode to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OPMode_Single\r
- * @arg TIM_OPMode_Repetitive\r
- * @retval None\r
- */\r
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_OPM_MODE(TIM_OPMode));\r
- /* Reset the OPM Bit */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);\r
- /* Configure the OPM Mode */\r
- TIMx->CR1 |= TIM_OPMode;\r
-}\r
-\r
-/**\r
- * @brief Selects the TIMx Trigger Output Mode.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_TRGOSource: specifies the Trigger Output source.\r
- * This paramter can be one of the following values:\r
- *\r
- * - For all TIMx\r
- * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).\r
- * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).\r
- * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).\r
- *\r
- * - For all TIMx except TIM6 and TIM7\r
- * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag\r
- * is to be set, as soon as a capture or compare match occurs (TRGO).\r
- * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).\r
- * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).\r
- * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).\r
- * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).\r
- *\r
- * @retval None\r
- */\r
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST7_PERIPH(TIMx));\r
- assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));\r
- /* Reset the MMS Bits */\r
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);\r
- /* Select the TRGO source */\r
- TIMx->CR2 |= TIM_TRGOSource;\r
-}\r
-\r
-/**\r
- * @brief Selects the TIMx Slave Mode.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_SlaveMode: specifies the Timer Slave Mode.\r
- * This paramter can be one of the following values:\r
- * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes\r
- * the counter and triggers an update of the registers.\r
- * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.\r
- * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.\r
- * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.\r
- * @retval None\r
- */\r
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));\r
- /* Reset the SMS Bits */\r
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);\r
- /* Select the Slave Mode */\r
- TIMx->SMCR |= TIM_SlaveMode;\r
-}\r
-\r
-/**\r
- * @brief Sets or Resets the TIMx Master/Slave Mode.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.\r
- * This paramter can be one of the following values:\r
- * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer\r
- * and its slaves (through TRGO).\r
- * @arg TIM_MasterSlaveMode_Disable: No action\r
- * @retval None\r
- */\r
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));\r
- /* Reset the MSM Bit */\r
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);\r
- \r
- /* Set or Reset the MSM Bit */\r
- TIMx->SMCR |= TIM_MasterSlaveMode;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Counter Register value\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param Counter: specifies the Counter register new value.\r
- * @retval None\r
- */\r
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- /* Set the Counter Register value */\r
- TIMx->CNT = Counter;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Autoreload Register value\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param Autoreload: specifies the Autoreload register new value.\r
- * @retval None\r
- */\r
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- /* Set the Autoreload Register value */\r
- TIMx->ARR = Autoreload;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Capture Compare1 Register value\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param Compare1: specifies the Capture Compare1 register new value.\r
- * @retval None\r
- */\r
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- /* Set the Capture Compare1 Register value */\r
- TIMx->CCR1 = Compare1;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Capture Compare2 Register value\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param Compare2: specifies the Capture Compare2 register new value.\r
- * @retval None\r
- */\r
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- /* Set the Capture Compare2 Register value */\r
- TIMx->CCR2 = Compare2;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Capture Compare3 Register value\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param Compare3: specifies the Capture Compare3 register new value.\r
- * @retval None\r
- */\r
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- /* Set the Capture Compare3 Register value */\r
- TIMx->CCR3 = Compare3;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Capture Compare4 Register value\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param Compare4: specifies the Capture Compare4 register new value.\r
- * @retval None\r
- */\r
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- /* Set the Capture Compare4 Register value */\r
- TIMx->CCR4 = Compare4;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Input Capture 1 prescaler.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPSC_DIV1: no prescaler\r
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
- * @retval None\r
- */\r
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
- /* Reset the IC1PSC Bits */\r
- TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);\r
- /* Set the IC1PSC value */\r
- TIMx->CCMR1 |= TIM_ICPSC;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Input Capture 2 prescaler.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPSC_DIV1: no prescaler\r
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
- * @retval None\r
- */\r
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
- /* Reset the IC2PSC Bits */\r
- TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);\r
- /* Set the IC2PSC value */\r
- TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Input Capture 3 prescaler.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPSC_DIV1: no prescaler\r
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
- * @retval None\r
- */\r
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
- /* Reset the IC3PSC Bits */\r
- TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);\r
- /* Set the IC3PSC value */\r
- TIMx->CCMR2 |= TIM_ICPSC;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Input Capture 4 prescaler.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPSC_DIV1: no prescaler\r
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
- * @retval None\r
- */\r
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
- /* Reset the IC4PSC Bits */\r
- TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);\r
- /* Set the IC4PSC value */\r
- TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Clock Division value.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select \r
- * the TIM peripheral.\r
- * @param TIM_CKD: specifies the clock division value.\r
- * This parameter can be one of the following value:\r
- * @arg TIM_CKD_DIV1: TDTS = Tck_tim\r
- * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim\r
- * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim\r
- * @retval None\r
- */\r
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- assert_param(IS_TIM_CKD_DIV(TIM_CKD));\r
- /* Reset the CKD Bits */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);\r
- /* Set the CKD value */\r
- TIMx->CR1 |= TIM_CKD;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Input Capture 1 value.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @retval Capture Compare 1 Register value.\r
- */\r
-uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- /* Get the Capture 1 Register value */\r
- return TIMx->CCR1;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Input Capture 2 value.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @retval Capture Compare 2 Register value.\r
- */\r
-uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- /* Get the Capture 2 Register value */\r
- return TIMx->CCR2;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Input Capture 3 value.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @retval Capture Compare 3 Register value.\r
- */\r
-uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
- /* Get the Capture 3 Register value */\r
- return TIMx->CCR3;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Input Capture 4 value.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @retval Capture Compare 4 Register value.\r
- */\r
-uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- /* Get the Capture 4 Register value */\r
- return TIMx->CCR4;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Counter value.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @retval Counter Register value.\r
- */\r
-uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- /* Get the Counter Register value */\r
- return TIMx->CNT;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Prescaler value.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @retval Prescaler Register value.\r
- */\r
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- /* Get the Prescaler Register value */\r
- return TIMx->PSC;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified TIM flag is set or not.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param TIM_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_FLAG_Update: TIM update Flag\r
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
- * @arg TIM_FLAG_COM: TIM Commutation Flag\r
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
- * @arg TIM_FLAG_Break: TIM Break Flag\r
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
- * @note\r
- * - TIM6 and TIM7 can have only one update flag. \r
- * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,\r
- * TIM_FLAG_CC2 or TIM_FLAG_Trigger. \r
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. \r
- * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. \r
- * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
- * @retval The new state of TIM_FLAG (SET or RESET).\r
- */\r
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
-{ \r
- ITStatus bitstatus = RESET; \r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_GET_FLAG(TIM_FLAG));\r
- \r
- if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the TIMx's pending flags.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param TIM_FLAG: specifies the flag bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg TIM_FLAG_Update: TIM update Flag\r
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
- * @arg TIM_FLAG_COM: TIM Commutation Flag\r
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
- * @arg TIM_FLAG_Break: TIM Break Flag\r
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
- * @note\r
- * - TIM6 and TIM7 can have only one update flag. \r
- * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,\r
- * TIM_FLAG_CC2 or TIM_FLAG_Trigger. \r
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. \r
- * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. \r
- * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
- * @retval None\r
- */\r
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));\r
- \r
- /* Clear the flags */\r
- TIMx->SR = (uint16_t)~TIM_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the TIM interrupt has occurred or not.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param TIM_IT: specifies the TIM interrupt source to check.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_IT_Update: TIM update Interrupt source\r
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
- * @arg TIM_IT_COM: TIM Commutation Interrupt source\r
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
- * @arg TIM_IT_Break: TIM Break Interrupt source\r
- * @note\r
- * - TIM6 and TIM7 can generate only an update interrupt.\r
- * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,\r
- * TIM_IT_CC2 or TIM_IT_Trigger. \r
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. \r
- * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. \r
- * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
- * @retval The new state of the TIM_IT(SET or RESET).\r
- */\r
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
-{\r
- ITStatus bitstatus = RESET; \r
- uint16_t itstatus = 0x0, itenable = 0x0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_GET_IT(TIM_IT));\r
- \r
- itstatus = TIMx->SR & TIM_IT;\r
- \r
- itenable = TIMx->DIER & TIM_IT;\r
- if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the TIMx's interrupt pending bits.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param TIM_IT: specifies the pending bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg TIM_IT_Update: TIM1 update Interrupt source\r
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
- * @arg TIM_IT_COM: TIM Commutation Interrupt source\r
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
- * @arg TIM_IT_Break: TIM Break Interrupt source\r
- * @note\r
- * - TIM6 and TIM7 can generate only an update interrupt.\r
- * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,\r
- * TIM_IT_CC2 or TIM_IT_Trigger. \r
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. \r
- * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. \r
- * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
- * @retval None\r
- */\r
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_IT(TIM_IT));\r
- /* Clear the IT pending Bit */\r
- TIMx->SR = (uint16_t)~TIM_IT;\r
-}\r
-\r
-/**\r
- * @brief Configure the TI1 as Input.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param TIM_ICSelection: specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.\r
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.\r
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.\r
- * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- */\r
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter)\r
-{\r
- uint16_t tmpccmr1 = 0, tmpccer = 0;\r
- /* Disable the Channel 1: Reset the CC1E Bit */\r
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);\r
- tmpccmr1 = TIMx->CCMR1;\r
- tmpccer = TIMx->CCER;\r
- /* Select the Input and set the filter */\r
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));\r
- tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
- /* Select the Polarity and set the CC1E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));\r
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);\r
- /* Write to TIMx CCMR1 and CCER registers */\r
- TIMx->CCMR1 = tmpccmr1;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configure the TI2 as Input.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param TIM_ICSelection: specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.\r
- * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.\r
- * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.\r
- * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- */\r
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter)\r
-{\r
- uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;\r
- /* Disable the Channel 2: Reset the CC2E Bit */\r
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);\r
- tmpccmr1 = TIMx->CCMR1;\r
- tmpccer = TIMx->CCER;\r
- tmp = (uint16_t)(TIM_ICPolarity << 4);\r
- /* Select the Input and set the filter */\r
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));\r
- tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);\r
- tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);\r
- /* Select the Polarity and set the CC2E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));\r
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);\r
- /* Write to TIMx CCMR1 and CCER registers */\r
- TIMx->CCMR1 = tmpccmr1 ;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configure the TI3 as Input.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param TIM_ICSelection: specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.\r
- * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.\r
- * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.\r
- * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- */\r
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter)\r
-{\r
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
- /* Disable the Channel 3: Reset the CC3E Bit */\r
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);\r
- tmpccmr2 = TIMx->CCMR2;\r
- tmpccer = TIMx->CCER;\r
- tmp = (uint16_t)(TIM_ICPolarity << 8);\r
- /* Select the Input and set the filter */\r
- tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));\r
- tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
- /* Select the Polarity and set the CC3E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));\r
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);\r
- /* Write to TIMx CCMR2 and CCER registers */\r
- TIMx->CCMR2 = tmpccmr2;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configure the TI1 as Input.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param TIM_ICSelection: specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.\r
- * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.\r
- * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.\r
- * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- */\r
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter)\r
-{\r
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
-\r
- /* Disable the Channel 4: Reset the CC4E Bit */\r
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);\r
- tmpccmr2 = TIMx->CCMR2;\r
- tmpccer = TIMx->CCER;\r
- tmp = (uint16_t)(TIM_ICPolarity << 12);\r
- /* Select the Input and set the filter */\r
- tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));\r
- tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);\r
- tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);\r
-\r
- /* Select the Polarity and set the CC4E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));\r
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);\r
- /* Write to TIMx CCMR2 and CCER registers */\r
- TIMx->CCMR2 = tmpccmr2;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_usart.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the USART firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_usart.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup USART \r
- * @brief USART driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup USART_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Private_Defines\r
- * @{\r
- */\r
-\r
-#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */\r
-#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */\r
-\r
-#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */\r
-\r
-#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */\r
-#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */\r
-#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */\r
-#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */\r
-#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */\r
-\r
-#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */\r
-#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */\r
-\r
-#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */\r
-#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */\r
-#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */\r
-\r
-#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */\r
-#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */\r
-\r
-#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */\r
-#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */\r
-\r
-#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */\r
-#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */\r
-\r
-#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */\r
-#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */\r
-\r
-#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */\r
-#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */\r
-#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */\r
-#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */\r
-#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */\r
-\r
-/* USART OverSampling-8 Mask */\r
-#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */\r
-#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */\r
-\r
-/* USART One Bit Sampling Mask */\r
-#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */\r
-#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the USARTx peripheral registers to their default reset values.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.\r
- * @retval None\r
- */\r
-void USART_DeInit(USART_TypeDef* USARTx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
-\r
- if (USARTx == USART1)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);\r
- }\r
- else if (USARTx == USART2)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);\r
- }\r
- else if (USARTx == USART3)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);\r
- } \r
- else if (USARTx == UART4)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);\r
- } \r
- else\r
- {\r
- if (USARTx == UART5)\r
- { \r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the USARTx peripheral according to the specified\r
- * parameters in the USART_InitStruct .\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure\r
- * that contains the configuration information for the specified USART peripheral.\r
- * @retval None\r
- */\r
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)\r
-{\r
- uint32_t tmpreg = 0x00, apbclock = 0x00;\r
- uint32_t integerdivider = 0x00;\r
- uint32_t fractionaldivider = 0x00;\r
- uint32_t usartxbase = 0;\r
- RCC_ClocksTypeDef RCC_ClocksStatus;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); \r
- assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));\r
- assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));\r
- assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));\r
- assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));\r
- assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));\r
- /* The hardware flow control is available only for USART1, USART2 and USART3 */\r
- if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)\r
- {\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- }\r
-\r
- usartxbase = (uint32_t)USARTx;\r
-\r
-/*---------------------------- USART CR2 Configuration -----------------------*/\r
- tmpreg = USARTx->CR2;\r
- /* Clear STOP[13:12] bits */\r
- tmpreg &= CR2_STOP_CLEAR_Mask;\r
- /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/\r
- /* Set STOP[13:12] bits according to USART_StopBits value */\r
- tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;\r
- \r
- /* Write to USART CR2 */\r
- USARTx->CR2 = (uint16_t)tmpreg;\r
-\r
-/*---------------------------- USART CR1 Configuration -----------------------*/\r
- tmpreg = USARTx->CR1;\r
- /* Clear M, PCE, PS, TE and RE bits */\r
- tmpreg &= CR1_CLEAR_Mask;\r
- /* Configure the USART Word Length, Parity and mode ----------------------- */\r
- /* Set the M bits according to USART_WordLength value */\r
- /* Set PCE and PS bits according to USART_Parity value */\r
- /* Set TE and RE bits according to USART_Mode value */\r
- tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |\r
- USART_InitStruct->USART_Mode;\r
- /* Write to USART CR1 */\r
- USARTx->CR1 = (uint16_t)tmpreg;\r
-\r
-/*---------------------------- USART CR3 Configuration -----------------------*/ \r
- tmpreg = USARTx->CR3;\r
- /* Clear CTSE and RTSE bits */\r
- tmpreg &= CR3_CLEAR_Mask;\r
- /* Configure the USART HFC -------------------------------------------------*/\r
- /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */\r
- tmpreg |= USART_InitStruct->USART_HardwareFlowControl;\r
- /* Write to USART CR3 */\r
- USARTx->CR3 = (uint16_t)tmpreg;\r
-\r
-/*---------------------------- USART BRR Configuration -----------------------*/\r
- /* Configure the USART Baud Rate -------------------------------------------*/\r
- RCC_GetClocksFreq(&RCC_ClocksStatus);\r
- if (usartxbase == USART1_BASE)\r
- {\r
- apbclock = RCC_ClocksStatus.PCLK2_Frequency;\r
- }\r
- else\r
- {\r
- apbclock = RCC_ClocksStatus.PCLK1_Frequency;\r
- }\r
- \r
- /* Determine the integer part */\r
- if ((USARTx->CR1 & CR1_OVER8_Set) != 0)\r
- {\r
- /* Integer part computing in case Oversampling mode is 8 Samples */\r
- integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); \r
- }\r
- else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
- {\r
- /* Integer part computing in case Oversampling mode is 16 Samples */\r
- integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); \r
- }\r
- tmpreg = (integerdivider / 100) << 4;\r
-\r
- /* Determine the fractional part */\r
- fractionaldivider = integerdivider - (100 * (tmpreg >> 4));\r
-\r
- /* Implement the fractional part in the register */\r
- if ((USARTx->CR1 & CR1_OVER8_Set) != 0)\r
- {\r
- tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);\r
- }\r
- else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
- {\r
- tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);\r
- }\r
- \r
- /* Write to USART BRR */\r
- USARTx->BRR = (uint16_t)tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each USART_InitStruct member with its default value.\r
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure\r
- * which will be initialized.\r
- * @retval None\r
- */\r
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct)\r
-{\r
- /* USART_InitStruct members default value */\r
- USART_InitStruct->USART_BaudRate = 9600;\r
- USART_InitStruct->USART_WordLength = USART_WordLength_8b;\r
- USART_InitStruct->USART_StopBits = USART_StopBits_1;\r
- USART_InitStruct->USART_Parity = USART_Parity_No ;\r
- USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;\r
- USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; \r
-}\r
-\r
-/**\r
- * @brief Initializes the USARTx peripheral Clock according to the \r
- * specified parameters in the USART_ClockInitStruct .\r
- * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral.\r
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
- * structure that contains the configuration information for the specified \r
- * USART peripheral. \r
- * @note The Smart Card mode is not available for UART4 and UART5.\r
- * @retval None\r
- */\r
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)\r
-{\r
- uint32_t tmpreg = 0x00;\r
- /* Check the parameters */\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));\r
- assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));\r
- assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));\r
- assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));\r
- \r
-/*---------------------------- USART CR2 Configuration -----------------------*/\r
- tmpreg = USARTx->CR2;\r
- /* Clear CLKEN, CPOL, CPHA and LBCL bits */\r
- tmpreg &= CR2_CLOCK_CLEAR_Mask;\r
- /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/\r
- /* Set CLKEN bit according to USART_Clock value */\r
- /* Set CPOL bit according to USART_CPOL value */\r
- /* Set CPHA bit according to USART_CPHA value */\r
- /* Set LBCL bit according to USART_LastBit value */\r
- tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | \r
- USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;\r
- /* Write to USART CR2 */\r
- USARTx->CR2 = (uint16_t)tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each USART_ClockInitStruct member with its default value.\r
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
- * structure which will be initialized.\r
- * @retval None\r
- */\r
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)\r
-{\r
- /* USART_ClockInitStruct members default value */\r
- USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;\r
- USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;\r
- USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;\r
- USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified USART peripheral.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the USARTx peripheral.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected USART by setting the UE bit in the CR1 register */\r
- USARTx->CR1 |= CR1_UE_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected USART by clearing the UE bit in the CR1 register */\r
- USARTx->CR1 &= CR1_UE_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified USART interrupts.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.\r
- * This parameter can be one of the following values:\r
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
- * @arg USART_IT_LBD: LIN Break detection interrupt\r
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt\r
- * @arg USART_IT_TC: Transmission complete interrupt\r
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
- * @arg USART_IT_IDLE: Idle line detection interrupt\r
- * @arg USART_IT_PE: Parity Error interrupt\r
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
- * @param NewState: new state of the specified USARTx interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)\r
-{\r
- uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;\r
- uint32_t usartxbase = 0x00;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_CONFIG_IT(USART_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- /* The CTS interrupt is not available for UART4 and UART5 */\r
- if (USART_IT == USART_IT_CTS)\r
- {\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- } \r
- \r
- usartxbase = (uint32_t)USARTx;\r
-\r
- /* Get the USART register index */\r
- usartreg = (((uint8_t)USART_IT) >> 0x05);\r
-\r
- /* Get the interrupt position */\r
- itpos = USART_IT & IT_Mask;\r
- itmask = (((uint32_t)0x01) << itpos);\r
- \r
- if (usartreg == 0x01) /* The IT is in CR1 register */\r
- {\r
- usartxbase += 0x0C;\r
- }\r
- else if (usartreg == 0x02) /* The IT is in CR2 register */\r
- {\r
- usartxbase += 0x10;\r
- }\r
- else /* The IT is in CR3 register */\r
- {\r
- usartxbase += 0x14; \r
- }\r
- if (NewState != DISABLE)\r
- {\r
- *(__IO uint32_t*)usartxbase |= itmask;\r
- }\r
- else\r
- {\r
- *(__IO uint32_t*)usartxbase &= ~itmask;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART\92s DMA interface.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3 or UART4. \r
- * @param USART_DMAReq: specifies the DMA request.\r
- * This parameter can be any combination of the following values:\r
- * @arg USART_DMAReq_Tx: USART DMA transmit request\r
- * @arg USART_DMAReq_Rx: USART DMA receive request\r
- * @param NewState: new state of the DMA Request sources.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note The DMA mode is not available for UART5. \r
- * @retval None\r
- */\r
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_1234_PERIPH(USARTx));\r
- assert_param(IS_USART_DMAREQ(USART_DMAReq)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the DMA transfer for selected requests by setting the DMAT and/or\r
- DMAR bits in the USART CR3 register */\r
- USARTx->CR3 |= USART_DMAReq;\r
- }\r
- else\r
- {\r
- /* Disable the DMA transfer for selected requests by clearing the DMAT and/or\r
- DMAR bits in the USART CR3 register */\r
- USARTx->CR3 &= (uint16_t)~USART_DMAReq;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Sets the address of the USART node.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_Address: Indicates the address of the USART node.\r
- * @retval None\r
- */\r
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_ADDRESS(USART_Address)); \r
- \r
- /* Clear the USART address */\r
- USARTx->CR2 &= CR2_Address_Mask;\r
- /* Set the USART address node */\r
- USARTx->CR2 |= USART_Address;\r
-}\r
-\r
-/**\r
- * @brief Selects the USART WakeUp method.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_WakeUp: specifies the USART wakeup method.\r
- * This parameter can be one of the following values:\r
- * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection\r
- * @arg USART_WakeUp_AddressMark: WakeUp by an address mark\r
- * @retval None\r
- */\r
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_WAKEUP(USART_WakeUp));\r
- \r
- USARTx->CR1 &= CR1_WAKE_Mask;\r
- USARTx->CR1 |= USART_WakeUp;\r
-}\r
-\r
-/**\r
- * @brief Determines if the USART is in mute mode or not.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the USART mute mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the USART mute mode by setting the RWU bit in the CR1 register */\r
- USARTx->CR1 |= CR1_RWU_Set;\r
- }\r
- else\r
- {\r
- /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */\r
- USARTx->CR1 &= CR1_RWU_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Sets the USART LIN Break detection length.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_LINBreakDetectLength: specifies the LIN break detection length.\r
- * This parameter can be one of the following values:\r
- * @arg USART_LINBreakDetectLength_10b: 10-bit break detection\r
- * @arg USART_LINBreakDetectLength_11b: 11-bit break detection\r
- * @retval None\r
- */\r
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));\r
- \r
- USARTx->CR2 &= CR2_LBDL_Mask;\r
- USARTx->CR2 |= USART_LINBreakDetectLength; \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART\92s LIN mode.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the USART LIN mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r
- USARTx->CR2 |= CR2_LINEN_Set;\r
- }\r
- else\r
- {\r
- /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */\r
- USARTx->CR2 &= CR2_LINEN_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Transmits single data through the USARTx peripheral.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param Data: the data to transmit.\r
- * @retval None\r
- */\r
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_DATA(Data)); \r
- \r
- /* Transmit Data */\r
- USARTx->DR = (Data & (uint16_t)0x01FF);\r
-}\r
-\r
-/**\r
- * @brief Returns the most recent received data by the USARTx peripheral.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @retval The received data.\r
- */\r
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- \r
- /* Receive Data */\r
- return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);\r
-}\r
-\r
-/**\r
- * @brief Transmits break characters.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @retval None\r
- */\r
-void USART_SendBreak(USART_TypeDef* USARTx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- \r
- /* Send break characters */\r
- USARTx->CR1 |= CR1_SBK_Set;\r
-}\r
-\r
-/**\r
- * @brief Sets the specified USART guard time.\r
- * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.\r
- * @param USART_GuardTime: specifies the guard time.\r
- * @note The guard time bits are not available for UART4 and UART5. \r
- * @retval None\r
- */\r
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- \r
- /* Clear the USART Guard time */\r
- USARTx->GTPR &= GTPR_LSB_Mask;\r
- /* Set the USART guard time */\r
- USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);\r
-}\r
-\r
-/**\r
- * @brief Sets the system clock prescaler.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_Prescaler: specifies the prescaler clock. \r
- * @note The function is used for IrDA mode with UART4 and UART5.\r
- * @retval None\r
- */\r
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- \r
- /* Clear the USART prescaler */\r
- USARTx->GTPR &= GTPR_MSB_Mask;\r
- /* Set the USART prescaler */\r
- USARTx->GTPR |= USART_Prescaler;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART\92s Smart Card mode.\r
- * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.\r
- * @param NewState: new state of the Smart Card mode.\r
- * This parameter can be: ENABLE or DISABLE. \r
- * @note The Smart Card mode is not available for UART4 and UART5. \r
- * @retval None\r
- */\r
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the SC mode by setting the SCEN bit in the CR3 register */\r
- USARTx->CR3 |= CR3_SCEN_Set;\r
- }\r
- else\r
- {\r
- /* Disable the SC mode by clearing the SCEN bit in the CR3 register */\r
- USARTx->CR3 &= CR3_SCEN_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables NACK transmission.\r
- * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. \r
- * @param NewState: new state of the NACK transmission.\r
- * This parameter can be: ENABLE or DISABLE. \r
- * @note The Smart Card mode is not available for UART4 and UART5.\r
- * @retval None\r
- */\r
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_123_PERIPH(USARTx)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the NACK transmission by setting the NACK bit in the CR3 register */\r
- USARTx->CR3 |= CR3_NACK_Set;\r
- }\r
- else\r
- {\r
- /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */\r
- USARTx->CR3 &= CR3_NACK_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART\92s Half Duplex communication.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the USART Communication.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
- USARTx->CR3 |= CR3_HDSEL_Set;\r
- }\r
- else\r
- {\r
- /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */\r
- USARTx->CR3 &= CR3_HDSEL_Reset;\r
- }\r
-}\r
-\r
-\r
-/**\r
- * @brief Enables or disables the USART's 8x oversampling mode.\r
- * @param USARTx: Select the USART or the UART peripheral.\r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the USART one bit sampling methode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note\r
- * This function has to be called before calling USART_Init()\r
- * function in order to have correct baudrate Divider value. \r
- * @retval None\r
- */\r
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */\r
- USARTx->CR1 |= CR1_OVER8_Set;\r
- }\r
- else\r
- {\r
- /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */\r
- USARTx->CR1 &= CR1_OVER8_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART's one bit sampling methode.\r
- * @param USARTx: Select the USART or the UART peripheral.\r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the USART one bit sampling methode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */\r
- USARTx->CR3 |= CR3_ONEBITE_Set;\r
- }\r
- else\r
- {\r
- /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */\r
- USARTx->CR3 &= CR3_ONEBITE_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the USART\92s IrDA interface.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_IrDAMode: specifies the IrDA mode.\r
- * This parameter can be one of the following values:\r
- * @arg USART_IrDAMode_LowPower\r
- * @arg USART_IrDAMode_Normal\r
- * @retval None\r
- */\r
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));\r
- \r
- USARTx->CR3 &= CR3_IRLP_Mask;\r
- USARTx->CR3 |= USART_IrDAMode;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART\92s IrDA interface.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the IrDA mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the IrDA mode by setting the IREN bit in the CR3 register */\r
- USARTx->CR3 |= CR3_IREN_Set;\r
- }\r
- else\r
- {\r
- /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */\r
- USARTx->CR3 &= CR3_IREN_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified USART flag is set or not.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)\r
- * @arg USART_FLAG_LBD: LIN Break detection flag\r
- * @arg USART_FLAG_TXE: Transmit data register empty flag\r
- * @arg USART_FLAG_TC: Transmission Complete flag\r
- * @arg USART_FLAG_RXNE: Receive data register not empty flag\r
- * @arg USART_FLAG_IDLE: Idle Line detection flag\r
- * @arg USART_FLAG_ORE: OverRun Error flag\r
- * @arg USART_FLAG_NE: Noise Error flag\r
- * @arg USART_FLAG_FE: Framing Error flag\r
- * @arg USART_FLAG_PE: Parity Error flag\r
- * @retval The new state of USART_FLAG (SET or RESET).\r
- */\r
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_FLAG(USART_FLAG));\r
- /* The CTS flag is not available for UART4 and UART5 */\r
- if (USART_FLAG == USART_FLAG_CTS)\r
- {\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- } \r
- \r
- if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the USARTx's pending flags.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_FLAG: specifies the flag to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).\r
- * @arg USART_FLAG_LBD: LIN Break detection flag.\r
- * @arg USART_FLAG_TC: Transmission Complete flag.\r
- * @arg USART_FLAG_RXNE: Receive data register not empty flag.\r
- * \r
- * @note\r
- * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
- * error) and IDLE (Idle line detected) flags are cleared by software \r
- * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) \r
- * followed by a read operation to USART_DR register (USART_ReceiveData()).\r
- * - RXNE flag can be also cleared by a read to the USART_DR register \r
- * (USART_ReceiveData()).\r
- * - TC flag can be also cleared by software sequence: a read operation to \r
- * USART_SR register (USART_GetFlagStatus()) followed by a write operation\r
- * to USART_DR register (USART_SendData()).\r
- * - TXE flag is cleared only by a write to the USART_DR register \r
- * (USART_SendData()).\r
- * @retval None\r
- */\r
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));\r
- /* The CTS flag is not available for UART4 and UART5 */\r
- if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)\r
- {\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- } \r
- \r
- USARTx->SR = (uint16_t)~USART_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified USART interrupt has occurred or not.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_IT: specifies the USART interrupt source to check.\r
- * This parameter can be one of the following values:\r
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
- * @arg USART_IT_LBD: LIN Break detection interrupt\r
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt\r
- * @arg USART_IT_TC: Transmission complete interrupt\r
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
- * @arg USART_IT_IDLE: Idle line detection interrupt\r
- * @arg USART_IT_ORE: OverRun Error interrupt\r
- * @arg USART_IT_NE: Noise Error interrupt\r
- * @arg USART_IT_FE: Framing Error interrupt\r
- * @arg USART_IT_PE: Parity Error interrupt\r
- * @retval The new state of USART_IT (SET or RESET).\r
- */\r
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)\r
-{\r
- uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;\r
- ITStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_GET_IT(USART_IT));\r
- /* The CTS interrupt is not available for UART4 and UART5 */ \r
- if (USART_IT == USART_IT_CTS)\r
- {\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- } \r
- \r
- /* Get the USART register index */\r
- usartreg = (((uint8_t)USART_IT) >> 0x05);\r
- /* Get the interrupt position */\r
- itmask = USART_IT & IT_Mask;\r
- itmask = (uint32_t)0x01 << itmask;\r
- \r
- if (usartreg == 0x01) /* The IT is in CR1 register */\r
- {\r
- itmask &= USARTx->CR1;\r
- }\r
- else if (usartreg == 0x02) /* The IT is in CR2 register */\r
- {\r
- itmask &= USARTx->CR2;\r
- }\r
- else /* The IT is in CR3 register */\r
- {\r
- itmask &= USARTx->CR3;\r
- }\r
- \r
- bitpos = USART_IT >> 0x08;\r
- bitpos = (uint32_t)0x01 << bitpos;\r
- bitpos &= USARTx->SR;\r
- if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- \r
- return bitstatus; \r
-}\r
-\r
-/**\r
- * @brief Clears the USARTx\92s interrupt pending bits.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_IT: specifies the interrupt pending bit to clear.\r
- * This parameter can be one of the following values:\r
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
- * @arg USART_IT_LBD: LIN Break detection interrupt\r
- * @arg USART_IT_TC: Transmission complete interrupt. \r
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt.\r
- * \r
- * @note\r
- * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
- * error) and IDLE (Idle line detected) pending bits are cleared by \r
- * software sequence: a read operation to USART_SR register \r
- * (USART_GetITStatus()) followed by a read operation to USART_DR register \r
- * (USART_ReceiveData()).\r
- * - RXNE pending bit can be also cleared by a read to the USART_DR register \r
- * (USART_ReceiveData()).\r
- * - TC pending bit can be also cleared by software sequence: a read \r
- * operation to USART_SR register (USART_GetITStatus()) followed by a write \r
- * operation to USART_DR register (USART_SendData()).\r
- * - TXE pending bit is cleared only by a write to the USART_DR register \r
- * (USART_SendData()).\r
- * @retval None\r
- */\r
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)\r
-{\r
- uint16_t bitpos = 0x00, itmask = 0x00;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_CLEAR_IT(USART_IT));\r
- /* The CTS interrupt is not available for UART4 and UART5 */\r
- if (USART_IT == USART_IT_CTS)\r
- {\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- } \r
- \r
- bitpos = USART_IT >> 0x08;\r
- itmask = ((uint16_t)0x01 << (uint16_t)bitpos);\r
- USARTx->SR = (uint16_t)~itmask;\r
-}\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_wwdg.c\r
- * @author MCD Application Team\r
- * @version V3.3.0\r
- * @date 04/16/2010\r
- * @brief This file provides all the WWDG firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_wwdg.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup WWDG \r
- * @brief WWDG driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup WWDG_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup WWDG_Private_Defines\r
- * @{\r
- */\r
-\r
-/* ----------- WWDG registers bit address in the alias region ----------- */\r
-#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)\r
-\r
-/* Alias word address of EWI bit */\r
-#define CFR_OFFSET (WWDG_OFFSET + 0x04)\r
-#define EWI_BitNumber 0x09\r
-#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))\r
-\r
-/* --------------------- WWDG registers bit mask ------------------------ */\r
-\r
-/* CR register bit mask */\r
-#define CR_WDGA_Set ((uint32_t)0x00000080)\r
-\r
-/* CFR register bit mask */\r
-#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)\r
-#define CFR_W_Mask ((uint32_t)0xFFFFFF80)\r
-#define BIT_Mask ((uint8_t)0x7F)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup WWDG_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup WWDG_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup WWDG_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup WWDG_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the WWDG peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void WWDG_DeInit(void)\r
-{\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Sets the WWDG Prescaler.\r
- * @param WWDG_Prescaler: specifies the WWDG Prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1\r
- * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2\r
- * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4\r
- * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8\r
- * @retval None\r
- */\r
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));\r
- /* Clear WDGTB[1:0] bits */\r
- tmpreg = WWDG->CFR & CFR_WDGTB_Mask;\r
- /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */\r
- tmpreg |= WWDG_Prescaler;\r
- /* Store the new value */\r
- WWDG->CFR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Sets the WWDG window value.\r
- * @param WindowValue: specifies the window value to be compared to the downcounter.\r
- * This parameter value must be lower than 0x80.\r
- * @retval None\r
- */\r
-void WWDG_SetWindowValue(uint8_t WindowValue)\r
-{\r
- __IO uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));\r
- /* Clear W[6:0] bits */\r
-\r
- tmpreg = WWDG->CFR & CFR_W_Mask;\r
-\r
- /* Set W[6:0] bits according to WindowValue value */\r
- tmpreg |= WindowValue & (uint32_t) BIT_Mask;\r
-\r
- /* Store the new value */\r
- WWDG->CFR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables the WWDG Early Wakeup interrupt(EWI).\r
- * @param None\r
- * @retval None\r
- */\r
-void WWDG_EnableIT(void)\r
-{\r
- *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;\r
-}\r
-\r
-/**\r
- * @brief Sets the WWDG counter value.\r
- * @param Counter: specifies the watchdog counter value.\r
- * This parameter must be a number between 0x40 and 0x7F.\r
- * @retval None\r
- */\r
-void WWDG_SetCounter(uint8_t Counter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_WWDG_COUNTER(Counter));\r
- /* Write to T[6:0] bits to configure the counter value, no need to do\r
- a read-modify-write; writing a 0 to WDGA bit does nothing */\r
- WWDG->CR = Counter & BIT_Mask;\r
-}\r
-\r
-/**\r
- * @brief Enables WWDG and load the counter value. \r
- * @param Counter: specifies the watchdog counter value.\r
- * This parameter must be a number between 0x40 and 0x7F.\r
- * @retval None\r
- */\r
-void WWDG_Enable(uint8_t Counter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_WWDG_COUNTER(Counter));\r
- WWDG->CR = CR_WDGA_Set | Counter;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the Early Wakeup interrupt flag is set or not.\r
- * @param None\r
- * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)\r
- */\r
-FlagStatus WWDG_GetFlagStatus(void)\r
-{\r
- return (FlagStatus)(WWDG->SR);\r
-}\r
-\r
-/**\r
- * @brief Clears Early Wakeup interrupt flag.\r
- * @param None\r
- * @retval None\r
- */\r
-void WWDG_ClearFlag(void)\r
-{\r
- WWDG->SR = (uint32_t)RESET;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file misc.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides all the miscellaneous firmware functions (add-on\r
- * to CMSIS functions).\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "misc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup MISC \r
- * @brief MISC driver modules\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup MISC_Private_Functions\r
- * @{\r
- */\r
-/**\r
- *\r
-@verbatim \r
- *******************************************************************************\r
- Interrupts configuration functions\r
- ******************************************************************************* \r
- \r
- This section provide functions allowing to configure the NVIC interrupts (IRQ).\r
- The Cortex-M3 exceptions are managed by CMSIS functions.\r
- \r
- 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() function\r
- according to the following table.\r
- \r
- The table below gives the allowed values of the pre-emption priority and subpriority according\r
- to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function\r
- ============================================================================================================================\r
- NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description\r
- ============================================================================================================================\r
- NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority\r
- | | | 4 bits for subpriority\r
- ----------------------------------------------------------------------------------------------------------------------------\r
- NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority\r
- | | | 3 bits for subpriority\r
- ---------------------------------------------------------------------------------------------------------------------------- \r
- NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority\r
- | | | 2 bits for subpriority\r
- ---------------------------------------------------------------------------------------------------------------------------- \r
- NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority\r
- | | | 1 bits for subpriority\r
- ---------------------------------------------------------------------------------------------------------------------------- \r
- NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority\r
- | | | 0 bits for subpriority \r
- ============================================================================================================================ \r
-\r
-\r
- 2. Enable and Configure the priority of the selected IRQ Channels. \r
-\r
-@note When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,\r
- the IRQ priority will be managed only by subpriority.\r
- The sub-priority is only used to sort pending exception priorities, \r
- and does not affect active exceptions.\r
-\r
-@note Lower priority values gives higher priority.\r
-\r
-@note Priority Order:\r
- 1. Lowest Preemption priority\r
- 2. Lowest Subpriority\r
- 3. Lowest hardware priority (IRQn position)\r
- \r
-@endverbatim\r
-*/\r
-\r
-/**\r
- * @brief Configures the priority grouping: pre-emption priority and subpriority.\r
- * @param NVIC_PriorityGroup: specifies the priority grouping bits length. \r
- * This parameter can be one of the following values:\r
- * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority\r
- * 4 bits for subpriority\r
- * @note When NVIC_PriorityGroup_0 is selected, it will no be any nested \r
- * interrupt. This interrupts priority is managed only with subpriority. \r
- * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority\r
- * 3 bits for subpriority\r
- * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority\r
- * 2 bits for subpriority\r
- * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority\r
- * 1 bits for subpriority\r
- * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority\r
- * 0 bits for subpriority\r
- * @retval None\r
- */\r
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));\r
- \r
- /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */\r
- SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;\r
-}\r
-\r
-/**\r
- * @brief Initializes the NVIC peripheral according to the specified\r
- * parameters in the NVIC_InitStruct.\r
- * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()\r
- * function should be called before. \r
- * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains\r
- * the configuration information for the specified NVIC peripheral.\r
- * @retval None\r
- */\r
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)\r
-{\r
- uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));\r
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); \r
- assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));\r
- \r
- if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)\r
- {\r
- /* Compute the Corresponding IRQ Priority --------------------------------*/ \r
- tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;\r
- tmppre = (0x4 - tmppriority);\r
- tmpsub = tmpsub >> tmppriority;\r
-\r
- tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;\r
- tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;\r
- tmppriority = tmppriority << 0x04;\r
- \r
- NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;\r
- \r
- /* Enable the Selected IRQ Channels --------------------------------------*/\r
- NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
- }\r
- else\r
- {\r
- /* Disable the Selected IRQ Channels -------------------------------------*/\r
- NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Sets the vector table location and Offset.\r
- * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.\r
- * This parameter can be one of the following values:\r
- * @arg NVIC_VectTab_RAM\r
- * @arg NVIC_VectTab_FLASH\r
- * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.\r
- * @retval None\r
- */\r
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));\r
- assert_param(IS_NVIC_OFFSET(Offset)); \r
- \r
- SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);\r
-}\r
-\r
-/**\r
- * @brief Selects the condition for the system to enter low power mode.\r
- * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.\r
- * This parameter can be one of the following values:\r
- * @arg NVIC_LP_SEVONPEND\r
- * @arg NVIC_LP_SLEEPDEEP\r
- * @arg NVIC_LP_SLEEPONEXIT\r
- * @param NewState: new state of LP condition. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_NVIC_LP(LowPowerMode));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
- \r
- if (NewState != DISABLE)\r
- {\r
- SCB->SCR |= LowPowerMode;\r
- }\r
- else\r
- {\r
- SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the SysTick clock source.\r
- * @param SysTick_CLKSource: specifies the SysTick clock source.\r
- * This parameter can be one of the following values:\r
- * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.\r
- * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.\r
- * @retval None\r
- */\r
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));\r
- \r
- if (SysTick_CLKSource == SysTick_CLKSource_HCLK)\r
- {\r
- SysTick->CTRL |= SysTick_CLKSource_HCLK;\r
- }\r
- else\r
- {\r
- SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_adc.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Analog to Digital Convertor (ADC) peripheral: \r
- * - Initialization and Configuration\r
- * - Power saving\r
- * - Analog Watchdog configuration \r
- * - Temperature Sensor & Vrefint (Voltage Reference internal) management \r
- * - Regular Channels Configuration\r
- * - Regular Channels DMA Configuration\r
- * - Injected channels Configuration \r
- * - Interrupts and flags management \r
- * \r
- * @verbatim\r
- * \r
- * =================================================================== \r
- * How to use this driver\r
- * =================================================================== \r
- * - Configure the ADC Prescaler, conversion resolution and data \r
- * alignment using the ADC_Init() function.\r
- * - Activate the ADC peripheral using ADC_Cmd() function. \r
- *\r
- * Regular channels group configuration\r
- * ==================================== \r
- * - To configure the ADC regular channels group features, use \r
- * ADC_Init() and ADC_RegularChannelConfig() functions.\r
- * - To activate the continuous mode, use the ADC_continuousModeCmd()\r
- * function.\r
- * - To configurate and activate the Discontinuous mode, use the \r
- * ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. \r
- * - To read the ADC converted values, use the ADC_GetConversionValue()\r
- * function.\r
- *\r
- * DMA for Regular channels group features configuration\r
- * ====================================================== \r
- * - To enable the DMA mode for regular channels group, use the \r
- * ADC_DMACmd() function.\r
- * - To enable the generation of DMA requests continuously at the end\r
- * of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() \r
- * function. \r
- \r
- * Injected channels group configuration\r
- * ===================================== \r
- * - To configure the ADC Injected channels group features, use \r
- * ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()\r
- * functions.\r
- * - To activate the continuous mode, use the ADC_continuousModeCmd()\r
- * function.\r
- * - To activate the Injected Discontinuous mode, use the \r
- * ADC_InjectedDiscModeCmd() function. \r
- * - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() \r
- * function. \r
- * - To read the ADC converted values, use the ADC_GetInjectedConversionValue() \r
- * function.\r
- * \r
- * @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_adc.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup ADC \r
- * @brief ADC driver modules\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* ADC DISCNUM mask */\r
-#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)\r
- \r
-/* ADC AWDCH mask */\r
-#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) \r
- \r
-/* ADC Analog watchdog enable mode mask */\r
-#define CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF)\r
- \r
-/* CR1 register Mask */\r
-#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) \r
- \r
-/* ADC DELAY mask */ \r
-#define CR2_DELS_RESET ((uint32_t)0xFFFFFF0F)\r
- \r
-/* ADC JEXTEN mask */\r
-#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)\r
- \r
-/* ADC JEXTSEL mask */\r
-#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)\r
- \r
-/* CR2 register Mask */\r
-#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)\r
-\r
-/* ADC SQx mask */\r
-#define SQR5_SQ_SET ((uint32_t)0x0000001F) \r
-#define SQR4_SQ_SET ((uint32_t)0x0000001F) \r
-#define SQR3_SQ_SET ((uint32_t)0x0000001F) \r
-#define SQR2_SQ_SET ((uint32_t)0x0000001F) \r
-#define SQR1_SQ_SET ((uint32_t)0x0000001F)\r
-\r
-/* ADC L Mask */\r
-#define SQR1_L_RESET ((uint32_t)0xFE0FFFFF) \r
-\r
-/* ADC JSQx mask */\r
-#define JSQR_JSQ_SET ((uint32_t)0x0000001F) \r
- \r
-/* ADC JL mask */\r
-#define JSQR_JL_SET ((uint32_t)0x00300000) \r
-#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) \r
-\r
-/* ADC SMPx mask */\r
-#define SMPR1_SMP_SET ((uint32_t)0x00000007) \r
-#define SMPR2_SMP_SET ((uint32_t)0x00000007)\r
-#define SMPR3_SMP_SET ((uint32_t)0x00000007) \r
-\r
-/* ADC JDRx registers offset */\r
-#define JDR_OFFSET ((uint8_t)0x30) \r
- \r
-/* ADC CCR register Mask */\r
-#define CR_CLEAR_MASK ((uint32_t)0xFFFCFFFF) \r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup ADC_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup ADC_Group1 Initialization and Configuration functions\r
- * @brief Initialization and Configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Initialization and Configuration functions\r
- =============================================================================== \r
- This section provides functions allowing to:\r
- - Initialize and configure the ADC Prescaler\r
- - ADC Conversion Resolution (12bit..6bit)\r
- - Scan Conversion Mode (multichannels or one channel) for regular group\r
- - ADC Continuous Conversion Mode (Continuous or Single conversion) for regular group\r
- - External trigger Edge and source of regular group, \r
- - Converted data alignment (left or right)\r
- - The number of ADC conversions that will be done using the sequencer for regular channel group\r
- - Enable or disable the ADC peripheral\r
- \r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes ADC1 peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void ADC_DeInit(ADC_TypeDef* ADCx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- \r
- /* Enable ADC1 reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);\r
- /* Release ADC1 from reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Initializes the ADCx peripheral according to the specified parameters\r
- * in the ADC_InitStruct.\r
- * @note This function is used to configure the global features of the ADC ( \r
- * Resolution and Data Alignment), however, the rest of the configuration\r
- * parameters are specific to the regular channels group (scan mode \r
- * activation, continuous mode activation, External trigger source and \r
- * edge, number of conversion in the regular channels group sequencer). \r
- * @param ADCx: where x can be 1 to select the ADC peripheral.\r
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains \r
- * the configuration information for the specified ADC peripheral.\r
- * @retval None\r
- */\r
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) \r
-{\r
- uint32_t tmpreg1 = 0;\r
- uint8_t tmpreg2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); \r
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));\r
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); \r
- assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); \r
- assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); \r
- assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); \r
- assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));\r
- \r
- /*---------------------------- ADCx CR1 Configuration -----------------*/\r
- /* Get the ADCx CR1 value */\r
- tmpreg1 = ADCx->CR1;\r
- /* Clear RES and SCAN bits */ \r
- tmpreg1 &= CR1_CLEAR_MASK;\r
- /* Configure ADCx: scan conversion mode and resolution */\r
- /* Set SCAN bit according to ADC_ScanConvMode value */\r
- /* Set RES bit according to ADC_Resolution value */ \r
- tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | ADC_InitStruct->ADC_Resolution);\r
- /* Write to ADCx CR1 */\r
- ADCx->CR1 = tmpreg1;\r
- \r
- /*---------------------------- ADCx CR2 Configuration -----------------*/\r
- /* Get the ADCx CR2 value */\r
- tmpreg1 = ADCx->CR2;\r
- /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */\r
- tmpreg1 &= CR2_CLEAR_MASK;\r
- /* Configure ADCx: external trigger event and edge, data alignment and continuous conversion mode */\r
- /* Set ALIGN bit according to ADC_DataAlign value */\r
- /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ \r
- /* Set EXTSEL bits according to ADC_ExternalTrigConv value */\r
- /* Set CONT bit according to ADC_ContinuousConvMode value */\r
- tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | \r
- ADC_InitStruct->ADC_ExternalTrigConvEdge | ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));\r
- /* Write to ADCx CR2 */\r
- ADCx->CR2 = tmpreg1;\r
- \r
- /*---------------------------- ADCx SQR1 Configuration -----------------*/\r
- /* Get the ADCx SQR1 value */\r
- tmpreg1 = ADCx->SQR1;\r
- /* Clear L bits */\r
- tmpreg1 &= SQR1_L_RESET;\r
- /* Configure ADCx: regular channel sequence length */\r
- /* Set L bits according to ADC_NbrOfConversion value */ \r
- tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);\r
- tmpreg1 |= ((uint32_t)tmpreg2 << 20);\r
- /* Write to ADCx SQR1 */\r
- ADCx->SQR1 = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Fills each ADC_InitStruct member with its default value.\r
- * @note This function is used to initialize the global features of the ADC ( \r
- * Resolution and Data Alignment), however, the rest of the configuration\r
- * parameters are specific to the regular channels group (scan mode \r
- * activation, continuous mode activation, External trigger source and \r
- * edge, number of conversion in the regular channels group sequencer). \r
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will \r
- * be initialized.\r
- * @retval None\r
- */\r
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) \r
-{\r
- /* Reset ADC init structure parameters values */\r
- /* Initialize the ADC_Resolution member */\r
- ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;\r
-\r
- /* Initialize the ADC_ScanConvMode member */\r
- ADC_InitStruct->ADC_ScanConvMode = DISABLE;\r
-\r
- /* Initialize the ADC_ContinuousConvMode member */\r
- ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;\r
-\r
- /* Initialize the ADC_ExternalTrigConvEdge member */\r
- ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;\r
-\r
- /* Initialize the ADC_ExternalTrigConv member */\r
- ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T2_CC2;\r
-\r
- /* Initialize the ADC_DataAlign member */\r
- ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;\r
-\r
- /* Initialize the ADC_NbrOfConversion member */\r
- ADC_InitStruct->ADC_NbrOfConversion = 1;\r
-}\r
-\r
-/**\r
- * @brief Initializes the ADCs peripherals according to the specified parameters\r
- * in the ADC_CommonInitStruct.\r
- * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure \r
- * that contains the configuration information (Prescaler) for ADC1 peripheral.\r
- * @retval None\r
- */\r
-void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) \r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));\r
-\r
- /*---------------------------- ADC CCR Configuration -----------------*/\r
- /* Get the ADC CCR value */\r
- tmpreg = ADC->CCR;\r
-\r
- /* Clear ADCPRE bit */ \r
- tmpreg &= CR_CLEAR_MASK;\r
- \r
- /* Configure ADCx: ADC prescaler according to ADC_Prescaler */ \r
- tmpreg |= (uint32_t)(ADC_CommonInitStruct->ADC_Prescaler); \r
- \r
- /* Write to ADC CCR */\r
- ADC->CCR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each ADC_CommonInitStruct member with its default value.\r
- * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure\r
- * which will be initialized.\r
- * @retval None\r
- */\r
-void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) \r
-{\r
- /* Reset ADC init structure parameters values */\r
- /* Initialize the ADC_Prescaler member */\r
- ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div1;\r
-\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified ADC peripheral.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param NewState: new state of the ADCx peripheral. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Set the ADON bit to wake up the ADC from power down mode */\r
- ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC peripheral */\r
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Group2 Power saving functions\r
- * @brief Power saving functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Power saving functions\r
- =============================================================================== \r
-\r
- This section provides functions allowing to reduce power consumption.\r
- The two function must be combined to get the maximal benefits:\r
- When the ADC frequency is higher than the CPU one, it is recommended to \r
- 1. Insert a freeze delay : \r
- ==> using ADC_DelaySelectionConfig(ADC1, ADC_DelayLength_Freeze);\r
- 2. Enable the power down in Idle and Delay phases :\r
- ==> using ADC_PowerDownCmd(ADC1, ADC_PowerDown_Idle_Delay, ENABLE);\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the ADC Power Down during Delay and/or Idle phase.\r
- * @note ADC power-on and power-off can be managed by hardware to cut the \r
- * consumption when the ADC is not converting. \r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_PowerDown: The ADC power down configuration. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_PowerDown_Delay: ADC is powered down during delay phase \r
- * @arg ADC_PowerDown_Idle: ADC is powered down during Idle phase \r
- * @arg ADC_PowerDown_Idle_Delay: ADC is powered down during Delay and Idle phases\r
- * @note The ADC can be powered down: \r
- * - During the hardware delay insertion (using the ADC_PowerDown_Delay\r
- * parameter) \r
- * => The ADC is powered up again at the end of the delay. \r
- * - During the ADC is waiting for a trigger event ( using the \r
- * ADC_PowerDown_Idle parameter) \r
- * => The ADC is powered up at the next trigger event.\r
- * - During the hardware delay insertion or the ADC is waiting for a \r
- * trigger event (using the ADC_PowerDown_Idle_Delay parameter) \r
- * => The ADC is powered up only at the end of the delay and at the \r
- * next trigger event. \r
- * @param NewState: new state of the ADCx power down. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_ADC_POWER_DOWN(ADC_PowerDown));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the ADC power-down during Delay and/or Idle phase */\r
- ADCx->CR1 |= ADC_PowerDown;\r
- }\r
- else\r
- {\r
- /* Disable The ADC power-down during Delay and/or Idle phase */\r
- ADCx->CR1 &= (uint32_t)~ADC_PowerDown;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Defines the length of the delay which is applied after a conversion \r
- * or a sequence of conversion.\r
- * @note When the CPU clock is not fast enough to manage the data rate, a \r
- * Hardware delay can be introduced between ADC conversions to reduce \r
- * this data rate. \r
- * @note The Hardware delay is inserted after :\r
- * - each regular conversion\r
- * - after each sequence of injected conversions\r
- * @note No Hardware delay is inserted between conversions of different groups.\r
- * @note When the hardware delay is not enough, the Freeze Delay Mode can be \r
- * selected and a new conversion can start only if all the previous data \r
- * of the same group have been treated:\r
- * - for a regular conversion: once the ADC conversion data register has \r
- * been read (using ADC_GetConversionValue() function) or if the EOC \r
- * Flag has been cleared (using ADC_ClearFlag() function).\r
- * - for an injected conversion: when the JEOC bit has been cleared \r
- * (using ADC_ClearFlag() function).\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_DelayLength: The length of delay which is applied after a \r
- * conversion or a sequence of conversion. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_DelayLength_None: No delay \r
- * @arg ADC_DelayLength_Freeze: Delay until the converted data has been read.\r
- * @arg ADC_DelayLength_7Cycles: Delay length equal to 7 APB clock cycles\r
- * @arg ADC_DelayLength_15Cycles: Delay length equal to 15 APB clock cycles \r
- * @arg ADC_DelayLength_31Cycles: Delay length equal to 31 APB clock cycles \r
- * @arg ADC_DelayLength_63Cycles: Delay length equal to 63 APB clock cycles \r
- * @arg ADC_DelayLength_127Cycles: Delay length equal to 127 APB clock cycles \r
- * @arg ADC_DelayLength_255Cycles: Delay length equal to 255 APB clock cycles \r
- * @retval None\r
- */\r
-void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_DELAY_LENGTH(ADC_DelayLength));\r
-\r
- /* Get the old register value */ \r
- tmpreg = ADCx->CR2;\r
- /* Clear the old delay length */\r
- tmpreg &= CR2_DELS_RESET;\r
- /* Set the delay length */\r
- tmpreg |= ADC_DelayLength;\r
- /* Store the new register value */\r
- ADCx->CR2 = tmpreg;\r
-\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Group3 Analog Watchdog configuration functions\r
- * @brief Analog Watchdog configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Analog Watchdog configuration functions\r
- =============================================================================== \r
-\r
- This section provides functions allowing to configure the Analog Watchdog\r
- (AWD) feature in the ADC.\r
- \r
- A typical configuration Analog Watchdog is done following these steps :\r
- 1. the ADC guarded channel(s) is (are) selected using the \r
- ADC_AnalogWatchdogSingleChannelConfig() function.\r
- 2. The Analog watchdog lower and higher threshold are configured using the \r
- ADC_AnalogWatchdogThresholdsConfig() function.\r
- 3. The Analog watchdog is enabled and configured to enable the check, on one\r
- or more channels, using the ADC_AnalogWatchdogCmd() function.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
- \r
-/**\r
- * @brief Enables or disables the analog watchdog on single/all regular\r
- * or injected channels\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single \r
- * regular channel\r
- * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single \r
- * injected channel\r
- * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a \r
- * single regular or injected channel \r
- * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular \r
- * channel\r
- * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected \r
- * channel\r
- * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all \r
- * regular and injected channels\r
- * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog\r
- * @retval None \r
- */\r
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));\r
-\r
- /* Get the old register value */\r
- tmpreg = ADCx->CR1;\r
- /* Clear AWDEN, JAWDEN and AWDSGL bits */ \r
- tmpreg &= CR1_AWDMODE_RESET;\r
- /* Set the analog watchdog enable mode */\r
- tmpreg |= ADC_AnalogWatchdog;\r
- /* Store the new register value */\r
- ADCx->CR1 = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Configures the high and low thresholds of the analog watchdog. \r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param HighThreshold: the ADC analog watchdog High threshold value.\r
- * This parameter must be a 12bit value.\r
- * @param LowThreshold: the ADC analog watchdog Low threshold value.\r
- * This parameter must be a 12bit value.\r
- * @retval None\r
- */\r
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,\r
- uint16_t LowThreshold)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_THRESHOLD(HighThreshold));\r
- assert_param(IS_ADC_THRESHOLD(LowThreshold));\r
-\r
- /* Set the ADCx high threshold */\r
- ADCx->HTR = HighThreshold;\r
- /* Set the ADCx low threshold */\r
- ADCx->LTR = LowThreshold;\r
-}\r
-\r
-/**\r
- * @brief Configures the analog watchdog guarded single channel\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_Channel: the ADC channel to configure for the analog watchdog. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_Channel_0: ADC Channel0 selected\r
- * @arg ADC_Channel_1: ADC Channel1 selected\r
- * @arg ADC_Channel_2: ADC Channel2 selected\r
- * @arg ADC_Channel_3: ADC Channel3 selected\r
- * @arg ADC_Channel_4: ADC Channel4 selected\r
- * @arg ADC_Channel_5: ADC Channel5 selected\r
- * @arg ADC_Channel_6: ADC Channel6 selected\r
- * @arg ADC_Channel_7: ADC Channel7 selected\r
- * @arg ADC_Channel_8: ADC Channel8 selected\r
- * @arg ADC_Channel_9: ADC Channel9 selected\r
- * @arg ADC_Channel_10: ADC Channel10 selected\r
- * @arg ADC_Channel_11: ADC Channel11 selected\r
- * @arg ADC_Channel_12: ADC Channel12 selected\r
- * @arg ADC_Channel_13: ADC Channel13 selected\r
- * @arg ADC_Channel_14: ADC Channel14 selected\r
- * @arg ADC_Channel_15: ADC Channel15 selected\r
- * @arg ADC_Channel_16: ADC Channel16 selected\r
- * @arg ADC_Channel_17: ADC Channel17 selected\r
- * @arg ADC_Channel_18: ADC Channel18 selected\r
- * @arg ADC_Channel_19: ADC Channel19 selected\r
- * @arg ADC_Channel_20: ADC Channel20 selected\r
- * @arg ADC_Channel_21: ADC Channel21 selected\r
- * @arg ADC_Channel_22: ADC Channel22 selected\r
- * @arg ADC_Channel_23: ADC Channel23 selected\r
- * @arg ADC_Channel_24: ADC Channel24 selected\r
- * @arg ADC_Channel_25: ADC Channel25 selected\r
- * @retval None\r
- */\r
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
-\r
- /* Get the old register value */\r
- tmpreg = ADCx->CR1;\r
- /* Clear the Analog watchdog channel select bits */\r
- tmpreg &= CR1_AWDCH_RESET;\r
- /* Set the Analog watchdog channel */\r
- tmpreg |= ADC_Channel;\r
- /* Store the new register value */\r
- ADCx->CR1 = tmpreg;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Group4 Temperature Sensor & Vrefint (Voltage Reference internal) management function\r
- * @brief Temperature Sensor & Vrefint (Voltage Reference internal) management function \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Temperature Sensor & Vrefint (Voltage Reference internal) management function\r
- =============================================================================== \r
-\r
- This section provides a function allowing to enable/ disable the internal \r
- connections between the ADC and the Temperature Sensor and the Vrefint source.\r
- \r
- A typical configuration to get the Temperature sensor and Vrefint channels \r
- voltages or is done following these steps :\r
- 1. Enable the internal connection of Temperature sensor and Vrefint sources \r
- with the ADC channels using ADC_TempSensorVrefintCmd() function. \r
- 2. select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using \r
- ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions \r
- 3. Get the voltage values, using ADC_GetConversionValue() or \r
- ADC_GetInjectedConversionValue().\r
- \r
-@endverbatim\r
- * @{\r
- */\r
- \r
-/**\r
- * @brief Enables or disables the temperature sensor and Vrefint channel.\r
- * @param NewState: new state of the temperature sensor and Vref int channels.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_TempSensorVrefintCmd(FunctionalState NewState) \r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the temperature sensor and Vrefint channel*/\r
- ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;\r
- }\r
- else\r
- {\r
- /* Disable the temperature sensor and Vrefint channel*/\r
- ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Group5 Regular Channels Configuration functions\r
- * @brief Regular Channels Configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Regular Channels Configuration functions\r
- =============================================================================== \r
-\r
- This section provides functions allowing to manage the ADC regular channels,\r
- it is composed of 2 sub sections : \r
- \r
- 1. Configuration and management functions for regular channels: This subsection \r
- provides functions allowing to configure the ADC regular channels : \r
- - Configure the rank in the regular group sequencer for each channel\r
- - Configure the sampling time for each channel\r
- - select the conversion Trigger for regular channels\r
- - select the desired EOC event behavior configuration\r
- - Activate the continuous Mode (*)\r
- - Activate the Discontinuous Mode \r
- Please Note that the following features for regular channels are configurated\r
- using the ADC_Init() function : \r
- - scan mode activation \r
- - continuous mode activation (**) \r
- - External trigger source \r
- - External trigger edge \r
- - number of conversion in the regular channels group sequencer.\r
- \r
- @note : (*) and (**) are performing the same configuration\r
- \r
- 2. Get the conversion data: This subsection provides an important function in \r
- the ADC peripheral since it returns the converted data of the current \r
- regular channel. When the Conversion value is read, the EOC Flag is \r
- automatically cleared.\r
- \r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures for the selected ADC regular channel its corresponding\r
- * rank in the sequencer and its sampling time.\r
- * @param ADCx: where x can be 1 to select the ADC peripheral.\r
- * @param ADC_Channel: the ADC channel to configure. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_Channel_0: ADC Channel0 selected\r
- * @arg ADC_Channel_1: ADC Channel1 selected\r
- * @arg ADC_Channel_2: ADC Channel2 selected\r
- * @arg ADC_Channel_3: ADC Channel3 selected\r
- * @arg ADC_Channel_4: ADC Channel4 selected\r
- * @arg ADC_Channel_5: ADC Channel5 selected\r
- * @arg ADC_Channel_6: ADC Channel6 selected\r
- * @arg ADC_Channel_7: ADC Channel7 selected\r
- * @arg ADC_Channel_8: ADC Channel8 selected\r
- * @arg ADC_Channel_9: ADC Channel9 selected\r
- * @arg ADC_Channel_10: ADC Channel10 selected\r
- * @arg ADC_Channel_11: ADC Channel11 selected\r
- * @arg ADC_Channel_12: ADC Channel12 selected\r
- * @arg ADC_Channel_13: ADC Channel13 selected\r
- * @arg ADC_Channel_14: ADC Channel14 selected\r
- * @arg ADC_Channel_15: ADC Channel15 selected\r
- * @arg ADC_Channel_16: ADC Channel16 selected\r
- * @arg ADC_Channel_17: ADC Channel17 selected\r
- * @arg ADC_Channel_18: ADC Channel18 selected \r
- * @arg ADC_Channel_19: ADC Channel19 selected\r
- * @arg ADC_Channel_20: ADC Channel20 selected\r
- * @arg ADC_Channel_21: ADC Channel21 selected\r
- * @arg ADC_Channel_22: ADC Channel22 selected\r
- * @arg ADC_Channel_23: ADC Channel23 selected\r
- * @arg ADC_Channel_24: ADC Channel24 selected\r
- * @arg ADC_Channel_25: ADC Channel25 selected\r
- * @param Rank: The rank in the regular group sequencer. This parameter\r
- * must be between 1 to 26.\r
- * @param ADC_SampleTime: The sample time value to be set for the selected \r
- * channel. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles \r
- * @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles\r
- * @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles\r
- * @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles \r
- * @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles \r
- * @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles \r
- * @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles \r
- * @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles \r
- * @retval None\r
- */\r
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
-{\r
- uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
- assert_param(IS_ADC_REGULAR_RANK(Rank));\r
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
-\r
- /* if ADC_Channel_20 ... ADC_Channel_25 is selected */\r
- if (ADC_Channel > ADC_Channel_19)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR1;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));\r
- /* Clear the old sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));\r
- /* Set the new sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR1 = tmpreg1;\r
- }\r
- \r
- /* if ADC_Channel_10 ... ADC_Channel_19 is selected */\r
- else if (ADC_Channel > ADC_Channel_9)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR2;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));\r
- /* Clear the old sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));\r
- /* Set the new sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR2 = tmpreg1;\r
- }\r
- \r
- else /* ADC_Channel include in ADC_Channel_[0..9] */\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR3;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);\r
- /* Clear the old sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
- /* Set the new sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR3 = tmpreg1;\r
- }\r
- /* For Rank 1 to 6 */\r
- if (Rank < 7)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SQR5;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SQR5_SQ_SET << (5 * (Rank - 1));\r
- /* Clear the old SQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));\r
- /* Set the SQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SQR5 = tmpreg1;\r
- }\r
- /* For Rank 7 to 12 */\r
- else if (Rank < 13)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SQR4;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SQR4_SQ_SET << (5 * (Rank - 7));\r
- /* Clear the old SQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));\r
- /* Set the SQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SQR4 = tmpreg1;\r
- } \r
- /* For Rank 13 to 18 */\r
- else if (Rank < 19)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SQR3;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 13));\r
- /* Clear the old SQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));\r
- /* Set the SQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SQR3 = tmpreg1;\r
- }\r
- \r
- /* For Rank 19 to 24 */\r
- else if (Rank < 25)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SQR2;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 19));\r
- /* Clear the old SQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 19));\r
- /* Set the SQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SQR2 = tmpreg1;\r
- } \r
- \r
- /* For Rank 25 to 27 */\r
- else\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SQR1;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 25));\r
- /* Clear the old SQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 25));\r
- /* Set the SQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SQR1 = tmpreg1;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables the selected ADC software start conversion of the regular channels.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @retval None\r
- */\r
-void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
-\r
- /* Enable the selected ADC conversion for regular group */\r
- ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r
-}\r
-\r
-/**\r
- * @brief Gets the selected ADC Software start regular conversion Status.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @retval The new state of ADC software start conversion (SET or RESET).\r
- */\r
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)\r
-{\r
- FlagStatus bitstatus = RESET;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
-\r
- /* Check the status of SWSTART bit */\r
- if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET)\r
- {\r
- /* SWSTART bit is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* SWSTART bit is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the SWSTART bit status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the EOC on each regular channel conversion\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param NewState: new state of the selected ADC EOC flag rising\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC EOC rising on each regular channel conversion */\r
- ADCx->CR2 |= ADC_CR2_EOCS;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC EOC rising on each regular channel conversion */\r
- ADCx->CR2 &= (uint32_t)~ADC_CR2_EOCS;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the ADC continuous conversion mode \r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param NewState: new state of the selected ADC continuous conversion mode\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC continuous conversion mode */\r
- ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC continuous conversion mode */\r
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the discontinuous mode for the selected ADC regular\r
- * group channel.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param Number: specifies the discontinuous mode regular channel count value. \r
- * This number must be between 1 and 8.\r
- * @retval None\r
- */\r
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)\r
-{\r
- uint32_t tmpreg1 = 0;\r
- uint32_t tmpreg2 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));\r
-\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->CR1;\r
- /* Clear the old discontinuous mode channel count */\r
- tmpreg1 &= CR1_DISCNUM_RESET;\r
- /* Set the discontinuous mode channel count */\r
- tmpreg2 = Number - 1;\r
- tmpreg1 |= tmpreg2 << 13;\r
- /* Store the new register value */\r
- ADCx->CR1 = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the discontinuous mode on regular group\r
- * channel for the specified ADC\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param NewState: new state of the selected ADC discontinuous mode on regular \r
- * group channel. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC regular discontinuous mode */\r
- ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC regular discontinuous mode */\r
- ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Returns the last ADCx conversion result data for regular channel. \r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @retval The Data conversion value.\r
- */\r
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
-\r
- /* Return the selected ADC conversion value */\r
- return (uint16_t) ADCx->DR;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Group6 Regular Channels DMA Configuration functions\r
- * @brief Regular Channels DMA Configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Regular Channels DMA Configuration functions\r
- =============================================================================== \r
-\r
- This section provides functions allowing to configure the DMA for ADC regular \r
- channels.\r
- Since converted regular channel values are stored into a unique data register, \r
- it is useful to use DMA for conversion of more than one regular channel. This \r
- avoids the loss of the data already stored in the ADC Data register. \r
- \r
- When the DMA mode is enabled (using the ADC_DMACmd() function), after each\r
- conversion of a regular channel, a DMA request is generated.\r
- \r
- Depending on the "DMA disable selection" configuration (using the \r
- ADC_DMARequestAfterLastTransferCmd() function), at the end of the last DMA \r
- transfer, two possibilities are allowed:\r
- - No new DMA request is issued to the DMA controller (feature DISABLED) \r
- - Requests can continue to be generated (feature ENABLED).\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified ADC DMA request.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param NewState: new state of the selected ADC DMA transfer.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_DMA_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC DMA request */\r
- ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC DMA request */\r
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);\r
- }\r
-}\r
-\r
-\r
-/**\r
- * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) \r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param NewState: new state of the selected ADC EOC flag rising\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC DMA request after last transfer */\r
- ADCx->CR2 |= ADC_CR2_DDS;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC DMA request after last transfer */\r
- ADCx->CR2 &= (uint32_t)~ADC_CR2_DDS;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Group7 Injected channels Configuration functions\r
- * @brief Injected channels Configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Injected channels Configuration functions\r
- =============================================================================== \r
-\r
- This section provide functions allowing to configure the ADC Injected channels,\r
- it is composed of 2 sub sections : \r
- \r
- 1. Configuration functions for Injected channels: This subsection provides \r
- functions allowing to configure the ADC injected channels : \r
- - Configure the rank in the injected group sequencer for each channel\r
- - Configure the sampling time for each channel \r
- - Activate the Auto injected Mode \r
- - Activate the Discontinuous Mode \r
- - scan mode activation \r
- - External/software trigger source \r
- - External trigger edge \r
- - injected channels sequencer.\r
- \r
- 2. Get the Specified Injected channel conversion data: This subsection \r
- provides an important function in the ADC peripheral since it returns the \r
- converted data of the specific injected channel.\r
-\r
-@endverbatim\r
- * @{\r
- */ \r
-\r
-/**\r
- * @brief Configures for the selected ADC injected channel its corresponding\r
- * rank in the sequencer and its sample time.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_Channel: the ADC channel to configure. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_Channel_0: ADC Channel0 selected\r
- * @arg ADC_Channel_1: ADC Channel1 selected\r
- * @arg ADC_Channel_2: ADC Channel2 selected\r
- * @arg ADC_Channel_3: ADC Channel3 selected\r
- * @arg ADC_Channel_4: ADC Channel4 selected\r
- * @arg ADC_Channel_5: ADC Channel5 selected\r
- * @arg ADC_Channel_6: ADC Channel6 selected\r
- * @arg ADC_Channel_7: ADC Channel7 selected\r
- * @arg ADC_Channel_8: ADC Channel8 selected\r
- * @arg ADC_Channel_9: ADC Channel9 selected\r
- * @arg ADC_Channel_10: ADC Channel10 selected\r
- * @arg ADC_Channel_11: ADC Channel11 selected\r
- * @arg ADC_Channel_12: ADC Channel12 selected\r
- * @arg ADC_Channel_13: ADC Channel13 selected\r
- * @arg ADC_Channel_14: ADC Channel14 selected\r
- * @arg ADC_Channel_15: ADC Channel15 selected\r
- * @arg ADC_Channel_16: ADC Channel16 selected\r
- * @arg ADC_Channel_17: ADC Channel17 selected\r
- * @arg ADC_Channel_18: ADC Channel18 selected \r
- * @arg ADC_Channel_19: ADC Channel19 selected\r
- * @arg ADC_Channel_20: ADC Channel20 selected\r
- * @arg ADC_Channel_21: ADC Channel21 selected\r
- * @arg ADC_Channel_22: ADC Channel22 selected\r
- * @arg ADC_Channel_23: ADC Channel23 selected\r
- * @arg ADC_Channel_24: ADC Channel24 selected\r
- * @arg ADC_Channel_25: ADC Channel25 selected\r
- * @param Rank: The rank in the injected group sequencer. This parameter\r
- * must be between 1 to 4.\r
- * @param ADC_SampleTime: The sample time value to be set for the selected \r
- * channel. This parameter can be one of the following values:\r
- * @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles \r
- * @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles\r
- * @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles\r
- * @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles \r
- * @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles \r
- * @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles \r
- * @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles \r
- * @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles \r
- * @retval None\r
- */\r
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
-{\r
- uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
- assert_param(IS_ADC_INJECTED_RANK(Rank));\r
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
- \r
- /* if ADC_Channel_20 ... ADC_Channel_25 is selected */\r
- if (ADC_Channel > ADC_Channel_19)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR1;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));\r
- /* Clear the old sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));\r
- /* Set the new sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR1 = tmpreg1;\r
- }\r
- \r
- /* if ADC_Channel_10 ... ADC_Channel_19 is selected */\r
- else if (ADC_Channel > ADC_Channel_9)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR2;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));\r
- /* Clear the old sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));\r
- /* Set the new sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR2 = tmpreg1;\r
- }\r
- \r
- else /* ADC_Channel include in ADC_Channel_[0..9] */\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR3;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);\r
- /* Clear the old sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
- /* Set the new sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR3 = tmpreg1;\r
- }\r
- \r
- /* Rank configuration */\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->JSQR;\r
- /* Get JL value: Number = JL+1 */\r
- tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20;\r
- /* Calculate the mask to clear: ((Rank-1)+(4- (JL+1))) */ \r
- tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));\r
- /* Clear the old JSQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set: ((Rank-1)+(4- (JL+1))) */ \r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));\r
- /* Set the JSQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->JSQR = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Configures the sequencer length for injected channels\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param Length: The sequencer length. \r
- * This parameter must be a number between 1 to 4.\r
- * @retval None\r
- */\r
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)\r
-{\r
- uint32_t tmpreg1 = 0;\r
- uint32_t tmpreg2 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_INJECTED_LENGTH(Length));\r
- \r
- /* Get the old register value */\r
- tmpreg1 = ADCx->JSQR;\r
- /* Clear the old injected sequence length JL bits */\r
- tmpreg1 &= JSQR_JL_RESET;\r
- /* Set the injected sequence length JL bits */\r
- tmpreg2 = Length - 1; \r
- tmpreg1 |= tmpreg2 << 20;\r
- /* Store the new register value */\r
- ADCx->JSQR = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Set the injected channels conversion value offset\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_InjectedChannel: the ADC injected channel to set its offset. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r
- * @param Offset: the offset value for the selected ADC injected channel\r
- * This parameter must be a 12bit value.\r
- * @retval None\r
- */\r
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)\r
-{\r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
- assert_param(IS_ADC_OFFSET(Offset)); \r
- \r
- tmp = (uint32_t)ADCx;\r
- tmp += ADC_InjectedChannel;\r
- \r
- /* Set the selected injected channel data offset */\r
- *(__IO uint32_t *) tmp = (uint32_t)Offset;\r
-}\r
-\r
-/**\r
- * @brief Configures the ADCx external trigger for injected channels conversion.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected \r
- * conversion. This parameter can be one of the following values: \r
- * @arg ADC_ExternalTrigInjecConv_T9_CC1: Timer9 capture compare1 selected \r
- * @arg ADC_ExternalTrigInjecConv_T9_TRGO: Timer9 TRGO event selected \r
- * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected \r
- * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected\r
- * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected \r
- * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected \r
- * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected \r
- * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected \r
- * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected \r
- * @arg ADC_ExternalTrigInjecConv_T10_CC1: Timer10 capture compare1 selected\r
- * @arg ADC_ExternalTrigInjecConv_T7_TRGO: Timer7 TRGO event selected \r
- * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected \r
- * @retval None\r
- */\r
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));\r
-\r
- /* Get the old register value */\r
- tmpreg = ADCx->CR2;\r
- /* Clear the old external event selection for injected group */\r
- tmpreg &= CR2_JEXTSEL_RESET;\r
- /* Set the external event selection for injected group */\r
- tmpreg |= ADC_ExternalTrigInjecConv;\r
- /* Store the new register value */\r
- ADCx->CR2 = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Configures the ADCx external trigger edge for injected channels conversion.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger\r
- * edge to start injected conversion. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_ExternalTrigConvEdge_None: external trigger disabled for \r
- * injected conversion\r
- * @arg ADC_ExternalTrigConvEdge_Rising: detection on rising edge\r
- * @arg ADC_ExternalTrigConvEdge_Falling: detection on falling edge\r
- * @arg ADC_External ADC_ExternalTrigConvEdge_RisingFalling: detection on \r
- * both rising and falling edge\r
- * @retval None\r
- */\r
-void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));\r
-\r
- /* Get the old register value */\r
- tmpreg = ADCx->CR2;\r
- /* Clear the old external trigger edge for injected group */\r
- tmpreg &= CR2_JEXTEN_RESET;\r
- /* Set the new external trigger edge for injected group */\r
- tmpreg |= ADC_ExternalTrigInjecConvEdge;\r
- /* Store the new register value */\r
- ADCx->CR2 = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables the selected ADC software start conversion of the injected \r
- * channels.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @retval None\r
- */\r
-void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- /* Enable the selected ADC conversion for injected group */\r
- ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;\r
-}\r
-\r
-/**\r
- * @brief Gets the selected ADC Software start injected conversion Status.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @retval The new state of ADC software start injected conversion (SET or RESET).\r
- */\r
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)\r
-{\r
- FlagStatus bitstatus = RESET;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
-\r
- /* Check the status of JSWSTART bit */\r
- if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)\r
- {\r
- /* JSWSTART bit is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* JSWSTART bit is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the JSWSTART bit status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the selected ADC automatic injected group\r
- * conversion after regular one.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param NewState: new state of the selected ADC auto injected\r
- * conversion. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC automatic injected group conversion */\r
- ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC automatic injected group conversion */\r
- ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the discontinuous mode for injected group\r
- * channel for the specified ADC\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param NewState: new state of the selected ADC discontinuous mode\r
- * on injected group channel. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC injected discontinuous mode */\r
- ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC injected discontinuous mode */\r
- ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Returns the ADC injected channel conversion result\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_InjectedChannel: the converted ADC injected channel.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r
- * @retval The Data conversion value.\r
- */\r
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)\r
-{\r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
-\r
- tmp = (uint32_t)ADCx;\r
- tmp += ADC_InjectedChannel + JDR_OFFSET;\r
- \r
- /* Returns the selected injected channel conversion data value */\r
- return (uint16_t) (*(__IO uint32_t*) tmp); \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Group8 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- Interrupts and flags management functions\r
- =============================================================================== \r
-\r
- This section provides functions allowing to configure the ADC Interrupts and get \r
- the status and clear flags and Interrupts pending bits.\r
- \r
- The ADC provide 4 Interrupts sources and 9 Flags which can be divided into 3 groups:\r
- \r
- I. Flags and Interrupts for ADC regular channels\r
- =================================================\r
- Flags :\r
- ---------- \r
- 1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost\r
-\r
- 2. ADC_FLAG_EOC : Regular channel end of conversion + to indicate (depending \r
- on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of :\r
- ==> a regular CHANNEL conversion \r
- ==> sequence of regular GROUP conversions .\r
-\r
- 3. ADC_FLAG_STRT: Regular channel start + to indicate when regular CHANNEL \r
- conversion starts.\r
- \r
- 4. ADC_FLAG_RCNR: Regular channel not ready+ to indicate if a new regular \r
- conversion can be launched\r
- \r
- Interrupts :\r
- ------------\r
- 1. ADC_IT_OVR \r
- 2. ADC_IT_EOC \r
- \r
- \r
- II. Flags and Interrupts for ADC Injected channels\r
- =================================================\r
- Flags :\r
- ---------- \r
- 1. ADC_FLAG_JEOC : Injected channel end of conversion+ to indicate at \r
- the end of injected GROUP conversion \r
- \r
- 2. ADC_FLAG_JSTRT: Injected channel start + to indicate hardware when \r
- injected GROUP conversion starts.\r
-\r
- 3. ADC_FLAG_JCNR: Injected channel not ready + to indicate if a new \r
- injected conversion can be launched.\r
-\r
- Interrupts :\r
- ------------\r
- 1. ADC_IT_JEOC \r
-\r
- III. General Flags and Interrupts for the ADC\r
- ================================================= \r
- Flags :\r
- ---------- \r
- 1. ADC_FLAG_AWD: Analog watchdog + to indicate if the converted voltage \r
- crosses the programmed thresholds values.\r
- \r
- 2. ADC_FLAG_ADONS: ADC ON status + to indicate if the ADC is ready to convert.\r
- \r
- Interrupts :\r
- ------------\r
- 1. ADC_IT_AWD \r
-\r
-@endverbatim\r
- * @{\r
- */ \r
-\r
-/**\r
- * @brief Enables or disables the specified ADC interrupts.\r
- * @param ADCx: where x can be 1 to select the ADC peripheral.\r
- * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_IT_EOC: End of conversion interrupt \r
- * @arg ADC_IT_AWD: Analog watchdog interrupt \r
- * @arg ADC_IT_JEOC: End of injected conversion interrupt \r
- * @arg ADC_IT_OVR: overrun interrupt \r
- * @param NewState: new state of the specified ADC interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) \r
-{\r
- uint32_t itmask = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_ADC_IT(ADC_IT)); \r
-\r
- /* Get the ADC IT index */\r
- itmask = (uint8_t)ADC_IT;\r
- itmask = (uint32_t)0x01 << itmask; \r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC interrupts */\r
- ADCx->CR1 |= itmask;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC interrupts */\r
- ADCx->CR1 &= (~(uint32_t)itmask);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified ADC flag is set or not.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_FLAG: specifies the flag to check. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_FLAG_AWD: Analog watchdog flag\r
- * @arg ADC_FLAG_EOC: End of conversion flag\r
- * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
- * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
- * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
- * @arg ADC_FLAG_OVR: Overrun flag \r
- * @arg ADC_FLAG_ADONS: ADC ON status \r
- * @arg ADC_FLAG_RCNR: Regular channel not ready \r
- * @arg ADC_FLAG_JCNR: Injected channel not ready \r
- * @retval The new state of ADC_FLAG (SET or RESET).\r
- */\r
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_GET_FLAG(ADC_FLAG));\r
-\r
- /* Check the status of the specified ADC flag */\r
- if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)\r
- {\r
- /* ADC_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* ADC_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the ADC_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the ADCx's pending flags.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_FLAG: specifies the flag to clear. \r
- * This parameter can be any combination of the following values:\r
- * @arg ADC_FLAG_AWD: Analog watchdog flag\r
- * @arg ADC_FLAG_EOC: End of conversion flag\r
- * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
- * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
- * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
- * @arg ADC_FLAG_OVR: overrun flag \r
- * @retval None\r
- */\r
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));\r
-\r
- /* Clear the selected ADC flags */\r
- ADCx->SR = ~(uint32_t)ADC_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified ADC interrupt has occurred or not.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_IT: specifies the ADC interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_IT_EOC: End of conversion interrupt \r
- * @arg ADC_IT_AWD: Analog watchdog interrupt \r
- * @arg ADC_IT_JEOC: End of injected conversion interrupt \r
- * @arg ADC_IT_OVR: Overrun interrupt \r
- * @retval The new state of ADC_IT (SET or RESET).\r
- */\r
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t itmask = 0, enablestatus = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_IT(ADC_IT));\r
-\r
- /* Get the ADC IT index */\r
- itmask = (uint32_t)((uint32_t)ADC_IT >> 8);\r
-\r
- /* Get the ADC_IT enable bit status */\r
- enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)); \r
-\r
- /* Check the status of the specified ADC interrupt */\r
- if (((uint32_t)(ADCx->SR & (uint32_t)itmask) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r
- { \r
- /* ADC_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* ADC_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the ADC_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the ADCx\92s interrupt pending bits.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_IT: specifies the ADC interrupt pending bit to clear.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_IT_EOC: End of conversion interrupt \r
- * @arg ADC_IT_AWD: Analog watchdog interrupt \r
- * @arg ADC_IT_JEOC: End of injected conversion interrupt \r
- * @arg ADC_IT_OVR: Overrun interrupt \r
- * @retval None\r
- */\r
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
-{\r
- uint8_t itmask = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_IT(ADC_IT)); \r
-\r
- /* Get the ADC IT index */\r
- itmask = (uint8_t)(ADC_IT >> 8);\r
-\r
- /* Clear the selected ADC interrupt pending bits */\r
- ADCx->SR = ~(uint32_t)itmask;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_comp.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the comparators (COMP1 and COMP2) peripheral: \r
- * - Comparators configuration\r
- * - Window mode control\r
- * - Internal Reference Voltage (VREFINT) output\r
- *\r
- * @verbatim\r
- *\r
- * ===================================================================\r
- * How to use this driver\r
- * ===================================================================\r
- * \r
- * The device integrates two analog comparators COMP1 and COMP2: \r
- * - COMP1 is a fixed threshold (VREFINT) that shares the non inverting\r
- * input with the ADC channels.\r
- *\r
- * - COMP2 is a rail-to-rail comparator whose the inverting input \r
- * can be selected among: DAC_OUT1, DAC_OUT2, 1/4 VREFINT,\r
- * 1/2 VERFINT, 3/4 VREFINT, VREFINT, PB3 and whose the output\r
- * can be redirected to embedded timers: TIM2, TIM3, TIM4, TIM10\r
- *\r
- * - The two comparators COMP1 and COMP2 can be combined in window\r
- * mode.\r
- *\r
- * @note\r
- * 1- Comparator APB clock must be enabled to get write access\r
- * to comparator register using\r
- * RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE);\r
- *\r
- * 2- COMP1 comparator and ADC can't be used at the same time since\r
- * they share the same ADC switch matrix (analog switches).\r
- *\r
- * 3- When an I/O is used as comparator input, the corresponding GPIO \r
- * registers should be configured in analog mode.\r
- *\r
- * 4- Comparators outputs (CMP1OUT and CMP2OUT) are not mapped on\r
- * GPIO pin. They are only internal.\r
- * To get the comparator output level, use COMP_GetOutputLevel()\r
- *\r
- * 5- COMP1 and COMP2 outputs are internally connected to EXTI Line 21\r
- * and EXTI Line 22 respectively.\r
- * Interrupts can be used by configuring the EXTI Line using the \r
- * EXTI peripheral driver.\r
- *\r
- * 6- After enabling the comparator (COMP1 or COMP2), user should wait\r
- * for start-up time (tSTART) to get right output levels.\r
- * Please refer to product datasheet for more information on tSTART. \r
- *\r
- * 7- Comparators cannot be used to exit the device from Sleep or Stop \r
- * mode when the internal reference voltage is switched off using \r
- * the PWR_UltraLowPowerCmd() function (ULP bit in the PWR_CR register).\r
- *\r
- * @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_comp.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup COMP \r
- * @brief COMP driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup COMP_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup COMP_Group1 Initialization and Configuration functions\r
- * @brief Initialization and Configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Initialization and Configuration functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
- \r
-/**\r
- * @brief Deinitializes COMP peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void COMP_DeInit(void)\r
-{\r
- COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP->CSR to reset value */\r
-}\r
-\r
-/**\r
- * @brief Initializes the COMP2 peripheral according to the specified parameters\r
- * in the COMP_InitStruct:\r
- * - COMP_InvertingInput specify the inverting input of COMP2\r
- * - COMP_OutputSelect connect the output of COMP2 to selected timer\r
- * input (Input capture / Output Compare Reference Clear)\r
- * - COMP_Speed configures COMP2 speed for optimum speed/consumption ratio\r
- * @note This function configures only COMP2.\r
- * @note COMP2 comparator is enabled as soon as the INSEL[2:0] bits are \r
- * different from "000".\r
- * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains \r
- * the configuration information for the specified COMP peripheral.\r
- * @retval None\r
- */\r
-void COMP_Init(COMP_InitTypeDef* COMP_InitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));\r
- assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_OutputSelect));\r
- assert_param(IS_COMP_SPEED(COMP_InitStruct->COMP_Speed));\r
-\r
- /*!< Get the COMP CSR value */\r
- tmpreg = COMP->CSR;\r
-\r
- /*!< Clear the INSEL[2:0], OUTSEL[1:0] and SPEED bits */ \r
- tmpreg &= (uint32_t) (~(uint32_t) (COMP_CSR_OUTSEL | COMP_CSR_INSEL | COMP_CSR_SPEED));\r
- \r
- /*!< Configure COMP: speed, inversion input selection and output redirection */\r
- /*!< Set SPEED bit according to COMP_InitStruct->COMP_Speed value */\r
- /*!< Set INSEL bits according to COMP_InitStruct->COMP_InvertingInput value */ \r
- /*!< Set OUTSEL bits according to COMP_InitStruct->COMP_OutputSelect value */ \r
- tmpreg |= (uint32_t)((COMP_InitStruct->COMP_Speed | COMP_InitStruct->COMP_InvertingInput \r
- | COMP_InitStruct->COMP_OutputSelect));\r
-\r
- /*!< The COMP2 comparator is enabled as soon as the INSEL[2:0] bits value are \r
- different from "000" */\r
- /*!< Write to COMP_CSR register */\r
- COMP->CSR = tmpreg; \r
-}\r
-\r
-/**\r
- * @brief Enable or disable the COMP1 peripheral.\r
- * After enabling COMP1, the following functions should be called to \r
- * connect the selected GPIO input to COMP1 non inverting input:\r
- * - Enable switch control mode using SYSCFG_RISwitchControlModeCmd()\r
- * - Close VCOMP switch using SYSCFG_RIIOSwitchConfig()\r
- * - Close the I/O switch number n corresponding to the I/O \r
- * using SYSCFG_RIIOSwitchConfig()\r
- * @param NewState: new state of the COMP1 peripheral.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note This function enables/disables only the COMP1.\r
- * @retval None\r
- */\r
-void COMP_Cmd(FunctionalState NewState)\r
-{\r
- /* Check the parameter */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the COMP1 */\r
- COMP->CSR |= (uint32_t) COMP_CSR_CMP1EN;\r
- }\r
- else\r
- {\r
- /* Disable the COMP1 */\r
- COMP->CSR &= (uint32_t)(~COMP_CSR_CMP1EN);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Return the output level (high or low) of the selected comparator:\r
- * - Comparator output is low when the non-inverting input is at a lower\r
- * voltage than the inverting input\r
- * - Comparator output is high when the non-inverting input is at a higher\r
- * voltage than the inverting input\r
- * @note Comparators outputs aren't available on GPIO (outputs levels are \r
- * only internal). The COMP1 and COMP2 outputs are connected internally \r
- * to the EXTI Line 21 and Line 22 respectively. \r
- * @param COMP_Selection: the selected comparator. \r
- * This parameter can be one of the following values:\r
- * @arg COMP_Selection_COMP1: COMP1 selected\r
- * @arg COMP_Selection_COMP2: COMP2 selected \r
- * @retval Returns the selected comparator output level.\r
- */\r
-uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection)\r
-{\r
- uint8_t compout = 0x0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));\r
-\r
- /* Check if Comparator 1 is selected */\r
- if(COMP_Selection == COMP_Selection_COMP1)\r
- {\r
- /* Check if comparator 1 output level is high */\r
- if((COMP->CSR & COMP_CSR_CMP1OUT) != (uint8_t) RESET)\r
- {\r
- /* Get Comparator 1 output level */\r
- compout = (uint8_t) COMP_OutputLevel_High;\r
- }\r
- /* comparator 1 output level is low */\r
- else\r
- {\r
- /* Get Comparator 1 output level */\r
- compout = (uint8_t) COMP_OutputLevel_Low;\r
- }\r
- }\r
- /* Comparator 2 is selected */\r
- else\r
- {\r
- /* Check if comparator 2 output level is high */\r
- if((COMP->CSR & COMP_CSR_CMP2OUT) != (uint8_t) RESET)\r
- {\r
- /* Get Comparator output level */\r
- compout = (uint8_t) COMP_OutputLevel_High;\r
- }\r
- /* comparator 2 output level is low */\r
- else\r
- {\r
- /* Get Comparator 2 output level */\r
- compout = (uint8_t) COMP_OutputLevel_Low;\r
- }\r
- }\r
- /* Return the comparator output level */\r
- return (uint8_t)(compout);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup COMP_Group2 Window mode control function\r
- * @brief Window mode control function \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Window mode control function\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the window mode.\r
- * In window mode:\r
- * - COMP1 inverting input is fixed to VREFINT defining the first\r
- * threshold\r
- * - COMP2 inverting input is configurable (DAC_OUT1, DAC_OUT2, VREFINT\r
- * sub-multiples, PB3) defining the second threshold\r
- * - COMP1 and COMP2 non inverting inputs are connected together.\r
- * @note In window mode, only the Group 6 (PB4 or PB5) can be used as\r
- * non-inverting inputs.\r
- * param NewState: new state of the window mode. \r
- * This parameter can be ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void COMP_WindowCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the window mode */\r
- COMP->CSR |= (uint32_t) COMP_CSR_WNDWE;\r
- }\r
- else\r
- {\r
- /* Disable the window mode */\r
- COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWE);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup COMP_Group3 Internal Reference Voltage output function\r
- * @brief Internal Reference Voltage (VREFINT) output function \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Internal Reference Voltage (VREFINT) output function\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the output of internal reference voltage (VREFINT).\r
- * The VREFINT output can be routed to any I/O in group 3: CH8 (PB0) or\r
- * CH9 (PB1).\r
- * To correctly use this function, the SYSCFG_RIIOSwitchConfig() function\r
- * should be called after.\r
- * @param NewState: new state of the Vrefint output.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void COMP_VrefintOutputCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the output of internal reference voltage */\r
- COMP->CSR |= (uint32_t) COMP_CSR_VREFOUTEN;\r
- }\r
- else\r
- {\r
- /* Disable the output of internal reference voltage */\r
- COMP->CSR &= (uint32_t) (~COMP_CSR_VREFOUTEN);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_crc.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides all the CRC firmware functions.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_crc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup CRC \r
- * @brief CRC driver modules\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup CRC_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Resets the CRC Data register (DR).\r
- * @param None\r
- * @retval None\r
- */\r
-void CRC_ResetDR(void)\r
-{\r
- /* Reset CRC generator */\r
- CRC->CR = CRC_CR_RESET;\r
-}\r
-\r
-/**\r
- * @brief Computes the 32-bit CRC of a given data word(32-bit).\r
- * @param Data: data word(32-bit) to compute its CRC\r
- * @retval 32-bit CRC\r
- */\r
-uint32_t CRC_CalcCRC(uint32_t Data)\r
-{\r
- CRC->DR = Data;\r
- \r
- return (CRC->DR);\r
-}\r
-\r
-/**\r
- * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).\r
- * @param pBuffer: pointer to the buffer containing the data to be computed\r
- * @param BufferLength: length of the buffer to be computed \r
- * @retval 32-bit CRC\r
- */\r
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)\r
-{\r
- uint32_t index = 0;\r
- \r
- for(index = 0; index < BufferLength; index++)\r
- {\r
- CRC->DR = pBuffer[index];\r
- }\r
- return (CRC->DR);\r
-}\r
-\r
-/**\r
- * @brief Returns the current CRC value.\r
- * @param None\r
- * @retval 32-bit CRC\r
- */\r
-uint32_t CRC_GetCRC(void)\r
-{\r
- return (CRC->DR);\r
-}\r
-\r
-/**\r
- * @brief Stores a 8-bit data in the Independent Data(ID) register.\r
- * @param IDValue: 8-bit value to be stored in the ID register \r
- * @retval None\r
- */\r
-void CRC_SetIDRegister(uint8_t IDValue)\r
-{\r
- CRC->IDR = IDValue;\r
-}\r
-\r
-/**\r
- * @brief Returns the 8-bit data stored in the Independent Data(ID) register\r
- * @param None\r
- * @retval 8-bit value of the ID register \r
- */\r
-uint8_t CRC_GetIDRegister(void)\r
-{\r
- return (CRC->IDR);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_dac.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Digital-to-Analog Converter (DAC) peripheral: \r
- * - DAC channels configuration: trigger, output buffer, data format\r
- * - DMA management \r
- * - Interrupts and flags management\r
- *\r
- * @verbatim\r
- * \r
- * ===================================================================\r
- * DAC Peripheral features\r
- * ===================================================================\r
- * The device integrates two 12-bit Digital Analog Converters that can \r
- * be used independently or simultaneously (dual mode):\r
- * 1- DAC channel1 with DAC_OUT1 (PA4) as output\r
- * 1- DAC channel2 with DAC_OUT2 (PA5) as output\r
- *\r
- * Digital to Analog conversion can be non-triggered using DAC_Trigger_None\r
- * and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using \r
- * DAC_SetChannel1Data()/DAC_SetChannel2Data.\r
- * \r
- * Digital to Analog conversion can be triggered by:\r
- * 1- External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.\r
- * The used pin (GPIOx_Pin9) must be configured in input mode.\r
- *\r
- * 2- Timers TRGO: TIM2, TIM4, TIM6, TIM7 and TIM9 \r
- * (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)\r
- * The timer TRGO event should be selected using TIM_SelectOutputTrigger()\r
- *\r
- * 3- Software using DAC_Trigger_Software\r
- *\r
- * Each DAC channel integrates an output buffer that can be used to \r
- * reduce the output impedance, and to drive external loads directly\r
- * without having to add an external operational amplifier.\r
- * To enable, the output buffer use \r
- * DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
- * \r
- * Refer to the device datasheet for more details about output impedance\r
- * value with and without output buffer.\r
- *\r
- * Both DAC channels can be used to generate\r
- * 1- Noise wave using DAC_WaveGeneration_Noise\r
- * 2- Triangle wave using DAC_WaveGeneration_Triangle\r
- * \r
- * Wave generation can be disabled using DAC_WaveGeneration_None\r
- *\r
- * The DAC data format can be:\r
- * 1- 8-bit right alignment using DAC_Align_8b_R\r
- * 2- 12-bit left alignment using DAC_Align_12b_L\r
- * 3- 12-bit right alignment using DAC_Align_12b_R\r
- *\r
- * The analog output voltage on each DAC channel pin is determined\r
- * by the following equation: DAC_OUTx = VREF+ * DOR / 4095\r
- * with DOR is the Data Output Register\r
- * VEF+ is the input voltage reference (refer to the device datasheet)\r
- * e.g. To set DAC_OUT1 to 0.7V, use\r
- * DAC_SetChannel1Data(DAC_Align_12b_R, 868);\r
- * Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V\r
- *\r
- * A DMA1 request can be generated when an external trigger (but not\r
- * a software trigger) occurs if DMA1 requests are enabled using\r
- * DAC_DMACmd()\r
- * DMA1 requests are mapped as following:\r
- * 1- DAC channel1 is mapped on DMA1 channel3 which must be already \r
- * configured\r
- * 2- DAC channel2 is mapped on DMA1 channel4 which must be already \r
- * configured\r
- *\r
- * =================================================================== \r
- * How to use this driver \r
- * =================================================================== \r
- * - DAC APB clock must be enabled to get write access to DAC\r
- * registers using\r
- * RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)\r
- * - Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.\r
- * - Configure the DAC channel using DAC_Init()\r
- * - Enable the DAC channel using DAC_Cmd()\r
- * \r
- * @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_dac.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup DAC \r
- * @brief DAC driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* CR register Mask */\r
-#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)\r
-\r
-/* DAC Dual Channels SWTRIG masks */\r
-#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)\r
-#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)\r
-\r
-/* DHR registers offsets */\r
-#define DHR12R1_OFFSET ((uint32_t)0x00000008)\r
-#define DHR12R2_OFFSET ((uint32_t)0x00000014)\r
-#define DHR12RD_OFFSET ((uint32_t)0x00000020)\r
-\r
-/* DOR register offset */\r
-#define DOR_OFFSET ((uint32_t)0x0000002C)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup DAC_Private_Functions\r
- * @{\r
- */ \r
-\r
-/** @defgroup DAC_Group1 DAC channels configuration\r
- * @brief DAC channels configuration: trigger, output buffer, data format \r
- *\r
-@verbatim \r
- ===============================================================================\r
- DAC channels configuration: trigger, output buffer, data format\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the DAC peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void DAC_DeInit(void)\r
-{\r
- /* Enable DAC reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);\r
- /* Release DAC from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Initializes the DAC peripheral according to the specified \r
- * parameters in the DAC_InitStruct.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that\r
- * contains the configuration information for the specified DAC channel.\r
- * DAC_Trigger selects the trigger source: EXTI Line 9, TIM2, TIM4....\r
- * DAC_WaveGeneration selects the waveform to be generated: noise, triangle\r
- * DAC_LFSRUnmask_TriangleAmplitude \r
- * defines the LFSR when noise waveform is selected by DAC_WaveGeneration\r
- * or defines the amplitude of the triangle waveform when it is \r
- * selected by DAC_WaveGeneration\r
- * DAC_OutputBuffer enables/disables the output buffer on DAC_OUTx\r
- * @retval None\r
- */\r
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)\r
-{\r
- uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
-\r
- /* Check the DAC parameters */\r
- assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));\r
- assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));\r
- assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));\r
- assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));\r
-\r
-/*---------------------------- DAC CR Configuration --------------------------*/\r
- /* Get the DAC CR value */\r
- tmpreg1 = DAC->CR;\r
- /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */\r
- tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);\r
- /* Configure for the selected DAC channel: buffer output, trigger, wave generation,\r
- mask/amplitude for wave generation */\r
- /* Set TSELx and TENx bits according to DAC_Trigger value */\r
- /* Set WAVEx bits according to DAC_WaveGeneration value */\r
- /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ \r
- /* Set BOFFx bit according to DAC_OutputBuffer value */ \r
- tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |\r
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);\r
- /* Calculate CR register value depending on DAC_Channel */\r
- tmpreg1 |= tmpreg2 << DAC_Channel;\r
- /* Write to DAC CR */\r
- DAC->CR = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Fills each DAC_InitStruct member with its default value.\r
- * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will \r
- * be initialized.\r
- * @retval None\r
- */\r
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)\r
-{\r
-/*--------------- Reset DAC init structure parameters values -----------------*/\r
- /* Initialize the DAC_Trigger member */\r
- DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;\r
- /* Initialize the DAC_WaveGeneration member */\r
- DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;\r
- /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */\r
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;\r
- /* Initialize the DAC_OutputBuffer member */\r
- DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified DAC channel.\r
- * @param DAC_Channel: The selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param NewState: new state of the DAC channel. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note When the DAC channel is enabled the trigger source can no more\r
- * be modified.\r
- * @retval None\r
- */\r
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DAC channel */\r
- DAC->CR |= (DAC_CR_EN1 << DAC_Channel);\r
- }\r
- else\r
- {\r
- /* Disable the selected DAC channel */\r
- DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the selected DAC channel software trigger.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param NewState: new state of the selected DAC channel software trigger.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable software trigger for the selected DAC channel */\r
- DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);\r
- }\r
- else\r
- {\r
- /* Disable software trigger for the selected DAC channel */\r
- DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables simultaneously the two DAC channels software\r
- * triggers.\r
- * @param NewState: new state of the DAC channels software triggers.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable software trigger for both DAC channels */\r
- DAC->SWTRIGR |= DUAL_SWTRIG_SET;\r
- }\r
- else\r
- {\r
- /* Disable software trigger for both DAC channels */\r
- DAC->SWTRIGR &= DUAL_SWTRIG_RESET;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the selected DAC channel wave generation.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_Wave: Specifies the wave type to enable or disable.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Wave_Noise: noise wave generation\r
- * @arg DAC_Wave_Triangle: triangle wave generation\r
- * @param NewState: new state of the selected DAC channel wave generation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note \r
- * @retval None\r
- */\r
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_WAVE(DAC_Wave)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected wave generation for the selected DAC channel */\r
- DAC->CR |= DAC_Wave << DAC_Channel;\r
- }\r
- else\r
- {\r
- /* Disable the selected wave generation for the selected DAC channel */\r
- DAC->CR &= ~(DAC_Wave << DAC_Channel);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Set the specified data holding register value for DAC channel1.\r
- * @param DAC_Align: Specifies the data alignment for DAC channel1.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Align_8b_R: 8bit right data alignment selected\r
- * @arg DAC_Align_12b_L: 12bit left data alignment selected\r
- * @arg DAC_Align_12b_R: 12bit right data alignment selected\r
- * @param Data : Data to be loaded in the selected data holding register.\r
- * @retval None\r
- */\r
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)\r
-{ \r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DAC_ALIGN(DAC_Align));\r
- assert_param(IS_DAC_DATA(Data));\r
- \r
- tmp = (uint32_t)DAC_BASE; \r
- tmp += DHR12R1_OFFSET + DAC_Align;\r
-\r
- /* Set the DAC channel1 selected data holding register */\r
- *(__IO uint32_t *) tmp = Data;\r
-}\r
-\r
-/**\r
- * @brief Set the specified data holding register value for DAC channel2.\r
- * @param DAC_Align: Specifies the data alignment for DAC channel2.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Align_8b_R: 8bit right data alignment selected\r
- * @arg DAC_Align_12b_L: 12bit left data alignment selected\r
- * @arg DAC_Align_12b_R: 12bit right data alignment selected\r
- * @param Data : Data to be loaded in the selected data holding register.\r
- * @retval None\r
- */\r
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)\r
-{\r
- __IO uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_DAC_ALIGN(DAC_Align));\r
- assert_param(IS_DAC_DATA(Data));\r
- \r
- tmp = (uint32_t)DAC_BASE;\r
- tmp += DHR12R2_OFFSET + DAC_Align;\r
-\r
- /* Set the DAC channel2 selected data holding register */\r
- *(__IO uint32_t *)tmp = Data;\r
-}\r
-\r
-/**\r
- * @brief Set the specified data holding register value for dual channel DAC.\r
- * @param DAC_Align: Specifies the data alignment for dual channel DAC.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Align_8b_R: 8bit right data alignment selected\r
- * @arg DAC_Align_12b_L: 12bit left data alignment selected\r
- * @arg DAC_Align_12b_R: 12bit right data alignment selected\r
- * @param Data2: Data for DAC Channel2 to be loaded in the selected data \r
- * holding register.\r
- * @param Data1: Data for DAC Channel1 to be loaded in the selected data \r
- * holding register.\r
- * @note In dual mode, a unique register access is required to write in both\r
- * DAC channels at the same time.\r
- * @retval None\r
- */\r
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)\r
-{\r
- uint32_t data = 0, tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DAC_ALIGN(DAC_Align));\r
- assert_param(IS_DAC_DATA(Data1));\r
- assert_param(IS_DAC_DATA(Data2));\r
- \r
- /* Calculate and set dual DAC data holding register value */\r
- if (DAC_Align == DAC_Align_8b_R)\r
- {\r
- data = ((uint32_t)Data2 << 8) | Data1; \r
- }\r
- else\r
- {\r
- data = ((uint32_t)Data2 << 16) | Data1;\r
- }\r
- \r
- tmp = (uint32_t)DAC_BASE;\r
- tmp += DHR12RD_OFFSET + DAC_Align;\r
-\r
- /* Set the dual DAC selected data holding register */\r
- *(__IO uint32_t *)tmp = data;\r
-}\r
-\r
-/**\r
- * @brief Returns the last data output value of the selected DAC channel.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @retval The selected DAC channel data output value.\r
- */\r
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)\r
-{\r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- \r
- tmp = (uint32_t) DAC_BASE ;\r
- tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);\r
- \r
- /* Returns the DAC channel data output register value */\r
- return (uint16_t) (*(__IO uint32_t*) tmp);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Group2 DMA management functions\r
- * @brief DMA management functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- DMA management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified DAC channel DMA request.\r
- * When enabled DMA1 is generated when an external trigger (EXTI Line9,\r
- * TIM2, TIM4, TIM6, TIM7 or TIM9 but not a software trigger) occurs\r
- * @param DAC_Channel: the selected DAC channel.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param NewState: new state of the selected DAC channel DMA request.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which \r
- * must be already configured. \r
- * @retval None\r
- */\r
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DAC channel DMA request */\r
- DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);\r
- }\r
- else\r
- {\r
- /* Disable the selected DAC channel DMA request */\r
- DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Group3 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- Interrupts and flags management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified DAC interrupts.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. \r
- * This parameter can be the following values:\r
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask\r
- * @note The DMA underrun occurs when a second external trigger arrives before\r
- * the acknowledgement for the first external trigger is received (first request).\r
- * @param NewState: new state of the specified DAC interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */ \r
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) \r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_DAC_IT(DAC_IT)); \r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DAC interrupts */\r
- DAC->CR |= (DAC_IT << DAC_Channel);\r
- }\r
- else\r
- {\r
- /* Disable the selected DAC interrupts */\r
- DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified DAC flag is set or not.\r
- * @param DAC_Channel: thee selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_FLAG: specifies the flag to check. \r
- * This parameter can be only of the following value:\r
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag\r
- * @note The DMA underrun occurs when a second external trigger arrives before\r
- * the acknowledgement for the first external trigger is received (first request).\r
- * @retval The new state of DAC_FLAG (SET or RESET).\r
- */\r
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_FLAG(DAC_FLAG));\r
-\r
- /* Check the status of the specified DAC flag */\r
- if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)\r
- {\r
- /* DAC_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* DAC_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the DAC_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the DAC channel's pending flags.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_FLAG: specifies the flag to clear. \r
- * This parameter can be of the following value:\r
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag \r
- * @retval None\r
- */\r
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_FLAG(DAC_FLAG));\r
-\r
- /* Clear the selected DAC flags */\r
- DAC->SR = (DAC_FLAG << DAC_Channel);\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified DAC interrupt has occurred or not.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_IT: specifies the DAC interrupt source to check. \r
- * This parameter can be the following values:\r
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask\r
- * @note The DMA underrun occurs when a second external trigger arrives before\r
- * the acknowledgement for the first external trigger is received (first request).\r
- * @retval The new state of DAC_IT (SET or RESET).\r
- */\r
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t enablestatus = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_IT(DAC_IT));\r
-\r
- /* Get the DAC_IT enable bit status */\r
- enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;\r
- \r
- /* Check the status of the specified DAC interrupt */\r
- if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)\r
- {\r
- /* DAC_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* DAC_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the DAC_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the DAC channel\92s interrupt pending bits.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_IT: specifies the DAC interrupt pending bit to clear.\r
- * This parameter can be the following values:\r
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r
- * @retval None\r
- */\r
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_IT(DAC_IT)); \r
-\r
- /* Clear the selected DAC interrupt pending bits */\r
- DAC->SR = (DAC_IT << DAC_Channel);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_dbgmcu.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides all the DBGMCU firmware functions.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_dbgmcu.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup DBGMCU \r
- * @brief DBGMCU driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup DBGMCU_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Returns the device revision identifier.\r
- * @param None\r
- * @retval Device revision identifier\r
- */\r
-uint32_t DBGMCU_GetREVID(void)\r
-{\r
- return(DBGMCU->IDCODE >> 16);\r
-}\r
-\r
-/**\r
- * @brief Returns the device identifier.\r
- * @param None\r
- * @retval Device identifier\r
- */\r
-uint32_t DBGMCU_GetDEVID(void)\r
-{\r
- return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);\r
-}\r
-\r
-/**\r
- * @brief Configures low power mode behavior when the MCU is in Debug mode.\r
- * @param DBGMCU_Periph: specifies the low power mode.\r
- * This parameter can be any combination of the following values:\r
- * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode \r
- * @arg DBGMCU_STOP: Keep debugger connection during STOP mode \r
- * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode \r
- * @param NewState: new state of the specified low power mode in Debug mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- DBGMCU->CR |= DBGMCU_Periph;\r
- }\r
- else\r
- {\r
- DBGMCU->CR &= ~DBGMCU_Periph;\r
- }\r
-}\r
-\r
-\r
-/**\r
- * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.\r
- * @param DBGMCU_Periph: specifies the APB1 peripheral.\r
- * This parameter can be any combination of the following values:\r
- * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted\r
- * @arg DBGMCU_RTC_STOP: RTC Wakeup counter stopped when Core is halted \r
- * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted\r
- * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted\r
- * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is \r
- * halted\r
- * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is \r
- * halted \r
- * @param NewState: new state of the specified APB1 peripheral in Debug mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- DBGMCU->APB1FZ |= DBGMCU_Periph;\r
- }\r
- else\r
- {\r
- DBGMCU->APB1FZ &= ~DBGMCU_Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.\r
- * @param DBGMCU_Periph: specifies the APB2 peripheral.\r
- * This parameter can be any combination of the following values:\r
- * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted \r
- * @param NewState: new state of the specified APB2 peripheral in Debug mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- DBGMCU->APB2FZ |= DBGMCU_Periph;\r
- }\r
- else\r
- {\r
- DBGMCU->APB2FZ &= ~DBGMCU_Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_dma.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Direct Memory Access controller (DMA): \r
- * - Initialization and Configuration\r
- * - Data Counter\r
- * - Interrupts and flags management\r
- * \r
- * @verbatim\r
- * \r
- * =================================================================== \r
- * How to use this driver\r
- * =================================================================== \r
- * 1. Enable The DMA controller clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE)\r
- * function for DMA1 or using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE)\r
- * function for DMA2.\r
- *\r
- * 2. Enable and configure the peripheral to be connected to the DMA channel\r
- * (except for internal SRAM / FLASH memories: no initialization is \r
- * necessary). \r
- * \r
- * 3. For a given Channel, program the Source and Destination addresses, \r
- * the transfer Direction, the Buffer Size, the Peripheral and Memory\r
- * Incrementation mode and Data Size, the Circular or Normal mode, \r
- * the channel transfer Priority and the Memory-to-Memory transfer \r
- * mode (if needed) using the DMA_Init() function.\r
- *\r
- * 4. Enable the NVIC and the corresponding interrupt(s) using the function \r
- * DMA_ITConfig() if you need to use DMA interrupts. \r
- *\r
- * 5. Enable the DMA channel using the DMA_Cmd() function. \r
- * \r
- * 6. Activate the needed channel Request using PPP_DMACmd() function for\r
- * any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)\r
- * The function allowing this operation is provided in each PPP peripheral\r
- * driver (ie. SPI_DMACmd for SPI peripheral). \r
- *\r
- * 7. Optionally, you can configure the number of data to be transferred\r
- * when the channel is disabled (ie. after each Transfer Complete event\r
- * or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().\r
- * And you can get the number of remaining data to be transferred using \r
- * the function DMA_GetCurrDataCounter() at run time (when the DMA channel is\r
- * enabled and running). \r
- * \r
- * 8. To control DMA events you can use one of the following \r
- * two methods:\r
- * a- Check on DMA channel flags using the function DMA_GetFlagStatus(). \r
- * b- Use DMA interrupts through the function DMA_ITConfig() at initialization\r
- * phase and DMA_GetITStatus() function into interrupt routines in\r
- * communication phase. \r
- * After checking on a flag you should clear it using DMA_ClearFlag()\r
- * function. And after checking on an interrupt event you should \r
- * clear it using DMA_ClearITPendingBit() function. \r
- * \r
- * @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_dma.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup DMA \r
- * @brief DMA driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-/* DMA1 Channelx interrupt pending bit masks */\r
-#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))\r
-#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))\r
-#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))\r
-#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))\r
-#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))\r
-#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))\r
-#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))\r
-\r
-/* DMA FLAG mask */\r
-#define FLAG_MASK ((uint32_t)0x10000000)\r
-\r
-/* DMA registers Masks */\r
-#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-\r
-/** @defgroup DMA_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup DMA_Group1 Initialization and Configuration functions\r
- * @brief Initialization and Configuration functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- Initialization and Configuration functions\r
- =============================================================================== \r
-\r
- This subsection provides functions allowing to initialize the DMA channel source\r
- and destination addresses, incrementation and data sizes, transfer direction, \r
- buffer size, circular/normal mode selection, memory-to-memory mode selection \r
- and channel priority value.\r
- \r
- The DMA_Init() function follows the DMA configuration procedures as described in\r
- reference manual (RM0038).\r
-\r
-@endverbatim\r
- * @{\r
- */\r
- \r
-/**\r
- * @brief Deinitializes the DMAy Channelx registers to their default reset\r
- * values.\r
- * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
- * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
- * @retval None\r
- */\r
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
-\r
- /* Disable the selected DMAy Channelx */\r
- DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);\r
-\r
- /* Reset DMAy Channelx control register */\r
- DMAy_Channelx->CCR = 0;\r
- \r
- /* Reset DMAy Channelx remaining bytes register */\r
- DMAy_Channelx->CNDTR = 0;\r
- \r
- /* Reset DMAy Channelx peripheral address register */\r
- DMAy_Channelx->CPAR = 0;\r
- \r
- /* Reset DMAy Channelx memory address register */\r
- DMAy_Channelx->CMAR = 0;\r
- \r
- if (DMAy_Channelx == DMA1_Channel1)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel1 */\r
- DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel2)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel2 */\r
- DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel3)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel3 */\r
- DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel4)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel4 */\r
- DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel5)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel5 */\r
- DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel6)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel6 */\r
- DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;\r
- }\r
- else\r
- {\r
- if (DMAy_Channelx == DMA1_Channel7)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel7 */\r
- DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK; \r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the DMAy Channelx according to the specified\r
- * parameters in the DMA_InitStruct.\r
- * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
- * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that\r
- * contains the configuration information for the specified DMA Channel.\r
- * @retval None\r
- */\r
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));\r
- assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));\r
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));\r
- assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); \r
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));\r
- assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));\r
- assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));\r
- assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));\r
- assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));\r
-\r
-/*--------------------------- DMAy Channelx CCR Configuration -----------------*/\r
- /* Get the DMAy_Channelx CCR value */\r
- tmpreg = DMAy_Channelx->CCR;\r
- /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */\r
- tmpreg &= CCR_CLEAR_MASK;\r
- /* Configure DMAy Channelx: data transfer, data size, priority level and mode */\r
- /* Set DIR bit according to DMA_DIR value */\r
- /* Set CIRC bit according to DMA_Mode value */\r
- /* Set PINC bit according to DMA_PeripheralInc value */\r
- /* Set MINC bit according to DMA_MemoryInc value */\r
- /* Set PSIZE bits according to DMA_PeripheralDataSize value */\r
- /* Set MSIZE bits according to DMA_MemoryDataSize value */\r
- /* Set PL bits according to DMA_Priority value */\r
- /* Set the MEM2MEM bit according to DMA_M2M value */\r
- tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |\r
- DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |\r
- DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |\r
- DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;\r
-\r
- /* Write to DMAy Channelx CCR */\r
- DMAy_Channelx->CCR = tmpreg;\r
-\r
-/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
- /* Write to DMAy Channelx CNDTR */\r
- DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;\r
-\r
-/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/\r
- /* Write to DMAy Channelx CPAR */\r
- DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;\r
-\r
-/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/\r
- /* Write to DMAy Channelx CMAR */\r
- DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;\r
-}\r
-\r
-/**\r
- * @brief Fills each DMA_InitStruct member with its default value.\r
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will\r
- * be initialized.\r
- * @retval None\r
- */\r
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)\r
-{\r
-/*-------------- Reset DMA init structure parameters values ------------------*/\r
- /* Initialize the DMA_PeripheralBaseAddr member */\r
- DMA_InitStruct->DMA_PeripheralBaseAddr = 0;\r
- /* Initialize the DMA_MemoryBaseAddr member */\r
- DMA_InitStruct->DMA_MemoryBaseAddr = 0;\r
- /* Initialize the DMA_DIR member */\r
- DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;\r
- /* Initialize the DMA_BufferSize member */\r
- DMA_InitStruct->DMA_BufferSize = 0;\r
- /* Initialize the DMA_PeripheralInc member */\r
- DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;\r
- /* Initialize the DMA_MemoryInc member */\r
- DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;\r
- /* Initialize the DMA_PeripheralDataSize member */\r
- DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;\r
- /* Initialize the DMA_MemoryDataSize member */\r
- DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;\r
- /* Initialize the DMA_Mode member */\r
- DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;\r
- /* Initialize the DMA_Priority member */\r
- DMA_InitStruct->DMA_Priority = DMA_Priority_Low;\r
- /* Initialize the DMA_M2M member */\r
- DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified DMAy Channelx.\r
- * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
- * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
- * @param NewState: new state of the DMAy Channelx. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DMAy Channelx */\r
- DMAy_Channelx->CCR |= DMA_CCR1_EN;\r
- }\r
- else\r
- {\r
- /* Disable the selected DMAy Channelx */\r
- DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Group2 Data Counter functions\r
- * @brief Data Counter functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Data Counter functions\r
- =============================================================================== \r
-\r
- This subsection provides function allowing to configure and read the buffer size\r
- (number of data to be transferred). \r
-\r
- The DMA data counter can be written only when the DMA channel is disabled \r
- (ie. after transfer complete event).\r
-\r
- The following function can be used to write the Channel data counter value:\r
- - void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);\r
-\r
-@note It is advised to use this function rather than DMA_Init() in situations where\r
- only the Data buffer needs to be reloaded.\r
-\r
- The DMA data counter can be read to indicate the number of remaining transfers for\r
- the relative DMA channel. This counter is decremented at the end of each data \r
- transfer and when the transfer is complete: \r
- - If Normal mode is selected: the counter is set to 0.\r
- - If Circular mode is selected: the counter is reloaded with the initial value\r
- (configured before enabling the DMA channel)\r
- \r
- The following function can be used to read the Channel data counter value:\r
- - uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Sets the number of data units in the current DMAy Channelx transfer.\r
- * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
- * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
- * @param DataNumber: The number of data units in the current DMAy Channelx\r
- * transfer. \r
- * @note This function can only be used when the DMAy_Channelx is disabled. \r
- * @retval None.\r
- */\r
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- \r
-/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
- /* Write to DMAy Channelx CNDTR */\r
- DMAy_Channelx->CNDTR = DataNumber; \r
-}\r
-\r
-/**\r
- * @brief Returns the number of remaining data units in the current\r
- * DMAy Channelx transfer.\r
- * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
- * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
- * @retval The number of remaining data units in the current DMAy Channelx\r
- * transfer.\r
- */\r
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- /* Return the number of remaining data units for DMAy Channelx */\r
- return ((uint16_t)(DMAy_Channelx->CNDTR));\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Group3 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Interrupts and flags management functions\r
- =============================================================================== \r
-\r
- This subsection provides functions allowing to configure the DMA Interrupts \r
- sources and check or clear the flags or pending bits status.\r
- The user should identify which mode will be used in his application to manage the\r
- DMA controller events: Polling mode or Interrupt mode. \r
- \r
- Polling Mode\r
- =============\r
- Each DMA channel can be managed through 4 event Flags:\r
- (y : DMA Controller number \r
- x : DMA channel number )\r
- 1. DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred\r
- 2. DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occured\r
- 3. DMAy_FLAG_TEx : to indicate that a Transfer Error occured.\r
- 4. DMAy_FLAG_GLx : to indicate that at least one of the events described \r
- above occured. \r
-\r
-@note Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the \r
- same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).\r
-\r
- In this Mode it is advised to use the following functions:\r
- - FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);\r
- - void DMA_ClearFlag(uint32_t DMA_FLAG);\r
-\r
- Interrupt Mode\r
- ===============\r
- Each DMA channel can be managed through 4 Interrupts:\r
-\r
- Interrupt Source\r
- ----------------\r
- 1. DMA_IT_TC: specifies the interrupt source for the Transfer Complete event. \r
- 2. DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete event.\r
- 3. DMA_IT_TE : specifies the interrupt source for the transfer errors event.\r
- 4. DMA_IT_GL : to indicate that at least one of the interrupts described \r
- above occurred. \r
-\r
-@note Clearing DMA_IT_GL interrupt results in clearing all other interrupts of the \r
- same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).\r
- \r
- In this Mode it is advised to use the following functions:\r
- - void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);\r
- - ITStatus DMA_GetITStatus(uint32_t DMA_IT);\r
- - void DMA_ClearITPendingBit(uint32_t DMA_IT);\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified DMAy Channelx interrupts.\r
- * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
- * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
- * @param DMA_IT: specifies the DMA interrupts sources to be enabled\r
- * or disabled. \r
- * This parameter can be any combination of the following values:\r
- * @arg DMA_IT_TC: Transfer complete interrupt mask\r
- * @arg DMA_IT_HT: Half transfer interrupt mask\r
- * @arg DMA_IT_TE: Transfer error interrupt mask\r
- * @param NewState: new state of the specified DMA interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- assert_param(IS_DMA_CONFIG_IT(DMA_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DMA interrupts */\r
- DMAy_Channelx->CCR |= DMA_IT;\r
- }\r
- else\r
- {\r
- /* Disable the selected DMA interrupts */\r
- DMAy_Channelx->CCR &= ~DMA_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified DMAy Channelx flag is set or not.\r
- * @param DMA_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
- * \r
- * @note\r
- * The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags \r
- * relative to the same channel is set (Transfer Complete, Half-transfer \r
- * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or \r
- * DMAy_FLAG_TEx). \r
- * \r
- * @retval The new state of DMA_FLAG (SET or RESET).\r
- */\r
-FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_DMA_GET_FLAG(DMA_FLAG));\r
-\r
- /* Calculate the used DMA */\r
- if ((DMA_FLAG & FLAG_MASK) == (uint32_t)RESET)\r
- {\r
- /* Get DMA1 ISR register value */\r
- tmpreg = DMA1->ISR ;\r
- }\r
-\r
- /* Check the status of the specified DMA flag */\r
- if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)\r
- {\r
- /* DMA_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* DMA_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- \r
- /* Return the DMA_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the DMAy Channelx's pending flags.\r
- * @param DMA_FLAG: specifies the flag to clear.\r
- * This parameter can be any combination (for the same DMA) of the following values:\r
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
- * \r
- * @note\r
- * Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags\r
- * relative to the same channel (Transfer Complete, Half-transfer Complete and \r
- * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). \r
- * \r
- * @retval None\r
- */\r
-void DMA_ClearFlag(uint32_t DMA_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));\r
-\r
- if ((DMA_FLAG & FLAG_MASK) == (uint32_t)RESET)\r
- {\r
- /* Clear the selected DMA flags */\r
- DMA1->IFCR = DMA_FLAG;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.\r
- * @param DMA_IT: specifies the DMA interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
- * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
- * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
- * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
- * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
- * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
- * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
- * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
- * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
- * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
- * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
- * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
- * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
- * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
- * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
- * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
- * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
- * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
- * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
- * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
- * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
- * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
- * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
- * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
- * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
- * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
- * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
- * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
- * \r
- * @note\r
- * The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other \r
- * interrupts relative to the same channel is set (Transfer Complete, \r
- * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, \r
- * DMAy_IT_HTx or DMAy_IT_TEx). \r
- * \r
- * @retval The new state of DMA_IT (SET or RESET).\r
- */\r
-ITStatus DMA_GetITStatus(uint32_t DMA_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DMA_GET_IT(DMA_IT));\r
-\r
- /* Calculate the used DMA */\r
- if ((DMA_IT & FLAG_MASK) == (uint32_t)RESET)\r
- {\r
- /* Get DMA1 ISR register value */\r
- tmpreg = DMA1->ISR ;\r
- }\r
-\r
- /* Check the status of the specified DMA interrupt */\r
- if ((tmpreg & DMA_IT) != (uint32_t)RESET)\r
- {\r
- /* DMA_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* DMA_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the DMA_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the DMAy Channelx\92s interrupt pending bits.\r
- * @param DMA_IT: specifies the DMA interrupt pending bit to clear.\r
- * This parameter can be any combination (for the same DMA) of the following values:\r
- * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
- * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
- * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
- * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
- * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
- * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
- * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
- * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
- * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
- * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
- * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
- * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
- * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
- * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
- * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
- * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
- * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
- * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
- * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
- * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
- * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
- * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
- * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
- * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
- * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
- * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
- * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
- * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
- * \r
- * @note\r
- * Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other \r
- * interrupts relative to the same channel (Transfer Complete, Half-transfer \r
- * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and \r
- * DMAy_IT_TEx). \r
- * \r
- * @retval None\r
- */\r
-void DMA_ClearITPendingBit(uint32_t DMA_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_CLEAR_IT(DMA_IT));\r
-\r
- /* Calculate the used DMA */\r
- if ((DMA_IT & FLAG_MASK) == (uint32_t)RESET)\r
- {\r
- /* Clear the selected DMA interrupt pending bits */\r
- DMA1->IFCR = DMA_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_exti.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the EXTI peripheral: \r
- * - Initialization and Configuration\r
- * - Interrupts and flags management\r
- *\r
- * @verbatim \r
- * \r
- * ===================================================================\r
- * EXTI features\r
- * ===================================================================\r
- * \r
- * External interrupt/event lines are mapped as following:\r
- * 1- All available GPIO pins are connected to the 16 external \r
- * interrupt/event lines from EXTI0 to EXTI15.\r
- * 2- EXTI line 16 is connected to the PVD output\r
- * 3- EXTI line 17 is connected to the RTC Alarm event\r
- * 4- EXTI line 18 is connected to the USB Device FS wakeup event\r
- * 5- EXTI line 19 is connected to the RTC Tamper and TimeStamp events\r
- * 6- EXTI line 20 is connected to the RTC Wakeup event\r
- * 7- EXTI line 21 is connected to the Comparator 1 wakeup event \r
- * 8- EXTI line 22 is connected to the Comparator 2 wakeup event\r
- *\r
- * ===================================================================\r
- * How to use this driver\r
- * =================================================================== \r
- * \r
- * In order to use an I/O pin as an external interrupt source, follow\r
- * steps below:\r
- * 1- Configure the I/O in input mode using GPIO_Init()\r
- * 2- Select the input source pin for the EXTI line using \r
- * SYSCFG_EXTILineConfig()\r
- * 3- Select the mode(interrupt, event) and configure the trigger \r
- * selection (Rising, falling or both) using EXTI_Init()\r
- * 4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()\r
- * \r
- *@note SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx\r
- * registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
- * \r
- * @endverbatim \r
- *\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_exti.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup EXTI \r
- * @brief EXTI driver modules\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup EXTI_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup EXTI_Group1 Initialization and Configuration functions\r
- * @brief Initialization and Configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Initialization and Configuration functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the EXTI peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void EXTI_DeInit(void)\r
-{\r
- EXTI->IMR = 0x00000000;\r
- EXTI->EMR = 0x00000000;\r
- EXTI->RTSR = 0x00000000; \r
- EXTI->FTSR = 0x00000000; \r
- EXTI->PR = 0x007FFFFF;\r
-}\r
-\r
-/**\r
- * @brief Initializes the EXTI peripheral according to the specified\r
- * parameters in the EXTI_InitStruct.\r
- * EXTI_Line specifies the EXTI line (EXTI0....EXTI22) \r
- * EXTI_Mode specifies which EXTI line is used as interrupt or an event\r
- * EXTI_Trigger selects the trigger. When the trigger occurs, interrupt\r
- * pending bit will be set\r
- * EXTI_LineCmd controls (Enable/Disable) the EXTI line\r
- * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure\r
- * that contains the configuration information for the EXTI peripheral.\r
- * @retval None\r
- */\r
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)\r
-{\r
- uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));\r
- assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));\r
- assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); \r
- assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));\r
-\r
- tmp = (uint32_t)EXTI_BASE;\r
- \r
- if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)\r
- {\r
- /* Clear EXTI line configuration */\r
- EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;\r
- EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;\r
- \r
- tmp += EXTI_InitStruct->EXTI_Mode;\r
-\r
- *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
-\r
- /* Clear Rising Falling edge configuration */\r
- EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;\r
- EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;\r
- \r
- /* Select the trigger for the selected external interrupts */\r
- if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)\r
- {\r
- /* Rising Falling edge */\r
- EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;\r
- EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;\r
- }\r
- else\r
- {\r
- tmp = (uint32_t)EXTI_BASE;\r
- tmp += EXTI_InitStruct->EXTI_Trigger;\r
-\r
- *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
- }\r
- }\r
- else\r
- {\r
- tmp += EXTI_InitStruct->EXTI_Mode;\r
-\r
- /* Disable the selected external lines */\r
- *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Fills each EXTI_InitStruct member with its reset value.\r
- * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will\r
- * be initialized.\r
- * @retval None\r
- */\r
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)\r
-{\r
- EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;\r
- EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;\r
- EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;\r
- EXTI_InitStruct->EXTI_LineCmd = DISABLE;\r
-}\r
-\r
-/**\r
- * @brief Generates a Software interrupt on selected EXTI line.\r
- * @param EXTI_Line: specifies the EXTI line on which the software interrupt\r
- * will be generated.\r
- * This parameter can be any combination of EXTI_Linex where x can be (0..22).\r
- * @retval None\r
- */\r
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_EXTI_LINE(EXTI_Line));\r
- \r
- EXTI->SWIER |= EXTI_Line;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup EXTI_Group2 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Interrupts and flags management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Checks whether the specified EXTI line flag is set or not.\r
- * @param EXTI_Line: specifies the EXTI line flag to check.\r
- * This parameter can be:\r
- * @arg EXTI_Linex: External interrupt line x where x(0..22)\r
- * @retval The new state of EXTI_Line (SET or RESET).\r
- */\r
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
- \r
- if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the EXTI\92s line pending flags.\r
- * @param EXTI_Line: specifies the EXTI lines flags to clear.\r
- * This parameter can be any combination of EXTI_Linex where x can be (0..22).\r
- * @retval None\r
- */\r
-void EXTI_ClearFlag(uint32_t EXTI_Line)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_EXTI_LINE(EXTI_Line));\r
- \r
- EXTI->PR = EXTI_Line;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified EXTI line is asserted or not.\r
- * @param EXTI_Line: specifies the EXTI line to check.\r
- * This parameter can be:\r
- * @arg EXTI_Linex: External interrupt line x where x(0..22)\r
- * @retval The new state of EXTI_Line (SET or RESET).\r
- */\r
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t enablestatus = 0;\r
- /* Check the parameters */\r
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
- \r
- enablestatus = EXTI->IMR & EXTI_Line;\r
- if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the EXTI\92s line pending bits.\r
- * @param EXTI_Line: specifies the EXTI lines to clear.\r
- * This parameter can be any combination of EXTI_Linex where x can be (0..22).\r
- * @retval None\r
- */\r
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_EXTI_LINE(EXTI_Line));\r
- \r
- EXTI->PR = EXTI_Line;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_flash.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides all the Flash firmware functions. These functions \r
- * can be executed from Internal FLASH or Internal SRAM memories. \r
- * The functions that should be called from SRAM are defined inside \r
- * the "stm32l1xx_flash_ramfunc.c" file.\r
- * This file provides firmware functions to manage the following \r
- * functionalities of the FLASH peripheral:\r
- * - FLASH Interface configuration\r
- * - FLASH Memory Programming\r
- * - DATA EEPROM Programming\r
- * - Option Bytes Programming\r
- * - Interrupts and flags management\r
- * \r
- * @verbatim\r
- * \r
- * ===================================================================\r
- * How to use this driver\r
- * ===================================================================\r
- * \r
- * This driver provides functions to configure and program the Flash \r
- * memory of all STM32L1xx devices\r
- * These functions are split in 5 groups\r
- * \r
- * 1. FLASH Interface configuration functions: this group includes \r
- * the management of following features:\r
- * - Set the latency\r
- * - Enable/Disable the prefetch buffer\r
- * - Enable/Disable the 64 bit Read Access \r
- * - Enable/Disable the RUN PowerDown mode\r
- * - Enable/Disable the SLEEP PowerDown mode \r
- * \r
- * 2. FLASH Memory Programming functions: this group includes all \r
- * needed functions to erase and program the main memory:\r
- * - Lock and Unlock the Flash interface.\r
- * - Erase function: Erase Page.\r
- * - Program functions: Fast Word and Half Page(should be \r
- * executed from internal SRAM).\r
- * \r
- * 3. DATA EEPROM Programming functions: this group includes all \r
- * needed functions to erase and program the DATA EEPROM memory:\r
- * - Lock and Unlock the DATA EEPROM interface.\r
- * - Erase function: Erase Word, erase Double Word (should be \r
- * executed from internal SRAM).\r
- * - Program functions: Fast Program Byte, Fast Program Half-Word, \r
- * FastProgramWord, Program Byte, Program Half-Word, \r
- * Program Word and Program Double-Word (should be executed \r
- * from internal SRAM).\r
- * \r
- * 4. FLASH Option Bytes Programming functions: this group includes \r
- * all needed functions to:\r
- * - Lock and Unlock the Flash Option bytes. \r
- * - Set/Reset the write protection\r
- * - Set the Read protection Level\r
- * - Set the BOR level\r
- * - Program the user option Bytes \r
- * - Launch the Option Bytes loader\r
- * - Get the Write protection\r
- * - Get the read protection status\r
- * - Get the BOR level\r
- * - Get the user option bytes \r
- * \r
- * 5. FLASH Interrupts and flag management functions: this group \r
- * includes all needed functions to:\r
- * - Enable/Disable the flash interrupt sources\r
- * - Get flags status\r
- * - Clear flags\r
- * - Get Flash operation status\r
- * - Wait for last flash operation \r
- * \r
- * @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_flash.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup FLASH \r
- * @brief FLASH driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
- \r
-/* FLASH Mask */\r
-#define RDPRT_MASK ((uint32_t)0x00000002)\r
-#define WRP01_MASK ((uint32_t)0x0000FFFF)\r
-#define WRP23_MASK ((uint32_t)0xFFFF0000)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
- \r
-/** @defgroup FLASH_Private_Functions\r
- * @{\r
- */ \r
-\r
-/** @defgroup FLASH_Group1 FLASH Interface configuration functions\r
- * @brief FLASH Interface configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- FLASH Interface configuration functions\r
- =============================================================================== \r
-\r
- FLASH_Interface configuration_Functions, includes the following functions:\r
- - void FLASH_SetLatency(uint32_t FLASH_Latency):\r
- To correctly read data from Flash memory, the number of wait states (LATENCY) \r
- must be correctly programmed according to the frequency of the CPU clock \r
- (HCLK) and the supply voltage of the device.\r
- ---------------------------------------------------------------- \r
- | Wait states | HCLK clock frequency (MHz) |\r
- | |------------------------------------------------| \r
- | (Latency) | voltage range | voltage range | \r
- | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |\r
- | |----------------|---------------|---------------| \r
- | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |\r
- |-------------- |----------------|---------------|---------------| \r
- |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |\r
- |---------------|----------------|---------------|---------------| \r
- |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32| \r
- ---------------------------------------------------------------- \r
- \r
- - void FLASH_PrefetchBufferCmd(FunctionalState NewState);\r
- - void FLASH_ReadAccess64Cmd(FunctionalState NewState);\r
- - void FLASH_RUNPowerDownCmd(FunctionalState NewState);\r
- - void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);\r
- - void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);\r
- \r
- Here below the allowed configuration of Latency, 64Bit access and prefetch buffer\r
- -------------------------------------------------------------------------------- \r
- | | ACC64 = 0 | ACC64 = 1 |\r
- | Latency |----------------|---------------|---------------|---------------| \r
- | | PRFTEN = 0 | PRFTEN = 1 | PRFTEN = 0 | PRFTEN = 1 | \r
- |---------------|----------------|---------------|---------------|---------------| \r
- |0WS(1CPU cycle)| YES | NO | YES | YES |\r
- |---------------|----------------|---------------|---------------|---------------| \r
- |1WS(2CPU cycle)| NO | NO | YES | YES | \r
- -------------------------------------------------------------------------------- \r
- All these functions don't need the unlock sequence.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Sets the code latency value.\r
- * @param FLASH_Latency: specifies the FLASH Latency value.\r
- * This parameter can be one of the following values:\r
- * @arg FLASH_Latency_0: FLASH Zero Latency cycle\r
- * @arg FLASH_Latency_1: FLASH One Latency cycle\r
- * @retval None\r
- */\r
-void FLASH_SetLatency(uint32_t FLASH_Latency)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_LATENCY(FLASH_Latency));\r
- \r
- /* Read the ACR register */\r
- tmpreg = FLASH->ACR; \r
- \r
- /* Sets the Latency value */\r
- tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY));\r
- tmpreg |= FLASH_Latency;\r
- \r
- /* Write the ACR register */\r
- FLASH->ACR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Prefetch Buffer.\r
- * @param NewState: new state of the FLASH prefetch buffer.\r
- * This parameter can be: ENABLE or DISABLE. \r
- * @retval None\r
- */\r
-void FLASH_PrefetchBufferCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if(NewState != DISABLE)\r
- {\r
- FLASH->ACR |= FLASH_ACR_PRFTEN;\r
- }\r
- else\r
- {\r
- FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTEN));\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables read access to flash by 64 bits.\r
- * @param NewState: new state of the FLASH read access mode.\r
- * This parameter can be: ENABLE or DISABLE. \r
- * @note - If this bit is set, the Read access 64 bit is used.\r
- * - If this bit is reset, the Read access 32 bit is used.\r
- * @note - This bit cannot be written at the same time as the LATENCY and \r
- * PRFTEN bits. \r
- * - To reset this bit, the LATENCY should be zero wait state and the \r
- * prefetch off.\r
- * @retval None\r
- */\r
-void FLASH_ReadAccess64Cmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if(NewState != DISABLE)\r
- {\r
- FLASH->ACR |= FLASH_ACR_ACC64;\r
- }\r
- else\r
- {\r
- FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_ACC64));\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enable or disable the power down mode during Sleep mode.\r
- * @note This function is used to power down the FLASH when the system is in SLEEP LP mode. \r
- * @param NewState: new state of the power down mode during sleep mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void FLASH_SLEEPPowerDownCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Set the SLEEP_PD bit to put Flash in power down mode during sleep mode */\r
- FLASH->ACR |= FLASH_ACR_SLEEP_PD;\r
- }\r
- else\r
- {\r
- /* Clear the SLEEP_PD bit in to put Flash in idle mode during sleep mode */\r
- FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_SLEEP_PD));\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASH_Group2 FLASH Memory Programming functions\r
- * @brief FLASH Memory Programming functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- FLASH Memory Programming functions\r
- =============================================================================== \r
-\r
- The FLASH Memory Programming functions, includes the following functions:\r
- - void FLASH_Unlock(void);\r
- - void FLASH_Lock(void);\r
- - FLASH_Status FLASH_ErasePage(uint32_t Page_Address);\r
- - FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);\r
- \r
- Any operation of erase or program should follow these steps:\r
-\r
- 1. Call the FLASH_Unlock() function to enable the flash control register and \r
- program memory access\r
-\r
- 2. Call the desired function to erase page or program data\r
-\r
- 3. Call the FLASH_Lock() to disable the flash program memory access \r
- (recommended to protect the FLASH memory against possible unwanted operation)\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Unlocks the FLASH control register and program memory access.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_Unlock(void)\r
-{\r
- if((FLASH->PECR & FLASH_PECR_PRGLOCK) != RESET)\r
- {\r
- /* Unlocking the data memory and FLASH_PECR register access */\r
- DATA_EEPROM_Unlock();\r
- \r
- /* Unlocking the program memory access */\r
- FLASH->PRGKEYR = FLASH_PRGKEY1;\r
- FLASH->PRGKEYR = FLASH_PRGKEY2; \r
- }\r
-}\r
-\r
-/**\r
- * @brief Locks the Program memory access.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_Lock(void)\r
-{\r
- /* Set the PRGLOCK Bit to lock the program memory access */\r
- FLASH->PECR |= FLASH_PECR_PRGLOCK;\r
-}\r
-\r
-/**\r
- * @brief Erases a specified page in program memory.\r
- * @note - To correctly run this function, the FLASH_Unlock() function\r
- * must be called before.\r
- * - Call the FLASH_Lock() to disable the flash memory access \r
- * (recommended to protect the FLASH memory against possible unwanted operation) \r
- * @param Page_Address: The page address in program memory to be erased.\r
- * @note A Page is erased in the Program memory only if the address to load \r
- * is the start address of a page (multiple of 256 bytes). \r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address));\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* If the previous operation is completed, proceed to erase the page */\r
-\r
- /* Set the ERASE bit */\r
- FLASH->PECR |= FLASH_PECR_ERASE;\r
-\r
- /* Set PROG bit */\r
- FLASH->PECR |= FLASH_PECR_PROG;\r
- \r
- /* Write 00000000h to the first word of the program page to erase */\r
- *(__IO uint32_t *)Page_Address = 0x00000000;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
-\r
- /* If the erase operation is completed, disable the ERASE and PROG bits */\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE); \r
- } \r
- /* Return the Erase Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Programs a word at a specified address in program memory.\r
- * @note - To correctly run this function, the FLASH_Unlock() function\r
- * must be called before.\r
- * - Call the FLASH_Lock() to disable the flash memory access \r
- * (recommended to protect the FLASH memory against possible unwanted operation) \r
- * @param Address: specifies the address to be written.\r
- * @param Data: specifies the data to be written.\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* If the previous operation is completed, proceed to program the new word */ \r
- *(__IO uint32_t *)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
- }\r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup FLASH_Group3 DATA EEPROM Programming functions\r
- * @brief DATA EEPROM Programming functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- DATA EEPROM Programming functions\r
- =============================================================================== \r
-\r
- The DATA_EEPROM Programming_Functions, includes the following functions:\r
- - void DATA_EEPROM_Unlock(void);\r
- - void DATA_EEPROM_Lock(void);\r
- - FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);\r
- - FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);\r
- - FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);\r
- - FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);\r
- - FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);\r
- - FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
- - FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);\r
- \r
- Any operation of erase or program should follow these steps:\r
-\r
- 1. Call the DATA_EEPROM_Unlock() function to enable the data EEPROM access\r
- and Flash program erase control register access.\r
-\r
- 2. Call the desired function to erase or program data\r
-\r
- 3. Call the DATA_EEPROM_Lock() to disable the data EEPROM access\r
- and Flash program erase control register access(recommended\r
- to protect the DATA_EEPROM against possible unwanted operation)\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Unlocks the data memory and FLASH_PECR register access.\r
- * @param None\r
- * @retval None\r
- */\r
-void DATA_EEPROM_Unlock(void)\r
-{\r
- if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET)\r
- { \r
- /* Unlocking the Data memory and FLASH_PECR register access*/\r
- FLASH->PEKEYR = FLASH_PEKEY1;\r
- FLASH->PEKEYR = FLASH_PEKEY2;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Locks the Data memory and FLASH_PECR register access.\r
- * @param None\r
- * @retval None\r
- */\r
-void DATA_EEPROM_Lock(void)\r
-{\r
- /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */\r
- FLASH->PECR |= FLASH_PECR_PELOCK;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables DATA EEPROM fixed Time programming (2*Tprog).\r
- * @param NewState: new state of the DATA EEPROM fixed Time programming mode.\r
- * This parameter can be: ENABLE or DISABLE. \r
- * @retval None\r
- */\r
-void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if(NewState != DISABLE)\r
- {\r
- FLASH->PECR |= (uint32_t)FLASH_PECR_FTDW;\r
- }\r
- else\r
- {\r
- FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
- }\r
-}\r
-\r
-/**\r
- * @brief Erase a word in data memory.\r
- * @param Address: specifies the address to be erased\r
- * @note1 - A data memory word is erased in the data memory only if the address \r
- * to load is the start address of a word (multiple of a word).\r
- * @note2 - To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation) \r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* Write "00000000h" to valid address in the data memory" */\r
- *(__IO uint32_t *) Address = 0x00000000;\r
- }\r
- \r
- /* Return the erase status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Write a Byte at a specified address in data memory.\r
- * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation) \r
- * @param Address: specifies the address to be written.\r
- * @param Data: specifies the data to be written.\r
- * @note This function assumes that the is data word is already erased. \r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- uint32_t tmp = 0, tmpaddr = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_DATA_ADDRESS(Address)); \r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* Clear the FTDW bit */\r
- FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
- \r
- if(Data != (uint8_t)0x00) \r
- {\r
- /* If the previous operation is completed, proceed to write the new Data */ \r
- *(__IO uint8_t *)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
- }\r
- else\r
- {\r
- tmpaddr = Address & 0xFFFFFFFC;\r
- tmp = * (__IO uint32_t *) tmpaddr;\r
- tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
- tmp &= ~tmpaddr;\r
- status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
- status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); \r
- } \r
- }\r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Writes a half word at a specified address in data memory.\r
- * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation) \r
- * @param Address: specifies the address to be written.\r
- * @param Data: specifies the data to be written.\r
- * @note This function assumes that the is data word is already erased. \r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- uint32_t tmp = 0, tmpaddr = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* Clear the FTDW bit */\r
- FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
- \r
- if(Data != (uint16_t)0x0000) \r
- {\r
- /* If the previous operation is completed, proceed to write the new data */ \r
- *(__IO uint16_t *)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- }\r
- else\r
- {\r
- if((Address & 0x3) != 0x3)\r
- { \r
- tmpaddr = Address & 0xFFFFFFFC;\r
- tmp = * (__IO uint32_t *) tmpaddr;\r
- tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
- tmp &= ~tmpaddr; \r
- status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
- status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); \r
- }\r
- else\r
- {\r
- DATA_EEPROM_FastProgramByte(Address, 0x00);\r
- DATA_EEPROM_FastProgramByte(Address + 1, 0x00); \r
- } \r
- } \r
- } \r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Programs a word at a specified address in data memory.\r
- * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * - Call the DATA_EEPROM_Lock() to the data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation) \r
- * @param Address: specifies the address to be written.\r
- * @param Data: specifies the data to be written.\r
- * @note This function assumes that the is data word is already erased. \r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* Clear the FTDW bit */\r
- FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
- \r
- /* If the previous operation is completed, proceed to program the new data */ \r
- *(__IO uint32_t *)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
- }\r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Write a Byte at a specified address in data memory without erase.\r
- * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation) \r
- * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before \r
- * this function to configure the Fixed Time Programming. \r
- * @param Address: specifies the address to be written.\r
- * @param Data: specifies the data to be written.\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- uint32_t tmp = 0, tmpaddr = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_DATA_ADDRESS(Address)); \r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- if(Data != (uint8_t) 0x00)\r
- { \r
- *(__IO uint8_t *)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
-\r
- }\r
- else\r
- {\r
- tmpaddr = Address & 0xFFFFFFFC;\r
- tmp = * (__IO uint32_t *) tmpaddr;\r
- tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
- tmp &= ~tmpaddr; \r
- status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
- status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); \r
- } \r
- }\r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Writes a half word at a specified address in data memory without erase.\r
- * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation)\r
- * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before \r
- * this function to configure the Fixed Time Programming \r
- * @param Address: specifies the address to be written.\r
- * @param Data: specifies the data to be written.\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- uint32_t tmp = 0, tmpaddr = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- if(Data != (uint16_t)0x0000)\r
- {\r
- *(__IO uint16_t *)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
- }\r
- else\r
- {\r
- if((Address & 0x3) != 0x3)\r
- {\r
- tmpaddr = Address & 0xFFFFFFFC;\r
- tmp = * (__IO uint32_t *) tmpaddr;\r
- tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
- tmp &= ~tmpaddr; \r
- status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
- status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); \r
- }\r
- else\r
- {\r
- DATA_EEPROM_FastProgramByte(Address, 0x00);\r
- DATA_EEPROM_FastProgramByte(Address + 1, 0x00); \r
- } \r
- } \r
- } \r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Programs a word at a specified address in data memory without erase.\r
- * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation) \r
- * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before \r
- * this function to configure the Fixed Time Programming. \r
- * @param Address: specifies the address to be written.\r
- * @param Data: specifies the data to be written.\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- *(__IO uint32_t *)Address = Data;\r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
- }\r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASH_Group4 Option Bytes Programming functions\r
- * @brief Option Bytes Programming functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Option Bytes Programming functions\r
- =============================================================================== \r
-\r
- The FLASH_Option Bytes Programming_functions, includes the following functions:\r
- - void FLASH_OB_Unlock(void);\r
- - void FLASH_OB_Lock(void);\r
- - void FLASH_OB_Launch(void);\r
- - FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);\r
- - FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);\r
- - FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);\r
- - FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);\r
- - uint8_t FLASH_OB_GetUser(void);\r
- - uint32_t FLASH_OB_GetWRP(void);\r
- - FlagStatus FLASH_OB_GetRDP(void);\r
- - uint8_t FLASH_OB_GetBOR(void);\r
- \r
- Any operation of erase or program should follow these steps:\r
- \r
- 1. Call the FLASH_OB_Unlock() function to enable the Flash option control register access\r
- \r
- 2. Call one or several functions to program the desired option bytes \r
- - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable \r
- the desired sector write protection\r
- - void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level\r
- - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure \r
- the user option Bytes: IWDG, STOP and the Standby.\r
- - void FLASH_OB_BORConfig(uint8_t OB_BOR) => to Set the BOR level \r
- - FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) => to program the OTP bytes \r
- \r
- 3. Once all needed option bytes to be programmed are correctly written, call the\r
- FLASH_OB_Launch(void) function to launch the Option Bytes programming process. \r
- \r
- 4. Call the FLASH_OB_Lock() to disable the Flash option control register access (recommended\r
- to protect the option Bytes against possible unwanted operations)\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Unlocks the option bytes block access.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_OB_Unlock(void)\r
-{\r
- if((FLASH->PECR & FLASH_PECR_OPTLOCK) != RESET)\r
- {\r
- /* Unlocking the data memory and FLASH_PECR register access */\r
- DATA_EEPROM_Unlock();\r
- \r
- /* Unlocking the option bytes block access */\r
- FLASH->OPTKEYR = FLASH_OPTKEY1;\r
- FLASH->OPTKEYR = FLASH_OPTKEY2;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Locks the option bytes block access.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_OB_Lock(void)\r
-{\r
- /* Set the OPTLOCK Bit to lock the option bytes block access */\r
- FLASH->PECR |= FLASH_PECR_OPTLOCK;\r
-}\r
-\r
-/**\r
- * @brief Launch the option byte loading.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_OB_Launch(void)\r
-{\r
- /* Set the OBL_Launch bit to lauch the option byte loading */\r
- FLASH->PECR |= FLASH_PECR_OBL_LAUNCH;\r
-}\r
-\r
-/**\r
- * @brief Write protects the desired pages\r
- * @note - To correctly run this function, the FLASH_OB_Unlock() function\r
- * must be called before.\r
- * - Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
- * (recommended to protect the FLASH memory against possible unwanted operation) \r
- * @param OB_WRP: specifies the address of the pages to be write protected.\r
- * This parameter can be:\r
- * @arg value between OB_WRP_Pages0to15 and OB_WRP_Pages496to511\r
- * @arg OB_WRP_AllPages\r
- * @param NewState: new state of the specified FLASH Pages Wtite protection.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)\r
-{\r
- uint32_t WRP01_Data = 0, WRP23_Data = 0;\r
- \r
- FLASH_Status status = FLASH_COMPLETE;\r
- uint32_t tmp1 = 0, tmp2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_OB_WRP(OB_WRP));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- if (NewState != DISABLE)\r
- {\r
- WRP01_Data = (uint16_t)(((OB_WRP & WRP01_MASK) | OB->WRP01));\r
- WRP23_Data = (uint16_t)((((OB_WRP & WRP23_MASK)>>16 | OB->WRP23))); \r
- tmp1 = (uint32_t)(~(WRP01_Data) << 16)|(WRP01_Data);\r
- OB->WRP01 = tmp1;\r
- \r
- tmp2 = (uint32_t)(~(WRP23_Data) << 16)|(WRP23_Data);\r
- OB->WRP23 = tmp2; \r
- } \r
- \r
- else\r
- {\r
- WRP01_Data = (uint16_t)(~OB_WRP & (WRP01_MASK & OB->WRP01));\r
- WRP23_Data = (uint16_t)((((~OB_WRP & WRP23_MASK)>>16 & OB->WRP23))); \r
-\r
- tmp1 = (uint32_t)((~WRP01_Data) << 16)|(WRP01_Data);\r
- OB->WRP01 = tmp1;\r
- \r
- tmp2 = (uint32_t)((~WRP23_Data) << 16)|(WRP23_Data);\r
- OB->WRP23 = tmp2;\r
- }\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- }\r
-\r
- /* Return the write protection operation Status */\r
- return status; \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the read out protection.\r
- * @note - To correctly run this function, the FLASH_OB_Unlock() function\r
- * must be called before.\r
- * - Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
- * (recommended to protect the FLASH memory against possible unwanted operation) \r
- * @param FLASH_ReadProtection_Level: specifies the read protection level. \r
- * This parameter can be:\r
- * @arg OB_RDP_Level_0: No protection\r
- * @arg OB_RDP_Level_1: Read protection of the memory \r
- * @arg OB_RDP_Level_2: Chip protection\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- uint8_t tmp1 = 0;\r
- uint32_t tmp2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_OB_RDP(OB_RDP));\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- /* calculate the option byte to write */\r
- tmp1 = (uint8_t)(~(OB_RDP ));\r
- tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)OB_RDP));\r
- \r
- if(status == FLASH_COMPLETE)\r
- { \r
- /* program read protection level */\r
- OB->RDP = tmp2;\r
- }\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- /* Return the Read protection operation Status */\r
- return status; \r
-}\r
-\r
-/**\r
- * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.\r
- * @note - To correctly run this function, the FLASH_OB_Unlock() function\r
- * must be called before.\r
- * - Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
- * (recommended to protect the FLASH memory against possible unwanted operation) \r
- * @param OB_IWDG: Selects the WDG mode\r
- * This parameter can be one of the following values:\r
- * @arg OB_IWDG_SW: Software WDG selected\r
- * @arg OB_IWDG_HW: Hardware WDG selected\r
- * @param OB_STOP: Reset event when entering STOP mode.\r
- * This parameter can be one of the following values:\r
- * @arg OB_STOP_NoRST: No reset generated when entering in STOP\r
- * @arg OB_STOP_RST: Reset generated when entering in STOP\r
- * @param OB_STDBY: Reset event when entering Standby mode.\r
- * This parameter can be one of the following values:\r
- * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY\r
- * @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE; \r
- uint32_t tmp = 0, tmp1 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));\r
- assert_param(IS_OB_STOP_SOURCE(OB_STOP));\r
- assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));\r
-\r
- /* Get the User Option byte register */\r
- tmp1 = (FLASH->OBR & 0x000F0000) >> 16;\r
- \r
- /* Calculate the user option byte to write */ \r
- tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << ((uint32_t)0x10));\r
- tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1);\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- { \r
- /* Write the User Option Byte */ \r
- OB->USER = tmp; \r
- }\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- /* Return the Option Byte program Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Programs the FLASH brownout reset threshold level Option Byte.\r
- * @note - To correctly run this function, the FLASH_OB_Unlock() function\r
- * must be called before.\r
- * - Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
- * (recommended to protect the FLASH memory against possible unwanted operation) \r
- * @param OB_BOR: Selects the brownout reset threshold level\r
- * This parameter can be one of the following values:\r
- * @arg OB_BOR_OFF: BOR is disabled at power down, the reset is asserted when the VDD \r
- * power supply reaches the PDR(Power Down Reset) threshold (1.5V)\r
- * @arg OB_BOR_LEVEL1: BOR Reset threshold levels for 1.7V - 1.8V VDD power supply\r
- * @arg OB_BOR_LEVEL2: BOR Reset threshold levels for 1.9V - 2.0V VDD power supply\r
- * @arg OB_BOR_LEVEL3: BOR Reset threshold levels for 2.3V - 2.4V VDD power supply\r
- * @arg OB_BOR_LEVEL4: BOR Reset threshold levels for 2.55V - 2.65V VDD power supply\r
- * @arg OB_BOR_LEVEL5: BOR Reset threshold levels for 2.8V - 2.9V VDD power supply\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- uint32_t tmp = 0, tmp1 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_OB_BOR_LEVEL(OB_BOR));\r
-\r
- /* Get the User Option byte register */\r
- tmp1 = (FLASH->OBR & 0x00700000) >> 16;\r
- \r
- /* Calculate the option byte to write */\r
- tmp = (uint32_t)~(OB_BOR | tmp1)<<16;\r
- tmp |= (OB_BOR | tmp1);\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- { \r
- /* Write the BOR Option Byte */ \r
- OB->USER = tmp; \r
- }\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- /* Return the Option Byte program Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Returns the FLASH User Option Bytes values.\r
- * @param None\r
- * @retval The FLASH User Option Bytes .\r
- */\r
-uint8_t FLASH_OB_GetUser(void)\r
-{\r
- /* Return the User Option Byte */\r
- return (uint8_t)(FLASH->OBR >> 20);\r
-}\r
-\r
-/**\r
- * @brief Returns the FLASH Write Protection Option Bytes value.\r
- * @param None\r
- * @retval The FLASH Write Protection Option Bytes value\r
- */\r
-uint32_t FLASH_OB_GetWRP(void)\r
-{\r
- /* Return the FLASH write protection Register value */\r
- return (uint32_t)(FLASH->WRPR);\r
-}\r
-\r
-/**\r
- * @brief Checks whether the FLASH Read out Protection Status is set or not.\r
- * @param None\r
- * @retval FLASH ReadOut Protection Status(SET or RESET)\r
- */\r
-FlagStatus FLASH_OB_GetRDP(void)\r
-{\r
- FlagStatus readstatus = RESET;\r
- \r
- if ((uint8_t)(FLASH->OBR) != (uint8_t)OB_RDP_Level_0)\r
- {\r
- readstatus = SET;\r
- }\r
- else\r
- {\r
- readstatus = RESET;\r
- }\r
- return readstatus;\r
-}\r
-\r
-/**\r
- * @brief Returns the FLASH BOR level.\r
- * @param None\r
- * @retval The FLASH User Option Bytes .\r
- */\r
-uint8_t FLASH_OB_GetBOR(void)\r
-{\r
- /* Return the BOR level */\r
- return (uint8_t)((FLASH->OBR & (uint32_t)0x000F0000) >> 16);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASH_Group5 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- Interrupts and flags management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified FLASH interrupts.\r
- * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or \r
- * disabled.\r
- * This parameter can be any combination of the following values: \r
- * @arg FLASH_IT_EOP: FLASH end of programming Interrupt\r
- * @arg FLASH_IT_ERR: FLASH Error Interrupt \r
- * @retval None \r
- */\r
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_IT(FLASH_IT)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if(NewState != DISABLE)\r
- {\r
- /* Enable the interrupt sources */\r
- FLASH->PECR |= FLASH_IT;\r
- }\r
- else\r
- {\r
- /* Disable the interrupt sources */\r
- FLASH->PECR &= ~(uint32_t)FLASH_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified FLASH flag is set or not.\r
- * @param FLASH_FLAG: specifies the FLASH flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag \r
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag\r
- * @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode\r
- * @arg FLASH_FLAG_ENDHV: FLASH End of high voltage flag\r
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \r
- * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag\r
- * @arg FLASH_FLAG_SIZERR: FLASH size error flag \r
- * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag \r
- * @retval The new state of FLASH_FLAG (SET or RESET).\r
- */\r
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));\r
-\r
- if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- /* Return the new state of FLASH_FLAG (SET or RESET) */\r
- return bitstatus; \r
-}\r
-\r
-/**\r
- * @brief Clears the FLASH\92s pending flags.\r
- * @param FLASH_FLAG: specifies the FLASH flags to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag\r
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \r
- * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag \r
- * @arg FLASH_FLAG_SIZERR: FLASH size error flag \r
- * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag \r
- * @retval None\r
- */\r
-void FLASH_ClearFlag(uint32_t FLASH_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));\r
- \r
- /* Clear the flags */\r
- FLASH->SR = FLASH_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Returns the FLASH Status.\r
- * @param None\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.\r
- */\r
-FLASH_Status FLASH_GetStatus(void)\r
-{\r
- FLASH_Status FLASHstatus = FLASH_COMPLETE;\r
- \r
- if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) \r
- {\r
- FLASHstatus = FLASH_BUSY;\r
- }\r
- else \r
- { \r
- if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)\r
- { \r
- FLASHstatus = FLASH_ERROR_WRP;\r
- }\r
- else \r
- {\r
- if((FLASH->SR & (uint32_t)0xFEF0) != (uint32_t)0x00)\r
- {\r
- FLASHstatus = FLASH_ERROR_PROGRAM; \r
- }\r
- else\r
- {\r
- FLASHstatus = FLASH_COMPLETE;\r
- }\r
- }\r
- }\r
- /* Return the FLASH Status */\r
- return FLASHstatus;\r
-}\r
-\r
-\r
-/**\r
- * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur.\r
- * @param Timeout: FLASH programming Timeout\r
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)\r
-{ \r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Check for the FLASH Status */\r
- status = FLASH_GetStatus();\r
- \r
- /* Wait for a FLASH operation to complete or a TIMEOUT to occur */\r
- while((status == FLASH_BUSY) && (Timeout != 0x00))\r
- {\r
- status = FLASH_GetStatus();\r
- Timeout--;\r
- }\r
- \r
- if(Timeout == 0x00 )\r
- {\r
- status = FLASH_TIMEOUT;\r
- }\r
- /* Return the operation status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
- /**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_flash_ramfunc.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides all the Flash firmware functions which should be\r
- * executed from the internal SRAM. This file should be placed in \r
- * internal SRAM. \r
- * Other FLASH memory functions that can be used from the FLASH are \r
- * defined in the "stm32l1xx_flash.c" file. \r
- * @verbatim \r
- * \r
- * ARM Compiler\r
- * ------------\r
- * RAM functions are defined using the toolchain options. \r
- * Functions that are be executed in RAM should reside in a separate\r
- * source module. Using the 'Options for File' dialog you can simply change\r
- * the 'Code / Const' area of a module to a memory space in physical RAM.\r
- * Available memory areas are declared in the 'Target' tab of the \r
- * 'Options for Target' dialog.\r
- * \r
- * ICCARM Compiler\r
- * ---------------\r
- * RAM functions are defined using a specific toolchain keyword "__ramfunc". \r
- * \r
- * GNU Compiler\r
- * ------------\r
- * RAM functions are defined using a specific toolchain attribute\r
- * "__attribute__((section(".data")))".\r
- * \r
- * TASKING Compiler\r
- * ----------------\r
- * RAM functions are defined using a specific toolchain pragma. This \r
- * pragma is defined inside this file. \r
- * \r
- * @endverbatim \r
- *\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_flash.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup FLASH \r
- * @brief FLASH driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-static __RAM_FUNC GetStatus(void);\r
-static __RAM_FUNC WaitForLastOperation(uint32_t Timeout);\r
-\r
-/* Private functions ---------------------------------------------------------*/\r
- \r
-/** @defgroup FLASH_Private_Functions\r
- * @{\r
- */ \r
-\r
-/** @addtogroup FLASH_Group1\r
- *\r
-@verbatim \r
-@endverbatim\r
- * @{\r
- */ \r
-#if defined ( __TASKING__ )\r
-#pragma section_code_init on\r
-#endif\r
-\r
-/**\r
- * @brief Enable or disable the power down mode during RUN mode.\r
- * @note: This function can be used only when the user code is running from Internal SRAM\r
- * @param NewState: new state of the power down mode during RUN mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-__RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Unlock the RUN_PD bit */\r
- FLASH->PDKEYR = FLASH_PDKEY1;\r
- FLASH->PDKEYR = FLASH_PDKEY2;\r
- \r
- /* Set the RUN_PD bit in FLASH_ACR register to put Flash in power down mode */\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_RUN_PD;\r
-\r
- if((FLASH->ACR & FLASH_ACR_RUN_PD) != FLASH_ACR_RUN_PD)\r
- {\r
- status = FLASH_ERROR_PROGRAM;\r
- }\r
- }\r
- else\r
- {\r
- /* Clear the RUN_PD bit in FLASH_ACR register to put Flash in idle mode */\r
- FLASH->ACR &= (uint32_t)(~(uint32_t)FLASH_ACR_RUN_PD);\r
- }\r
-\r
- /* Return the Write Status */\r
- return status; \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup FLASH_Group2\r
- *\r
-@verbatim \r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Programs a half page in program memory.\r
- * @param Address: specifies the address to be written.\r
- * @param pBuffer: pointer to the buffer containing the data to be written to \r
- * the half page.\r
- * @note - To correctly run this function, the FLASH_Unlock() function\r
- * must be called before.\r
- * - Call the FLASH_Lock() to disable the flash memory access \r
- * (recommended to protect the FLASH memory against possible unwanted operation)\r
- * @note Half page write is possible only from SRAM.\r
- * @note If there are more than 32 words to write, after 32 words another \r
- * Half Page programming operation starts and has to be finished.\r
- * @note A half page is written to the program memory only if the first \r
- * address to load is the start address of a half page (multiple of 128 \r
- * bytes) and the 31 remaining words to load are in the same half page.\r
- * @note During the Program memory half page write all read operations are \r
- * forbidden (this includes DMA read operations and debugger read \r
- * operations such as breakpoints, periodic updates, etc.)\r
- * @note If a PGAERR is set during a Program memory half page write, the \r
- * complete write operation is aborted. Software should then reset the \r
- * FPRG and PROG/DATA bits and restart the write operation from the \r
- * beginning. \r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-__RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer)\r
-{\r
- uint32_t count = 0; \r
- \r
- FLASH_Status status = FLASH_COMPLETE;\r
-\r
- /* Wait for last operation to be completed */\r
- status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new \r
- half page */\r
- FLASH->PECR |= FLASH_PECR_FPRG;\r
- FLASH->PECR |= FLASH_PECR_PROG;\r
- \r
- /* Write one half page directly with 32 different words */\r
- while(count < 32)\r
- {\r
- *(__IO uint32_t*) (Address + (4 * count)) = *(pBuffer++);\r
- count ++; \r
- }\r
- /* Wait for last operation to be completed */\r
- status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- /* if the write operation is completed, disable the PROG and FPRG bits */\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);\r
- }\r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup FLASH_Group3\r
- *\r
-@verbatim \r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Erase a double word in data memory.\r
- * @param Address: specifies the address to be erased\r
- * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation) \r
- * @note Data memory double word erase is possible only from SRAM.\r
- * @note A double word is erased to the data memory only if the first address \r
- * to load is the start address of a double word (multiple of 8 bytes) \r
- * @note During the Data memory double word erase, all read operations are \r
- * forbidden (this includes DMA read operations and debugger read \r
- * operations such as breakpoints, periodic updates, etc.) \r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-\r
-__RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Wait for last operation to be completed */\r
- status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* If the previous operation is completed, proceed to erase the next double word */\r
- /* Set the ERASE bit */\r
- FLASH->PECR |= FLASH_PECR_ERASE;\r
-\r
- /* Set DATA bit */\r
- FLASH->PECR |= FLASH_PECR_DATA;\r
- \r
- /* Write 00000000h to the 2 words to erase */\r
- *(__IO uint64_t *)Address = 0x00000000;\r
- \r
- /* Wait for last operation to be completed */\r
- status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- /* If the erase operation is completed, disable the ERASE and DATA bits */\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);\r
- } \r
- /* Return the erase status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Write a double word in data memory without erase.\r
- * @param Address: specifies the address to be written.\r
- * @param Data: specifies the data to be written.\r
- * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation) \r
- * @note Data memory double word write is possible only from SRAM.\r
- * @note A data memory double word is written to the data memory only if the \r
- * first address to load is the start address of a double word (multiple \r
- * of double word). \r
- * @note During the Data memory double word write, all read operations are \r
- * forbidden (this includes DMA read operations and debugger read \r
- * operations such as breakpoints, periodic updates, etc.) \r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */ \r
-__RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Wait for last operation to be completed */\r
- status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* If the previous operation is completed, proceed to program the new data*/\r
- FLASH->PECR |= FLASH_PECR_FPRG;\r
- FLASH->PECR |= FLASH_PECR_DATA;\r
- \r
- /* Write the 2 words */ \r
- *(__IO uint32_t *)Address = (uint32_t) Data;\r
- Address += 4;\r
- *(__IO uint32_t *)Address = (uint32_t) (Data >> 32);\r
- \r
- /* Wait for last operation to be completed */\r
- status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- /* If the write operation is completed, disable the FPRG and DATA bits */\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA); \r
- }\r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @brief Returns the FLASH Status.\r
- * @param None\r
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE\r
- */\r
-static __RAM_FUNC GetStatus(void)\r
-{\r
- FLASH_Status FLASHstatus = FLASH_COMPLETE;\r
- \r
- if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) \r
- {\r
- FLASHstatus = FLASH_BUSY;\r
- }\r
- else \r
- { \r
- if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)\r
- { \r
- FLASHstatus = FLASH_ERROR_WRP;\r
- }\r
- else \r
- {\r
- if((FLASH->SR & (uint32_t)0xFEF0) != (uint32_t)0x00)\r
- {\r
- FLASHstatus = FLASH_ERROR_PROGRAM; \r
- }\r
- else\r
- {\r
- FLASHstatus = FLASH_COMPLETE;\r
- }\r
- }\r
- }\r
- /* Return the FLASH Status */\r
- return FLASHstatus;\r
-}\r
-\r
-/**\r
- * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur.\r
- * @param Timeout: FLASH programming Timeout\r
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or \r
- * FLASH_TIMEOUT.\r
- */\r
-static __RAM_FUNC WaitForLastOperation(uint32_t Timeout)\r
-{ \r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Check for the FLASH Status */\r
- status = GetStatus();\r
- \r
- /* Wait for a FLASH operation to complete or a TIMEOUT to occur */\r
- while((status == FLASH_BUSY) && (Timeout != 0x00))\r
- {\r
- status = GetStatus();\r
- Timeout--;\r
- }\r
- \r
- if(Timeout == 0x00 )\r
- {\r
- status = FLASH_TIMEOUT;\r
- }\r
- /* Return the operation status */\r
- return status;\r
-}\r
-\r
-#if defined ( __TASKING__ )\r
-#pragma section_code_init restore\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
- \r
- /**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_gpio.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the GPIO peripheral: \r
- * - Initialization and Configuration\r
- * - GPIO Read and Write\r
- * - GPIO Alternate functions configuration\r
- * \r
- * @verbatim\r
- *\r
- * ===================================================================\r
- * How to use this driver\r
- * =================================================================== \r
- * 1. Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()\r
- * \r
- * 2. Configure the GPIO pin(s) using GPIO_Init()\r
- * Four possible configuration are available for each pin:\r
- * - Input: Floating, Pull-up, Pull-down.\r
- * - Output: Push-Pull (Pull-up, Pull-down or no Pull)\r
- * Open Drain (Pull-up, Pull-down or no Pull).\r
- * In output mode, the speed is configurable: Very Low, Low,\r
- * Medium or High.\r
- * - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)\r
- * Open Drain (Pull-up, Pull-down or no Pull).\r
- * - Analog: required mode when a pin is to be used as ADC channel,\r
- * DAC output or comparator input.\r
- * \r
- * 3- Peripherals alternate function:\r
- * - For ADC, DAC and comparators, configure the desired pin in \r
- * analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN\r
- * - For other peripherals (TIM, USART...):\r
- * - Connect the pin to the desired peripherals' Alternate \r
- * Function (AF) using GPIO_PinAFConfig() function\r
- * - Configure the desired pin in alternate function mode using\r
- * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
- * - Select the type, pull-up/pull-down and output speed via \r
- * GPIO_PuPd, GPIO_OType and GPIO_Speed members\r
- * - Call GPIO_Init() function\r
- * \r
- * 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()\r
- * \r
- * 5. To set/reset the level of a pin configured in output mode use\r
- * GPIO_SetBits()/GPIO_ResetBits()\r
- * \r
- * 6. During and just after reset, the alternate functions are not \r
- * active and the GPIO pins are configured in input floating mode\r
- * (except JTAG pins).\r
- *\r
- * 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as \r
- * general-purpose (PC14 and PC15, respectively) when the LSE\r
- * oscillator is off. The LSE has priority over the GPIO function.\r
- *\r
- * 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as \r
- * general-purpose PH0 and PH1, respectively, when the HSE \r
- * oscillator is off. The HSE has priority over the GPIO function.\r
- * \r
- * @endverbatim \r
- *\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_gpio.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup GPIO \r
- * @brief GPIO driver modules\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup GPIO_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup GPIO_Group1 Initialization and Configuration\r
- * @brief Initialization and Configuration\r
- *\r
-@verbatim \r
- ===============================================================================\r
- Initialization and Configuration\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the GPIOx peripheral registers to their default reset \r
- * values.\r
- * By default, The GPIO pins are configured in input floating mode\r
- * (except JTAG pins).\r
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
- * @retval None\r
- */\r
-void GPIO_DeInit(GPIO_TypeDef* GPIOx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
-\r
- if(GPIOx == GPIOA)\r
- {\r
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);\r
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE); \r
- }\r
- else if(GPIOx == GPIOB)\r
- {\r
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);\r
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);\r
- }\r
- else if(GPIOx == GPIOC)\r
- {\r
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);\r
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);\r
- }\r
- else if(GPIOx == GPIOD)\r
- {\r
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);\r
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);\r
- }\r
- else if(GPIOx == GPIOE)\r
- {\r
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);\r
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);\r
- }\r
- else\r
- {\r
- if(GPIOx == GPIOH)\r
- {\r
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, ENABLE);\r
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, DISABLE);\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the GPIOx peripheral according to the specified \r
- * parameters in the GPIO_InitStruct.\r
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
- * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that \r
- * contains the configuration information for the specified GPIO\r
- * peripheral.\r
- * GPIO_Pin: selects the pin to be configured: GPIO_Pin_0 -> GPIO_Pin_15\r
- * GPIO_Mode: selects the mode of the pin: \r
- * - Input mode: GPIO_Mode_IN\r
- * - Output mode: GPIO_Mode_OUT\r
- * - Alternate Function mode: GPIO_Mode_AF\r
- * - Analog mode: GPIO_Mode_AN\r
- * GPIO_Speed: selects the speed of the pin if configured in Output:\r
- * - Very Low: GPIO_Speed_400KHz\r
- * - Low: GPIO_Speed_2MHz\r
- * - Medium: GPIO_Speed_10MHz\r
- * - High: GPIO_Speed_40MHz\r
- * GPIO_OType: selects the Output type (if the selected mode is output):\r
- * - Push-pull: GPIO_OType_PP\r
- * - Open Drain: GPIO_OType_OD\r
- * GPIO_PuPd: configures the Pull-up/Pull-down resistor on the pin:\r
- * - pull-up: GPIO_PuPd_UP\r
- * - pull-down: GPIO_PuPd_DOWN\r
- * - Neither pull-up nor Pull-down: GPIO_PuPd_NOPULL\r
- * @retval None\r
- */\r
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)\r
-{\r
- uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));\r
- assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));\r
- assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));\r
-\r
- /* -------------------------Configure the port pins---------------- */\r
- /*-- GPIO Mode Configuration --*/\r
- for (pinpos = 0x00; pinpos < 0x10; pinpos++)\r
- {\r
- pos = ((uint32_t)0x01) << pinpos;\r
-\r
- /* Get the port pins position */\r
- currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;\r
-\r
- if (currentpin == pos)\r
- {\r
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));\r
-\r
- GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));\r
-\r
- if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))\r
- {\r
- /* Check Speed mode parameters */\r
- assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));\r
-\r
- /* Speed mode configuration */\r
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));\r
- GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));\r
-\r
- /*Check Output mode parameters */\r
- assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));\r
-\r
- /* Output mode configuration */\r
- GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;\r
- GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));\r
- }\r
-\r
- /* Pull-up Pull down resistor configuration */\r
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));\r
- GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Fills each GPIO_InitStruct member with its default value.\r
- * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will \r
- * be initialized.\r
- * @retval None\r
- */\r
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)\r
-{\r
- /* Reset GPIO init structure parameters values */\r
- GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;\r
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;\r
- GPIO_InitStruct->GPIO_Speed = GPIO_Speed_400KHz;\r
- GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;\r
- GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;\r
-}\r
-\r
-/**\r
- * @brief Locks GPIO Pins configuration registers.\r
- * The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,\r
- * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\r
- * The configuration of the locked GPIO pins can no longer be modified\r
- * until the next reset.\r
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
- * @param GPIO_Pin: specifies the port bit to be written.\r
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
- * @retval None\r
- */\r
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
-{\r
- uint32_t tmp = 0x00010000;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- assert_param(IS_GPIO_PIN(GPIO_Pin));\r
- \r
- tmp |= GPIO_Pin;\r
- /* Set LCKK bit */\r
- GPIOx->LCKR = tmp;\r
- /* Reset LCKK bit */\r
- GPIOx->LCKR = GPIO_Pin;\r
- /* Set LCKK bit */\r
- GPIOx->LCKR = tmp;\r
- /* Read LCKK bit*/\r
- tmp = GPIOx->LCKR;\r
- /* Read LCKK bit*/\r
- tmp = GPIOx->LCKR;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_Group2 GPIO Read and Write\r
- * @brief GPIO Read and Write\r
- *\r
-@verbatim \r
- ===============================================================================\r
- GPIO Read and Write\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Reads the specified input port pin.\r
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
- * @param GPIO_Pin: specifies the port bit to read.\r
- * This parameter can be GPIO_Pin_x where x can be (0..15).\r
- * @retval The input port pin value.\r
- */\r
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
-{\r
- uint8_t bitstatus = 0x00;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
-\r
- if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
- {\r
- bitstatus = (uint8_t)Bit_SET;\r
- }\r
- else\r
- {\r
- bitstatus = (uint8_t)Bit_RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Reads the specified GPIO input data port.\r
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
- * @retval GPIO input data port value.\r
- */\r
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- \r
- return ((uint16_t)GPIOx->IDR);\r
-}\r
-\r
-/**\r
- * @brief Reads the specified output data port bit.\r
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
- * @param GPIO_Pin: Specifies the port bit to read.\r
- * This parameter can be GPIO_Pin_x where x can be (0..15).\r
- * @retval The output port pin value.\r
- */\r
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
-{\r
- uint8_t bitstatus = 0x00;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
- \r
- if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
- {\r
- bitstatus = (uint8_t)Bit_SET;\r
- }\r
- else\r
- {\r
- bitstatus = (uint8_t)Bit_RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Reads the specified GPIO output data port.\r
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
- * @retval GPIO output data port value.\r
- */\r
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- \r
- return ((uint16_t)GPIOx->ODR);\r
-}\r
-\r
-/**\r
- * @brief Sets the selected data port bits.\r
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
- * @param GPIO_Pin: specifies the port bits to be written.\r
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
- * @note This functions uses GPIOx_BSRR register to allow atomic read/modify \r
- * accesses. In this way, there is no risk of an IRQ occurring between\r
- * the read and the modify access.\r
- * @retval None\r
- */\r
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- assert_param(IS_GPIO_PIN(GPIO_Pin));\r
- \r
- GPIOx->BSRRL = GPIO_Pin;\r
-}\r
-\r
-/**\r
- * @brief Clears the selected data port bits.\r
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
- * @param GPIO_Pin: specifies the port bits to be written.\r
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
- * @note This functions uses GPIOx_BSRR register to allow atomic read/modify \r
- * accesses. In this way, there is no risk of an IRQ occurring between\r
- * the read and the modify access.\r
- * @retval None\r
- */\r
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- assert_param(IS_GPIO_PIN(GPIO_Pin));\r
- \r
- GPIOx->BSRRH = GPIO_Pin;\r
-}\r
-\r
-/**\r
- * @brief Sets or clears the selected data port bit.\r
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
- * @param GPIO_Pin: specifies the port bit to be written.\r
- * This parameter can be one of GPIO_Pin_x where x can be (0..15).\r
- * @param BitVal: specifies the value to be written to the selected bit.\r
- * This parameter can be one of the BitAction enum values:\r
- * @arg Bit_RESET: to clear the port pin\r
- * @arg Bit_SET: to set the port pin\r
- * @retval None\r
- */\r
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
- assert_param(IS_GPIO_BIT_ACTION(BitVal));\r
- \r
- if (BitVal != Bit_RESET)\r
- {\r
- GPIOx->BSRRL = GPIO_Pin;\r
- }\r
- else\r
- {\r
- GPIOx->BSRRH = GPIO_Pin ;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Writes data to the specified GPIO data port.\r
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
- * @param PortVal: specifies the value to be written to the port output data \r
- * register.\r
- * @retval None\r
- */\r
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- \r
- GPIOx->ODR = PortVal;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions\r
- * @brief GPIO Alternate functions configuration functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- GPIO Alternate functions configuration functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Changes the mapping of the specified pin.\r
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
- * @param GPIO_PinSource: specifies the pin for the Alternate function.\r
- * This parameter can be GPIO_PinSourcex where x can be (0..15).\r
- * @param GPIO_AFSelection: selects the pin to used as Alternat function.\r
- * This parameter can be one of the following values:\r
- * @arg GPIO_AF_RTC_50Hz: RTC 50/60 Hz synchronization\r
- * @arg GPIO_AF_MCO: Microcontroller clock output\r
- * @arg GPIO_AF_RTC_AF1: Time stamp, Tamper, Alarm A out, Alarm B out,\r
- * 512 Hz clock output (with an LSE oscillator of 32.768 kHz)\r
- * @arg GPIO_AF_WKUP: wakeup\r
- * @arg GPIO_AF_SWJ: SWJ (SW and JTAG)\r
- * @arg GPIO_AF_TRACE\r
- * @arg GPIO_AF_TIM2\r
- * @arg GPIO_AF_TIM3\r
- * @arg GPIO_AF_TIM4\r
- * @arg GPIO_AF_TIM9\r
- * @arg GPIO_AF_TIM10\r
- * @arg GPIO_AF_TIM11\r
- * @arg GPIO_AF_I2C1\r
- * @arg GPIO_AF_I2C2\r
- * @arg GPIO_AF_SPI1\r
- * @arg GPIO_AF_SPI2\r
- * @arg GPIO_AF_USART1\r
- * @arg GPIO_AF_USART2\r
- * @arg GPIO_AF_USART3\r
- * @arg GPIO_AF_USB\r
- * @arg GPIO_AF_LCD\r
- * @arg GPIO_AF_RI\r
- * @arg GPIO_AF_EVENTOUT: Cortex-M3 EVENTOUT signal\r
- * @note: The pin should already been configured in Alternate Function mode(AF)\r
- * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
- * @note: Please refer to the Alternate function mapping table in the device \r
- * datasheet for the detailed mapping of the system and peripherals\92\r
- * alternate function I/O pins. \r
- * @note: EVENTOUT is not mapped on PH0, PH1 and PH2. \r
- * @retval None\r
- */\r
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)\r
-{\r
- uint32_t temp = 0x00;\r
- uint32_t temp_2 = 0x00;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
- assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
- assert_param(IS_GPIO_AF(GPIO_AF));\r
- \r
- temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;\r
- GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;\r
- temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;\r
- GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_i2c.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Inter-integrated circuit (I2C)\r
- * - Initialization and Configuration\r
- * - Data transfers\r
- * - PEC management\r
- * - DMA transfers management\r
- * - Interrupts, events and flags management \r
- * \r
- * @verbatim\r
- * \r
- * ===================================================================\r
- * How to use this driver\r
- * ===================================================================\r
- * 1. Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)\r
- * function for I2C1 or I2C2.\r
- *\r
- * 2. Enable SDA, SCL and SMBA (when used) GPIO clocks using \r
- * RCC_AHBPeriphClockCmd() function. \r
- *\r
- * 3. Peripherals alternate function: \r
- * - Connect the pin to the desired peripherals' Alternate \r
- * Function (AF) using GPIO_PinAFConfig() function\r
- * - Configure the desired pin in alternate function by:\r
- * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
- * - Select the type, pull-up/pull-down and output speed via \r
- * GPIO_PuPd, GPIO_OType and GPIO_Speed members\r
- * - Call GPIO_Init() function\r
- * \r
- * 4. Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged\r
- * Address using the I2C_Init() function.\r
- *\r
- * 5. Optionally you can enable/configure the following parameters without\r
- * re-initialization (i.e there is no need to call again I2C_Init() function):\r
- * - Enable the acknowledge feature using I2C_AcknowledgeConfig() function\r
- * - Enable the dual addressing mode using I2C_DualAddressCmd() function\r
- * - Enable the general call using the I2C_GeneralCallCmd() function\r
- * - Enable the clock stretching using I2C_StretchClockCmd() function\r
- * - Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()\r
- * function\r
- * - Enable the PEC Calculation using I2C_CalculatePEC() function\r
- * - For SMBus Mode: \r
- * - Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function\r
- * - Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function\r
- *\r
- * 6. Enable the NVIC and the corresponding interrupt using the function \r
- * I2C_ITConfig() if you need to use interrupt mode. \r
- *\r
- * 7. When using the DMA mode \r
- * - Configure the DMA using DMA_Init() function\r
- * - Active the needed channel Request using I2C_DMACmd() or\r
- I2C_DMALastTransferCmd() function\r
- * \r
- * 8. Enable the I2C using the I2C_Cmd() function.\r
- * \r
- * 9. Enable the DMA using the DMA_Cmd() function when using DMA mode in the \r
- * transfers. \r
- *\r
- * @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_i2c.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup I2C \r
- * @brief I2C driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*<! I2C registers Masks */\r
-#define FLAG_MASK ((uint32_t)0x00FFFFFF) /*<! I2C FLAG mask */\r
-#define ITEN_MASK ((uint32_t)0x07000000) /*<! I2C Interrupt Enable mask */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup I2C_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup I2C_Group1 Initialization and Configuration functions\r
- * @brief Initialization and Configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Initialization and Configuration functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the I2Cx peripheral registers to their default reset values.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @retval None\r
- */\r
-void I2C_DeInit(I2C_TypeDef* I2Cx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
-\r
- if (I2Cx == I2C1)\r
- {\r
- /* Enable I2C1 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);\r
- /* Release I2C1 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);\r
- }\r
- else\r
- {\r
- /* Enable I2C2 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);\r
- /* Release I2C2 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the I2Cx peripheral according to the specified \r
- * parameters in the I2C_InitStruct.\r
- * @note To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency \r
- * (I2C peripheral input clock) must be a multiple of 10 MHz. \r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that\r
- * contains the configuration information for the specified I2C peripheral.\r
- * @retval None\r
- */\r
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)\r
-{\r
- uint16_t tmpreg = 0, freqrange = 0;\r
- uint16_t result = 0x04;\r
- uint32_t pclk1 = 8000000;\r
- RCC_ClocksTypeDef rcc_clocks;\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));\r
- assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));\r
- assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));\r
- assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));\r
- assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));\r
- assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));\r
-\r
-/*---------------------------- I2Cx CR2 Configuration ------------------------*/\r
- /* Get the I2Cx CR2 value */\r
- tmpreg = I2Cx->CR2;\r
- /* Clear frequency FREQ[5:0] bits */\r
- tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ);\r
- /* Get pclk1 frequency value */\r
- RCC_GetClocksFreq(&rcc_clocks);\r
- pclk1 = rcc_clocks.PCLK1_Frequency;\r
- /* Set frequency bits depending on pclk1 value */\r
- freqrange = (uint16_t)(pclk1 / 1000000);\r
- tmpreg |= freqrange;\r
- /* Write to I2Cx CR2 */\r
- I2Cx->CR2 = tmpreg;\r
-\r
-/*---------------------------- I2Cx CCR Configuration ------------------------*/\r
- /* Disable the selected I2C peripheral to configure TRISE */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);\r
- /* Reset tmpreg value */\r
- /* Clear F/S, DUTY and CCR[11:0] bits */\r
- tmpreg = 0;\r
-\r
- /* Configure speed in standard mode */\r
- if (I2C_InitStruct->I2C_ClockSpeed <= 100000)\r
- {\r
- /* Standard mode speed calculate */\r
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));\r
- /* Test if CCR value is under 0x4*/\r
- if (result < 0x04)\r
- {\r
- /* Set minimum allowed value */\r
- result = 0x04; \r
- }\r
- /* Set speed value for standard mode */\r
- tmpreg |= result; \r
- /* Set Maximum Rise Time for standard mode */\r
- I2Cx->TRISE = freqrange + 1; \r
- }\r
- /* Configure speed in fast mode */\r
- /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral\r
- input clock) must be a multiple of 10 MHz */\r
- else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/\r
- {\r
- if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)\r
- {\r
- /* Fast mode speed calculate: Tlow/Thigh = 2 */\r
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));\r
- }\r
- else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/\r
- {\r
- /* Fast mode speed calculate: Tlow/Thigh = 16/9 */\r
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));\r
- /* Set DUTY bit */\r
- result |= I2C_DutyCycle_16_9;\r
- }\r
-\r
- /* Test if CCR value is under 0x1*/\r
- if ((result & I2C_CCR_CCR) == 0)\r
- {\r
- /* Set minimum allowed value */\r
- result |= (uint16_t)0x0001; \r
- }\r
- /* Set speed value and set F/S bit for fast mode */\r
- tmpreg |= (uint16_t)(result | I2C_CCR_FS);\r
- /* Set Maximum Rise Time for fast mode */\r
- I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); \r
- }\r
-\r
- /* Write to I2Cx CCR */\r
- I2Cx->CCR = tmpreg;\r
- /* Enable the selected I2C peripheral */\r
- I2Cx->CR1 |= I2C_CR1_PE;\r
-\r
-/*---------------------------- I2Cx CR1 Configuration ------------------------*/\r
- /* Get the I2Cx CR1 value */\r
- tmpreg = I2Cx->CR1;\r
- /* Clear ACK, SMBTYPE and SMBUS bits */\r
- tmpreg &= CR1_CLEAR_MASK;\r
- /* Configure I2Cx: mode and acknowledgement */\r
- /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */\r
- /* Set ACK bit according to I2C_Ack value */\r
- tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);\r
- /* Write to I2Cx CR1 */\r
- I2Cx->CR1 = tmpreg;\r
-\r
-/*---------------------------- I2Cx OAR1 Configuration -----------------------*/\r
- /* Set I2Cx Own Address1 and acknowledged address */\r
- I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);\r
-}\r
-\r
-/**\r
- * @brief Fills each I2C_InitStruct member with its default value.\r
- * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.\r
- * @retval None\r
- */\r
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)\r
-{\r
-/*---------------- Reset I2C init structure parameters values ----------------*/\r
- /* initialize the I2C_ClockSpeed member */\r
- I2C_InitStruct->I2C_ClockSpeed = 5000;\r
- /* Initialize the I2C_Mode member */\r
- I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;\r
- /* Initialize the I2C_DutyCycle member */\r
- I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;\r
- /* Initialize the I2C_OwnAddress1 member */\r
- I2C_InitStruct->I2C_OwnAddress1 = 0;\r
- /* Initialize the I2C_Ack member */\r
- I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;\r
- /* Initialize the I2C_AcknowledgedAddress member */\r
- I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C peripheral.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2Cx peripheral. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C peripheral */\r
- I2Cx->CR1 |= I2C_CR1_PE;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C peripheral */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Generates I2Cx communication START condition.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C START condition generation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Generate a START condition */\r
- I2Cx->CR1 |= I2C_CR1_START;\r
- }\r
- else\r
- {\r
- /* Disable the START condition generation */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Generates I2Cx communication STOP condition.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C STOP condition generation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Generate a STOP condition */\r
- I2Cx->CR1 |= I2C_CR1_STOP;\r
- }\r
- else\r
- {\r
- /* Disable the STOP condition generation */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C acknowledge feature.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C Acknowledgement.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the acknowledgement */\r
- I2Cx->CR1 |= I2C_CR1_ACK;\r
- }\r
- else\r
- {\r
- /* Disable the acknowledgement */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the specified I2C own address2.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param Address: specifies the 7bit I2C own address2.\r
- * @retval None.\r
- */\r
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)\r
-{\r
- uint16_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
-\r
- /* Get the old register value */\r
- tmpreg = I2Cx->OAR2;\r
-\r
- /* Reset I2Cx Own address2 bit [7:1] */\r
- tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2);\r
-\r
- /* Set I2Cx Own address2 */\r
- tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);\r
-\r
- /* Store the new register value */\r
- I2Cx->OAR2 = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C dual addressing mode.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C dual addressing mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable dual addressing mode */\r
- I2Cx->OAR2 |= I2C_OAR2_ENDUAL;\r
- }\r
- else\r
- {\r
- /* Disable dual addressing mode */\r
- I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C general call feature.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C General call.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable generall call */\r
- I2Cx->CR1 |= I2C_CR1_ENGC;\r
- }\r
- else\r
- {\r
- /* Disable generall call */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C software reset.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C software reset.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Peripheral under reset */\r
- I2Cx->CR1 |= I2C_CR1_SWRST;\r
- }\r
- else\r
- {\r
- /* Peripheral not under reset */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Drives the SMBusAlert pin high or low for the specified I2C.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_SMBusAlert: specifies SMBAlert pin level. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low\r
- * @arg I2C_SMBusAlert_High: SMBAlert pin driven high\r
- * @retval None\r
- */\r
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));\r
- if (I2C_SMBusAlert == I2C_SMBusAlert_Low)\r
- {\r
- /* Drive the SMBusAlert pin Low */\r
- I2Cx->CR1 |= I2C_SMBusAlert_Low;\r
- }\r
- else\r
- {\r
- /* Drive the SMBusAlert pin High */\r
- I2Cx->CR1 &= I2C_SMBusAlert_High;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C ARP.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2Cx ARP. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C ARP */\r
- I2Cx->CR1 |= I2C_CR1_ENARP;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C ARP */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C Clock stretching.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2Cx Clock stretching.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState == DISABLE)\r
- {\r
- /* Enable the selected I2C Clock stretching */\r
- I2Cx->CR1 |= I2C_CR1_NOSTRETCH;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C Clock stretching */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the specified I2C fast mode duty cycle.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_DutyCycle: specifies the fast mode duty cycle.\r
- * This parameter can be one of the following values:\r
- * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2\r
- * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9\r
- * @retval None\r
- */\r
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));\r
- if (I2C_DutyCycle != I2C_DutyCycle_16_9)\r
- {\r
- /* I2C fast mode Tlow/Thigh=2 */\r
- I2Cx->CCR &= I2C_DutyCycle_2;\r
- }\r
- else\r
- {\r
- /* I2C fast mode Tlow/Thigh=16/9 */\r
- I2Cx->CCR |= I2C_DutyCycle_16_9;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Transmits the address byte to select the slave device.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param Address: specifies the slave address which will be transmitted\r
- * @param I2C_Direction: specifies whether the I2C device will be a\r
- * Transmitter or a Receiver. This parameter can be one of the following values\r
- * @arg I2C_Direction_Transmitter: Transmitter mode\r
- * @arg I2C_Direction_Receiver: Receiver mode\r
- * @retval None.\r
- */\r
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_DIRECTION(I2C_Direction));\r
- /* Test on the direction to set/reset the read/write bit */\r
- if (I2C_Direction != I2C_Direction_Transmitter)\r
- {\r
- /* Set the address bit0 for read */\r
- Address |= I2C_OAR1_ADD0;\r
- }\r
- else\r
- {\r
- /* Reset the address bit0 for write */\r
- Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0);\r
- }\r
- /* Send the address */\r
- I2Cx->DR = Address;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Group2 Data transfers functions\r
- * @brief Data transfers functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Data transfers functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Sends a data byte through the I2Cx peripheral.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param Data: Byte to be transmitted..\r
- * @retval None\r
- */\r
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- /* Write in the DR register the data to be sent */\r
- I2Cx->DR = Data;\r
-}\r
-\r
-/**\r
- * @brief Returns the most recent received data by the I2Cx peripheral.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @retval The value of the received data.\r
- */\r
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- /* Return the data in the DR register */\r
- return (uint8_t)I2Cx->DR;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Group3 PEC management functions\r
- * @brief PEC management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- PEC management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C PEC transfer.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C PEC transmission.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C PEC transmission */\r
- I2Cx->CR1 |= I2C_CR1_PEC;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C PEC transmission */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the specified I2C PEC position.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_PECPosition: specifies the PEC position. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_PECPosition_Next: indicates that the next byte is PEC\r
- * @arg I2C_PECPosition_Current: indicates that current byte is PEC\r
- * @retval None\r
- */\r
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));\r
- if (I2C_PECPosition == I2C_PECPosition_Next)\r
- {\r
- /* Next byte in shift register is PEC */\r
- I2Cx->CR1 |= I2C_PECPosition_Next;\r
- }\r
- else\r
- {\r
- /* Current byte in shift register is PEC */\r
- I2Cx->CR1 &= I2C_PECPosition_Current;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the PEC value calculation of the transferred bytes.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2Cx PEC value calculation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C PEC calculation */\r
- I2Cx->CR1 |= I2C_CR1_ENPEC;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C PEC calculation */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Returns the PEC value for the specified I2C.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @retval The PEC value.\r
- */\r
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- /* Return the selected I2C PEC value */\r
- return ((I2Cx->SR2) >> 8);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Group4 DMA transfers management functions\r
- * @brief DMA transfers management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- DMA transfers management functions\r
- =============================================================================== \r
- This section provides functions allowing to configure the I2C DMA channels \r
- requests.\r
- \r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C DMA requests.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C DMA transfer.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C DMA requests */\r
- I2Cx->CR2 |= I2C_CR2_DMAEN;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C DMA requests */\r
- I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Specifies that the next DMA transfer is the last one.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C DMA last transfer.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Next DMA transfer is the last transfer */\r
- I2Cx->CR2 |= I2C_CR2_LAST;\r
- }\r
- else\r
- {\r
- /* Next DMA transfer is not the last transfer */\r
- I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Group5 Interrupts events and flags management functions\r
- * @brief Interrupts, events and flags management functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- Interrupts, events and flags management functions\r
- =============================================================================== \r
- This section provides functions allowing to configure the I2C Interrupts \r
- sources and check or clear the flags or pending bits status.\r
- The user should identify which mode will be used in his application to manage \r
- the communication: Polling mode, Interrupt mode or DMA mode. \r
-\r
- ===============================================================================\r
- I2C State Monitoring Functions \r
- =============================================================================== \r
- This I2C driver provides three different ways for I2C state monitoring\r
- depending on the application requirements and constraints:\r
- \r
- \r
- 1. Basic state monitoring (Using I2C_CheckEvent() function)\r
- -----------------------------------------------------------\r
- It compares the status registers (SR1 and SR2) content to a given event\r
- (can be the combination of one or more flags).\r
- It returns SUCCESS if the current status includes the given flags \r
- and returns ERROR if one or more flags are missing in the current status.\r
-\r
- - When to use\r
- - This function is suitable for most applications as well as for startup \r
- activity since the events are fully described in the product reference \r
- manual (RM0038).\r
- - It is also suitable for users who need to define their own events.\r
-\r
- - Limitations\r
- - If an error occurs (ie. error flags are set besides to the monitored \r
- flags), the I2C_CheckEvent() function may return SUCCESS despite \r
- the communication hold or corrupted real state. \r
- In this case, it is advised to use error interrupts to monitor \r
- the error events and handle them in the interrupt IRQ handler.\r
- \r
- @note \r
- For error management, it is advised to use the following functions:\r
- - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
- - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.\r
- Where x is the peripheral instance (I2C1, I2C2 ...)\r
- - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the \r
- I2Cx_ER_IRQHandler() function in order to determine which error occurred.\r
- - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() \r
- and/or I2C_GenerateStop() in order to clear the error flag and source \r
- and return to correct communication status.\r
- \r
- \r
- 2. Advanced state monitoring (Using the function I2C_GetLastEvent())\r
- -------------------------------------------------------------------- \r
- Using the function I2C_GetLastEvent() which returns the image of both status \r
- registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
- by 16 bits and concatenated to Status Register 1).\r
-\r
- - When to use\r
- - This function is suitable for the same applications above but it \r
- allows to overcome the mentioned limitation of I2C_GetFlagStatus() \r
- function.\r
- - The returned value could be compared to events already defined in \r
- the library (stm32l1xx_i2c.h) or to custom values defined by user.\r
- This function is suitable when multiple flags are monitored at the \r
- same time.\r
- - At the opposite of I2C_CheckEvent() function, this function allows \r
- user to choose when an event is accepted (when all events flags are \r
- set and no other flags are set or just when the needed flags are set \r
- like I2C_CheckEvent() function.\r
-\r
- - Limitations\r
- - User may need to define his own events.\r
- - Same remark concerning the error management is applicable for this \r
- function if user decides to check only regular communication flags \r
- (and ignores error flags).\r
- \r
- \r
- 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())\r
- -----------------------------------------------------------------------\r
- \r
- Using the function I2C_GetFlagStatus() which simply returns the status of \r
- one single flag (ie. I2C_FLAG_RXNE ...). \r
-\r
- - When to use\r
- - This function could be used for specific applications or in debug \r
- phase.\r
- - It is suitable when only one flag checking is needed (most I2C \r
- events are monitored through multiple flags).\r
- - Limitations: \r
- - When calling this function, the Status register is accessed. \r
- Some flags are cleared when the status register is accessed. \r
- So checking the status of one Flag, may clear other ones.\r
- - Function may need to be called twice or more in order to monitor \r
- one single event.\r
- \r
- For detailed description of Events, please refer to section I2C_Events in \r
- stm32l1xx_i2c.h file.\r
- \r
-@endverbatim\r
- * @{\r
- */\r
- \r
-/**\r
- * @brief Reads the specified I2C register and returns its value.\r
- * @param I2C_Register: specifies the register to read.\r
- * This parameter can be one of the following values:\r
- * @arg I2C_Register_CR1: CR1 register.\r
- * @arg I2C_Register_CR2: CR2 register.\r
- * @arg I2C_Register_OAR1: OAR1 register.\r
- * @arg I2C_Register_OAR2: OAR2 register.\r
- * @arg I2C_Register_DR: DR register.\r
- * @arg I2C_Register_SR1: SR1 register.\r
- * @arg I2C_Register_SR2: SR2 register.\r
- * @arg I2C_Register_CCR: CCR register.\r
- * @arg I2C_Register_TRISE: TRISE register.\r
- * @retval The value of the read register.\r
- */\r
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)\r
-{\r
- __IO uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_REGISTER(I2C_Register));\r
-\r
- tmp = (uint32_t) I2Cx;\r
- tmp += I2C_Register;\r
-\r
- /* Return the selected register value */\r
- return (*(__IO uint16_t *) tmp);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C interrupts.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. \r
- * This parameter can be any combination of the following values:\r
- * @arg I2C_IT_BUF: Buffer interrupt mask\r
- * @arg I2C_IT_EVT: Event interrupt mask\r
- * @arg I2C_IT_ERR: Error interrupt mask\r
- * @param NewState: new state of the specified I2C interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_I2C_CONFIG_IT(I2C_IT));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C interrupts */\r
- I2Cx->CR2 |= I2C_IT;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C interrupts */\r
- I2Cx->CR2 &= (uint16_t)~I2C_IT;\r
- }\r
-}\r
-\r
-/**\r
- ===============================================================================\r
- 1. Basic state monitoring \r
- =============================================================================== \r
- */\r
-\r
-/**\r
- * @brief Checks whether the last I2Cx Event is equal to the one passed\r
- * as parameter.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_EVENT: specifies the event to be checked. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1\r
- * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1\r
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1\r
- * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1\r
- * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1\r
- * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2\r
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2\r
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2\r
- * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3\r
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3\r
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3\r
- * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2\r
- * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4\r
- * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5\r
- * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 \r
- * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6\r
- * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7\r
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8\r
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2\r
- * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9\r
- * \r
- * @note: For detailed description of Events, please refer to section \r
- * I2C_Events in stm32l1xx_i2c.h file.\r
- * \r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: Last event is equal to the I2C_EVENT\r
- * - ERROR: Last event is different from the I2C_EVENT\r
- */\r
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)\r
-{\r
- uint32_t lastevent = 0;\r
- uint32_t flag1 = 0, flag2 = 0;\r
- ErrorStatus status = ERROR;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_EVENT(I2C_EVENT));\r
-\r
- /* Read the I2Cx status register */\r
- flag1 = I2Cx->SR1;\r
- flag2 = I2Cx->SR2;\r
- flag2 = flag2 << 16;\r
-\r
- /* Get the last event value from I2C status register */\r
- lastevent = (flag1 | flag2) & FLAG_MASK;\r
-\r
- /* Check whether the last event contains the I2C_EVENT */\r
- if ((lastevent & I2C_EVENT) == I2C_EVENT)\r
- {\r
- /* SUCCESS: last event is equal to I2C_EVENT */\r
- status = SUCCESS;\r
- }\r
- else\r
- {\r
- /* ERROR: last event is different from I2C_EVENT */\r
- status = ERROR;\r
- }\r
- /* Return status */\r
- return status;\r
-}\r
-\r
-/**\r
- ===============================================================================\r
- 2. Advanced state monitoring \r
- =============================================================================== \r
- */\r
-\r
-/**\r
- * @brief Returns the last I2Cx Event.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * \r
- * @note: For detailed description of Events, please refer to section \r
- * I2C_Events in stm32l1xx_i2c.h file.\r
- * \r
- * @retval The last event\r
- */\r
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)\r
-{\r
- uint32_t lastevent = 0;\r
- uint32_t flag1 = 0, flag2 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
-\r
- /* Read the I2Cx status register */\r
- flag1 = I2Cx->SR1;\r
- flag2 = I2Cx->SR2;\r
- flag2 = flag2 << 16;\r
-\r
- /* Get the last event value from I2C status register */\r
- lastevent = (flag1 | flag2) & FLAG_MASK;\r
-\r
- /* Return status */\r
- return lastevent;\r
-}\r
-\r
-/**\r
- ===============================================================================\r
- 3. Flag-based state monitoring \r
- =============================================================================== \r
- */\r
-\r
-/**\r
- * @brief Checks whether the specified I2C flag is set or not.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_FLAG: specifies the flag to check. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)\r
- * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)\r
- * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)\r
- * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)\r
- * @arg I2C_FLAG_TRA: Transmitter/Receiver flag\r
- * @arg I2C_FLAG_BUSY: Bus busy flag\r
- * @arg I2C_FLAG_MSL: Master/Slave flag\r
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
- * @arg I2C_FLAG_PECERR: PEC error in reception flag\r
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
- * @arg I2C_FLAG_AF: Acknowledge failure flag\r
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
- * @arg I2C_FLAG_BERR: Bus error flag\r
- * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)\r
- * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag\r
- * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)\r
- * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)\r
- * @arg I2C_FLAG_BTF: Byte transfer finished flag\r
- * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) \93ADSL\94\r
- * Address matched flag (Slave mode)\94ENDAD\94\r
- * @arg I2C_FLAG_SB: Start bit flag (Master mode)\r
- * @retval The new state of I2C_FLAG (SET or RESET).\r
- */\r
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- __IO uint32_t i2creg = 0, i2cxbase = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_GET_FLAG(I2C_FLAG));\r
-\r
- /* Get the I2Cx peripheral base address */\r
- i2cxbase = (uint32_t)I2Cx;\r
- \r
- /* Read flag register index */\r
- i2creg = I2C_FLAG >> 28;\r
- \r
- /* Get bit[23:0] of the flag */\r
- I2C_FLAG &= FLAG_MASK;\r
- \r
- if(i2creg != 0)\r
- {\r
- /* Get the I2Cx SR1 register address */\r
- i2cxbase += 0x14;\r
- }\r
- else\r
- {\r
- /* Flag in I2Cx SR2 Register */\r
- I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);\r
- /* Get the I2Cx SR2 register address */\r
- i2cxbase += 0x18;\r
- }\r
- \r
- if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)\r
- {\r
- /* I2C_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* I2C_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- \r
- /* Return the I2C_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the I2Cx's pending flags.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_FLAG: specifies the flag to clear. \r
- * This parameter can be any combination of the following values:\r
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
- * @arg I2C_FLAG_PECERR: PEC error in reception flag\r
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
- * @arg I2C_FLAG_AF: Acknowledge failure flag\r
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
- * @arg I2C_FLAG_BERR: Bus error flag\r
- * \r
- * @note\r
- * - STOPF (STOP detection) is cleared by software sequence: a read operation \r
- * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation \r
- * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r
- * - ADD10 (10-bit header sent) is cleared by software sequence: a read \r
- * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the \r
- * second byte of the address in DR register.\r
- * - BTF (Byte Transfer Finished) is cleared by software sequence: a read \r
- * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a \r
- * read/write to I2C_DR register (I2C_SendData()).\r
- * - ADDR (Address sent) is cleared by software sequence: a read operation to \r
- * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to \r
- * I2C_SR2 register ((void)(I2Cx->SR2)).\r
- * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1\r
- * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR\r
- * register (I2C_SendData()).\r
- * @retval None\r
- */\r
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
-{\r
- uint32_t flagpos = 0;\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));\r
- /* Get the I2C flag position */\r
- flagpos = I2C_FLAG & FLAG_MASK;\r
- /* Clear the selected I2C flag */\r
- I2Cx->SR1 = (uint16_t)~flagpos;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified I2C interrupt has occurred or not.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_IT: specifies the interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_IT_SMBALERT: SMBus Alert flag\r
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag\r
- * @arg I2C_IT_PECERR: PEC error in reception flag\r
- * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)\r
- * @arg I2C_IT_AF: Acknowledge failure flag\r
- * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)\r
- * @arg I2C_IT_BERR: Bus error flag\r
- * @arg I2C_IT_TXE: Data register empty flag (Transmitter)\r
- * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag\r
- * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)\r
- * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)\r
- * @arg I2C_IT_BTF: Byte transfer finished flag\r
- * @arg I2C_IT_ADDR: Address sent flag (Master mode) \93ADSL\94\r
- * Address matched flag (Slave mode)\94ENDAD\94\r
- * @arg I2C_IT_SB: Start bit flag (Master mode)\r
- * @retval The new state of I2C_IT (SET or RESET).\r
- */\r
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t enablestatus = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_GET_IT(I2C_IT));\r
-\r
- /* Check if the interrupt source is enabled or not */\r
- enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ;\r
- \r
- /* Get bit[23:0] of the flag */\r
- I2C_IT &= FLAG_MASK;\r
-\r
- /* Check the status of the specified I2C flag */\r
- if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)\r
- {\r
- /* I2C_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* I2C_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the I2C_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the I2Cx\92s interrupt pending bits.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_IT: specifies the interrupt pending bit to clear. \r
- * This parameter can be any combination of the following values:\r
- * @arg I2C_IT_SMBALERT: SMBus Alert interrupt\r
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt\r
- * @arg I2C_IT_PECERR: PEC error in reception interrupt\r
- * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)\r
- * @arg I2C_IT_AF: Acknowledge failure interrupt\r
- * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)\r
- * @arg I2C_IT_BERR: Bus error interrupt\r
- * \r
- * @note\r
- * - STOPF (STOP detection) is cleared by software sequence: a read operation \r
- * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r
- * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r
- * - ADD10 (10-bit header sent) is cleared by software sequence: a read \r
- * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second \r
- * byte of the address in I2C_DR register.\r
- * - BTF (Byte Transfer Finished) is cleared by software sequence: a read \r
- * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a \r
- * read/write to I2C_DR register (I2C_SendData()).\r
- * - ADDR (Address sent) is cleared by software sequence: a read operation to \r
- * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to \r
- * I2C_SR2 register ((void)(I2Cx->SR2)).\r
- * - SB (Start Bit) is cleared by software sequence: a read operation to \r
- * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r
- * I2C_DR register (I2C_SendData()).\r
- * @retval None\r
- */\r
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
-{\r
- uint32_t flagpos = 0;\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_CLEAR_IT(I2C_IT));\r
- /* Get the I2C flag position */\r
- flagpos = I2C_IT & FLAG_MASK;\r
- /* Clear the selected I2C flag */\r
- I2Cx->SR1 = (uint16_t)~flagpos;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
-\r
-\r
-\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_iwdg.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Independent watchdog (IWDG) peripheral: \r
- * - Prescaler and Counter configuration\r
- * - IWDG activation\r
- * - Flag management\r
- *\r
- * @verbatim \r
- * \r
- * ===================================================================\r
- * IWDG features\r
- * ===================================================================\r
- * \r
- * The IWDG can be started by either software or hardware (configurable\r
- * through option byte).\r
- * \r
- * The IWDG is clocked by its own dedicated low-speed clock (LSI) and\r
- * thus stays active even if the main clock fails.\r
- * Once the IWDG is started, the LSI is forced ON and cannot be disabled\r
- * (LSI cannot be disabled too), and the counter starts counting down from \r
- * the reset value of 0xFFF. When it reaches the end of count value (0x000)\r
- * a system reset is generated.\r
- * The IWDG counter should be reloaded at regular intervals to prevent\r
- * an MCU reset.\r
- * \r
- * The IWDG is implemented in the VDD voltage domain that is still functional\r
- * in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY) \r
- * \r
- * IWDGRST flag in RCC_CSR register can be used to inform when a IWDG\r
- * reset occurs\r
- * \r
- * Min-max timeout value @37KHz (LSI): ~108us / ~28.3s\r
- * The IWDG timeout may vary due to LSI frequency dispersion. STM32L1xx\r
- * devices provide the capability to measure the LSI frequency (LSI clock\r
- * connected internally to TIM10 CH1 input capture). The measured value\r
- * can be used to have an IWDG timeout with an acceptable accuracy. \r
- * For more information, please refer to the STM32L1xx Reference manual\r
- * \r
- * \r
- * ===================================================================\r
- * How to use this driver\r
- * ===================================================================\r
- * 1. Enable write access to IWDG_PR and IWDG_RLR registers using\r
- * IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function\r
- * \r
- * 2. Configure the IWDG prescaler using IWDG_SetPrescaler() function\r
- * \r
- * 3. Configure the IWDG counter value using IWDG_SetReload() function.\r
- * This value will be loaded in the IWDG counter each time the counter\r
- * is reloaded, then the IWDG will start counting down from this value.\r
- * \r
- * 4. Start the IWDG using IWDG_Enable() function, when the IWDG is used\r
- * in software mode (no need to enable the LSI, it will be enabled\r
- * by hardware)\r
- * \r
- * 5. Then the application program must reload the IWDG counter at regular\r
- * intervals during normal operation to prevent an MCU reset, using\r
- * IWDG_ReloadCounter() function. \r
- * \r
- * @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_iwdg.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup IWDG \r
- * @brief IWDG driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* ---------------------- IWDG registers bit mask ----------------------------*/\r
-/* KR register bit mask */\r
-#define KR_KEY_RELOAD ((uint16_t)0xAAAA)\r
-#define KR_KEY_ENABLE ((uint16_t)0xCCCC)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup IWDG_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions\r
- * @brief Prescaler and Counter configuration functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- Prescaler and Counter configuration functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.\r
- * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.\r
- * This parameter can be one of the following values:\r
- * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers\r
- * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers\r
- * @retval None\r
- */\r
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));\r
- IWDG->KR = IWDG_WriteAccess;\r
-}\r
-\r
-/**\r
- * @brief Sets IWDG Prescaler value.\r
- * @param IWDG_Prescaler: specifies the IWDG Prescaler value.\r
- * This parameter can be one of the following values:\r
- * @arg IWDG_Prescaler_4: IWDG prescaler set to 4\r
- * @arg IWDG_Prescaler_8: IWDG prescaler set to 8\r
- * @arg IWDG_Prescaler_16: IWDG prescaler set to 16\r
- * @arg IWDG_Prescaler_32: IWDG prescaler set to 32\r
- * @arg IWDG_Prescaler_64: IWDG prescaler set to 64\r
- * @arg IWDG_Prescaler_128: IWDG prescaler set to 128\r
- * @arg IWDG_Prescaler_256: IWDG prescaler set to 256\r
- * @retval None\r
- */\r
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));\r
- IWDG->PR = IWDG_Prescaler;\r
-}\r
-\r
-/**\r
- * @brief Sets IWDG Reload value.\r
- * @param Reload: specifies the IWDG Reload value.\r
- * This parameter must be a number between 0 and 0x0FFF.\r
- * @retval None\r
- */\r
-void IWDG_SetReload(uint16_t Reload)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_IWDG_RELOAD(Reload));\r
- IWDG->RLR = Reload;\r
-}\r
-\r
-/**\r
- * @brief Reloads IWDG counter with value defined in the reload register\r
- * (write access to IWDG_PR and IWDG_RLR registers disabled).\r
- * @param None\r
- * @retval None\r
- */\r
-void IWDG_ReloadCounter(void)\r
-{\r
- IWDG->KR = KR_KEY_RELOAD;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Group2 IWDG activation function\r
- * @brief IWDG activation function \r
- *\r
-@verbatim \r
- ===============================================================================\r
- IWDG activation function\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).\r
- * @param None\r
- * @retval None\r
- */\r
-void IWDG_Enable(void)\r
-{\r
- IWDG->KR = KR_KEY_ENABLE;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Group3 Flag management function \r
- * @brief Flag management function \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Flag management function \r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Checks whether the specified IWDG flag is set or not.\r
- * @param IWDG_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg IWDG_FLAG_PVU: Prescaler Value Update on going\r
- * @arg IWDG_FLAG_RVU: Reload Value Update on going\r
- * @retval The new state of IWDG_FLAG (SET or RESET).\r
- */\r
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_IWDG_FLAG(IWDG_FLAG));\r
- if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- /* Return the flag status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_lcd.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the LCD controller (LCD) peripheral: \r
- * - Initialization and configuration\r
- * - LCD RAM memory write\r
- * - Interrupts and flags management \r
- * \r
- * @verbatim\r
- * \r
- * =================================================================== \r
- * LCD Clock\r
- * =================================================================== \r
- * LCDCLK is the same as RTCCLK. \r
- * To configure the RTCCLK/LCDCLK, proceed as follows:\r
- * - Enable the Power Controller (PWR) APB1 interface clock using the\r
- * RCC_APB1PeriphClockCmd() function.\r
- * - Enable access to RTC domain using the PWR_RTCAccessCmd() function.\r
- * - Select the RTC clock source using the RCC_RTCCLKConfig() function. \r
- * \r
- * The frequency generator allows you to achieve various LCD frame rates \r
- * starting from an LCD input clock frequency (LCDCLK) which can vary \r
- * from 32 kHz up to 1 MHz.\r
- * \r
- * =================================================================== \r
- * LCD and low power modes\r
- * =================================================================== \r
- * The LCD still active during STOP mode.\r
- * \r
- * ===================================================================\r
- * How to use this driver\r
- * =================================================================== \r
- * 1. Enable LCD clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_LCD, ENABLE) function\r
- * \r
- * 2. Configure the LCD prescaler, divider, duty, bias and voltage source\r
- * using LCD_Init() function \r
- * \r
- * 3. Optionally you can enable/configure:\r
- * - LCD High Drive using the LCD_HighDriveCmd() function\r
- * - LCD High Drive using the LCD_MuxSegmentCmd() function \r
- * - LCD Pulse ON Duration using the LCD_PulseOnDurationConfig() function\r
- * - LCD Dead Time using the LCD_DeadTimeConfig() function \r
- * - The LCD Blink mode and frequency using the LCD_BlinkConfig() function\r
- * - The LCD Contrast using the LCD_ContrastConfig() function \r
- *\r
- * 4. Call the LCD_WaitForSynchro() function to wait for LCD_FCR register\r
- * synchronization.\r
- * \r
- * 5. Call the LCD_Cmd() to enable the LCD controller\r
- * \r
- * 6. Wait until the LCD Controller status is enabled and the step-up\r
- * converter is ready using the LCD_GetFlagStatus() and\r
- * LCD_FLAG_ENS and LCD_FLAG_RDY flags. \r
- * \r
- * 7. Write to the LCD RAM memory using the LCD_Write() function.\r
- * \r
- * 8. Request an update display using the LCD_UpdateDisplayRequest()\r
- * function.\r
- * \r
- * 9. Wait until the update display is finished by checking the UDD\r
- * flag status using the LCD_GetFlagStatus(LCD_FLAG_UDD)\r
- * \r
- * \r
- * @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_lcd.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup LCD \r
- * @brief LCD driver modules\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* ------------ LCD registers bit address in the alias region --------------- */\r
-#define LCD_OFFSET (LCD_BASE - PERIPH_BASE)\r
-\r
-/* --- CR Register ---*/\r
-\r
-/* Alias word address of LCDEN bit */\r
-#define CR_OFFSET (LCD_OFFSET + 0x00)\r
-#define LCDEN_BitNumber 0x00\r
-#define CR_LCDEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LCDEN_BitNumber * 4))\r
-\r
-/* Alias word address of MUX_SEG bit */\r
-#define MUX_SEG_BitNumber 0x07\r
-#define CR_MUX_SEG_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MUX_SEG_BitNumber * 4))\r
-\r
-\r
-/* --- FCR Register ---*/\r
-\r
-/* Alias word address of HD bit */\r
-#define FCR_OFFSET (LCD_OFFSET + 0x04)\r
-#define HD_BitNumber 0x00\r
-#define FCR_HD_BB (PERIPH_BB_BASE + (FCR_OFFSET * 32) + (HD_BitNumber * 4))\r
-\r
-/* --- SR Register ---*/\r
-\r
-/* Alias word address of UDR bit */\r
-#define SR_OFFSET (LCD_OFFSET + 0x08)\r
-#define UDR_BitNumber 0x02\r
-#define SR_UDR_BB (PERIPH_BB_BASE + (SR_OFFSET * 32) + (UDR_BitNumber * 4))\r
-\r
-#define FCR_MASK ((uint32_t)0xFC03FFFF) /* LCD FCR Mask */\r
-#define CR_MASK ((uint32_t)0xFFFFFF81) /* LCD CR Mask */\r
-#define PON_MASK ((uint32_t)0xFFFFFF8F) /* LCD PON Mask */\r
-#define DEAD_MASK ((uint32_t)0xFFFFFC7F) /* LCD DEAD Mask */\r
-#define BLINK_MASK ((uint32_t)0xFFFC1FFF) /* LCD BLINK Mask */\r
-#define CONTRAST_MASK ((uint32_t)0xFFFFE3FF) /* LCD CONTRAST Mask */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup LCD_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup LCD_Group1 Initialization and Configuration functions\r
- * @brief Initialization and Configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Initialization and Configuration functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the LCD peripheral registers to their default reset \r
- * values.\r
- * @param None\r
- * @retval None\r
- */\r
-void LCD_DeInit(void)\r
-{\r
- /* Enable LCD reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_LCD, ENABLE);\r
- /* Release LCD from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_LCD, DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Initializes the LCD peripheral according to the specified parameters \r
- * in the LCD_InitStruct.\r
- * @note This function can be used only when the LCD is disabled. \r
- * @param LCD_InitStruct: pointer to a LCD_InitTypeDef structure that contains \r
- * the configuration information for the specified LCD peripheral.\r
- * @retval None\r
- */\r
-void LCD_Init(LCD_InitTypeDef* LCD_InitStruct)\r
-{\r
- /* Check function parameters */\r
- assert_param(IS_LCD_PRESCALER(LCD_InitStruct->LCD_Prescaler));\r
- assert_param(IS_LCD_DIVIDER(LCD_InitStruct->LCD_Divider));\r
- assert_param(IS_LCD_DUTY(LCD_InitStruct->LCD_Duty));\r
- assert_param(IS_LCD_BIAS(LCD_InitStruct->LCD_Bias)); \r
- assert_param(IS_LCD_VOLTAGE_SOURCE(LCD_InitStruct->LCD_VoltageSource));\r
-\r
- LCD->FCR &= (uint32_t)FCR_MASK;\r
- LCD->FCR |= (uint32_t)(LCD_InitStruct->LCD_Prescaler | LCD_InitStruct->LCD_Divider);\r
-\r
- LCD_WaitForSynchro();\r
-\r
- LCD->CR &= (uint32_t)CR_MASK;\r
- LCD->CR |= (uint32_t)(LCD_InitStruct->LCD_Duty | LCD_InitStruct->LCD_Bias | \\r
- LCD_InitStruct->LCD_VoltageSource);\r
-\r
-}\r
-\r
-/**\r
- * @brief Fills each LCD_InitStruct member with its default value.\r
- * @param LCD_InitStruct: pointer to a LCD_InitTypeDef structure which will \r
- * be initialized.\r
- * @retval None\r
- */\r
-void LCD_StructInit(LCD_InitTypeDef* LCD_InitStruct)\r
-{\r
-/*--------------- Reset LCD init structure parameters values -----------------*/\r
- LCD_InitStruct->LCD_Prescaler = LCD_Prescaler_1; /*!< Initialize the LCD_Prescaler member */\r
- \r
- LCD_InitStruct->LCD_Divider = LCD_Divider_16; /*!< Initialize the LCD_Divider member */\r
- \r
- LCD_InitStruct->LCD_Duty = LCD_Duty_Static; /*!< Initialize the LCD_Duty member */\r
- \r
- LCD_InitStruct->LCD_Bias = LCD_Bias_1_4; /*!< Initialize the LCD_Bias member */\r
- \r
- LCD_InitStruct->LCD_VoltageSource = LCD_VoltageSource_Internal; /*!< Initialize the LCD_VoltageSource member */\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the LCD Controller.\r
- * @param NewState: new state of the LCD peripheral.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void LCD_Cmd(FunctionalState NewState)\r
-{\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- *(__IO uint32_t *) CR_LCDEN_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Waits until the LCD FCR register is synchronized in the LCDCLK domain.\r
- * This function must be called after any write operation to LCD_FCR register.\r
- * @param None\r
- * @retval None\r
- */\r
-void LCD_WaitForSynchro(void)\r
-{\r
- /* Loop until FCRSF flag is set */\r
- while ((LCD->SR & LCD_FLAG_FCRSF) == (uint32_t)RESET)\r
- {\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the low resistance divider. Displays with high \r
- * internal resistance may need a longer drive time to achieve \r
- * satisfactory contrast. This function is useful in this case if some \r
- * additional power consumption can be tolerated.\r
- * @note When this mode is enabled, the PulseOn Duration (PON) have to be \r
- * programmed to 1/CK_PS (LCD_PulseOnDuration_1). \r
- * @param NewState: new state of the low resistance divider.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void LCD_HighDriveCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- *(__IO uint32_t *) FCR_HD_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Mux Segment.\r
- * @note This function can be used only when the LCD is disabled. \r
- * @param NewState: new state of the Mux Segment.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void LCD_MuxSegmentCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- *(__IO uint32_t *) CR_MUX_SEG_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Configures the LCD pulses on duration.\r
- * @param LCD_PulseOnDuration: specifies the LCD pulse on duration in terms of \r
- * CK_PS (prescaled LCD clock period) pulses.\r
- * This parameter can be one of the following values:\r
- * @arg LCD_PulseOnDuration_0: 0 pulse\r
- * @arg LCD_PulseOnDuration_1: Pulse ON duration = 1/CK_PS\r
- * @arg LCD_PulseOnDuration_2: Pulse ON duration = 2/CK_PS\r
- * @arg LCD_PulseOnDuration_3: Pulse ON duration = 3/CK_PS\r
- * @arg LCD_PulseOnDuration_4: Pulse ON duration = 4/CK_PS\r
- * @arg LCD_PulseOnDuration_5: Pulse ON duration = 5/CK_PS\r
- * @arg LCD_PulseOnDuration_6: Pulse ON duration = 6/CK_PS\r
- * @arg LCD_PulseOnDuration_7: Pulse ON duration = 7/CK_PS\r
- * @retval None\r
- */\r
-void LCD_PulseOnDurationConfig(uint32_t LCD_PulseOnDuration)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_LCD_PULSE_ON_DURATION(LCD_PulseOnDuration));\r
-\r
- LCD->FCR &= (uint32_t)PON_MASK;\r
- LCD->FCR |= (uint32_t)(LCD_PulseOnDuration);\r
-}\r
-\r
-/**\r
- * @brief Configures the LCD dead time.\r
- * @param LCD_DeadTime: specifies the LCD dead time.\r
- * This parameter can be one of the following values:\r
- * @arg LCD_DeadTime_0: No dead Time\r
- * @arg LCD_DeadTime_1: One Phase between different couple of Frame\r
- * @arg LCD_DeadTime_2: Two Phase between different couple of Frame\r
- * @arg LCD_DeadTime_3: Three Phase between different couple of Frame\r
- * @arg LCD_DeadTime_4: Four Phase between different couple of Frame\r
- * @arg LCD_DeadTime_5: Five Phase between different couple of Frame\r
- * @arg LCD_DeadTime_6: Six Phase between different couple of Frame \r
- * @arg LCD_DeadTime_7: Seven Phase between different couple of Frame\r
- * @retval None\r
- */\r
-void LCD_DeadTimeConfig(uint32_t LCD_DeadTime)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_LCD_DEAD_TIME(LCD_DeadTime));\r
-\r
- LCD->FCR &= (uint32_t)DEAD_MASK;\r
- LCD->FCR |= (uint32_t)(LCD_DeadTime);\r
-}\r
-\r
-/**\r
- * @brief Configures the LCD Blink mode and Blink frequency.\r
- * @param LCD_BlinkMode: specifies the LCD blink mode.\r
- * This parameter can be one of the following values:\r
- * @arg LCD_BlinkMode_Off: Blink disabled\r
- * @arg LCD_BlinkMode_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel)\r
- * @arg LCD_BlinkMode_SEG0_AllCOM: Blink enabled on SEG[0], all COM (up to 8 \r
- * pixels according to the programmed duty)\r
- * @arg LCD_BlinkMode_AllSEG_AllCOM: Blink enabled on all SEG and all COM \r
- * (all pixels)\r
- * @param LCD_BlinkFrequency: specifies the LCD blink frequency.\r
- * This parameter can be one of the following values:\r
- * @arg LCD_BlinkFrequency_Div8: The Blink frequency = fLcd/8\r
- * @arg LCD_BlinkFrequency_Div16: The Blink frequency = fLcd/16\r
- * @arg LCD_BlinkFrequency_Div32: The Blink frequency = fLcd/32\r
- * @arg LCD_BlinkFrequency_Div64: The Blink frequency = fLcd/64 \r
- * @arg LCD_BlinkFrequency_Div128: The Blink frequency = fLcd/128\r
- * @arg LCD_BlinkFrequency_Div256: The Blink frequency = fLcd/256\r
- * @arg LCD_BlinkFrequency_Div512: The Blink frequency = fLcd/512\r
- * @arg LCD_BlinkFrequency_Div1024: The Blink frequency = fLcd/1024\r
- * @retval None\r
- */\r
-void LCD_BlinkConfig(uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_LCD_BLINK_MODE(LCD_BlinkMode));\r
- assert_param(IS_LCD_BLINK_FREQUENCY(LCD_BlinkFrequency));\r
- \r
- LCD->FCR &= (uint32_t)BLINK_MASK;\r
- LCD->FCR |= (uint32_t)(LCD_BlinkMode | LCD_BlinkFrequency);\r
-}\r
-\r
-/**\r
- * @brief Configures the LCD Contrast.\r
- * @param LCD_Contrast: specifies the LCD Contrast.\r
- * This parameter can be one of the following values:\r
- * @arg LCD_Contrast_Level_0: Maximum Voltage = 2.60V\r
- * @arg LCD_Contrast_Level_1: Maximum Voltage = 2.73V\r
- * @arg LCD_Contrast_Level_2: Maximum Voltage = 2.86V\r
- * @arg LCD_Contrast_Level_3: Maximum Voltage = 2.99V\r
- * @arg LCD_Contrast_Level_4: Maximum Voltage = 3.12V\r
- * @arg LCD_Contrast_Level_5: Maximum Voltage = 3.25V\r
- * @arg LCD_Contrast_Level_6: Maximum Voltage = 3.38V\r
- * @arg LCD_Contrast_Level_7: Maximum Voltage = 3.51V\r
- * @retval None\r
- */\r
-void LCD_ContrastConfig(uint32_t LCD_Contrast)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_LCD_CONTRAST(LCD_Contrast));\r
-\r
- LCD->FCR &= (uint32_t)CONTRAST_MASK;\r
- LCD->FCR |= (uint32_t)(LCD_Contrast);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup LCD_Group2 LCD RAM memory write functions\r
- * @brief LCD RAM memory write functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- LCD RAM memory write functions\r
- =============================================================================== \r
-\r
- Using its double buffer memory the LCD controller ensures the coherency of the \r
- displayed information without having to use interrupts to control LCD_RAM \r
- modification.\r
- The application software can access the first buffer level (LCD_RAM) through \r
- the APB interface. Once it has modified the LCD_RAM, it sets the UDR flag in \r
- the LCD_SR register using the LCD_UpdateDisplayRequest() function.\r
- This UDR flag (update display request) requests the updated information to be \r
- moved into the second buffer level (LCD_DISPLAY).\r
- This operation is done synchronously with the frame (at the beginning of the \r
- next frame), until the update is completed, the LCD_RAM is write protected and \r
- the UDR flag stays high.\r
- Once the update is completed another flag (UDD - Update Display Done) is set and\r
- generates an interrupt if the UDDIE bit in the LCD_FCR register is set.\r
- The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one \r
- even frame.\r
- The update will not occur (UDR = 1 and UDD = 0) until the display is \r
- enabled (LCDEN = 1).\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Writes a word in the specific LCD RAM.\r
- * @param LCD_RAMRegister: specifies the LCD Contrast.\r
- * This parameter can be one of the following values:\r
- * @arg LCD_RAMRegister_0: LCD RAM Register 0\r
- * @arg LCD_RAMRegister_1: LCD RAM Register 1\r
- * @arg LCD_RAMRegister_2: LCD RAM Register 2\r
- * @arg LCD_RAMRegister_3: LCD RAM Register 3\r
- * @arg LCD_RAMRegister_4: LCD RAM Register 4\r
- * @arg LCD_RAMRegister_5: LCD RAM Register 5\r
- * @arg LCD_RAMRegister_6: LCD RAM Register 6 \r
- * @arg LCD_RAMRegister_7: LCD RAM Register 7 \r
- * @arg LCD_RAMRegister_8: LCD RAM Register 8\r
- * @arg LCD_RAMRegister_9: LCD RAM Register 9\r
- * @arg LCD_RAMRegister_10: LCD RAM Register 10\r
- * @arg LCD_RAMRegister_11: LCD RAM Register 11\r
- * @arg LCD_RAMRegister_12: LCD RAM Register 12 \r
- * @arg LCD_RAMRegister_13: LCD RAM Register 13 \r
- * @arg LCD_RAMRegister_14: LCD RAM Register 14 \r
- * @arg LCD_RAMRegister_15: LCD RAM Register 15 \r
- * @param LCD_Data: specifies LCD Data Value to be written.\r
- * @retval None\r
- */\r
-void LCD_Write(uint32_t LCD_RAMRegister, uint32_t LCD_Data)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_LCD_RAM_REGISTER(LCD_RAMRegister));\r
-\r
- /* Copy data bytes to RAM register */\r
- LCD->RAM[LCD_RAMRegister] = (uint32_t)LCD_Data;\r
-}\r
-\r
-/**\r
- * @brief Enables the Update Display Request.\r
- * @note Each time software modifies the LCD_RAM it must set the UDR bit to \r
- * transfer the updated data to the second level buffer. \r
- * The UDR bit stays set until the end of the update and during this \r
- * time the LCD_RAM is write protected. \r
- * @note When the display is disabled, the update is performed for all \r
- * LCD_DISPLAY locations.\r
- * When the display is enabled, the update is performed only for locations \r
- * for which commons are active (depending on DUTY). For example if \r
- * DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated. \r
- * @param None\r
- * @retval None\r
- */\r
-void LCD_UpdateDisplayRequest(void)\r
-{\r
- *(__IO uint32_t *) SR_UDR_BB = (uint32_t)0x01;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup LCD_Group3 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Interrupts and flags management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified LCD interrupts.\r
- * @param LCD_IT: specifies the LCD interrupts sources to be enabled or disabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg LCD_IT_SOF: Start of Frame Interrupt\r
- * @arg LCD_IT_UDD: Update Display Done Interrupt\r
- * @param NewState: new state of the specified LCD interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void LCD_ITConfig(uint32_t LCD_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_LCD_IT(LCD_IT)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- LCD->FCR |= LCD_IT;\r
- }\r
- else\r
- {\r
- LCD->FCR &= (uint32_t)~LCD_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified LCD flag is set or not.\r
- * @param LCD_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.\r
- * @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR \r
- * goes from 0 to 1. On deactivation it reflects the real status of \r
- * LCD so it becomes 0 at the end of the last displayed frame. \r
- * @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at \r
- * the beginning of a new frame, at the same time as the display data is \r
- * updated.\r
- * @arg LCD_FLAG_UDR: Update Display Request flag.\r
- * @arg LCD_FLAG_UDD: Update Display Done flag. \r
- * @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status \r
- * of the step-up converter.\r
- * @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag. \r
- * This flag is set by hardware each time the LCD_FCR register is updated \r
- * in the LCDCLK domain. \r
- * @retval The new state of LCD_FLAG (SET or RESET).\r
- */\r
-FlagStatus LCD_GetFlagStatus(uint32_t LCD_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_LCD_GET_FLAG(LCD_FLAG));\r
- \r
- if ((LCD->SR & LCD_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the LCD's pending flags.\r
- * @param LCD_FLAG: specifies the flag to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg LCD_FLAG_SOF: Start of Frame Interrupt\r
- * @arg LCD_FLAG_UDD: Update Display Done Interrupt\r
- * @retval None\r
- */\r
-void LCD_ClearFlag(uint32_t LCD_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_LCD_CLEAR_FLAG(LCD_FLAG));\r
- \r
- /* Clear the corresponding LCD flag */\r
- LCD->CLR = (uint32_t)LCD_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified RTC interrupt has occurred or not.\r
- * @param RTC_IT: specifies the RTC interrupts sources to check.\r
- * This parameter can be one of the following values:\r
- * @arg LCD_IT_SOF: Start of Frame Interrupt\r
- * @arg LCD_IT_UDD: Update Display Done Interrupt.\r
- * @note If the device is in STOP mode (PCLK not provided) UDD will not \r
- * generate an interrupt even if UDDIE = 1. \r
- * If the display is not enabled the UDD interrupt will never occur. \r
- * @retval The new state of the LCD_IT (SET or RESET).\r
- */\r
-ITStatus LCD_GetITStatus(uint32_t LCD_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_LCD_GET_IT(LCD_IT));\r
- \r
- if ((LCD->SR & LCD_IT) != (uint16_t)RESET) \r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- \r
- if (((LCD->FCR & LCD_IT) != (uint16_t)RESET) && (bitstatus != (uint32_t)RESET))\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the LCD's interrupt pending bits.\r
- * @param LCD_IT: specifies the interrupt pending bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg LCD_IT_SOF: Start of Frame Interrupt\r
- * @arg LCD_IT_UDD: Update Display Done Interrupt\r
- * @retval None\r
- */\r
-void LCD_ClearITPendingBit(uint32_t LCD_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_LCD_IT(LCD_IT));\r
- \r
- /* Clear the corresponding LCD pending bit */\r
- LCD->CLR = (uint32_t)LCD_IT;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_pwr.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Power Controller (PWR) peripheral: \r
- * - RTC Domain Access\r
- * - PVD configuration\r
- * - WakeUp pins configuration\r
- * - Ultra Low Power mode configuration\r
- * - Voltage Scaling configuration\r
- * - Low Power modes configuration\r
- * - Flags management\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_pwr.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup PWR \r
- * @brief PWR driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* --------- PWR registers bit address in the alias region ---------- */\r
-#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)\r
-\r
-/* --- CR Register ---*/\r
-\r
-/* Alias word address of DBP bit */\r
-#define CR_OFFSET (PWR_OFFSET + 0x00)\r
-#define DBP_BitNumber 0x08\r
-#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))\r
-\r
-/* Alias word address of PVDE bit */\r
-#define PVDE_BitNumber 0x04\r
-#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))\r
-\r
-/* Alias word address of ULP bit */\r
-#define ULP_BitNumber 0x09\r
-#define CR_ULP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4))\r
-\r
-/* Alias word address of FWU bit */\r
-#define FWU_BitNumber 0x0A\r
-#define CR_FWU_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4))\r
-\r
-/* --- CSR Register ---*/\r
-\r
-/* Alias word address of EWUP bit */\r
-#define CSR_OFFSET (PWR_OFFSET + 0x04)\r
-#define EWUP_BitNumber 0x08\r
-#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))\r
-\r
-/* ------------------ PWR registers bit mask ------------------------ */\r
-\r
-/* CR register bit mask */\r
-#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)\r
-#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)\r
-#define CR_VOS_MASK ((uint32_t)0xFFFFE7FF)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup PWR_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup PWR_Group1 RTC Domain Access function \r
- * @brief RTC Domain Access function \r
- *\r
-@verbatim \r
- ===============================================================================\r
- RTC Domain Access function \r
- =============================================================================== \r
-\r
- After reset, the RTC Registers (RCC CSR Register, RTC registers and RTC backup \r
- registers) are protected against possible stray write accesses.\r
- To enable access to RTC domain use the PWR_RTCAccessCmd(ENABLE) function.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the PWR peripheral registers to their default reset values.\r
- * @note Before calling this function, the VOS[1:0] bits should be configured \r
- * to "10" and the system frequency has to be configured accordingly. \r
- * To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig()\r
- * function. \r
- * @note ULP and FWU bits are not reset by this function. \r
- * @param None\r
- * @retval None\r
- */\r
-void PWR_DeInit(void)\r
-{\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables access to the RTC and backup registers.\r
- * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the \r
- * RTC Domain Access should be kept enabled.\r
- * @param NewState: new state of the access to the RTC and backup registers.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void PWR_RTCAccessCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Group2 PVD configuration functions\r
- * @brief PVD configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- PVD configuration functions\r
- =============================================================================== \r
-\r
- - The PVD is used to monitor the VDD power supply by comparing it to a threshold\r
- selected by the PVD Level (PLS[2:0] bits in the PWR_CR).\r
- - The PVD can use an external input analog voltage (PVD_IN) which is compared \r
- internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode \r
- when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).\r
- - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the \r
- PVD threshold. This event is internally connected to the EXTI line16\r
- and can generate an interrupt if enabled through the EXTI registers.\r
- - The PVD is stopped in Standby mode.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r
- * @param PWR_PVDLevel: specifies the PVD detection level\r
- * This parameter can be one of the following values:\r
- * @arg PWR_PVDLevel_0: PVD detection level set to 1.9V\r
- * @arg PWR_PVDLevel_1: PVD detection level set to 2.1V\r
- * @arg PWR_PVDLevel_2: PVD detection level set to 2.3V\r
- * @arg PWR_PVDLevel_3: PVD detection level set to 2.5V\r
- * @arg PWR_PVDLevel_4: PVD detection level set to 2.7V\r
- * @arg PWR_PVDLevel_5: PVD detection level set to 2.9V\r
- * @arg PWR_PVDLevel_6: PVD detection level set to 3.1V\r
- * @arg PWR_PVDLevel_7: External input analog voltage (Compare internally to VREFINT)\r
- * @retval None\r
- */\r
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));\r
- \r
- tmpreg = PWR->CR;\r
- \r
- /* Clear PLS[7:5] bits */\r
- tmpreg &= CR_PLS_MASK;\r
- \r
- /* Set PLS[7:5] bits according to PWR_PVDLevel value */\r
- tmpreg |= PWR_PVDLevel;\r
- \r
- /* Store the new value */\r
- PWR->CR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Power Voltage Detector(PVD).\r
- * @param NewState: new state of the PVD.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void PWR_PVDCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Group3 WakeUp pins configuration functions\r
- * @brief WakeUp pins configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- WakeUp pins configuration functions\r
- =============================================================================== \r
-\r
- - WakeUp pins are used to wakeup the system from Standby mode. These pins are \r
- forced in input pull down configuration and are active on rising edges.\r
- - There are three WakeUp pins: WakeUp Pin 1 on PA.00, WakeUp Pin 2 on PC.13 and\r
- WakeUp Pin 3 on PE.06.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the WakeUp Pin functionality.\r
- * @param PWR_WakeUpPin: specifies the WakeUpPin.\r
- * This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.\r
- * @param NewState: new state of the WakeUp Pin functionality.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)\r
-{\r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));\r
- \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- tmp = CSR_EWUP_BB + PWR_WakeUpPin;\r
- \r
- *(__IO uint32_t *) (tmp) = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Group4 Ultra Low Power mode configuration functions\r
- * @brief Ultra Low Power mode configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Ultra Low Power mode configuration functions\r
- =============================================================================== \r
-\r
- - The internal voltage reference consumption is not negligible, in particular \r
- in Stop and Standby mode. To reduce power consumption, use the PWR_UltraLowPowerCmd()\r
- function (ULP bit (Ultra low power) in the PWR_CR register) to disable the \r
- internal voltage reference. However, in this case, when exiting from the \r
- Stop/Standby mode, the functions managed through the internal voltage reference \r
- are not reliable during the internal voltage reference startup time (up to 3 ms).\r
- To reduce the wakeup time, the device can exit from Stop/Standby mode without \r
- waiting for the internal voltage reference startup time. This is performed \r
- by using the PWR_FastWakeUpCmd() function (setting the FWU bit (Fast\r
- wakeup) in the PWR_CR register) before entering Stop/Standby mode.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the Fast WakeUp from Ultra Low Power mode.\r
- * @param NewState: new state of the Fast WakeUp functionality.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void PWR_FastWakeUpCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- *(__IO uint32_t *) CR_FWU_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Ultra Low Power mode.\r
- * @param NewState: new state of the Ultra Low Power mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void PWR_UltraLowPowerCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- *(__IO uint32_t *) CR_ULP_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Group5 Voltage Scaling configuration functions\r
- * @brief Voltage Scaling configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Voltage Scaling configuration functions\r
- =============================================================================== \r
-\r
- - The dynamic voltage scaling is a power management technique which consists in \r
- increasing or decreasing the voltage used for the digital peripherals (VCORE), \r
- according to the circumstances.\r
- \r
- Depending on the device voltage range, the maximum frequency and FLASH wait\r
- state should be adapted accordingly:\r
- \r
- +------------------------------------------------------------------+ \r
- | Wait states | HCLK clock frequency (MHz) |\r
- | |------------------------------------------------| \r
- | (Latency) | voltage range | voltage range | \r
- | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |\r
- | |----------------|---------------|---------------|\r
- | | Range 3 | Range 2 | Range 1 |\r
- | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |\r
- |---------------- |----------------|---------------|---------------| \r
- | 0WS(1CPU cycle) |0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |\r
- |-----------------|----------------|---------------|---------------| \r
- | 1WS(2CPU cycle) |2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32|\r
- |-----------------|----------------|---------------|---------------| \r
- | CPU Performance | Low | Medium | High |\r
- |-----__----------|----------------|---------------|---------------| \r
- |Power Performance| High | Medium | Low | \r
- +------------------------------------------------------------------+ \r
-\r
- - To modify the Product voltage range, user application has to:\r
- - Check VDD to identify which ranges are allowed (see table above)\r
- - Check the PWR_FLAG_VOSF (Voltage Scaling update ongoing) using the PWR_GetFlagStatus() \r
- function and wait until it is reset.\r
- - Configure the Voltage range using the PWR_VoltageScalingConfig() function.\r
-\r
- - When VCORE range 1 is selected and VDD drops below 2.0 V, the application must\r
- reconfigure the system:\r
- - Detect that VDD drops below 2.0 V using the PVD Level 1\r
- - Adapt the clock frequency to the voltage range that will be selected at next step\r
- - Select the required voltage range\r
- - When VCORE range 2 or range 3 is selected and VDD drops below 2.0 V, no system\r
- reconfiguration is required.\r
- \r
- - When VDD is above 2.0 V, any of the 3 voltage ranges can be selected\r
- - When the voltage range is above the targeted voltage range (e.g. from range \r
- 1 to 2):\r
- - Adapt the clock frequency to the lower voltage range that will be selected \r
- at next step.\r
- - Select the required voltage range.\r
- - When the voltage range is below the targeted voltage range (e.g. from range \r
- 3 to 1):\r
- - Select the required voltage range.\r
- - Tune the clock frequency if needed.\r
- \r
- - When VDD is below 2.0 V, only range 2 and 3 can be selected:\r
- - From range 2 to range 3\r
- - Adapt the clock frequency to voltage range 3.\r
- - Select voltage range 3.\r
- - From range 3 to range 2\r
- - Select the voltage range 2.\r
- - Tune the clock frequency if needed.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the voltage scaling range.\r
- * @note During voltage scaling configuration, the system clock is stopped \r
- * until the regulator is stabilized (VOSF = 0). This must be taken \r
- * into account during application developement, in case a critical \r
- * reaction time to interrupt is needed, and depending on peripheral \r
- * used (timer, communication,...).\r
- * \r
- * @param PWR_VoltageScaling: specifies the voltage scaling range.\r
- * This parameter can be:\r
- * @arg PWR_VoltageScaling_Range1: Voltage Scaling Range 1 (VCORE = 1.8V)\r
- * @arg PWR_VoltageScaling_Range2: Voltage Scaling Range 2 (VCORE = 1.5V)\r
- * @arg PWR_VoltageScaling_Range3: Voltage Scaling Range 3 (VCORE = 1.2V) \r
- * @retval None\r
- */\r
-void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling)\r
-{\r
- uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(PWR_VoltageScaling));\r
- \r
- tmp = PWR->CR;\r
-\r
- tmp &= CR_VOS_MASK;\r
- tmp |= PWR_VoltageScaling;\r
- \r
- PWR->CR = tmp & 0xFFFFFFF3;\r
-\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Group6 Low Power modes configuration functions\r
- * @brief Low Power modes configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Low Power modes configuration functions\r
- =============================================================================== \r
-\r
- The devices feature five low-power modes:\r
- - Low power run mode: regulator in low power mode, limited clock frequency, \r
- limited number of peripherals running.\r
- - Sleep mode: Cortex-M3 core stopped, peripherals kept running.\r
- - Low power sleep mode: Cortex-M3 core stopped, limited clock frequency, \r
- limited number of peripherals running, regulator in low power mode.\r
- - Stop mode: all clocks are stopped, regulator running, regulator in low power mode\r
- - Standby mode: VCORE domain powered off\r
- \r
- Low power run mode (LP run)\r
- ===========================\r
- - Entry:\r
- - Decrease the system frequency.\r
- - The regulator is forced in low power mode using the PWR_EnterLowPowerRunMode()\r
- function.\r
- - Exit:\r
- - The regulator is forced in Main regulator mode sing the PWR_EnterLowPowerRunMode()\r
- function.\r
- - Increase the system frequency if needed.\r
-\r
- Sleep mode\r
- ===========\r
- - Entry:\r
- - The Sleep mode is entered by using the PWR_EnterSleepMode(PWR_Regulator_ON,) \r
- function with regulator ON.\r
- - Exit:\r
- - Any peripheral interrupt acknowledged by the nested vectored interrupt \r
- controller (NVIC) can wake up the device from Sleep mode.\r
-\r
- Low power sleep mode (LP sleep)\r
- ===============================\r
- - Entry:\r
- - The Flash memory must be switched off by using the FLASH_SLEEPPowerDownCmd()\r
- function.\r
- - Decrease the system frequency.\r
- - The regulator is forced in low power mode and the WFI or WFE instructions\r
- are executed using the PWR_EnterSleepMode(PWR_Regulator_LowPower,) function \r
- with regulator in LowPower.\r
- - Exit:\r
- - Any peripheral interrupt acknowledged by the nested vectored interrupt \r
- controller (NVIC) can wake up the device from Sleep LP mode.\r
-\r
- Stop mode\r
- ==========\r
- In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI,\r
- the HSI and the HSE RC oscillators are disabled. Internal SRAM and register \r
- contents are preserved.\r
- The voltage regulator can be configured either in normal or low-power mode.\r
- To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature\r
- sensor can be switched off before entering the Stop mode. They can be switched \r
- on again by software after exiting the Stop mode using the PWR_UltraLowPowerCmd()\r
- function. \r
- \r
- - Entry:\r
- - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) \r
- function with regulator in LowPower or with Regulator ON.\r
- - Exit:\r
- - Any EXTI Line (Internal or External) configured in Interrupt/Event mode.\r
- \r
- Standby mode\r
- ============\r
- The Standby mode allows to achieve the lowest power consumption. It is based \r
- on the Cortex-M3 deepsleep mode, with the voltage regulator disabled. \r
- The VCORE domain is consequently powered off. The PLL, the MSI, the HSI \r
- oscillator and the HSE oscillator are also switched off. SRAM and register \r
- contents are lost except for the RTC registers, RTC backup registers and \r
- Standby circuitry.\r
- \r
- The voltage regulator is OFF.\r
- \r
- To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature\r
- sensor can be switched off before entering the Standby mode. They can be switched \r
- on again by software after exiting the Standby mode using the PWR_UltraLowPowerCmd()\r
- function. \r
- \r
- - Entry:\r
- - The Standby mode is entered using the PWR_EnterSTANDBYMode() function.\r
- - Exit:\r
- - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,\r
- tamper event, time-stamp event, external reset in NRST pin, IWDG reset. \r
-\r
- Auto-wakeup (AWU) from low-power mode\r
- =====================================\r
- The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC \r
- Wakeup event, a tamper event, a time-stamp event, or a comparator event, \r
- without depending on an external interrupt (Auto-wakeup mode).\r
-\r
- - RTC auto-wakeup (AWU) from the Stop mode\r
- ----------------------------------------\r
- \r
- - To wake up from the Stop mode with an RTC alarm event, it is necessary to:\r
- - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt \r
- or Event modes) using the EXTI_Init() function.\r
- - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function\r
- - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() \r
- and RTC_AlarmCmd() functions.\r
- - To wake up from the Stop mode with an RTC Tamper or time stamp event, it \r
- is necessary to:\r
- - Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt \r
- or Event modes) using the EXTI_Init() function.\r
- - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() \r
- function\r
- - Configure the RTC to detect the tamper or time stamp event using the\r
- RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()\r
- functions.\r
- - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:\r
- - Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt \r
- or Event modes) using the EXTI_Init() function.\r
- - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function\r
- - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), \r
- RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.\r
-\r
- - RTC auto-wakeup (AWU) from the Standby mode\r
- -------------------------------------------\r
- - To wake up from the Standby mode with an RTC alarm event, it is necessary to:\r
- - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function\r
- - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() \r
- and RTC_AlarmCmd() functions.\r
- - To wake up from the Standby mode with an RTC Tamper or time stamp event, it \r
- is necessary to:\r
- - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() \r
- function\r
- - Configure the RTC to detect the tamper or time stamp event using the\r
- RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()\r
- functions.\r
- - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:\r
- - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function\r
- - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), \r
- RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.\r
-\r
- - Comparator auto-wakeup (AWU) from the Stop mode\r
- -----------------------------------------------\r
- - To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup\r
- event, it is necessary to:\r
- - Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 \r
- to be sensitive to to the selected edges (falling, rising or falling \r
- and rising) (Interrupt or Event modes) using the EXTI_Init() function.\r
- - Configure the comparator to generate the event.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enters/Exits the Low Power Run mode.\r
- * @note Low power run mode can only be entered when VCORE is in range 2.\r
- * In addition, the dynamic voltage scaling must not be used when Low \r
- * power run mode is selected. Only Stop and Sleep modes with regulator \r
- * configured in Low power mode is allowed when Low power run mode is \r
- * selected. \r
- * @note In Low power run mode, all I/O pins keep the same state as in Run mode. \r
- * @param NewState: new state of the Low Power Run mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void PWR_EnterLowPowerRunMode(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- PWR->CR |= PWR_CR_LPSDSR;\r
- PWR->CR |= PWR_CR_LPRUN; \r
- }\r
- else\r
- {\r
- PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPRUN); \r
- PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPSDSR); \r
- } \r
-}\r
-\r
-/**\r
- * @brief Enters Sleep mode.\r
- * @note In Sleep mode, all I/O pins keep the same state as in Run mode. \r
- * @param PWR_Regulator: specifies the regulator state in Sleep mode.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_Regulator_ON: Sleep mode with regulator ON\r
- * @arg PWR_Regulator_LowPower: Sleep mode with regulator in low power mode\r
- * @note Low power sleep mode can only be entered when VCORE is in range 2.\r
- * @note When the voltage regulator operates in low power mode, an additional \r
- * startup delay is incurred when waking up from Low power sleep mode.\r
- * \r
- * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction\r
- * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction\r
- * @retval None\r
- */\r
-void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
-\r
- assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));\r
- \r
- /* Select the regulator state in Sleep mode ---------------------------------*/\r
- tmpreg = PWR->CR;\r
- \r
- /* Clear PDDS and LPDSR bits */\r
- tmpreg &= CR_DS_MASK;\r
- \r
- /* Set LPDSR bit according to PWR_Regulator value */\r
- tmpreg |= PWR_Regulator;\r
- \r
- /* Store the new value */\r
- PWR->CR = tmpreg;\r
-\r
- /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);\r
- \r
- /* Select SLEEP mode entry -------------------------------------------------*/\r
- if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)\r
- { \r
- /* Request Wait For Interrupt */\r
- __WFI();\r
- }\r
- else\r
- {\r
- /* Request Wait For Event */\r
- __WFE();\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enters STOP mode.\r
- * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r
- * @note When exiting Stop mode by issuing an interrupt or a wakeup event, \r
- * the MSI RC oscillator is selected as system clock.\r
- * @note When the voltage regulator operates in low power mode, an additional \r
- * startup delay is incurred when waking up from Stop mode. \r
- * By keeping the internal regulator ON during Stop mode, the consumption \r
- * is higher although the startup time is reduced. \r
- * @param PWR_Regulator: specifies the regulator state in STOP mode.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_Regulator_ON: STOP mode with regulator ON\r
- * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode\r
- * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction\r
- * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction\r
- * @retval None\r
- */\r
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
- assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));\r
- \r
- /* Select the regulator state in STOP mode ---------------------------------*/\r
- tmpreg = PWR->CR;\r
- /* Clear PDDS and LPDSR bits */\r
- tmpreg &= CR_DS_MASK;\r
- \r
- /* Set LPDSR bit according to PWR_Regulator value */\r
- tmpreg |= PWR_Regulator;\r
- \r
- /* Store the new value */\r
- PWR->CR = tmpreg;\r
- \r
- /* Set SLEEPDEEP bit of Cortex System Control Register */\r
- SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
- \r
- /* Select STOP mode entry --------------------------------------------------*/\r
- if(PWR_STOPEntry == PWR_STOPEntry_WFI)\r
- { \r
- /* Request Wait For Interrupt */\r
- __WFI();\r
- }\r
- else\r
- {\r
- /* Request Wait For Event */\r
- __WFE();\r
- }\r
- /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); \r
-}\r
-\r
-/**\r
- * @brief Enters STANDBY mode.\r
- * @note In Standby mode, all I/O pins are high impedance except for:\r
- * - Reset pad (still available) \r
- * - RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, \r
- * time-stamp, RTC Alarm out, or RTC clock calibration out.\r
- * - WKUP pin 1 (PA0) and WKUP pin 3 (PE6), if enabled. \r
- * @param None\r
- * @retval None\r
- */\r
-void PWR_EnterSTANDBYMode(void)\r
-{\r
- /* Clear Wakeup flag */\r
- PWR->CR |= PWR_CR_CWUF;\r
- \r
- /* Select STANDBY mode */\r
- PWR->CR |= PWR_CR_PDDS;\r
- \r
- /* Set SLEEPDEEP bit of Cortex System Control Register */\r
- SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
- \r
-/* This option is used to ensure that store operations are completed */\r
-#if defined ( __CC_ARM )\r
- __force_stores();\r
-#endif\r
- /* Request Wait For Interrupt */\r
- __WFI();\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Group7 Flags management functions\r
- * @brief Flags management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Flags management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Checks whether the specified PWR flag is set or not.\r
- * @param PWR_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event \r
- * was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), \r
- * RTC Tamper event, RTC TimeStamp event or RTC Wakeup.\r
- * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was\r
- * resumed from StandBy mode. \r
- * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled \r
- * by the PWR_PVDCmd() function.\r
- * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. This \r
- * flag indicates the state of the internal voltage reference, VREFINT.\r
- * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for \r
- * the internal regulator to be ready after the voltage range is changed.\r
- * The VOSF flag indicates that the regulator has reached the voltage level \r
- * defined with bits VOS[1:0] of PWR_CR register.\r
- * @arg PWR_FLAG_REGLP: Regulator LP flag. This flag is set by hardware \r
- * when the MCU is in Low power run mode.\r
- * When the MCU exits from Low power run mode, this flag stays SET until \r
- * the regulator is ready in main mode. A polling on this flag is \r
- * recommended to wait for the regulator main mode. \r
- * This flag is RESET by hardware when the regulator is ready. \r
- * @retval The new state of PWR_FLAG (SET or RESET).\r
- */\r
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_PWR_GET_FLAG(PWR_FLAG));\r
- \r
- if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- /* Return the flag status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the PWR's pending flags.\r
- * @param PWR_FLAG: specifies the flag to clear.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_FLAG_WU: Wake Up flag\r
- * @arg PWR_FLAG_SB: StandBy flag\r
- * @retval None\r
- */\r
-void PWR_ClearFlag(uint32_t PWR_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));\r
- \r
- PWR->CR |= PWR_FLAG << 2;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_rcc.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Reset and clock control (RCC) peripheral: \r
- * - Internal/external clocks, PLL, CSS and MCO configuration\r
- * - System, AHB and APB busses clocks configuration\r
- * - Peripheral clocks configuration\r
- * - Interrupts and flags management\r
- *\r
- * @verbatim\r
- * \r
- * ===================================================================\r
- * RCC specific features\r
- * ===================================================================\r
- * \r
- * After reset the device is running from MSI (2 MHz) with Flash 0 WS, \r
- * all peripherals are off except internal SRAM, Flash and JTAG.\r
- * - There is no prescaler on High speed (AHB) and Low speed (APB) busses;\r
- * all peripherals mapped on these busses are running at MSI speed.\r
- * - The clock for all peripherals is switched off, except the SRAM and FLASH.\r
- * - All GPIOs are in input floating state, except the JTAG pins which\r
- * are assigned to be used for debug purpose.\r
- * \r
- * Once the device started from reset, the user application has to: \r
- * - Configure the clock source to be used to drive the System clock\r
- * (if the application needs higher frequency/performance)\r
- * - Configure the System clock frequency and Flash settings \r
- * - Configure the AHB and APB busses prescalers\r
- * - Enable the clock for the peripheral(s) to be used\r
- * - Configure the clock source(s) for peripherals whose clocks are not\r
- * derived from the System clock (ADC, RTC/LCD and IWDG) \r
- * \r
- * @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup RCC \r
- * @brief RCC driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-/* ------------ RCC registers bit address in the alias region ----------- */\r
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)\r
-\r
-/* --- CR Register ---*/\r
-\r
-/* Alias word address of HSION bit */\r
-#define CR_OFFSET (RCC_OFFSET + 0x00)\r
-#define HSION_BitNumber 0x00\r
-#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))\r
-\r
-/* Alias word address of MSION bit */\r
-#define MSION_BitNumber 0x08\r
-#define CR_MSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))\r
-\r
-/* Alias word address of PLLON bit */\r
-#define PLLON_BitNumber 0x18\r
-#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))\r
-\r
-/* Alias word address of CSSON bit */\r
-#define CSSON_BitNumber 0x1C\r
-#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))\r
-\r
-/* --- CSR Register ---*/\r
-\r
-/* Alias word address of LSION bit */\r
-#define CSR_OFFSET (RCC_OFFSET + 0x34)\r
-#define LSION_BitNumber 0x00\r
-#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))\r
-\r
-/* Alias word address of RTCEN bit */\r
-#define RTCEN_BitNumber 0x16\r
-#define CSR_RTCEN_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))\r
-\r
-/* Alias word address of RTCRST bit */\r
-#define RTCRST_BitNumber 0x17\r
-#define CSR_RTCRST_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))\r
-\r
-\r
-/* ---------------------- RCC registers mask -------------------------------- */\r
-/* RCC Flag Mask */\r
-#define FLAG_MASK ((uint8_t)0x1F)\r
-\r
-/* CR register byte 3 (Bits[23:16]) base address */\r
-#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)\r
-\r
-/* ICSCR register byte 4 (Bits[31:24]) base address */\r
-#define ICSCR_BYTE4_ADDRESS ((uint32_t)0x40023807)\r
-\r
-/* CFGR register byte 3 (Bits[23:16]) base address */\r
-#define CFGR_BYTE3_ADDRESS ((uint32_t)0x4002380A)\r
-\r
-/* CFGR register byte 4 (Bits[31:24]) base address */\r
-#define CFGR_BYTE4_ADDRESS ((uint32_t)0x4002380B)\r
-\r
-/* CIR register byte 2 (Bits[15:8]) base address */\r
-#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002380D)\r
-\r
-/* CIR register byte 3 (Bits[23:16]) base address */\r
-#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002380E)\r
-\r
-/* CSR register byte 2 (Bits[15:8]) base address */\r
-#define CSR_BYTE2_ADDRESS ((uint32_t)0x40023835)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-\r
-static __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};\r
-static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup RCC_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions\r
- * @brief Internal and external clocks, PLL, CSS and MCO configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Internal/external clocks, PLL, CSS and MCO configuration functions\r
- =============================================================================== \r
-\r
- This section provide functions allowing to configure the internal/external clocks,\r
- PLL, CSS and MCO.\r
- \r
- 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through\r
- the PLL as System clock source.\r
-\r
- 2. MSI (multi-speed internal), multispeed low power RC (65.536 KHz to 4.194 MHz)\r
- MHz used as System clock source.\r
-\r
- 3. LSI (low-speed internal), 37 KHz low consumption RC used as IWDG and/or RTC\r
- clock source.\r
-\r
- 4. HSE (high-speed external), 1 to 24 MHz crystal oscillator used directly or\r
- through the PLL as System clock source. Can be used also as RTC clock source.\r
-\r
- 5. LSE (low-speed external), 32 KHz oscillator used as RTC clock source. \r
-\r
- 6. PLL (clocked by HSI or HSE), for System clock and USB (48 MHz).\r
-\r
- 7. CSS (Clock security system), once enable and if a HSE clock failure occurs \r
- (HSE used directly or through PLL as System clock source), the System clock\r
- is automatically switched to MSI and an interrupt is generated if enabled. \r
- The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) \r
- exception vector. \r
-\r
- 8. MCO (microcontroller clock output), used to output SYSCLK, HSI, MSI, HSE, PLL,\r
- LSI or LSE clock (through a configurable prescaler) on PA8 pin.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Resets the RCC clock configuration to the default reset state.\r
- * @note - The default reset state of the clock configuration is given below:\r
- * - MSI ON and used as system clock source (MSI range is not modified\r
- * by this function, it keep the value configured by user application)\r
- * - HSI, HSE and PLL OFF\r
- * - AHB, APB1 and APB2 prescaler set to 1.\r
- * - CSS and MCO OFF\r
- * - All interrupts disabled\r
- * - However, this function doesn't modify the configuration of the\r
- * - Peripheral clocks\r
- * - LSI, LSE and RTC clocks \r
- * @param None\r
- * @retval None\r
- */\r
-void RCC_DeInit(void)\r
-{\r
- \r
- /* Set MSION bit */\r
- RCC->CR |= (uint32_t)0x00000100;\r
-\r
- /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */\r
- RCC->CFGR &= (uint32_t)0x88FFC00C;\r
- \r
- /* Reset HSION, HSEON, CSSON and PLLON bits */\r
- RCC->CR &= (uint32_t)0xEEFEFFFE;\r
-\r
- /* Reset HSEBYP bit */\r
- RCC->CR &= (uint32_t)0xFFFBFFFF;\r
-\r
- /* Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */\r
- RCC->CFGR &= (uint32_t)0xFF02FFFF;\r
-\r
- /* Disable all interrupts */\r
- RCC->CIR = 0x00000000;\r
-}\r
-\r
-/**\r
- * @brief Configures the External High Speed oscillator (HSE).\r
- * @note - After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r
- * software should wait on HSERDY flag to be set indicating that HSE clock\r
- * is stable and can be used to clock the PLL and/or system clock.\r
- * - HSE state can not be changed if it is used directly or through the\r
- * PLL as system clock. In this case, you have to select another source\r
- * of the system clock then change the HSE state (ex. disable it).\r
- * - The HSE is stopped by hardware when entering STOP and STANDBY modes. \r
- * @note This function reset the CSSON bit, so if the Clock security system(CSS)\r
- * was previously enabled you have to enable it again after calling this\r
- * function.\r
- * @param RCC_HSE: specifies the new state of the HSE.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after\r
- * 6 HSE oscillator clock cycles.\r
- * @arg RCC_HSE_ON: turn ON the HSE oscillator\r
- * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock\r
- * @retval None\r
- */\r
-void RCC_HSEConfig(uint8_t RCC_HSE)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_HSE(RCC_HSE));\r
-\r
- /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/\r
- *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;\r
-\r
- /* Set the new HSE configuration -------------------------------------------*/\r
- *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;\r
-\r
-}\r
-\r
-/**\r
- * @brief Waits for HSE start-up.\r
- * @note This functions waits on HSERDY flag to be set and return SUCCESS if \r
- * this flag is set, otherwise returns ERROR if the timeout is reached \r
- * and this flag is not set. The timeout value is defined by the constant\r
- * HSE_STARTUP_TIMEOUT in stm32l1xx.h file. You can tailor it depending\r
- * on the HSE crystal used in your application. \r
- * @param None\r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: HSE oscillator is stable and ready to use\r
- * - ERROR: HSE oscillator not yet ready\r
- */\r
-ErrorStatus RCC_WaitForHSEStartUp(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0;\r
- ErrorStatus status = ERROR;\r
- FlagStatus HSEStatus = RESET;\r
- \r
- /* Wait till HSE is ready and if timeout is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);\r
- StartUpCounter++; \r
- } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));\r
- \r
- if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)\r
- {\r
- status = SUCCESS;\r
- }\r
- else\r
- {\r
- status = ERROR;\r
- } \r
- return (status);\r
-}\r
-\r
-/**\r
- * @brief Adjusts the Internal Multi Speed oscillator (MSI) calibration value.\r
- * @note The calibration is used to compensate for the variations in voltage\r
- * and temperature that influence the frequency of the internal MSI RC.\r
- * Refer to the Application Note AN3300 for more details on how to \r
- * calibrate the MSI.\r
- * @param MSICalibrationValue: specifies the MSI calibration trimming value.\r
- * This parameter must be a number between 0 and 0xFF.\r
- * @retval None\r
- */\r
-void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue)\r
-{\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RCC_MSI_CALIBRATION_VALUE(MSICalibrationValue));\r
-\r
- *(__IO uint8_t *) ICSCR_BYTE4_ADDRESS = MSICalibrationValue; \r
-}\r
-\r
-/**\r
- * @brief Configures the Internal Multi Speed oscillator (MSI) clock range.\r
- * @note - After restart from Reset or wakeup from STANDBY, the MSI clock is \r
- * around 2.097 MHz. The MSI clock does not change after wake-up from\r
- * STOP mode.\r
- * - The MSI clock range can be modified on the fly. \r
- * @param RCC_MSIRange: specifies the MSI Clock range.\r
- * This parameter must be one of the following values:\r
- * @arg RCC_MSIRange_0: MSI clock is around 65.536 KHz\r
- * @arg RCC_MSIRange_1: MSI clock is around 131.072 KHz\r
- * @arg RCC_MSIRange_2: MSI clock is around 262.144 KHz\r
- * @arg RCC_MSIRange_3: MSI clock is around 524.288 KHz\r
- * @arg RCC_MSIRange_4: MSI clock is around 1.048 MHz\r
- * @arg RCC_MSIRange_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)\r
- * @arg RCC_MSIRange_6: MSI clock is around \r
- * \r
- * @retval None\r
- */\r
-void RCC_MSIRangeConfig(uint32_t RCC_MSIRange)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_MSIRange));\r
- \r
- tmpreg = RCC->ICSCR;\r
- \r
- /* Clear MSIRANGE[2:0] bits */\r
- tmpreg &= ~RCC_ICSCR_MSIRANGE;\r
- \r
- /* Set the MSIRANGE[2:0] bits according to RCC_MSIRange value */\r
- tmpreg |= (uint32_t)RCC_MSIRange;\r
-\r
- /* Store the new value */\r
- RCC->ICSCR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Internal Multi Speed oscillator (MSI).\r
- * @note - The MSI is stopped by hardware when entering STOP and STANDBY modes.\r
- * It is used (enabled by hardware) as system clock source after\r
- * startup from Reset, wakeup from STOP and STANDBY mode, or in case\r
- * of failure of the HSE used directly or indirectly as system clock\r
- * (if the Clock Security System CSS is enabled). \r
- * - MSI can not be stopped if it is used as system clock source.\r
- * In this case, you have to select another source of the system\r
- * clock then stop the MSI. \r
- * - After enabling the MSI, the application software should wait on\r
- * MSIRDY flag to be set indicating that MSI clock is stable and can\r
- * be used as system clock source. \r
- * @param NewState: new state of the MSI.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator\r
- * clock cycles. \r
- * @retval None\r
- */\r
-void RCC_MSICmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CR_MSION_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.\r
- * @note The calibration is used to compensate for the variations in voltage\r
- * and temperature that influence the frequency of the internal HSI RC.\r
- * Refer to the Application Note AN3300 for more details on how to \r
- * calibrate the HSI.\r
- * @param HSICalibrationValue: specifies the HSI calibration trimming value.\r
- * This parameter must be a number between 0 and 0x1F.\r
- * @retval None\r
- */\r
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));\r
- \r
- tmpreg = RCC->ICSCR;\r
- \r
- /* Clear HSITRIM[4:0] bits */\r
- tmpreg &= ~RCC_ICSCR_HSITRIM;\r
- \r
- /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */\r
- tmpreg |= (uint32_t)HSICalibrationValue << 8;\r
-\r
- /* Store the new value */\r
- RCC->ICSCR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Internal High Speed oscillator (HSI).\r
- * @note - After enabling the HSI, the application software should wait on \r
- * HSIRDY flag to be set indicating that HSI clock is stable and can\r
- * be used to clock the PLL and/or system clock.\r
- * - HSI can not be stopped if it is used directly or through the PLL\r
- * as system clock. In this case, you have to select another source \r
- * of the system clock then stop the HSI.\r
- * - The HSI is stopped by hardware when entering STOP and STANDBY modes. \r
- * @param NewState: new state of the HSI.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r
- * clock cycles. \r
- * @retval None\r
- */\r
-void RCC_HSICmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Configures the External Low Speed oscillator (LSE).\r
- * @note - As the LSE is in the RTC domain and write access is denied to this\r
- * domain after reset, you have to enable write access using \r
- * PWR_RTCAccessCmd(ENABLE) function before to configure the LSE\r
- * (to be done once after reset). \r
- * - After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application\r
- * software should wait on LSERDY flag to be set indicating that LSE clock\r
- * is stable and can be used to clock the RTC.\r
- * @param RCC_LSE: specifies the new state of the LSE.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after\r
- * 6 LSE oscillator clock cycles.\r
- * @arg RCC_LSE_ON: turn ON the LSE oscillator\r
- * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock\r
- * @retval None\r
- */\r
-void RCC_LSEConfig(uint8_t RCC_LSE)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_LSE(RCC_LSE));\r
- \r
- /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/\r
- *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_OFF;\r
-\r
- /* Set the new LSE configuration -------------------------------------------*/\r
- *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE; \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Internal Low Speed oscillator (LSI). \r
- * @note - After enabling the LSI, the application software should wait on \r
- * LSIRDY flag to be set indicating that LSI clock is stable and can\r
- * be used to clock the IWDG and/or the RTC.\r
- * - LSI can not be disabled if the IWDG is running. \r
- * @param NewState: new state of the LSI.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r
- * clock cycles. \r
- * @retval None\r
- */\r
-void RCC_LSICmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Configures the PLL clock source and multiplication factor.\r
- * @note This function must be used only when the PLL is disabled.\r
- * \r
- * @param RCC_PLLSource: specifies the PLL entry clock source.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock source\r
- * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock source\r
- * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as\r
- * PLL source).\r
- * \r
- * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock\r
- * This parameter can be:\r
- * @arg RCC_PLLMul_3: PLL clock source multiplied by 3\r
- * @arg RCC_PLLMul_4: PLL clock source multiplied by 4\r
- * @arg RCC_PLLMul_6: PLL clock source multiplied by 6\r
- * @arg RCC_PLLMul_8: PLL clock source multiplied by 8\r
- * @arg RCC_PLLMul_12: PLL clock source multiplied by 12\r
- * @arg RCC_PLLMul_16: PLL clock source multiplied by 16 \r
- * @arg RCC_PLLMul_24: PLL clock source multiplied by 24\r
- * @arg RCC_PLLMul_32: PLL clock source multiplied by 32\r
- * @arg RCC_PLLMul_48: PLL clock source multiplied by 48\r
- * @note The application software must set correctly the PLL multiplication\r
- * factor to avoid exceeding\r
- * - 96 MHz as PLLVCO when the product is in range 1\r
- * - 48 MHz as PLLVCO when the product is in range 2\r
- * - 24 MHz when the product is in range 3\r
- * @note When using the USB the PLLVCO should be 96MHz\r
- * \r
- * @param RCC_PLLDiv: specifies the PLL division factor.\r
- * This parameter can be:\r
- * @arg RCC_PLLDiv_2: PLL Clock output divided by 2 \r
- * @arg RCC_PLLDiv_3: PLL Clock output divided by 3 \r
- * @arg RCC_PLLDiv_4: PLL Clock output divided by 4 \r
- * @note The application software must set correctly the output division to avoid\r
- * exceeding 32 MHz as SYSCLK.\r
- * \r
- * @retval None\r
- */\r
-void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));\r
- assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));\r
- assert_param(IS_RCC_PLL_DIV(RCC_PLLDiv));\r
- \r
- *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = (uint8_t)(RCC_PLLSource | ((uint8_t)(RCC_PLLMul | (uint8_t)(RCC_PLLDiv))));\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the PLL.\r
- * @note - After enabling the PLL, the application software should wait on \r
- * PLLRDY flag to be set indicating that PLL clock is stable and can\r
- * be used as system clock source.\r
- * - The PLL can not be disabled if it is used as system clock source\r
- * - The PLL is disabled by hardware when entering STOP and STANDBY modes. \r
- * @param NewState: new state of the PLL.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_PLLCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Clock Security System.\r
- * @note If a failure is detected on the HSE oscillator clock, this oscillator\r
- * is automatically disabled and an interrupt is generated to inform the\r
- * software about the failure (Clock Security System Interrupt, CSSI),\r
- * allowing the MCU to perform rescue operations. The CSSI is linked to \r
- * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. \r
- * @param NewState: new state of the Clock Security System.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Selects the clock source to output on MCO pin (PA8).\r
- * @note PA8 should be configured in alternate function mode. \r
- * @param RCC_MCOSource: specifies the clock source to output.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_MCOSource_NoClock: No clock selected\r
- * @arg RCC_MCOSource_SYSCLK: System clock selected\r
- * @arg RCC_MCOSource_HSI: HSI oscillator clock selected\r
- * @arg RCC_MCOSource_MSI: MSI oscillator clock selected \r
- * @arg RCC_MCOSource_HSE: HSE oscillator clock selected\r
- * @arg RCC_MCOSource_PLLCLK: PLL clock selected\r
- * @arg RCC_MCOSource_LSI: LSI clock selected\r
- * @arg RCC_MCOSource_LSE: LSE clock selected \r
- * @param RCC_MCODiv: specifies the MCO prescaler.\r
- * This parameter can be one of the following values: \r
- * @arg RCC_MCODiv_1: no division applied to MCO clock \r
- * @arg RCC_MCODiv_2: division by 2 applied to MCO clock\r
- * @arg RCC_MCODiv_4: division by 4 applied to MCO clock\r
- * @arg RCC_MCODiv_8: division by 8 applied to MCO clock\r
- * @arg RCC_MCODiv_16: division by 16 applied to MCO clock \r
- * @retval None\r
- */\r
-void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));\r
- assert_param(IS_RCC_MCO_DIV(RCC_MCODiv));\r
- \r
- /* Select MCO clock source and prescaler */\r
- *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCOSource | RCC_MCODiv; \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions\r
- * @brief System, AHB and APB busses clocks configuration functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- System, AHB and APB busses clocks configuration functions\r
- =============================================================================== \r
-\r
- This section provide functions allowing to configure the System, AHB, APB1 and \r
- APB2 busses clocks.\r
- \r
- 1. Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,\r
- HSE and PLL.\r
- The AHB clock (HCLK) is derived from System clock through configurable prescaler\r
- and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).\r
- APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through \r
- configurable prescalers and used to clock the peripherals mapped on these busses.\r
- You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. \r
-\r
-Note: All the peripheral clocks are derived from the System clock (SYSCLK) except:\r
-==== - The USB 48 MHz clock which is derived from the PLL VCO clock.\r
- - The ADC clock which is always the HSI clock. A divider by 1, 2 or 4 allows\r
- to adapt the clock frequency to the device operating conditions. \r
- - The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC (HSE\r
- divided by a programmable prescaler).\r
- The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD\r
- clock frequency.\r
- - IWDG clock which is always the LSI clock.\r
- \r
- 2. The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32 MHz.\r
- Depending on the device voltage range, the maximum frequency should be \r
- adapted accordingly:\r
- +----------------------------------------------------------------+ \r
- | Wait states | HCLK clock frequency (MHz) |\r
- | |------------------------------------------------| \r
- | (Latency) | voltage range | voltage range | \r
- | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |\r
- | |----------------|---------------|---------------| \r
- | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |\r
- |-------------- |----------------|---------------|---------------| \r
- |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |\r
- |---------------|----------------|---------------|---------------| \r
- |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32| \r
- +----------------------------------------------------------------+ \r
-\r
- 3. After reset, the System clock source is the MSI (2 MHz) with 0 WS, Flash\r
- 32-bit access is enabled and prefetch is disabled.\r
- \r
- It is recommended to use the following software sequences to tune the number\r
- of wait states needed to access the Flash memory with the CPU frequency (HCLK).\r
- - Increasing the CPU frequency (in the same voltage range)\r
- - Program the Flash 64-bit access, using "FLASH_ReadAccess64Cmd(ENABLE)" function\r
- - Check that 64-bit access is taken into account by reading FLASH_ACR\r
- - Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" function\r
- - Check that the new number of WS is taken into account by reading FLASH_ACR\r
- - Modify the CPU clock source, using "RCC_SYSCLKConfig()" function\r
- - If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function\r
- - Check that the new CPU clock source is taken into account by reading \r
- the clock source status, using "RCC_GetSYSCLKSource()" function \r
- - Decreasing the CPU frequency (in the same voltage range)\r
- - Modify the CPU clock source, using "RCC_SYSCLKConfig()" function\r
- - If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function\r
- - Check that the new CPU clock source is taken into account by reading \r
- the clock source status, using "RCC_GetSYSCLKSource()" function\r
- - Program the new number of WS, using "FLASH_SetLatency()" function\r
- - Check that the new number of WS is taken into account by reading FLASH_ACR\r
- - Enable the Flash 32-bit access, using "FLASH_ReadAccess64Cmd(DISABLE)" function\r
- - Check that 32-bit access is taken into account by reading FLASH_ACR\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the system clock (SYSCLK).\r
- * @note - The MSI is used (enabled by hardware) as system clock source after\r
- * startup from Reset, wake-up from STOP and STANDBY mode, or in case\r
- * of failure of the HSE used directly or indirectly as system clock\r
- * (if the Clock Security System CSS is enabled).\r
- * - A switch from one clock source to another occurs only if the target\r
- * clock source is ready (clock stable after startup delay or PLL locked). \r
- * If a clock source which is not yet ready is selected, the switch will\r
- * occur when the clock source will be ready. \r
- * You can use RCC_GetSYSCLKSource() function to know which clock is\r
- * currently used as system clock source. \r
- * @param RCC_SYSCLKSource: specifies the clock source used as system clock source \r
- * This parameter can be one of the following values:\r
- * @arg RCC_SYSCLKSource_MSI: MSI selected as system clock source\r
- * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source\r
- * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source\r
- * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source\r
- * @retval None\r
- */\r
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));\r
- \r
- tmpreg = RCC->CFGR;\r
- \r
- /* Clear SW[1:0] bits */\r
- tmpreg &= ~RCC_CFGR_SW;\r
- \r
- /* Set SW[1:0] bits according to RCC_SYSCLKSource value */\r
- tmpreg |= RCC_SYSCLKSource;\r
- \r
- /* Store the new value */\r
- RCC->CFGR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Returns the clock source used as system clock.\r
- * @param None\r
- * @retval The clock source used as system clock. The returned value can be one \r
- * of the following values:\r
- * - 0x00: MSI used as system clock\r
- * - 0x04: HSI used as system clock \r
- * - 0x08: HSE used as system clock\r
- * - 0x0C: PLL used as system clock\r
- */\r
-uint8_t RCC_GetSYSCLKSource(void)\r
-{\r
- return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));\r
-}\r
-\r
-/**\r
- * @brief Configures the AHB clock (HCLK).\r
- * @note Depending on the device voltage range, the software has to set correctly\r
- * these bits to ensure that the system frequency does not exceed the\r
- * maximum allowed frequency (for more details refer to section above\r
- * "CPU, AHB and APB busses clocks configuration functions")\r
- * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from \r
- * the system clock (SYSCLK).\r
- * This parameter can be one of the following values:\r
- * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK\r
- * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2\r
- * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4\r
- * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8\r
- * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16\r
- * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64\r
- * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128\r
- * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256\r
- * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512\r
- * @retval None\r
- */\r
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RCC_HCLK(RCC_SYSCLK));\r
- \r
- tmpreg = RCC->CFGR;\r
- \r
- /* Clear HPRE[3:0] bits */\r
- tmpreg &= ~RCC_CFGR_HPRE;\r
- \r
- /* Set HPRE[3:0] bits according to RCC_SYSCLK value */\r
- tmpreg |= RCC_SYSCLK;\r
- \r
- /* Store the new value */\r
- RCC->CFGR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Configures the Low Speed APB clock (PCLK1).\r
- * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from \r
- * the AHB clock (HCLK).\r
- * This parameter can be one of the following values:\r
- * @arg RCC_HCLK_Div1: APB1 clock = HCLK\r
- * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2\r
- * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4\r
- * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8\r
- * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16\r
- * @retval None\r
- */\r
-void RCC_PCLK1Config(uint32_t RCC_HCLK)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RCC_PCLK(RCC_HCLK));\r
- \r
- tmpreg = RCC->CFGR;\r
- \r
- /* Clear PPRE1[2:0] bits */\r
- tmpreg &= ~RCC_CFGR_PPRE1;\r
- \r
- /* Set PPRE1[2:0] bits according to RCC_HCLK value */\r
- tmpreg |= RCC_HCLK;\r
- \r
- /* Store the new value */\r
- RCC->CFGR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Configures the High Speed APB clock (PCLK2).\r
- * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from \r
- * the AHB clock (HCLK).\r
- * This parameter can be one of the following values:\r
- * @arg RCC_HCLK_Div1: APB2 clock = HCLK\r
- * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2\r
- * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4\r
- * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8\r
- * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16\r
- * @retval None\r
- */\r
-void RCC_PCLK2Config(uint32_t RCC_HCLK)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RCC_PCLK(RCC_HCLK));\r
- \r
- tmpreg = RCC->CFGR;\r
- \r
- /* Clear PPRE2[2:0] bits */\r
- tmpreg &= ~RCC_CFGR_PPRE2;\r
- \r
- /* Set PPRE2[2:0] bits according to RCC_HCLK value */\r
- tmpreg |= RCC_HCLK << 3;\r
- \r
- /* Store the new value */\r
- RCC->CFGR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Returns the frequencies of the System, AHB and APB busses clocks.\r
- * @note - The frequency returned by this function is not the real frequency\r
- * in the chip. It is calculated based on the predefined constant and\r
- * the source selected by RCC_SYSCLKConfig():\r
- * \r
- * - If SYSCLK source is MSI, function returns constant the MSI value\r
- * as defined by the MSI range, refer to RCC_MSIRangeConfig()\r
- * \r
- * - If SYSCLK source is HSI, function returns constant HSI_VALUE(*)\r
- * \r
- * - If SYSCLK source is HSE, function returns constant HSE_VALUE(**)\r
- * \r
- * - If SYSCLK source is PLL, function returns constant HSE_VALUE(**) \r
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
- * \r
- * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value\r
- * 16 MHz) but the real value may vary depending on the variations\r
- * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue(). \r
- * \r
- * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value\r
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real\r
- * frequency of the crystal used. Otherwise, this function may\r
- * return wrong result.\r
- * \r
- * - The result of this function could be not correct when using fractional\r
- * value for HSE crystal. \r
- * \r
- * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold \r
- * the clocks frequencies. \r
- * @retval None\r
- */\r
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)\r
-{\r
- uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, presc = 0, msirange = 0;\r
-\r
- /* Get SYSCLK source -------------------------------------------------------*/\r
- tmp = RCC->CFGR & RCC_CFGR_SWS;\r
- \r
- switch (tmp)\r
- {\r
- case 0x00: /* MSI used as system clock */\r
- msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;\r
- RCC_Clocks->SYSCLK_Frequency = (32768 * (1 << (msirange + 1)));\r
- break;\r
- case 0x04: /* HSI used as system clock */\r
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r
- break;\r
- case 0x08: /* HSE used as system clock */\r
- RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;\r
- break;\r
- case 0x0C: /* PLL used as system clock */\r
- /* Get PLL clock source and multiplication factor ----------------------*/\r
- pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;\r
- plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;\r
- pllmul = PLLMulTable[(pllmul >> 18)];\r
- plldiv = (plldiv >> 22) + 1;\r
- \r
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
-\r
- if (pllsource == 0x00)\r
- {\r
- /* HSI oscillator clock selected as PLL clock source */\r
- RCC_Clocks->SYSCLK_Frequency = (((HSI_VALUE) * pllmul) / plldiv);\r
- }\r
- else\r
- {\r
- /* HSE selected as PLL clock source */\r
- RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE) * pllmul) / plldiv);\r
- }\r
- break;\r
- default: /* MSI used as system clock */\r
- msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;\r
- RCC_Clocks->SYSCLK_Frequency = (32768 * (1 << (msirange + 1)));\r
- break;\r
- }\r
- /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/\r
- /* Get HCLK prescaler */\r
- tmp = RCC->CFGR & RCC_CFGR_HPRE;\r
- tmp = tmp >> 4;\r
- presc = APBAHBPrescTable[tmp]; \r
- /* HCLK clock frequency */\r
- RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;\r
-\r
- /* Get PCLK1 prescaler */\r
- tmp = RCC->CFGR & RCC_CFGR_PPRE1;\r
- tmp = tmp >> 8;\r
- presc = APBAHBPrescTable[tmp];\r
- /* PCLK1 clock frequency */\r
- RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
-\r
- /* Get PCLK2 prescaler */\r
- tmp = RCC->CFGR & RCC_CFGR_PPRE2;\r
- tmp = tmp >> 11;\r
- presc = APBAHBPrescTable[tmp];\r
- /* PCLK2 clock frequency */\r
- RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Group3 Peripheral clocks configuration functions\r
- * @brief Peripheral clocks configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Peripheral clocks configuration functions\r
- =============================================================================== \r
-\r
- This section provide functions allowing to configure the Peripheral clocks. \r
- \r
- 1. The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC (HSE\r
- divided by a programmable prescaler).\r
- \r
- 2. After restart from Reset or wakeup from STANDBY, all peripherals are off\r
- except internal SRAM, Flash and JTAG. Before to start using a peripheral you\r
- have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd()\r
- , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.\r
-\r
- 3. To reset the peripherals configuration (to the default state after device reset)\r
- you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and \r
- RCC_APB1PeriphResetCmd() functions.\r
- \r
- 4. To further reduce power consumption in SLEEP mode the peripheral clocks can\r
- be disabled prior to executing the WFI or WFE instructions. You can do this\r
- using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and\r
- RCC_APB1PeriphClockLPModeCmd() functions. \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the RTC and LCD clock (RTCCLK / LCDCLK).\r
- * @note - As the RTC clock configuration bits are in the RTC domain and write\r
- * access is denied to this domain after reset, you have to enable write\r
- * access using PWR_RTCAccessCmd(ENABLE) function before to configure\r
- * the RTC clock source (to be done once after reset). \r
- * - Once the RTC clock is configured it can't be changed unless the RTC\r
- * is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)\r
- * - The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).\r
- * \r
- * @param RCC_RTCCLKSource: specifies the RTC clock source.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock\r
- * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock\r
- * @arg RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock\r
- * @arg RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock\r
- * @arg RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock\r
- * @arg RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock\r
- * \r
- * @note - If the LSE or LSI is used as RTC clock source, the RTC continues to\r
- * work in STOP and STANDBY modes, and can be used as wakeup source.\r
- * However, when the HSE clock is used as RTC clock source, the RTC\r
- * cannot be used in STOP and STANDBY modes.\r
- * \r
- * - The maximum input clock frequency for RTC is 1MHz (when using HSE as\r
- * RTC clock source).\r
- * \r
- * @retval None\r
- */\r
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));\r
- \r
- if ((RCC_RTCCLKSource & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)\r
- { \r
- /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */\r
- tmpreg = RCC->CR;\r
-\r
- /* Clear RTCPRE[1:0] bits */\r
- tmpreg &= ~RCC_CR_RTCPRE;\r
-\r
- /* Configure HSE division factor for RTC clock */\r
- tmpreg |= (RCC_RTCCLKSource & RCC_CR_RTCPRE);\r
-\r
- /* Store the new value */\r
- RCC->CR = tmpreg;\r
- }\r
- \r
- RCC->CSR &= ~RCC_CSR_RTCSEL;\r
- \r
- /* Select the RTC clock source */\r
- RCC->CSR |= (RCC_RTCCLKSource & RCC_CSR_RTCSEL);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the RTC clock.\r
- * @note This function must be used only after the RTC clock source was selected\r
- * using the RCC_RTCCLKConfig function.\r
- * @param NewState: new state of the RTC clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_RTCCLKCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CSR_RTCEN_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Forces or releases the RTC peripheral and associated resources reset.\r
- * @note This function resets the RTC peripheral, RTC clock source selection\r
- * (in RCC_CSR) and the backup registers.\r
- * @param NewState: new state of the RTC reset.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_RTCResetCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CSR_RTCRST_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the AHB peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before \r
- * using it. \r
- * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_AHBPeriph_GPIOA\r
- * @arg RCC_AHBPeriph_GPIOB\r
- * @arg RCC_AHBPeriph_GPIOC \r
- * @arg RCC_AHBPeriph_GPIOD\r
- * @arg RCC_AHBPeriph_GPIOE\r
- * @arg RCC_AHBPeriph_GPIOH\r
- * @arg RCC_AHBPeriph_CRC\r
- * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) \r
- * @arg RCC_AHBPeriph_DMA1\r
- * @param NewState: new state of the specified peripheral clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- RCC->AHBENR |= RCC_AHBPeriph;\r
- }\r
- else\r
- {\r
- RCC->AHBENR &= ~RCC_AHBPeriph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the High Speed APB (APB2) peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before \r
- * using it.\r
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_APB2Periph_SYSCFG\r
- * @arg RCC_APB2Periph_TIM9\r
- * @arg RCC_APB2Periph_TIM10\r
- * @arg RCC_APB2Periph_TIM11\r
- * @arg RCC_APB2Periph_ADC1\r
- * @arg RCC_APB2Periph_SPI1\r
- * @arg RCC_APB2Periph_USART1 \r
- * @param NewState: new state of the specified peripheral clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- RCC->APB2ENR |= RCC_APB2Periph;\r
- }\r
- else\r
- {\r
- RCC->APB2ENR &= ~RCC_APB2Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before \r
- * using it.\r
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_APB1Periph_TIM2\r
- * @arg RCC_APB1Periph_TIM3\r
- * @arg RCC_APB1Periph_TIM4\r
- * @arg RCC_APB1Periph_TIM6\r
- * @arg RCC_APB1Periph_TIM7\r
- * @arg RCC_APB1Periph_LCD\r
- * @arg RCC_APB1Periph_WWDG\r
- * @arg RCC_APB1Periph_SPI2\r
- * @arg RCC_APB1Periph_USART2\r
- * @arg RCC_APB1Periph_USART3\r
- * @arg RCC_APB1Periph_I2C1\r
- * @arg RCC_APB1Periph_I2C2\r
- * @arg RCC_APB1Periph_USB\r
- * @arg RCC_APB1Periph_PWR\r
- * @arg RCC_APB1Periph_DAC\r
- * @arg RCC_APB1Periph_COMP \r
- * @param NewState: new state of the specified peripheral clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- RCC->APB1ENR |= RCC_APB1Periph;\r
- }\r
- else\r
- {\r
- RCC->APB1ENR &= ~RCC_APB1Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Forces or releases AHB peripheral reset.\r
- * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_AHBPeriph_GPIOA\r
- * @arg RCC_AHBPeriph_GPIOB\r
- * @arg RCC_AHBPeriph_GPIOC \r
- * @arg RCC_AHBPeriph_GPIOD\r
- * @arg RCC_AHBPeriph_GPIOE\r
- * @arg RCC_AHBPeriph_GPIOH\r
- * @arg RCC_AHBPeriph_CRC\r
- * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) \r
- * @arg RCC_AHBPeriph_DMA1 \r
- * @param NewState: new state of the specified peripheral reset.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- RCC->AHBRSTR |= RCC_AHBPeriph;\r
- }\r
- else\r
- {\r
- RCC->AHBRSTR &= ~RCC_AHBPeriph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Forces or releases High Speed APB (APB2) peripheral reset.\r
- * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_APB2Periph_SYSCFG\r
- * @arg RCC_APB2Periph_TIM9\r
- * @arg RCC_APB2Periph_TIM10\r
- * @arg RCC_APB2Periph_TIM11\r
- * @arg RCC_APB2Periph_ADC1\r
- * @arg RCC_APB2Periph_SPI1\r
- * @arg RCC_APB2Periph_USART1 \r
- * @param NewState: new state of the specified peripheral reset.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- RCC->APB2RSTR |= RCC_APB2Periph;\r
- }\r
- else\r
- {\r
- RCC->APB2RSTR &= ~RCC_APB2Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Forces or releases Low Speed APB (APB1) peripheral reset.\r
- * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_APB1Periph_TIM2\r
- * @arg RCC_APB1Periph_TIM3\r
- * @arg RCC_APB1Periph_TIM4\r
- * @arg RCC_APB1Periph_TIM6\r
- * @arg RCC_APB1Periph_TIM7\r
- * @arg RCC_APB1Periph_LCD\r
- * @arg RCC_APB1Periph_WWDG\r
- * @arg RCC_APB1Periph_SPI2\r
- * @arg RCC_APB1Periph_USART2\r
- * @arg RCC_APB1Periph_USART3\r
- * @arg RCC_APB1Periph_I2C1\r
- * @arg RCC_APB1Periph_I2C2\r
- * @arg RCC_APB1Periph_USB\r
- * @arg RCC_APB1Periph_PWR\r
- * @arg RCC_APB1Periph_DAC\r
- * @arg RCC_APB1Periph_COMP \r
- * @param NewState: new state of the specified peripheral clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- RCC->APB1RSTR |= RCC_APB1Periph;\r
- }\r
- else\r
- {\r
- RCC->APB1RSTR &= ~RCC_APB1Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the AHB peripheral clock during SLEEP mode.\r
- * @note - Peripheral clock gating in SLEEP mode can be used to further reduce\r
- * power consumption.\r
- * - After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * - By default, all peripheral clocks are enabled during SLEEP mode. \r
- * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_AHBPeriph_GPIOA\r
- * @arg RCC_AHBPeriph_GPIOB\r
- * @arg RCC_AHBPeriph_GPIOC \r
- * @arg RCC_AHBPeriph_GPIOD\r
- * @arg RCC_AHBPeriph_GPIOE\r
- * @arg RCC_AHBPeriph_GPIOH\r
- * @arg RCC_AHBPeriph_CRC\r
- * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) \r
- * @arg RCC_AHBPeriph_SRAM \r
- * @arg RCC_AHBPeriph_DMA1\r
- * @param NewState: new state of the specified peripheral clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_AHB_LPMODE_PERIPH(RCC_AHBPeriph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- RCC->AHBLPENR |= RCC_AHBPeriph;\r
- }\r
- else\r
- {\r
- RCC->AHBLPENR &= ~RCC_AHBPeriph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the APB2 peripheral clock during SLEEP mode.\r
- * @note - Peripheral clock gating in SLEEP mode can be used to further reduce\r
- * power consumption.\r
- * - After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * - By default, all peripheral clocks are enabled during SLEEP mode. \r
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_APB2Periph_SYSCFG\r
- * @arg RCC_APB2Periph_TIM9\r
- * @arg RCC_APB2Periph_TIM10\r
- * @arg RCC_APB2Periph_TIM11\r
- * @arg RCC_APB2Periph_ADC1\r
- * @arg RCC_APB2Periph_SPI1\r
- * @arg RCC_APB2Periph_USART1 \r
- * @param NewState: new state of the specified peripheral clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- RCC->APB2LPENR |= RCC_APB2Periph;\r
- }\r
- else\r
- {\r
- RCC->APB2LPENR &= ~RCC_APB2Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the APB1 peripheral clock during SLEEP mode.\r
- * @note - Peripheral clock gating in SLEEP mode can be used to further reduce\r
- * power consumption.\r
- * - After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * - By default, all peripheral clocks are enabled during SLEEP mode. \r
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_APB1Periph_TIM2\r
- * @arg RCC_APB1Periph_TIM3\r
- * @arg RCC_APB1Periph_TIM4\r
- * @arg RCC_APB1Periph_TIM6\r
- * @arg RCC_APB1Periph_TIM7\r
- * @arg RCC_APB1Periph_LCD\r
- * @arg RCC_APB1Periph_WWDG\r
- * @arg RCC_APB1Periph_SPI2\r
- * @arg RCC_APB1Periph_USART2\r
- * @arg RCC_APB1Periph_USART3\r
- * @arg RCC_APB1Periph_I2C1\r
- * @arg RCC_APB1Periph_I2C2\r
- * @arg RCC_APB1Periph_USB\r
- * @arg RCC_APB1Periph_PWR\r
- * @arg RCC_APB1Periph_DAC\r
- * @arg RCC_APB1Periph_COMP \r
- * @param NewState: new state of the specified peripheral clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- RCC->APB1LPENR |= RCC_APB1Periph;\r
- }\r
- else\r
- {\r
- RCC->APB1LPENR &= ~RCC_APB1Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Group4 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Interrupts and flags management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified RCC interrupts.\r
- * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled\r
- * and if the HSE clock fails, the CSS interrupt occurs and an NMI is\r
- * automatically generated. The NMI will be executed indefinitely, and \r
- * since NMI has higher priority than any other IRQ (and main program)\r
- * the application will be stacked in the NMI ISR unless the CSS interrupt\r
- * pending bit is cleared.\r
- * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
- * @arg RCC_IT_LSERDY: LSE ready interrupt\r
- * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
- * @arg RCC_IT_HSERDY: HSE ready interrupt\r
- * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
- * @arg RCC_IT_MSIRDY: MSI ready interrupt\r
- * @param NewState: new state of the specified RCC interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_IT(RCC_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */\r
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;\r
- }\r
- else\r
- {\r
- /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */\r
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified RCC flag is set or not.\r
- * @param RCC_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
- * @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready \r
- * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
- * @arg RCC_FLAG_PLLRDY: PLL clock ready\r
- * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
- * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
- * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset \r
- * @arg RCC_FLAG_PINRST: Pin reset\r
- * @arg RCC_FLAG_PORRST: POR/PDR reset\r
- * @arg RCC_FLAG_SFTRST: Software reset\r
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset\r
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset\r
- * @arg RCC_FLAG_LPWRRST: Low Power reset\r
- * @retval The new state of RCC_FLAG (SET or RESET).\r
- */\r
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)\r
-{\r
- uint32_t tmp = 0;\r
- uint32_t statusreg = 0;\r
- FlagStatus bitstatus = RESET;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RCC_FLAG(RCC_FLAG));\r
-\r
- /* Get the RCC register index */\r
- tmp = RCC_FLAG >> 5;\r
-\r
- if (tmp == 1) /* The flag to check is in CR register */\r
- {\r
- statusreg = RCC->CR;\r
- }\r
- else /* The flag to check is in CSR register (tmp == 2) */\r
- {\r
- statusreg = RCC->CSR;\r
- }\r
-\r
- /* Get the flag position */\r
- tmp = RCC_FLAG & FLAG_MASK;\r
-\r
- if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- /* Return the flag status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the RCC reset flags.\r
- * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, \r
- * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.\r
- * @param None\r
- * @retval None\r
- */\r
-void RCC_ClearFlag(void)\r
-{\r
- /* Set RMVF bit to clear the reset flags */\r
- RCC->CSR |= RCC_CSR_RMVF;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified RCC interrupt has occurred or not.\r
- * @param RCC_IT: specifies the RCC interrupt source to check.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
- * @arg RCC_IT_LSERDY: LSE ready interrupt\r
- * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
- * @arg RCC_IT_HSERDY: HSE ready interrupt\r
- * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
- * @arg RCC_IT_MSIRDY: MSI ready interrupt \r
- * @arg RCC_IT_CSS: Clock Security System interrupt\r
- * @retval The new state of RCC_IT (SET or RESET).\r
- */\r
-ITStatus RCC_GetITStatus(uint8_t RCC_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_RCC_GET_IT(RCC_IT));\r
- \r
- /* Check the status of the specified RCC interrupt */\r
- if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- /* Return the RCC_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the RCC's interrupt pending bits.\r
- * @param RCC_IT: specifies the interrupt pending bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
- * @arg RCC_IT_LSERDY: LSE ready interrupt\r
- * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
- * @arg RCC_IT_HSERDY: HSE ready interrupt\r
- * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
- * @arg RCC_IT_MSIRDY: MSI ready interrupt \r
- * @arg RCC_IT_CSS: Clock Security System interrupt\r
- * @retval None\r
- */\r
-void RCC_ClearITPendingBit(uint8_t RCC_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_CLEAR_IT(RCC_IT));\r
- \r
- /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt\r
- pending bits */\r
- *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_rtc.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Real-Time Clock (RTC) peripheral: \r
- * - Initialization\r
- * - Calendar (Time and Date) configuration\r
- * - Alarms (Alarm A and Alarm B) configuration\r
- * - WakeUp Timer configuration\r
- * - Daylight Saving configuration\r
- * - Output pin Configuration\r
- * - Digital Calibration configuration\r
- * - TimeStamp configuration\r
- * - Tampers configuration\r
- * - Backup Data Registers configuration\r
- * - Output Type Config configuration\r
- * - Interrupts and flags management \r
- * \r
- * @verbatim\r
- * \r
- * =================================================================== \r
- * RTC Domain Reset\r
- * =================================================================== \r
- * After power-on reset, the RTC domain (RTC clock source configuration,\r
- * RTC registers and RTC Backup data registers) is reset. You can also\r
- * reset this domain by software using the RCC_RTCResetCmd() function. \r
- * \r
- * =================================================================== \r
- * RTC Operating Condition\r
- * =================================================================== \r
- * As long as the supply voltage remains in the operating range, \r
- * the RTC never stops, regardless of the device status (Run mode, \r
- * low power modes or under reset).\r
- * \r
- * =================================================================== \r
- * RTC Domain Access\r
- * =================================================================== \r
- * After reset, the RTC domain (RTC clock source configuration,\r
- * RTC registers and RTC Backup data registers) are protected against \r
- * possible stray write accesses. \r
- * To enable access to the RTC Domain and RTC registers, proceed as follows:\r
- * - Enable the Power Controller (PWR) APB1 interface clock using the\r
- * RCC_APB1PeriphClockCmd() function.\r
- * - Enable access to RTC domain using the PWR_RTCAccessCmd() function.\r
- * - Select the RTC clock source using the RCC_RTCCLKConfig() function.\r
- * - Enable RTC Clock using the RCC_RTCCLKCmd() function.\r
- * \r
- * =================================================================== \r
- * RTC Driver: how to use it\r
- * =================================================================== \r
- * - Enable the RTC domain access (see description in the section above)\r
- * - Configure the RTC Prescaler (Asynchronous and Synchronous) and\r
- * RTC hour format using the RTC_Init() function.\r
- * \r
- * Time and Date configuration\r
- * =========================== \r
- * - To configure the RTC Calendar (Time and Date) use the RTC_SetTime()\r
- * and RTC_SetDate() functions.\r
- * - To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()\r
- * functions.\r
- * - Use the RTC_DayLightSavingConfig() function to add or sub one\r
- * hour to the RTC Calendar. \r
- * \r
- * Alarm configuration\r
- * =================== \r
- * - To configure the RTC Alarm use the RTC_SetAlarm() function.\r
- * - Enable the selected RTC Alarm using the RTC_AlarmCmd() function \r
- * - To read the RTC Alarm, use the RTC_GetAlarm() function.\r
- * \r
- * RTC Wakeup configuration\r
- * ======================== \r
- * - Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()\r
- * function.\r
- * - Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() \r
- * function \r
- * - Enable the RTC WakeUp using the RTC_WakeUpCmd() function \r
- * - To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() \r
- * function.\r
- * \r
- * Outputs configuration\r
- * ===================== \r
- * The RTC has 2 different outputs:\r
- * - AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B\r
- * and WaKeUp signals. \r
- * To output the selected RTC signal on RTC_AF1 pin, use the \r
- * RTC_OutputConfig() function. \r
- * - AFO_CALIB: this output is used to manage the RTC Clock divided \r
- * by 64 (512Hz) signal.\r
- * To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd()\r
- * function. \r
- * \r
- * Digital Calibration configuration\r
- * ================================= \r
- * - Configure the RTC Digital Calibration Value and the corresponding\r
- * sign using the RTC_DigitalCalibConfig() function.\r
- * - Enable the RTC Digital Calibration using the RTC_DigitalCalibCmd() \r
- * function \r
- * \r
- * TimeStamp configuration\r
- * ======================= \r
- * - Configure the RTC_AF1 trigger and enables the RTC TimeStamp \r
- * using the RTC_TimeStampCmd() function.\r
- * - To read the RTC TimeStamp Time and Date register, use the \r
- * RTC_GetTimeStamp() function. \r
- *\r
- * Tamper configuration\r
- * ==================== \r
- * - Configure the RTC Tamper trigger using the RTC_TamperConfig() \r
- * function.\r
- * - Enable the RTC Tamper using the RTC_TamperCmd() function.\r
- *\r
- * Backup Data Registers configuration\r
- * =================================== \r
- * - To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()\r
- * function. \r
- * - To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()\r
- * function. \r
- * \r
- * =================================================================== \r
- * RTC and low power modes\r
- * =================================================================== \r
- * The MCU can be woken up from a low power mode by an RTC alternate \r
- * function.\r
- * The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), \r
- * RTC wakeup, RTC tamper event detection and RTC time stamp event detection.\r
- * These RTC alternate functions can wake up the system from the Stop \r
- * and Standby lowpower modes.\r
- * The system can also wake up from low power modes without depending \r
- * on an external interrupt (Auto-wakeup mode), by using the RTC alarm \r
- * or the RTC wakeup events.\r
- * The RTC provides a programmable time base for waking up from the \r
- * Stop or Standby mode at regular intervals.\r
- * Wakeup from STOP and Standby modes is possible only when the RTC \r
- * clock source is LSE or LSI.\r
- * \r
- * =================================================================== \r
- * Selection of RTC_AF1 alternate functions\r
- * =================================================================== \r
- * The RTC_AF1 pin (PC13) can be used for the following purposes:\r
- * - Wakeup pin 2 (WKUP2) using the PWR_WakeUpPinCmd() function.\r
- * - AFO_ALARM output \r
- * - AFO_CALIB output\r
- * - AFI_TAMPER\r
- * - AFI_TIMESTAMP\r
- * \r
- * +------------------------------------------------------------------------------------------+ \r
- * | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | WKUP2 |ALARMOUTTYPE |\r
- * | configuration | ENABLED | ENABLED | ENABLED | ENABLED |ENABLED | AFO_ALARM |\r
- * | and function | | | | | |Configuration |\r
- * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
- * | Alarm out | | | | | Don't | |\r
- * | output OD | 1 | 0 |Don't care | Don't care | care | 0 |\r
- * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
- * | Alarm out | | | | | Don't | |\r
- * | output PP | 1 | 0 |Don't care | Don't care | care | 1 |\r
- * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
- * | Calibration out | | | | | Don't | |\r
- * | output PP | 0 | 1 |Don't care | Don't care | care | Don't care |\r
- * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
- * | TAMPER input | | | | | Don't | | \r
- * | floating | 0 | 0 | 1 | 0 | care | Don't care |\r
- * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
- * | TIMESTAMP and | | | | | Don't | |\r
- * | TAMPER input | 0 | 0 | 1 | 1 | care | Don't care |\r
- * | floating | | | | | | | \r
- * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
- * | TIMESTAMP input | | | | | Don't | | \r
- * | floating | 0 | 0 | 0 | 1 | care | Don't care | \r
- * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
- * | Wakeup Pin 2 | 0 | 0 | 0 | 0 | 1 | Don't care | \r
- * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
- * | Standard GPIO | 0 | 0 | 0 | 0 | 0 | Don't care | \r
- * +------------------------------------------------------------------------------------------+ \r
- *\r
- * @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_rtc.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup RTC \r
- * @brief RTC driver modules\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-/* Masks Definition */\r
-#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)\r
-#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) \r
-#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) \r
-#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)\r
-#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \\r
- RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \\r
- RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \\r
- RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F ))\r
-\r
-#define INITMODE_TIMEOUT ((uint32_t) 0x00002000)\r
-#define SYNCHRO_TIMEOUT ((uint32_t) 0x00001000)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-static uint8_t RTC_ByteToBcd2(uint8_t Value);\r
-static uint8_t RTC_Bcd2ToByte(uint8_t Value);\r
-\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup RTC_Private_Functions\r
- * @{\r
- */ \r
-\r
-/** @defgroup RTC_Group1 Initialization and Configuration functions\r
- * @brief Initialization and Configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Initialization and Configuration functions\r
- =============================================================================== \r
-\r
- This section provide functions allowing to initialize and configure the RTC\r
- Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers\r
- Write protection, enter and exit the RTC initialization mode, RTC registers\r
- synchronization check and reference clock detection enable.\r
- \r
- 1. The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is\r
- split into 2 programmable prescalers to minimize power consumption.\r
- - A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.\r
- - When both prescalers are used, it is recommended to configure the asynchronous\r
- prescaler to a high value to minimize consumption.\r
-\r
- 2. All RTC registers are Write protected. Writing to the RTC registers\r
- is enabled by writing a key into the Write Protection register, RTC_WPR.\r
-\r
- 3. To Configure the RTC Calendar, user application should enter initialization\r
- mode. In this mode, the calendar counter is stopped and its value can be \r
- updated. When the initialization sequence is complete, the calendar restarts \r
- counting after 4 RTCCLK cycles.\r
-\r
- 4. To read the calendar through the shadow registers after Calendar initialization,\r
- calendar update or after wakeup from low power modes the software must first \r
- clear the RSF flag. The software must then wait until it is set again before \r
- reading the calendar, which means that the calendar registers have been \r
- correctly copied into the RTC_TR and RTC_DR shadow registers.\r
- The RTC_WaitForSynchro() function implements the above software sequence \r
- (RSF clear and RSF check).\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the RTC registers to their default reset values.\r
- * @note This function doesn't reset the RTC Clock source and RTC Backup Data\r
- * registers. \r
- * @param None\r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: RTC registers are deinitialized\r
- * - ERROR: RTC registers are not deinitialized\r
- */\r
-ErrorStatus RTC_DeInit(void)\r
-{\r
- __IO uint32_t wutcounter = 0x00;\r
- uint32_t wutwfstatus = 0x00;\r
- ErrorStatus status = ERROR;\r
- \r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53;\r
-\r
- /* Set Initialization mode */\r
- if (RTC_EnterInitMode() == ERROR)\r
- {\r
- status = ERROR;\r
- } \r
- else\r
- {\r
- /* Reset TR, DR and CR registers */\r
- RTC->TR = (uint32_t)0x00000000;\r
- RTC->DR = (uint32_t)0x00002101;\r
- /* Reset All CR bits except CR[2:0] */\r
- RTC->CR &= (uint32_t)0x00000007;\r
- \r
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r
- do\r
- {\r
- wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;\r
- wutcounter++; \r
- } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));\r
- \r
- if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)\r
- {\r
- status = ERROR;\r
- }\r
- else\r
- {\r
- /* Reset all RTC CR register bits */\r
- RTC->CR &= (uint32_t)0x00000000;\r
- RTC->WUTR = (uint32_t)0x0000FFFF;\r
- RTC->PRER = (uint32_t)0x007F00FF;\r
- RTC->CALIBR = (uint32_t)0x00000000;\r
- RTC->ALRMAR = (uint32_t)0x00000000; \r
- RTC->ALRMBR = (uint32_t)0x00000000;\r
- \r
- /* Reset ISR register and exit initialization mode */\r
- RTC->ISR = (uint32_t)0x00000000;\r
- \r
- /* Reset Tamper and alternate functions configuration register */\r
- RTC->TAFCR = 0x00000000;\r
- \r
- if(RTC_WaitForSynchro() == ERROR)\r
- {\r
- status = ERROR;\r
- }\r
- else\r
- {\r
- status = SUCCESS; \r
- }\r
- }\r
- }\r
- \r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
- \r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Initializes the RTC registers according to the specified parameters \r
- * in RTC_InitStruct.\r
- * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains \r
- * the configuration information for the RTC peripheral.\r
- * @note The RTC Prescaler register is write protected and can be written in \r
- * initialization mode only. \r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: RTC registers are initialized\r
- * - ERROR: RTC registers are not initialized \r
- */\r
-ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)\r
-{\r
- ErrorStatus status = ERROR;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));\r
- assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));\r
- assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));\r
-\r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53;\r
-\r
- /* Set Initialization mode */\r
- if (RTC_EnterInitMode() == ERROR)\r
- {\r
- status = ERROR;\r
- } \r
- else\r
- {\r
- /* Clear RTC CR FMT Bit */\r
- RTC->CR &= ((uint32_t)~(RTC_CR_FMT));\r
- /* Set RTC_CR register */\r
- RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat));\r
- \r
- /* Configure the RTC PRER */\r
- RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);\r
- RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);\r
-\r
- /* Exit Initialization mode */\r
- RTC_ExitInitMode();\r
-\r
- status = SUCCESS; \r
- }\r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
- \r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Fills each RTC_InitStruct member with its default value.\r
- * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be \r
- * initialized.\r
- * @retval None\r
- */\r
-void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)\r
-{\r
- /* Initialize the RTC_HourFormat member */\r
- RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;\r
- \r
- /* Initialize the RTC_AsynchPrediv member */\r
- RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;\r
-\r
- /* Initialize the RTC_SynchPrediv member */\r
- RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the RTC registers write protection.\r
- * @note All the RTC registers are write protected except for RTC_ISR[13:8], \r
- * RTC_TAFCR and RTC_BKPxR.\r
- * @note Writing a wrong key reactivates the write protection.\r
- * @note The protection mechanism is not affected by system reset. \r
- * @param NewState: new state of the write protection.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RTC_WriteProtectionCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
- }\r
- else\r
- {\r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53; \r
- }\r
-}\r
-\r
-/**\r
- * @brief Enters the RTC Initialization mode.\r
- * @note The RTC Initialization mode is write protected, use the \r
- * RTC_WriteProtectionCmd(DISABLE) before calling this function. \r
- * @param None\r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: RTC is in Init mode\r
- * - ERROR: RTC is not in Init mode \r
- */\r
-ErrorStatus RTC_EnterInitMode(void)\r
-{\r
- __IO uint32_t initcounter = 0x00;\r
- ErrorStatus status = ERROR;\r
- uint32_t initstatus = 0x00;\r
- \r
- /* Check if the Initialization mode is set */\r
- if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)\r
- {\r
- /* Set the Initialization mode */\r
- RTC->ISR = (uint32_t)RTC_INIT_MASK;\r
- \r
- /* Wait till RTC is in INIT state and if Time out is reached exit */\r
- do\r
- {\r
- initstatus = RTC->ISR & RTC_ISR_INITF;\r
- initcounter++; \r
- } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));\r
- \r
- if ((RTC->ISR & RTC_ISR_INITF) != RESET)\r
- {\r
- status = SUCCESS;\r
- }\r
- else\r
- {\r
- status = ERROR;\r
- } \r
- }\r
- else\r
- {\r
- status = SUCCESS; \r
- } \r
- \r
- return (status); \r
-}\r
-\r
-/**\r
- * @brief Exits the RTC Initialization mode.\r
- * @note When the initialization sequence is complete, the calendar restarts \r
- * counting after 4 RTCCLK cycles. \r
- * @note The RTC Initialization mode is write protected, use the \r
- * RTC_WriteProtectionCmd(DISABLE) before calling this function. \r
- * @param None\r
- * @retval None\r
- */\r
-void RTC_ExitInitMode(void)\r
-{ \r
- /* Exit Initialization mode */\r
- RTC->ISR &= (uint32_t)~RTC_ISR_INIT; \r
-}\r
-\r
-/**\r
- * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are \r
- * synchronized with RTC APB clock.\r
- * @note The RTC Resynchronization mode is write protected, use the \r
- * RTC_WriteProtectionCmd(DISABLE) before calling this function. \r
- * @note To read the calendar through the shadow registers after Calendar \r
- * initialization, calendar update or after wakeup from low power modes \r
- * the software must first clear the RSF flag. \r
- * The software must then wait until it is set again before reading \r
- * the calendar, which means that the calendar registers have been \r
- * correctly copied into the RTC_TR and RTC_DR shadow registers. \r
- * @param None\r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: RTC registers are synchronised\r
- * - ERROR: RTC registers are not synchronised\r
- */\r
-ErrorStatus RTC_WaitForSynchro(void)\r
-{\r
- __IO uint32_t synchrocounter = 0;\r
- ErrorStatus status = ERROR;\r
- uint32_t synchrostatus = 0x00;\r
-\r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53;\r
- \r
- /* Clear RSF flag */\r
- RTC->ISR &= (uint32_t)RTC_RSF_MASK;\r
- \r
- /* Wait the registers to be synchronised */\r
- do\r
- {\r
- synchrostatus = RTC->ISR & RTC_ISR_RSF;\r
- synchrocounter++; \r
- } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));\r
- \r
- if ((RTC->ISR & RTC_ISR_RSF) != RESET)\r
- {\r
- status = SUCCESS;\r
- }\r
- else\r
- {\r
- status = ERROR;\r
- } \r
-\r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
- \r
- return (status); \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the RTC reference clock detection.\r
- * @param NewState: new state of the RTC reference clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: RTC reference clock detection is enabled\r
- * - ERROR: RTC reference clock detection is disabled \r
- */\r
-ErrorStatus RTC_RefClockCmd(FunctionalState NewState)\r
-{ \r
- ErrorStatus status = ERROR;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53;\r
- \r
- /* Set Initialization mode */\r
- if (RTC_EnterInitMode() == ERROR)\r
- {\r
- status = ERROR;\r
- } \r
- else\r
- { \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the RTC reference clock detection */\r
- RTC->CR |= RTC_CR_REFCKON; \r
- }\r
- else\r
- {\r
- /* Disable the RTC reference clock detection */\r
- RTC->CR &= ~RTC_CR_REFCKON; \r
- }\r
- /* Exit Initialization mode */\r
- RTC_ExitInitMode();\r
- \r
- status = SUCCESS;\r
- }\r
- \r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
- \r
- return status; \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Group2 Time and Date configuration functions\r
- * @brief Time and Date configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Time and Date configuration functions\r
- =============================================================================== \r
-\r
- This section provide functions allowing to program and read the RTC Calendar\r
- (Time and Date).\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Set the RTC current time.\r
- * @param RTC_Format: specifies the format of the entered parameters.\r
- * This parameter can be one of the following values:\r
- * @arg RTC_Format_BIN: Binary data format \r
- * @arg RTC_Format_BCD: BCD data format\r
- * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains \r
- * the time configuration information for the RTC. \r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: RTC Time register is configured\r
- * - ERROR: RTC Time register is not configured\r
- */\r
-ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
- ErrorStatus status = ERROR;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RTC_FORMAT(RTC_Format));\r
- \r
- if (RTC_Format == RTC_Format_BIN)\r
- {\r
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
- {\r
- assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));\r
- assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));\r
- } \r
- else\r
- {\r
- RTC_TimeStruct->RTC_H12 = 0x00;\r
- assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));\r
- }\r
- assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));\r
- assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));\r
- }\r
- else\r
- {\r
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
- {\r
- tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);\r
- assert_param(IS_RTC_HOUR12(tmpreg));\r
- assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); \r
- } \r
- else\r
- {\r
- RTC_TimeStruct->RTC_H12 = 0x00;\r
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));\r
- }\r
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));\r
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));\r
- }\r
- \r
- /* Check the input parameters format */\r
- if (RTC_Format != RTC_Format_BIN)\r
- {\r
- tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \\r
- ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \\r
- ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \\r
- ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); \r
- } \r
- else\r
- {\r
- tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \\r
- ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \\r
- ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \\r
- (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));\r
- } \r
-\r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53;\r
-\r
- /* Set Initialization mode */\r
- if (RTC_EnterInitMode() == ERROR)\r
- {\r
- status = ERROR;\r
- } \r
- else\r
- {\r
- /* Set the RTC_TR register */\r
- RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);\r
-\r
- /* Exit Initialization mode */\r
- RTC_ExitInitMode(); \r
-\r
- if(RTC_WaitForSynchro() == ERROR)\r
- {\r
- status = ERROR;\r
- }\r
- else\r
- {\r
- status = SUCCESS;\r
- }\r
- \r
- }\r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
- \r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Fills each RTC_TimeStruct member with its default value\r
- * (Time = 00h:00min:00sec).\r
- * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be \r
- * initialized.\r
- * @retval None\r
- */\r
-void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)\r
-{\r
- /* Time = 00h:00min:00sec */\r
- RTC_TimeStruct->RTC_H12 = RTC_H12_AM;\r
- RTC_TimeStruct->RTC_Hours = 0;\r
- RTC_TimeStruct->RTC_Minutes = 0;\r
- RTC_TimeStruct->RTC_Seconds = 0; \r
-}\r
-\r
-/**\r
- * @brief Get the RTC current Time.\r
- * @param RTC_Format: specifies the format of the returned parameters.\r
- * This parameter can be one of the following values:\r
- * @arg RTC_Format_BIN: Binary data format \r
- * @arg RTC_Format_BCD: BCD data format\r
- * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will \r
- * contain the returned current time configuration. \r
- * @retval None\r
- */\r
-void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RTC_FORMAT(RTC_Format));\r
-\r
- /* Get the RTC_TR register */\r
- tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); \r
- \r
- /* Fill the structure fields with the read parameters */\r
- RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r
- RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);\r
- RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));\r
- RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); \r
-\r
- /* Check the input parameters format */\r
- if (RTC_Format == RTC_Format_BIN)\r
- {\r
- /* Convert the structure parameters to Binary format */\r
- RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);\r
- RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);\r
- RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); \r
- }\r
-}\r
-\r
-/**\r
- * @brief Set the RTC current date.\r
- * @param RTC_Format: specifies the format of the entered parameters.\r
- * This parameter can be one of the following values:\r
- * @arg RTC_Format_BIN: Binary data format \r
- * @arg RTC_Format_BCD: BCD data format\r
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains \r
- * the date configuration information for the RTC.\r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: RTC Date register is configured\r
- * - ERROR: RTC Date register is not configured\r
- */\r
-ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
- ErrorStatus status = ERROR;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RTC_FORMAT(RTC_Format));\r
-\r
- if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))\r
- {\r
- RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;\r
- } \r
- if (RTC_Format == RTC_Format_BIN)\r
- {\r
- assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));\r
- assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));\r
- assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));\r
- }\r
- else\r
- {\r
- assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));\r
- tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);\r
- assert_param(IS_RTC_MONTH(tmpreg));\r
- tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);\r
- assert_param(IS_RTC_DATE(tmpreg));\r
- }\r
- assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));\r
-\r
- /* Check the input parameters format */\r
- if (RTC_Format != RTC_Format_BIN)\r
- {\r
- tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \\r
- (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \\r
- ((uint32_t)RTC_DateStruct->RTC_Date) | \\r
- (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); \r
- } \r
- else\r
- {\r
- tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \\r
- ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \\r
- ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \\r
- ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));\r
- }\r
-\r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53;\r
-\r
- /* Set Initialization mode */\r
- if (RTC_EnterInitMode() == ERROR)\r
- {\r
- status = ERROR;\r
- } \r
- else\r
- {\r
- /* Set the RTC_DR register */\r
- RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);\r
-\r
- /* Exit Initialization mode */\r
- RTC_ExitInitMode(); \r
-\r
- if(RTC_WaitForSynchro() == ERROR)\r
- {\r
- status = ERROR;\r
- }\r
- else\r
- {\r
- status = SUCCESS;\r
- }\r
- }\r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
- \r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Fills each RTC_DateStruct member with its default value\r
- * (Monday, January 01 xx00).\r
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be \r
- * initialized.\r
- * @retval None\r
- */\r
-void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)\r
-{\r
- /* Monday, January 01 xx00 */\r
- RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;\r
- RTC_DateStruct->RTC_Date = 1;\r
- RTC_DateStruct->RTC_Month = RTC_Month_January;\r
- RTC_DateStruct->RTC_Year = 0;\r
-}\r
-\r
-/**\r
- * @brief Get the RTC current date. \r
- * @param RTC_Format: specifies the format of the returned parameters.\r
- * This parameter can be one of the following values:\r
- * @arg RTC_Format_BIN: Binary data format \r
- * @arg RTC_Format_BCD: BCD data format\r
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will \r
- * contain the returned current date configuration. \r
- * @retval None\r
- */\r
-void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RTC_FORMAT(RTC_Format));\r
- \r
- /* Get the RTC_TR register */\r
- tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); \r
-\r
- /* Fill the structure fields with the read parameters */\r
- RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);\r
- RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r
- RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));\r
- RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); \r
-\r
- /* Check the input parameters format */\r
- if (RTC_Format == RTC_Format_BIN)\r
- {\r
- /* Convert the structure parameters to Binary format */\r
- RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);\r
- RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);\r
- RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);\r
- RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay); \r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Group3 Alarms configuration functions\r
- * @brief Alarms (Alarm A and Alarm B) configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Alarms (Alarm A and Alarm B) configuration functions\r
- =============================================================================== \r
-\r
- This section provide functions allowing to program and read the RTC Alarms.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Set the specified RTC Alarm.\r
- * @note The Alarm register can only be written when the corresponding Alarm\r
- * is disabled (Use the RTC_AlarmCmd(DISABLE)). \r
- * @param RTC_Format: specifies the format of the returned parameters.\r
- * This parameter can be one of the following values:\r
- * @arg RTC_Format_BIN: Binary data format \r
- * @arg RTC_Format_BCD: BCD data format\r
- * @param RTC_Alarm: specifies the alarm to be configured.\r
- * This parameter can be one of the following values:\r
- * @arg RTC_Alarm_A: to select Alarm A\r
- * @arg RTC_Alarm_B: to select Alarm B \r
- * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that \r
- * contains the alarm configuration parameters. \r
- * @retval None\r
- */\r
-void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RTC_FORMAT(RTC_Format));\r
- assert_param(IS_RTC_ALARM(RTC_Alarm));\r
- assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));\r
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));\r
-\r
- if (RTC_Format == RTC_Format_BIN)\r
- {\r
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
- {\r
- assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));\r
- assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));\r
- } \r
- else\r
- {\r
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;\r
- assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));\r
- }\r
- assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));\r
- assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));\r
- \r
- if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)\r
- {\r
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));\r
- }\r
- else\r
- {\r
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));\r
- }\r
- }\r
- else\r
- {\r
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
- {\r
- tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);\r
- assert_param(IS_RTC_HOUR12(tmpreg));\r
- assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));\r
- } \r
- else\r
- {\r
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;\r
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));\r
- }\r
- \r
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));\r
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));\r
- \r
- if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)\r
- {\r
- tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);\r
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); \r
- }\r
- else\r
- {\r
- tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);\r
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); \r
- } \r
- }\r
-\r
- /* Check the input parameters format */\r
- if (RTC_Format != RTC_Format_BIN)\r
- {\r
- tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \\r
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \\r
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \\r
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \\r
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \\r
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \\r
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); \r
- } \r
- else\r
- {\r
- tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \\r
- ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \\r
- ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \\r
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \\r
- ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \\r
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \\r
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); \r
- } \r
-\r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53;\r
-\r
- /* Configure the Alarm register */\r
- if (RTC_Alarm == RTC_Alarm_A)\r
- {\r
- RTC->ALRMAR = (uint32_t)tmpreg;\r
- }\r
- else\r
- {\r
- RTC->ALRMBR = (uint32_t)tmpreg;\r
- }\r
-\r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
-}\r
-\r
-/**\r
- * @brief Fills each RTC_AlarmStruct member with its default value\r
- * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =\r
- * all fields are masked).\r
- * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which\r
- * will be initialized.\r
- * @retval None\r
- */\r
-void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)\r
-{\r
- /* Alarm Time Settings : Time = 00h:00mn:00sec */\r
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;\r
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;\r
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;\r
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;\r
-\r
- /* Alarm Date Settings : Date = 1st day of the month */\r
- RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;\r
- RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;\r
-\r
- /* Alarm Masks Settings : Mask = all fields are not masked */\r
- RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;\r
-}\r
-\r
-/**\r
- * @brief Get the RTC Alarm value and masks.\r
- * @param RTC_Format: specifies the format of the output parameters.\r
- * This parameter can be one of the following values:\r
- * @arg RTC_Format_BIN: Binary data format \r
- * @arg RTC_Format_BCD: BCD data format\r
- * @param RTC_Alarm: specifies the alarm to be read.\r
- * This parameter can be one of the following values:\r
- * @arg RTC_Alarm_A: to select Alarm A\r
- * @arg RTC_Alarm_B: to select Alarm B \r
- * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will \r
- * contains the output alarm configuration values. \r
- * @retval None\r
- */\r
-void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RTC_FORMAT(RTC_Format));\r
- assert_param(IS_RTC_ALARM(RTC_Alarm)); \r
-\r
- /* Get the RTC_ALRMxR register */\r
- if (RTC_Alarm == RTC_Alarm_A)\r
- {\r
- tmpreg = (uint32_t)(RTC->ALRMAR);\r
- }\r
- else\r
- {\r
- tmpreg = (uint32_t)(RTC->ALRMBR);\r
- }\r
-\r
- /* Fill the structure with the read parameters */\r
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \\r
- RTC_ALRMAR_HU)) >> 16);\r
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \\r
- RTC_ALRMAR_MNU)) >> 8);\r
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \\r
- RTC_ALRMAR_SU));\r
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);\r
- RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);\r
- RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);\r
- RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);\r
-\r
- if (RTC_Format == RTC_Format_BIN)\r
- {\r
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \\r
- RTC_AlarmTime.RTC_Hours);\r
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \\r
- RTC_AlarmTime.RTC_Minutes);\r
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \\r
- RTC_AlarmTime.RTC_Seconds);\r
- RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);\r
- } \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified RTC Alarm.\r
- * @param RTC_Alarm: specifies the alarm to be configured.\r
- * This parameter can be any combination of the following values:\r
- * @arg RTC_Alarm_A: to select Alarm A\r
- * @arg RTC_Alarm_B: to select Alarm B \r
- * @param NewState: new state of the specified alarm.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: RTC Alarm is enabled/disabled\r
- * - ERROR: RTC Alarm is not enabled/disabled \r
- */\r
-ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)\r
-{\r
- __IO uint32_t alarmcounter = 0x00;\r
- uint32_t alarmstatus = 0x00;\r
- ErrorStatus status = ERROR;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53;\r
-\r
- /* Configure the Alarm state */\r
- if (NewState != DISABLE)\r
- {\r
- RTC->CR |= (uint32_t)RTC_Alarm;\r
-\r
- status = SUCCESS; \r
- }\r
- else\r
- { \r
- /* Disable the Alarm in RTC_CR register */\r
- RTC->CR &= (uint32_t)~RTC_Alarm;\r
- \r
- /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */\r
- do\r
- {\r
- alarmstatus = RTC->ISR & (RTC_Alarm >> 8);\r
- alarmcounter++; \r
- } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));\r
- \r
- if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)\r
- {\r
- status = ERROR;\r
- } \r
- else\r
- {\r
- status = SUCCESS;\r
- } \r
- } \r
-\r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
- \r
- return status;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Group4 WakeUp Timer configuration functions\r
- * @brief WakeUp Timer configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- WakeUp Timer configuration functions\r
- =============================================================================== \r
-\r
- This section provide functions allowing to program and read the RTC WakeUp.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the RTC Wakeup clock source.\r
- * @note The WakeUp Clock source can only be changed when the RTC WakeUp\r
- * is disabled (Use the RTC_WakeUpCmd(DISABLE)). \r
- * @param RTC_WakeUpClock: Wakeup Clock source.\r
- * This parameter can be one of the following values:\r
- * @arg RTC_WakeUpClock_RTCCLK_Div16\r
- * @arg RTC_WakeUpClock_RTCCLK_Div8\r
- * @arg RTC_WakeUpClock_RTCCLK_Div4\r
- * @arg RTC_WakeUpClock_RTCCLK_Div2\r
- * @arg RTC_WakeUpClock_CK_SPRE_16bits\r
- * @arg RTC_WakeUpClock_CK_SPRE_17bits\r
- * @retval None\r
- */\r
-void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));\r
-\r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53;\r
-\r
- /* Clear the Wakeup Timer clock source bits in CR register */\r
- RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL;\r
-\r
- /* Configure the clock source */\r
- RTC->CR |= (uint32_t)RTC_WakeUpClock;\r
- \r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
-}\r
-\r
-/**\r
- * @brief Configures the RTC Wakeup counter.\r
- * @note The RTC WakeUp counter can only be written when the RTC WakeUp\r
- * is disabled (Use the RTC_WakeUpCmd(DISABLE)). \r
- * @param RTC_WakeUpCounter: specifies the WakeUp counter.\r
- * This parameter can be a value from 0x0000 to 0xFFFF. \r
- * @retval None\r
- */\r
-void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter));\r
- \r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53;\r
- \r
- /* Configure the Wakeup Timer counter */\r
- RTC->WUTR = (uint32_t)RTC_WakeUpCounter;\r
- \r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
-}\r
-\r
-/**\r
- * @brief Returns the RTC WakeUp timer counter value.\r
- * @param None\r
- * @retval The RTC WakeUp Counter value.\r
- */\r
-uint32_t RTC_GetWakeUpCounter(void)\r
-{\r
- /* Get the counter value */\r
- return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT));\r
-}\r
-\r
-/**\r
- * @brief Enables or Disables the RTC WakeUp timer.\r
- * @param NewState: new state of the WakeUp timer.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)\r
-{\r
- __IO uint32_t wutcounter = 0x00;\r
- uint32_t wutwfstatus = 0x00;\r
- ErrorStatus status = ERROR;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53;\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the Wakeup Timer */\r
- RTC->CR |= (uint32_t)RTC_CR_WUTE;\r
- status = SUCCESS; \r
- }\r
- else\r
- {\r
- /* Disable the Wakeup Timer */\r
- RTC->CR &= (uint32_t)~RTC_CR_WUTE;\r
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r
- do\r
- {\r
- wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;\r
- wutcounter++; \r
- } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));\r
- \r
- if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)\r
- {\r
- status = ERROR;\r
- }\r
- else\r
- {\r
- status = SUCCESS;\r
- } \r
- }\r
-\r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
- \r
- return status;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Group5 Daylight Saving configuration functions\r
- * @brief Daylight Saving configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Daylight Saving configuration functions\r
- =============================================================================== \r
-\r
- This section provide functions allowing to configure the RTC DayLight Saving.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Adds or substract one hour from the current time.\r
- * @param RTC_DayLightSaveOperation: the value of hour adjustment. \r
- * This parameter can be one of the following values:\r
- * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)\r
- * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)\r
- * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit \r
- * in CR register to store the operation.\r
- * This parameter can be one of the following values:\r
- * @arg RTC_StoreOperation_Reset\r
- * @arg RTC_StoreOperation_Set\r
- * @retval None\r
- */\r
-void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));\r
- assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));\r
-\r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53;\r
-\r
- /* Clear the bits to be configured */\r
- RTC->CR &= (uint32_t)~(RTC_CR_BCK);\r
-\r
- /* Configure the RTC_CR register */\r
- RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);\r
-\r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
-}\r
-\r
-/**\r
- * @brief Returns the RTC Day Light Saving stored operation.\r
- * @param None\r
- * @retval RTC Day Light Saving stored operation.\r
- * - RTC_StoreOperation_Reset\r
- * - RTC_StoreOperation_Set \r
- */\r
-uint32_t RTC_GetStoreOperation(void)\r
-{\r
- return (RTC->CR & RTC_CR_BCK);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Group6 Output pin Configuration function\r
- * @brief Output pin Configuration function \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Output pin Configuration function\r
- =============================================================================== \r
-\r
- This section provide functions allowing to configure the RTC Output source.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the RTC output source (AFO_ALARM).\r
- * @param RTC_Output: Specifies which signal will be routed to the RTC output. \r
- * This parameter can be one of the following values:\r
- * @arg RTC_Output_Disable: No output selected\r
- * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output\r
- * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output\r
- * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output\r
- * @param RTC_OutputPolarity: Specifies the polarity of the output signal. \r
- * This parameter can be one of the following:\r
- * @arg RTC_OutputPolarity_High: The output pin is high when the \r
- * ALRAF/ALRBF/WUTF is high (depending on OSEL)\r
- * @arg RTC_OutputPolarity_Low: The output pin is low when the \r
- * ALRAF/ALRBF/WUTF is high (depending on OSEL)\r
- * @retval None\r
- */\r
-void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RTC_OUTPUT(RTC_Output));\r
- assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));\r
-\r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53;\r
-\r
- /* Clear the bits to be configured */\r
- RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);\r
-\r
- /* Configure the output selection and polarity */\r
- RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);\r
-\r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Group7 Digital Calibration configuration functions\r
- * @brief Digital Calibration configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Digital Calibration configuration functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the digital calibration parameters.\r
- * @param RTC_CalibSign: specifies the sign of the calibration value.\r
- * This parameter can be one of the following values:\r
- * @arg RTC_CalibSign_Positive: The value sign is positive \r
- * @arg RTC_CalibSign_Negative: The value sign is negative\r
- * @param Value: value of calibration expressed in ppm (coded on 5 bits) \r
- * - This value should be between 0 and 63 when using negative sign\r
- * with a 2-ppm step.\r
- * - This value should be between 0 and 126 when using positive sign\r
- * with a 4-ppm step.\r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: RTC digital calibration are initialized\r
- * - ERROR: RTC digital calibration are not initialized \r
- */\r
-ErrorStatus RTC_DigitalCalibConfig(uint32_t RTC_CalibSign, uint32_t Value)\r
-{\r
- ErrorStatus status = ERROR;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign));\r
- assert_param(IS_RTC_CALIB_VALUE(Value)); \r
-\r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53;\r
-\r
- /* Set Initialization mode */\r
- if (RTC_EnterInitMode() == ERROR)\r
- {\r
- status = ERROR;\r
- } \r
- else\r
- {\r
- /* Set the calibration value */\r
- RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value);\r
- /* Exit Initialization mode */\r
- RTC_ExitInitMode();\r
- \r
- status = SUCCESS;\r
- } \r
-\r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
- \r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the digital calibration process.\r
- * @param NewState: new state of the digital calibration.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: RTC digital calibration are enabled/disabled\r
- * - ERROR: RTC digital calibration are not enabled/disabled \r
- */\r
-ErrorStatus RTC_DigitalCalibCmd(FunctionalState NewState)\r
-{\r
- ErrorStatus status = ERROR;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53;\r
- \r
- /* Set Initialization mode */\r
- if (RTC_EnterInitMode() == ERROR)\r
- {\r
- status = ERROR;\r
- }\r
- else\r
- {\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the Digital Calibration */\r
- RTC->CR |= (uint32_t)RTC_CR_DCE;\r
- }\r
- else\r
- { \r
- /* Disable the Digital Calibration */\r
- RTC->CR &= (uint32_t)~RTC_CR_DCE;\r
- }\r
- /* Exit Initialization mode */\r
- RTC_ExitInitMode();\r
- \r
- status = SUCCESS;\r
- } \r
- \r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
- \r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the RTC clock to be output through the relative \r
- * pin.\r
- * @param NewState: new state of the digital calibration Output.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RTC_CalibOutputCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53;\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the RTC clock output */\r
- RTC->CR |= (uint32_t)RTC_CR_COE;\r
- }\r
- else\r
- { \r
- /* Disable the RTC clock output */\r
- RTC->CR &= (uint32_t)~RTC_CR_COE;\r
- }\r
- \r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup RTC_Group8 TimeStamp configuration functions\r
- * @brief TimeStamp configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- TimeStamp configuration functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or Disables the RTC TimeStamp functionality with the \r
- * specified time stamp pin stimulating edge.\r
- * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is \r
- * activated.\r
- * This parameter can be one of the following:\r
- * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising \r
- * edge of the related pin.\r
- * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the \r
- * falling edge of the related pin.\r
- * @param NewState: new state of the TimeStamp.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- /* Get the RTC_CR register and clear the bits to be configured */\r
- tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));\r
-\r
- /* Get the new configuration */\r
- if (NewState != DISABLE)\r
- {\r
- tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);\r
- }\r
- else\r
- {\r
- tmpreg |= (uint32_t)(RTC_TimeStampEdge);\r
- }\r
-\r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53;\r
-\r
- /* Configure the Time Stamp TSEDGE and Enable bits */\r
- RTC->CR = (uint32_t)tmpreg;\r
-\r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
-}\r
-\r
-/**\r
- * @brief Get the RTC TimeStamp value and masks.\r
- * @param RTC_Format: specifies the format of the output parameters.\r
- * This parameter can be one of the following values:\r
- * @arg RTC_Format_BIN: Binary data format \r
- * @arg RTC_Format_BCD: BCD data format\r
- * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will \r
- * contains the TimeStamp time values. \r
- * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will \r
- * contains the TimeStamp date values. \r
- * @retval None\r
- */\r
-void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, \r
- RTC_DateTypeDef* RTC_StampDateStruct)\r
-{\r
- uint32_t tmptime = 0, tmpdate = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RTC_FORMAT(RTC_Format));\r
-\r
- /* Get the TimeStamp time and date registers values */\r
- tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);\r
- tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);\r
-\r
- /* Fill the Time structure fields with the read parameters */\r
- RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r
- RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);\r
- RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));\r
- RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); \r
-\r
- /* Fill the Date structure fields with the read parameters */\r
- RTC_StampDateStruct->RTC_Year = 0;\r
- RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r
- RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));\r
- RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);\r
-\r
- /* Check the input parameters format */\r
- if (RTC_Format == RTC_Format_BIN)\r
- {\r
- /* Convert the Time structure parameters to Binary format */\r
- RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);\r
- RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);\r
- RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);\r
-\r
- /* Convert the Date structure parameters to Binary format */\r
- RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);\r
- RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);\r
- RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Group9 Tampers configuration functions\r
- * @brief Tampers configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Tampers configuration functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the select Tamper pin edge.\r
- * @param RTC_Tamper: Selected tamper pin.\r
- * This parameter can be RTC_Tamper_1.\r
- * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that \r
- * stimulates tamper event. \r
- * This parameter can be one of the following values:\r
- * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.\r
- * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. \r
- * @retval None\r
- */\r
-void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RTC_TAMPER(RTC_Tamper)); \r
- assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));\r
- \r
- if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)\r
- { \r
- /* Configure the RTC_TAFCR register */\r
- RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); \r
- }\r
- else\r
- { \r
- /* Configure the RTC_TAFCR register */\r
- RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); \r
- } \r
-}\r
-\r
-/**\r
- * @brief Enables or Disables the Tamper detection.\r
- * @param RTC_Tamper: Selected tamper pin.\r
- * This parameter can be RTC_Tamper_1.\r
- * @param NewState: new state of the tamper pin.\r
- * This parameter can be: ENABLE or DISABLE. \r
- * @retval None\r
- */\r
-void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RTC_TAMPER(RTC_Tamper)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected Tamper pin */\r
- RTC->TAFCR |= (uint32_t)RTC_Tamper;\r
- }\r
- else\r
- {\r
- /* Disable the selected Tamper pin */\r
- RTC->TAFCR &= (uint32_t)~RTC_Tamper; \r
- } \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Group10 Backup Data Registers configuration functions\r
- * @brief Backup Data Registers configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Backup Data Registers configuration functions \r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Writes a data in a specified RTC Backup data register.\r
- * @param RTC_BKP_DR: RTC Backup data Register number.\r
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r
- * specify the register.\r
- * @param Data: Data to be written in the specified RTC Backup data register. \r
- * @retval None\r
- */\r
-void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)\r
-{\r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RTC_BKP(RTC_BKP_DR));\r
-\r
- tmp = RTC_BASE + 0x50;\r
- tmp += (RTC_BKP_DR * 4);\r
-\r
- /* Write the specified register */\r
- *(__IO uint32_t *)tmp = (uint32_t)Data;\r
-}\r
-\r
-/**\r
- * @brief Reads data from the specified RTC Backup data Register.\r
- * @param RTC_BKP_DR: RTC Backup data Register number.\r
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r
- * specify the register. \r
- * @retval None\r
- */\r
-uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)\r
-{\r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RTC_BKP(RTC_BKP_DR));\r
-\r
- tmp = RTC_BASE + 0x50;\r
- tmp += (RTC_BKP_DR * 4);\r
- \r
- /* Read the specified register */\r
- return (*(__IO uint32_t *)tmp);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Group11 Output Type Config configuration functions\r
- * @brief Output Type Config configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Output Type Config configuration functions \r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the RTC Output Pin mode. \r
- * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode.\r
- * This parameter can be one of the following values:\r
- * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in \r
- * Open Drain mode.\r
- * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in \r
- * Push Pull mode. \r
- * @retval None\r
- */\r
-void RTC_OutputTypeConfig(uint32_t RTC_OutputType)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));\r
- \r
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);\r
- RTC->TAFCR |= (uint32_t)(RTC_OutputType); \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Group12 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Interrupts and flags management functions\r
- =============================================================================== \r
- All RTC interrupts are connected to the EXTI controller.\r
- \r
- - To enable the RTC Alarm interrupt, the following sequence is required:\r
- - Configure and enable the EXTI Line 17 in interrupt mode and select the rising \r
- edge sensitivity using the EXTI_Init() function.\r
- - Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init()\r
- function.\r
- - Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using\r
- the RTC_SetAlarm() and RTC_AlarmCmd() functions.\r
-\r
- - To enable the RTC Wakeup interrupt, the following sequence is required:\r
- - Configure and enable the EXTI Line 20 in interrupt mode and select the rising \r
- edge sensitivity using the EXTI_Init() function.\r
- - Configure and enable the RTC_WKUP IRQ channel in the NVIC using the NVIC_Init()\r
- function.\r
- - Configure the RTC to generate the RTC wakeup timer event using the \r
- RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.\r
-\r
- - To enable the RTC Tamper interrupt, the following sequence is required:\r
- - Configure and enable the EXTI Line 19 in interrupt mode and select the rising \r
- edge sensitivity using the EXTI_Init() function.\r
- - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()\r
- function.\r
- - Configure the RTC to detect the RTC tamper event using the \r
- RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.\r
-\r
- - To enable the RTC TimeStamp interrupt, the following sequence is required:\r
- - Configure and enable the EXTI Line 19 in interrupt mode and select the rising \r
- edge sensitivity using the EXTI_Init() function.\r
- - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()\r
- function.\r
- - Configure the RTC to detect the RTC time-stamp event using the \r
- RTC_TimeStampCmd() functions.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified RTC interrupts.\r
- * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. \r
- * This parameter can be any combination of the following values:\r
- * @arg RTC_IT_TS: Time Stamp interrupt mask\r
- * @arg RTC_IT_WUT: WakeUp Timer interrupt mask\r
- * @arg RTC_IT_ALRB: Alarm B interrupt mask\r
- * @arg RTC_IT_ALRA: Alarm A interrupt mask\r
- * @arg RTC_IT_TAMP: Tamper event interrupt mask\r
- * @param NewState: new state of the specified RTC interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RTC_CONFIG_IT(RTC_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- /* Disable the write protection for RTC registers */\r
- RTC->WPR = 0xCA;\r
- RTC->WPR = 0x53;\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Configure the Interrupts in the RTC_CR register */\r
- RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);\r
- /* Configure the Tamper Interrupt in the RTC_TAFCR */\r
- RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);\r
- }\r
- else\r
- {\r
- /* Configure the Interrupts in the RTC_CR register */\r
- RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);\r
- /* Configure the Tamper Interrupt in the RTC_TAFCR */\r
- RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);\r
- }\r
- /* Enable the write protection for RTC registers */\r
- RTC->WPR = 0xFF; \r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified RTC flag is set or not.\r
- * @param RTC_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag\r
- * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag\r
- * @arg RTC_FLAG_TSF: Time Stamp event flag\r
- * @arg RTC_FLAG_WUTF: WakeUp Timer flag\r
- * @arg RTC_FLAG_ALRBF: Alarm B flag\r
- * @arg RTC_FLAG_ALRAF: Alarm A flag\r
- * @arg RTC_FLAG_INITF: Initialization mode flag\r
- * @arg RTC_FLAG_RSF: Registers Synchronized flag\r
- * @arg RTC_FLAG_INITS: Registers Configured flag\r
- * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag\r
- * @arg RTC_FLAG_ALRBWF: Alarm B Write flag\r
- * @arg RTC_FLAG_ALRAWF: Alarm A write flag\r
- * @retval The new state of RTC_FLAG (SET or RESET).\r
- */\r
-FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RTC_GET_FLAG(RTC_FLAG));\r
- \r
- /* Get all the flags */\r
- tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);\r
- \r
- /* Return the status of the flag */\r
- if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the RTC's pending flags.\r
- * @param RTC_FLAG: specifies the RTC flag to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag\r
- * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag \r
- * @arg RTC_FLAG_TSF: Time Stamp event flag\r
- * @arg RTC_FLAG_WUTF: WakeUp Timer flag\r
- * @arg RTC_FLAG_ALRBF: Alarm B flag\r
- * @arg RTC_FLAG_ALRAF: Alarm A flag\r
- * @arg RTC_FLAG_RSF: Registers Synchronized flag\r
- * @retval None\r
- */\r
-void RTC_ClearFlag(uint32_t RTC_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));\r
-\r
- /* Clear the Flags in the RTC_ISR register */\r
- RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); \r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified RTC interrupt has occurred or not.\r
- * @param RTC_IT: specifies the RTC interrupt source to check.\r
- * This parameter can be one of the following values:\r
- * @arg RTC_IT_TS: Time Stamp interrupt \r
- * @arg RTC_IT_WUT: WakeUp Timer interrupt \r
- * @arg RTC_IT_ALRB: Alarm B interrupt \r
- * @arg RTC_IT_ALRA: Alarm A interrupt \r
- * @arg RTC_IT_TAMP1: Tamper 1 event interrupt \r
- * @retval The new state of RTC_IT (SET or RESET).\r
- */\r
-ITStatus RTC_GetITStatus(uint32_t RTC_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t tmpreg = 0, enablestatus = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RTC_GET_IT(RTC_IT));\r
- \r
- /* Get the TAMPER Interrupt enable bit and pending bit */\r
- tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));\r
- \r
- /* Get the Interrupt enable Status */\r
- enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15)));\r
- \r
- /* Get the Interrupt pending bit */\r
- tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));\r
- \r
- /* Get the status of the Interrupt */\r
- if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the RTC's interrupt pending bits.\r
- * @param RTC_IT: specifies the RTC interrupt pending bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg RTC_IT_TS: Time Stamp interrupt \r
- * @arg RTC_IT_WUT: WakeUp Timer interrupt \r
- * @arg RTC_IT_ALRB: Alarm B interrupt \r
- * @arg RTC_IT_ALRA: Alarm A interrupt \r
- * @arg RTC_IT_TAMP1: Tamper 1 event interrupt \r
- * @retval None\r
- */\r
-void RTC_ClearITPendingBit(uint32_t RTC_IT)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RTC_CLEAR_IT(RTC_IT));\r
-\r
- /* Get the RTC_ISR Interrupt pending bits mask */\r
- tmpreg = (uint32_t)(RTC_IT >> 4);\r
-\r
- /* Clear the interrupt pending bits in the RTC_ISR register */\r
- RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @brief Converts a 2 digit decimal to BCD format.\r
- * @param Value: Byte to be converted.\r
- * @retval Converted byte\r
- */\r
-static uint8_t RTC_ByteToBcd2(uint8_t Value)\r
-{\r
- uint8_t bcdhigh = 0;\r
- \r
- while (Value >= 10)\r
- {\r
- bcdhigh++;\r
- Value -= 10;\r
- }\r
- \r
- return ((uint8_t)(bcdhigh << 4) | Value);\r
-}\r
-\r
-/**\r
- * @brief Convert from 2 digit BCD to Binary.\r
- * @param Value: BCD value to be converted.\r
- * @retval Converted word\r
- */\r
-static uint8_t RTC_Bcd2ToByte(uint8_t Value)\r
-{\r
- uint8_t tmp = 0;\r
- tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;\r
- return (tmp + (Value & (uint8_t)0x0F));\r
-}\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_spi.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Serial peripheral interface (SPI): \r
- * - Initialization and Configuration\r
- * - Data transfers functions\r
- * - Hardware CRC Calculation\r
- * - DMA transfers management\r
- * - Interrupts and flags management \r
- * \r
- * @verbatim\r
- * \r
- * The I2S feature is not implemented in STM32L1xx Ultra Low Power\r
- * Medium-density devices and will be supported in future products.\r
- * \r
- * ===================================================================\r
- * How to use this driver\r
- * ===================================================================\r
- * 1. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)\r
- * function for SPI1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)\r
- * function for SPI2.\r
- *\r
- * 2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHBPeriphClockCmd()\r
- * function. \r
- *\r
- * 3. Peripherals alternate function: \r
- * - Connect the pin to the desired peripherals' Alternate \r
- * Function (AF) using GPIO_PinAFConfig() function\r
- * - Configure the desired pin in alternate function by:\r
- * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
- * - Select the type, pull-up/pull-down and output speed via \r
- * GPIO_PuPd, GPIO_OType and GPIO_Speed members\r
- * - Call GPIO_Init() function\r
- * \r
- * 4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave \r
- * Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()\r
- * function.\r
- *\r
- * 5. Enable the NVIC and the corresponding interrupt using the function \r
- * SPI_ITConfig() if you need to use interrupt mode. \r
- *\r
- * 6. When using the DMA mode \r
- * - Configure the DMA using DMA_Init() function\r
- * - Active the needed channel Request using SPI_I2S_DMACmd() function\r
- * \r
- * 7. Enable the SPI using the SPI_Cmd() function.\r
- * \r
- * 8. Enable the DMA using the DMA_Cmd() function when using DMA mode. \r
- *\r
- * 9. Optionally you can enable/configure the following parameters without\r
- * re-initialization (i.e there is no need to call again SPI_Init() function):\r
- * - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)\r
- * is programmed as Data direction parameter using the SPI_Init() function\r
- * it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx\r
- * using the SPI_BiDirectionalLineConfig() function.\r
- * - When SPI_NSS_Soft is selected as Slave Select Management parameter \r
- * using the SPI_Init() function it can be possible to manage the \r
- * NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.\r
- * - Reconfigure the data size using the SPI_DataSizeConfig() function \r
- * - Enable or disable the SS output using the SPI_SSOutputCmd() function \r
- * \r
- * 10. To use the CRC Hardware calculation feature refer to the Peripheral \r
- * CRC hardware Calculation subsection.\r
- *\r
- * @endverbatim \r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_spi.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup SPI \r
- * @brief SPI driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* SPI registers Masks */\r
-#define CR1_CLEAR_MASK ((uint16_t)0x3040)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup SPI_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup SPI_Group1 Initialization and Configuration functions\r
- * @brief Initialization and Configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Initialization and Configuration functions\r
- =============================================================================== \r
-\r
- This section provides a set of functions allowing to initialize the SPI Direction,\r
- SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud\r
- Rate Prescaler, SPI First Bit and SPI CRC Polynomial.\r
- \r
- The SPI_Init() function follows the SPI configuration procedures for Master mode\r
- and Slave mode (details for these procedures are available in reference manual\r
- (RM0038)).\r
- \r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the SPIx peripheral registers to their default\r
- * reset values.\r
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
- * @retval None\r
- */\r
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
-\r
- if (SPIx == SPI1)\r
- {\r
- /* Enable SPI1 reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);\r
- /* Release SPI1 from reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);\r
- }\r
- else\r
- {\r
- if (SPIx == SPI2)\r
- {\r
- /* Enable SPI2 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);\r
- /* Release SPI2 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the SPIx peripheral according to the specified \r
- * parameters in the SPI_InitStruct.\r
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that\r
- * contains the configuration information for the specified SPI peripheral.\r
- * @retval None\r
- */\r
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)\r
-{\r
- uint16_t tmpreg = 0;\r
- \r
- /* check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- \r
- /* Check the SPI parameters */\r
- assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));\r
- assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));\r
- assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));\r
- assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));\r
- assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));\r
- assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));\r
- assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));\r
- assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));\r
- assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));\r
-\r
-/*---------------------------- SPIx CR1 Configuration ------------------------*/\r
- /* Get the SPIx CR1 value */\r
- tmpreg = SPIx->CR1;\r
- /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */\r
- tmpreg &= CR1_CLEAR_MASK;\r
- /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler\r
- master/salve mode, CPOL and CPHA */\r
- /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */\r
- /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */\r
- /* Set LSBFirst bit according to SPI_FirstBit value */\r
- /* Set BR bits according to SPI_BaudRatePrescaler value */\r
- /* Set CPOL bit according to SPI_CPOL value */\r
- /* Set CPHA bit according to SPI_CPHA value */\r
- tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |\r
- SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | \r
- SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | \r
- SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);\r
- /* Write to SPIx CR1 */\r
- SPIx->CR1 = tmpreg;\r
- \r
-/*---------------------------- SPIx CRCPOLY Configuration --------------------*/\r
- /* Write to SPIx CRCPOLY */\r
- SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;\r
-}\r
-\r
-/**\r
- * @brief Fills each SPI_InitStruct member with its default value.\r
- * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.\r
- * @retval None\r
- */\r
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)\r
-{\r
-/*--------------- Reset SPI init structure parameters values -----------------*/\r
- /* Initialize the SPI_Direction member */\r
- SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
- /* initialize the SPI_Mode member */\r
- SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;\r
- /* initialize the SPI_DataSize member */\r
- SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;\r
- /* Initialize the SPI_CPOL member */\r
- SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;\r
- /* Initialize the SPI_CPHA member */\r
- SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;\r
- /* Initialize the SPI_NSS member */\r
- SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;\r
- /* Initialize the SPI_BaudRatePrescaler member */\r
- SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
- /* Initialize the SPI_FirstBit member */\r
- SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;\r
- /* Initialize the SPI_CRCPolynomial member */\r
- SPI_InitStruct->SPI_CRCPolynomial = 7;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified SPI peripheral.\r
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
- * @param NewState: new state of the SPIx peripheral. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI peripheral */\r
- SPIx->CR1 |= SPI_CR1_SPE;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI peripheral */\r
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the data size for the selected SPI.\r
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
- * @param SPI_DataSize: specifies the SPI data size.\r
- * This parameter can be one of the following values:\r
- * @arg SPI_DataSize_16b: Set data frame format to 16bit\r
- * @arg SPI_DataSize_8b: Set data frame format to 8bit\r
- * @retval None\r
- */\r
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_DATASIZE(SPI_DataSize));\r
- /* Clear DFF bit */\r
- SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;\r
- /* Set new DFF bit value */\r
- SPIx->CR1 |= SPI_DataSize;\r
-}\r
-\r
-/**\r
- * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.\r
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
- * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. \r
- * This parameter can be one of the following values:\r
- * @arg SPI_Direction_Tx: Selects Tx transmission direction\r
- * @arg SPI_Direction_Rx: Selects Rx receive direction\r
- * @retval None\r
- */\r
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_DIRECTION(SPI_Direction));\r
- if (SPI_Direction == SPI_Direction_Tx)\r
- {\r
- /* Set the Tx only mode */\r
- SPIx->CR1 |= SPI_Direction_Tx;\r
- }\r
- else\r
- {\r
- /* Set the Rx only mode */\r
- SPIx->CR1 &= SPI_Direction_Rx;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures internally by software the NSS pin for the selected SPI.\r
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
- * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.\r
- * This parameter can be one of the following values:\r
- * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally\r
- * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally\r
- * @retval None\r
- */\r
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));\r
- if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)\r
- {\r
- /* Set NSS pin internally by software */\r
- SPIx->CR1 |= SPI_NSSInternalSoft_Set;\r
- }\r
- else\r
- {\r
- /* Reset NSS pin internally by software */\r
- SPIx->CR1 &= SPI_NSSInternalSoft_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SS output for the selected SPI.\r
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
- * @param NewState: new state of the SPIx SS output. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI SS output */\r
- SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI SS output */\r
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Group2 Data transfers functions\r
- * @brief Data transfers functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- Data transfers functions\r
- =============================================================================== \r
-\r
- This section provides a set of functions allowing to manage the SPI data transfers\r
- \r
- In reception, data are received and then stored into an internal Rx buffer while \r
- In transmission, data are first stored into an internal Tx buffer before being \r
- transmitted.\r
-\r
- The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()\r
- function and returns the Rx buffered value. Whereas a write access to the SPI_DR \r
- can be done using SPI_I2S_SendData() function and stores the written data into \r
- Tx buffer.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Returns the most recent received data by the SPIx peripheral. \r
- * @param SPIx: where x can be 1 or 2 in SPI mode.\r
- * @retval The value of the received data.\r
- */\r
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- \r
- /* Return the data in the DR register */\r
- return SPIx->DR;\r
-}\r
-\r
-/**\r
- * @brief Transmits a Data through the SPIx peripheral.\r
- * @param SPIx: where x can be 1 or 2 in SPI mode. \r
- * @param Data: Data to be transmitted.\r
- * @retval None\r
- */\r
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- \r
- /* Write in the DR register the data to be sent */\r
- SPIx->DR = Data;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Group3 Hardware CRC Calculation functions\r
- * @brief Hardware CRC Calculation functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- Hardware CRC Calculation functions\r
- =============================================================================== \r
-\r
- This section provides a set of functions allowing to manage the SPI CRC hardware \r
- calculation\r
-\r
- SPI communication using CRC is possible through the following procedure:\r
- 1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, \r
- Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()\r
- function.\r
- 2. Enable the CRC calculation using the SPI_CalculateCRC() function.\r
- 3. Enable the SPI using the SPI_Cmd() function\r
- 4. Before writing the last data to the TX buffer, set the CRCNext bit using the \r
- SPI_TransmitCRC() function to indicate that after transmission of the last \r
- data, the CRC should be transmitted.\r
- 5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT\r
- bit is reset. The CRC is also received and compared against the SPI_RXCRCR \r
- value. \r
- If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt\r
- can be generated when the SPI_I2S_IT_ERR interrupt is enabled.\r
-\r
-Note: \r
------\r
- - It is advised to don't read the calculate CRC values during the communication.\r
-\r
- - When the SPI is in slave mode, be careful to enable CRC calculation only \r
- when the clock is stable, that is, when the clock is in the steady state. \r
- If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive \r
- to the SCK slave input clock as soon as CRCEN is set, and this, whatever \r
- the value of the SPE bit.\r
-\r
- - With high bitrate frequencies, be careful when transmitting the CRC.\r
- As the number of used CPU cycles has to be as low as possible in the CRC \r
- transfer phase, it is forbidden to call software functions in the CRC \r
- transmission sequence to avoid errors in the last data and CRC reception. \r
- In fact, CRCNEXT bit has to be written before the end of the transmission/reception \r
- of the last data.\r
-\r
- - For high bit rate frequencies, it is advised to use the DMA mode to avoid the\r
- degradation of the SPI speed performance due to CPU accesses impacting the \r
- SPI bandwidth.\r
-\r
- - When the STM32L15xxx are configured as slaves and the NSS hardware mode is \r
- used, the NSS pin needs to be kept low between the data phase and the CRC \r
- phase.\r
-\r
- - When the SPI is configured in slave mode with the CRC feature enabled, CRC\r
- calculation takes place even if a high level is applied on the NSS pin. \r
- This may happen for example in case of a multislave environment where the \r
- communication master addresses slaves alternately.\r
-\r
- - Between a slave deselection (high level on NSS) and a new slave selection \r
- (low level on NSS), the CRC value should be cleared on both master and slave\r
- sides in order to resynchronize the master and slave for their respective \r
- CRC calculation.\r
-\r
- To clear the CRC, follow the procedure below:\r
- 1. Disable SPI using the SPI_Cmd() function\r
- 2. Disable the CRC calculation using the SPI_CalculateCRC() function.\r
- 3. Enable the CRC calculation using the SPI_CalculateCRC() function.\r
- 4. Enable SPI using the SPI_Cmd() function.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the CRC value calculation of the transferred bytes.\r
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
- * @param NewState: new state of the SPIx CRC value calculation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI CRC calculation */\r
- SPIx->CR1 |= SPI_CR1_CRCEN;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI CRC calculation */\r
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Transmit the SPIx CRC value.\r
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
- * @retval None\r
- */\r
-void SPI_TransmitCRC(SPI_TypeDef* SPIx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- \r
- /* Enable the selected SPI CRC transmission */\r
- SPIx->CR1 |= SPI_CR1_CRCNEXT;\r
-}\r
-\r
-/**\r
- * @brief Returns the transmit or the receive CRC register value for the specified SPI.\r
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
- * @param SPI_CRC: specifies the CRC register to be read.\r
- * This parameter can be one of the following values:\r
- * @arg SPI_CRC_Tx: Selects Tx CRC register\r
- * @arg SPI_CRC_Rx: Selects Rx CRC register\r
- * @retval The selected CRC register value..\r
- */\r
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)\r
-{\r
- uint16_t crcreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_CRC(SPI_CRC));\r
- if (SPI_CRC != SPI_CRC_Rx)\r
- {\r
- /* Get the Tx CRC register */\r
- crcreg = SPIx->TXCRCR;\r
- }\r
- else\r
- {\r
- /* Get the Rx CRC register */\r
- crcreg = SPIx->RXCRCR;\r
- }\r
- /* Return the selected CRC register */\r
- return crcreg;\r
-}\r
-\r
-/**\r
- * @brief Returns the CRC Polynomial register value for the specified SPI.\r
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
- * @retval The CRC Polynomial register value.\r
- */\r
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- \r
- /* Return the CRC polynomial register */\r
- return SPIx->CRCPR;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Group4 DMA transfers management functions\r
- * @brief DMA transfers management functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- DMA transfers management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the SPIx DMA interface.\r
- * @param SPIx: where x can be 1 or 2 in SPI mode \r
- * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. \r
- * This parameter can be any combination of the following values:\r
- * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request\r
- * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request\r
- * @param NewState: new state of the selected SPI DMA transfer request.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI DMA requests */\r
- SPIx->CR2 |= SPI_I2S_DMAReq;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI DMA requests */\r
- SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Group5 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- Interrupts and flags management functions\r
- =============================================================================== \r
-\r
- This section provides a set of functions allowing to configure the SPI Interrupts \r
- sources and check or clear the flags or pending bits status.\r
- The user should identify which mode will be used in his application to manage \r
- the communication: Polling mode, Interrupt mode or DMA mode. \r
- \r
- Polling Mode\r
- =============\r
- In Polling Mode, the SPI communication can be managed by 6 flags:\r
- 1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register\r
- 2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register\r
- 3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.\r
- 4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur \r
- 5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur\r
- 6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur\r
-\r
-Note: Do not use the BSY flag to handle each data transmission or reception.\r
------ It is better to use the TXE and RXNE flags instead.\r
-\r
- In this Mode it is advised to use the following functions:\r
- - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
- - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
-\r
- Interrupt Mode\r
- ===============\r
- In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources\r
- and 5 pending bits: \r
- Pending Bits:\r
- ------------- \r
- 1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register\r
- 2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register\r
- 3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur \r
- 4. SPI_IT_MODF : to indicate if a Mode Fault error occur\r
- 5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur\r
-\r
- Interrupt Source:\r
- -----------------\r
- 1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty \r
- interrupt. \r
- 2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not \r
- empty interrupt.\r
- 3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.\r
-\r
- In this Mode it is advised to use the following functions:\r
- - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);\r
- - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
- - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
-\r
- DMA Mode\r
- ========\r
- In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:\r
- 1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request\r
- 2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request\r
-\r
- In this Mode it is advised to use the following function:\r
- - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified SPI interrupts.\r
- * @param SPIx: where x can be 1 or 2 in SPI mode \r
- * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. \r
- * This parameter can be one of the following values:\r
- * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask\r
- * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask\r
- * @arg SPI_I2S_IT_ERR: Error interrupt mask\r
- * @param NewState: new state of the specified SPI interrupt.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)\r
-{\r
- uint16_t itpos = 0, itmask = 0 ;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));\r
-\r
- /* Get the SPI IT index */\r
- itpos = SPI_I2S_IT >> 4;\r
-\r
- /* Set the IT mask */\r
- itmask = (uint16_t)1 << (uint16_t)itpos;\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI interrupt */\r
- SPIx->CR2 |= itmask;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI interrupt */\r
- SPIx->CR2 &= (uint16_t)~itmask;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified SPI flag is set or not.\r
- * @param SPIx: where x can be 1 or 2 in SPI mode \r
- * @param SPI_I2S_FLAG: specifies the SPI flag to check. \r
- * This parameter can be one of the following values:\r
- * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.\r
- * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.\r
- * @arg SPI_I2S_FLAG_BSY: Busy flag.\r
- * @arg SPI_I2S_FLAG_OVR: Overrun flag.\r
- * @arg SPI_I2S_FLAG_MODF: Mode Fault flag.\r
- * @arg SPI_I2S_FLAG_CRCERR: CRC Error flag.\r
- * @retval The new state of SPI_I2S_FLAG (SET or RESET).\r
- */\r
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));\r
- \r
- /* Check the status of the specified SPI flag */\r
- if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)\r
- {\r
- /* SPI_I2S_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* SPI_I2S_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the SPI_I2S_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the SPIx CRC Error (CRCERR) flag.\r
- * @param SPIx: where x can be 1 or 2 in SPI mode \r
- * @param SPI_I2S_FLAG: specifies the SPI flag to clear. \r
- * This function clears only CRCERR flag.\r
- * @note\r
- * - OVR (OverRun error) flag is cleared by software sequence: a read \r
- * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read \r
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).\r
- * - MODF (Mode Fault) flag is cleared by software sequence: a read/write \r
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a \r
- * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).\r
- * @retval None\r
- */\r
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));\r
- \r
- /* Clear the selected SPI CRC Error (CRCERR) flag */\r
- SPIx->SR = (uint16_t)~SPI_I2S_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified SPI interrupt has occurred or not.\r
- * @param SPIx: where x can be\r
- * - 1 or 2 in SPI mode \r
- * @param SPI_I2S_IT: specifies the SPI interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.\r
- * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.\r
- * @arg SPI_I2S_IT_OVR: Overrun interrupt.\r
- * @arg SPI_I2S_IT_MODF: Mode Fault interrupt.\r
- * @arg SPI_I2S_IT_CRCERR: CRC Error interrupt.\r
- * @retval The new state of SPI_I2S_IT (SET or RESET).\r
- */\r
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint16_t itpos = 0, itmask = 0, enablestatus = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));\r
-\r
- /* Get the SPI_I2S_IT index */\r
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
-\r
- /* Get the SPI_I2S_IT IT mask */\r
- itmask = SPI_I2S_IT >> 4;\r
-\r
- /* Set the IT mask */\r
- itmask = 0x01 << itmask;\r
-\r
- /* Get the SPI_I2S_IT enable bit status */\r
- enablestatus = (SPIx->CR2 & itmask) ;\r
-\r
- /* Check the status of the specified SPI interrupt */\r
- if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)\r
- {\r
- /* SPI_I2S_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* SPI_I2S_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the SPI_I2S_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.\r
- * @param SPIx: where x can be\r
- * - 1 or 2 in SPI mode \r
- * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.\r
- * This function clears only CRCERR interrupt pending bit. \r
- * @note\r
- * - OVR (OverRun Error) interrupt pending bit is cleared by software \r
- * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) \r
- * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).\r
- * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:\r
- * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) \r
- * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable \r
- * the SPI).\r
- * @retval None\r
- */\r
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
-{\r
- uint16_t itpos = 0;\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));\r
-\r
- /* Get the SPI_I2S IT index */\r
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
-\r
- /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */\r
- SPIx->SR = (uint16_t)~itpos;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_syscfg.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the SYSCFG and RI peripherals: \r
- * - SYSCFG Initialization and Configuration\r
- * - RI Initialization and Configuration\r
- *\r
- * @verbatim\r
- * \r
- * ===================================================================\r
- * How to use this driver\r
- * ===================================================================\r
- * \r
- * This driver provides functions for:\r
- * \r
- * 1. Remapping the memory accessible in the code area using\r
- * SYSCFG_MemoryRemapConfig() \r
- * 2. Manage the EXTI lines connection to the GPIOs using\r
- * SYSCFG_EXTILineConfig().\r
- * 3. Routing of I/Os toward the input captures of timers (TIM2, TIM3 and TIM4).\r
- * 4. Input routing of COMP1 and COMP2\r
- * 5. Routing of internal reference voltage VREFINT to PB0 and PB1.\r
- *\r
- * 6. The RI registers can be accessed only when the comparator \r
- * APB interface clock is enabled.\r
- * To enable comparator clock use:\r
- * RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE);\r
- *\r
- * Following functions uses RI registers:\r
- * - SYSCFG_RIDeInit()\r
- * - SYSCFG_RITIMSelect()\r
- * - SYSCFG_RITIMInputCaptureConfig()\r
- * - SYSCFG_RIResistorConfig()\r
- * - SYSCFG_RIIOSwitchConfig()\r
- * - SYSCFG_RISwitchControlModeCmd()\r
- * - SYSCFG_RIHysteresisConfig()\r
- *\r
- * 7- The SYSCFG registers can be accessed only when the SYSCFG \r
- * interface APB clock is enabled.\r
- * To enable SYSCFG APB clock use:\r
- * RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
- *\r
- * Following functions uses SYSCFG registers:\r
- * - SYSCFG_MemoryRemapConfig()\r
- * - SYSCFG_USBPuCmd()\r
- * - SYSCFG_EXTILineConfig()\r
- * \r
- * @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_syscfg.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup SYSCFG \r
- * @brief SYSCFG driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-#define TIM_SELECT_MASK ((uint32_t)0xFFFCFFFF) /*!< TIM select mask */\r
-#define IC_ROUTING_MASK ((uint32_t)0x0000000F) /*!< Input Capture routing mask */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup SYSCFG_Private_Functions\r
- * @{\r
- */ \r
-\r
-/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions\r
- * @brief SYSCFG Initialization and Configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- SYSCFG Initialization and Configuration functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the SYSCFG registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- * @ Note: MEMRMP bits are not reset by APB2 reset.\r
- */\r
-void SYSCFG_DeInit(void)\r
-{\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Deinitializes the RI registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void SYSCFG_RIDeInit(void)\r
-{\r
- RI->ICR = ((uint32_t)0x00000000); /*!< Set RI->ICR to reset value */\r
- RI->ASCR1 = ((uint32_t)0x00000000); /*!< Set RI->ASCR1 to reset value */ \r
- RI->ASCR2 = ((uint32_t)0x00000000); /*!< Set RI->ASCR2 to reset value */ \r
- RI->HYSCR1 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR1 to reset value */\r
- RI->HYSCR2 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR2 to reset value */\r
- RI->HYSCR3 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR3 to reset value */\r
-}\r
-\r
-/**\r
- * @brief Changes the mapping of the specified memory.\r
- * @param SYSCFG_Memory: selects the memory remapping.\r
- * This parameter can be one of the following values:\r
- * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 \r
- * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000\r
- * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000 \r
- * @retval None\r
- */\r
-void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));\r
- SYSCFG->MEMRMP = SYSCFG_MemoryRemap;\r
-}\r
-\r
-/**\r
- * @brief Control the internal pull-up on USB DP line.\r
- * @param NewState: New state of the internal pull-up on USB DP line. \r
- * This parameter can be ENABLE: Connect internal pull-up on USB DP line.\r
- * or DISABLE: Disconnect internal pull-up on USB DP line.\r
- * @retval None\r
- */\r
-void SYSCFG_USBPuCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- { \r
- /* Connect internal pull-up on USB DP line */\r
- SYSCFG->PMC |= (uint32_t) SYSCFG_PMC_USB_PU;\r
- }\r
- else\r
- {\r
- /* Disconnect internal pull-up on USB DP line */\r
- SYSCFG->PMC &= (uint32_t)(~SYSCFG_PMC_USB_PU);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the GPIO pin used as EXTI Line.\r
- * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source \r
- * for EXTI lines where x can be (A, B, C, D, E or H).\r
- * @param EXTI_PinSourcex: specifies the EXTI line to be configured.\r
- * This parameter can be EXTI_PinSourcex where x can be (0..15)\r
- * @retval None\r
- */\r
-void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)\r
-{\r
- uint32_t tmp = 0x00;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));\r
- assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));\r
- \r
- tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));\r
- SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;\r
- SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SYSCFG_Group2 RI Initialization and Configuration functions\r
- * @brief RI Initialization and Configuration functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- RI Initialization and Configuration functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the routing interface to select which Timer to be routed.\r
- * @note Routing capability can be applied only on one of the three timers\r
- * (TIM2, TIM3 or TIM4) at a time.\r
- * @param TIM_Select: Timer select.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_Select_None: No timer selected and default Timer mapping is enabled.\r
- * @arg TIM_Select_TIM2: Timer 2 Input Captures to be routed.\r
- * @arg TIM_Select_TIM3: Timer 3 Input Captures to be routed.\r
- * @arg TIM_Select_TIM4: Timer 4 Input Captures to be routed.\r
- * @retval None.\r
- */\r
-void SYSCFG_RITIMSelect(uint32_t TIM_Select)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RI_TIM(TIM_Select));\r
-\r
- /* Get the old register value */\r
- tmpreg = RI->ICR;\r
-\r
- /* Clear the TIMx select bits */\r
- tmpreg &= TIM_SELECT_MASK;\r
-\r
- /* Select the Timer */\r
- tmpreg |= (TIM_Select);\r
-\r
- /* Write to RI->ICR register */\r
- RI->ICR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Configures the routing interface to map Input Capture 1, 2, 3 or 4\r
- * to a selected I/O pin.\r
- * @param RI_InputCapture selects which input capture to be routed.\r
- * This parameter can be one (or combination) of the following parameters:\r
- * @arg RI_InputCapture_IC1: Input capture 1 is selected.\r
- * @arg RI_InputCapture_IC2: Input capture 2 is selected.\r
- * @arg RI_InputCapture_IC3: Input capture 3 is selected.\r
- * @arg RI_InputCapture_IC4: Input capture 4 is selected.\r
- * @param RI_InputCaptureRouting: selects which pin to be routed to Input Capture.\r
- * This parameter can be one of the following values:\r
- * @arg RI_InputCaptureRouting_0 to RI_InputCaptureRouting_15\r
- * e.g.\r
- * SYSCFG_RITIMSelect(TIM_Select_TIM2)\r
- * SYSCFG_RITIMInputCaptureConfig(RI_InputCapture_IC1, RI_InputCaptureRouting_1)\r
- * allows routing of Input capture IC1 of TIM2 to PA4.\r
- * For details about correspondence between RI_InputCaptureRouting_x \r
- * and I/O pins refer to the parameters' description in the header file\r
- * or refer to the product reference manual.\r
- * @note Input capture selection bits are not reset by this function.\r
- * To reset input capture selection bits, use SYSCFG_RIDeInit() function.\r
- * @note The I/O should be configured in alternate function mode (AF14) using\r
- * GPIO_PinAFConfig() function.\r
- * @retval None.\r
- */\r
-void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RI_INPUTCAPTURE(RI_InputCapture));\r
- assert_param(IS_RI_INPUTCAPTURE_ROUTING(RI_InputCaptureRouting));\r
-\r
- /* Get the old register value */\r
- tmpreg = RI->ICR;\r
-\r
- /* Select input captures to be routed */\r
- tmpreg |= (RI_InputCapture);\r
-\r
- if((RI_InputCapture & RI_InputCapture_IC1) == RI_InputCapture_IC1)\r
- {\r
- /* Clear the input capture select bits */\r
- tmpreg &= (uint32_t)(~IC_ROUTING_MASK);\r
-\r
- /* Set RI_InputCaptureRouting bits */\r
- tmpreg |= (uint32_t)( RI_InputCaptureRouting);\r
- }\r
-\r
- if((RI_InputCapture & RI_InputCapture_IC2) == RI_InputCapture_IC2)\r
- {\r
- /* Clear the input capture select bits */\r
- tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 4));\r
-\r
- /* Set RI_InputCaptureRouting bits */\r
- tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 4)); \r
- }\r
-\r
- if((RI_InputCapture & RI_InputCapture_IC3) == RI_InputCapture_IC3)\r
- {\r
- /* Clear the input capture select bits */\r
- tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 8));\r
-\r
- /* Set RI_InputCaptureRouting bits */\r
- tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 8)); \r
- }\r
-\r
- if((RI_InputCapture & RI_InputCapture_IC4) == RI_InputCapture_IC4)\r
- {\r
- /* Clear the input capture select bits */\r
- tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 12));\r
-\r
- /* Set RI_InputCaptureRouting bits */\r
- tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 12)); \r
- }\r
-\r
- /* Write to RI->ICR register */\r
- RI->ICR = tmpreg;\r
-}\r
-/**\r
- * @brief Configures the Pull-up and Pull-down Resistors \r
- * @param RI_Resistor selects the resistor to connect. \r
- * This parameter can be one of the following values:\r
- * @arg RI_Resistor_10KPU: 10K pull-up resistor\r
- * @arg RI_Resistor_400KPU: 400K pull-up resistor \r
- * @arg RI_Resistor_10KPD: 10K pull-down resistor \r
- * @arg RI_Resistor_400KPD: 400K pull-down resistor\r
- * @param NewState: New state of the analog switch associated to the selected \r
- * resistor.\r
- * This parameter can be:\r
- * ENABLE so the selected resistor is connected\r
- * or DISABLE so the selected resistor is disconnected\r
- * @note To avoid extra power consumption, only one resistor should be enabled\r
- * at a time. \r
- * @retval None\r
- */\r
-void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RI_RESISTOR(RI_Resistor));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the resistor */\r
- COMP->CSR |= (uint32_t) RI_Resistor;\r
- }\r
- else\r
- {\r
- /* Disable the Resistor */\r
- COMP->CSR &= (uint32_t) (~RI_Resistor);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Close or Open the routing interface Input Output switches.\r
- * @param RI_IOSwitch: selects the I/O analog switch number.\r
- * This parameter can be one of the following values:\r
- * @arg RI_IOSwitch_CH0 --> RI_IOSwitch_CH15\r
- * @arg RI_IOSwitch_CH18 --> RI_IOSwitch_CH25\r
- * @arg RI_IOSwitch_GR10_1 --> RI_IOSwitch_GR10_4\r
- * @arg RI_IOSwitch_GR6_1 --> RI_IOSwitch_GR6_2\r
- * @arg RI_IOSwitch_GR5_1 --> RI_IOSwitch_GR5_3\r
- * @arg RI_IOSwitch_GR4_1 --> RI_IOSwitch_GR4_3\r
- * @arg RI_IOSwitch_VCOMP\r
- * @param NewState: New state of the analog switch. \r
- * This parameter can be \r
- * ENABLE so the Input Output switch is closed\r
- * or DISABLE so the Input Output switch is open\r
- * @retval None\r
- */\r
-void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState)\r
-{\r
- uint32_t ioswitchmask = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RI_IOSWITCH(RI_IOSwitch));\r
- \r
- /* Read Analog switch register index */\r
- ioswitchmask = RI_IOSwitch >> 31;\r
- \r
- /* Get Bits[30:0] of the IO switch */\r
- RI_IOSwitch &= 0x7FFFFFFF;\r
- \r
- \r
- if (NewState != DISABLE)\r
- { \r
- if (ioswitchmask != 0)\r
- {\r
- /* Close the analog switches */\r
- RI->ASCR1 |= RI_IOSwitch;\r
- }\r
- else\r
- {\r
- /* Open the analog switches */\r
- RI->ASCR2 |= RI_IOSwitch;\r
- }\r
- }\r
- else\r
- {\r
- if (ioswitchmask != 0)\r
- {\r
- /* Close the analog switches */\r
- RI->ASCR1 &= (~ (uint32_t)RI_IOSwitch);\r
- }\r
- else\r
- {\r
- /* Open the analog switches */\r
- RI->ASCR2 &= (~ (uint32_t)RI_IOSwitch);\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enable or disable the switch control mode.\r
- * @param NewState: New state of the switch control mode. This parameter can\r
- * be ENABLE: ADC analog switches closed if the corresponding \r
- * I/O switch is also closed.\r
- * When using COMP1 switch control mode must be enabled.\r
- * or DISABLE: ADC analog switches open or controlled by the ADC interface.\r
- * When using the ADC for acquisition switch control mode \r
- * must be disabled.\r
- * @note COMP1 comparator and ADC cannot be used at the same time since \r
- * they share the ADC switch matrix.\r
- * @retval None\r
- */\r
-void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
- \r
- if (NewState != DISABLE)\r
- { \r
- /* Enable the Switch control mode */ \r
- RI->ASCR1 |= (uint32_t) RI_ASCR1_SCM;\r
- }\r
- else\r
- {\r
- /* Disable the Switch control mode */ \r
- RI->ASCR1 &= (uint32_t)(~RI_ASCR1_SCM);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enable or disable Hysteresis of the input schmitt triger of Ports A..E\r
- * When the I/Os are programmed in input mode by standard I/O port \r
- * registers, the Schmitt trigger and the hysteresis are enabled by default. \r
- * When hysteresis is disabled, it is possible to read the \r
- * corresponding port with a trigger level of VDDIO/2. \r
- * @param RI_Port: selects the GPIO Port.\r
- * This parameter can be one of the following values:\r
- * @arg RI_PortA : Port A is selected\r
- * @arg RI_PortB : Port B is selected\r
- * @arg RI_PortC : Port C is selected\r
- * @arg RI_PortD : Port D is selected\r
- * @arg RI_PortE : Port E is selected\r
- * @param RI_Pin : Selects the pin(s) on which to enable or disable hysteresis.\r
- * This parameter can any value from RI_Pin_x where x can be (0..15) or RI_Pin_All.\r
- * @param NewState new state of the Hysteresis.\r
- * This parameter can be:\r
- * ENABLE so the Hysteresis is on\r
- * or DISABLE so the Hysteresis is off\r
- * @retval None\r
- */\r
-void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin,\r
- FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RI_PORT(RI_Port));\r
- assert_param(IS_RI_PIN(RI_Pin));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if(RI_Port == RI_PortA)\r
- { \r
- if (NewState != DISABLE)\r
- {\r
- /* Hysteresis on */\r
- RI->HYSCR1 &= (uint32_t)~((uint32_t)RI_Pin);\r
- }\r
- else\r
- {\r
- /* Hysteresis off */\r
- RI->HYSCR1 |= (uint32_t) RI_Pin;\r
- }\r
- }\r
- \r
- else if(RI_Port == RI_PortB)\r
- {\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Hysteresis on */\r
- RI->HYSCR1 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);\r
- }\r
- else\r
- {\r
- /* Hysteresis off */\r
- RI->HYSCR1 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);\r
- }\r
- } \r
- \r
- else if(RI_Port == RI_PortC)\r
- {\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Hysteresis on */\r
- RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin));\r
- }\r
- else\r
- {\r
- /* Hysteresis off */\r
- RI->HYSCR2 |= (uint32_t) (RI_Pin );\r
- }\r
- } \r
- else if(RI_Port == RI_PortD)\r
- {\r
- if (NewState != DISABLE)\r
- {\r
- /* Hysteresis on */\r
- RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);\r
- }\r
- else\r
- {\r
- /* Hysteresis off */\r
- RI->HYSCR2 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);\r
-\r
- }\r
- } \r
- else /* RI_Port == RI_PortE */\r
- {\r
- if (NewState != DISABLE)\r
- {\r
- /* Hysteresis on */\r
- RI->HYSCR3 &= (uint32_t) (~((uint32_t)RI_Pin));\r
- }\r
- else\r
- {\r
- /* Hysteresis off */\r
- RI->HYSCR3 |= (uint32_t) (RI_Pin );\r
- }\r
- } \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ \r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_tim.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the TIM peripheral:\r
- * - TimeBase management\r
- * - Output Compare management\r
- * - Input Capture management\r
- * - Interrupts, DMA and flags management\r
- * - Clocks management\r
- * - Synchronization management\r
- * - Specific interface management\r
- * - Specific remapping management \r
- * \r
- * @verbatim\r
- * \r
- * ===================================================================\r
- * How to use this driver\r
- * ===================================================================\r
- * This driver provides functions to configure and program the TIM \r
- * of all STM32L1xx devices\r
- * These functions are split in 8 groups: \r
- * \r
- * 1. TIM TimeBase management: this group includes all needed functions \r
- * to configure the TM Timebase unit:\r
- * - Set/Get Prescaler\r
- * - Set/Get Autoreload \r
- * - Counter modes configuration\r
- * - Set Clock division \r
- * - Select the One Pulse mode\r
- * - Update Request Configuration\r
- * - Update Disable Configuration\r
- * - Auto-Preload Configuration \r
- * - Enable/Disable the counter \r
- * \r
- * 2. TIM Output Compare management: this group includes all needed \r
- * functions to configure the Capture/Compare unit used in Output \r
- * compare mode: \r
- * - Configure each channel, independently, in Output Compare mode\r
- * - Select the output compare modes\r
- * - Select the Polarities of each channel\r
- * - Set/Get the Capture/Compare register values\r
- * - Select the Output Compare Fast mode \r
- * - Select the Output Compare Forced mode \r
- * - Output Compare-Preload Configuration \r
- * - Clear Output Compare Reference\r
- * - Select the OCREF Clear signal\r
- * - Enable/Disable the Capture/Compare Channels \r
- * \r
- * 3. TIM Input Capture management: this group includes all needed \r
- * functions to configure the Capture/Compare unit used in \r
- * Input Capture mode:\r
- * - Configure each channel in input capture mode\r
- * - Configure Channel1/2 in PWM Input mode\r
- * - Set the Input Capture Prescaler\r
- * - Get the Capture/Compare values \r
- * \r
- * 4. TIM interrupts, DMA and flags management\r
- * - Enable/Disable interrupt sources\r
- * - Get flags status\r
- * - Clear flags/ Pending bits\r
- * - Enable/Disable DMA requests \r
- * - Configure DMA burst mode\r
- * - Select CaptureCompare DMA request \r
- * \r
- * 5. TIM clocks management: this group includes all needed functions \r
- * to configure the clock controller unit:\r
- * - Select internal/External clock\r
- * - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx\r
- * \r
- * 6. TIM synchronization management: this group includes all needed \r
- * functions to configure the Synchronization unit:\r
- * - Select Input Trigger \r
- * - Select Output Trigger \r
- * - Select Master Slave Mode \r
- * - ETR Configuration when used as external trigger \r
- * \r
- * 7. TIM specific interface management, this group includes all \r
- * needed functions to use the specific TIM interface:\r
- * - Encoder Interface Configuration\r
- * - Select Hall Sensor \r
- * \r
- * 8. TIM specific remapping management includes the Remapping \r
- * configuration of specific timers \r
- * \r
- * @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_tim.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup TIM \r
- * @brief TIM driver modules\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-/* ---------------------- TIM registers bit mask ------------------------ */\r
-#define SMCR_ETR_MASK ((uint16_t)0x00FF) \r
-#define CCMR_OFFSET ((uint16_t)0x0018)\r
-#define CCER_CCE_SET ((uint16_t)0x0001) \r
- \r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-\r
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter);\r
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter);\r
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter);\r
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter);\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup TIM_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup TIM_Group1 TimeBase management functions\r
- * @brief TimeBase management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- TimeBase management functions\r
- =============================================================================== \r
- \r
- =================================================================== \r
- TIM Driver: how to use it in Timing(Time base) Mode\r
- =================================================================== \r
- To use the Timer in Timing(Time base) mode, the following steps are mandatory:\r
- \r
- 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function\r
- \r
- 2. Fill the TIM_TimeBaseInitStruct with the desired parameters.\r
- \r
- 3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit\r
- with the corresponding configuration\r
- \r
- 4. Enable the NVIC if you need to generate the update interrupt. \r
- \r
- 5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) \r
- \r
- 6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r
- \r
- Note1: All other functions can be used seperatly to modify, if needed,\r
- a specific feature of the Timer. \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the TIMx peripheral registers to their default reset values.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @retval None\r
- * \r
- */\r
-void TIM_DeInit(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
- \r
- if (TIMx == TIM2)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);\r
- }\r
- else if (TIMx == TIM3)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);\r
- }\r
- else if (TIMx == TIM4)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);\r
- } \r
-\r
- else if (TIMx == TIM6)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);\r
- } \r
- else if (TIMx == TIM7)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);\r
- } \r
-\r
- else if (TIMx == TIM9)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);\r
- } \r
- else if (TIMx == TIM10)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);\r
- } \r
- else\r
- {\r
- if (TIMx == TIM11)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); \r
- } \r
- }\r
- \r
-}\r
-\r
-/**\r
- * @brief Initializes the TIMx Time Base Unit peripheral according to \r
- * the specified parameters in the TIM_TimeBaseInitStruct.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef\r
- * structure that contains the configuration information for\r
- * the specified TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
-{\r
- uint16_t tmpcr1 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
- assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));\r
- assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));\r
-\r
- tmpcr1 = TIMx->CR1; \r
-\r
- if(((TIMx) == TIM2) || ((TIMx) == TIM3) || ((TIMx) == TIM4))\r
- { \r
- /* Select the Counter Mode */\r
- tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;\r
- }\r
- \r
- if(((TIMx) != TIM6) && ((TIMx) != TIM7))\r
- {\r
- /* Set the clock division */\r
- tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));\r
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;\r
- }\r
-\r
- TIMx->CR1 = tmpcr1;\r
-\r
- /* Set the Autoreload value */\r
- TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;\r
- \r
- /* Set the Prescaler value */\r
- TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;\r
- \r
- /* Generate an update event to reload the Prescaler value immediatly */\r
- TIMx->EGR = TIM_PSCReloadMode_Immediate; \r
-}\r
-\r
-/**\r
- * @brief Fills each TIM_TimeBaseInitStruct member with its default value.\r
- * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef\r
- * structure which will be initialized.\r
- * @retval None\r
- */\r
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
-{\r
- /* Set the default configuration */\r
- TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;\r
- TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;\r
- TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;\r
- TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Prescaler.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param Prescaler: specifies the Prescaler Register value\r
- * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode\r
- * This parameter can be one of the following values:\r
- * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.\r
- * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.\r
- * @retval None\r
- */\r
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));\r
- \r
- /* Set the Prescaler value */\r
- TIMx->PSC = Prescaler;\r
- /* Set or reset the UG Bit */\r
- TIMx->EGR = TIM_PSCReloadMode;\r
-}\r
-\r
-/**\r
- * @brief Specifies the TIMx Counter Mode to be used.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_CounterMode: specifies the Counter Mode to be used\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CounterMode_Up: TIM Up Counting Mode\r
- * @arg TIM_CounterMode_Down: TIM Down Counting Mode\r
- * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1\r
- * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2\r
- * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3\r
- * @retval None\r
- */\r
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)\r
-{\r
- uint16_t tmpcr1 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));\r
- \r
- tmpcr1 = TIMx->CR1;\r
- /* Reset the CMS and DIR Bits */\r
- tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
- /* Set the Counter Mode */\r
- tmpcr1 |= TIM_CounterMode;\r
- /* Write to TIMx CR1 register */\r
- TIMx->CR1 = tmpcr1;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Counter Register value\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param Counter: specifies the Counter register new value.\r
- * @retval None\r
- */\r
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- \r
- /* Set the Counter Register value */\r
- TIMx->CNT = Counter;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Autoreload Register value\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param Autoreload: specifies the Autoreload register new value.\r
- * @retval None\r
- */\r
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- \r
- /* Set the Autoreload Register value */\r
- TIMx->ARR = Autoreload;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Counter value.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @retval Counter Register value.\r
- */\r
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- \r
- /* Get the Counter Register value */\r
- return TIMx->CNT;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Prescaler value.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @retval Prescaler Register value.\r
- */\r
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- \r
- /* Get the Prescaler Register value */\r
- return TIMx->PSC;\r
-}\r
-\r
-/**\r
- * @brief Enables or Disables the TIMx Update event.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param NewState: new state of the TIMx UDIS bit\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Set the Update Disable Bit */\r
- TIMx->CR1 |= TIM_CR1_UDIS;\r
- }\r
- else\r
- {\r
- /* Reset the Update Disable Bit */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Update Request Interrupt source.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param TIM_UpdateSource: specifies the Update source.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow\r
- or the setting of UG bit, or an update generation\r
- through the slave mode controller.\r
- * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.\r
- * @retval None\r
- */\r
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));\r
- \r
- if (TIM_UpdateSource != TIM_UpdateSource_Global)\r
- {\r
- /* Set the URS Bit */\r
- TIMx->CR1 |= TIM_CR1_URS;\r
- }\r
- else\r
- {\r
- /* Reset the URS Bit */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables TIMx peripheral Preload register on ARR.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param NewState: new state of the TIMx peripheral Preload register\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Set the ARR Preload Bit */\r
- TIMx->CR1 |= TIM_CR1_ARPE;\r
- }\r
- else\r
- {\r
- /* Reset the ARR Preload Bit */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the TIMx\92s One Pulse Mode.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param TIM_OPMode: specifies the OPM Mode to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OPMode_Single\r
- * @arg TIM_OPMode_Repetitive\r
- * @retval None\r
- */\r
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_OPM_MODE(TIM_OPMode));\r
- \r
- /* Reset the OPM Bit */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);\r
- /* Configure the OPM Mode */\r
- TIMx->CR1 |= TIM_OPMode;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Clock Division value.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_CKD: specifies the clock division value.\r
- * This parameter can be one of the following value:\r
- * @arg TIM_CKD_DIV1: TDTS = Tck_tim\r
- * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim\r
- * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim\r
- * @retval None\r
- */\r
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_CKD_DIV(TIM_CKD));\r
- \r
- /* Reset the CKD Bits */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);\r
- /* Set the CKD value */\r
- TIMx->CR1 |= TIM_CKD;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified TIM peripheral.\r
- * @param TIMx: where x can be 2 to 11 to select the TIMx peripheral.\r
- * @param NewState: new state of the TIMx peripheral.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the TIM Counter */\r
- TIMx->CR1 |= TIM_CR1_CEN;\r
- }\r
- else\r
- {\r
- /* Disable the TIM Counter */\r
- TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Group2 Output Compare management functions\r
- * @brief Output Compare management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Output Compare management functions\r
- =============================================================================== \r
- \r
- =================================================================== \r
- TIM Driver: how to use it in Output Compare Mode\r
- =================================================================== \r
- To use the Timer in Output Compare mode, the following steps are mandatory:\r
- \r
- 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function\r
- \r
- 2. Configure the TIM pins by configuring the corresponding GPIO pins\r
- \r
- 2. Configure the Time base unit as described in the first part of this driver, if needed,\r
- else the Timer will run with the default configuration:\r
- - Autoreload value = 0xFFFF\r
- - Prescaler value = 0x0000\r
- - Counter mode = Up counting\r
- - Clock Division = TIM_CKD_DIV1\r
- \r
- 3. Fill the TIM_OCInitStruct with the desired parameters including:\r
- - The TIM Output Compare mode: TIM_OCMode\r
- - TIM Output State: TIM_OutputState\r
- - TIM Pulse value: TIM_Pulse\r
- - TIM Output Compare Polarity : TIM_OCPolarity\r
- \r
- 4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the \r
- corresponding configuration\r
- \r
- 5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r
- \r
- Note1: All other functions can be used separately to modify, if needed,\r
- a specific feature of the Timer. \r
- \r
- Note2: In case of PWM mode, this function is mandatory:\r
- TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); \r
- \r
- Note3: If the corresponding interrupt or DMA request are needed, the user should:\r
- 1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). \r
- 2. Enable the corresponding interrupt (or DMA request) using the function \r
- TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Initializes the TIMx Channel1 according to the specified\r
- * parameters in the TIM_OCInitStruct.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
- * that contains the configuration information for the specified TIM \r
- * peripheral.\r
- * @retval None\r
- */\r
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- uint16_t tmpccmrx = 0, tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
- /* Disable the Channel 1: Reset the CC1E Bit */\r
- TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);\r
- \r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- \r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmrx = TIMx->CCMR1;\r
- \r
- /* Reset the Output Compare Mode Bits */\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));\r
- \r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
- \r
- /* Reset the Output Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;\r
- \r
- /* Set the Output State */\r
- tmpccer |= TIM_OCInitStruct->TIM_OutputState;\r
- \r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;\r
- \r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmrx;\r
- \r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIMx Channel2 according to the specified\r
- * parameters in the TIM_OCInitStruct.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
- * that contains the configuration information for the specified TIM \r
- * peripheral.\r
- * @retval None\r
- */\r
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- uint16_t tmpccmrx = 0, tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx)); \r
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
- /* Disable the Channel 2: Reset the CC2E Bit */\r
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));\r
- \r
- /* Get the TIMx CCER register value */ \r
- tmpccer = TIMx->CCER;\r
- \r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmrx = TIMx->CCMR1;\r
- \r
- /* Reset the Output Compare Mode Bits */\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));\r
- \r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
- \r
- /* Reset the Output Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);\r
- \r
- /* Set the Output State */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);\r
- \r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;\r
- \r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmrx;\r
- \r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIMx Channel3 according to the specified\r
- * parameters in the TIM_OCInitStruct.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
- * that contains the configuration information for the specified TIM \r
- * peripheral.\r
- * @retval None\r
- */\r
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- uint16_t tmpccmrx = 0, tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
-\r
- /* Disable the Channel 2: Reset the CC2E Bit */\r
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));\r
- \r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- \r
- /* Get the TIMx CCMR2 register value */\r
- tmpccmrx = TIMx->CCMR2;\r
- \r
- /* Reset the Output Compare Mode Bits */\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));\r
- \r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
- \r
- /* Reset the Output Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);\r
- \r
- /* Set the Output State */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);\r
- \r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;\r
- \r
- /* Write to TIMx CCMR2 */\r
- TIMx->CCMR2 = tmpccmrx;\r
- \r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIMx Channel4 according to the specified\r
- * parameters in the TIM_OCInitStruct.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
- * that contains the configuration information for the specified TIM \r
- * peripheral.\r
- * @retval None\r
- */\r
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- uint16_t tmpccmrx = 0, tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
-\r
- /* Disable the Channel 2: Reset the CC4E Bit */\r
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));\r
- \r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- \r
- /* Get the TIMx CCMR2 register value */\r
- tmpccmrx = TIMx->CCMR2;\r
- \r
- /* Reset the Output Compare Mode Bits */\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));\r
- \r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
- \r
- /* Reset the Output Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);\r
- \r
- /* Set the Output State */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);\r
- \r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;\r
- \r
- /* Write to TIMx CCMR2 */ \r
- TIMx->CCMR2 = tmpccmrx;\r
- \r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Fills each TIM_OCInitStruct member with its default value.\r
- * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will\r
- * be initialized.\r
- * @retval None\r
- */\r
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- /* Set the default configuration */\r
- TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;\r
- TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;\r
- TIM_OCInitStruct->TIM_Pulse = 0x0000;\r
- TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;\r
-}\r
-\r
-/**\r
- * @brief Selects the TIM Output Compare Mode.\r
- * @note This function disables the selected channel before changing the Output\r
- * Compare Mode.\r
- * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_Channel: specifies the TIM Channel\r
- * This parameter can be one of the following values:\r
- * @arg TIM_Channel_1: TIM Channel 1\r
- * @arg TIM_Channel_2: TIM Channel 2\r
- * @arg TIM_Channel_3: TIM Channel 3\r
- * @arg TIM_Channel_4: TIM Channel 4\r
- * @param TIM_OCMode: specifies the TIM Output Compare Mode.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCMode_Timing\r
- * @arg TIM_OCMode_Active\r
- * @arg TIM_OCMode_Toggle\r
- * @arg TIM_OCMode_PWM1\r
- * @arg TIM_OCMode_PWM2\r
- * @arg TIM_ForcedAction_Active\r
- * @arg TIM_ForcedAction_InActive\r
- * @retval None\r
- */\r
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)\r
-{\r
- uint32_t tmp = 0;\r
- uint16_t tmp1 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx)); \r
- assert_param(IS_TIM_OCM(TIM_OCMode));\r
- \r
- tmp = (uint32_t) TIMx;\r
- tmp += CCMR_OFFSET;\r
-\r
- tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;\r
-\r
- /* Disable the Channel: Reset the CCxE Bit */\r
- TIMx->CCER &= (uint16_t) ~tmp1;\r
-\r
- if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))\r
- {\r
- tmp += (TIM_Channel>>1);\r
-\r
- /* Reset the OCxM bits in the CCMRx register */\r
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);\r
- \r
- /* Configure the OCxM bits in the CCMRx register */\r
- *(__IO uint32_t *) tmp |= TIM_OCMode;\r
- }\r
- else\r
- {\r
- tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;\r
-\r
- /* Reset the OCxM bits in the CCMRx register */\r
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);\r
- \r
- /* Configure the OCxM bits in the CCMRx register */\r
- *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Capture Compare1 Register value\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param Compare1: specifies the Capture Compare1 register new value.\r
- * @retval None\r
-\r
- */\r
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- \r
- /* Set the Capture Compare1 Register value */\r
- TIMx->CCR1 = Compare1;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Capture Compare2 Register value\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param Compare2: specifies the Capture Compare2 register new value.\r
- * @retval None\r
-\r
- */\r
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- \r
- /* Set the Capture Compare2 Register value */\r
- TIMx->CCR2 = Compare2;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Capture Compare3 Register value\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param Compare3: specifies the Capture Compare3 register new value.\r
- * @retval None\r
-\r
- */\r
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- \r
- /* Set the Capture Compare3 Register value */\r
- TIMx->CCR3 = Compare3;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Capture Compare4 Register value\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param Compare4: specifies the Capture Compare4 register new value.\r
- * @retval None\r
-\r
- */\r
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- \r
- /* Set the Capture Compare4 Register value */\r
- TIMx->CCR4 = Compare4;\r
-}\r
-\r
-/**\r
- * @brief Forces the TIMx output 1 waveform to active or inactive level.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ForcedAction_Active: Force active level on OC1REF\r
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.\r
- * @retval None\r
- */\r
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC1M Bits */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);\r
- /* Configure The Forced output Mode */\r
- tmpccmr1 |= TIM_ForcedAction;\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
- \r
-/**\r
- * @brief Forces the TIMx output 2 waveform to active or inactive level.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM \r
- * peripheral.\r
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ForcedAction_Active: Force active level on OC2REF\r
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.\r
- * @retval None\r
- */\r
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
- \r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC2M Bits */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);\r
- /* Configure The Forced output Mode */\r
- tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Forces the TIMx output 3 waveform to active or inactive level.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ForcedAction_Active: Force active level on OC3REF\r
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.\r
- * @retval None\r
- */\r
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
- \r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC1M Bits */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);\r
- /* Configure The Forced output Mode */\r
- tmpccmr2 |= TIM_ForcedAction;\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Forces the TIMx output 4 waveform to active or inactive level.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ForcedAction_Active: Force active level on OC4REF\r
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.\r
- * @retval None\r
- */\r
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
- \r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC2M Bits */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);\r
- /* Configure The Forced output Mode */\r
- tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx peripheral Preload register on CCR1.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCPreload_Enable\r
- * @arg TIM_OCPreload_Disable\r
- * @retval None\r
- */\r
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
- \r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC1PE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);\r
- /* Enable or Disable the Output Compare Preload feature */\r
- tmpccmr1 |= TIM_OCPreload;\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx peripheral Preload register on CCR2.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCPreload_Enable\r
- * @arg TIM_OCPreload_Disable\r
- * @retval None\r
- */\r
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
- \r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC2PE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);\r
- /* Enable or Disable the Output Compare Preload feature */\r
- tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx peripheral Preload register on CCR3.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCPreload_Enable\r
- * @arg TIM_OCPreload_Disable\r
- * @retval None\r
- */\r
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
- \r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC3PE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);\r
- /* Enable or Disable the Output Compare Preload feature */\r
- tmpccmr2 |= TIM_OCPreload;\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx peripheral Preload register on CCR4.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCPreload_Enable\r
- * @arg TIM_OCPreload_Disable\r
- * @retval None\r
- */\r
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
- \r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC4PE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);\r
- /* Enable or Disable the Output Compare Preload feature */\r
- tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Output Compare 1 Fast feature.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
- * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
- * @retval None\r
- */\r
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
- \r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC1FE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);\r
- /* Enable or Disable the Output Compare Fast Bit */\r
- tmpccmr1 |= TIM_OCFast;\r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Output Compare 2 Fast feature.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
- * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
- * @retval None\r
- */\r
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
- \r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC2FE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);\r
- /* Enable or Disable the Output Compare Fast Bit */\r
- tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);\r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Output Compare 3 Fast feature.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
- * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
- * @retval None\r
- */\r
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
- \r
- /* Get the TIMx CCMR2 register value */\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC3FE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);\r
- /* Enable or Disable the Output Compare Fast Bit */\r
- tmpccmr2 |= TIM_OCFast;\r
- /* Write to TIMx CCMR2 */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Output Compare 4 Fast feature.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
- * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
- * @retval None\r
- */\r
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
- \r
- /* Get the TIMx CCMR2 register value */\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC4FE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);\r
- /* Enable or Disable the Output Compare Fast Bit */\r
- tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);\r
- /* Write to TIMx CCMR2 */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Clears or safeguards the OCREF1 signal on an external event\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCClear_Enable: TIM Output clear enable\r
- * @arg TIM_OCClear_Disable: TIM Output clear disable\r
- * @retval None\r
- */\r
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
- \r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC1CE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);\r
- /* Enable or Disable the Output Compare Clear Bit */\r
- tmpccmr1 |= TIM_OCClear;\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Clears or safeguards the OCREF2 signal on an external event\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
-\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCClear_Enable: TIM Output clear enable\r
- * @arg TIM_OCClear_Disable: TIM Output clear disable\r
- * @retval None\r
- */\r
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
- \r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC2CE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);\r
- /* Enable or Disable the Output Compare Clear Bit */\r
- tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Clears or safeguards the OCREF3 signal on an external event\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCClear_Enable: TIM Output clear enable\r
- * @arg TIM_OCClear_Disable: TIM Output clear disable\r
- * @retval None\r
- */\r
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
- \r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC3CE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);\r
- /* Enable or Disable the Output Compare Clear Bit */\r
- tmpccmr2 |= TIM_OCClear;\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Clears or safeguards the OCREF4 signal on an external event\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCClear_Enable: TIM Output clear enable\r
- * @arg TIM_OCClear_Disable: TIM Output clear disable\r
- * @retval None\r
- */\r
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
- \r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC4CE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);\r
- /* Enable or Disable the Output Compare Clear Bit */\r
- tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx channel 1 polarity.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_OCPolarity: specifies the OC1 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCPolarity_High: Output Compare active high\r
- * @arg TIM_OCPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
- \r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC1P Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);\r
- tmpccer |= TIM_OCPolarity;\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx channel 2 polarity.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_OCPolarity: specifies the OC2 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCPolarity_High: Output Compare active high\r
- * @arg TIM_OCPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
- \r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC2P Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);\r
- tmpccer |= (uint16_t)(TIM_OCPolarity << 4);\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx channel 3 polarity.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCPolarity: specifies the OC3 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCPolarity_High: Output Compare active high\r
- * @arg TIM_OCPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
- \r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC3P Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);\r
- tmpccer |= (uint16_t)(TIM_OCPolarity << 8);\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx channel 4 polarity.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCPolarity: specifies the OC4 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCPolarity_High: Output Compare active high\r
- * @arg TIM_OCPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
- \r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC4P Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);\r
- tmpccer |= (uint16_t)(TIM_OCPolarity << 12);\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Selects the OCReference Clear source.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCReferenceClear: specifies the OCReference Clear source.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.\r
- * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input. \r
- * @retval None\r
- */\r
-void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));\r
-\r
- /* Set the TIM_OCReferenceClear source */\r
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS);\r
- TIMx->SMCR |= TIM_OCReferenceClear;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIM Capture Compare Channel x.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_Channel: specifies the TIM Channel\r
- * This parameter can be one of the following values:\r
- * @arg TIM_Channel_1: TIM Channel 1\r
- * @arg TIM_Channel_2: TIM Channel 2\r
- * @arg TIM_Channel_3: TIM Channel 3\r
- * @arg TIM_Channel_4: TIM Channel 4\r
- * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.\r
- * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. \r
- * @retval None\r
- */\r
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)\r
-{\r
- uint16_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx)); \r
- assert_param(IS_TIM_CCX(TIM_CCx));\r
-\r
- tmp = CCER_CCE_SET << TIM_Channel;\r
-\r
- /* Reset the CCxE Bit */\r
- TIMx->CCER &= (uint16_t)~ tmp;\r
-\r
- /* Set or reset the CCxE Bit */ \r
- TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Group3 Input Capture management functions\r
- * @brief Input Capture management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Input Capture management functions\r
- =============================================================================== \r
- \r
- =================================================================== \r
- TIM Driver: how to use it in Input Capture Mode\r
- =================================================================== \r
- To use the Timer in Input Capture mode, the following steps are mandatory:\r
- \r
- 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function\r
- \r
- 2. Configure the TIM pins by configuring the corresponding GPIO pins\r
- \r
- 2. Configure the Time base unit as described in the first part of this driver, if needed,\r
- else the Timer will run with the default configuration:\r
- - Autoreload value = 0xFFFF\r
- - Prescaler value = 0x0000\r
- - Counter mode = Up counting\r
- - Clock Division = TIM_CKD_DIV1\r
- \r
- 3. Fill the TIM_ICInitStruct with the desired parameters including:\r
- - TIM Channel: TIM_Channel\r
- - TIM Input Capture polarity: TIM_ICPolarity\r
- - TIM Input Capture selection: TIM_ICSelection\r
- - TIM Input Capture Prescaler: TIM_ICPrescaler\r
- - TIM Input CApture filter value: TIM_ICFilter\r
- \r
- 4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the \r
- corresponding configuration and to measure only frequency or duty cycle of the input signal,\r
- or,\r
- Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the \r
- corresponding configuration and to measure the frequency and the duty cycle of the input signal\r
- \r
- 5. Enable the NVIC or the DMA to read the measured frequency. \r
- \r
- 6. Enable the corresponding interrupt (or DMA request) to read the Captured value,\r
- using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) \r
- \r
- 7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r
- \r
- 8. Use TIM_GetCapturex(TIMx); to read the captured value.\r
- \r
- Note1: All other functions can be used seperatly to modify, if needed,\r
- a specific feature of the Timer. \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Initializes the TIM peripheral according to the specified\r
- * parameters in the TIM_ICInitStruct.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
- * that contains the configuration information for the specified TIM \r
- * peripheral.\r
- * @retval None\r
- */\r
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));\r
- assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));\r
- assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));\r
- \r
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
- {\r
- /* TI1 Configuration */\r
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
- TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)\r
- {\r
- /* TI2 Configuration */\r
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
- TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)\r
- {\r
- /* TI3 Configuration */\r
- TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
- TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
- else\r
- {\r
- /* TI4 Configuration */\r
- TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
- TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Fills each TIM_ICInitStruct member with its default value.\r
- * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will\r
- * be initialized.\r
- * @retval None\r
- */\r
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)\r
-{\r
- /* Set the default configuration */\r
- TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;\r
- TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;\r
- TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;\r
- TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;\r
- TIM_ICInitStruct->TIM_ICFilter = 0x00;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIM peripheral according to the specified\r
- * parameters in the TIM_ICInitStruct to measure an external PWM signal.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
- * that contains the configuration information for the specified TIM \r
- * peripheral.\r
- * @retval None\r
- */\r
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
-{\r
- uint16_t icoppositepolarity = TIM_ICPolarity_Rising;\r
- uint16_t icoppositeselection = TIM_ICSelection_DirectTI;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- /* Select the Opposite Input Polarity */\r
- if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)\r
- {\r
- icoppositepolarity = TIM_ICPolarity_Falling;\r
- }\r
- else\r
- {\r
- icoppositepolarity = TIM_ICPolarity_Rising;\r
- }\r
- /* Select the Opposite Input */\r
- if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)\r
- {\r
- icoppositeselection = TIM_ICSelection_IndirectTI;\r
- }\r
- else\r
- {\r
- icoppositeselection = TIM_ICSelection_DirectTI;\r
- }\r
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
- {\r
- /* TI1 Configuration */\r
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- /* TI2 Configuration */\r
- TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
- else\r
- { \r
- /* TI2 Configuration */\r
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- /* TI1 Configuration */\r
- TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Input Capture 1 value.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @retval Capture Compare 1 Register value.\r
-\r
- */\r
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- \r
- /* Get the Capture 1 Register value */\r
- return TIMx->CCR1;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Input Capture 2 value.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @retval Capture Compare 2 Register value.\r
-\r
- */\r
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- \r
- /* Get the Capture 2 Register value */\r
- return TIMx->CCR2;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Input Capture 3 value.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @retval Capture Compare 3 Register value.\r
- */\r
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
- \r
- /* Get the Capture 3 Register value */\r
- return TIMx->CCR3;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Input Capture 4 value.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @retval Capture Compare 4 Register value.\r
- */\r
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- \r
- /* Get the Capture 4 Register value */\r
- return TIMx->CCR4;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Input Capture 1 prescaler.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPSC_DIV1: no prescaler\r
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
- * @retval None\r
- */\r
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
- \r
- /* Reset the IC1PSC Bits */\r
- TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);\r
- /* Set the IC1PSC value */\r
- TIMx->CCMR1 |= TIM_ICPSC;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Input Capture 2 prescaler.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPSC_DIV1: no prescaler\r
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
- * @retval None\r
- */\r
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
- \r
- /* Reset the IC2PSC Bits */\r
- TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);\r
- /* Set the IC2PSC value */\r
- TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Input Capture 3 prescaler.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPSC_DIV1: no prescaler\r
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
- * @retval None\r
- */\r
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
- \r
- /* Reset the IC3PSC Bits */\r
- TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);\r
- /* Set the IC3PSC value */\r
- TIMx->CCMR2 |= TIM_ICPSC;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Input Capture 4 prescaler.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPSC_DIV1: no prescaler\r
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
- * @retval None\r
- */\r
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
- \r
- /* Reset the IC4PSC Bits */\r
- TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);\r
- /* Set the IC4PSC value */\r
- TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Group4 Interrupts DMA and flags management functions\r
- * @brief Interrupts, DMA and flags management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Interrupts, DMA and flags management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified TIM interrupts.\r
- * @param TIMx: where x can be 2 to 11 to select the TIMx peripheral.\r
- * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg TIM_IT_Update: TIM update Interrupt source\r
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
- * @note \r
- * - TIM6 and TIM7 can only generate an update interrupt. \r
- * - TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4 and TIM_IT_Trigger can not be used with TIM10 and TIM11\r
- * - TIM_IT_CC3, TIM_IT_CC4 can not be used with TIM9. \r
- * @param NewState: new state of the TIM interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_IT(TIM_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the Interrupt sources */\r
- TIMx->DIER |= TIM_IT;\r
- }\r
- else\r
- {\r
- /* Disable the Interrupt sources */\r
- TIMx->DIER &= (uint16_t)~TIM_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx event to be generate by software.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param TIM_EventSource: specifies the event source.\r
- * This parameter can be one or more of the following values: \r
- * @arg TIM_EventSource_Update: Timer update Event source\r
- * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source\r
- * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source\r
- * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source\r
- * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source \r
- * @arg TIM_EventSource_Trigger: Timer Trigger Event source\r
- * @note \r
- * - TIM6 and TIM7 can only generate an update event. \r
- * - TIM9 can only generate an update event, Capture Compare 1 event, \r
- * Capture Compare 2 event and TIM_EventSource_Trigger. \r
- * - TIM10 and TIM11 can only generate an update event and Capture Compare 1 event. \r
- * @retval None\r
- */\r
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); \r
- /* Set the event sources */\r
- TIMx->EGR = TIM_EventSource;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified TIM flag is set or not.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param TIM_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_FLAG_Update: TIM update Flag\r
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
- * @note\r
- * - TIM6 and TIM7 can have only one update flag.\r
- * - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger,\r
- * TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags \r
- * - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1 or TIM_FLAG_CC1OF flags \r
- * @retval The new state of TIM_FLAG (SET or RESET).\r
- */\r
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
-{ \r
- ITStatus bitstatus = RESET; \r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_GET_FLAG(TIM_FLAG));\r
- \r
- if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the TIMx's pending flags.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param TIM_FLAG: specifies the flag bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg TIM_FLAG_Update: TIM update Flag\r
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
- * @note\r
- * - TIM6 and TIM7 can have only one update flag. \r
- * - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger flags\r
- * TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags \r
- * - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1\r
- * or TIM_FLAG_CC1OF flags \r
- * @retval None\r
- */\r
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));\r
- \r
- /* Clear the flags */\r
- TIMx->SR = (uint16_t)~TIM_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the TIM interrupt has occurred or not.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param TIM_IT: specifies the TIM interrupt source to check.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_IT_Update: TIM update Interrupt source\r
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
- * @note\r
- * - TIM6 and TIM7 can generate only an update interrupt.\r
- * - TIM9 can have only update interrupt, TIM_FLAG_CC1 or TIM_FLAG_CC2,\r
- * interrupt and TIM_IT_Trigger interrupt.\r
- * - TIM10 and TIM11 can have only update interrupt or TIM_FLAG_CC1\r
- * interrupt \r
- * @retval The new state of the TIM_IT(SET or RESET).\r
- */\r
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
-{\r
- ITStatus bitstatus = RESET; \r
- uint16_t itstatus = 0x0, itenable = 0x0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_GET_IT(TIM_IT));\r
- \r
- itstatus = TIMx->SR & TIM_IT;\r
- \r
- itenable = TIMx->DIER & TIM_IT;\r
- if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the TIMx's interrupt pending bits.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param TIM_IT: specifies the pending bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg TIM_IT_Update: TIM update Interrupt source\r
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
- * @note\r
- * - TIM6 and TIM7 can generate only an update interrupt.\r
- * - TIM9 can have only update interrupt, TIM_IT_CC1 or TIM_IT_CC2,\r
- * and TIM_IT_Trigger interrupt. \r
- * - TIM10 and TIM11 can have only update interrupt or TIM_IT_CC1\r
- * interrupt \r
- * @retval None\r
- */\r
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_IT(TIM_IT));\r
- \r
- /* Clear the IT pending Bit */\r
- TIMx->SR = (uint16_t)~TIM_IT;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx\92s DMA interface.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_DMABase: DMA Base address.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,\r
- * TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR,\r
- * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,\r
- * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,\r
- * TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3, \r
- * TIM_DMABase_CCR4, TIM_DMABase_DCR.\r
- * @param TIM_DMABurstLength: DMA Burst length.\r
- * This parameter can be one value between:\r
- * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.\r
- * @retval None\r
- */\r
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); \r
- assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));\r
- /* Set the DMA Base and the DMA Burst Length */\r
- TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx\92s DMA Requests.\r
- * @param TIMx: where x can be 2, 3, 4, 6 or 7 to select the TIM peripheral. \r
- * @param TIM_DMASource: specifies the DMA Request sources.\r
- * This parameter can be any combination of the following values:\r
- * @arg TIM_DMA_Update: TIM update Interrupt source\r
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
- * @arg TIM_DMA_Trigger: TIM Trigger DMA source\r
- * @param NewState: new state of the DMA Request sources.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
- assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the DMA sources */\r
- TIMx->DIER |= TIM_DMASource; \r
- }\r
- else\r
- {\r
- /* Disable the DMA sources */\r
- TIMx->DIER &= (uint16_t)~TIM_DMASource;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the TIMx peripheral Capture Compare DMA source.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param NewState: new state of the Capture Compare DMA source\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Set the CCDS Bit */\r
- TIMx->CR2 |= TIM_CR2_CCDS;\r
- }\r
- else\r
- {\r
- /* Reset the CCDS Bit */\r
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Group5 Clocks management functions\r
- * @brief Clocks management functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- Clocks management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the TIMx internal Clock\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- /* Disable slave mode to clock the prescaler directly with the internal clock */\r
- TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Internal Trigger as External Clock\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_ITRSource: Trigger source.\r
- * This parameter can be one of the following values:\r
- * @param TIM_TS_ITR0: Internal Trigger 0\r
- * @param TIM_TS_ITR1: Internal Trigger 1\r
- * @param TIM_TS_ITR2: Internal Trigger 2\r
- * @param TIM_TS_ITR3: Internal Trigger 3\r
- * @retval None\r
- */\r
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
- /* Select the Internal Trigger */\r
- TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);\r
- /* Select the External clock mode1 */\r
- TIMx->SMCR |= TIM_SlaveMode_External1;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Trigger as External Clock\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_TIxExternalCLKSource: Trigger source.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector\r
- * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1\r
- * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2\r
- * @param TIM_ICPolarity: specifies the TIx Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param ICFilter : specifies the filter value.\r
- * This parameter must be a value between 0x0 and 0xF.\r
- * @retval None\r
- */\r
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
- uint16_t TIM_ICPolarity, uint16_t ICFilter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));\r
- assert_param(IS_TIM_IC_FILTER(ICFilter));\r
- \r
- /* Configure the Timer Input Clock Source */\r
- if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)\r
- {\r
- TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
- }\r
- else\r
- {\r
- TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
- }\r
- /* Select the Trigger source */\r
- TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);\r
- /* Select the External clock mode1 */\r
- TIMx->SMCR |= TIM_SlaveMode_External1;\r
-}\r
-\r
-/**\r
- * @brief Configures the External clock Mode1\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
- * @param ExtTRGFilter: External Trigger Filter.\r
- * This parameter must be a value between 0x00 and 0x0F\r
- * @retval None\r
- */\r
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
- uint16_t ExtTRGFilter)\r
-{\r
- uint16_t tmpsmcr = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
- \r
- /* Configure the ETR Clock source */\r
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
- \r
- /* Get the TIMx SMCR register value */\r
- tmpsmcr = TIMx->SMCR;\r
- /* Reset the SMS Bits */\r
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
- /* Select the External clock mode1 */\r
- tmpsmcr |= TIM_SlaveMode_External1;\r
- /* Select the Trigger selection : ETRF */\r
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
- tmpsmcr |= TIM_TS_ETRF;\r
- /* Write to TIMx SMCR */\r
- TIMx->SMCR = tmpsmcr;\r
-}\r
-\r
-/**\r
- * @brief Configures the External clock Mode2\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
- * @param ExtTRGFilter: External Trigger Filter.\r
- * This parameter must be a value between 0x00 and 0x0F\r
- * @retval None\r
- */\r
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
- \r
- /* Configure the ETR Clock source */\r
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
- /* Enable the External clock mode2 */\r
- TIMx->SMCR |= TIM_SMCR_ECE;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Group6 Synchronization management functions\r
- * @brief Synchronization management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Synchronization management functions\r
- =============================================================================== \r
- \r
- =================================================================== \r
- TIM Driver: how to use it in synchronization Mode\r
- =================================================================== \r
- Case of two/several Timers\r
- **************************\r
- 1. Configure the Master Timers using the following functions:\r
- - void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); \r
- - void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); \r
- 2. Configure the Slave Timers using the following functions: \r
- - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); \r
- - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); \r
- \r
- Case of Timers and external trigger(ETR pin)\r
- ******************************************** \r
- 1. Configure the Etrenal trigger using this function:\r
- - void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
- uint16_t ExtTRGFilter);\r
- 2. Configure the Slave Timers using the following functions: \r
- - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); \r
- - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Selects the Input Trigger source\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_InputTriggerSource: The Input Trigger source.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_TS_ITR0: Internal Trigger 0\r
- * @arg TIM_TS_ITR1: Internal Trigger 1\r
- * @arg TIM_TS_ITR2: Internal Trigger 2\r
- * @arg TIM_TS_ITR3: Internal Trigger 3\r
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r
- * @arg TIM_TS_ETRF: External Trigger input\r
- * @retval None\r
- */\r
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
-{\r
- uint16_t tmpsmcr = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx)); \r
- assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
-\r
- /* Get the TIMx SMCR register value */\r
- tmpsmcr = TIMx->SMCR;\r
- /* Reset the TS Bits */\r
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
- /* Set the Input Trigger source */\r
- tmpsmcr |= TIM_InputTriggerSource;\r
- /* Write to TIMx SMCR */\r
- TIMx->SMCR = tmpsmcr;\r
-}\r
-\r
-/**\r
- * @brief Selects the TIMx Trigger Output Mode.\r
- * @param TIMx: where x can be 2, 3, 4, 6, 7 or 9 to select the TIM peripheral.\r
- * @param TIM_TRGOSource: specifies the Trigger Output source.\r
- * This paramter can be one of the following values:\r
- *\r
- * - For all TIMx\r
- * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).\r
- * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).\r
- * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).\r
- *\r
- * - For all TIMx except TIM6 and TIM7\r
- * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag\r
- * is to be set, as soon as a capture or compare match occurs (TRGO).\r
- * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).\r
-\r
- * - For all TIMx except TIM6, TIM7, TIM10 and TIM11\r
- * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).\r
-\r
- * - For TIM2, TIM3 and TIM4\r
- * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).\r
- * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).\r
- *\r
- * @retval None\r
- */\r
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));\r
- assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));\r
-\r
- /* Reset the MMS Bits */\r
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);\r
- /* Select the TRGO source */\r
- TIMx->CR2 |= TIM_TRGOSource;\r
-}\r
-\r
-/**\r
- * @brief Selects the TIMx Slave Mode.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_SlaveMode: specifies the Timer Slave Mode.\r
- * This paramter can be one of the following values:\r
- * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes\r
- * the counter and triggers an update of the registers.\r
- * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.\r
- * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.\r
- * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.\r
- * @retval None\r
- */\r
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx)); \r
- assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));\r
- \r
- /* Reset the SMS Bits */\r
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);\r
- /* Select the Slave Mode */\r
- TIMx->SMCR |= TIM_SlaveMode;\r
-}\r
-\r
-/**\r
- * @brief Sets or Resets the TIMx Master/Slave Mode.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.\r
- * This paramter can be one of the following values:\r
- * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer\r
- * and its slaves (through TRGO).\r
- * @arg TIM_MasterSlaveMode_Disable: No action\r
- * @retval None\r
- */\r
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));\r
- \r
- /* Reset the MSM Bit */\r
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);\r
- \r
- /* Set or Reset the MSM Bit */\r
- TIMx->SMCR |= TIM_MasterSlaveMode;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx External Trigger (ETR).\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
- * @param ExtTRGFilter: External Trigger Filter.\r
- * This parameter must be a value between 0x00 and 0x0F\r
- * @retval None\r
- */\r
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
- uint16_t ExtTRGFilter)\r
-{\r
- uint16_t tmpsmcr = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
- \r
- tmpsmcr = TIMx->SMCR;\r
- /* Reset the ETR Bits */\r
- tmpsmcr &= SMCR_ETR_MASK;\r
- /* Set the Prescaler, the Filter value and the Polarity */\r
- tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));\r
- /* Write to TIMx SMCR */\r
- TIMx->SMCR = tmpsmcr;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Group7 Specific interface management functions\r
- * @brief Specific interface management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Specific interface management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the TIMx Encoder Interface.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.\r
- * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.\r
- * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending\r
- * on the level of the other input.\r
- * @param TIM_IC1Polarity: specifies the IC1 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
- * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
- * @param TIM_IC2Polarity: specifies the IC2 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
- * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
- * @retval None\r
- */\r
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)\r
-{\r
- uint16_t tmpsmcr = 0;\r
- uint16_t tmpccmr1 = 0;\r
- uint16_t tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));\r
- assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));\r
- assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));\r
- \r
- /* Get the TIMx SMCR register value */\r
- tmpsmcr = TIMx->SMCR;\r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- /* Set the encoder Mode */\r
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
- tmpsmcr |= TIM_EncoderMode;\r
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));\r
- tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;\r
- /* Set the TI1 and the TI2 Polarities */\r
- tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));\r
- tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));\r
- /* Write to TIMx SMCR */\r
- TIMx->SMCR = tmpsmcr;\r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmr1;\r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx\92s Hall sensor interface.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param NewState: new state of the TIMx Hall sensor interface.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Set the TI1S Bit */\r
- TIMx->CR2 |= TIM_CR2_TI1S;\r
- }\r
- else\r
- {\r
- /* Reset the TI1S Bit */\r
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Group8 Specific remapping management function\r
- * @brief Specific remapping management function\r
- *\r
-@verbatim \r
- ===============================================================================\r
- Specific remapping management function\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the TIM9, TIM10 and TIM11 Remapping input Capabilities.\r
- * @param TIMx: where x can be 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_Remap: specifies the TIM input remapping source.\r
- * This parameter can be one of the following values:\r
- * @arg TIM9_GPIO: TIM9 Channel 1 is connected to dedicated Timer pin(default)\r
- * @arg TIM9_LSE: TIM9 Channel 1 is connected to LSE clock.\r
- * @arg TIM10_GPIO: TIM10 Channel 1 is connected to dedicated Timer pin(default) \r
- * @arg TIM10_LSI: TIM10 Channel 1 is connected to LSI clock.\r
- * @arg TIM10_LSE: TIM10 Channel 1 is connected to LSE clock.\r
- * @arg TIM10_RTC: TIM10 Channel 1 is connected to RTC Output event. \r
- * @arg TIM11_GPIO: TIM11 Channel 1 is connected to dedicated Timer pin(default) \r
- * @arg TIM11_MSI: TIM11 Channel 1 is connected to MSI clock.\r
- * @arg TIM11_HSE_RTC: TIM11 Channel 1 is connected to HSE_RTC clock. \r
- * @retval None\r
- */\r
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_REMAP(TIM_Remap));\r
-\r
- /* Set the Timer remapping configuration */\r
- TIMx->OR = TIM_Remap;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @brief Configure the TI1 as Input.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param TIM_ICSelection: specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.\r
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.\r
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.\r
- * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- */\r
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter)\r
-{\r
- uint16_t tmpccmr1 = 0, tmpccer = 0;\r
- \r
- /* Disable the Channel 1: Reset the CC1E Bit */\r
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);\r
- tmpccmr1 = TIMx->CCMR1;\r
- tmpccer = TIMx->CCER;\r
- /* Select the Input and set the filter */\r
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));\r
- tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
- /* Select the Polarity and set the CC1E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));\r
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);\r
- /* Write to TIMx CCMR1 and CCER registers */\r
- TIMx->CCMR1 = tmpccmr1;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configure the TI2 as Input.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param TIM_ICSelection: specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.\r
- * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.\r
- * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.\r
- * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- */\r
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter)\r
-{\r
- uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;\r
- \r
- /* Disable the Channel 2: Reset the CC2E Bit */\r
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);\r
- tmpccmr1 = TIMx->CCMR1;\r
- tmpccer = TIMx->CCER;\r
- tmp = (uint16_t)(TIM_ICPolarity << 4);\r
- /* Select the Input and set the filter */\r
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));\r
- tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);\r
- tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);\r
- /* Select the Polarity and set the CC2E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));\r
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);\r
- /* Write to TIMx CCMR1 and CCER registers */\r
- TIMx->CCMR1 = tmpccmr1 ;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configure the TI3 as Input.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param TIM_ICSelection: specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.\r
- * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.\r
- * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.\r
- * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- */\r
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter)\r
-{\r
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
- \r
- /* Disable the Channel 3: Reset the CC3E Bit */\r
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);\r
- tmpccmr2 = TIMx->CCMR2;\r
- tmpccer = TIMx->CCER;\r
- tmp = (uint16_t)(TIM_ICPolarity << 8);\r
- /* Select the Input and set the filter */\r
- tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));\r
- tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
- /* Select the Polarity and set the CC3E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));\r
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);\r
- /* Write to TIMx CCMR2 and CCER registers */\r
- TIMx->CCMR2 = tmpccmr2;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configure the TI4 as Input.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param TIM_ICSelection: specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.\r
- * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.\r
- * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.\r
- * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- */\r
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter)\r
-{\r
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
- \r
- /* Disable the Channel 4: Reset the CC4E Bit */\r
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);\r
- tmpccmr2 = TIMx->CCMR2;\r
- tmpccer = TIMx->CCER;\r
- tmp = (uint16_t)(TIM_ICPolarity << 12);\r
- /* Select the Input and set the filter */\r
- tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));\r
- tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);\r
- tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);\r
-\r
- /* Select the Polarity and set the CC4E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP));\r
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);\r
- /* Write to TIMx CCMR2 and CCER registers */\r
- TIMx->CCMR2 = tmpccmr2;\r
- TIMx->CCER = tmpccer ;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_usart.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Universal synchronous asynchronous receiver\r
- * transmitter (USART): \r
- * - Initialization and Configuration\r
- * - Data transfers\r
- * - Multi-Processor Communication\r
- * - LIN mode\r
- * - Half-duplex mode\r
- * - Smartcard mode\r
- * - IrDA mode\r
- * - DMA transfers management\r
- * - Interrupts and flags management \r
- * \r
- * @verbatim\r
- * \r
- * ===================================================================\r
- * How to use this driver\r
- * ===================================================================\r
- * 1. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)\r
- * function for USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE)\r
- * function for USART2 and USART3.\r
- *\r
- * 2. According to the USART mode, enable the GPIO clocks using \r
- * RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS, \r
- * or and SCLK). \r
- *\r
- * 3. Peripheral\92s alternate function: \r
- * - Connect the pin to the desired peripherals' Alternate \r
- * Function (AF) using GPIO_PinAFConfig() function\r
- * - Configure the desired pin in alternate function by:\r
- * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
- * - Select the type, pull-up/pull-down and output speed via \r
- * GPIO_PuPd, GPIO_OType and GPIO_Speed members\r
- * - Call GPIO_Init() function\r
- * \r
- * 4. Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware \r
- * flow control and Mode(Receiver/Transmitter) using the SPI_Init()\r
- * function.\r
- *\r
- * 5. For synchronous mode, enable the clock and program the polarity,\r
- * phase and last bit using the USART_ClockInit() function.\r
- *\r
- * 5. Enable the NVIC and the corresponding interrupt using the function \r
- * USART_ITConfig() if you need to use interrupt mode. \r
- *\r
- * 6. When using the DMA mode \r
- * - Configure the DMA using DMA_Init() function\r
- * - Active the needed channel Request using USART_DMACmd() function\r
- * \r
- * 7. Enable the USART using the USART_Cmd() function.\r
- * \r
- * 8. Enable the DMA using the DMA_Cmd() function, when using DMA mode. \r
- *\r
- * Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections\r
- * for more details\r
- * \r
- * @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_usart.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup USART \r
- * @brief USART driver modules\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */\r
-#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \\r
- USART_CR1_PS | USART_CR1_TE | \\r
- USART_CR1_RE))\r
-\r
-/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */\r
-#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \\r
- USART_CR2_CPHA | USART_CR2_LBCL))\r
-\r
-/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */\r
-#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))\r
-\r
-/*!< USART Interrupts mask */\r
-#define IT_MASK ((uint16_t)0x001F)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup USART_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup USART_Group1 Initialization and Configuration functions\r
- * @brief Initialization and Configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Initialization and Configuration functions\r
- =============================================================================== \r
-\r
- This subsection provides a set of functions allowing to initialize the USART \r
- in asynchronous and in synchronous modes.\r
- - For the asynchronous mode only these parameters can be configured: \r
- - Baud Rate\r
- - Word Length \r
- - Stop Bit\r
- - Parity: If the parity is enabled, then the MSB bit of the data written\r
- in the data register is transmitted but is changed by the parity bit.\r
- Depending on the frame length defined by the M bit (8-bits or 9-bits),\r
- the possible USART frame formats are as listed in the following table:\r
- +-------------------------------------------------------------+ \r
- | M bit | PCE bit | USART frame |\r
- |---------------------|---------------------------------------| \r
- | 0 | 0 | | SB | 8 bit data | STB | |\r
- |---------|-----------|---------------------------------------| \r
- | 0 | 1 | | SB | 7 bit data | PB | STB | |\r
- |---------|-----------|---------------------------------------| \r
- | 1 | 0 | | SB | 9 bit data | STB | |\r
- |---------|-----------|---------------------------------------| \r
- | 1 | 1 | | SB | 8 bit data | PB | STB | |\r
- +-------------------------------------------------------------+ \r
- - Hardware flow control\r
- - Receiver/transmitter modes\r
-\r
- The USART_Init() function follows the USART asynchronous configuration procedure\r
- (details for the procedure are available in reference manual (RM0038)).\r
-\r
- - For the synchronous mode in addition to the asynchronous mode parameters these \r
- parameters should be also configured:\r
- - USART Clock Enabled\r
- - USART polarity\r
- - USART phase\r
- - USART LastBit\r
- \r
- These parameters can be configured using the USART_ClockInit() function.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
- \r
-/**\r
- * @brief Deinitializes the USARTx peripheral registers to their default reset values.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values: USART1, USART2 or USART3.\r
- * @retval None\r
- */\r
-void USART_DeInit(USART_TypeDef* USARTx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
-\r
- if (USARTx == USART1)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);\r
- }\r
- else if (USARTx == USART2)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);\r
- }\r
- else \r
- {\r
- if (USARTx == USART3)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); \r
- }\r
- } \r
-}\r
-\r
-/**\r
- * @brief Initializes the USARTx peripheral according to the specified\r
- * parameters in the USART_InitStruct .\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure\r
- * that contains the configuration information for the specified USART peripheral.\r
- * @retval None\r
- */\r
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)\r
-{\r
- uint32_t tmpreg = 0x00, apbclock = 0x00;\r
- uint32_t integerdivider = 0x00;\r
- uint32_t fractionaldivider = 0x00;\r
- RCC_ClocksTypeDef RCC_ClocksStatus;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); \r
- assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));\r
- assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));\r
- assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));\r
- assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));\r
- assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));\r
- \r
-/*---------------------------- USART CR2 Configuration -----------------------*/\r
- tmpreg = USARTx->CR2;\r
- /* Clear STOP[13:12] bits */\r
- tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);\r
-\r
- /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/\r
- /* Set STOP[13:12] bits according to USART_StopBits value */\r
- tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;\r
- \r
- /* Write to USART CR2 */\r
- USARTx->CR2 = (uint16_t)tmpreg;\r
-\r
-/*---------------------------- USART CR1 Configuration -----------------------*/\r
- tmpreg = USARTx->CR1;\r
- /* Clear M, PCE, PS, TE and RE bits */\r
- tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);\r
-\r
- /* Configure the USART Word Length, Parity and mode ----------------------- */\r
- /* Set the M bits according to USART_WordLength value */\r
- /* Set PCE and PS bits according to USART_Parity value */\r
- /* Set TE and RE bits according to USART_Mode value */\r
- tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |\r
- USART_InitStruct->USART_Mode;\r
-\r
- /* Write to USART CR1 */\r
- USARTx->CR1 = (uint16_t)tmpreg;\r
-\r
-/*---------------------------- USART CR3 Configuration -----------------------*/ \r
- tmpreg = USARTx->CR3;\r
- /* Clear CTSE and RTSE bits */\r
- tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);\r
-\r
- /* Configure the USART HFC -------------------------------------------------*/\r
- /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */\r
- tmpreg |= USART_InitStruct->USART_HardwareFlowControl;\r
-\r
- /* Write to USART CR3 */\r
- USARTx->CR3 = (uint16_t)tmpreg;\r
-\r
-/*---------------------------- USART BRR Configuration -----------------------*/\r
- /* Configure the USART Baud Rate -------------------------------------------*/\r
- RCC_GetClocksFreq(&RCC_ClocksStatus);\r
- if (USARTx == USART1) \r
- {\r
- apbclock = RCC_ClocksStatus.PCLK2_Frequency;\r
- }\r
- else\r
- {\r
- apbclock = RCC_ClocksStatus.PCLK1_Frequency;\r
- }\r
-\r
- /* Determine the integer part */\r
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)\r
- {\r
- /* Integer part computing in case Oversampling mode is 8 Samples */\r
- integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); \r
- }\r
- else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
- {\r
- /* Integer part computing in case Oversampling mode is 16 Samples */\r
- integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); \r
- }\r
- tmpreg = (integerdivider / 100) << 4;\r
-\r
- /* Determine the fractional part */\r
- fractionaldivider = integerdivider - (100 * (tmpreg >> 4));\r
-\r
- /* Implement the fractional part in the register */\r
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)\r
- {\r
- tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);\r
- }\r
- else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
- {\r
- tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);\r
- }\r
- \r
- /* Write to USART BRR */\r
- USARTx->BRR = (uint16_t)tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each USART_InitStruct member with its default value.\r
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure\r
- * which will be initialized.\r
- * @retval None\r
- */\r
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct)\r
-{\r
- /* USART_InitStruct members default value */\r
- USART_InitStruct->USART_BaudRate = 9600;\r
- USART_InitStruct->USART_WordLength = USART_WordLength_8b;\r
- USART_InitStruct->USART_StopBits = USART_StopBits_1;\r
- USART_InitStruct->USART_Parity = USART_Parity_No ;\r
- USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;\r
- USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; \r
-}\r
-\r
-/**\r
- * @brief Initializes the USARTx peripheral Clock according to the \r
- * specified parameters in the USART_ClockInitStruct .\r
- * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral.\r
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
- * structure that contains the configuration information for the specified \r
- * USART peripheral. \r
- * @retval None\r
- */\r
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)\r
-{\r
- uint32_t tmpreg = 0x00;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));\r
- assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));\r
- assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));\r
- assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));\r
- \r
-/*---------------------------- USART CR2 Configuration -----------------------*/\r
- tmpreg = USARTx->CR2;\r
- /* Clear CLKEN, CPOL, CPHA and LBCL bits */\r
- tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);\r
- /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/\r
- /* Set CLKEN bit according to USART_Clock value */\r
- /* Set CPOL bit according to USART_CPOL value */\r
- /* Set CPHA bit according to USART_CPHA value */\r
- /* Set LBCL bit according to USART_LastBit value */\r
- tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | \r
- USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;\r
- /* Write to USART CR2 */\r
- USARTx->CR2 = (uint16_t)tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each USART_ClockInitStruct member with its default value.\r
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
- * structure which will be initialized.\r
- * @retval None\r
- */\r
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)\r
-{\r
- /* USART_ClockInitStruct members default value */\r
- USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;\r
- USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;\r
- USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;\r
- USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified USART peripheral.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param NewState: new state of the USARTx peripheral.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected USART by setting the UE bit in the CR1 register */\r
- USARTx->CR1 |= USART_CR1_UE;\r
- }\r
- else\r
- {\r
- /* Disable the selected USART by clearing the UE bit in the CR1 register */\r
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Sets the system clock prescaler.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param USART_Prescaler: specifies the prescaler clock. \r
- * @retval None\r
- */\r
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- \r
- /* Clear the USART prescaler */\r
- USARTx->GTPR &= USART_GTPR_GT;\r
- /* Set the USART prescaler */\r
- USARTx->GTPR |= USART_Prescaler;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART's 8x oversampling mode.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3.\r
- * @param NewState: new state of the USART 8x oversampling mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- *\r
- * @note\r
- * This function has to be called before calling USART_Init()\r
- * function in order to have correct baudrate Divider value.\r
- * @retval : None\r
- */\r
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */\r
- USARTx->CR1 |= USART_CR1_OVER8;\r
- }\r
- else\r
- {\r
- /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */\r
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8);\r
- }\r
-} \r
-\r
-/**\r
- * @brief Enables or disables the USART's one bit sampling method.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3.\r
- * @param NewState: new state of the USART one bit sampling method.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval : None\r
- */\r
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */\r
- USARTx->CR3 |= USART_CR3_ONEBIT;\r
- }\r
- else\r
- {\r
- /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */\r
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Group2 Data transfers functions\r
- * @brief Data transfers functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Data transfers functions\r
- =============================================================================== \r
-\r
- This subsection provides a set of functions allowing to manage the USART data \r
- transfers.\r
- \r
- During an USART reception, data shifts in least significant bit first through \r
- the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) \r
- between the internal bus and the received shift register.\r
-\r
- When a transmission is taking place, a write instruction to the USART_DR register \r
- stores the data in the TDR register and which is copied in the shift register \r
- at the end of the current transmission.\r
-\r
- The read access of the USART_DR register can be done using the USART_ReceiveData()\r
- function and returns the RDR buffered value. Whereas a write access to the USART_DR \r
- can be done using USART_SendData() function and stores the written data into \r
- TDR buffer.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Transmits single data through the USARTx peripheral.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param Data: the data to transmit.\r
- * @retval None\r
- */\r
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_DATA(Data)); \r
- \r
- /* Transmit Data */\r
- USARTx->DR = (Data & (uint16_t)0x01FF);\r
-}\r
-\r
-/**\r
- * @brief Returns the most recent received data by the USARTx peripheral.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @retval The received data.\r
- */\r
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- \r
- /* Receive Data */\r
- return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Group3 MultiProcessor Communication functions\r
- * @brief Multi-Processor Communication functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Multi-Processor Communication functions\r
- =============================================================================== \r
-\r
- This subsection provides a set of functions allowing to manage the USART \r
- multiprocessor communication.\r
- \r
- For instance one of the USARTs can be the master, its TX output is connected to \r
- the RX input of the other USART. The others are slaves, their respective TX outputs \r
- are logically ANDed together and connected to the RX input of the master.\r
-\r
- USART multiprocessor communication is possible through the following procedure:\r
- 1. Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter \r
- or Mode receiver and hardware flow control values using the USART_Init()\r
- function.\r
- 2. Configures the USART address using the USART_SetAddress() function.\r
- 3. Configures the wake up methode (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark)\r
- using USART_WakeUpConfig() function only for the slaves.\r
- 4. Enable the USART using the USART_Cmd() function.\r
- 5. Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function.\r
-\r
- The USART Slave exit from mute mode when receive the wake up condition.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Sets the address of the USART node.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param USART_Address: Indicates the address of the USART node.\r
- * @retval None\r
- */\r
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_ADDRESS(USART_Address)); \r
- \r
- /* Clear the USART address */\r
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD);\r
- /* Set the USART address node */\r
- USARTx->CR2 |= USART_Address;\r
-}\r
-\r
-/**\r
- * @brief Determines if the USART is in mute mode or not.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param NewState: new state of the USART mute mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the USART mute mode by setting the RWU bit in the CR1 register */\r
- USARTx->CR1 |= USART_CR1_RWU;\r
- }\r
- else\r
- {\r
- /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */\r
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU);\r
- }\r
-}\r
-/**\r
- * @brief Selects the USART WakeUp method.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param USART_WakeUp: specifies the USART wakeup method.\r
- * This parameter can be one of the following values:\r
- * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection\r
- * @arg USART_WakeUp_AddressMark: WakeUp by an address mark\r
- * @retval None\r
- */\r
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_WAKEUP(USART_WakeUp));\r
- \r
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE);\r
- USARTx->CR1 |= USART_WakeUp;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Group4 LIN mode functions\r
- * @brief LIN mode functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- LIN mode functions\r
- =============================================================================== \r
-\r
- This subsection provides a set of functions allowing to manage the USART LIN \r
- Mode communication.\r
- \r
- In LIN mode, 8-bit data format with 1 stop bit is required in accordance with \r
- the LIN standard.\r
-\r
- Only this LIN Feature is supported by the USART IP:\r
- - LIN Master Synchronous Break send capability and LIN slave break detection\r
- capability : 13-bit break generation and 10/11 bit break detection\r
-\r
-\r
- USART LIN Master transmitter communication is possible through the following procedure:\r
- 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, \r
- Mode transmitter or Mode receiver and hardware flow control values using \r
- the USART_Init() function.\r
- 2. Enable the USART using the USART_Cmd() function.\r
- 3. Enable the LIN mode using the USART_LINCmd() function.\r
- 4. Send the break character using USART_SendBreak() function.\r
-\r
- USART LIN Master receiver communication is possible through the following procedure:\r
- 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, \r
- Mode transmitter or Mode receiver and hardware flow control values using \r
- the USART_Init() function.\r
- 2. Enable the USART using the USART_Cmd() function.\r
- 3. Configures the break detection length using the USART_LINBreakDetectLengthConfig()\r
- function.\r
- 4. Enable the LIN mode using the USART_LINCmd() function.\r
-\r
-Note:\r
-----\r
- 1. In LIN mode, the following bits must be kept cleared:\r
- - CLKEN in the USART_CR2 register,\r
- - STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Sets the USART LIN Break detection length.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param USART_LINBreakDetectLength: specifies the LIN break detection length.\r
- * This parameter can be one of the following values:\r
- * @arg USART_LINBreakDetectLength_10b: 10-bit break detection\r
- * @arg USART_LINBreakDetectLength_11b: 11-bit break detection\r
- * @retval None\r
- */\r
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));\r
- \r
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL);\r
- USARTx->CR2 |= USART_LINBreakDetectLength; \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART\92s LIN mode.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param NewState: new state of the USART LIN mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r
- USARTx->CR2 |= USART_CR2_LINEN;\r
- }\r
- else\r
- {\r
- /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */\r
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Transmits break characters.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @retval None\r
- */\r
-void USART_SendBreak(USART_TypeDef* USARTx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- \r
- /* Send break characters */\r
- USARTx->CR1 |= USART_CR1_SBK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Group5 Halfduplex mode function\r
- * @brief Half-duplex mode function \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Half-duplex mode function\r
- =============================================================================== \r
-\r
- This subsection provides a set of functions allowing to manage the USART \r
- Half-duplex communication.\r
- \r
- The USART can be configured to follow a single-wire half-duplex protocol where \r
- the TX and RX lines are internally connected.\r
-\r
- USART Half duplex communication is possible through the following procedure:\r
- 1. Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter \r
- or Mode receiver and hardware flow control values using the USART_Init()\r
- function.\r
- 2. Configures the USART address using the USART_SetAddress() function.\r
- 3. Enable the USART using the USART_Cmd() function.\r
- 4. Enable the half duplex mode using USART_HalfDuplexCmd() function.\r
-\r
-Note:\r
-----\r
- 1. The RX pin is no longer used\r
- 2. In Half-duplex mode the following bits must be kept cleared:\r
- - LINEN and CLKEN bits in the USART_CR2 register.\r
- - SCEN and IREN bits in the USART_CR3 register.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the USART\92s Half Duplex communication.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param NewState: new state of the USART Communication.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
- USARTx->CR3 |= USART_CR3_HDSEL;\r
- }\r
- else\r
- {\r
- /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */\r
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup USART_Group6 Smartcard mode functions\r
- * @brief Smartcard mode functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Smartcard mode functions\r
- =============================================================================== \r
-\r
- This subsection provides a set of functions allowing to manage the USART \r
- Smartcard communication.\r
- \r
- The Smartcard interface is designed to support asynchronous protocol Smartcards as\r
- defined in the ISO 7816-3 standard.\r
-\r
- The USART can provide a clock to the smartcard through the SCLK output.\r
- In smartcard mode, SCLK is not associated to the communication but is simply derived \r
- from the internal peripheral input clock through a 5-bit prescaler.\r
-\r
- Smartcard communication is possible through the following procedure:\r
- 1. Configures the Smartcard Prsecaler using the USART_SetPrescaler() function.\r
- 2. Configures the Smartcard Guard Time using the USART_SetGuardTime() function.\r
- 3. Program the USART clock using the USART_ClockInit() function as following:\r
- - USART Clock enabled\r
- - USART CPOL Low\r
- - USART CPHA on first edge\r
- - USART Last Bit Clock Enabled\r
- 4. Program the Smartcard interface using the USART_Init() function as following:\r
- - Word Length = 9 Bits\r
- - 1.5 Stop Bit\r
- - Even parity\r
- - BaudRate = 12096 baud\r
- - Hardware flow control disabled (RTS and CTS signals)\r
- - Tx and Rx enabled\r
- 5. Optionally you can enable the parity error interrupt using the USART_ITConfig()\r
- function\r
- 6. Enable the USART using the USART_Cmd() function.\r
- 7. Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.\r
- 8. Enable the Smartcard interface using the USART_SmartCardCmd() function.\r
-\r
- Please refer to the ISO 7816-3 specification for more details.\r
-\r
-Note: \r
------\r
- 1. It is also possible to choose 0.5 stop bit for receiving but it is recommended \r
- to use 1.5 stop bits for both transmitting and receiving to avoid switching \r
- between the two configurations.\r
- 2. In smartcard mode, the following bits must be kept cleared:\r
- - LINEN bit in the USART_CR2 register.\r
- - HDSEL and IREN bits in the USART_CR3 register.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Sets the specified USART guard time.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param USART_GuardTime: specifies the guard time. \r
- * @retval None\r
- */\r
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- \r
- /* Clear the USART Guard time */\r
- USARTx->GTPR &= USART_GTPR_PSC;\r
- /* Set the USART guard time */\r
- USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART\92s Smart Card mode.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param NewState: new state of the Smart Card mode.\r
- * This parameter can be: ENABLE or DISABLE. \r
- * @retval None\r
- */\r
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the SC mode by setting the SCEN bit in the CR3 register */\r
- USARTx->CR3 |= USART_CR3_SCEN;\r
- }\r
- else\r
- {\r
- /* Disable the SC mode by clearing the SCEN bit in the CR3 register */\r
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables NACK transmission.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param NewState: new state of the NACK transmission.\r
- * This parameter can be: ENABLE or DISABLE. \r
- * @retval None\r
- */\r
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the NACK transmission by setting the NACK bit in the CR3 register */\r
- USARTx->CR3 |= USART_CR3_NACK;\r
- }\r
- else\r
- {\r
- /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */\r
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Group7 IrDA mode functions\r
- * @brief IrDA mode functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- IrDA mode functions\r
- =============================================================================== \r
-\r
- This subsection provides a set of functions allowing to manage the USART \r
- IrDA communication.\r
- \r
- IrDA is a half duplex communication protocol. If the Transmitter is busy, any data\r
- on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver \r
- is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.\r
- While receiving data, transmission should be avoided as the data to be transmitted\r
- could be corrupted.\r
-\r
- IrDA communication is possible through the following procedure:\r
- 1. Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver \r
- modes and hardware flow control values using the USART_Init() function.\r
- 2. Enable the USART using the USART_Cmd() function.\r
- 3. Configures the IrDA pulse width by configuring the prescaler using \r
- the USART_SetPrescaler() function.\r
- 4. Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode\r
- using the USART_IrDAConfig() function.\r
- 5. Enable the IrDA using the USART_IrDACmd() function.\r
-\r
-Note: \r
------\r
- 1. A pulse of width less than two and greater than one PSC period(s) may or may\r
- not be rejected.\r
- 2. The receiver set up time should be managed by software. The IrDA physical layer\r
- specification specifies a minimum of 10 ms delay between transmission and \r
- reception (IrDA is a half duplex protocol).\r
- 3. In IrDA mode, the following bits must be kept cleared:\r
- - LINEN, STOP and CLKEN bits in the USART_CR2 register.\r
- - SCEN and HDSEL bits in the USART_CR3 register.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the USART\92s IrDA interface.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param USART_IrDAMode: specifies the IrDA mode.\r
- * This parameter can be one of the following values:\r
- * @arg USART_IrDAMode_LowPower\r
- * @arg USART_IrDAMode_Normal\r
- * @retval None\r
- */\r
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));\r
- \r
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP);\r
- USARTx->CR3 |= USART_IrDAMode;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART\92s IrDA interface.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param NewState: new state of the IrDA mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the IrDA mode by setting the IREN bit in the CR3 register */\r
- USARTx->CR3 |= USART_CR3_IREN;\r
- }\r
- else\r
- {\r
- /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */\r
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Group8 DMA transfers management functions\r
- * @brief DMA transfers management functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- DMA transfers management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
- \r
-/**\r
- * @brief Enables or disables the USART\92s DMA interface.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param USART_DMAReq: specifies the DMA request.\r
- * This parameter can be any combination of the following values:\r
- * @arg USART_DMAReq_Tx: USART DMA transmit request\r
- * @arg USART_DMAReq_Rx: USART DMA receive request\r
- * @param NewState: new state of the DMA Request sources.\r
- * This parameter can be: ENABLE or DISABLE. \r
- * @retval None\r
- */\r
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_DMAREQ(USART_DMAReq)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the DMA transfer for selected requests by setting the DMAT and/or\r
- DMAR bits in the USART CR3 register */\r
- USARTx->CR3 |= USART_DMAReq;\r
- }\r
- else\r
- {\r
- /* Disable the DMA transfer for selected requests by clearing the DMAT and/or\r
- DMAR bits in the USART CR3 register */\r
- USARTx->CR3 &= (uint16_t)~USART_DMAReq;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup USART_Group9 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Interrupts and flags management functions\r
- =============================================================================== \r
-\r
- This subsection provides a set of functions allowing to configure the USART \r
- Interrupts sources, DMA channels requests and check or clear the flags or \r
- pending bits status.\r
- The user should identify which mode will be used in his application to manage \r
- the communication: Polling mode, Interrupt mode or DMA mode. \r
- \r
- Polling Mode\r
- =============\r
- In Polling Mode, the SPI communication can be managed by 10 flags:\r
- 1. USART_FLAG_TXE : to indicate the status of the transmit buffer register\r
- 2. USART_FLAG_RXNE : to indicate the status of the receive buffer register\r
- 3. USART_FLAG_TC : to indicate the status of the transmit operation\r
- 4. USART_FLAG_IDLE : to indicate the status of the Idle Line \r
- 5. USART_FLAG_CTS : to indicate the status of the nCTS input\r
- 6. USART_FLAG_LBD : to indicate the status of the LIN break detection\r
- 7. USART_FLAG_NE : to indicate if a noise error occur\r
- 8. USART_FLAG_FE : to indicate if a frame error occur\r
- 9. USART_FLAG_PE : to indicate if a parity error occur\r
- 10. USART_FLAG_ORE : to indicate if an Overrun error occur\r
-\r
- In this Mode it is advised to use the following functions:\r
- - FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
- - void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
-\r
- Interrupt Mode\r
- ===============\r
- In Interrupt Mode, the USART communication can be managed by 8 interrupt sources\r
- and 10 pending bits: \r
-\r
- Pending Bits:\r
- ------------- \r
- 1. USART_IT_TXE : to indicate the status of the transmit buffer register\r
- 2. USART_IT_RXNE : to indicate the status of the receive buffer register\r
- 3. USART_IT_TC : to indicate the status of the transmit operation\r
- 4. USART_IT_IDLE : to indicate the status of the Idle Line \r
- 5. USART_IT_CTS : to indicate the status of the nCTS input\r
- 6. USART_IT_LBD : to indicate the status of the LIN break detection\r
- 7. USART_IT_NE : to indicate if a noise error occur\r
- 8. USART_IT_FE : to indicate if a frame error occur\r
- 9. USART_IT_PE : to indicate if a parity error occur\r
- 10. USART_IT_ORE : to indicate if an Overrun error occur\r
-\r
- Interrupt Source:\r
- -----------------\r
- 1. USART_IT_TXE : specifies the interrupt source for the Tx buffer empty \r
- interrupt. \r
- 2. USART_IT_RXNE : specifies the interrupt source for the Rx buffer not \r
- empty interrupt.\r
- 3. USART_IT_TC : specifies the interrupt source for the Transmit complete \r
- interrupt. \r
- 4. USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. \r
- 5. USART_IT_CTS : specifies the interrupt source for the CTS interrupt. \r
- 6. USART_IT_LBD : specifies the interrupt source for the LIN break detection\r
- interrupt. \r
- 7. USART_IT_PE : specifies the interrupt source for theparity error interrupt. \r
- 8. USART_IT_ERR : specifies the interrupt source for the errors interrupt.\r
-\r
- Note: Some parameters are coded in order to use them as interrupt source or \r
- ---- as pending bits.\r
-\r
- In this Mode it is advised to use the following functions:\r
- - void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);\r
- - ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);\r
- - void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);\r
-\r
- DMA Mode\r
- ========\r
- In DMA Mode, the USART communication can be managed by 2 DMA Channel requests:\r
- 1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request\r
- 2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request\r
-\r
- In this Mode it is advised to use the following function:\r
- - void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified USART interrupts.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.\r
- * This parameter can be one of the following values:\r
- * @arg USART_IT_CTS: CTS change interrupt\r
- * @arg USART_IT_LBD: LIN Break detection interrupt\r
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt\r
- * @arg USART_IT_TC: Transmission complete interrupt\r
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
- * @arg USART_IT_IDLE: Idle line detection interrupt\r
- * @arg USART_IT_PE: Parity Error interrupt\r
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
- * @param NewState: new state of the specified USARTx interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)\r
-{\r
- uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;\r
- uint32_t usartxbase = 0x00;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_CONFIG_IT(USART_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- usartxbase = (uint32_t)USARTx;\r
-\r
- /* Get the USART register index */\r
- usartreg = (((uint8_t)USART_IT) >> 0x05);\r
-\r
- /* Get the interrupt position */\r
- itpos = USART_IT & IT_MASK;\r
- itmask = (((uint32_t)0x01) << itpos);\r
- \r
- if (usartreg == 0x01) /* The IT is in CR1 register */\r
- {\r
- usartxbase += 0x0C;\r
- }\r
- else if (usartreg == 0x02) /* The IT is in CR2 register */\r
- {\r
- usartxbase += 0x10;\r
- }\r
- else /* The IT is in CR3 register */\r
- {\r
- usartxbase += 0x14; \r
- }\r
- if (NewState != DISABLE)\r
- {\r
- *(__IO uint32_t*)usartxbase |= itmask;\r
- }\r
- else\r
- {\r
- *(__IO uint32_t*)usartxbase &= ~itmask;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified USART flag is set or not.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param USART_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg USART_FLAG_CTS: CTS Change flag\r
- * @arg USART_FLAG_LBD: LIN Break detection flag\r
- * @arg USART_FLAG_TXE: Transmit data register empty flag\r
- * @arg USART_FLAG_TC: Transmission Complete flag\r
- * @arg USART_FLAG_RXNE: Receive data register not empty flag\r
- * @arg USART_FLAG_IDLE: Idle Line detection flag\r
- * @arg USART_FLAG_ORE: OverRun Error flag\r
- * @arg USART_FLAG_NE: Noise Error flag\r
- * @arg USART_FLAG_FE: Framing Error flag\r
- * @arg USART_FLAG_PE: Parity Error flag\r
- * @retval The new state of USART_FLAG (SET or RESET).\r
- */\r
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_FLAG(USART_FLAG));\r
- \r
- if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the USARTx's pending flags.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param USART_FLAG: specifies the flag to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg USART_FLAG_CTS: CTS Change flag.\r
- * @arg USART_FLAG_LBD: LIN Break detection flag.\r
- * @arg USART_FLAG_TC: Transmission Complete flag.\r
- * @arg USART_FLAG_RXNE: Receive data register not empty flag.\r
- * \r
- * @note\r
- * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
- * error) and IDLE (Idle line detected) flags are cleared by software \r
- * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) \r
- * followed by a read operation to USART_DR register (USART_ReceiveData()).\r
- * - RXNE flag can be also cleared by a read to the USART_DR register \r
- * (USART_ReceiveData()).\r
- * - TC flag can be also cleared by software sequence: a read operation to \r
- * USART_SR register (USART_GetFlagStatus()) followed by a write operation\r
- * to USART_DR register (USART_SendData()).\r
- * - TXE flag is cleared only by a write to the USART_DR register \r
- * (USART_SendData()).\r
- * @retval None\r
- */\r
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));\r
- \r
- USARTx->SR = (uint16_t)~USART_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified USART interrupt has occurred or not.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param USART_IT: specifies the USART interrupt source to check.\r
- * This parameter can be one of the following values:\r
- * @arg USART_IT_CTS: CTS change interrupt\r
- * @arg USART_IT_LBD: LIN Break detection interrupt\r
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt\r
- * @arg USART_IT_TC: Transmission complete interrupt\r
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
- * @arg USART_IT_IDLE: Idle line detection interrupt\r
- * @arg USART_IT_ORE: OverRun Error interrupt\r
- * @arg USART_IT_NE: Noise Error interrupt\r
- * @arg USART_IT_FE: Framing Error interrupt\r
- * @arg USART_IT_PE: Parity Error interrupt\r
- * @retval The new state of USART_IT (SET or RESET).\r
- */\r
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)\r
-{\r
- uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;\r
- ITStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_GET_IT(USART_IT)); \r
- \r
- /* Get the USART register index */\r
- usartreg = (((uint8_t)USART_IT) >> 0x05);\r
- /* Get the interrupt position */\r
- itmask = USART_IT & IT_MASK;\r
- itmask = (uint32_t)0x01 << itmask;\r
- \r
- if (usartreg == 0x01) /* The IT is in CR1 register */\r
- {\r
- itmask &= USARTx->CR1;\r
- }\r
- else if (usartreg == 0x02) /* The IT is in CR2 register */\r
- {\r
- itmask &= USARTx->CR2;\r
- }\r
- else /* The IT is in CR3 register */\r
- {\r
- itmask &= USARTx->CR3;\r
- }\r
- \r
- bitpos = USART_IT >> 0x08;\r
- bitpos = (uint32_t)0x01 << bitpos;\r
- bitpos &= USARTx->SR;\r
- if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- \r
- return bitstatus; \r
-}\r
-\r
-/**\r
- * @brief Clears the USARTx\92s interrupt pending bits.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param USART_IT: specifies the interrupt pending bit to clear.\r
- * This parameter can be one of the following values:\r
- * @arg USART_IT_CTS: CTS change interrupt\r
- * @arg USART_IT_LBD: LIN Break detection interrupt\r
- * @arg USART_IT_TC: Transmission complete interrupt. \r
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt.\r
- * \r
- * @note\r
- * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
- * error) and IDLE (Idle line detected) pending bits are cleared by \r
- * software sequence: a read operation to USART_SR register \r
- * (USART_GetITStatus()) followed by a read operation to USART_DR register \r
- * (USART_ReceiveData()).\r
- * - RXNE pending bit can be also cleared by a read to the USART_DR register \r
- * (USART_ReceiveData()).\r
- * - TC pending bit can be also cleared by software sequence: a read \r
- * operation to USART_SR register (USART_GetITStatus()) followed by a write \r
- * operation to USART_DR register (USART_SendData()).\r
- * - TXE pending bit is cleared only by a write to the USART_DR register \r
- * (USART_SendData()).\r
- * @retval None\r
- */\r
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)\r
-{\r
- uint16_t bitpos = 0x00, itmask = 0x00;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_CLEAR_IT(USART_IT)); \r
- \r
- bitpos = USART_IT >> 0x08;\r
- itmask = ((uint16_t)0x01 << (uint16_t)bitpos);\r
- USARTx->SR = (uint16_t)~itmask;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_wwdg.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Window watchdog (WWDG) peripheral: \r
- * - Prescaler, Refresh window and Counter configuration\r
- * - WWDG activation\r
- * - Interrupts and flags management\r
- * \r
- * @verbatim\r
- * \r
- * ===================================================================\r
- * WWDG features\r
- * ===================================================================\r
- * \r
- * Once enabled the WWDG generates a system reset on expiry of a programmed\r
- * time period, unless the program refreshes the counter (downcounter) \r
- * before to reach 0x3F value (i.e. a reset is generated when the counter\r
- * value rolls over from 0x40 to 0x3F). \r
- * An MCU reset is also generated if the counter value is refreshed\r
- * before the counter has reached the refresh window value. This \r
- * implies that the counter must be refreshed in a limited window.\r
- * \r
- * Once enabled the WWDG cannot be disabled except by a system reset. \r
- * \r
- * WWDGRST flag in RCC_CSR register can be used to inform when a WWDG\r
- * reset occurs.\r
- * \r
- * The WWDG counter input clock is derived from the APB clock divided \r
- * by a programmable prescaler.\r
- * \r
- * WWDG counter clock = PCLK1 / Prescaler\r
- * WWDG timeout = (WWDG counter clock) * (counter value)\r
- * \r
- * Min-max timeout value @32MHz (PCLK1): ~128us / ~65.6ms\r
- * \r
- * ===================================================================\r
- * How to use this driver\r
- * =================================================================== \r
- * 1. Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function\r
- * \r
- * 2. Configure the WWDG prescaler using WWDG_SetPrescaler() function\r
- * \r
- * 3. Configure the WWDG refresh window using WWDG_SetWindowValue() function\r
- * \r
- * 4. Set the WWDG counter value and start it using WWDG_Enable() function.\r
- * When the WWDG is enabled the counter value should be configured to \r
- * a value greater than 0x40 to prevent generating an immediate reset. \r
- * \r
- * 5. Optionally you can enable the Early wakeup interrupt which is \r
- * generated when the counter reach 0x40.\r
- * Once enabled this interrupt cannot be disabled except by a system reset.\r
- * \r
- * 6. Then the application program must refresh the WWDG counter at regular\r
- * intervals during normal operation to prevent an MCU reset, using\r
- * WWDG_SetCounter() function. This operation must occur only when\r
- * the counter value is lower than the refresh window value, \r
- * programmed using WWDG_SetWindowValue(). \r
- *\r
- * @endverbatim \r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_wwdg.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup WWDG \r
- * @brief WWDG driver modules\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-/* ----------- WWDG registers bit address in the alias region ----------- */\r
-#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)\r
-\r
-/* Alias word address of EWI bit */\r
-#define CFR_OFFSET (WWDG_OFFSET + 0x04)\r
-#define EWI_BitNumber 0x09\r
-#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))\r
-\r
-/* --------------------- WWDG registers bit mask ------------------------ */\r
-\r
-/* CFR register bit mask */\r
-#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)\r
-#define CFR_W_MASK ((uint32_t)0xFFFFFF80)\r
-#define BIT_MASK ((uint8_t)0x7F)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup WWDG_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions\r
- * @brief Prescaler, Refresh window and Counter configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Prescaler, Refresh window and Counter configuration functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the WWDG peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void WWDG_DeInit(void)\r
-{\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Sets the WWDG Prescaler.\r
- * @param WWDG_Prescaler: specifies the WWDG Prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1\r
- * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2\r
- * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4\r
- * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8\r
- * @retval None\r
- */\r
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));\r
- /* Clear WDGTB[1:0] bits */\r
- tmpreg = WWDG->CFR & CFR_WDGTB_MASK;\r
- /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */\r
- tmpreg |= WWDG_Prescaler;\r
- /* Store the new value */\r
- WWDG->CFR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Sets the WWDG window value.\r
- * @param WindowValue: specifies the window value to be compared to the downcounter.\r
- * This parameter value must be lower than 0x80.\r
- * @retval None\r
- */\r
-void WWDG_SetWindowValue(uint8_t WindowValue)\r
-{\r
- __IO uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));\r
- /* Clear W[6:0] bits */\r
-\r
- tmpreg = WWDG->CFR & CFR_W_MASK;\r
-\r
- /* Set W[6:0] bits according to WindowValue value */\r
- tmpreg |= WindowValue & (uint32_t) BIT_MASK;\r
-\r
- /* Store the new value */\r
- WWDG->CFR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables the WWDG Early Wakeup interrupt(EWI).\r
- * @note Once enabled this interrupt cannot be disabled except by a system reset. \r
- * @param None\r
- * @retval None\r
- */\r
-void WWDG_EnableIT(void)\r
-{\r
- *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;\r
-}\r
-\r
-/**\r
- * @brief Sets the WWDG counter value.\r
- * @param Counter: specifies the watchdog counter value.\r
- * This parameter must be a number between 0x40 and 0x7F (to prevent generating\r
- * an immediate reset) \r
- * @retval None\r
- */\r
-void WWDG_SetCounter(uint8_t Counter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_WWDG_COUNTER(Counter));\r
- /* Write to T[6:0] bits to configure the counter value, no need to do\r
- a read-modify-write; writing a 0 to WDGA bit does nothing */\r
- WWDG->CR = Counter & BIT_MASK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup WWDG_Group2 WWDG activation functions\r
- * @brief WWDG activation functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- WWDG activation functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables WWDG and load the counter value. \r
- * @param Counter: specifies the watchdog counter value.\r
- * This parameter must be a number between 0x40 and 0x7F (to prevent generating\r
- * an immediate reset)\r
- * @retval None\r
- */\r
-void WWDG_Enable(uint8_t Counter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_WWDG_COUNTER(Counter));\r
- WWDG->CR = WWDG_CR_WDGA | Counter;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup WWDG_Group3 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Interrupts and flags management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Checks whether the Early Wakeup interrupt flag is set or not.\r
- * @param None\r
- * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)\r
- */\r
-FlagStatus WWDG_GetFlagStatus(void)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- \r
- if ((WWDG->SR) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears Early Wakeup interrupt flag.\r
- * @param None\r
- * @retval None\r
- */\r
-void WWDG_ClearFlag(void)\r
-{\r
- WWDG->SR = (uint32_t)RESET;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-EXECUTABLE=IO_Toggle.elf
-BIN_IMAGE=IO_Toggle.bin
-
-CC=arm-none-eabi-gcc
-OBJCOPY=arm-none-eabi-objcopy
-
-CFLAGS=-g -O2 -mlittle-endian -mthumb
-CFLAGS+=-mcpu=cortex-m4
-CFLAGS+=-ffreestanding -nostdlib
-
-# to run from FLASH
-CFLAGS+=-Wl,-T,stm32_flash.ld
-
-# stm32f4_discovery lib
-CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc
-CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc/device_support
-CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc/core_support
-
-all: $(BIN_IMAGE)
-
-$(BIN_IMAGE): $(EXECUTABLE)
- $(OBJCOPY) -O binary $^ $@
-
-$(EXECUTABLE): main.c system_stm32f4xx.c startup_stm32f4xx.s stm32f4xx_it.c
- $(CC) $(CFLAGS) $^ -o $@ -L../../STM32F4xx_StdPeriph_Driver/build -lSTM32F4xx_StdPeriph_Driver
-
-clean:
- rm -rf $(EXECUTABLE)
- rm -rf $(BIN_IMAGE)
-
-.PHONY: all clean
+++ /dev/null
-/**
- ******************************************************************************
- * @file IO_Toggle/main.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief Main program body
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4_discovery.h"
-#include "stm32f4xx_conf.h"
-
-/** @addtogroup STM32F4_Discovery_Peripheral_Examples
- * @{
- */
-
-/** @addtogroup IO_Toggle
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-GPIO_InitTypeDef GPIO_InitStructure;
-
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-void Delay(__IO uint32_t nCount);
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief Main program
- * @param None
- * @retval None
- */
-int main(void)
-{
- /*!< At this stage the microcontroller clock setting is already configured,
- this is done through SystemInit() function which is called from startup
- file (startup_stm32f4xx.s) before to branch to application main.
- To reconfigure the default setting of SystemInit() function, refer to
- system_stm32f4xx.c file
- */
-
- /* GPIOD Periph clock enable */
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
-
- /* Configure PD12, PD13, PD14 and PD15 in output pushpull mode */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13| GPIO_Pin_14| GPIO_Pin_15;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_Init(GPIOD, &GPIO_InitStructure);
-
- while (1)
- {
- /* PD12 to be toggled */
- GPIO_SetBits(GPIOD, GPIO_Pin_12);
-
- /* Insert delay */
- Delay(0x3FFFFF);
-
- /* PD13 to be toggled */
- GPIO_SetBits(GPIOD, GPIO_Pin_13);
-
- /* Insert delay */
- Delay(0x3FFFFF);
-
- /* PD14 to be toggled */
- GPIO_SetBits(GPIOD, GPIO_Pin_14);
-
- /* Insert delay */
- Delay(0x3FFFFF);
-
- /* PD15 to be toggled */
- GPIO_SetBits(GPIOD, GPIO_Pin_15);
-
- /* Insert delay */
- Delay(0x7FFFFF);
-
- GPIO_ResetBits(GPIOD, GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_14|GPIO_Pin_15);
-
- /* Insert delay */
- Delay(0xFFFFFF);
- }
-}
-
-/**
- * @brief Delay Function.
- * @param nCount:specifies the Delay time length.
- * @retval None
- */
-void Delay(__IO uint32_t nCount)
-{
- while(nCount--)
- {
- }
-}
-
-#ifdef USE_FULL_ASSERT
-
-/**
- * @brief Reports the name of the source file and the source line number
- * where the assert_param error has occurred.
- * @param file: pointer to the source file name
- * @param line: assert_param error line source number
- * @retval None
- */
-void assert_failed(uint8_t* file, uint32_t line)
-{
- /* User can add his own implementation to report the file name and line number,
- ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
- /* Infinite loop */
- while (1)
- {
- }
-}
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- @page GPIO_IOToggle GPIO IO Toggle example
-
- @verbatim
- ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
- * @file IO_Toggle/readme.txt
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief Description of the GPIO IO Toggle example.
- ******************************************************************************
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- ******************************************************************************
- @endverbatim
-
-@par Example Description
-
-This example describes how to toggle the GPIO pins connected on AHB bus.
-
-PD12, PD13, PD14 and PD15 (configured in output pushpull mode) toggles in a forever loop.
- - Set PD12, PD13, PD14 and PD15 by setting corresponding bits in BSRRL register
- - Reset PD12, PD13, PD14 and PD15 by setting corresponding bits in BSRRH register
-
-In this example, HCLK is configured at 168 MHz.
-
-@par Directory contents
-
- - IO_Toggle/stm32f4xx_conf.h Library Configuration file
- - IO_Toggle/stm32f4xx_it.c Interrupt handlers
- - IO_Toggle/stm32f4xx_it.h Interrupt handlers header file
- - IO_Toggle/main.c Main program
- - IO_Toggle/system_stm32f4xx.c STM32F4xx system source file
-
-@par Hardware and Software environment
-
- - This example runs on STM32F4xx Devices Revision A.
-
- - This example has been tested with STM32F4-Discovery (MB997) RevA and can be
- easily tailored to any other development board
-
- - STM32F4-Discovery
- - LED4, LED3, LED5 and LED6 are connected respectively to PD.12, PD.13, PD.14 and PD.15.
-
-
-@par How to use it ?
-
-In order to make the program work, you must do the following :
-
- + EWARM
- - Open the IO_Toggle.eww workspace
- - Rebuild all files: Project->Rebuild all
- - Load project image: Project->Debug
- - Run program: Debug->Go(F5)
-
- + MDK-ARM
- - Open the IO_Toggle.uvproj project
- - Rebuild all files: Project->Rebuild all target files
- - Load project image: Debug->Start/Stop Debug Session
- - Run program: Debug->Run (F5)
-
- + TASKING
- - Open TASKING toolchain.
- - Click on File->Import, select General->'Existing Projects into Workspace'
- and then click "Next".
- - Browse to TASKING workspace directory and select the project "IO_Toggle"
- - Rebuild all project files: Select the project in the "Project explorer"
- window then click on Project->build project menu.
- - Run program: Select the project in the "Project explorer" window then click
- Run->Debug (F11)
-
- + TrueSTUDIO
- - Open the TrueSTUDIO toolchain.
- - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace
- directory.
- - Click on File->Import, select General->'Existing Projects into Workspace'
- and then click "Next".
- - Browse to the TrueSTUDIO workspace directory and select the project "IO_Toggle"
- - Rebuild all project files: Select the project in the "Project explorer"
- window then click on Project->build project menu.
- - Run program: Select the project in the "Project explorer" window then click
- Run->Debug (F11)
-
-
-
- * <h3><center>© COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
+++ /dev/null
-/**
- ******************************************************************************
- * @file startup_stm32f4xx.s
- * @author MCD Application Team
- * @version V1.0.0
- * @date 30-September-2011
- * @brief STM32F4xx Devices vector table for RIDE7 toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the clock system and the external SRAM mounted on
- * STM324xG-EVAL board to be used as data memory (optional,
- * to be enabled by user)
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M4 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m3
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
-
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-/* Call the application's entry point.*/
- bl main
- bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- * @param None
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-*******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
- .word NMI_Handler
- .word HardFault_Handler
- .word MemManage_Handler
- .word BusFault_Handler
- .word UsageFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word DebugMon_Handler
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
- /* External Interrupts */
- .word WWDG_IRQHandler /* Window WatchDog */
- .word PVD_IRQHandler /* PVD through EXTI Line detection */
- .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
- .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
- .word FLASH_IRQHandler /* FLASH */
- .word RCC_IRQHandler /* RCC */
- .word EXTI0_IRQHandler /* EXTI Line0 */
- .word EXTI1_IRQHandler /* EXTI Line1 */
- .word EXTI2_IRQHandler /* EXTI Line2 */
- .word EXTI3_IRQHandler /* EXTI Line3 */
- .word EXTI4_IRQHandler /* EXTI Line4 */
- .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
- .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
- .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
- .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
- .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
- .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
- .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
- .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
- .word CAN1_TX_IRQHandler /* CAN1 TX */
- .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
- .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
- .word CAN1_SCE_IRQHandler /* CAN1 SCE */
- .word EXTI9_5_IRQHandler /* External Line[9:5]s */
- .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
- .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
- .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
- .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .word TIM2_IRQHandler /* TIM2 */
- .word TIM3_IRQHandler /* TIM3 */
- .word TIM4_IRQHandler /* TIM4 */
- .word I2C1_EV_IRQHandler /* I2C1 Event */
- .word I2C1_ER_IRQHandler /* I2C1 Error */
- .word I2C2_EV_IRQHandler /* I2C2 Event */
- .word I2C2_ER_IRQHandler /* I2C2 Error */
- .word SPI1_IRQHandler /* SPI1 */
- .word SPI2_IRQHandler /* SPI2 */
- .word USART1_IRQHandler /* USART1 */
- .word USART2_IRQHandler /* USART2 */
- .word USART3_IRQHandler /* USART3 */
- .word EXTI15_10_IRQHandler /* External Line[15:10]s */
- .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
- .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
- .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
- .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
- .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
- .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
- .word FSMC_IRQHandler /* FSMC */
- .word SDIO_IRQHandler /* SDIO */
- .word TIM5_IRQHandler /* TIM5 */
- .word SPI3_IRQHandler /* SPI3 */
- .word UART4_IRQHandler /* UART4 */
- .word UART5_IRQHandler /* UART5 */
- .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
- .word TIM7_IRQHandler /* TIM7 */
- .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
- .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
- .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
- .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
- .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
- .word ETH_IRQHandler /* Ethernet */
- .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
- .word CAN2_TX_IRQHandler /* CAN2 TX */
- .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
- .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
- .word CAN2_SCE_IRQHandler /* CAN2 SCE */
- .word OTG_FS_IRQHandler /* USB OTG FS */
- .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
- .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
- .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
- .word USART6_IRQHandler /* USART6 */
- .word I2C3_EV_IRQHandler /* I2C3 event */
- .word I2C3_ER_IRQHandler /* I2C3 error */
- .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
- .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
- .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
- .word OTG_HS_IRQHandler /* USB OTG HS */
- .word DCMI_IRQHandler /* DCMI */
- .word CRYP_IRQHandler /* CRYP crypto */
- .word HASH_RNG_IRQHandler /* Hash and Rng */
- .word FPU_IRQHandler /* FPU */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak MemManage_Handler
- .thumb_set MemManage_Handler,Default_Handler
-
- .weak BusFault_Handler
- .thumb_set BusFault_Handler,Default_Handler
-
- .weak UsageFault_Handler
- .thumb_set UsageFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_IRQHandler
- .thumb_set PVD_IRQHandler,Default_Handler
-
- .weak TAMP_STAMP_IRQHandler
- .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
-
- .weak RTC_WKUP_IRQHandler
- .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
- .thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
- .thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_IRQHandler
- .thumb_set EXTI2_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
- .thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
- .thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream0_IRQHandler
- .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
-
- .weak DMA1_Stream1_IRQHandler
- .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
-
- .weak DMA1_Stream2_IRQHandler
- .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
-
- .weak DMA1_Stream3_IRQHandler
- .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
-
- .weak DMA1_Stream4_IRQHandler
- .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream5_IRQHandler
- .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
-
- .weak DMA1_Stream6_IRQHandler
- .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
-
- .weak ADC_IRQHandler
- .thumb_set ADC_IRQHandler,Default_Handler
-
- .weak CAN1_TX_IRQHandler
- .thumb_set CAN1_TX_IRQHandler,Default_Handler
-
- .weak CAN1_RX0_IRQHandler
- .thumb_set CAN1_RX0_IRQHandler,Default_Handler
-
- .weak CAN1_RX1_IRQHandler
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
- .weak CAN1_SCE_IRQHandler
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
- .weak EXTI9_5_IRQHandler
- .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_TIM9_IRQHandler
- .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
-
- .weak TIM1_UP_TIM10_IRQHandler
- .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
-
- .weak TIM1_TRG_COM_TIM11_IRQHandler
- .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM4_IRQHandler
- .thumb_set TIM4_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
- .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
- .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
- .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
- .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak USART3_IRQHandler
- .thumb_set USART3_IRQHandler,Default_Handler
-
- .weak EXTI15_10_IRQHandler
- .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak OTG_FS_WKUP_IRQHandler
- .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
-
- .weak TIM8_BRK_TIM12_IRQHandler
- .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
- .weak TIM8_UP_TIM13_IRQHandler
- .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
- .weak TIM8_TRG_COM_TIM14_IRQHandler
- .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
- .weak TIM8_CC_IRQHandler
- .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
- .weak DMA1_Stream7_IRQHandler
- .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
-
- .weak FSMC_IRQHandler
- .thumb_set FSMC_IRQHandler,Default_Handler
-
- .weak SDIO_IRQHandler
- .thumb_set SDIO_IRQHandler,Default_Handler
-
- .weak TIM5_IRQHandler
- .thumb_set TIM5_IRQHandler,Default_Handler
-
- .weak SPI3_IRQHandler
- .thumb_set SPI3_IRQHandler,Default_Handler
-
- .weak UART4_IRQHandler
- .thumb_set UART4_IRQHandler,Default_Handler
-
- .weak UART5_IRQHandler
- .thumb_set UART5_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM7_IRQHandler
- .thumb_set TIM7_IRQHandler,Default_Handler
-
- .weak DMA2_Stream0_IRQHandler
- .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
-
- .weak DMA2_Stream1_IRQHandler
- .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
-
- .weak DMA2_Stream2_IRQHandler
- .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
-
- .weak DMA2_Stream3_IRQHandler
- .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
-
- .weak DMA2_Stream4_IRQHandler
- .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
-
- .weak ETH_IRQHandler
- .thumb_set ETH_IRQHandler,Default_Handler
-
- .weak ETH_WKUP_IRQHandler
- .thumb_set ETH_WKUP_IRQHandler,Default_Handler
-
- .weak CAN2_TX_IRQHandler
- .thumb_set CAN2_TX_IRQHandler,Default_Handler
-
- .weak CAN2_RX0_IRQHandler
- .thumb_set CAN2_RX0_IRQHandler,Default_Handler
-
- .weak CAN2_RX1_IRQHandler
- .thumb_set CAN2_RX1_IRQHandler,Default_Handler
-
- .weak CAN2_SCE_IRQHandler
- .thumb_set CAN2_SCE_IRQHandler,Default_Handler
-
- .weak OTG_FS_IRQHandler
- .thumb_set OTG_FS_IRQHandler,Default_Handler
-
- .weak DMA2_Stream5_IRQHandler
- .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
-
- .weak DMA2_Stream6_IRQHandler
- .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
-
- .weak DMA2_Stream7_IRQHandler
- .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
-
- .weak USART6_IRQHandler
- .thumb_set USART6_IRQHandler,Default_Handler
-
- .weak I2C3_EV_IRQHandler
- .thumb_set I2C3_EV_IRQHandler,Default_Handler
-
- .weak I2C3_ER_IRQHandler
- .thumb_set I2C3_ER_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_OUT_IRQHandler
- .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_IN_IRQHandler
- .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
-
- .weak OTG_HS_WKUP_IRQHandler
- .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
-
- .weak OTG_HS_IRQHandler
- .thumb_set OTG_HS_IRQHandler,Default_Handler
-
- .weak DCMI_IRQHandler
- .thumb_set DCMI_IRQHandler,Default_Handler
-
- .weak CRYP_IRQHandler
- .thumb_set CRYP_IRQHandler,Default_Handler
-
- .weak HASH_RNG_IRQHandler
- .thumb_set HASH_RNG_IRQHandler,Default_Handler
-
- .weak FPU_IRQHandler
- .thumb_set FPU_IRQHandler,Default_Handler
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/*
-*****************************************************************************
-**
-** File : stm32_flash.ld
-**
-** Abstract : Linker script for STM32F407VG Device with
-** 1024KByte FLASH, 192KByte RAM
-**
-** Set heap size, stack size and stack location according
-** to application requirements.
-**
-** Set memory bank area and size if external memory is used.
-**
-** Target : STMicroelectronics STM32
-**
-** Environment : Atollic TrueSTUDIO(R)
-**
-** Distribution: The file is distributed \93as is,\94 without any warranty
-** of any kind.
-**
-** (c)Copyright Atollic AB.
-** You may use this file as-is or modify it according to the needs of your
-** project. Distribution of this file (unmodified or modified) is not
-** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
-** rights to distribute the assembled, compiled & linked contents of this
-** file as part of an application binary file, provided that it is built
-** using the Atollic TrueSTUDIO(R) toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20020000; /* end of 128K RAM on AHB bus*/
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0; /* required amount of heap */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
- RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K
- MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
-}
-
-/* Define output sections */
-SECTIONS
-{
- /* The startup code goes first into FLASH */
- .isr_vector :
- {
- . = ALIGN(4);
- KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
- } >FLASH
-
- /* The program code and other data goes into FLASH */
- .text :
- {
- . = ALIGN(4);
- *(.text) /* .text sections (code) */
- *(.text*) /* .text* sections (code) */
- *(.rodata) /* .rodata sections (constants, strings, etc.) */
- *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
- *(.glue_7) /* glue arm to thumb code */
- *(.glue_7t) /* glue thumb to arm code */
- *(.eh_frame)
-
- KEEP (*(.init))
- KEEP (*(.fini))
-
- . = ALIGN(4);
- _etext = .; /* define a global symbols at end of code */
- } >FLASH
-
-
- .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
- .ARM : {
- __exidx_start = .;
- *(.ARM.exidx*)
- __exidx_end = .;
- } >FLASH
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array*))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >FLASH
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array*))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >FLASH
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(.fini_array*))
- KEEP (*(SORT(.fini_array.*)))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } >FLASH
-
- /* used by the startup to initialize data */
- _sidata = .;
-
- /* Initialized data sections goes into RAM, load LMA copy after code */
- .data : AT ( _sidata )
- {
- . = ALIGN(4);
- _sdata = .; /* create a global symbol at data start */
- *(.data) /* .data sections */
- *(.data*) /* .data* sections */
-
- . = ALIGN(4);
- _edata = .; /* define a global symbol at data end */
- } >RAM
-
- /* Uninitialized data section */
- . = ALIGN(4);
- .bss :
- {
- /* This is used by the startup in order to initialize the .bss secion */
- _sbss = .; /* define a global symbol at bss start */
- __bss_start__ = _sbss;
- *(.bss)
- *(.bss*)
- *(COMMON)
-
- . = ALIGN(4);
- _ebss = .; /* define a global symbol at bss end */
- __bss_end__ = _ebss;
- } >RAM
-
- /* User_heap_stack section, used to check that there is enough RAM left */
- ._user_heap_stack :
- {
- . = ALIGN(4);
- PROVIDE ( end = . );
- PROVIDE ( _end = . );
- . = . + _Min_Heap_Size;
- . = . + _Min_Stack_Size;
- . = ALIGN(4);
- } >RAM
-
- /* MEMORY_bank1 section, code must be located here explicitly */
- /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
- .memory_b1_text :
- {
- *(.mb1text) /* .mb1text sections (code) */
- *(.mb1text*) /* .mb1text* sections (code) */
- *(.mb1rodata) /* read-only data (constants) */
- *(.mb1rodata*)
- } >MEMORY_B1
-
- /* Remove information from the standard libraries */
- /DISCARD/ :
- {
- libc.a ( * )
- libm.a ( * )
- libgcc.a ( * )
- }
-
- .ARM.attributes 0 : { *(.ARM.attributes) }
-}
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4_discovery.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief This file contains definitions for STM32F4-Discovery Kit's Leds and
- * push-button hardware resources.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4_DISCOVERY_H
-#define __STM32F4_DISCOVERY_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
- #include "stm32f4xx.h"
-
-/** @addtogroup Utilities
- * @{
- */
-
-/** @addtogroup STM32F4_DISCOVERY
- * @{
- */
-
-/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL
- * @{
- */
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Types
- * @{
- */
-typedef enum
-{
- LED4 = 0,
- LED3 = 1,
- LED5 = 2,
- LED6 = 3
-} Led_TypeDef;
-
-typedef enum
-{
- BUTTON_USER = 0,
-} Button_TypeDef;
-
-typedef enum
-{
- BUTTON_MODE_GPIO = 0,
- BUTTON_MODE_EXTI = 1
-} ButtonMode_TypeDef;
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Constants
- * @{
- */
-
-/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL_LED
- * @{
- */
-#define LEDn 4
-
-#define LED4_PIN GPIO_Pin_12
-#define LED4_GPIO_PORT GPIOD
-#define LED4_GPIO_CLK RCC_AHB1Periph_GPIOD
-
-#define LED3_PIN GPIO_Pin_13
-#define LED3_GPIO_PORT GPIOD
-#define LED3_GPIO_CLK RCC_AHB1Periph_GPIOD
-
-#define LED5_PIN GPIO_Pin_14
-#define LED5_GPIO_PORT GPIOD
-#define LED5_GPIO_CLK RCC_AHB1Periph_GPIOD
-
-#define LED6_PIN GPIO_Pin_15
-#define LED6_GPIO_PORT GPIOD
-#define LED6_GPIO_CLK RCC_AHB1Periph_GPIOD
-/**
- * @}
- */
-
-/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL_BUTTON
- * @{
- */
-#define BUTTONn 1
-
-/**
- * @brief Wakeup push-button
- */
-#define USER_BUTTON_PIN GPIO_Pin_0
-#define USER_BUTTON_GPIO_PORT GPIOA
-#define USER_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOA
-#define USER_BUTTON_EXTI_LINE EXTI_Line0
-#define USER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA
-#define USER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0
-#define USER_BUTTON_EXTI_IRQn EXTI0_IRQn
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Functions
- * @{
- */
-void STM_EVAL_LEDInit(Led_TypeDef Led);
-void STM_EVAL_LEDOn(Led_TypeDef Led);
-void STM_EVAL_LEDOff(Led_TypeDef Led);
-void STM_EVAL_LEDToggle(Led_TypeDef Led);
-void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
-uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4_DISCOVERY_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file IO_Toggle/stm32f4xx_conf.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief Library configuration file.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_CONF_H
-#define __STM32F4xx_CONF_H
-
-#if defined (HSE_VALUE)
-/* Redefine the HSE value; it's equal to 8 MHz on the STM32F4-DISCOVERY Kit */
- #undef HSE_VALUE
- #define HSE_VALUE ((uint32_t)8000000)
-#endif /* HSE_VALUE */
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment the line below to enable peripheral header file inclusion */
-#include "stm32f4xx_adc.h"
-#include "stm32f4xx_can.h"
-#include "stm32f4xx_crc.h"
-#include "stm32f4xx_cryp.h"
-#include "stm32f4xx_dac.h"
-#include "stm32f4xx_dbgmcu.h"
-#include "stm32f4xx_dcmi.h"
-#include "stm32f4xx_dma.h"
-#include "stm32f4xx_exti.h"
-#include "stm32f4xx_flash.h"
-#include "stm32f4xx_fsmc.h"
-#include "stm32f4xx_hash.h"
-#include "stm32f4xx_gpio.h"
-#include "stm32f4xx_i2c.h"
-#include "stm32f4xx_iwdg.h"
-#include "stm32f4xx_pwr.h"
-#include "stm32f4xx_rcc.h"
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_rtc.h"
-#include "stm32f4xx_sdio.h"
-#include "stm32f4xx_spi.h"
-#include "stm32f4xx_syscfg.h"
-#include "stm32f4xx_tim.h"
-#include "stm32f4xx_usart.h"
-#include "stm32f4xx_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* If an external clock source is used, then the value of the following define
- should be set to the value of the external clock source, else, if no external
- clock is used, keep this define commented */
-/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */
-
-
-/* Uncomment the line below to expanse the "assert_param" macro in the
- Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT 1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr: If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F4xx_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file IO_Toggle/stm32f4xx_it.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief Main Interrupt Service Routines.
- * This file provides template for all exceptions handler and
- * peripherals interrupt service routine.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_it.h"
-
-/** @addtogroup STM32F4_Discovery_Peripheral_Examples
- * @{
- */
-
-/** @addtogroup IO_Toggle
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/* Cortex-M4 Processor Exceptions Handlers */
-/******************************************************************************/
-
-/**
- * @brief This function handles NMI exception.
- * @param None
- * @retval None
- */
-void NMI_Handler(void)
-{
-}
-
-/**
- * @brief This function handles Hard Fault exception.
- * @param None
- * @retval None
- */
-void HardFault_Handler(void)
-{
- /* Go to infinite loop when Hard Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles Memory Manage exception.
- * @param None
- * @retval None
- */
-void MemManage_Handler(void)
-{
- /* Go to infinite loop when Memory Manage exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles Bus Fault exception.
- * @param None
- * @retval None
- */
-void BusFault_Handler(void)
-{
- /* Go to infinite loop when Bus Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles Usage Fault exception.
- * @param None
- * @retval None
- */
-void UsageFault_Handler(void)
-{
- /* Go to infinite loop when Usage Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles SVCall exception.
- * @param None
- * @retval None
- */
-void SVC_Handler(void)
-{
-}
-
-/**
- * @brief This function handles Debug Monitor exception.
- * @param None
- * @retval None
- */
-void DebugMon_Handler(void)
-{
-}
-
-/**
- * @brief This function handles PendSVC exception.
- * @param None
- * @retval None
- */
-void PendSV_Handler(void)
-{
-}
-
-/**
- * @brief This function handles SysTick Handler.
- * @param None
- * @retval None
- */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/* STM32F4xx Peripherals Interrupt Handlers */
-/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
-/* available peripheral interrupt handler's name please refer to the startup */
-/* file (startup_stm32f4xx.s). */
-/******************************************************************************/
-
-/**
- * @brief This function handles PPP interrupt request.
- * @param None
- * @retval None
- */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file GPIO/IOToggle/stm32f4xx_it.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief This file contains the headers of the interrupt handlers.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_IT_H
-#define __STM32F4xx_IT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file system_stm32f4xx.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
- * This file contains the system clock configuration for STM32F4xx devices,
- * and is generated by the clock configuration tool
- * stm32f4xx_Clock_Configuration_V1.0.0.xls
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
- * and Divider factors, AHB/APBx prescalers and Flash settings),
- * depending on the configuration made in the clock xls tool.
- * This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f4xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (16 MHz) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. If the system clock source selected by user fails to startup, the SystemInit()
- * function will do nothing and HSI still used as system clock source. User can
- * add some code to deal with this issue inside the SetSysClock() function.
- *
- * 4. The default value of HSE crystal is set to 8 MHz, refer to "HSE_VALUE" define
- * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
- * through PLL, and you are using different crystal you have to adapt the HSE
- * value to your own configuration.
- *
- * 5. This file configures the system clock as follows:
- *=============================================================================
- *=============================================================================
- * Supported STM32F4xx device revision | Rev A
- *-----------------------------------------------------------------------------
- * System Clock source | PLL (HSE)
- *-----------------------------------------------------------------------------
- * SYSCLK(Hz) | 168000000
- *-----------------------------------------------------------------------------
- * HCLK(Hz) | 168000000
- *-----------------------------------------------------------------------------
- * AHB Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB1 Prescaler | 4
- *-----------------------------------------------------------------------------
- * APB2 Prescaler | 2
- *-----------------------------------------------------------------------------
- * HSE Frequency(Hz) | 8000000
- *-----------------------------------------------------------------------------
- * PLL_M | 8
- *-----------------------------------------------------------------------------
- * PLL_N | 336
- *-----------------------------------------------------------------------------
- * PLL_P | 2
- *-----------------------------------------------------------------------------
- * PLL_Q | 7
- *-----------------------------------------------------------------------------
- * PLLI2S_N | NA
- *-----------------------------------------------------------------------------
- * PLLI2S_R | NA
- *-----------------------------------------------------------------------------
- * I2S input clock | NA
- *-----------------------------------------------------------------------------
- * VDD(V) | 3.3
- *-----------------------------------------------------------------------------
- * High Performance mode | Enabled
- *-----------------------------------------------------------------------------
- * Flash Latency(WS) | 5
- *-----------------------------------------------------------------------------
- * Prefetch Buffer | OFF
- *-----------------------------------------------------------------------------
- * Instruction cache | ON
- *-----------------------------------------------------------------------------
- * Data cache | ON
- *-----------------------------------------------------------------------------
- * Require 48MHz for USB OTG FS, | Enabled
- * SDIO and RNG clock |
- *-----------------------------------------------------------------------------
- *=============================================================================
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f4xx_system
- * @{
- */
-
-/** @addtogroup STM32F4xx_System_Private_Includes
- * @{
- */
-
-#include "stm32f4xx.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Defines
- * @{
- */
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
- on STM324xG_EVAL board as data memory */
-/* #define DATA_IN_ExtSRAM */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-
-
-/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
-#define PLL_M 8
-#define PLL_N 336
-
-/* SYSCLK = PLL_VCO / PLL_P */
-#define PLL_P 2
-
-/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
-#define PLL_Q 7
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Variables
- * @{
- */
-
- uint32_t SystemCoreClock = 168000000;
-
- __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
- * @{
- */
-
-static void SetSysClock(void);
-#ifdef DATA_IN_ExtSRAM
- static void SystemInit_ExtMemCtl(void);
-#endif /* DATA_IN_ExtSRAM */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the Embedded Flash Interface, the PLL and update the
- * SystemFrequency variable.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-
-#ifdef DATA_IN_ExtSRAM
- SystemInit_ExtMemCtl();
-#endif /* DATA_IN_ExtSRAM */
-
- /* Configure the System clock source, PLL Multiplier and Divider factors,
- AHB/APBx prescalers and Flash settings ----------------------------------*/
- SetSysClock();
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
- * 16 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
- * 25 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate(void)
-{
- uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock source */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock source */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock source */
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
- SYSCLK = PLL_VCO / PLL_P
- */
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-
- pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
- SystemCoreClock = pllvco/pllp;
- break;
- default:
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK frequency --------------------------------------------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @brief Configures the System clock source, PLL Multiplier and Divider factors,
- * AHB/APBx prescalers and Flash settings
- * @Note This function should be called only once the RCC clock configuration
- * is reset to the default reset state (done in SystemInit() function).
- * @param None
- * @retval None
- */
-static void SetSysClock(void)
-{
-/******************************************************************************/
-/* PLL (clocked by HSE) used as System clock source */
-/******************************************************************************/
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable high performance mode, System frequency up to 168 MHz */
- RCC->APB1ENR |= RCC_APB1ENR_PWREN;
- PWR->CR |= PWR_CR_PMODE;
-
- /* HCLK = SYSCLK / 1*/
- RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK / 2*/
- RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
-
- /* PCLK1 = HCLK / 4*/
- RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
-
- /* Configure the main PLL */
- RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
- (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
-
- /* Enable the main PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till the main PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
- FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
-
- /* Select the main PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= RCC_CFGR_SW_PLL;
-
- /* Wait till the main PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-
-}
-
-/**
- * @brief Setup the external memory controller. Called in startup_stm32f4xx.s
- * before jump to __main
- * @param None
- * @retval None
- */
-#ifdef DATA_IN_ExtSRAM
-/**
- * @brief Setup the external memory controller.
- * Called in startup_stm32f4xx.s before jump to main.
- * This function configures the external SRAM mounted on STM324xG_EVAL board
- * This SRAM will be used as program data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtl(void)
-{
-/*-- GPIOs Configuration -----------------------------------------------------*/
-/*
- +-------------------+--------------------+------------------+------------------+
- + SRAM pins assignment +
- +-------------------+--------------------+------------------+------------------+
- | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
- | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
- | PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
- | PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
- | PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
- | PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
- | PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
- | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+
- | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 |
- | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 |
- | PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+
- | PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 |
- | | PE15 <-> FSMC_D12 |
- +-------------------+--------------------+
-*/
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
- RCC->AHB1ENR = 0x00000078;
-
- /* Connect PDx pins to FSMC Alternate function */
- GPIOD->AFR[0] = 0x00cc00cc;
- GPIOD->AFR[1] = 0xcc0ccccc;
- /* Configure PDx pins in Alternate function mode */
- GPIOD->MODER = 0xaaaa0a0a;
- /* Configure PDx pins speed to 100 MHz */
- GPIOD->OSPEEDR = 0xffff0f0f;
- /* Configure PDx pins Output type to push-pull */
- GPIOD->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PDx pins */
- GPIOD->PUPDR = 0x00000000;
-
- /* Connect PEx pins to FSMC Alternate function */
- GPIOE->AFR[0] = 0xc00cc0cc;
- GPIOE->AFR[1] = 0xcccccccc;
- /* Configure PEx pins in Alternate function mode */
- GPIOE->MODER = 0xaaaa828a;
- /* Configure PEx pins speed to 100 MHz */
- GPIOE->OSPEEDR = 0xffffc3cf;
- /* Configure PEx pins Output type to push-pull */
- GPIOE->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PEx pins */
- GPIOE->PUPDR = 0x00000000;
-
- /* Connect PFx pins to FSMC Alternate function */
- GPIOF->AFR[0] = 0x00cccccc;
- GPIOF->AFR[1] = 0xcccc0000;
- /* Configure PFx pins in Alternate function mode */
- GPIOF->MODER = 0xaa000aaa;
- /* Configure PFx pins speed to 100 MHz */
- GPIOF->OSPEEDR = 0xff000fff;
- /* Configure PFx pins Output type to push-pull */
- GPIOF->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PFx pins */
- GPIOF->PUPDR = 0x00000000;
-
- /* Connect PGx pins to FSMC Alternate function */
- GPIOG->AFR[0] = 0x00cccccc;
- GPIOG->AFR[1] = 0x000000c0;
- /* Configure PGx pins in Alternate function mode */
- GPIOG->MODER = 0x00080aaa;
- /* Configure PGx pins speed to 100 MHz */
- GPIOG->OSPEEDR = 0x000c0fff;
- /* Configure PGx pins Output type to push-pull */
- GPIOG->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PGx pins */
- GPIOG->PUPDR = 0x00000000;
-
-/*-- FSMC Configuration ------------------------------------------------------*/
- /* Enable the FSMC interface clock */
- RCC->AHB3ENR = 0x00000001;
-
- /* Configure and enable Bank1_SRAM2 */
- FSMC_Bank1->BTCR[2] = 0x00001015;
- FSMC_Bank1->BTCR[3] = 0x00010603;//0x00010400;
- FSMC_Bank1E->BWTR[2] = 0x0fffffff;
-/*
- Bank1_SRAM2 is configured as follow:
-
- p.FSMC_AddressSetupTime = 3;//0;
- p.FSMC_AddressHoldTime = 0;
- p.FSMC_DataSetupTime = 6;//4;
- p.FSMC_BusTurnAroundDuration = 1;
- p.FSMC_CLKDivision = 0;
- p.FSMC_DataLatency = 0;
- p.FSMC_AccessMode = FSMC_AccessMode_A;
-
- FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
- FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
- FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
- FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
- FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
- FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
- FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
- FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
- FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
- FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
- FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
- FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
- FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
- FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
- FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
-*/
-
-}
-#endif /* DATA_IN_ExtSRAM */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-EXECUTABLE=STM32F4-Discovery_Demo.elf
-BIN_IMAGE=STM32F4-Discovery_Demo.bin
-
-CC=arm-none-eabi-gcc
-OBJCOPY=arm-none-eabi-objcopy
-
-CFLAGS=-g -O2 -mlittle-endian -mthumb
-CFLAGS+=-mcpu=cortex-m4
-CFLAGS+=-ffreestanding -nostdlib
-
-#usb_conf.h
-CFLAGS+=-DUSE_USB_OTG_FS=1
-
-# to run from FLASH
-CFLAGS+=-Wl,-T,stm32_flash.ld
-
-CFLAGS+=-I./
-
-# stm32f4_discovery lib
-CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc
-CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc/device_support
-CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc/core_support
-
-#STM32_USB_Device_Library
-CFLAGS+=-I../../STM32_USB_Device_Library/Class/hid/inc
-CFLAGS+=-I../../STM32_USB_Device_Library/Core/inc
-
-#STM32_USB_OTG_Driver
-CFLAGS+=-I../../STM32_USB_OTG_Driver/inc
-
-#STM32F4xx_StdPeriph_Driver\inc
-CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc
-
-#Utilities
-CFLAGS+=-I../../Utilities/STM32F4-Discovery
-
-all: $(BIN_IMAGE)
-
-$(BIN_IMAGE): $(EXECUTABLE)
- $(OBJCOPY) -O binary $^ $@
-
-$(EXECUTABLE): main.c selftest.c system_stm32f4xx.c startup_stm32f4xx.s stm32f4xx_it.c \
- usb_bsp.c usbd_desc.c usbd_usr.c usb_core.c \
- ../../Utilities/STM32F4-Discovery/stm32f4_discovery.c \
- ../../Utilities/STM32F4-Discovery/stm32f4_discovery_audio_codec.c \
- ../../Utilities/STM32F4-Discovery/stm32f4_discovery_lis302dl.c \
- ../../STM32_USB_OTG_Driver/src/usb_dcd_int.c \
- ../../STM32_USB_OTG_Driver/src/usb_dcd.c \
- ../../STM32_USB_Device_Library/Core/src/usbd_core.c \
- ../../STM32_USB_Device_Library/Core/src/usbd_req.c \
- ../../STM32_USB_Device_Library/Core/src/usbd_ioreq.c \
- ../../STM32_USB_Device_Library/Class/hid/src/usbd_hid_core.c \
-
-
- $(CC) $(CFLAGS) $^ -o $@ -L../../STM32F4xx_StdPeriph_Driver/build -lSTM32F4xx_StdPeriph_Driver -L../../STM32F_USB_OTG_Driver/build
-
-clean:
- rm -rf $(EXECUTABLE)
- rm -rf $(BIN_IMAGE)
-
-.PHONY: all clean
+++ /dev/null
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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- <meta content="MCD Application Team" name="author"></head>
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- <tbody>
- <tr>
- <td style="vertical-align: top;">
- <p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
- </td>
- </tr>
- <tr style="">
- <td style="padding: 1.5pt;">
- <h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
-Notes for STM32F4-Discovery Board Demonstration firmware</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
- <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
-2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
- <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
- </td>
- </tr>
- </tbody>
- </table>
- <p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p>
- <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
- <tbody>
- <tr style="">
- <td style="padding: 0cm;" valign="top">
- <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
- <ol style="margin-top: 0cm;" start="1" type="1">
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F4-Discovery Board Demonstration firmware update History</a><o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
- </ol>
- <span style="font-family: "Times New Roman";">
- </span>
- <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F4-Discovery Board Demonstration firmware update History</span></h2><div style="margin-left: 40px;"><span style="font-size: 10pt; font-family: Verdana;">For more information on the STM32F4-Discovery board visit <a href="http://www.st.com/stm32f4-discovery" target="_blank">www.st.com/stm32f4-discovery</a>.</span></div><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 186px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 19-September-2011</span></h3>
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
- <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">First official version of the<span style="font-weight: bold; font-style: italic;"> STM32F4-Discovery Board Demonstration firmware</span></span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"></span></span><br><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
- <p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The
-enclosed firmware and all the related documentation are not covered by
-a License Agreement, if you need such License you can contact your
-local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>
-
- <b><span style="font-size: 10pt; font-family: Verdana; color: black;">THE
-PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
-SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
-ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
-CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
-CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
-THEIR PRODUCTS.</span></b>
-
- <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
- <hr align="center" size="2" width="100%"></span></div>
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
-complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STMicroelectronics<span style="color: black;"> Microcontrollers visit </span><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;">www.st.com</span></u></a></span><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"><a href="http://www.st.com/stm32l" target="_blank"></a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
- </td>
- </tr>
- </tbody>
- </table>
- <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
- </td>
- </tr>
- </tbody>
-</table>
-</div>
-<p class="MsoNormal"><o:p> </o:p></p>
-</div>
-
-</body></html>
\ No newline at end of file
+++ /dev/null
-/**
- ******************************************************************************
- * @file main.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief Main program body
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-#include "usbd_hid_core.h"
-#include "usbd_usr.h"
-#include "usbd_desc.h"
-
-//Library config for this project!!!!!!!!!!!
-#include "stm32f4xx_conf.h"
-
-/** @addtogroup STM32F4-Discovery_Demo
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-#define TESTRESULT_ADDRESS 0x080FFFFC
-#define ALLTEST_PASS 0x00000000
-#define ALLTEST_FAIL 0x55555555
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment = 4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN USB_OTG_CORE_HANDLE USB_OTG_dev __ALIGN_END;
-
-uint16_t PrescalerValue = 0;
-
-__IO uint32_t TimingDelay;
-__IO uint8_t DemoEnterCondition = 0x00;
-__IO uint8_t UserButtonPressed = 0x00;
-LIS302DL_InitTypeDef LIS302DL_InitStruct;
-LIS302DL_FilterConfigTypeDef LIS302DL_FilterStruct;
-__IO int8_t X_Offset, Y_Offset, Z_Offset = 0x00;
-uint8_t Buffer[6];
-
-/* Private function prototypes -----------------------------------------------*/
-static uint32_t Demo_USBConfig(void);
-static void TIM4_Config(void);
-static void Demo_Exec(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief Main program.
- * @param None
- * @retval None
- */
-int main(void)
-{
- RCC_ClocksTypeDef RCC_Clocks;
-
- /* Initialize LEDs and User_Button on STM32F4-Discovery --------------------*/
- STM_EVAL_PBInit(BUTTON_USER, BUTTON_MODE_EXTI);
-
- STM_EVAL_LEDInit(LED4);
- STM_EVAL_LEDInit(LED3);
- STM_EVAL_LEDInit(LED5);
- STM_EVAL_LEDInit(LED6);
-
- /* SysTick end of count event each 10ms */
- RCC_GetClocksFreq(&RCC_Clocks);
- SysTick_Config(RCC_Clocks.HCLK_Frequency / 100);
-
- if (STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET)
- {
- /* Turn on LEDs available on STM32F4-Discovery ---------------------------*/
- STM_EVAL_LEDOn(LED4);
- STM_EVAL_LEDOn(LED3);
- STM_EVAL_LEDOn(LED5);
- STM_EVAL_LEDOn(LED6);
-
- if ((*(__IO uint32_t*) TESTRESULT_ADDRESS) == ALLTEST_PASS)
- {
- TimingDelay = 300;
- /* Waiting User Button is pressed or Test Program condition verified */
- while ((STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET)&&(TimingDelay != 0x00))
- {}
- }
- else
- {
- /* Waiting User Button is Released or TimeOut*/
- TimingDelay = 300;
- while ((STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET)&&(TimingDelay != 0x00))
- {}
- if (STM_EVAL_PBGetState(BUTTON_USER) == Bit_RESET)
- {
- TimingDelay = 0x00;
- }
- }
- if (TimingDelay == 0x00)
- {
- /* Turn off LEDs available on STM32F4-Discovery ------------------------*/
- STM_EVAL_LEDOff(LED4);
- STM_EVAL_LEDOff(LED3);
- STM_EVAL_LEDOff(LED5);
- STM_EVAL_LEDOff(LED6);
-
- /* Waiting User Button is released */
- while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET)
- {}
-
- /* Unlocks the FLASH control register access */
- FLASH_Unlock();
-
- /* Move discovery kit to detect negative and positive acceleration values
- on X, Y and Z axis */
- Accelerometer_MEMS_Test();
-
- /* USB Hardware connection */
- USB_Test();
-
- /* Audio Hardware connection */
- Audio_Test();
-
- /* Microphone MEMS Hardware connection */
- Microphone_MEMS_Test();
-
- /* Write PASS code at last word in the flash memory */
- FLASH_ProgramWord(TESTRESULT_ADDRESS, ALLTEST_PASS);
-
- while(1)
- {
- /* Toggle Green LED: signaling the End of the Test program */
- STM_EVAL_LEDToggle(LED4);
- Delay(10);
- }
- }
- else
- {
- Demo_Exec();
- }
- }
- else
- {
- Demo_Exec();
- }
-}
-
-/**
- * @brief Execute the demo application.
- * @param None
- * @retval None
- */
-static void Demo_Exec(void)
-{
- RCC_ClocksTypeDef RCC_Clocks;
- uint8_t togglecounter = 0x00;
-
- while(1)
- {
- DemoEnterCondition = 0x00;
-
- /* Reset UserButton_Pressed variable */
- UserButtonPressed = 0x00;
-
- /* Initialize LEDs to be managed by GPIO */
- STM_EVAL_LEDInit(LED4);
- STM_EVAL_LEDInit(LED3);
- STM_EVAL_LEDInit(LED5);
- STM_EVAL_LEDInit(LED6);
-
- /* SysTick end of count event each 10ms */
- RCC_GetClocksFreq(&RCC_Clocks);
- SysTick_Config(RCC_Clocks.HCLK_Frequency / 100);
-
- /* Turn OFF all LEDs */
- STM_EVAL_LEDOff(LED4);
- STM_EVAL_LEDOff(LED3);
- STM_EVAL_LEDOff(LED5);
- STM_EVAL_LEDOff(LED6);
-
- /* Waiting User Button is pressed */
- while (UserButtonPressed == 0x00)
- {
- /* Toggle LED4 */
- STM_EVAL_LEDToggle(LED4);
- Delay(10);
- /* Toggle LED4 */
- STM_EVAL_LEDToggle(LED3);
- Delay(10);
- /* Toggle LED4 */
- STM_EVAL_LEDToggle(LED5);
- Delay(10);
- /* Toggle LED4 */
- STM_EVAL_LEDToggle(LED6);
- Delay(10);
- togglecounter ++;
- if (togglecounter == 0x10)
- {
- togglecounter = 0x00;
- while (togglecounter < 0x10)
- {
- STM_EVAL_LEDToggle(LED4);
- STM_EVAL_LEDToggle(LED3);
- STM_EVAL_LEDToggle(LED5);
- STM_EVAL_LEDToggle(LED6);
- Delay(10);
- togglecounter ++;
- }
- togglecounter = 0x00;
- }
- }
-
- /* Waiting User Button is Released */
- while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET)
- {}
- UserButtonPressed = 0x00;
-
- /* TIM4 channels configuration */
- TIM4_Config();
-
- /* Disable all Timer4 channels */
- TIM_CCxCmd(TIM4, TIM_Channel_1, DISABLE);
- TIM_CCxCmd(TIM4, TIM_Channel_2, DISABLE);
- TIM_CCxCmd(TIM4, TIM_Channel_3, DISABLE);
- TIM_CCxCmd(TIM4, TIM_Channel_4, DISABLE);
-
- /* MEMS configuration */
- LIS302DL_InitStruct.Power_Mode = LIS302DL_LOWPOWERMODE_ACTIVE;
- LIS302DL_InitStruct.Output_DataRate = LIS302DL_DATARATE_100;
- LIS302DL_InitStruct.Axes_Enable = LIS302DL_XYZ_ENABLE;
- LIS302DL_InitStruct.Full_Scale = LIS302DL_FULLSCALE_2_3;
- LIS302DL_InitStruct.Self_Test = LIS302DL_SELFTEST_NORMAL;
- LIS302DL_Init(&LIS302DL_InitStruct);
-
- /* Required delay for the MEMS Accelerometre: Turn-on time = 3/Output data Rate
- = 3/100 = 30ms */
- Delay(30);
-
- DemoEnterCondition = 0x01;
- /* MEMS High Pass Filter configuration */
- LIS302DL_FilterStruct.HighPassFilter_Data_Selection = LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER;
- LIS302DL_FilterStruct.HighPassFilter_CutOff_Frequency = LIS302DL_HIGHPASSFILTER_LEVEL_1;
- LIS302DL_FilterStruct.HighPassFilter_Interrupt = LIS302DL_HIGHPASSFILTERINTERRUPT_1_2;
- LIS302DL_FilterConfig(&LIS302DL_FilterStruct);
-
- LIS302DL_Read(Buffer, LIS302DL_OUT_X_ADDR, 6);
- X_Offset = Buffer[0];
- Y_Offset = Buffer[2];
- Z_Offset = Buffer[4];
-
- /* USB configuration */
- Demo_USBConfig();
-
- /* Waiting User Button is pressed */
- while (UserButtonPressed == 0x00)
- {}
-
- /* Waiting User Button is Released */
- while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET)
- {}
-
- /* Disable SPI1 used to drive the MEMS accelerometre */
- SPI_Cmd(LIS302DL_SPI, DISABLE);
-
- /* Disconnect the USB device */
- DCD_DevDisconnect(&USB_OTG_dev);
- USB_OTG_StopDevice(&USB_OTG_dev);
- }
-}
-
-/**
- * @brief Initializes the USB for the demonstration application.
- * @param None
- * @retval None
- */
-static uint32_t Demo_USBConfig(void)
-{
- USBD_Init(&USB_OTG_dev,
- USB_OTG_FS_CORE_ID,
- &USR_desc,
- &USBD_HID_cb,
- &USR_cb);
-
- return 0;
-}
-
-/**
- * @brief Configures the TIM Peripheral.
- * @param None
- * @retval None
- */
-static void TIM4_Config(void)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
- TIM_OCInitTypeDef TIM_OCInitStructure;
- TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
-
- /* --------------------------- System Clocks Configuration -----------------*/
- /* TIM4 clock enable */
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
-
- /* GPIOD clock enable */
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
-
- /*-------------------------- GPIO Configuration ----------------------------*/
- /* GPIOD Configuration: Pins 12, 13, 14 and 15 in output push-pull */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
- GPIO_Init(GPIOD, &GPIO_InitStructure);
-
- /* Connect TIM4 pins to AF2 */
- GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_TIM4);
- GPIO_PinAFConfig(GPIOD, GPIO_PinSource13, GPIO_AF_TIM4);
- GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_TIM4);
- GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_TIM4);
-
- /* -----------------------------------------------------------------------
- TIM4 Configuration: Output Compare Timing Mode:
-
- In this example TIM4 input clock (TIM4CLK) is set to 2 * APB1 clock (PCLK1),
- since APB1 prescaler is different from 1 (APB1 Prescaler = 4, see system_stm32f4xx.c file).
- TIM4CLK = 2 * PCLK1
- PCLK1 = HCLK / 4
- => TIM4CLK = 2*(HCLK / 4) = HCLK/2 = SystemCoreClock/2
-
- To get TIM4 counter clock at 2 KHz, the prescaler is computed as follows:
- Prescaler = (TIM4CLK / TIM1 counter clock) - 1
- Prescaler = (168 MHz/(2 * 2 KHz)) - 1 = 41999
-
- To get TIM4 output clock at 1 Hz, the period (ARR)) is computed as follows:
- ARR = (TIM4 counter clock / TIM4 output clock) - 1
- = 1999
-
- TIM4 Channel1 duty cycle = (TIM4_CCR1/ TIM4_ARR)* 100 = 50%
- TIM4 Channel2 duty cycle = (TIM4_CCR2/ TIM4_ARR)* 100 = 50%
- TIM4 Channel3 duty cycle = (TIM4_CCR3/ TIM4_ARR)* 100 = 50%
- TIM4 Channel4 duty cycle = (TIM4_CCR4/ TIM4_ARR)* 100 = 50%
-
- ==> TIM4_CCRx = TIM4_ARR/2 = 1000 (where x = 1, 2, 3 and 4).
-
- Note:
- SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f4xx.c file.
- Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate()
- function to update SystemCoreClock variable value. Otherwise, any configuration
- based on this variable will be incorrect.
- ----------------------------------------------------------------------- */
-
-
- /* Compute the prescaler value */
- PrescalerValue = (uint16_t) ((SystemCoreClock /2) / 2000) - 1;
-
- /* Time base configuration */
- TIM_TimeBaseStructure.TIM_Period = TIM_ARR;
- TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue;
- TIM_TimeBaseStructure.TIM_ClockDivision = 0;
- TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
- TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
-
- /* Enable TIM4 Preload register on ARR */
- TIM_ARRPreloadConfig(TIM4, ENABLE);
-
- /* TIM PWM1 Mode configuration: Channel */
- TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
- TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
- TIM_OCInitStructure.TIM_Pulse = TIM_CCR;
- TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
-
- /* Output Compare PWM1 Mode configuration: Channel1 */
- TIM_OC1Init(TIM4, &TIM_OCInitStructure);
- TIM_CCxCmd(TIM4, TIM_Channel_1, DISABLE);
-
- TIM_OC1PreloadConfig(TIM4, TIM_OCPreload_Enable);
-
- /* Output Compare PWM1 Mode configuration: Channel2 */
- TIM_OC2Init(TIM4, &TIM_OCInitStructure);
- TIM_CCxCmd(TIM4, TIM_Channel_2, DISABLE);
-
- TIM_OC2PreloadConfig(TIM4, TIM_OCPreload_Enable);
-
- /* Output Compare PWM1 Mode configuration: Channel3 */
- TIM_OC3Init(TIM4, &TIM_OCInitStructure);
- TIM_CCxCmd(TIM4, TIM_Channel_3, DISABLE);
-
- TIM_OC3PreloadConfig(TIM4, TIM_OCPreload_Enable);
-
- /* Output Compare PWM1 Mode configuration: Channel4 */
- TIM_OC4Init(TIM4, &TIM_OCInitStructure);
- TIM_CCxCmd(TIM4, TIM_Channel_4, DISABLE);
-
- TIM_OC4PreloadConfig(TIM4, TIM_OCPreload_Enable);
-
- /* TIM4 enable counter */
- TIM_Cmd(TIM4, ENABLE);
-}
-
-/**
- * @brief Inserts a delay time.
- * @param nTime: specifies the delay time length, in 10 ms.
- * @retval None
- */
-void Delay(__IO uint32_t nTime)
-{
- TimingDelay = nTime;
-
- while(TimingDelay != 0);
-}
-
-/**
- * @brief Decrements the TimingDelay variable.
- * @param None
- * @retval None
- */
-void TimingDelay_Decrement(void)
-{
- if (TimingDelay != 0x00)
- {
- TimingDelay--;
- }
-}
-
-/**
- * @brief This function handles the test program fail.
- * @param None
- * @retval None
- */
-void Fail_Handler(void)
-{
- /* Erase last sector */
- FLASH_EraseSector(FLASH_Sector_11, VoltageRange_3);
- /* Write FAIL code at last word in the flash memory */
- FLASH_ProgramWord(TESTRESULT_ADDRESS, ALLTEST_FAIL);
-
- while(1)
- {
- /* Toggle Red LED */
- STM_EVAL_LEDToggle(LED5);
- Delay(5);
- }
-}
-
-/**
- * @brief MEMS accelerometre management of the timeout situation.
- * @param None.
- * @retval None.
- */
-uint32_t LIS302DL_TIMEOUT_UserCallback(void)
-{
- /* MEMS Accelerometer Timeout error occured during Test program execution */
- if (DemoEnterCondition == 0x00)
- {
- /* Timeout error occured for SPI TXE/RXNE flags waiting loops.*/
- Fail_Handler();
- }
- /* MEMS Accelerometer Timeout error occured during Demo execution */
- else
- {
- while (1)
- {
- }
- }
- return 0;
-}
-
-#ifdef USE_FULL_ASSERT
-
-/**
- * @brief Reports the name of the source file and the source line number
- * where the assert_param error has occurred.
- * @param file: pointer to the source file name
- * @param line: assert_param error line source number
- * @retval None
- */
-void assert_failed(uint8_t* file, uint32_t line)
-{
- /* User can add his own implementation to report the file name and line number,
- ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
- /* Infinite loop */
- while (1)
- {
- }
-}
-#endif
-
-/**
- * @}
- */
-
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file main.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief Header for main.c module
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4_DISCOVERY_DEMO_H
-#define __STM32F4_DISCOVERY_DEMO_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4_discovery.h"
-#include "stm32f4_discovery_audio_codec.h"
-#include "stm32f4_discovery_lis302dl.h"
-#include "selftest.h"
-#include <stdio.h>
-
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* TIM2 Autoreload and Capture Compare register values */
-#define TIM_ARR (uint16_t)1999
-#define TIM_CCR (uint16_t)1000
-
-/* MEMS Microphone SPI Interface */
-#define SPI_SCK_PIN GPIO_Pin_10
-#define SPI_SCK_GPIO_PORT GPIOB
-#define SPI_SCK_GPIO_CLK RCC_AHB1Periph_GPIOB
-#define SPI_SCK_SOURCE GPIO_PinSource10
-#define SPI_SCK_AF GPIO_AF_SPI2
-
-#define SPI_MOSI_PIN GPIO_Pin_3
-#define SPI_MOSI_GPIO_PORT GPIOC
-#define SPI_MOSI_GPIO_CLK RCC_AHB1Periph_GPIOC
-#define SPI_MOSI_SOURCE GPIO_PinSource3
-#define SPI_MOSI_AF GPIO_AF_SPI2
-
-/* Exported macro ------------------------------------------------------------*/
-#define ABS(x) (x < 0) ? (-x) : x
-#define MAX(a,b) (a < b) ? (b) : a
-/* Exported functions ------------------------------------------------------- */
-void TimingDelay_Decrement(void);
-void Delay(__IO uint32_t nTime);
-void Fail_Handler(void);
-#endif /* __STM32F4_DISCOVERY_DEMO_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file selftest.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief This file provides the hardware tests
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "selftest.h"
-
-//Library config for this project!!!!!!!!!!!
-#include "stm32f4xx_conf.h"
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define MEMS_PASSCONDITION 15
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Init Structure definition */
-RCC_ClocksTypeDef RCC_Clocks;
-ADC_InitTypeDef ADC_InitStructure;
-ADC_CommonInitTypeDef ADC_CommonInitStructure;
-
-__IO uint16_t ConvData1, ConvData2;
-__IO uint16_t counter0 = 0, counter1 = 0, Idx = 0;
-uint8_t ADC_Channel[2] = {ADC_Channel_2, ADC_Channel_3};
-uint8_t DACTest = 0;
-uint8_t GPIO_Pin [2] = {GPIO_Pin_2, GPIO_Pin_3};
-
-uint16_t count = 0, count1 = 24, Left_Right = 0;
-const int16_t sinebuf[48] = {0, 4276, 8480, 12539, 16383, 19947, 23169, 25995,
- 28377, 30272, 31650, 32486, 32767, 32486, 31650, 30272,
- 28377, 25995, 23169, 19947, 16383, 12539, 8480, 4276,
- 0, -4276, -8480, -12539, -16383, -19947, -23169, -25995,
- -28377, -30272, -31650, -32486, -32767, -32486, -31650, -30272,
- -28377, -25995, -23169, -19947, -16383, -12539, -8480, -4276
- };
-extern __IO uint32_t TimingDelay;
-
-extern LIS302DL_InitTypeDef LIS302DL_InitStruct;
-extern LIS302DL_FilterConfigTypeDef LIS302DL_FilterStruct;
-
-extern __IO int8_t X_Offset, Y_Offset, Z_Offset;
-extern uint8_t Buffer[6];
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/**
- * @brief Test MEMS Hardware.
- * The main objectif of this test is to check the hardware connection of the
- * MEMS peripheral.
- * @param None
- * @retval None
- */
-void Accelerometer_MEMS_Test(void)
-{
- uint8_t temp, memsteststatus = 0x00;
- uint8_t xdata, ydata = 0;
-
- /* MEMS configuration ------------------------------------------------------*/
- /* Set configuration of LIS302DL*/
- LIS302DL_InitStruct.Power_Mode = LIS302DL_LOWPOWERMODE_ACTIVE;
- LIS302DL_InitStruct.Output_DataRate = LIS302DL_DATARATE_100;
- LIS302DL_InitStruct.Axes_Enable = LIS302DL_X_ENABLE | LIS302DL_Y_ENABLE;
- LIS302DL_InitStruct.Full_Scale = LIS302DL_FULLSCALE_2_3;
- LIS302DL_InitStruct.Self_Test = LIS302DL_SELFTEST_NORMAL;
- LIS302DL_Init(&LIS302DL_InitStruct);
-
- /* Set configuration of Internal High Pass Filter of LIS302DL*/
- LIS302DL_FilterStruct.HighPassFilter_Data_Selection = LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER;
- LIS302DL_FilterStruct.HighPassFilter_CutOff_Frequency = LIS302DL_HIGHPASSFILTER_LEVEL_1;
- LIS302DL_FilterStruct.HighPassFilter_Interrupt = LIS302DL_HIGHPASSFILTERINTERRUPT_1_2;
- LIS302DL_FilterConfig(&LIS302DL_FilterStruct);
-
- /* Required delay for the MEMS Accelerometre: Turn-on time = 3/Output data Rate
- = 3/100 = 30ms */
- Delay(30);
-
- /* Read WHO_AM_I register */
- LIS302DL_Read(&temp, LIS302DL_WHO_AM_I_ADDR, 1);
-
- /* Check device identification register, this register should contains
- the device identifier that for LIS302DL is set to 0x3B */
- if (temp != 0x3B)
- {
- Fail_Handler();
- }
-
- TimingDelay = 500;
- /* Wait until detecting all MEMS direction or timeout */
- while((memsteststatus == 0x00)&&(TimingDelay != 0x00))
- {
- LIS302DL_Read(Buffer, LIS302DL_OUT_X_ADDR, 4);
- xdata = ABS((int8_t)(Buffer[0]));
- ydata = ABS((int8_t)(Buffer[2]));
- /* Check test PASS condition */
- if ((xdata > MEMS_PASSCONDITION) || (ydata > MEMS_PASSCONDITION))
- {
- /* MEMS Test PASS */
- memsteststatus = 0x01;
- }
- }
-
- /* MEMS test status: PASS */
- if(memsteststatus != 0x00)
- {
- /* Turn Green LED ON: signaling MEMS Test PASS */
- STM_EVAL_LEDOn(LED4);
-
- /* Waiting User Button is pressed */
- while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_RESET)
- {}
-
- /* Waiting User Button is Released */
- while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET)
- {}
-
- /* Turn Green LED OFF: signaling the end of MEMS Test and switching to
- the next Sub Test */
- STM_EVAL_LEDOff(LED4);
- }
- /* MEMS test status: Timeout occurs */
- else
- {
- Fail_Handler();
- }
-}
-
-/**
- * @brief Test USB Hardware.
- * The main objectif of this test is to check the hardware connection of the
- * Audio and USB peripheral.
- * @param None
- * @retval None
- */
-void USB_Test(void)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
-
- /******************************** USB Test **********************************/
-
- /*----------------- Part1: without cables connected ------------------------*/
-
- /* GPIOA, GPIOC and GPIOD clock enable */
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | \
- RCC_AHB1Periph_GPIOD, ENABLE);
-
- /* GPIOD Configuration: Pins 5 in output push-pull */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOD, &GPIO_InitStructure);
-
- /* Turn LED8 ON using PD5 */
- GPIO_ResetBits(GPIOD, GPIO_Pin_5);
-
- /* GPIOC Configuration: Pin 0 in output push-pull */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOC, &GPIO_InitStructure);
-
- /* GPIOA Configuration: Pin 9 in input pull-up */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- /* Turn LED7 ON using PC0 (5v) */
- GPIO_ResetBits(GPIOC, GPIO_Pin_0);
-
- /* Waiting delay 10ms */
- Delay(1);
-
- if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_9) == Bit_RESET)
- {
- Fail_Handler();
- }
-
- /* GPIOA Configuration: Pins 10 in output push-pull */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- /* Waiting delay 10ms */
- Delay(1);
-
- /* Check the ID level without cable connected */
- if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_10) == Bit_RESET)
- {
- Fail_Handler();
- }
-
- /* Turn LED7 OFF using PC0 */
- GPIO_SetBits(GPIOC, GPIO_Pin_0);
-
- /* GPIOA Configuration: Pins 11, 12 in input pull-up */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- /* GPIOA Configuration: Pin 9 in output push-pull */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
- GPIO_ResetBits(GPIOA, GPIO_Pin_9);
-
- /* Waiting delay 10ms */
- Delay(1);
-
- /* Check PA11 and PA12 level without cable connected */
- if ((GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_11) == Bit_RESET) || \
- (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_12) == Bit_RESET))
- {
- Fail_Handler();
- }
-
- /* GPIOA Configuration: Pins 12 in input pull-up */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- /* GPIOA Configuration: Pin 11 in output push-pull */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
- GPIO_ResetBits(GPIOA, GPIO_Pin_11);
-
- /* Waiting delay 10ms */
- Delay(1);
-
- /* Check PA12 level without cable connected */
- if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_12) == Bit_RESET)
- {
- Fail_Handler();
- }
-
- /* GPIOA Configuration: Pins 11 in input pull-up */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- /* GPIOA Configuration: Pin 12 in output push-pull */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
- GPIO_ResetBits(GPIOA, GPIO_Pin_12);
-
- /* Waiting delay 10ms */
- Delay(1);
-
- /* Check PA12 level without cable connected */
- if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_11) == Bit_RESET)
- {
- Fail_Handler();
- }
-
- /* GPIOA Configuration: Pins 9 in output push-pull */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- /* Turn LED7 ON using PA9 */
- GPIO_SetBits(GPIOA, GPIO_Pin_9);
-
- /* Turn Green LED ON: signaling Audio USB Test part1 PASS */
- STM_EVAL_LEDOn(LED4);
-
- /* Waiting User Button is pressed */
- while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_RESET)
- {}
-
- /* Waiting User Button is Released */
- while (STM_EVAL_PBGetState(BUTTON_USER) != Bit_RESET)
- {}
-
- /* Turn Green LED OFF: signaling the end of Audio USB Test part1 and switching to
- the part2 */
- STM_EVAL_LEDOff(LED4);
-
- /* Turn LED7 OFF using PA9 */
- GPIO_ResetBits(GPIOA, GPIO_Pin_9);
-
- /* Turn LED8 OFF using PD5 */
- GPIO_SetBits(GPIOD, GPIO_Pin_5);
-
- /*--------------- Part2: with Audio USB cables connected ------------------*/
-
- /*********************************** USB Test *******************************/
- /* Check the ID level with cable connected */
- if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_10) != Bit_RESET)
- {
- Fail_Handler();
- }
-
- /* GPIOA Configuration: Pins 11, 12 in input pull-down */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- /* GPIOA Configuration: Pin 9 in output push-pull */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
- GPIO_SetBits(GPIOA, GPIO_Pin_9);
-
- /* Waiting delay 10ms */
- Delay(1);
-
- /* Check PA11 and PA12 level with cable connected */
- if ((GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_11) == Bit_RESET) || \
- (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_12) == Bit_RESET))
- {
- Fail_Handler();
- }
-
- /* GPIOA Configuration: Pins 9, 12 in input pull-down */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_12;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- /* GPIOA Configuration: Pin 11 in output push-pull */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
- GPIO_SetBits(GPIOA, GPIO_Pin_11);
-
- /* Waiting delay 10ms */
- Delay(1);
-
- /* Check PA9 and PA12 level with cable connected */
- if ((GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_9) == Bit_RESET)|| \
- (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_12) == Bit_RESET))
- {
- Fail_Handler();
- }
-
- /* GPIOA Configuration: Pins 9, 11 in input pull-down */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_11;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- /* GPIOA Configuration: Pin 12 in output push-pull */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
- GPIO_SetBits(GPIOA, GPIO_Pin_12);
-
- /* Waiting delay 10ms */
- Delay(1);
-
- /* Check PA9 and PA12 level with cable connected */
- if ((GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_9) == Bit_RESET)|| \
- (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_11) == Bit_RESET))
- {
- Fail_Handler();
- }
-
- /* GPIOA Configuration: Pins 11, 12 in input pull-down */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- /* GPIOA Configuration: Pin 9 in output push-pull */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- /* Turn LED7 OFF using PA9 */
- GPIO_ResetBits(GPIOA, GPIO_Pin_9);
-}
-
-/**
- * @brief Test Audio Hardware.
- * The main objectif of this test is to check the hardware connection of the
- * Audio peripheral.
- * @param None
- * @retval None
- */
-void Audio_Test(void)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
- uint8_t audioteststatus = 0x00;
-
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC2, ENABLE);
-
- /* Set the current audio interface: I2S or DAC */
- EVAL_AUDIO_SetAudioInterface(AUDIO_INTERFACE_I2S);
-
- /* Initialize the Audio codec and all related peripherals (I2S, I2C, IOs...) */
- if (EVAL_AUDIO_Init(OUTPUT_DEVICE_HEADPHONE, 87, I2S_AudioFreq_48k) !=0)
- {
- Fail_Handler();
- }
- /* I2S code to be exectued under the I2S interrupt */
- DACTest = 0;
-
- /* ADC Common Init */
- ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent;
- ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div8;
- ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
- ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_20Cycles;
- ADC_CommonInit(&ADC_CommonInitStructure);
-
- /* ADC peripherals Init */
- ADC_StructInit(&ADC_InitStructure);
- ADC_InitStructure.ADC_Resolution = ADC_Resolution_8b;
- ADC_InitStructure.ADC_ScanConvMode = DISABLE;
- ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
- ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
- ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
- ADC_InitStructure.ADC_NbrOfConversion = 1;
- ADC_Init(ADC1, &ADC_InitStructure);
-
- ADC_Init(ADC2, &ADC_InitStructure);
-
- /* Configure ADC Channels pin as analog input */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 ;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- counter1 = 0;
- counter0 = 0;
- audioteststatus = 0;
- /* ADCperipheral[PerIdx] Regular Channel Config */
- ADC_RegularChannelConfig(ADC1, ADC_Channel_2, 1, ADC_SampleTime_56Cycles);
- /* ADCperipheral[PerIdx] Regular Channel Config */
- ADC_RegularChannelConfig(ADC2, ADC_Channel_3, 1, ADC_SampleTime_56Cycles);
- /* Enable ADC1 */
- ADC_Cmd(ADC1, ENABLE);
- ADC_Cmd(ADC2, ENABLE);
-
- TimingDelay = 500;
- /* Wait until detecting 500 data*/
- while((audioteststatus == 0)&&(TimingDelay != 0))
- {
- ADC_SoftwareStartConv(ADC1);
- while(ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC) == RESET);
- ConvData1 = ADC_GetConversionValue(ADC1);
-
- ADC_SoftwareStartConv(ADC2);
- while(ADC_GetFlagStatus(ADC2, ADC_FLAG_EOC) == RESET);
- ConvData2 = ADC_GetConversionValue(ADC2);
-
- /* 1.75V equals to 150 */
- if ((ConvData1 > 150) && (ConvData2 < 10) && (counter1 != 500))
- {
- counter1 ++;
- }
- if ((ConvData1 < 10) && (ConvData2 > 150) && (counter0 != 500))
- {
- counter0 ++;
- }
- if((counter1 == 500) && (counter0 == 500))
- {
- audioteststatus = 1;
- }
- }
-
- /* Disable ADC Peripherals */
- ADC_Cmd(ADC1, DISABLE);
- ADC_Cmd(ADC2, DISABLE);
-
- /* Audio test status: FAIL */
- if(audioteststatus == 0)
- {
- Fail_Handler();
- }
-
- EVAL_AUDIO_DeInit();
- EVAL_AUDIO_SetAudioInterface(AUDIO_INTERFACE_DAC);
- /* Initialize the Audio codec and all related peripherals (I2S, I2C, IOs...) */
- if (EVAL_AUDIO_Init(OUTPUT_DEVICE_HEADPHONE, 100, I2S_AudioFreq_48k) !=0)
- {
- Fail_Handler();
- }
-
- /* DAC code to be exectued under the I2S interrupt */
- DACTest = 1;
- counter1 = 0;
- counter0 = 0;
- audioteststatus = 0;
-
- /* Enable ADC1 */
- ADC_Cmd(ADC1, ENABLE);
- ADC_Cmd(ADC2, ENABLE);
-
- TimingDelay = 500;
- /* Wait until detecting 50 data*/
- while((audioteststatus == 0)&&(TimingDelay != 0))
- {
-
- ADC_SoftwareStartConv(ADC1);
- while(ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC) == RESET);
-
- ConvData1 = ADC_GetConversionValue(ADC1);
-
- ADC_SoftwareStartConv(ADC2);
- while(ADC_GetFlagStatus(ADC2, ADC_FLAG_EOC) == RESET);
-
- ConvData2 = ADC_GetConversionValue(ADC2);
-
- /* 2.0V equals to 170 */
- if ((ConvData1 > 170) && (ConvData2 > 170) &&(counter1 != 500))
- {
- counter1 ++;
- }
- if ((ConvData1 < 10) && (ConvData2 < 10) && (counter0 != 500))
- {
- counter0 ++;
- }
- if((counter1 == 500) && (counter0 == 500))
- {
- audioteststatus = 1;
- }
- }
-
- /* Audio test status: FAIL */
- if(audioteststatus == 0x00)
- {
- Fail_Handler();
- }
-
- /* Turn Green LED ON: signaling Audio USB Test part2 PASS */
- STM_EVAL_LEDOn(LED4);
-
- /* Waiting User_Button pressed */
- while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_RESET)
- {}
-
- /* Turn Green LED OFF: signaling the end of Audio USB Test part2 */
- STM_EVAL_LEDOff(LED4);
-}
-
-/**
- * @brief Test Micophone MEMS Hardware.
- * The main objectif of this test is to check the hardware connection of the
- * Microphone MEMS peripheral.
- * @param None
- * @retval None
- */
-void Microphone_MEMS_Test(void)
-{
- uint16_t data = 0x00;
- uint8_t index = 0x00;
- I2S_InitTypeDef I2S_InitStructure;
- GPIO_InitTypeDef GPIO_InitStructure;
-
- /* Enable the SPI clock */
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
-
- /* Enable GPIO clocks */
- RCC_AHB1PeriphClockCmd(SPI_SCK_GPIO_CLK | SPI_MOSI_GPIO_CLK, ENABLE);
-
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz;
-
- /* SPI SCK pin configuration */
- GPIO_InitStructure.GPIO_Pin = SPI_SCK_PIN;
- GPIO_Init(SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
- /* Connect SPI pins to AF5 */
- GPIO_PinAFConfig(SPI_SCK_GPIO_PORT, SPI_SCK_SOURCE, SPI_SCK_AF);
-
- /* SPI MOSI pin configuration */
- GPIO_InitStructure.GPIO_Pin = SPI_MOSI_PIN;
- GPIO_Init(SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
- GPIO_PinAFConfig(SPI_MOSI_GPIO_PORT, SPI_MOSI_SOURCE, SPI_MOSI_AF);
-
- /* I2S configuration -------------------------------------------------------*/
- SPI_I2S_DeInit(SPI2);
- I2S_InitStructure.I2S_AudioFreq = 64000;
- I2S_InitStructure.I2S_Standard = I2S_Standard_MSB;
- I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
- I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
- I2S_InitStructure.I2S_Mode = I2S_Mode_MasterRx;
- I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
- /* Initialize the I2S peripheral with the structure above */
- I2S_Init(SPI2, &I2S_InitStructure);
-
- /* Enable the I2S peripheral */
- I2S_Cmd(SPI2, ENABLE);
-
- /* Waiting until MEMS microphone ready : Wake-up Time */
- Delay(10);
-
- TimingDelay = 500;
- /* Wait until detect the click on the MEMS microphone or TimeOut delay*/
- while((index < 30) && (TimingDelay != 0x00))
- {
- /* Waiting RXNE Flag or TimeOut delay */
- while((SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_RXNE) == RESET)&& (TimingDelay != 0x00))
- {}
- data = SPI_I2S_ReceiveData(SPI2);
- if (data == 0xFFFF)
- {
- index++;
- }
- }
-
- /* MEMS microphone test status: Timeout occurs */
- if(index != 30)
- {
- Fail_Handler();
- }
-}
-
-/*--------------------------------
- Callbacks implementation:
- the callbacks prototypes are defined in the stm324xg_eval_audio_codec.h file
- and their implementation should be done in the user code if they are needed.
- Below some examples of callback implementations.
- --------------------------------------------------------*/
-/**
- * @brief Calculates the remaining file size and new position of the pointer.
- * @param None
- * @retval None
- */
-void EVAL_AUDIO_TransferComplete_CallBack(uint32_t pBuffer, uint32_t Size)
-{
- /* Calculate the remaining audio data in the file and the new size
- for the DMA transfer. If the Audio files size is less than the DMA max
- data transfer size, so there is no calculation to be done, just restart
- from the beginning of the file ... */
- /* Check if the end of file has been reached */
-
-}
-
-/**
- * @brief Manages the DMA Half Transfer complete interrupt.
- * @param None
- * @retval None
- */
-void EVAL_AUDIO_HalfTransfer_CallBack(uint32_t pBuffer, uint32_t Size)
-{
-#ifdef AUDIO_MAL_MODE_CIRCULAR
-
- /* Display message on the LCD screen */
- LCD_DisplayStringLine(Line8, " 1/2 Buffer Reached ");
-
-#endif /* AUDIO_MAL_MODE_CIRCULAR */
-
- /* Generally this interrupt routine is used to load the buffer when
- a streaming scheme is used: When first Half buffer is already transferred load
- the new data to the first half of buffer while DMA is transferring data from
- the second half. And when Transfer complete occurs, load the second half of
- the buffer while the DMA is transferring from the first half ... */
- /*
- ...........
- */
-}
-/**
- * @brief Get next data sample callback
- * @param None
- * @retval Next data sample to be sent
- */
-uint16_t EVAL_AUDIO_GetSampleCallBack(void)
-{
- uint16_t data = 0;
-
- if (DACTest == 0)
- {
- if (Left_Right==0)
- {
- /* Get the next sample to be sent */
- data = sinebuf[count++];
-
- if (count == 48)
- {
- count = 0x00;
- }
- Left_Right = 1;
- }
- else
- {
- /* Get the next sample to be sent */
- data = sinebuf[count1++];
-
- if (count1 == 48)
- {
- count1 = 0x00;
- }
- Left_Right = 0;
- }
- }
- else
- {
- /* Get the next sample to be sent */
- data = 32768 + sinebuf[count++];
-
- if (count == 48)
- {
- count = 0x00;
- }
- }
- return data;
-}
-
-
-/**
- * @brief Manages the DMA FIFO error interrupt.
- * @param None
- * @retval None
- */
-void EVAL_AUDIO_Error_CallBack(void* pData)
-{
- /* Stop the program with an infinite loop */
- while (1)
- {}
-
- /* could also generate a system reset to recover from the error */
- /* .... */
-}
-
-#ifndef USE_DEFAULT_TIMEOUT_CALLBACK
-/**
- * @brief Basic management of the timeout situation.
- * @param None.
- * @retval None.
- */
-uint32_t Codec_TIMEOUT_UserCallback(void)
-{
- /* Block communication and all processes */
- while (1)
- {
- }
-}
-#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */
-/*----------------------------------------------------------------------------*/
-
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file selftest.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief Header for selftest.c module
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __SELFTEST_H
-#define __SELFTEST_H
-
-/* Includes ------------------------------------------------------------------*/
-#include <stdio.h>
-#include "main.h"
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void Audio_Test(void);
-void Accelerometer_MEMS_Test(void);
-void USB_Test(void);
-void Microphone_MEMS_Test(void);
-
-#endif /* __SELFTEST_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file startup_stm32f4xx.s
- * @author MCD Application Team
- * @version V1.0.0
- * @date 30-September-2011
- * @brief STM32F4xx Devices vector table for RIDE7 toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the clock system and the external SRAM mounted on
- * STM324xG-EVAL board to be used as data memory (optional,
- * to be enabled by user)
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M4 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m3
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
-
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-/* Call the application's entry point.*/
- bl main
- bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- * @param None
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-*******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
- .word NMI_Handler
- .word HardFault_Handler
- .word MemManage_Handler
- .word BusFault_Handler
- .word UsageFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word DebugMon_Handler
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
- /* External Interrupts */
- .word WWDG_IRQHandler /* Window WatchDog */
- .word PVD_IRQHandler /* PVD through EXTI Line detection */
- .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
- .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
- .word FLASH_IRQHandler /* FLASH */
- .word RCC_IRQHandler /* RCC */
- .word EXTI0_IRQHandler /* EXTI Line0 */
- .word EXTI1_IRQHandler /* EXTI Line1 */
- .word EXTI2_IRQHandler /* EXTI Line2 */
- .word EXTI3_IRQHandler /* EXTI Line3 */
- .word EXTI4_IRQHandler /* EXTI Line4 */
- .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
- .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
- .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
- .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
- .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
- .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
- .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
- .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
- .word CAN1_TX_IRQHandler /* CAN1 TX */
- .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
- .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
- .word CAN1_SCE_IRQHandler /* CAN1 SCE */
- .word EXTI9_5_IRQHandler /* External Line[9:5]s */
- .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
- .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
- .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
- .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .word TIM2_IRQHandler /* TIM2 */
- .word TIM3_IRQHandler /* TIM3 */
- .word TIM4_IRQHandler /* TIM4 */
- .word I2C1_EV_IRQHandler /* I2C1 Event */
- .word I2C1_ER_IRQHandler /* I2C1 Error */
- .word I2C2_EV_IRQHandler /* I2C2 Event */
- .word I2C2_ER_IRQHandler /* I2C2 Error */
- .word SPI1_IRQHandler /* SPI1 */
- .word SPI2_IRQHandler /* SPI2 */
- .word USART1_IRQHandler /* USART1 */
- .word USART2_IRQHandler /* USART2 */
- .word USART3_IRQHandler /* USART3 */
- .word EXTI15_10_IRQHandler /* External Line[15:10]s */
- .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
- .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
- .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
- .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
- .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
- .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
- .word FSMC_IRQHandler /* FSMC */
- .word SDIO_IRQHandler /* SDIO */
- .word TIM5_IRQHandler /* TIM5 */
- .word SPI3_IRQHandler /* SPI3 */
- .word UART4_IRQHandler /* UART4 */
- .word UART5_IRQHandler /* UART5 */
- .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
- .word TIM7_IRQHandler /* TIM7 */
- .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
- .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
- .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
- .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
- .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
- .word ETH_IRQHandler /* Ethernet */
- .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
- .word CAN2_TX_IRQHandler /* CAN2 TX */
- .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
- .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
- .word CAN2_SCE_IRQHandler /* CAN2 SCE */
- .word OTG_FS_IRQHandler /* USB OTG FS */
- .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
- .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
- .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
- .word USART6_IRQHandler /* USART6 */
- .word I2C3_EV_IRQHandler /* I2C3 event */
- .word I2C3_ER_IRQHandler /* I2C3 error */
- .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
- .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
- .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
- .word OTG_HS_IRQHandler /* USB OTG HS */
- .word DCMI_IRQHandler /* DCMI */
- .word CRYP_IRQHandler /* CRYP crypto */
- .word HASH_RNG_IRQHandler /* Hash and Rng */
- .word FPU_IRQHandler /* FPU */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak MemManage_Handler
- .thumb_set MemManage_Handler,Default_Handler
-
- .weak BusFault_Handler
- .thumb_set BusFault_Handler,Default_Handler
-
- .weak UsageFault_Handler
- .thumb_set UsageFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_IRQHandler
- .thumb_set PVD_IRQHandler,Default_Handler
-
- .weak TAMP_STAMP_IRQHandler
- .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
-
- .weak RTC_WKUP_IRQHandler
- .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
- .thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
- .thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_IRQHandler
- .thumb_set EXTI2_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
- .thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
- .thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream0_IRQHandler
- .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
-
- .weak DMA1_Stream1_IRQHandler
- .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
-
- .weak DMA1_Stream2_IRQHandler
- .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
-
- .weak DMA1_Stream3_IRQHandler
- .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
-
- .weak DMA1_Stream4_IRQHandler
- .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream5_IRQHandler
- .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
-
- .weak DMA1_Stream6_IRQHandler
- .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
-
- .weak ADC_IRQHandler
- .thumb_set ADC_IRQHandler,Default_Handler
-
- .weak CAN1_TX_IRQHandler
- .thumb_set CAN1_TX_IRQHandler,Default_Handler
-
- .weak CAN1_RX0_IRQHandler
- .thumb_set CAN1_RX0_IRQHandler,Default_Handler
-
- .weak CAN1_RX1_IRQHandler
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
- .weak CAN1_SCE_IRQHandler
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
- .weak EXTI9_5_IRQHandler
- .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_TIM9_IRQHandler
- .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
-
- .weak TIM1_UP_TIM10_IRQHandler
- .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
-
- .weak TIM1_TRG_COM_TIM11_IRQHandler
- .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM4_IRQHandler
- .thumb_set TIM4_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
- .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
- .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
- .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
- .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak USART3_IRQHandler
- .thumb_set USART3_IRQHandler,Default_Handler
-
- .weak EXTI15_10_IRQHandler
- .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak OTG_FS_WKUP_IRQHandler
- .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
-
- .weak TIM8_BRK_TIM12_IRQHandler
- .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
- .weak TIM8_UP_TIM13_IRQHandler
- .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
- .weak TIM8_TRG_COM_TIM14_IRQHandler
- .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
- .weak TIM8_CC_IRQHandler
- .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
- .weak DMA1_Stream7_IRQHandler
- .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
-
- .weak FSMC_IRQHandler
- .thumb_set FSMC_IRQHandler,Default_Handler
-
- .weak SDIO_IRQHandler
- .thumb_set SDIO_IRQHandler,Default_Handler
-
- .weak TIM5_IRQHandler
- .thumb_set TIM5_IRQHandler,Default_Handler
-
- .weak SPI3_IRQHandler
- .thumb_set SPI3_IRQHandler,Default_Handler
-
- .weak UART4_IRQHandler
- .thumb_set UART4_IRQHandler,Default_Handler
-
- .weak UART5_IRQHandler
- .thumb_set UART5_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM7_IRQHandler
- .thumb_set TIM7_IRQHandler,Default_Handler
-
- .weak DMA2_Stream0_IRQHandler
- .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
-
- .weak DMA2_Stream1_IRQHandler
- .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
-
- .weak DMA2_Stream2_IRQHandler
- .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
-
- .weak DMA2_Stream3_IRQHandler
- .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
-
- .weak DMA2_Stream4_IRQHandler
- .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
-
- .weak ETH_IRQHandler
- .thumb_set ETH_IRQHandler,Default_Handler
-
- .weak ETH_WKUP_IRQHandler
- .thumb_set ETH_WKUP_IRQHandler,Default_Handler
-
- .weak CAN2_TX_IRQHandler
- .thumb_set CAN2_TX_IRQHandler,Default_Handler
-
- .weak CAN2_RX0_IRQHandler
- .thumb_set CAN2_RX0_IRQHandler,Default_Handler
-
- .weak CAN2_RX1_IRQHandler
- .thumb_set CAN2_RX1_IRQHandler,Default_Handler
-
- .weak CAN2_SCE_IRQHandler
- .thumb_set CAN2_SCE_IRQHandler,Default_Handler
-
- .weak OTG_FS_IRQHandler
- .thumb_set OTG_FS_IRQHandler,Default_Handler
-
- .weak DMA2_Stream5_IRQHandler
- .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
-
- .weak DMA2_Stream6_IRQHandler
- .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
-
- .weak DMA2_Stream7_IRQHandler
- .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
-
- .weak USART6_IRQHandler
- .thumb_set USART6_IRQHandler,Default_Handler
-
- .weak I2C3_EV_IRQHandler
- .thumb_set I2C3_EV_IRQHandler,Default_Handler
-
- .weak I2C3_ER_IRQHandler
- .thumb_set I2C3_ER_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_OUT_IRQHandler
- .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_IN_IRQHandler
- .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
-
- .weak OTG_HS_WKUP_IRQHandler
- .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
-
- .weak OTG_HS_IRQHandler
- .thumb_set OTG_HS_IRQHandler,Default_Handler
-
- .weak DCMI_IRQHandler
- .thumb_set DCMI_IRQHandler,Default_Handler
-
- .weak CRYP_IRQHandler
- .thumb_set CRYP_IRQHandler,Default_Handler
-
- .weak HASH_RNG_IRQHandler
- .thumb_set HASH_RNG_IRQHandler,Default_Handler
-
- .weak FPU_IRQHandler
- .thumb_set FPU_IRQHandler,Default_Handler
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/*
-*****************************************************************************
-**
-** File : stm32_flash.ld
-**
-** Abstract : Linker script for STM32F207IG Device with
-** 1024KByte FLASH, 112KByte RAM
-**
-** Set heap size, stack size and stack location according
-** to application requirements.
-**
-** Set memory bank area and size if external memory is used.
-**
-** Target : STMicroelectronics STM32
-**
-** Environment : Atollic TrueSTUDIO(R)
-**
-** Distribution: The file is distributed \93as is,\94 without any warranty
-** of any kind.
-**
-** (c)Copyright Atollic AB.
-** You may use this file as-is or modify it according to the needs of your
-** project. Distribution of this file (unmodified or modified) is not
-** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
-** rights to distribute the assembled, compiled & linked contents of this
-** file as part of an application binary file, provided that it is built
-** using the Atollic TrueSTUDIO(R) toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x2001c000; /* end of 112K RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0; /* required amount of heap */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
- RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 112K
- MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
-}
-
-/* Define output sections */
-SECTIONS
-{
- /* The startup code goes first into FLASH */
- .isr_vector :
- {
- . = ALIGN(4);
- KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
- } >FLASH
-
- /* The program code and other data goes into FLASH */
- .text :
- {
- . = ALIGN(4);
- *(.text) /* .text sections (code) */
- *(.text*) /* .text* sections (code) */
- *(.rodata) /* .rodata sections (constants, strings, etc.) */
- *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
- *(.glue_7) /* glue arm to thumb code */
- *(.glue_7t) /* glue thumb to arm code */
- *(.eh_frame)
-
- KEEP (*(.init))
- KEEP (*(.fini))
-
- . = ALIGN(4);
- _etext = .; /* define a global symbols at end of code */
- } >FLASH
-
-
- .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
- .ARM : {
- __exidx_start = .;
- *(.ARM.exidx*)
- __exidx_end = .;
- } >FLASH
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array*))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >FLASH
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array*))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >FLASH
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(.fini_array*))
- KEEP (*(SORT(.fini_array.*)))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } >FLASH
-
- /* used by the startup to initialize data */
- _sidata = .;
-
- /* Initialized data sections goes into RAM, load LMA copy after code */
- .data : AT ( _sidata )
- {
- . = ALIGN(4);
- _sdata = .; /* create a global symbol at data start */
- *(.data) /* .data sections */
- *(.data*) /* .data* sections */
-
- . = ALIGN(4);
- _edata = .; /* define a global symbol at data end */
- } >RAM
-
- /* Uninitialized data section */
- . = ALIGN(4);
- .bss :
- {
- /* This is used by the startup in order to initialize the .bss secion */
- _sbss = .; /* define a global symbol at bss start */
- __bss_start__ = _sbss;
- *(.bss)
- *(.bss*)
- *(COMMON)
-
- . = ALIGN(4);
- _ebss = .; /* define a global symbol at bss end */
- __bss_end__ = _ebss;
- } >RAM
-
- /* User_heap_stack section, used to check that there is enough RAM left */
- ._user_heap_stack :
- {
- . = ALIGN(4);
- PROVIDE ( end = . );
- PROVIDE ( _end = . );
- . = . + _Min_Heap_Size;
- . = . + _Min_Stack_Size;
- . = ALIGN(4);
- } >RAM
-
- /* MEMORY_bank1 section, code must be located here explicitly */
- /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
- .memory_b1_text :
- {
- *(.mb1text) /* .mb1text sections (code) */
- *(.mb1text*) /* .mb1text* sections (code) */
- *(.mb1rodata) /* read-only data (constants) */
- *(.mb1rodata*)
- } >MEMORY_B1
-
- /* Remove information from the standard libraries */
- /DISCARD/ :
- {
- libc.a ( * )
- libm.a ( * )
- libgcc.a ( * )
- }
-
- .ARM.attributes 0 : { *(.ARM.attributes) }
-}
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_conf.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief Library configuration file.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_CONF_H
-#define __STM32F4xx_CONF_H
-
-#if defined (HSE_VALUE)
-/* Redefine the HSE value; it's equal to 8 MHz on the STM32F4-DISCOVERY Kit */
- #undef HSE_VALUE
- #define HSE_VALUE ((uint32_t)8000000)
-#endif /* HSE_VALUE */
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment the line below to enable peripheral header file inclusion */
-#include "stm32f4xx_adc.h"
-#include "stm32f4xx_can.h"
-#include "stm32f4xx_crc.h"
-#include "stm32f4xx_cryp.h"
-#include "stm32f4xx_dac.h"
-#include "stm32f4xx_dbgmcu.h"
-#include "stm32f4xx_dcmi.h"
-#include "stm32f4xx_dma.h"
-#include "stm32f4xx_exti.h"
-#include "stm32f4xx_flash.h"
-#include "stm32f4xx_fsmc.h"
-#include "stm32f4xx_hash.h"
-#include "stm32f4xx_gpio.h"
-#include "stm32f4xx_i2c.h"
-#include "stm32f4xx_iwdg.h"
-#include "stm32f4xx_pwr.h"
-#include "stm32f4xx_rcc.h"
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_rtc.h"
-#include "stm32f4xx_sdio.h"
-#include "stm32f4xx_spi.h"
-#include "stm32f4xx_syscfg.h"
-#include "stm32f4xx_tim.h"
-#include "stm32f4xx_usart.h"
-#include "stm32f4xx_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* If an external clock source is used, then the value of the following define
- should be set to the value of the external clock source, else, if no external
- clock is used, keep this define commented */
-/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */
-
-
-/* Uncomment the line below to expanse the "assert_param" macro in the
- Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT 1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr: If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F4xx_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_it.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief Main Interrupt Service Routines.
- * This file provides all exceptions handler and peripherals interrupt
- * service routine.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_it.h"
-#include "main.h"
-#include "usb_core.h"
-#include "usbd_core.h"
-#include "stm32f4_discovery.h"
-#include "usbd_hid_core.h"
-
-//Library config for this project!!!!!!!!!!!
-#include "stm32f4xx_conf.h"
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define CURSOR_STEP 7
-
-extern uint8_t Buffer[6];
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-extern __IO uint8_t DemoEnterCondition;
-uint8_t Counter = 0x00;
-extern int8_t X_Offset;
-extern int8_t Y_Offset;
-extern __IO uint8_t UserButtonPressed;
-__IO uint8_t TempAcceleration = 0;
-/* Private function prototypes -----------------------------------------------*/
-extern USB_OTG_CORE_HANDLE USB_OTG_dev;
-static uint8_t *USBD_HID_GetPos (void);
-extern uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev);
-
-/******************************************************************************/
-/* Cortex-M3 Processor Exceptions Handlers */
-/******************************************************************************/
-
-/**
- * @brief This function handles NMI exception.
- * @param None
- * @retval None
- */
-void NMI_Handler(void)
-{
-}
-
-/**
- * @brief This function handles Hard Fault exception.
- * @param None
- * @retval None
- */
-void HardFault_Handler(void)
-{
- /* Go to infinite loop when Hard Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles Memory Manage exception.
- * @param None
- * @retval None
- */
-void MemManage_Handler(void)
-{
- /* Go to infinite loop when Memory Manage exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles Bus Fault exception.
- * @param None
- * @retval None
- */
-void BusFault_Handler(void)
-{
- /* Go to infinite loop when Bus Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles Usage Fault exception.
- * @param None
- * @retval None
- */
-void UsageFault_Handler(void)
-{
- /* Go to infinite loop when Usage Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles SVCall exception.
- * @param None
- * @retval None
- */
-void SVC_Handler(void)
-{
-}
-
-/**
- * @brief This function handles Debug Monitor exception.
- * @param None
- * @retval None
- */
-void DebugMon_Handler(void)
-{
-}
-
-/**
- * @brief This function handles PendSVC exception.
- * @param None
- * @retval None
- */
-void PendSV_Handler(void)
-{
-}
-
-/**
- * @brief This function handles SysTick Handler.
- * @param None
- * @retval None
- */
-void SysTick_Handler(void)
-{
- uint8_t *buf;
- uint8_t temp1, temp2 = 0x00;
-
- if (DemoEnterCondition == 0x00)
- {
- TimingDelay_Decrement();
- }
- else
- {
- buf = USBD_HID_GetPos();
- if((buf[1] != 0) ||(buf[2] != 0))
- {
- USBD_HID_SendReport (&USB_OTG_dev,
- buf,
- 4);
- }
- Counter ++;
- if (Counter == 10)
- {
- Buffer[0] = 0;
- Buffer[2] = 0;
- /* Disable All TIM4 Capture Compare Channels */
- TIM_CCxCmd(TIM4, TIM_Channel_1, DISABLE);
- TIM_CCxCmd(TIM4, TIM_Channel_2, DISABLE);
- TIM_CCxCmd(TIM4, TIM_Channel_3, DISABLE);
- TIM_CCxCmd(TIM4, TIM_Channel_4, DISABLE);
-
- LIS302DL_Read(Buffer, LIS302DL_OUT_X_ADDR, 6);
- /* Remove the offsets values from data */
- Buffer[0] -= X_Offset;
- Buffer[2] -= Y_Offset;
- /* Update autoreload and capture compare registers value*/
- temp1 = ABS((int8_t)(Buffer[0]));
- temp2 = ABS((int8_t)(Buffer[2]));
- TempAcceleration = MAX(temp1, temp2);
-
- if(TempAcceleration != 0)
- {
- if ((int8_t)Buffer[0] < -2)
- {
- /* Enable TIM4 Capture Compare Channel 4 */
- TIM_CCxCmd(TIM4, TIM_Channel_4, ENABLE);
- /* Sets the TIM4 Capture Compare4 Register value */
- TIM_SetCompare4(TIM4, TIM_CCR/TempAcceleration);
- }
- if ((int8_t)Buffer[0] > 2)
- {
- /* Enable TIM4 Capture Compare Channel 2 */
- TIM_CCxCmd(TIM4, TIM_Channel_2, ENABLE);
- /* Sets the TIM4 Capture Compare2 Register value */
- TIM_SetCompare2(TIM4, TIM_CCR/TempAcceleration);
- }
- if ((int8_t)Buffer[2] > 2)
- {
- /* Enable TIM4 Capture Compare Channel 1 */
- TIM_CCxCmd(TIM4, TIM_Channel_1, ENABLE);
- /* Sets the TIM4 Capture Compare1 Register value */
- TIM_SetCompare1(TIM4, TIM_CCR/TempAcceleration);
- }
- if ((int8_t)Buffer[2] < -2)
- {
- /* Enable TIM4 Capture Compare Channel 3 */
- TIM_CCxCmd(TIM4, TIM_Channel_3, ENABLE);
- /* Sets the TIM4 Capture Compare3 Register value */
- TIM_SetCompare3(TIM4, TIM_CCR/TempAcceleration);
- }
- /* Time base configuration */
- TIM_SetAutoreload(TIM4, TIM_ARR/TempAcceleration);
- }
- Counter = 0x00;
- }
- }
-
-}
-
-/******************************************************************************/
-/* STM32Fxxx Peripherals Interrupt Handlers */
-/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
-/* available peripheral interrupt handler's name please refer to the startup */
-/* file (startup_stm32fxxx.s). */
-/******************************************************************************/
-
-/**
- * @brief This function handles PPP interrupt request.
- * @param None
- * @retval None
- */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
- * @brief This function handles EXTI0_IRQ Handler.
- * @param None
- * @retval None
- */
-void EXTI0_IRQHandler(void)
-{
- UserButtonPressed = 0x01;
-
- /* Clear the EXTI line pending bit */
- EXTI_ClearITPendingBit(USER_BUTTON_EXTI_LINE);
-}
-
-/**
- * @brief This function handles EXTI15_10_IRQ Handler.
- * @param None
- * @retval None
- */
-void OTG_FS_WKUP_IRQHandler(void)
-{
- if(USB_OTG_dev.cfg.low_power)
- {
- /* Reset SLEEPDEEP and SLEEPONEXIT bits */
- SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
-
- /* After wake-up from sleep mode, reconfigure the system clock */
- SystemInit();
- USB_OTG_UngateClock(&USB_OTG_dev);
- }
- EXTI_ClearITPendingBit(EXTI_Line18);
-}
-
-/**
- * @brief This function handles OTG_HS Handler.
- * @param None
- * @retval None
- */
-void OTG_FS_IRQHandler(void)
-{
- USBD_OTG_ISR_Handler (&USB_OTG_dev);
-}
-
-/**
-* @brief USBD_HID_GetPos
-* @param None
-* @retval Pointer to report
-*/
-static uint8_t *USBD_HID_GetPos (void)
-{
- static uint8_t HID_Buffer[4] = {0};
-
- HID_Buffer[1] = 0;
- HID_Buffer[2] = 0;
- /* LEFT Direction */
- if(((int8_t)Buffer[2]) < -2)
- {
- HID_Buffer[1] += CURSOR_STEP;
- }
- /* RIGHT Direction */
- if(((int8_t)Buffer[2]) > 2)
- {
- HID_Buffer[1] -= CURSOR_STEP;
- }
- /* UP Direction */
- if(((int8_t)Buffer[0]) < -2)
- {
- HID_Buffer[2] += CURSOR_STEP;
- }
- /* DOWN Direction */
- if(((int8_t)Buffer[0]) > 2)
- {
- HID_Buffer[2] -= CURSOR_STEP;
- }
-
- return HID_Buffer;
-}
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_it.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief This file contains the headers of the interrupt handlers.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_IT_H
-#define __STM32F4xx_IT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_conf.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file system_stm32f4xx.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
- * This file contains the system clock configuration for STM32F4xx devices,
- * and is generated by the clock configuration tool
- * stm32f4xx_Clock_Configuration_V1.0.0.xls
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
- * and Divider factors, AHB/APBx prescalers and Flash settings),
- * depending on the configuration made in the clock xls tool.
- * This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f4xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (16 MHz) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. If the system clock source selected by user fails to startup, the SystemInit()
- * function will do nothing and HSI still used as system clock source. User can
- * add some code to deal with this issue inside the SetSysClock() function.
- *
- * 4. The default value of HSE crystal is set to 8 MHz, refer to "HSE_VALUE" define
- * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
- * through PLL, and you are using different crystal you have to adapt the HSE
- * value to your own configuration.
- *
- * 5. This file configures the system clock as follows:
- *=============================================================================
- *=============================================================================
- * Supported STM32F4xx device revision | Rev A
- *-----------------------------------------------------------------------------
- * System Clock source | PLL (HSE)
- *-----------------------------------------------------------------------------
- * SYSCLK(Hz) | 168000000
- *-----------------------------------------------------------------------------
- * HCLK(Hz) | 168000000
- *-----------------------------------------------------------------------------
- * AHB Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB1 Prescaler | 4
- *-----------------------------------------------------------------------------
- * APB2 Prescaler | 2
- *-----------------------------------------------------------------------------
- * HSE Frequency(Hz) | 8000000
- *-----------------------------------------------------------------------------
- * PLL_M | 8
- *-----------------------------------------------------------------------------
- * PLL_N | 336
- *-----------------------------------------------------------------------------
- * PLL_P | 2
- *-----------------------------------------------------------------------------
- * PLL_Q | 7
- *-----------------------------------------------------------------------------
- * PLLI2S_N | 192
- *-----------------------------------------------------------------------------
- * PLLI2S_R | 5
- *-----------------------------------------------------------------------------
- * I2S input clock(Hz) | 38400000
- *-----------------------------------------------------------------------------
- * VDD(V) | 3.3
- *-----------------------------------------------------------------------------
- * High Performance mode | Enabled
- *-----------------------------------------------------------------------------
- * Flash Latency(WS) | 5
- *-----------------------------------------------------------------------------
- * Prefetch Buffer | OFF
- *-----------------------------------------------------------------------------
- * Instruction cache | ON
- *-----------------------------------------------------------------------------
- * Data cache | ON
- *-----------------------------------------------------------------------------
- * Require 48MHz for USB OTG FS, | Enabled
- * SDIO and RNG clock |
- *-----------------------------------------------------------------------------
- *=============================================================================
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f4xx_system
- * @{
- */
-
-/** @addtogroup STM32F4xx_System_Private_Includes
- * @{
- */
-
-#include "stm32f4xx.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Defines
- * @{
- */
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
- on STM324xG_EVAL board as data memory */
-/* #define DATA_IN_ExtSRAM */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-
-
-/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
-#define PLL_M 8
-#define PLL_N 336
-
-/* SYSCLK = PLL_VCO / PLL_P */
-#define PLL_P 2
-
-/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
-#define PLL_Q 7
-
-/* PLLI2S_VCO = (HSE_VALUE Or HSI_VALUE / PLL_M) * PLLI2S_N
- I2SCLK = PLLI2S_VCO / PLLI2S_R */
-#define PLLI2S_N 192
-#define PLLI2S_R 5
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Variables
- * @{
- */
-
- uint32_t SystemCoreClock = 168000000;
-
- __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
- * @{
- */
-
-static void SetSysClock(void);
-#ifdef DATA_IN_ExtSRAM
- static void SystemInit_ExtMemCtl(void);
-#endif /* DATA_IN_ExtSRAM */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the Embedded Flash Interface, the PLL and update the
- * SystemFrequency variable.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-
-#ifdef DATA_IN_ExtSRAM
- SystemInit_ExtMemCtl();
-#endif /* DATA_IN_ExtSRAM */
-
- /* Configure the System clock source, PLL Multiplier and Divider factors,
- AHB/APBx prescalers and Flash settings ----------------------------------*/
- SetSysClock();
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
- * 16 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
- * 25 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate(void)
-{
- uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock source */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock source */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock source */
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
- SYSCLK = PLL_VCO / PLL_P
- */
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-
- pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
- SystemCoreClock = pllvco/pllp;
- break;
- default:
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK frequency --------------------------------------------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @brief Configures the System clock source, PLL Multiplier and Divider factors,
- * AHB/APBx prescalers and Flash settings
- * @Note This function should be called only once the RCC clock configuration
- * is reset to the default reset state (done in SystemInit() function).
- * @param None
- * @retval None
- */
-static void SetSysClock(void)
-{
-/******************************************************************************/
-/* PLL (clocked by HSE) used as System clock source */
-/******************************************************************************/
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable high performance mode, System frequency up to 168 MHz */
- RCC->APB1ENR |= RCC_APB1ENR_PWREN;
- PWR->CR |= PWR_CR_PMODE;
-
- /* HCLK = SYSCLK / 1*/
- RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK / 2*/
- RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
-
- /* PCLK1 = HCLK / 4*/
- RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
-
- /* Configure the main PLL */
- RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
- (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
-
- /* Enable the main PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till the main PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
- FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
-
- /* Select the main PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= RCC_CFGR_SW_PLL;
-
- /* Wait till the main PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-
-/******************************************************************************/
-/* I2S clock configuration */
-/******************************************************************************/
- /* PLLI2S clock used as I2S clock source */
- RCC->CFGR &= ~RCC_CFGR_I2SSRC;
-
- /* Configure PLLI2S */
- RCC->PLLI2SCFGR = (PLLI2S_N << 6) | (PLLI2S_R << 28);
-
- /* Enable PLLI2S */
- RCC->CR |= ((uint32_t)RCC_CR_PLLI2SON);
-
- /* Wait till PLLI2S is ready */
- while((RCC->CR & RCC_CR_PLLI2SRDY) == 0)
- {
- }
-}
-
-/**
- * @brief Setup the external memory controller. Called in startup_stm32f4xx.s
- * before jump to __main
- * @param None
- * @retval None
- */
-#ifdef DATA_IN_ExtSRAM
-/**
- * @brief Setup the external memory controller.
- * Called in startup_stm32f4xx.s before jump to main.
- * This function configures the external SRAM mounted on STM324xG_EVAL board
- * This SRAM will be used as program data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtl(void)
-{
-/*-- GPIOs Configuration -----------------------------------------------------*/
-/*
- +-------------------+--------------------+------------------+------------------+
- + SRAM pins assignment +
- +-------------------+--------------------+------------------+------------------+
- | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
- | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
- | PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
- | PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
- | PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
- | PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
- | PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
- | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+
- | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 |
- | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 |
- | PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+
- | PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 |
- | | PE15 <-> FSMC_D12 |
- +-------------------+--------------------+
-*/
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
- RCC->AHB1ENR = 0x00000078;
-
- /* Connect PDx pins to FSMC Alternate function */
- GPIOD->AFR[0] = 0x00cc00cc;
- GPIOD->AFR[1] = 0xcc0ccccc;
- /* Configure PDx pins in Alternate function mode */
- GPIOD->MODER = 0xaaaa0a0a;
- /* Configure PDx pins speed to 100 MHz */
- GPIOD->OSPEEDR = 0xffff0f0f;
- /* Configure PDx pins Output type to push-pull */
- GPIOD->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PDx pins */
- GPIOD->PUPDR = 0x00000000;
-
- /* Connect PEx pins to FSMC Alternate function */
- GPIOE->AFR[0] = 0xc00cc0cc;
- GPIOE->AFR[1] = 0xcccccccc;
- /* Configure PEx pins in Alternate function mode */
- GPIOE->MODER = 0xaaaa828a;
- /* Configure PEx pins speed to 100 MHz */
- GPIOE->OSPEEDR = 0xffffc3cf;
- /* Configure PEx pins Output type to push-pull */
- GPIOE->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PEx pins */
- GPIOE->PUPDR = 0x00000000;
-
- /* Connect PFx pins to FSMC Alternate function */
- GPIOF->AFR[0] = 0x00cccccc;
- GPIOF->AFR[1] = 0xcccc0000;
- /* Configure PFx pins in Alternate function mode */
- GPIOF->MODER = 0xaa000aaa;
- /* Configure PFx pins speed to 100 MHz */
- GPIOF->OSPEEDR = 0xff000fff;
- /* Configure PFx pins Output type to push-pull */
- GPIOF->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PFx pins */
- GPIOF->PUPDR = 0x00000000;
-
- /* Connect PGx pins to FSMC Alternate function */
- GPIOG->AFR[0] = 0x00cccccc;
- GPIOG->AFR[1] = 0x000000c0;
- /* Configure PGx pins in Alternate function mode */
- GPIOG->MODER = 0x00080aaa;
- /* Configure PGx pins speed to 100 MHz */
- GPIOG->OSPEEDR = 0x000c0fff;
- /* Configure PGx pins Output type to push-pull */
- GPIOG->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PGx pins */
- GPIOG->PUPDR = 0x00000000;
-
-/*-- FSMC Configuration ------------------------------------------------------*/
- /* Enable the FSMC interface clock */
- RCC->AHB3ENR = 0x00000001;
-
- /* Configure and enable Bank1_SRAM2 */
- FSMC_Bank1->BTCR[2] = 0x00001015;
- FSMC_Bank1->BTCR[3] = 0x00010603;//0x00010400;
- FSMC_Bank1E->BWTR[2] = 0x0fffffff;
-/*
- Bank1_SRAM2 is configured as follow:
-
- p.FSMC_AddressSetupTime = 3;//0;
- p.FSMC_AddressHoldTime = 0;
- p.FSMC_DataSetupTime = 6;//4;
- p.FSMC_BusTurnAroundDuration = 1;
- p.FSMC_CLKDivision = 0;
- p.FSMC_DataLatency = 0;
- p.FSMC_AccessMode = FSMC_AccessMode_A;
-
- FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
- FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
- FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
- FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
- FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
- FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
- FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
- FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
- FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
- FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
- FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
- FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
- FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
- FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
- FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
-*/
-
-}
-#endif /* DATA_IN_ExtSRAM */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_bsp.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief This file is responsible to offer board support package and is
- * configurable by user.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_bsp.h"
-#include "usbd_conf.h"
-#include "stm32f4_discovery.h"
-
-//Library config for this project!!!!!!!!!!!
-#include "stm32f4xx_conf.h"
-
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
-* @{
-*/
-
-/** @defgroup USB_BSP
-* @brief This file is responsible to offer board support package
-* @{
-*/
-
-/** @defgroup USB_BSP_Private_Defines
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USB_BSP_Private_TypesDefinitions
-* @{
-*/
-/**
-* @}
-*/
-
-
-
-
-
-/** @defgroup USB_BSP_Private_Macros
-* @{
-*/
-/**
-* @}
-*/
-
-/** @defgroup USBH_BSP_Private_Variables
-* @{
-*/
-
-/**
-* @}
-*/
-
-/** @defgroup USBH_BSP_Private_FunctionPrototypes
-* @{
-*/
-/**
-* @}
-*/
-
-/** @defgroup USB_BSP_Private_Functions
-* @{
-*/
-
-
-/**
-* @brief USB_OTG_BSP_Init
-* Initilizes BSP configurations
-* @param None
-* @retval None
-*/
-
-void USB_OTG_BSP_Init(USB_OTG_CORE_HANDLE *pdev)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifndef USE_ULPI_PHY
-#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
- EXTI_InitTypeDef EXTI_InitStructure;
- NVIC_InitTypeDef NVIC_InitStructure;
-#endif
-#endif
-
-
- #ifdef USE_USB_OTG_FS
-
- RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_GPIOA , ENABLE);
-
- /* Configure SOF VBUS ID DM DP Pins */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 |
- GPIO_Pin_9 |
- GPIO_Pin_11 |
- GPIO_Pin_12;
-
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- GPIO_PinAFConfig(GPIOA,GPIO_PinSource8,GPIO_AF_OTG1_FS) ;
- GPIO_PinAFConfig(GPIOA,GPIO_PinSource9,GPIO_AF_OTG1_FS) ;
- GPIO_PinAFConfig(GPIOA,GPIO_PinSource11,GPIO_AF_OTG1_FS) ;
- GPIO_PinAFConfig(GPIOA,GPIO_PinSource12,GPIO_AF_OTG1_FS) ;
-
- /* this for ID line debug */
-
-
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
- GPIO_PinAFConfig(GPIOA,GPIO_PinSource10,GPIO_AF_OTG1_FS) ;
-
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_OTG_FS, ENABLE) ;
- #else // USE_USB_OTG_HS
-
- #ifdef USE_ULPI_PHY // ULPI
- RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB |
- RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOH |
- RCC_AHB1Periph_GPIOI, ENABLE);
-
-
- GPIO_PinAFConfig(GPIOA,GPIO_PinSource3, GPIO_AF_OTG2_HS) ; // D0
- GPIO_PinAFConfig(GPIOA,GPIO_PinSource5, GPIO_AF_OTG2_HS) ; // CLK
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource0, GPIO_AF_OTG2_HS) ; // D1
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource1, GPIO_AF_OTG2_HS) ; // D2
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource5, GPIO_AF_OTG2_HS) ; // D7
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource10,GPIO_AF_OTG2_HS) ; // D3
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource11,GPIO_AF_OTG2_HS) ; // D4
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource12,GPIO_AF_OTG2_HS) ; // D5
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource13,GPIO_AF_OTG2_HS) ; // D6
- GPIO_PinAFConfig(GPIOH,GPIO_PinSource4, GPIO_AF_OTG2_HS) ; // NXT
- GPIO_PinAFConfig(GPIOI,GPIO_PinSource11,GPIO_AF_OTG2_HS) ; // DIR
- GPIO_PinAFConfig(GPIOC,GPIO_PinSource0, GPIO_AF_OTG2_HS) ; // STP
-
- // CLK
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 ;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- // D0
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 ;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-
-
- // D1 D2 D3 D4 D5 D6 D7
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 |
- GPIO_Pin_5 | GPIO_Pin_10 |
- GPIO_Pin_11| GPIO_Pin_12 |
- GPIO_Pin_13 ;
-
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
- GPIO_Init(GPIOB, &GPIO_InitStructure);
-
-
- // STP
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 ;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_Init(GPIOC, &GPIO_InitStructure);
-
- //NXT
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_Init(GPIOH, &GPIO_InitStructure);
-
-
- //DIR
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 ;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_Init(GPIOI, &GPIO_InitStructure);
-
-
- RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_OTG_HS |
- RCC_AHB1Periph_OTG_HS_ULPI, ENABLE) ;
-
- #else
- #ifdef USE_I2C_PHY
- RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_GPIOB , ENABLE);
- /* Configure RESET INTN SCL SDA (Phy/I2C) Pins */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 |
- GPIO_Pin_1 |
- GPIO_Pin_10 |
- GPIO_Pin_11;
-
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_Init(GPIOB, &GPIO_InitStructure);
-
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource0,GPIO_AF_OTG2_FS) ;
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource1,GPIO_AF_OTG2_FS) ;
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource10,GPIO_AF_OTG2_FS) ;
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource11,GPIO_AF_OTG2_FS);
- RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_OTG_HS, ENABLE) ;
-
- #else
-
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB , ENABLE);
-
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 |
- GPIO_Pin_13 |
- GPIO_Pin_14 |
- GPIO_Pin_15;
-
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_Init(GPIOB, &GPIO_InitStructure);
-
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource12, GPIO_AF_OTG2_FS) ;
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource13,GPIO_AF_OTG2_FS) ;
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource14,GPIO_AF_OTG2_FS) ;
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource15,GPIO_AF_OTG2_FS) ;
- RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_OTG_HS, ENABLE) ;
- #endif
- #endif // USE_ULPI_PHY
-
- #endif //USB_OTG_HS
-
-
- /* enable the PWR clock */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
-
- /* Configure the Key button in EXTI mode */
- STM_EVAL_PBInit(BUTTON_USER, BUTTON_MODE_EXTI);
-
-#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
- EXTI_ClearITPendingBit(EXTI_Line18);
-
- EXTI_InitStructure.EXTI_Line = EXTI_Line18;
- EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
- EXTI_InitStructure.EXTI_LineCmd = ENABLE;
- EXTI_Init(&EXTI_InitStructure);
-
- EXTI_ClearITPendingBit(EXTI_Line18);
-
- NVIC_InitStructure.NVIC_IRQChannel = OTG_FS_WKUP_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
-
- EXTI_ClearITPendingBit(EXTI_Line18);
-#endif
-
-#ifdef USB_OTG_HS_LOW_PWR_MGMT_SUPPORT
- EXTI_ClearITPendingBit(EXTI_Line20);
-
- EXTI_InitStructure.EXTI_Line = EXTI_Line20;
- EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
- EXTI_InitStructure.EXTI_LineCmd = ENABLE;
- EXTI_Init(&EXTI_InitStructure);
-
- EXTI_ClearITPendingBit(EXTI_Line20);
-
- NVIC_InitStructure.NVIC_IRQChannel = OTG_HS_WKUP_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
-
- EXTI_ClearITPendingBit(EXTI_Line20);
-#endif
-
- EXTI_ClearITPendingBit(USER_BUTTON_EXTI_LINE);
-}
-/**
-* @brief USB_OTG_BSP_EnableInterrupt
-* Enabele USB Global interrupt
-* @param None
-* @retval None
-*/
-void USB_OTG_BSP_EnableInterrupt(USB_OTG_CORE_HANDLE *pdev)
-{
- NVIC_InitTypeDef NVIC_InitStructure;
-
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
-#ifdef USE_USB_OTG_HS
- NVIC_InitStructure.NVIC_IRQChannel = OTG_HS_IRQn;
-#else
- NVIC_InitStructure.NVIC_IRQChannel = OTG_FS_IRQn;
-#endif
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
-#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
- NVIC_InitStructure.NVIC_IRQChannel = OTG_HS_EP1_OUT_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
-
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
- NVIC_InitStructure.NVIC_IRQChannel = OTG_HS_EP1_IN_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
-#endif
-}
-/**
-* @brief USB_OTG_BSP_uDelay
-* This function provides delay time in micro sec
-* @param usec : Value of delay required in micro sec
-* @retval None
-*/
-void USB_OTG_BSP_uDelay (const uint32_t usec)
-{
- uint32_t count = 0;
- const uint32_t utime = (120 * usec / 7);
- do
- {
- if ( ++count > utime )
- {
- return ;
- }
- }
- while (1);
-}
-
-
-/**
-* @brief USB_OTG_BSP_mDelay
-* This function provides delay time in milli sec
-* @param msec : Value of delay required in milli sec
-* @retval None
-*/
-void USB_OTG_BSP_mDelay (const uint32_t msec)
-{
- USB_OTG_BSP_uDelay(msec * 1000);
-}
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_conf.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief General low level driver configuration
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_CONF__H__
-#define __USB_CONF__H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-
-/** @addtogroup USB_OTG_DRIVER
- * @{
- */
-
-/** @defgroup USB_CONF
- * @brief USB low level driver configuration file
- * @{
- */
-
-/** @defgroup USB_CONF_Exported_Defines
- * @{
- */
-
-/* USB Core and PHY interface configuration.
- Tip: To avoid modifying these defines each time you need to change the USB
- configuration, you can declare the needed define in your toolchain
- compiler preprocessor.
- */
-#ifndef USE_USB_OTG_FS
- //#define USE_USB_OTG_FS
-#endif /* USE_USB_OTG_FS */
-
-#ifdef USE_USB_OTG_FS
- #define USB_OTG_FS_CORE
-#endif
-
-/*******************************************************************************
-* FIFO Size Configuration in Device mode
-*
-* (i) Receive data FIFO size = RAM for setup packets +
-* OUT endpoint control information +
-* data OUT packets + miscellaneous
-* Space = ONE 32-bits words
-* --> RAM for setup packets = 10 spaces
-* (n is the nbr of CTRL EPs the device core supports)
-* --> OUT EP CTRL info = 1 space
-* (one space for status information written to the FIFO along with each
-* received packet)
-* --> data OUT packets = (Largest Packet Size / 4) + 1 spaces
-* (MINIMUM to receive packets)
-* --> OR data OUT packets = at least 2*(Largest Packet Size / 4) + 1 spaces
-* (if high-bandwidth EP is enabled or multiple isochronous EPs)
-* --> miscellaneous = 1 space per OUT EP
-* (one space for transfer complete status information also pushed to the
-* FIFO with each endpoint's last packet)
-*
-* (ii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for
-* that particular IN EP. More space allocated in the IN EP Tx FIFO results
-* in a better performance on the USB and can hide latencies on the AHB.
-*
-* (iii) TXn min size = 16 words. (n : Transmit FIFO index)
-* (iv) When a TxFIFO is not used, the Configuration should be as follows:
-* case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
-* --> Txm can use the space allocated for Txn.
-* case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
-* --> Txn should be configured with the minimum space of 16 words
-* (v) The FIFO is used optimally when used TxFIFOs are allocated in the top
-* of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
-*******************************************************************************/
-
-
-
-/****************** USB OTG FS CONFIGURATION **********************************/
-#ifdef USB_OTG_FS_CORE
- #define RX_FIFO_FS_SIZE 128
- #define TX0_FIFO_FS_SIZE 64
- #define TX1_FIFO_FS_SIZE 128
- #define TX2_FIFO_FS_SIZE 0
- #define TX3_FIFO_FS_SIZE 0
-
- //#define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
- //#define USB_OTG_FS_SOF_OUTPUT_ENABLED
-#endif
-
-/****************** USB OTG MODE CONFIGURATION ********************************/
-
-//#define USE_HOST_MODE
-#define USE_DEVICE_MODE
-//#define USE_OTG_MODE
-
-
-#ifndef USB_OTG_FS_CORE
- #ifndef USB_OTG_HS_CORE
- #error "USB_OTG_HS_CORE or USB_OTG_FS_CORE should be defined"
- #endif
-#endif
-
-
-#ifndef USE_DEVICE_MODE
- #ifndef USE_HOST_MODE
- #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
- #endif
-#endif
-
-#ifndef USE_USB_OTG_HS
- #ifndef USE_USB_OTG_FS
- #error "USE_USB_OTG_HS or USE_USB_OTG_FS should be defined"
- #endif
-#else //USE_USB_OTG_HS
- #ifndef USE_ULPI_PHY
- #ifndef USE_EMBEDDED_PHY
- #ifndef USE_I2C_PHY
- #error "USE_ULPI_PHY or USE_EMBEDDED_PHY or USE_I2C_PHY should be defined"
- #endif
- #endif
- #endif
-#endif
-
-/****************** C Compilers dependant keywords ****************************/
-/* In HS mode and when the DMA is used, all variables and data structures dealing
- with the DMA during the transaction process should be 4-bytes aligned */
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined (__GNUC__) /* GNU Compiler */
- #define __ALIGN_END __attribute__ ((aligned (4)))
- #define __ALIGN_BEGIN
- #else
- #define __ALIGN_END
- #if defined (__CC_ARM) /* ARM Compiler */
- #define __ALIGN_BEGIN __align(4)
- #elif defined (__ICCARM__) /* IAR Compiler */
- #define __ALIGN_BEGIN
- #elif defined (__TASKING__) /* TASKING Compiler */
- #define __ALIGN_BEGIN __align(4)
- #endif /* __CC_ARM */
- #endif /* __GNUC__ */
-#else
- #define __ALIGN_BEGIN
- #define __ALIGN_END
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-
-/* __packed keyword used to decrease the data type alignment to 1-byte */
-#if defined (__CC_ARM) /* ARM Compiler */
- #define __packed __packed
-#elif defined (__ICCARM__) /* IAR Compiler */
- #define __packed __packed
-#elif defined ( __GNUC__ ) /* GNU Compiler */
- #define __packed __attribute__ ((__packed__))
-#elif defined (__TASKING__) /* TASKING Compiler */
- #define __packed __unaligned
-#endif /* __CC_ARM */
-
-/****************** C Compilers dependant keywords ****************************/
-/* In HS mode and when the DMA is used, all variables and data structures dealing
- with the DMA during the transaction process should be 4-bytes aligned */
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined (__GNUC__) /* GNU Compiler */
- #define __ALIGN_END __attribute__ ((aligned (4)))
- #define __ALIGN_BEGIN
- #else
- #define __ALIGN_END
- #if defined (__CC_ARM) /* ARM Compiler */
- #define __ALIGN_BEGIN __align(4)
- #elif defined (__ICCARM__) /* IAR Compiler */
- #define __ALIGN_BEGIN
- #elif defined (__TASKING__) /* TASKING Compiler */
- #define __ALIGN_BEGIN __align(4)
- #endif /* __CC_ARM */
- #endif /* __GNUC__ */
-#else
- #define __ALIGN_BEGIN
- #define __ALIGN_END
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-
-/* __packed keyword used to decrease the data type alignment to 1-byte */
-#if defined (__CC_ARM) /* ARM Compiler */
- #define __packed __packed
-#elif defined (__ICCARM__) /* IAR Compiler */
- #define __packed __packed
-#elif defined ( __GNUC__ ) /* GNU Compiler */
- #define __packed __attribute__ ((__packed__))
-#elif defined (__TASKING__) /* TASKING Compiler */
- #define __packed __unaligned
-#endif /* __CC_ARM */
-
-
-/**
- * @}
- */
-
-
-/** @defgroup USB_CONF_Exported_Types
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_CONF_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_CONF_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_CONF_Exported_FunctionsPrototype
- * @{
- */
-/**
- * @}
- */
-
-
-#endif //__USB_CONF__H__
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_core.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief USB-OTG Core Layer
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_core.h"
-#include "usb_bsp.h"
-
-
-/** @addtogroup USB_OTG_DRIVER
-* @{
-*/
-
-/** @defgroup USB_CORE
-* @brief This file includes the USB-OTG Core Layer
-* @{
-*/
-
-
-/** @defgroup USB_CORE_Private_Defines
-* @{
-*/
-
-/**
-* @}
-*/
-
-
-/** @defgroup USB_CORE_Private_TypesDefinitions
-* @{
-*/
-/**
-* @}
-*/
-
-
-
-/** @defgroup USB_CORE_Private_Macros
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USB_CORE_Private_Variables
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USB_CORE_Private_FunctionPrototypes
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USB_CORE_Private_Functions
-* @{
-*/
-
-/**
-* @brief USB_OTG_EnableCommonInt
-* Initializes the commmon interrupts, used in both device and modes
-* @param pdev : Selected device
-* @retval None
-*/
-static void USB_OTG_EnableCommonInt(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_GINTMSK_TypeDef int_mask;
-
- int_mask.d32 = 0;
- /* Clear any pending USB_OTG Interrupts */
-#ifndef USE_OTG_MODE
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GOTGINT, 0xFFFFFFFF);
-#endif
- /* Clear any pending interrupts */
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF);
- /* Enable the interrupts in the INTMSK */
- int_mask.b.wkupintr = 1;
- int_mask.b.usbsuspend = 1;
-
-#ifdef USE_OTG_MODE
- int_mask.b.otgintr = 1;
- int_mask.b.sessreqintr = 1;
- int_mask.b.conidstschng = 1;
-#endif
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32);
-}
-
-/**
-* @brief USB_OTG_CoreReset : Soft reset of the core
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-static USB_OTG_STS USB_OTG_CoreReset(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_STS status = USB_OTG_OK;
- __IO USB_OTG_GRSTCTL_TypeDef greset;
- uint32_t count = 0;
-
- greset.d32 = 0;
- /* Wait for AHB master IDLE state. */
- do
- {
- USB_OTG_BSP_uDelay(3);
- greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL);
- if (++count > 200000)
- {
- return USB_OTG_OK;
- }
- }
- while (greset.b.ahbidle == 0);
- /* Core Soft Reset */
- count = 0;
- greset.b.csftrst = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRSTCTL, greset.d32 );
- do
- {
- greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL);
- if (++count > 200000)
- {
- break;
- }
- }
- while (greset.b.csftrst == 1);
- /* Wait for 3 PHY Clocks*/
- USB_OTG_BSP_uDelay(3);
- return status;
-}
-
-/**
-* @brief USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated
-* with the EP
-* @param pdev : Selected device
-* @param src : source pointer
-* @param ch_ep_num : end point number
-* @param bytes : No. of bytes
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev,
- uint8_t *src,
- uint8_t ch_ep_num,
- uint16_t len)
-{
- USB_OTG_STS status = USB_OTG_OK;
- if (pdev->cfg.dma_enable == 0)
- {
- uint32_t count32b= 0 , i= 0;
- __IO uint32_t *fifo;
-
- count32b = (len + 3) / 4;
- fifo = pdev->regs.DFIFO[ch_ep_num];
- for (i = 0; i < count32b; i++, src+=4)
- {
- USB_OTG_WRITE_REG32( fifo, *((__packed uint32_t *)src) );
- }
- }
- return status;
-}
-
-
-/**
-* @brief USB_OTG_ReadPacket : Reads a packet from the Rx FIFO
-* @param pdev : Selected device
-* @param dest : Destination Pointer
-* @param bytes : No. of bytes
-* @retval None
-*/
-void *USB_OTG_ReadPacket(USB_OTG_CORE_HANDLE *pdev,
- uint8_t *dest,
- uint16_t len)
-{
- uint32_t i=0;
- uint32_t count32b = (len + 3) / 4;
-
- __IO uint32_t *fifo = pdev->regs.DFIFO[0];
-
- for ( i = 0; i < count32b; i++, dest += 4 )
- {
- *(__packed uint32_t *)dest = USB_OTG_READ_REG32(fifo);
-
- }
- return ((void *)dest);
-}
-
-/**
-* @brief USB_OTG_SelectCore
-* Initialize core registers address.
-* @param pdev : Selected device
-* @param coreID : USB OTG Core ID
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev,
- USB_OTG_CORE_ID_TypeDef coreID)
-{
- uint32_t i , baseAddress = 0;
- USB_OTG_STS status = USB_OTG_OK;
-
- pdev->cfg.dma_enable = 0;
-
- /* at startup the core is in FS mode */
- pdev->cfg.speed = USB_OTG_SPEED_FULL;
- pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ;
-
- /* initialize device cfg following its address */
- if (coreID == USB_OTG_FS_CORE_ID)
- {
- baseAddress = USB_OTG_FS_BASE_ADDR;
- pdev->cfg.coreID = USB_OTG_FS_CORE_ID;
- pdev->cfg.host_channels = 8 ;
- pdev->cfg.dev_endpoints = 4 ;
- pdev->cfg.TotalFifoSize = 320; /* in 32-bits */
- pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY;
-
-#ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED
- pdev->cfg.Sof_output = 1;
-#endif
-
-#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
- pdev->cfg.low_power = 1;
-#endif
- }
- else if (coreID == USB_OTG_HS_CORE_ID)
- {
- baseAddress = USB_OTG_HS_BASE_ADDR;
- pdev->cfg.coreID = USB_OTG_HS_CORE_ID;
- pdev->cfg.host_channels = 12 ;
- pdev->cfg.dev_endpoints = 6 ;
- pdev->cfg.TotalFifoSize = 1280;/* in 32-bits */
-
-#ifdef USB_OTG_ULPI_PHY_ENABLED
- pdev->cfg.phy_itface = USB_OTG_ULPI_PHY;
-#else
- #ifdef USB_OTG_EMBEDDED_PHY_ENABLED
- pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY;
- #else
- #ifdef USB_OTG_I2C_PHY_ENABLED
- pdev->cfg.phy_itface = USB_OTG_I2C_PHY;
- #endif
- #endif
-#endif
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- pdev->cfg.dma_enable = 1;
-#endif
-
-#ifdef USB_OTG_HS_SOF_OUTPUT_ENABLED
- pdev->cfg.Sof_output = 1;
-#endif
-
-#ifdef USB_OTG_HS_LOW_PWR_MGMT_SUPPORT
- pdev->cfg.low_power = 1;
-#endif
-
- }
-
- pdev->regs.GREGS = (USB_OTG_GREGS *)(baseAddress + \
- USB_OTG_CORE_GLOBAL_REGS_OFFSET);
- pdev->regs.DREGS = (USB_OTG_DREGS *) (baseAddress + \
- USB_OTG_DEV_GLOBAL_REG_OFFSET);
-
- for (i = 0; i < pdev->cfg.dev_endpoints; i++)
- {
- pdev->regs.INEP_REGS[i] = (USB_OTG_INEPREGS *) \
- (baseAddress + USB_OTG_DEV_IN_EP_REG_OFFSET + \
- (i * USB_OTG_EP_REG_OFFSET));
- pdev->regs.OUTEP_REGS[i] = (USB_OTG_OUTEPREGS *) \
- (baseAddress + USB_OTG_DEV_OUT_EP_REG_OFFSET + \
- (i * USB_OTG_EP_REG_OFFSET));
- }
- pdev->regs.HREGS = (USB_OTG_HREGS *)(baseAddress + \
- USB_OTG_HOST_GLOBAL_REG_OFFSET);
- pdev->regs.HPRT0 = (uint32_t *)(baseAddress + USB_OTG_HOST_PORT_REGS_OFFSET);
-
- for (i = 0; i < pdev->cfg.host_channels; i++)
- {
- pdev->regs.HC_REGS[i] = (USB_OTG_HC_REGS *)(baseAddress + \
- USB_OTG_HOST_CHAN_REGS_OFFSET + \
- (i * USB_OTG_CHAN_REGS_OFFSET));
- }
- for (i = 0; i < pdev->cfg.host_channels; i++)
- {
- pdev->regs.DFIFO[i] = (uint32_t *)(baseAddress + USB_OTG_DATA_FIFO_OFFSET +\
- (i * USB_OTG_DATA_FIFO_SIZE));
- }
- pdev->regs.PCGCCTL = (uint32_t *)(baseAddress + USB_OTG_PCGCCTL_OFFSET);
-
- return status;
-}
-
-
-/**
-* @brief USB_OTG_CoreInit
-* Initializes the USB_OTG controller registers and prepares the core
-* device mode or host mode operation.
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_GUSBCFG_TypeDef usbcfg;
- USB_OTG_GCCFG_TypeDef gccfg;
- USB_OTG_GI2CCTL_TypeDef i2cctl;
- USB_OTG_GAHBCFG_TypeDef ahbcfg;
-
- usbcfg.d32 = 0;
- gccfg.d32 = 0;
- ahbcfg.d32 = 0;
-
-
-
- if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY)
- {
- gccfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GCCFG);
- gccfg.b.pwdn = 0;
-
- if (pdev->cfg.Sof_output)
- {
- gccfg.b.sofouten = 1;
- }
- USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32);
-
- /* Init The ULPI Interface */
- usbcfg.d32 = 0;
- usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
-
- usbcfg.b.physel = 0; /* HS Interface */
-#ifdef USB_OTG_INTERNAL_VBUS_ENABLED
- usbcfg.b.ulpi_ext_vbus_drv = 0; /* Use internal VBUS */
-#else
- #ifdef USB_OTG_EXTERNAL_VBUS_ENABLED
- usbcfg.b.ulpi_ext_vbus_drv = 1; /* Use external VBUS */
- #endif
-#endif
- usbcfg.b.term_sel_dl_pulse = 0; /* Data line pulsing using utmi_txvalid */
- usbcfg.b.ulpi_utmi_sel = 1; /* ULPI seleInterfacect */
-
- usbcfg.b.phyif = 0; /* 8 bits */
- usbcfg.b.ddrsel = 0; /* single data rate */
-
- usbcfg.b.ulpi_fsls = 0;
- usbcfg.b.ulpi_clk_sus_m = 0;
- USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
-
- /* Reset after a PHY select */
- USB_OTG_CoreReset(pdev);
-
- if(pdev->cfg.dma_enable == 1)
- {
-
- ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/
- ahbcfg.b.dmaenable = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32);
-
- }
- }
- else /* FS interface (embedded Phy or I2C Phy) */
- {
-
- usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);;
- usbcfg.b.physel = 1; /* FS Interface */
- USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
- /* Reset after a PHY select and set Host mode */
- USB_OTG_CoreReset(pdev);
- /* Enable the I2C interface and deactivate the power down*/
- gccfg.d32 = 0;
- gccfg.b.pwdn = 1;
-
- if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY)
- {
- gccfg.b.i2cifen = 1;
- }
- gccfg.b.vbussensingA = 1 ;
- gccfg.b.vbussensingB = 1 ;
-#ifndef VBUS_SENSING_ENABLED
- gccfg.b.disablevbussensing = 1;
-#endif
-
- if(pdev->cfg.Sof_output)
- {
- gccfg.b.sofouten = 1;
- }
-
- USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32);
- USB_OTG_BSP_mDelay(20);
- /* Program GUSBCFG.OtgUtmifsSel to I2C*/
- usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
-
- if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY)
- {
- usbcfg.b.otgutmifssel = 1;
- }
-
- USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
-
- if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY)
- {
- /*Program GI2CCTL.I2CEn*/
- i2cctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GI2CCTL);
- i2cctl.b.i2cdevaddr = 1;
- i2cctl.b.i2cen = 0;
- i2cctl.b.dat_se0 = 1;
- i2cctl.b.addr = 0x2D;
- USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GI2CCTL, i2cctl.d32);
-
- USB_OTG_BSP_mDelay(200);
-
- i2cctl.b.i2cen = 1;
- USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GI2CCTL, i2cctl.d32);
- USB_OTG_BSP_mDelay(200);
- }
- }
- /* case the HS core is working in FS mode */
- if(pdev->cfg.dma_enable == 1)
- {
-
- ahbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GAHBCFG);
- ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/
- ahbcfg.b.dmaenable = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32);
-
- }
- /* initialize OTG features */
-#ifdef USE_OTG_MODE
- usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
- usbcfg.b.hnpcap = 1;
- usbcfg.b.srpcap = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
- USB_OTG_EnableCommonInt(pdev);
-#endif
- return status;
-}
-/**
-* @brief USB_OTG_EnableGlobalInt
-* Enables the controller's Global Int in the AHB Config reg
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EnableGlobalInt(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_GAHBCFG_TypeDef ahbcfg;
-
- ahbcfg.d32 = 0;
- ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
- USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, 0, ahbcfg.d32);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_DisableGlobalInt
-* Enables the controller's Global Int in the AHB Config reg
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_GAHBCFG_TypeDef ahbcfg;
- ahbcfg.d32 = 0;
- ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
- USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32, 0);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
-* @param pdev : Selected device
-* @param num : FO num
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num )
-{
- USB_OTG_STS status = USB_OTG_OK;
- __IO USB_OTG_GRSTCTL_TypeDef greset;
-
- uint32_t count = 0;
- greset.d32 = 0;
- greset.b.txfflsh = 1;
- greset.b.txfnum = num;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 );
- do
- {
- greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL);
- if (++count > 200000)
- {
- break;
- }
- }
- while (greset.b.txfflsh == 1);
- /* Wait for 3 PHY Clocks*/
- USB_OTG_BSP_uDelay(3);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_FlushRxFifo : Flush a Rx FIFO
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_FlushRxFifo( USB_OTG_CORE_HANDLE *pdev )
-{
- USB_OTG_STS status = USB_OTG_OK;
- __IO USB_OTG_GRSTCTL_TypeDef greset;
- uint32_t count = 0;
-
- greset.d32 = 0;
- greset.b.rxfflsh = 1;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 );
- do
- {
- greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL);
- if (++count > 200000)
- {
- break;
- }
- }
- while (greset.b.rxfflsh == 1);
- /* Wait for 3 PHY Clocks*/
- USB_OTG_BSP_uDelay(3);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_SetCurrentMode : Set ID line
-* @param pdev : Selected device
-* @param mode : (Host/device)
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE *pdev , uint8_t mode)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_GUSBCFG_TypeDef usbcfg;
-
- usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
-
- usbcfg.b.force_host = 0;
- usbcfg.b.force_dev = 0;
-
- if ( mode == HOST_MODE)
- {
- usbcfg.b.force_host = 1;
- }
- else if ( mode == DEVICE_MODE)
- {
- usbcfg.b.force_dev = 1;
- }
-
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
- USB_OTG_BSP_mDelay(50);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_GetMode : Get current mode
-* @param pdev : Selected device
-* @retval current mode
-*/
-uint32_t USB_OTG_GetMode(USB_OTG_CORE_HANDLE *pdev)
-{
- return (USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS ) & 0x1);
-}
-
-
-/**
-* @brief USB_OTG_IsDeviceMode : Check if it is device mode
-* @param pdev : Selected device
-* @retval num_in_ep
-*/
-uint8_t USB_OTG_IsDeviceMode(USB_OTG_CORE_HANDLE *pdev)
-{
- return (USB_OTG_GetMode(pdev) != HOST_MODE);
-}
-
-
-/**
-* @brief USB_OTG_IsHostMode : Check if it is host mode
-* @param pdev : Selected device
-* @retval num_in_ep
-*/
-uint8_t USB_OTG_IsHostMode(USB_OTG_CORE_HANDLE *pdev)
-{
- return (USB_OTG_GetMode(pdev) == HOST_MODE);
-}
-
-
-/**
-* @brief USB_OTG_ReadCoreItr : returns the Core Interrupt register
-* @param pdev : Selected device
-* @retval Status
-*/
-uint32_t USB_OTG_ReadCoreItr(USB_OTG_CORE_HANDLE *pdev)
-{
- uint32_t v = 0;
- v = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS);
- v &= USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK);
- return v;
-}
-
-
-/**
-* @brief USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register
-* @param pdev : Selected device
-* @retval Status
-*/
-uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev)
-{
- return (USB_OTG_READ_REG32 (&pdev->regs.GREGS->GOTGINT));
-}
-
-#ifdef USE_HOST_MODE
-/**
-* @brief USB_OTG_CoreInitHost : Initializes USB_OTG controller for host mode
-* @param pdev : Selected device
-* @retval status
-*/
-USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_FSIZ_TypeDef nptxfifosize;
- USB_OTG_FSIZ_TypeDef ptxfifosize;
- USB_OTG_HCFG_TypeDef hcfg;
-
-#ifdef USE_OTG_MODE
- USB_OTG_OTGCTL_TypeDef gotgctl;
-#endif
-
- uint32_t i = 0;
-
- nptxfifosize.d32 = 0;
- ptxfifosize.d32 = 0;
-#ifdef USE_OTG_MODE
- gotgctl.d32 = 0;
-#endif
- hcfg.d32 = 0;
-
-
- /* configure charge pump IO */
- USB_OTG_BSP_ConfigVBUS(pdev);
-
- /* Restart the Phy Clock */
- USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0);
-
- /* Initialize Host Configuration Register */
- USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ); /* in init phase */
-
- hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG);
- hcfg.b.fslssupp = 0;
- USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32);
-
- /* Configure data FIFO sizes */
- /* Rx FIFO */
-#ifdef USB_OTG_FS_CORE
- if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID)
- {
- /* set Rx FIFO size */
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE);
- nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE;
- nptxfifosize.b.depth = TXH_NP_FS_FIFOSIZ;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32);
-
- ptxfifosize.b.startaddr = RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ;
- ptxfifosize.b.depth = TXH_P_FS_FIFOSIZ;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32);
- }
-#endif
-#ifdef USB_OTG_HS_CORE
- if (pdev->cfg.coreID == USB_OTG_HS_CORE_ID)
- {
- /* set Rx FIFO size */
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE);
- nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE;
- nptxfifosize.b.depth = TXH_NP_HS_FIFOSIZ;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32);
-
- ptxfifosize.b.startaddr = RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ;
- ptxfifosize.b.depth = TXH_P_HS_FIFOSIZ;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32);
- }
-#endif
-
-#ifdef USE_OTG_MODE
- /* Clear Host Set HNP Enable in the USB_OTG Control Register */
- gotgctl.b.hstsethnpen = 1;
- USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0);
-#endif
-
- /* Make sure the FIFOs are flushed. */
- USB_OTG_FlushTxFifo(pdev, 0x10 ); /* all Tx FIFOs */
- USB_OTG_FlushRxFifo(pdev);
-
-
- /* Clear all pending HC Interrupts */
- for (i = 0; i < pdev->cfg.host_channels; i++)
- {
- USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINT, 0xFFFFFFFF );
- USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCGINTMSK, 0 );
- }
-#ifndef USE_OTG_MODE
- USB_OTG_DriveVbus(pdev, 1);
-#endif
-
- USB_OTG_EnableHostInt(pdev);
- return status;
-}
-
-/**
-* @brief USB_OTG_IsEvenFrame
-* This function returns the frame number for sof packet
-* @param pdev : Selected device
-* @retval Frame number
-*/
-uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev)
-{
- return !(USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0x1);
-}
-
-/**
-* @brief USB_OTG_DriveVbus : set/reset vbus
-* @param pdev : Selected device
-* @param state : VBUS state
-* @retval None
-*/
-void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state)
-{
- USB_OTG_HPRT0_TypeDef hprt0;
-
- hprt0.d32 = 0;
-
- /* enable disable the external charge pump */
- USB_OTG_BSP_DriveVBUS(pdev, state);
-
- /* Turn on the Host port power. */
- hprt0.d32 = USB_OTG_ReadHPRT0(pdev);
- if ((hprt0.b.prtpwr == 0 ) && (state == 1 ))
- {
- hprt0.b.prtpwr = 1;
- USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
- }
- if ((hprt0.b.prtpwr == 1 ) && (state == 0 ))
- {
- hprt0.b.prtpwr = 0;
- USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
- }
-
- USB_OTG_BSP_mDelay(200);
-}
-/**
-* @brief USB_OTG_EnableHostInt: Enables the Host mode interrupts
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EnableHostInt(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_GINTMSK_TypeDef intmsk;
- intmsk.d32 = 0;
- /* Disable all interrupts. */
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTMSK, 0);
-
- /* Clear any pending interrupts. */
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF);
-
- /* Enable the common interrupts */
- USB_OTG_EnableCommonInt(pdev);
-
- if (pdev->cfg.dma_enable == 0)
- {
- intmsk.b.rxstsqlvl = 1;
- }
- intmsk.b.portintr = 1;
- intmsk.b.hcintr = 1;
- intmsk.b.disconnect = 1;
- intmsk.b.sofintr = 1;
- intmsk.b.incomplisoout = 1;
- USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32);
- return status;
-}
-
-/**
-* @brief USB_OTG_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
-* HCFG register on the PHY type
-* @param pdev : Selected device
-* @param freq : clock frequency
-* @retval None
-*/
-void USB_OTG_InitFSLSPClkSel(USB_OTG_CORE_HANDLE *pdev , uint8_t freq)
-{
- USB_OTG_HCFG_TypeDef hcfg;
-
- hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG);
- hcfg.b.fslspclksel = freq;
- USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32);
-}
-
-
-/**
-* @brief USB_OTG_ReadHPRT0 : Reads HPRT0 to modify later
-* @param pdev : Selected device
-* @retval HPRT0 value
-*/
-uint32_t USB_OTG_ReadHPRT0(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_HPRT0_TypeDef hprt0;
-
- hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
- hprt0.b.prtena = 0;
- hprt0.b.prtconndet = 0;
- hprt0.b.prtenchng = 0;
- hprt0.b.prtovrcurrchng = 0;
- return hprt0.d32;
-}
-
-
-/**
-* @brief USB_OTG_ReadHostAllChannels_intr : Register PCD Callbacks
-* @param pdev : Selected device
-* @retval Status
-*/
-uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev)
-{
- return (USB_OTG_READ_REG32 (&pdev->regs.HREGS->HAINT));
-}
-
-
-/**
-* @brief USB_OTG_ResetPort : Reset Host Port
-* @param pdev : Selected device
-* @retval status
-* @note : (1)The application must wait at least 10 ms (+ 10 ms security)
-* before clearing the reset bit.
-*/
-uint32_t USB_OTG_ResetPort(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_HPRT0_TypeDef hprt0;
-
- hprt0.d32 = USB_OTG_ReadHPRT0(pdev);
- hprt0.b.prtrst = 1;
- USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
- USB_OTG_BSP_mDelay (10); /* See Note #1 */
- hprt0.b.prtrst = 0;
- USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
- USB_OTG_BSP_mDelay (20);
- return 1;
-}
-
-
-/**
-* @brief USB_OTG_HC_Init : Prepares a host channel for transferring packets
-* @param pdev : Selected device
-* @param hc_num : channel number
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_HC_Init(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
-{
- USB_OTG_STS status = USB_OTG_OK;
- uint32_t intr_enable = 0;
- USB_OTG_HCGINTMSK_TypeDef hcintmsk;
- USB_OTG_GINTMSK_TypeDef gintmsk;
- USB_OTG_HCCHAR_TypeDef hcchar;
- USB_OTG_HCINTn_TypeDef hcint;
-
-
- gintmsk.d32 = 0;
- hcintmsk.d32 = 0;
- hcchar.d32 = 0;
-
- /* Clear old interrupt conditions for this host channel. */
- hcint.d32 = 0xFFFFFFFF;
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINT, hcint.d32);
-
- /* Enable channel interrupts required for this transfer. */
- hcintmsk.d32 = 0;
-
- if (pdev->cfg.dma_enable == 1)
- {
- hcintmsk.b.ahberr = 1;
- }
-
- switch (pdev->host.hc[hc_num].ep_type)
- {
- case EP_TYPE_CTRL:
- case EP_TYPE_BULK:
- hcintmsk.b.xfercompl = 1;
- hcintmsk.b.stall = 1;
- hcintmsk.b.xacterr = 1;
- hcintmsk.b.datatglerr = 1;
- hcintmsk.b.nak = 1;
- if (pdev->host.hc[hc_num].ep_is_in)
- {
- hcintmsk.b.bblerr = 1;
- }
- else
- {
- hcintmsk.b.nyet = 1;
- if (pdev->host.hc[hc_num].do_ping)
- {
- hcintmsk.b.ack = 1;
- }
- }
- break;
- case EP_TYPE_INTR:
- hcintmsk.b.xfercompl = 1;
- hcintmsk.b.nak = 1;
- hcintmsk.b.stall = 1;
- hcintmsk.b.xacterr = 1;
- hcintmsk.b.datatglerr = 1;
- hcintmsk.b.frmovrun = 1;
-
- if (pdev->host.hc[hc_num].ep_is_in)
- {
- hcintmsk.b.bblerr = 1;
- }
-
- break;
- case EP_TYPE_ISOC:
- hcintmsk.b.xfercompl = 1;
- hcintmsk.b.frmovrun = 1;
- hcintmsk.b.ack = 1;
-
- if (pdev->host.hc[hc_num].ep_is_in)
- {
- hcintmsk.b.xacterr = 1;
- hcintmsk.b.bblerr = 1;
- }
- break;
- }
-
-
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, hcintmsk.d32);
-
-
- /* Enable the top level host channel interrupt. */
- intr_enable = (1 << hc_num);
- USB_OTG_MODIFY_REG32(&pdev->regs.HREGS->HAINTMSK, 0, intr_enable);
-
- /* Make sure host channel interrupts are enabled. */
- gintmsk.b.hcintr = 1;
- USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, gintmsk.d32);
-
- /* Program the HCCHAR register */
- hcchar.d32 = 0;
- hcchar.b.devaddr = pdev->host.hc[hc_num].dev_addr;
- hcchar.b.epnum = pdev->host.hc[hc_num].ep_num;
- hcchar.b.epdir = pdev->host.hc[hc_num].ep_is_in;
- hcchar.b.lspddev = (pdev->host.hc[hc_num].speed == HPRT0_PRTSPD_LOW_SPEED);
- hcchar.b.eptype = pdev->host.hc[hc_num].ep_type;
- hcchar.b.mps = pdev->host.hc[hc_num].max_packet;
- if (pdev->host.hc[hc_num].ep_type == HCCHAR_INTR)
- {
- hcchar.b.oddfrm = 1;
- }
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_HC_StartXfer : Start transfer
-* @param pdev : Selected device
-* @param hc_num : channel number
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_HC_StartXfer(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_HCCHAR_TypeDef hcchar;
- USB_OTG_HCTSIZn_TypeDef hctsiz;
- USB_OTG_HNPTXSTS_TypeDef hnptxsts;
- USB_OTG_HPTXSTS_TypeDef hptxsts;
- USB_OTG_GINTMSK_TypeDef intmsk;
- uint16_t len_words = 0;
-
- uint16_t num_packets;
- uint16_t max_hc_pkt_count;
-
- max_hc_pkt_count = 256;
- hctsiz.d32 = 0;
- hcchar.d32 = 0;
- intmsk.d32 = 0;
-
- /* Compute the expected number of packets associated to the transfer */
- if (pdev->host.hc[hc_num].xfer_len > 0)
- {
- num_packets = (pdev->host.hc[hc_num].xfer_len + \
- pdev->host.hc[hc_num].max_packet - 1) / pdev->host.hc[hc_num].max_packet;
-
- if (num_packets > max_hc_pkt_count)
- {
- num_packets = max_hc_pkt_count;
- pdev->host.hc[hc_num].xfer_len = num_packets * \
- pdev->host.hc[hc_num].max_packet;
- }
- }
- else
- {
- num_packets = 1;
- }
- if (pdev->host.hc[hc_num].ep_is_in)
- {
- pdev->host.hc[hc_num].xfer_len = num_packets * \
- pdev->host.hc[hc_num].max_packet;
- }
- /* Initialize the HCTSIZn register */
- hctsiz.b.xfersize = pdev->host.hc[hc_num].xfer_len;
- hctsiz.b.pktcnt = num_packets;
- hctsiz.b.pid = pdev->host.hc[hc_num].data_pid;
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32);
-
- if (pdev->cfg.dma_enable == 1)
- {
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCDMA, (unsigned int)pdev->host.hc[hc_num].xfer_buff);
- }
-
-
- hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR);
- hcchar.b.oddfrm = USB_OTG_IsEvenFrame(pdev);
-
- /* Set host channel enable */
- hcchar.b.chen = 1;
- hcchar.b.chdis = 0;
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
-
- if (pdev->cfg.dma_enable == 0) /* Slave mode */
- {
- if((pdev->host.hc[hc_num].ep_is_in == 0) &&
- (pdev->host.hc[hc_num].xfer_len > 0))
- {
- switch(pdev->host.hc[hc_num].ep_type)
- {
- /* Non periodic transfer */
- case EP_TYPE_CTRL:
- case EP_TYPE_BULK:
-
- hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
- len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4;
-
- /* check if there is enough space in FIFO space */
- if(len_words > hnptxsts.b.nptxfspcavail)
- {
- /* need to process data in nptxfempty interrupt */
- intmsk.b.nptxfempty = 1;
- USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32);
- }
-
- break;
- /* Periodic transfer */
- case EP_TYPE_INTR:
- case EP_TYPE_ISOC:
- hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
- len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4;
- /* check if there is enough space in FIFO space */
- if(len_words > hptxsts.b.ptxfspcavail) /* split the transfer */
- {
- /* need to process data in ptxfempty interrupt */
- intmsk.b.ptxfempty = 1;
- USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32);
- }
- break;
-
- default:
- break;
- }
-
- /* Write packet into the Tx FIFO. */
- USB_OTG_WritePacket(pdev,
- pdev->host.hc[hc_num].xfer_buff ,
- hc_num, pdev->host.hc[hc_num].xfer_len);
- }
- }
- return status;
-}
-
-
-/**
-* @brief USB_OTG_HC_Halt : Halt channel
-* @param pdev : Selected device
-* @param hc_num : channel number
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_HC_Halt(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_HNPTXSTS_TypeDef nptxsts;
- USB_OTG_HPTXSTS_TypeDef hptxsts;
- USB_OTG_HCCHAR_TypeDef hcchar;
-
- nptxsts.d32 = 0;
- hptxsts.d32 = 0;
- hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR);
- hcchar.b.chen = 1;
- hcchar.b.chdis = 1;
-
- /* Check for space in the request queue to issue the halt. */
- if (hcchar.b.eptype == HCCHAR_CTRL || hcchar.b.eptype == HCCHAR_BULK)
- {
- nptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
- if (nptxsts.b.nptxqspcavail == 0)
- {
- hcchar.b.chen = 0;
- }
- }
- else
- {
- hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
- if (hptxsts.b.ptxqspcavail == 0)
- {
- hcchar.b.chen = 0;
- }
- }
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
- return status;
-}
-
-/**
-* @brief Issue a ping token
-* @param None
-* @retval : None
-*/
-USB_OTG_STS USB_OTG_HC_DoPing(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_HCCHAR_TypeDef hcchar;
- USB_OTG_HCTSIZn_TypeDef hctsiz;
-
- hctsiz.d32 = 0;
- hctsiz.b.dopng = 1;
- hctsiz.b.pktcnt = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32);
-
- hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR);
- hcchar.b.chen = 1;
- hcchar.b.chdis = 0;
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
- return status;
-}
-
-/**
-* @brief Stop the device and clean up fifo's
-* @param None
-* @retval : None
-*/
-void USB_OTG_StopHost(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_HCCHAR_TypeDef hcchar;
- uint32_t i;
-
- USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINTMSK , 0);
- USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINT, 0xFFFFFFFF);
- /* Flush out any leftover queued requests. */
-
- for (i = 0; i < pdev->cfg.host_channels; i++)
- {
- hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR);
- hcchar.b.chen = 0;
- hcchar.b.chdis = 1;
- hcchar.b.epdir = 0;
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[i]->HCCHAR, hcchar.d32);
- }
-
- /* Flush the FIFO */
- USB_OTG_FlushRxFifo(pdev);
- USB_OTG_FlushTxFifo(pdev , 0x10 );
-}
-#endif
-#ifdef USE_DEVICE_MODE
-/* PCD Core Layer */
-
-/**
-* @brief USB_OTG_InitDevSpeed :Initializes the DevSpd field of DCFG register
-* depending the PHY type and the enumeration speed of the device.
-* @param pdev : Selected device
-* @retval : None
-*/
-void USB_OTG_InitDevSpeed(USB_OTG_CORE_HANDLE *pdev , uint8_t speed)
-{
- USB_OTG_DCFG_TypeDef dcfg;
-
- dcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCFG);
- dcfg.b.devspd = speed;
- USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCFG, dcfg.d32);
-}
-
-
-/**
-* @brief USB_OTG_CoreInitDev : Initializes the USB_OTG controller registers
-* for device mode
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_DEPCTL_TypeDef depctl;
- uint32_t i;
- USB_OTG_DCFG_TypeDef dcfg;
- USB_OTG_FSIZ_TypeDef nptxfifosize;
- USB_OTG_FSIZ_TypeDef txfifosize;
- USB_OTG_DIEPMSK_TypeDef msk;
- USB_OTG_DTHRCTL_TypeDef dthrctl;
-
- depctl.d32 = 0;
- dcfg.d32 = 0;
- nptxfifosize.d32 = 0;
- txfifosize.d32 = 0;
- msk.d32 = 0;
-
- /* Restart the Phy Clock */
- USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0);
- /* Device configuration register */
- dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG);
- dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80;
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32 );
-
-#ifdef USB_OTG_FS_CORE
- if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID )
- {
-
- /* Set Full speed phy */
- USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_FULL);
-
- /* set Rx FIFO size */
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE);
-
- /* EP0 TX*/
- nptxfifosize.b.depth = TX0_FIFO_FS_SIZE;
- nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 );
-
-
- /* EP1 TX*/
- txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
- txfifosize.b.depth = TX1_FIFO_FS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 );
-
-
- /* EP2 TX*/
- txfifosize.b.startaddr += txfifosize.b.depth;
- txfifosize.b.depth = TX2_FIFO_FS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 );
-
-
- /* EP3 TX*/
- txfifosize.b.startaddr += txfifosize.b.depth;
- txfifosize.b.depth = TX3_FIFO_FS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 );
- }
-#endif
-#ifdef USB_OTG_HS_CORE
- if(pdev->cfg.coreID == USB_OTG_HS_CORE_ID )
- {
-
- /* Set High speed phy */
-
- if(pdev->cfg.phy_itface == USB_OTG_ULPI_PHY)
- {
- USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH);
- }
- else /* set High speed phy in Full speed mode */
- {
- USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH_IN_FULL);
- }
-
- /* set Rx FIFO size */
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE);
-
- /* EP0 TX*/
- nptxfifosize.b.depth = TX0_FIFO_HS_SIZE;
- nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 );
-
-
- /* EP1 TX*/
- txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
- txfifosize.b.depth = TX1_FIFO_HS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 );
-
-
- /* EP2 TX*/
- txfifosize.b.startaddr += txfifosize.b.depth;
- txfifosize.b.depth = TX2_FIFO_HS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 );
-
-
- /* EP3 TX*/
- txfifosize.b.startaddr += txfifosize.b.depth;
- txfifosize.b.depth = TX3_FIFO_HS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 );
-
- /* EP4 TX*/
- txfifosize.b.startaddr += txfifosize.b.depth;
- txfifosize.b.depth = TX4_FIFO_HS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[3], txfifosize.d32 );
-
-
- /* EP5 TX*/
- txfifosize.b.startaddr += txfifosize.b.depth;
- txfifosize.b.depth = TX5_FIFO_HS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[4], txfifosize.d32 );
- }
-#endif
- /* Flush the FIFOs */
- USB_OTG_FlushTxFifo(pdev , 0x10); /* all Tx FIFOs */
- USB_OTG_FlushRxFifo(pdev);
- /* Clear all pending Device Interrupts */
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 );
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 );
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF );
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 );
-
- for (i = 0; i < pdev->cfg.dev_endpoints; i++)
- {
- depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[i]->DIEPCTL);
- if (depctl.b.epena)
- {
- depctl.d32 = 0;
- depctl.b.epdis = 1;
- depctl.b.snak = 1;
- }
- else
- {
- depctl.d32 = 0;
- }
- USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPCTL, depctl.d32);
- USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPTSIZ, 0);
- USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
- }
- for (i = 0; i < pdev->cfg.dev_endpoints; i++)
- {
- USB_OTG_DEPCTL_TypeDef depctl;
- depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[i]->DOEPCTL);
- if (depctl.b.epena)
- {
- depctl.d32 = 0;
- depctl.b.epdis = 1;
- depctl.b.snak = 1;
- }
- else
- {
- depctl.d32 = 0;
- }
- USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPCTL, depctl.d32);
- USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPTSIZ, 0);
- USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
- }
- msk.d32 = 0;
- msk.b.txfifoundrn = 1;
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPMSK, msk.d32, msk.d32);
-
- if (pdev->cfg.dma_enable == 1)
- {
- dthrctl.d32 = 0;
- dthrctl.b.non_iso_thr_en = 1;
- dthrctl.b.iso_thr_en = 1;
- dthrctl.b.tx_thr_len = 64;
- dthrctl.b.rx_thr_en = 1;
- dthrctl.b.rx_thr_len = 64;
- USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DTHRCTL, dthrctl.d32);
- }
- USB_OTG_EnableDevInt(pdev);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_EnableDevInt : Enables the Device mode interrupts
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EnableDevInt(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_GINTMSK_TypeDef intmsk;
-
- intmsk.d32 = 0;
-
- /* Disable all interrupts. */
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, 0);
- /* Clear any pending interrupts */
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF);
- /* Enable the common interrupts */
- USB_OTG_EnableCommonInt(pdev);
-
- if (pdev->cfg.dma_enable == 0)
- {
- intmsk.b.rxstsqlvl = 1;
- }
-
- /* Enable interrupts matching to the Device mode ONLY */
- intmsk.b.usbsuspend = 1;
- intmsk.b.usbreset = 1;
- intmsk.b.enumdone = 1;
- intmsk.b.inepintr = 1;
- intmsk.b.outepintr = 1;
- intmsk.b.sofintr = 1;
-
- intmsk.b.incomplisoin = 1;
- intmsk.b.incomplisoout = 1;
-#ifdef VBUS_SENSING_ENABLED
- intmsk.b.sessreqintr = 1;
- intmsk.b.otgintr = 1;
-#endif
- USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_GetDeviceSpeed
-* Get the device speed from the device status register
-* @param None
-* @retval status
-*/
-enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_DSTS_TypeDef dsts;
- enum USB_OTG_SPEED speed = USB_SPEED_UNKNOWN;
-
-
- dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
-
- switch (dsts.b.enumspd)
- {
- case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
- speed = USB_SPEED_HIGH;
- break;
- case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
- case DSTS_ENUMSPD_FS_PHY_48MHZ:
- speed = USB_SPEED_FULL;
- break;
-
- case DSTS_ENUMSPD_LS_PHY_6MHZ:
- speed = USB_SPEED_LOW;
- break;
- }
-
- return speed;
-}
-/**
-* @brief enables EP0 OUT to receive SETUP packets and configures EP0
-* for transmitting packets
-* @param None
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EP0Activate(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_DSTS_TypeDef dsts;
- USB_OTG_DEPCTL_TypeDef diepctl;
- USB_OTG_DCTL_TypeDef dctl;
-
- dctl.d32 = 0;
- /* Read the Device Status and Endpoint 0 Control registers */
- dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
- diepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL);
- /* Set the MPS of the IN EP based on the enumeration speed */
- switch (dsts.b.enumspd)
- {
- case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
- case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
- case DSTS_ENUMSPD_FS_PHY_48MHZ:
- diepctl.b.mps = DEP0CTL_MPS_64;
- break;
- case DSTS_ENUMSPD_LS_PHY_6MHZ:
- diepctl.b.mps = DEP0CTL_MPS_8;
- break;
- }
- USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL, diepctl.d32);
- dctl.b.cgnpinnak = 1;
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, dctl.d32);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_EPActivate : Activates an EP
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EPActivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_DEPCTL_TypeDef depctl;
- USB_OTG_DAINT_TypeDef daintmsk;
- __IO uint32_t *addr;
-
-
- depctl.d32 = 0;
- daintmsk.d32 = 0;
- /* Read DEPCTLn register */
- if (ep->is_in == 1)
- {
- addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL;
- daintmsk.ep.in = 1 << ep->num;
- }
- else
- {
- addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL;
- daintmsk.ep.out = 1 << ep->num;
- }
- /* If the EP is already active don't change the EP Control
- * register. */
- depctl.d32 = USB_OTG_READ_REG32(addr);
- if (!depctl.b.usbactep)
- {
- depctl.b.mps = ep->maxpacket;
- depctl.b.eptype = ep->type;
- depctl.b.txfnum = ep->tx_fifo_num;
- depctl.b.setd0pid = 1;
- depctl.b.usbactep = 1;
- USB_OTG_WRITE_REG32(addr, depctl.d32);
- }
- /* Enable the Interrupt for this EP */
-#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
- if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID))
- {
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, 0, daintmsk.d32);
- }
- else
-#endif
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, 0, daintmsk.d32);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_EPDeactivate : Deactivates an EP
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_DEPCTL_TypeDef depctl;
- USB_OTG_DAINT_TypeDef daintmsk;
- __IO uint32_t *addr;
-
- depctl.d32 = 0;
- daintmsk.d32 = 0;
- /* Read DEPCTLn register */
- if (ep->is_in == 1)
- {
- addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL;
- daintmsk.ep.in = 1 << ep->num;
- }
- else
- {
- addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL;
- daintmsk.ep.out = 1 << ep->num;
- }
- depctl.b.usbactep = 0;
- USB_OTG_WRITE_REG32(addr, depctl.d32);
- /* Disable the Interrupt for this EP */
-
-#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
- if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID))
- {
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, daintmsk.d32, 0);
- }
- else
-#endif
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, daintmsk.d32, 0);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_EPStartXfer : Handle the setup for data xfer for an EP and
-* starts the xfer
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_DEPCTL_TypeDef depctl;
- USB_OTG_DEPXFRSIZ_TypeDef deptsiz;
- USB_OTG_DSTS_TypeDef dsts;
- uint32_t fifoemptymsk = 0;
-
- depctl.d32 = 0;
- deptsiz.d32 = 0;
- /* IN endpoint */
- if (ep->is_in == 1)
- {
- depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPCTL));
- deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ));
- /* Zero Length Packet? */
- if (ep->xfer_len == 0)
- {
- deptsiz.b.xfersize = 0;
- deptsiz.b.pktcnt = 1;
- }
- else
- {
- /* Program the transfer size and packet count
- * as follows: xfersize = N * maxpacket +
- * short_packet pktcnt = N + (short_packet
- * exist ? 1 : 0)
- */
- deptsiz.b.xfersize = ep->xfer_len;
- deptsiz.b.pktcnt = (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
-
- if (ep->type == EP_TYPE_ISOC)
- {
- deptsiz.b.mc = 1;
- }
- }
- USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ, deptsiz.d32);
-
- if (pdev->cfg.dma_enable == 1)
- {
- USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr);
- }
- else
- {
- if (ep->type != EP_TYPE_ISOC)
- {
- /* Enable the Tx FIFO Empty Interrupt for this EP */
- if (ep->xfer_len > 0)
- {
- fifoemptymsk = 1 << ep->num;
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk);
- }
- }
- }
-
-
- if (ep->type == EP_TYPE_ISOC)
- {
- dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
-
- if (((dsts.b.soffn)&0x1) == 0)
- {
- depctl.b.setd1pid = 1;
- }
- else
- {
- depctl.b.setd0pid = 1;
- }
- }
-
- /* EP enable, IN data in FIFO */
- depctl.b.cnak = 1;
- depctl.b.epena = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPCTL, depctl.d32);
-
- if (ep->type == EP_TYPE_ISOC)
- {
- USB_OTG_WritePacket(pdev, ep->xfer_buff, ep->num, ep->xfer_len);
- }
- }
- else
- {
- /* OUT endpoint */
- depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL));
- deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ));
- /* Program the transfer size and packet count as follows:
- * pktcnt = N
- * xfersize = N * maxpacket
- */
- if (ep->xfer_len == 0)
- {
- deptsiz.b.xfersize = ep->maxpacket;
- deptsiz.b.pktcnt = 1;
- }
- else
- {
- deptsiz.b.pktcnt = (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
- deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
- }
- USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32);
-
- if (pdev->cfg.dma_enable == 1)
- {
- USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr);
- }
-
- if (ep->type == EP_TYPE_ISOC)
- {
- if (ep->even_odd_frame)
- {
- depctl.b.setd1pid = 1;
- }
- else
- {
- depctl.b.setd0pid = 1;
- }
- }
- /* EP enable */
- depctl.b.cnak = 1;
- depctl.b.epena = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL, depctl.d32);
- }
- return status;
-}
-
-
-/**
-* @brief USB_OTG_EP0StartXfer : Handle the setup for a data xfer for EP0 and
-* starts the xfer
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_DEPCTL_TypeDef depctl;
- USB_OTG_DEP0XFRSIZ_TypeDef deptsiz;
- USB_OTG_INEPREGS *in_regs;
- uint32_t fifoemptymsk = 0;
-
- depctl.d32 = 0;
- deptsiz.d32 = 0;
- /* IN endpoint */
- if (ep->is_in == 1)
- {
- in_regs = pdev->regs.INEP_REGS[0];
- depctl.d32 = USB_OTG_READ_REG32(&in_regs->DIEPCTL);
- deptsiz.d32 = USB_OTG_READ_REG32(&in_regs->DIEPTSIZ);
- /* Zero Length Packet? */
- if (ep->xfer_len == 0)
- {
- deptsiz.b.xfersize = 0;
- deptsiz.b.pktcnt = 1;
-
- }
- else
- {
- if (ep->xfer_len > ep->maxpacket)
- {
- ep->xfer_len = ep->maxpacket;
- deptsiz.b.xfersize = ep->maxpacket;
- }
- else
- {
- deptsiz.b.xfersize = ep->xfer_len;
- }
- deptsiz.b.pktcnt = 1;
- }
- USB_OTG_WRITE_REG32(&in_regs->DIEPTSIZ, deptsiz.d32);
-
- if (pdev->cfg.dma_enable == 1)
- {
- USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr);
- }
-
- /* EP enable, IN data in FIFO */
- depctl.b.cnak = 1;
- depctl.b.epena = 1;
- USB_OTG_WRITE_REG32(&in_regs->DIEPCTL, depctl.d32);
-
-
-
- if (pdev->cfg.dma_enable == 0)
- {
- /* Enable the Tx FIFO Empty Interrupt for this EP */
- if (ep->xfer_len > 0)
- {
- {
- fifoemptymsk |= 1 << ep->num;
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk);
- }
- }
- }
- }
- else
- {
- /* OUT endpoint */
- depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
- deptsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ);
- /* Program the transfer size and packet count as follows:
- * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
- * pktcnt = N */
- if (ep->xfer_len == 0)
- {
- deptsiz.b.xfersize = ep->maxpacket;
- deptsiz.b.pktcnt = 1;
- }
- else
- {
- ep->xfer_len = ep->maxpacket;
- deptsiz.b.xfersize = ep->maxpacket;
- deptsiz.b.pktcnt = 1;
- }
- USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32);
- if (pdev->cfg.dma_enable == 1)
- {
- USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr);
- }
- /* EP enable */
- depctl.b.cnak = 1;
- depctl.b.epena = 1;
- USB_OTG_WRITE_REG32 (&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL), depctl.d32);
-
- }
- return status;
-}
-
-
-/**
-* @brief USB_OTG_EPSetStall : Set the EP STALL
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EPSetStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_DEPCTL_TypeDef depctl;
- __IO uint32_t *depctl_addr;
-
- depctl.d32 = 0;
- if (ep->is_in == 1)
- {
- depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
- depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
- /* set the disable and stall bits */
- if (depctl.b.epena)
- {
- depctl.b.epdis = 1;
- }
- depctl.b.stall = 1;
- USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
- }
- else
- {
- depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
- depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
- /* set the stall bit */
- depctl.b.stall = 1;
- USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
- }
- return status;
-}
-
-
-/**
-* @brief Clear the EP STALL
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EPClearStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_DEPCTL_TypeDef depctl;
- __IO uint32_t *depctl_addr;
-
- depctl.d32 = 0;
-
- if (ep->is_in == 1)
- {
- depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
- }
- else
- {
- depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
- }
- depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
- /* clear the stall bits */
- depctl.b.stall = 0;
- if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
- {
- depctl.b.setd0pid = 1; /* DATA0 */
- }
- USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_ReadDevAllOutEp_itr : returns OUT endpoint interrupt bits
-* @param pdev : Selected device
-* @retval OUT endpoint interrupt bits
-*/
-uint32_t USB_OTG_ReadDevAllOutEp_itr(USB_OTG_CORE_HANDLE *pdev)
-{
- uint32_t v;
- v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT);
- v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK);
- return ((v & 0xffff0000) >> 16);
-}
-
-
-/**
-* @brief USB_OTG_ReadDevOutEP_itr : returns Device OUT EP Interrupt register
-* @param pdev : Selected device
-* @param ep : end point number
-* @retval Device OUT EP Interrupt register
-*/
-uint32_t USB_OTG_ReadDevOutEP_itr(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum)
-{
- uint32_t v;
- v = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT);
- v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOEPMSK);
- return v;
-}
-
-
-/**
-* @brief USB_OTG_ReadDevAllInEPItr : Get int status register
-* @param pdev : Selected device
-* @retval int status register
-*/
-uint32_t USB_OTG_ReadDevAllInEPItr(USB_OTG_CORE_HANDLE *pdev)
-{
- uint32_t v;
- v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT);
- v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK);
- return (v & 0xffff);
-}
-
-/**
-* @brief configures EPO to receive SETUP packets
-* @param None
-* @retval : None
-*/
-void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_DEP0XFRSIZ_TypeDef doeptsize0;
- doeptsize0.d32 = 0;
- doeptsize0.b.supcnt = 3;
- doeptsize0.b.pktcnt = 1;
- doeptsize0.b.xfersize = 8 * 3;
- USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPTSIZ, doeptsize0.d32 );
-
- if (pdev->cfg.dma_enable == 1)
- {
- USB_OTG_DEPCTL_TypeDef doepctl;
- doepctl.d32 = 0;
- USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPDMA,
- (uint32_t)&pdev->dev.setup_packet);
-
- /* EP enable */
- doepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[0]->DOEPCTL);
- doepctl.b.epena = 1;
- doepctl.d32 = 0x80008000;
- USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPCTL, doepctl.d32);
- }
-}
-
-/**
-* @brief USB_OTG_RemoteWakeup : active remote wakeup signalling
-* @param None
-* @retval : None
-*/
-void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev)
-{
-
- USB_OTG_DCTL_TypeDef dctl;
- USB_OTG_DSTS_TypeDef dsts;
- USB_OTG_PCGCCTL_TypeDef power;
-
- if (pdev->dev.DevRemoteWakeup)
- {
- dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
- if(dsts.b.suspsts == 1)
- {
- if(pdev->cfg.low_power)
- {
- /* un-gate USB Core clock */
- power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL);
- power.b.gatehclk = 0;
- power.b.stoppclk = 0;
- USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
- }
- /* active Remote wakeup signaling */
- dctl.d32 = 0;
- dctl.b.rmtwkupsig = 1;
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, 0, dctl.d32);
- USB_OTG_BSP_mDelay(5);
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 );
- }
- }
-}
-
-
-/**
-* @brief USB_OTG_UngateClock : active USB Core clock
-* @param None
-* @retval : None
-*/
-void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev)
-{
- if(pdev->cfg.low_power)
- {
-
- USB_OTG_DSTS_TypeDef dsts;
- USB_OTG_PCGCCTL_TypeDef power;
-
- dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
-
- if(dsts.b.suspsts == 1)
- {
- /* un-gate USB Core clock */
- power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL);
- power.b.gatehclk = 0;
- power.b.stoppclk = 0;
- USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
-
- }
- }
-}
-
-/**
-* @brief Stop the device and clean up fifo's
-* @param None
-* @retval : None
-*/
-void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev)
-{
- uint32_t i;
-
- pdev->dev.device_status = 1;
-
- for (i = 0; i < pdev->cfg.dev_endpoints ; i++)
- {
- USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
- USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
- }
-
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 );
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 );
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 );
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF );
-
- /* Flush the FIFO */
- USB_OTG_FlushRxFifo(pdev);
- USB_OTG_FlushTxFifo(pdev , 0x10 );
-}
-
-/**
-* @brief returns the EP Status
-* @param pdev : Selected device
-* ep : endpoint structure
-* @retval : EP status
-*/
-
-uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep)
-{
- USB_OTG_DEPCTL_TypeDef depctl;
- __IO uint32_t *depctl_addr;
- uint32_t Status = 0;
-
- depctl.d32 = 0;
- if (ep->is_in == 1)
- {
- depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
- depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
-
- if (depctl.b.stall == 1)
- Status = USB_OTG_EP_TX_STALL;
- else if (depctl.b.naksts == 1)
- Status = USB_OTG_EP_TX_NAK;
- else
- Status = USB_OTG_EP_TX_VALID;
-
- }
- else
- {
- depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
- depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
- if (depctl.b.stall == 1)
- Status = USB_OTG_EP_RX_STALL;
- else if (depctl.b.naksts == 1)
- Status = USB_OTG_EP_RX_NAK;
- else
- Status = USB_OTG_EP_RX_VALID;
- }
-
- /* Return the current status */
- return Status;
-}
-
-/**
-* @brief Set the EP Status
-* @param pdev : Selected device
-* Status : new Status
-* ep : EP structure
-* @retval : None
-*/
-void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status)
-{
- USB_OTG_DEPCTL_TypeDef depctl;
- __IO uint32_t *depctl_addr;
-
- depctl.d32 = 0;
-
- /* Process for IN endpoint */
- if (ep->is_in == 1)
- {
- depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
- depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
-
- if (Status == USB_OTG_EP_TX_STALL)
- {
- USB_OTG_EPSetStall(pdev, ep); return;
- }
- else if (Status == USB_OTG_EP_TX_NAK)
- depctl.b.snak = 1;
- else if (Status == USB_OTG_EP_TX_VALID)
- {
- if (depctl.b.stall == 1)
- {
- ep->even_odd_frame = 0;
- USB_OTG_EPClearStall(pdev, ep);
- return;
- }
- depctl.b.cnak = 1;
- depctl.b.usbactep = 1;
- depctl.b.epena = 1;
- }
- else if (Status == USB_OTG_EP_TX_DIS)
- depctl.b.usbactep = 0;
- }
- else /* Process for OUT endpoint */
- {
- depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
- depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
-
- if (Status == USB_OTG_EP_RX_STALL) {
- depctl.b.stall = 1;
- }
- else if (Status == USB_OTG_EP_RX_NAK)
- depctl.b.snak = 1;
- else if (Status == USB_OTG_EP_RX_VALID)
- {
- if (depctl.b.stall == 1)
- {
- ep->even_odd_frame = 0;
- USB_OTG_EPClearStall(pdev, ep);
- return;
- }
- depctl.b.cnak = 1;
- depctl.b.usbactep = 1;
- depctl.b.epena = 1;
- }
- else if (Status == USB_OTG_EP_RX_DIS)
- {
- depctl.b.usbactep = 0;
- }
- }
-
- USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
-}
-
-#endif
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_core.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Header of the Core Layer
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_CORE_H__
-#define __USB_CORE_H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_conf.h"
-#include "usb_regs.h"
-#include "usb_defines.h"
-
-
-/** @addtogroup USB_OTG_DRIVER
- * @{
- */
-
-/** @defgroup USB_CORE
- * @brief usb otg driver core layer
- * @{
- */
-
-
-/** @defgroup USB_CORE_Exported_Defines
- * @{
- */
-
-#define USB_OTG_EP0_IDLE 0
-#define USB_OTG_EP0_SETUP 1
-#define USB_OTG_EP0_DATA_IN 2
-#define USB_OTG_EP0_DATA_OUT 3
-#define USB_OTG_EP0_STATUS_IN 4
-#define USB_OTG_EP0_STATUS_OUT 5
-#define USB_OTG_EP0_STALL 6
-
-#define USB_OTG_EP_TX_DIS 0x0000
-#define USB_OTG_EP_TX_STALL 0x0010
-#define USB_OTG_EP_TX_NAK 0x0020
-#define USB_OTG_EP_TX_VALID 0x0030
-
-#define USB_OTG_EP_RX_DIS 0x0000
-#define USB_OTG_EP_RX_STALL 0x1000
-#define USB_OTG_EP_RX_NAK 0x2000
-#define USB_OTG_EP_RX_VALID 0x3000
-/**
- * @}
- */
-#define MAX_DATA_LENGTH 0xFF
-
-/** @defgroup USB_CORE_Exported_Types
- * @{
- */
-
-
-typedef enum {
- USB_OTG_OK = 0,
- USB_OTG_FAIL
-}USB_OTG_STS;
-
-typedef enum {
- HC_IDLE = 0,
- HC_XFRC,
- HC_HALTED,
- HC_NAK,
- HC_NYET,
- HC_STALL,
- HC_XACTERR,
- HC_BBLERR,
- HC_DATATGLERR,
-}HC_STATUS;
-
-typedef enum {
- URB_IDLE = 0,
- URB_DONE,
- URB_NOTREADY,
- URB_ERROR,
- URB_STALL
-}URB_STATE;
-
-typedef enum {
- CTRL_START = 0,
- CTRL_XFRC,
- CTRL_HALTED,
- CTRL_NAK,
- CTRL_STALL,
- CTRL_XACTERR,
- CTRL_BBLERR,
- CTRL_DATATGLERR,
- CTRL_FAIL
-}CTRL_STATUS;
-
-
-typedef struct USB_OTG_hc
-{
- uint8_t dev_addr ;
- uint8_t ep_num;
- uint8_t ep_is_in;
- uint8_t speed;
- uint8_t do_ping;
- uint8_t ep_type;
- uint16_t max_packet;
- uint8_t data_pid;
- uint8_t *xfer_buff;
- uint32_t xfer_len;
- uint32_t xfer_count;
- uint8_t toggle_in;
- uint8_t toggle_out;
- uint32_t dma_addr;
-}
-USB_OTG_HC , *PUSB_OTG_HC;
-
-typedef struct USB_OTG_ep
-{
- uint8_t num;
- uint8_t is_in;
- uint8_t is_stall;
- uint8_t type;
- uint8_t data_pid_start;
- uint8_t even_odd_frame;
- uint16_t tx_fifo_num;
- uint32_t maxpacket;
- /* transaction level variables*/
- uint8_t *xfer_buff;
- uint32_t dma_addr;
- uint32_t xfer_len;
- uint32_t xfer_count;
- /* Transfer level variables*/
- uint32_t rem_data_len;
- uint32_t total_data_len;
- uint32_t ctl_data_len;
-
-}
-
-USB_OTG_EP , *PUSB_OTG_EP;
-
-
-
-typedef struct USB_OTG_core_cfg
-{
- uint8_t host_channels;
- uint8_t dev_endpoints;
- uint8_t speed;
- uint8_t dma_enable;
- uint16_t mps;
- uint16_t TotalFifoSize;
- uint8_t phy_itface;
- uint8_t Sof_output;
- uint8_t low_power;
- uint8_t coreID;
-
-}
-USB_OTG_CORE_CFGS, *PUSB_OTG_CORE_CFGS;
-
-
-
-typedef struct usb_setup_req {
-
- uint8_t bmRequest;
- uint8_t bRequest;
- uint16_t wValue;
- uint16_t wIndex;
- uint16_t wLength;
-} USB_SETUP_REQ;
-
-typedef struct _Device_TypeDef
-{
- uint8_t *(*GetDeviceDescriptor)( uint8_t speed , uint16_t *length);
- uint8_t *(*GetLangIDStrDescriptor)( uint8_t speed , uint16_t *length);
- uint8_t *(*GetManufacturerStrDescriptor)( uint8_t speed , uint16_t *length);
- uint8_t *(*GetProductStrDescriptor)( uint8_t speed , uint16_t *length);
- uint8_t *(*GetSerialStrDescriptor)( uint8_t speed , uint16_t *length);
- uint8_t *(*GetConfigurationStrDescriptor)( uint8_t speed , uint16_t *length);
- uint8_t *(*GetInterfaceStrDescriptor)( uint8_t speed , uint16_t *length);
-} USBD_DEVICE, *pUSBD_DEVICE;
-
-typedef struct USB_OTG_hPort
-{
- void (*Disconnect) (void *phost);
- void (*Connect) (void *phost);
- uint8_t ConnStatus;
- uint8_t DisconnStatus;
- uint8_t ConnHandled;
- uint8_t DisconnHandled;
-} USB_OTG_hPort_TypeDef;
-
-typedef struct _Device_cb
-{
- uint8_t (*Init) (void *pdev , uint8_t cfgidx);
- uint8_t (*DeInit) (void *pdev , uint8_t cfgidx);
- /* Control Endpoints*/
- uint8_t (*Setup) (void *pdev , USB_SETUP_REQ *req);
- uint8_t (*EP0_TxSent) (void *pdev );
- uint8_t (*EP0_RxReady) (void *pdev );
- /* Class Specific Endpoints*/
- uint8_t (*DataIn) (void *pdev , uint8_t epnum);
- uint8_t (*DataOut) (void *pdev , uint8_t epnum);
- uint8_t (*SOF) (void *pdev);
- uint8_t (*IsoINIncomplete) (void *pdev);
- uint8_t (*IsoOUTIncomplete) (void *pdev);
-
- uint8_t *(*GetConfigDescriptor)( uint8_t speed , uint16_t *length);
-#ifdef USB_OTG_HS_CORE
- uint8_t *(*GetOtherConfigDescriptor)( uint8_t speed , uint16_t *length);
-#endif
-
-#ifdef USB_SUPPORT_USER_STRING_DESC
- uint8_t *(*GetUsrStrDescriptor)( uint8_t speed ,uint8_t index, uint16_t *length);
-#endif
-
-} USBD_Class_cb_TypeDef;
-
-
-
-typedef struct _USBD_USR_PROP
-{
- void (*Init)(void);
- void (*DeviceReset)(uint8_t speed);
- void (*DeviceConfigured)(void);
- void (*DeviceSuspended)(void);
- void (*DeviceResumed)(void);
-
- void (*DeviceConnected)(void);
- void (*DeviceDisconnected)(void);
-
-}
-USBD_Usr_cb_TypeDef;
-
-typedef struct _DCD
-{
- uint8_t device_config;
- uint8_t device_state;
- uint8_t device_status;
- uint8_t device_address;
- uint32_t DevRemoteWakeup;
- USB_OTG_EP in_ep [USB_OTG_MAX_TX_FIFOS];
- USB_OTG_EP out_ep [USB_OTG_MAX_TX_FIFOS];
- uint8_t setup_packet [8*3];
- USBD_Class_cb_TypeDef *class_cb;
- USBD_Usr_cb_TypeDef *usr_cb;
- USBD_DEVICE *usr_device;
- uint8_t *pConfig_descriptor;
- }
-DCD_DEV , *DCD_PDEV;
-
-
-typedef struct _HCD
-{
- uint8_t Rx_Buffer [MAX_DATA_LENGTH];
- __IO uint32_t ConnSts;
- __IO uint32_t ErrCnt[USB_OTG_MAX_TX_FIFOS];
- __IO uint32_t XferCnt[USB_OTG_MAX_TX_FIFOS];
- __IO HC_STATUS HC_Status[USB_OTG_MAX_TX_FIFOS];
- __IO URB_STATE URB_State[USB_OTG_MAX_TX_FIFOS];
- USB_OTG_HC hc [USB_OTG_MAX_TX_FIFOS];
- uint16_t channel [USB_OTG_MAX_TX_FIFOS];
- USB_OTG_hPort_TypeDef *port_cb;
-}
-HCD_DEV , *USB_OTG_USBH_PDEV;
-
-
-typedef struct _OTG
-{
- uint8_t OTG_State;
- uint8_t OTG_PrevState;
- uint8_t OTG_Mode;
-}
-OTG_DEV , *USB_OTG_USBO_PDEV;
-
-typedef struct USB_OTG_handle
-{
- USB_OTG_CORE_CFGS cfg;
- USB_OTG_CORE_REGS regs;
-#ifdef USE_DEVICE_MODE
- DCD_DEV dev;
-#endif
-#ifdef USE_HOST_MODE
- HCD_DEV host;
-#endif
-#ifdef USE_OTG_MODE
- OTG_DEV otg;
-#endif
-}
-USB_OTG_CORE_HANDLE , *PUSB_OTG_CORE_HANDLE;
-
-/**
- * @}
- */
-
-
-/** @defgroup USB_CORE_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USB_CORE_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_CORE_Exported_FunctionsPrototype
- * @{
- */
-
-
-USB_OTG_STS USB_OTG_CoreInit (USB_OTG_CORE_HANDLE *pdev);
-USB_OTG_STS USB_OTG_SelectCore (USB_OTG_CORE_HANDLE *pdev,
- USB_OTG_CORE_ID_TypeDef coreID);
-USB_OTG_STS USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE *pdev);
-USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev);
-void* USB_OTG_ReadPacket (USB_OTG_CORE_HANDLE *pdev ,
- uint8_t *dest,
- uint16_t len);
-USB_OTG_STS USB_OTG_WritePacket (USB_OTG_CORE_HANDLE *pdev ,
- uint8_t *src,
- uint8_t ch_ep_num,
- uint16_t len);
-USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num);
-USB_OTG_STS USB_OTG_FlushRxFifo (USB_OTG_CORE_HANDLE *pdev);
-
-uint32_t USB_OTG_ReadCoreItr (USB_OTG_CORE_HANDLE *pdev);
-uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev);
-uint8_t USB_OTG_IsHostMode (USB_OTG_CORE_HANDLE *pdev);
-uint8_t USB_OTG_IsDeviceMode (USB_OTG_CORE_HANDLE *pdev);
-uint32_t USB_OTG_GetMode (USB_OTG_CORE_HANDLE *pdev);
-USB_OTG_STS USB_OTG_PhyInit (USB_OTG_CORE_HANDLE *pdev);
-USB_OTG_STS USB_OTG_SetCurrentMode (USB_OTG_CORE_HANDLE *pdev,
- uint8_t mode);
-
-/*********************** HOST APIs ********************************************/
-#ifdef USE_HOST_MODE
-USB_OTG_STS USB_OTG_CoreInitHost (USB_OTG_CORE_HANDLE *pdev);
-USB_OTG_STS USB_OTG_EnableHostInt (USB_OTG_CORE_HANDLE *pdev);
-USB_OTG_STS USB_OTG_HC_Init (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num);
-USB_OTG_STS USB_OTG_HC_Halt (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num);
-USB_OTG_STS USB_OTG_HC_StartXfer (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num);
-USB_OTG_STS USB_OTG_HC_DoPing (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num);
-uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev);
-uint32_t USB_OTG_ResetPort (USB_OTG_CORE_HANDLE *pdev);
-uint32_t USB_OTG_ReadHPRT0 (USB_OTG_CORE_HANDLE *pdev);
-void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state);
-void USB_OTG_InitFSLSPClkSel (USB_OTG_CORE_HANDLE *pdev ,uint8_t freq);
-uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) ;
-void USB_OTG_StopHost (USB_OTG_CORE_HANDLE *pdev);
-#endif
-/********************* DEVICE APIs ********************************************/
-#ifdef USE_DEVICE_MODE
-USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev);
-USB_OTG_STS USB_OTG_EnableDevInt (USB_OTG_CORE_HANDLE *pdev);
-uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev);
-enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev);
-USB_OTG_STS USB_OTG_EP0Activate (USB_OTG_CORE_HANDLE *pdev);
-USB_OTG_STS USB_OTG_EPActivate (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
-USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
-USB_OTG_STS USB_OTG_EPStartXfer (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
-USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
-USB_OTG_STS USB_OTG_EPSetStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
-USB_OTG_STS USB_OTG_EPClearStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
-uint32_t USB_OTG_ReadDevAllOutEp_itr (USB_OTG_CORE_HANDLE *pdev);
-uint32_t USB_OTG_ReadDevOutEP_itr (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum);
-uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev);
-void USB_OTG_InitDevSpeed (USB_OTG_CORE_HANDLE *pdev , uint8_t speed);
-uint8_t USBH_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev);
-void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev);
-void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev);
-void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev);
-void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev);
-void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status);
-uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep);
-#endif
-/**
- * @}
- */
-
-#endif /* __USB_CORE_H__ */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_conf.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief USB Device configuration file
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_CONF__H__
-#define __USBD_CONF__H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4_discovery.h"
-
-/** @defgroup USB_CONF_Exported_Defines
- * @{
- */
-
-
-#define USBD_CFG_MAX_NUM 1
-#define USBD_ITF_MAX_NUM 1
-
-#define USB_MAX_STR_DESC_SIZ 64
-
-
-
-#define USBD_DYNAMIC_DESCRIPTOR_CHANGE_ENABLED
-
-/** @defgroup USB_String_Descriptors
- * @{
- */
-
-
-/** @defgroup USB_HID_Class_Layer_Parameter
- * @{
- */
-#define HID_IN_EP 0x81
-#define HID_OUT_EP 0x01
-
-#define HID_IN_PACKET 4
-#define HID_OUT_PACKET 4
-
-/**
- * @}
- */
-/** @defgroup USB_CONF_Exported_Types
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_CONF_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_CONF_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_CONF_Exported_FunctionsPrototype
- * @{
- */
-/**
- * @}
- */
-
-
-#endif //__USBD_CONF__H__
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_desc.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief This file provides the USBD descriptors and string formating method.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_core.h"
-#include "usbd_desc.h"
-#include "usbd_req.h"
-#include "usbd_conf.h"
-#include "usb_regs.h"
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup USBD_DESC
- * @brief USBD descriptors module
- * @{
- */
-
-/** @defgroup USBD_DESC_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_DESC_Private_Defines
- * @{
- */
-
-#define USBD_VID 0x0483
-#define USBD_PID 0x5710
-
-#define USBD_LANGID_STRING 0x409
-#define USBD_MANUFACTURER_STRING "STMicroelectronics"
-
-#define USBD_PRODUCT_HS_STRING "Joystick in HS mode"
-#define USBD_SERIALNUMBER_HS_STRING "00000000011B"
-
-#define USBD_PRODUCT_FS_STRING "Joystick in FS Mode"
-#define USBD_SERIALNUMBER_FS_STRING "00000000011C"
-
-#define USBD_CONFIGURATION_HS_STRING "HID Config"
-#define USBD_INTERFACE_HS_STRING "HID Interface"
-
-#define USBD_CONFIGURATION_FS_STRING "HID Config"
-#define USBD_INTERFACE_FS_STRING "HID Interface"
-/**
- * @}
- */
-
-
-/** @defgroup USBD_DESC_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_DESC_Private_Variables
- * @{
- */
-
-USBD_DEVICE USR_desc =
-{
- USBD_USR_DeviceDescriptor,
- USBD_USR_LangIDStrDescriptor,
- USBD_USR_ManufacturerStrDescriptor,
- USBD_USR_ProductStrDescriptor,
- USBD_USR_SerialStrDescriptor,
- USBD_USR_ConfigStrDescriptor,
- USBD_USR_InterfaceStrDescriptor,
-
-};
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-/* USB Standard Device Descriptor */
-__ALIGN_BEGIN uint8_t USBD_DeviceDesc[USB_SIZ_DEVICE_DESC] __ALIGN_END =
- {
- 0x12, /*bLength */
- USB_DEVICE_DESCRIPTOR_TYPE, /*bDescriptorType*/
- 0x00, /*bcdUSB */
- 0x02,
- 0x00, /*bDeviceClass*/
- 0x00, /*bDeviceSubClass*/
- 0x00, /*bDeviceProtocol*/
- USB_OTG_MAX_EP0_SIZE, /*bMaxPacketSize*/
- LOBYTE(USBD_VID), /*idVendor*/
- HIBYTE(USBD_VID), /*idVendor*/
- LOBYTE(USBD_PID), /*idVendor*/
- HIBYTE(USBD_PID), /*idVendor*/
- 0x00, /*bcdDevice rel. 2.00*/
- 0x02,
- USBD_IDX_MFC_STR, /*Index of manufacturer string*/
- USBD_IDX_PRODUCT_STR, /*Index of product string*/
- USBD_IDX_SERIAL_STR, /*Index of serial number string*/
- USBD_CFG_MAX_NUM /*bNumConfigurations*/
- } ; /* USB_DeviceDescriptor */
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-/* USB Standard Device Descriptor */
-__ALIGN_BEGIN uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
-{
- USB_LEN_DEV_QUALIFIER_DESC,
- USB_DESC_TYPE_DEVICE_QUALIFIER,
- 0x00,
- 0x02,
- 0x00,
- 0x00,
- 0x00,
- 0x40,
- 0x01,
- 0x00,
-};
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-/* USB Standard Device Descriptor */
-__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID] __ALIGN_END =
-{
- USB_SIZ_STRING_LANGID,
- USB_DESC_TYPE_STRING,
- LOBYTE(USBD_LANGID_STRING),
- HIBYTE(USBD_LANGID_STRING),
-};
-/**
- * @}
- */
-
-
-/** @defgroup USBD_DESC_Private_FunctionPrototypes
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_DESC_Private_Functions
- * @{
- */
-
-/**
-* @brief USBD_USR_DeviceDescriptor
-* return the device descriptor
-* @param speed : current device speed
-* @param length : pointer to data length variable
-* @retval pointer to descriptor buffer
-*/
-uint8_t * USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length)
-{
- *length = sizeof(USBD_DeviceDesc);
- return USBD_DeviceDesc;
-}
-
-/**
-* @brief USBD_USR_LangIDStrDescriptor
-* return the LangID string descriptor
-* @param speed : current device speed
-* @param length : pointer to data length variable
-* @retval pointer to descriptor buffer
-*/
-uint8_t * USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length)
-{
- *length = sizeof(USBD_LangIDDesc);
- return USBD_LangIDDesc;
-}
-
-
-/**
-* @brief USBD_USR_ProductStrDescriptor
-* return the product string descriptor
-* @param speed : current device speed
-* @param length : pointer to data length variable
-* @retval pointer to descriptor buffer
-*/
-uint8_t * USBD_USR_ProductStrDescriptor( uint8_t speed , uint16_t *length)
-{
-
-
- if(speed == 0)
- {
- USBD_GetString (USBD_PRODUCT_HS_STRING, USBD_StrDesc, length);
- }
- else
- {
- USBD_GetString (USBD_PRODUCT_FS_STRING, USBD_StrDesc, length);
- }
- return USBD_StrDesc;
-}
-
-/**
-* @brief USBD_USR_ManufacturerStrDescriptor
-* return the manufacturer string descriptor
-* @param speed : current device speed
-* @param length : pointer to data length variable
-* @retval pointer to descriptor buffer
-*/
-uint8_t * USBD_USR_ManufacturerStrDescriptor( uint8_t speed , uint16_t *length)
-{
- USBD_GetString (USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
- return USBD_StrDesc;
-}
-
-/**
-* @brief USBD_USR_SerialStrDescriptor
-* return the serial number string descriptor
-* @param speed : current device speed
-* @param length : pointer to data length variable
-* @retval pointer to descriptor buffer
-*/
-uint8_t * USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length)
-{
- if(speed == USB_OTG_SPEED_HIGH)
- {
- USBD_GetString (USBD_SERIALNUMBER_HS_STRING, USBD_StrDesc, length);
- }
- else
- {
- USBD_GetString (USBD_SERIALNUMBER_FS_STRING, USBD_StrDesc, length);
- }
- return USBD_StrDesc;
-}
-
-/**
-* @brief USBD_USR_ConfigStrDescriptor
-* return the configuration string descriptor
-* @param speed : current device speed
-* @param length : pointer to data length variable
-* @retval pointer to descriptor buffer
-*/
-uint8_t * USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length)
-{
- if(speed == USB_OTG_SPEED_HIGH)
- {
- USBD_GetString (USBD_CONFIGURATION_HS_STRING, USBD_StrDesc, length);
- }
- else
- {
- USBD_GetString (USBD_CONFIGURATION_FS_STRING, USBD_StrDesc, length);
- }
- return USBD_StrDesc;
-}
-
-
-/**
-* @brief USBD_USR_InterfaceStrDescriptor
-* return the interface string descriptor
-* @param speed : current device speed
-* @param length : pointer to data length variable
-* @retval pointer to descriptor buffer
-*/
-uint8_t * USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length)
-{
- if(speed == 0)
- {
- USBD_GetString (USBD_INTERFACE_HS_STRING, USBD_StrDesc, length);
- }
- else
- {
- USBD_GetString (USBD_INTERFACE_FS_STRING, USBD_StrDesc, length);
- }
- return USBD_StrDesc;
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_desc.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief header file for the usbd_desc.c file
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-
-#ifndef __USB_DESC_H
-#define __USB_DESC_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_def.h"
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USB_DESC
- * @brief general defines for the usb device library file
- * @{
- */
-
-/** @defgroup USB_DESC_Exported_Defines
- * @{
- */
-#define USB_DEVICE_DESCRIPTOR_TYPE 0x01
-#define USB_CONFIGURATION_DESCRIPTOR_TYPE 0x02
-#define USB_STRING_DESCRIPTOR_TYPE 0x03
-#define USB_INTERFACE_DESCRIPTOR_TYPE 0x04
-#define USB_ENDPOINT_DESCRIPTOR_TYPE 0x05
-#define USB_SIZ_DEVICE_DESC 18
-#define USB_SIZ_STRING_LANGID 4
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_DESC_Exported_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_DESC_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBD_DESC_Exported_Variables
- * @{
- */
-extern uint8_t USBD_DeviceDesc [USB_SIZ_DEVICE_DESC];
-extern uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ];
-extern uint8_t USBD_OtherSpeedCfgDesc[USB_LEN_CFG_DESC];
-extern uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC];
-extern uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID];
-extern USBD_DEVICE USR_desc;
-/**
- * @}
- */
-
-/** @defgroup USBD_DESC_Exported_FunctionsPrototype
- * @{
- */
-
-
-uint8_t * USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length);
-uint8_t * USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length);
-uint8_t * USBD_USR_ManufacturerStrDescriptor ( uint8_t speed , uint16_t *length);
-uint8_t * USBD_USR_ProductStrDescriptor ( uint8_t speed , uint16_t *length);
-uint8_t * USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length);
-uint8_t * USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length);
-uint8_t * USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length);
-
-#ifdef USB_SUPPORT_USER_STRING_DESC
-uint8_t * USBD_USR_USRStringDesc (uint8_t speed, uint8_t idx , uint16_t *length);
-#endif /* USB_SUPPORT_USER_STRING_DESC */
-
-/**
- * @}
- */
-
-#endif /* __USBD_DESC_H */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_usr.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief This file includes the user application layer
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_usr.h"
-#include "usbd_ioreq.h"
-
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
-* @{
-*/
-
-/** @defgroup USBD_USR
-* @brief This file includes the user application layer
-* @{
-*/
-
-/** @defgroup USBD_USR_Private_TypesDefinitions
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USBD_USR_Private_Defines
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USBD_USR_Private_Macros
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USBD_USR_Private_Variables
-* @{
-*/
-
-USBD_Usr_cb_TypeDef USR_cb =
-{
- USBD_USR_Init,
- USBD_USR_DeviceReset,
- USBD_USR_DeviceConfigured,
- USBD_USR_DeviceSuspended,
- USBD_USR_DeviceResumed,
-
- USBD_USR_DeviceConnected,
- USBD_USR_DeviceDisconnected,
-
-
-};
-
-
-
-/**
-* @}
-*/
-
-/** @defgroup USBD_USR_Private_Constants
-* @{
-*/
-
-/**
-* @}
-*/
-
-
-
-/** @defgroup USBD_USR_Private_FunctionPrototypes
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USBD_USR_Private_Functions
-* @{
-*/
-
-/**
-* @brief USBD_USR_Init
-* Displays the message on LCD for host lib initialization
-* @param None
-* @retval None
-*/
-void USBD_USR_Init(void)
-{
- /* Setup SysTick Timer for 40 msec interrupts
- This interrupt is used to probe the joystick */
- if (SysTick_Config(SystemCoreClock / 24))
- {
- /* Capture error */
- while (1);
- }
-}
-
-/**
-* @brief USBD_USR_DeviceReset
-* Displays the message on LCD on device Reset Event
-* @param speed : device speed
-* @retval None
-*/
-void USBD_USR_DeviceReset(uint8_t speed )
-{
- switch (speed)
- {
- case USB_OTG_SPEED_HIGH:
- break;
-
- case USB_OTG_SPEED_FULL:
- break;
- default:
- break;
-
- }
-}
-
-
-/**
-* @brief USBD_USR_DeviceConfigured
-* Displays the message on LCD on device configuration Event
-* @param None
-* @retval Staus
-*/
-void USBD_USR_DeviceConfigured (void)
-{
-}
-
-
-/**
-* @brief USBD_USR_DeviceConnected
-* Displays the message on LCD on device connection Event
-* @param None
-* @retval Staus
-*/
-void USBD_USR_DeviceConnected (void)
-{
-}
-
-
-/**
-* @brief USBD_USR_DeviceDisonnected
-* Displays the message on LCD on device disconnection Event
-* @param None
-* @retval Staus
-*/
-void USBD_USR_DeviceDisconnected (void)
-{
-}
-
-/**
-* @brief USBD_USR_DeviceSuspended
-* Displays the message on LCD on device suspend Event
-* @param None
-* @retval None
-*/
-void USBD_USR_DeviceSuspended(void)
-{
- /* Users can do their application actions here for the USB-Reset */
-}
-
-
-/**
-* @brief USBD_USR_DeviceResumed
-* Displays the message on LCD on device resume Event
-* @param None
-* @retval None
-*/
-void USBD_USR_DeviceResumed(void)
-{
- /* Users can do their application actions here for the USB-Reset */
-}
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+++ /dev/null
-LIB = libSTM32F4xx_StdPeriph_Driver.a
-
-CC = arm-none-eabi-gcc
-AR = arm-none-eabi-ar
-RANLIB = arm-none-eabi-ranlib
-
-CFLAGS = -Wall -O2 -mlittle-endian -mthumb
-CFLAGS += -mcpu=cortex-m4 -ffreestanding -nostdlib
-CFLAGS += -I../inc -I../inc/device_support -I../inc/core_support
-
-SRCS = \
-../src/misc.c \
-../src/stm32f4xx_adc.c \
-../src/stm32f4xx_can.c \
-../src/stm32f4xx_crc.c \
-../src/stm32f4xx_cryp_aes.c \
-../src/stm32f4xx_cryp_des.c \
-../src/stm32f4xx_cryp_tdes.c \
-../src/stm32f4xx_cryp_des.c \
-../src/stm32f4xx_dac.c \
-../src/stm32f4xx_dbgmcu.c \
-../src/stm32f4xx_dcmi.c \
-../src/stm32f4xx_dma.c \
-../src/stm32f4xx_exti.c \
-../src/stm32f4xx_flash.c \
-../src/stm32f4xx_fsmc.c \
-../src/stm32f4xx_gpio.c \
-../src/stm32f4xx_hash_md5.c \
-../src/stm32f4xx_hash_sha1.c \
-../src/stm32f4xx_hash.c \
-../src/stm32f4xx_i2c.c \
-../src/stm32f4xx_iwdg.c \
-../src/stm32f4xx_pwr.c \
-../src/stm32f4xx_rcc.c \
-../src/stm32f4xx_rng.c \
-../src/stm32f4xx_rtc.c \
-../src/stm32f4xx_sdio.c \
-../src/stm32f4xx_spi.c \
-../src/stm32f4xx_syscfg.c \
-../src/stm32f4xx_tim.c \
-../src/stm32f4xx_usart.c \
-../src/stm32f4xx_wwdg.c \
-#../inc/core_support/core_cm4.c
-
-OBJS = $(SRCS:.c=.o)
-
-all: $(LIB)
-
-$(LIB): $(OBJS)
- $(AR) -r $(LIB) $(OBJS)
- $(RANLIB) $(LIB)
-
-%.o : %.c
- $(CC) $(CFLAGS) -c -o $@ $^
-
-clean:
- -rm -f $(OBJS)
- -rm -f $(LIB)
-
-.PHONY: all clean
+++ /dev/null
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010 ARM Limited. All rights reserved.
-*
-* $Date: 11. November 2010
-* $Revision: V1.0.2
-*
-* Project: CMSIS DSP Library
-* Title: arm_common_tables.h
-*
-* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
-*
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Version 1.0.2 2010/11/11
-* Documentation updated.
-*
-* Version 1.0.1 2010/10/05
-* Production release and review comments incorporated.
-*
-* Version 1.0.0 2010/09/20
-* Production release and review comments incorporated.
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_COMMON_TABLES_H
-#define _ARM_COMMON_TABLES_H
-
-#include "arm_math.h"
-
-extern uint16_t armBitRevTable[256];
-extern q15_t armRecipTableQ15[64];
-extern q31_t armRecipTableQ31[64];
-extern const q31_t realCoefAQ31[1024];
-extern const q31_t realCoefBQ31[1024];
-
-#endif /* ARM_COMMON_TABLES_H */
+++ /dev/null
-/* ----------------------------------------------------------------------
- * Copyright (C) 2010 ARM Limited. All rights reserved.
- *
- * $Date: 15. July 2011
- * $Revision: V1.0.10
- *
- * Project: CMSIS DSP Library
- * Title: arm_math.h
- *
- * Description: Public header file for CMSIS DSP Library
- *
- * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
- *
- * Version 1.0.10 2011/7/15
- * Big Endian support added and Merged M0 and M3/M4 Source code.
- *
- * Version 1.0.3 2010/11/29
- * Re-organized the CMSIS folders and updated documentation.
- *
- * Version 1.0.2 2010/11/11
- * Documentation updated.
- *
- * Version 1.0.1 2010/10/05
- * Production release and review comments incorporated.
- *
- * Version 1.0.0 2010/09/20
- * Production release and review comments incorporated.
- * -------------------------------------------------------------------- */
-
-/**
- \mainpage CMSIS DSP Software Library
- *
- * <b>Introduction</b>
- *
- * This user manual describes the CMSIS DSP software library,
- * a suite of common signal processing functions for use on Cortex-M processor based devices.
- *
- * The library is divided into a number of modules each covering a specific category:
- * - Basic math functions
- * - Fast math functions
- * - Complex math functions
- * - Filters
- * - Matrix functions
- * - Transforms
- * - Motor control functions
- * - Statistical functions
- * - Support functions
- * - Interpolation functions
- *
- * The library has separate functions for operating on 8-bit integers, 16-bit integers,
- * 32-bit integer and 32-bit floating-point values.
- *
- * <b>Processor Support</b>
- *
- * The library is completely written in C and is fully CMSIS compliant.
- * High performance is achieved through maximum use of Cortex-M4 intrinsics.
- *
- * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor,
- * with the DSP intrinsics being emulated through software.
- *
- *
- * <b>Toolchain Support</b>
- *
- * The library has been developed and tested with MDK-ARM version 4.21.
- * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
- *
- * <b>Using the Library</b>
- *
- * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
- * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
- * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
- * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
- * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
- * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
- * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
- * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
- * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
- *
- * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
- * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
- * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
- * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or
- * ARM_MATH_CM0 depending on the target processor in the application.
- *
- * <b>Examples</b>
- *
- * The library ships with a number of examples which demonstrate how to use the library functions.
- *
- * <b>Building the Library</b>
- *
- * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\DSP_Lib\Source\ARM</code> folder.
- * - arm_cortexM0b_math.uvproj
- * - arm_cortexM0l_math.uvproj
- * - arm_cortexM3b_math.uvproj
- * - arm_cortexM3l_math.uvproj
- * - arm_cortexM4b_math.uvproj
- * - arm_cortexM4l_math.uvproj
- * - arm_cortexM4bf_math.uvproj
- * - arm_cortexM4lf_math.uvproj
- *
- * Each library project have differant pre-processor macros.
- *
- * <b>ARM_MATH_CMx:</b>
- * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
- * and ARM_MATH_CM0 for building library on cortex-M0 target.
- *
- * <b>ARM_MATH_BIG_ENDIAN:</b>
- * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
- *
- * <b>ARM_MATH_MATRIX_CHECK:</b>
- * Define macro for checking on the input and output sizes of matrices
- *
- * <b>ARM_MATH_ROUNDING:</b>
- * Define macro for rounding on support functions
- *
- * <b>__FPU_PRESENT:</b>
- * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
- *
- *
- * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above.
- *
- * <b>Copyright Notice</b>
- *
- * Copyright (C) 2010 ARM Limited. All rights reserved.
- */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures. For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- * <pre>
- * typedef struct
- * {
- * uint16_t numRows; // number of rows of the matrix.
- * uint16_t numCols; // number of columns of the matrix.
- * float32_t *pData; // points to the data of the matrix.
- * } arm_matrix_instance_f32;
- * </pre>
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data. The array is of size <code>numRows X numCols</code>
- * and the values are arranged in row order. That is, the
- * matrix element (i, j) is stored at:
- * <pre>
- * pData[i*numCols + j]
- * </pre>
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure. For example:
- * <pre>
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
- * </pre>
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
- * specifies the number of columns, and <code>pData</code> points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices. For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns. If the size check fails the functions return:
- * <pre>
- * ARM_MATH_SIZE_MISMATCH
- * </pre>
- * Otherwise the functions return
- * <pre>
- * ARM_MATH_SUCCESS
- * </pre>
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the #define
- * <pre>
- * ARM_MATH_MATRIX_CHECK
- * </pre>
- * within the library project settings. By default this macro is defined
- * and size checking is enabled. By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster. With size checking disabled the functions always
- * return <code>ARM_MATH_SUCCESS</code>.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
-
-#if defined (ARM_MATH_CM4)
- #include "core_cm4.h"
-#elif defined (ARM_MATH_CM3)
- #include "core_cm3.h"
-#elif defined (ARM_MATH_CM0)
- #include "core_cm0.h"
-#else
-#include "ARMCM4.h"
-#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
-#endif
-
-#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
-#include "string.h"
- #include "math.h"
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
- /**
- * @brief Macros required for reciprocal calculation in Normalized LMS
- */
-
-#define DELTA_Q31 (0x100)
-#define DELTA_Q15 0x5
-#define INDEX_MASK 0x0000003F
-#define PI 3.14159265358979f
-
- /**
- * @brief Macros required for SINE and COSINE Fast math approximations
- */
-
-#define TABLE_SIZE 256
-#define TABLE_SPACING_Q31 0x800000
-#define TABLE_SPACING_Q15 0x80
-
- /**
- * @brief Macros required for SINE and COSINE Controller functions
- */
- /* 1.31(q31) Fixed value of 2/360 */
- /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING 0xB60B61
-
-
- /**
- * @brief Error status returned by some functions in the library.
- */
-
- typedef enum
- {
- ARM_MATH_SUCCESS = 0, /**< No error */
- ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
- ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
- ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
- ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
- ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
- ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
- } arm_status;
-
- /**
- * @brief 8-bit fractional data type in 1.7 format.
- */
- typedef int8_t q7_t;
-
- /**
- * @brief 16-bit fractional data type in 1.15 format.
- */
- typedef int16_t q15_t;
-
- /**
- * @brief 32-bit fractional data type in 1.31 format.
- */
- typedef int32_t q31_t;
-
- /**
- * @brief 64-bit fractional data type in 1.63 format.
- */
- typedef int64_t q63_t;
-
- /**
- * @brief 32-bit floating-point type definition.
- */
- typedef float float32_t;
-
- /**
- * @brief 64-bit floating-point type definition.
- */
- typedef double float64_t;
-
- /**
- * @brief definition to read/write two 16 bit values.
- */
-#define __SIMD32(addr) (*(int32_t **) & (addr))
-
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
- /**
- * @brief definition to pack two 16 bit values.
- */
-#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
- (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
-
-#endif
-
-
- /**
- * @brief definition to pack four 8 bit values.
- */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
- (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
- (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
- (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
-#else
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
- (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
- (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
- (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
-
-#endif
-
-
- /**
- * @brief Clips Q63 to Q31 values.
- */
- static __INLINE q31_t clip_q63_to_q31(
- q63_t x)
- {
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
- ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
- }
-
- /**
- * @brief Clips Q63 to Q15 values.
- */
- static __INLINE q15_t clip_q63_to_q15(
- q63_t x)
- {
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
- ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
- }
-
- /**
- * @brief Clips Q31 to Q7 values.
- */
- static __INLINE q7_t clip_q31_to_q7(
- q31_t x)
- {
- return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
- ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
- }
-
- /**
- * @brief Clips Q31 to Q15 values.
- */
- static __INLINE q15_t clip_q31_to_q15(
- q31_t x)
- {
- return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
- ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
- }
-
- /**
- * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
- */
-
- static __INLINE q63_t mult32x64(
- q63_t x,
- q31_t y)
- {
- return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
- (((q63_t) (x >> 32) * y)));
- }
-
-
-#if defined (ARM_MATH_CM0) && defined ( __CC_ARM )
-#define __CLZ __clz
-#endif
-
-#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
-
- static __INLINE uint32_t __CLZ(q31_t data);
-
-
- static __INLINE uint32_t __CLZ(q31_t data)
- {
- uint32_t count = 0;
- uint32_t mask = 0x80000000;
-
- while((data & mask) == 0)
- {
- count += 1u;
- mask = mask >> 1u;
- }
-
- return(count);
-
- }
-
-#endif
-
- /**
- * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.
- */
-
- static __INLINE uint32_t arm_recip_q31(
- q31_t in,
- q31_t * dst,
- q31_t * pRecipTable)
- {
-
- uint32_t out, tempVal;
- uint32_t index, i;
- uint32_t signBits;
-
- if(in > 0)
- {
- signBits = __CLZ(in) - 1;
- }
- else
- {
- signBits = __CLZ(-in) - 1;
- }
-
- /* Convert input sample to 1.31 format */
- in = in << signBits;
-
- /* calculation of index for initial approximated Val */
- index = (uint32_t) (in >> 24u);
- index = (index & INDEX_MASK);
-
- /* 1.31 with exp 1 */
- out = pRecipTable[index];
-
- /* calculation of reciprocal value */
- /* running approximation for two iterations */
- for (i = 0u; i < 2u; i++)
- {
- tempVal = (q31_t) (((q63_t) in * out) >> 31u);
- tempVal = 0x7FFFFFFF - tempVal;
- /* 1.31 with exp 1 */
- //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
- out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
- }
-
- /* write output */
- *dst = out;
-
- /* return num of signbits of out = 1/in value */
- return (signBits + 1u);
-
- }
-
- /**
- * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.
- */
- static __INLINE uint32_t arm_recip_q15(
- q15_t in,
- q15_t * dst,
- q15_t * pRecipTable)
- {
-
- uint32_t out = 0, tempVal = 0;
- uint32_t index = 0, i = 0;
- uint32_t signBits = 0;
-
- if(in > 0)
- {
- signBits = __CLZ(in) - 17;
- }
- else
- {
- signBits = __CLZ(-in) - 17;
- }
-
- /* Convert input sample to 1.15 format */
- in = in << signBits;
-
- /* calculation of index for initial approximated Val */
- index = in >> 8;
- index = (index & INDEX_MASK);
-
- /* 1.15 with exp 1 */
- out = pRecipTable[index];
-
- /* calculation of reciprocal value */
- /* running approximation for two iterations */
- for (i = 0; i < 2; i++)
- {
- tempVal = (q15_t) (((q31_t) in * out) >> 15);
- tempVal = 0x7FFF - tempVal;
- /* 1.15 with exp 1 */
- out = (q15_t) (((q31_t) out * tempVal) >> 14);
- }
-
- /* write output */
- *dst = out;
-
- /* return num of signbits of out = 1/in value */
- return (signBits + 1);
-
- }
-
-
- /*
- * @brief C custom defined intrinisic function for only M0 processors
- */
-#if defined(ARM_MATH_CM0)
-
- static __INLINE q31_t __SSAT(
- q31_t x,
- uint32_t y)
- {
- int32_t posMax, negMin;
- uint32_t i;
-
- posMax = 1;
- for (i = 0; i < (y - 1); i++)
- {
- posMax = posMax * 2;
- }
-
- if(x > 0)
- {
- posMax = (posMax - 1);
-
- if(x > posMax)
- {
- x = posMax;
- }
- }
- else
- {
- negMin = -posMax;
-
- if(x < negMin)
- {
- x = negMin;
- }
- }
- return (x);
-
-
- }
-
-#endif /* end of ARM_MATH_CM0 */
-
-
-
- /*
- * @brief C custom defined intrinsic function for M3 and M0 processors
- */
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
-
- /*
- * @brief C custom defined QADD8 for M3 and M0 processors
- */
- static __INLINE q31_t __QADD8(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q7_t r, s, t, u;
-
- r = (char) x;
- s = (char) y;
-
- r = __SSAT((q31_t) (r + s), 8);
- s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
- t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
- u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
-
- sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
- (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
-
- return sum;
-
- }
-
- /*
- * @brief C custom defined QSUB8 for M3 and M0 processors
- */
- static __INLINE q31_t __QSUB8(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q31_t r, s, t, u;
-
- r = (char) x;
- s = (char) y;
-
- r = __SSAT((r - s), 8);
- s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
- t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
- u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
-
- sum =
- (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF);
-
- return sum;
- }
-
- /*
- * @brief C custom defined QADD16 for M3 and M0 processors
- */
-
- /*
- * @brief C custom defined QADD16 for M3 and M0 processors
- */
- static __INLINE q31_t __QADD16(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q31_t r, s;
-
- r = (short) x;
- s = (short) y;
-
- r = __SSAT(r + s, 16);
- s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
-
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
- return sum;
-
- }
-
- /*
- * @brief C custom defined SHADD16 for M3 and M0 processors
- */
- static __INLINE q31_t __SHADD16(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q31_t r, s;
-
- r = (short) x;
- s = (short) y;
-
- r = ((r >> 1) + (s >> 1));
- s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
-
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
- return sum;
-
- }
-
- /*
- * @brief C custom defined QSUB16 for M3 and M0 processors
- */
- static __INLINE q31_t __QSUB16(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q31_t r, s;
-
- r = (short) x;
- s = (short) y;
-
- r = __SSAT(r - s, 16);
- s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
-
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
- return sum;
- }
-
- /*
- * @brief C custom defined SHSUB16 for M3 and M0 processors
- */
- static __INLINE q31_t __SHSUB16(
- q31_t x,
- q31_t y)
- {
-
- q31_t diff;
- q31_t r, s;
-
- r = (short) x;
- s = (short) y;
-
- r = ((r >> 1) - (s >> 1));
- s = (((x >> 17) - (y >> 17)) << 16);
-
- diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
- return diff;
- }
-
- /*
- * @brief C custom defined QASX for M3 and M0 processors
- */
- static __INLINE q31_t __QASX(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum = 0;
-
- sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
- clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
-
- return sum;
- }
-
- /*
- * @brief C custom defined SHASX for M3 and M0 processors
- */
- static __INLINE q31_t __SHASX(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q31_t r, s;
-
- r = (short) x;
- s = (short) y;
-
- r = ((r >> 1) - (y >> 17));
- s = (((x >> 17) + (s >> 1)) << 16);
-
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
- return sum;
- }
-
-
- /*
- * @brief C custom defined QSAX for M3 and M0 processors
- */
- static __INLINE q31_t __QSAX(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum = 0;
-
- sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
- clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
-
- return sum;
- }
-
- /*
- * @brief C custom defined SHSAX for M3 and M0 processors
- */
- static __INLINE q31_t __SHSAX(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q31_t r, s;
-
- r = (short) x;
- s = (short) y;
-
- r = ((r >> 1) + (y >> 17));
- s = (((x >> 17) - (s >> 1)) << 16);
-
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
- return sum;
- }
-
- /*
- * @brief C custom defined SMUSDX for M3 and M0 processors
- */
- static __INLINE q31_t __SMUSDX(
- q31_t x,
- q31_t y)
- {
-
- return ((q31_t)(((short) x * (short) (y >> 16)) -
- ((short) (x >> 16) * (short) y)));
- }
-
- /*
- * @brief C custom defined SMUADX for M3 and M0 processors
- */
- static __INLINE q31_t __SMUADX(
- q31_t x,
- q31_t y)
- {
-
- return ((q31_t)(((short) x * (short) (y >> 16)) +
- ((short) (x >> 16) * (short) y)));
- }
-
- /*
- * @brief C custom defined QADD for M3 and M0 processors
- */
- static __INLINE q31_t __QADD(
- q31_t x,
- q31_t y)
- {
- return clip_q63_to_q31((q63_t) x + y);
- }
-
- /*
- * @brief C custom defined QSUB for M3 and M0 processors
- */
- static __INLINE q31_t __QSUB(
- q31_t x,
- q31_t y)
- {
- return clip_q63_to_q31((q63_t) x - y);
- }
-
- /*
- * @brief C custom defined SMLAD for M3 and M0 processors
- */
- static __INLINE q31_t __SMLAD(
- q31_t x,
- q31_t y,
- q31_t sum)
- {
-
- return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
- ((short) x * (short) y));
- }
-
- /*
- * @brief C custom defined SMLADX for M3 and M0 processors
- */
- static __INLINE q31_t __SMLADX(
- q31_t x,
- q31_t y,
- q31_t sum)
- {
-
- return (sum + ((short) (x >> 16) * (short) (y)) +
- ((short) x * (short) (y >> 16)));
- }
-
- /*
- * @brief C custom defined SMLSDX for M3 and M0 processors
- */
- static __INLINE q31_t __SMLSDX(
- q31_t x,
- q31_t y,
- q31_t sum)
- {
-
- return (sum - ((short) (x >> 16) * (short) (y)) +
- ((short) x * (short) (y >> 16)));
- }
-
- /*
- * @brief C custom defined SMLALD for M3 and M0 processors
- */
- static __INLINE q63_t __SMLALD(
- q31_t x,
- q31_t y,
- q63_t sum)
- {
-
- return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
- ((short) x * (short) y));
- }
-
- /*
- * @brief C custom defined SMLALDX for M3 and M0 processors
- */
- static __INLINE q63_t __SMLALDX(
- q31_t x,
- q31_t y,
- q63_t sum)
- {
-
- return (sum + ((short) (x >> 16) * (short) y)) +
- ((short) x * (short) (y >> 16));
- }
-
- /*
- * @brief C custom defined SMUAD for M3 and M0 processors
- */
- static __INLINE q31_t __SMUAD(
- q31_t x,
- q31_t y)
- {
-
- return (((x >> 16) * (y >> 16)) +
- (((x << 16) >> 16) * ((y << 16) >> 16)));
- }
-
- /*
- * @brief C custom defined SMUSD for M3 and M0 processors
- */
- static __INLINE q31_t __SMUSD(
- q31_t x,
- q31_t y)
- {
-
- return (-((x >> 16) * (y >> 16)) +
- (((x << 16) >> 16) * ((y << 16) >> 16)));
- }
-
-
-
-
-#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */
-
-
- /**
- * @brief Instance structure for the Q7 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- } arm_fir_instance_q7;
-
- /**
- * @brief Instance structure for the Q15 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- } arm_fir_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- } arm_fir_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- } arm_fir_instance_f32;
-
-
- /**
- * @brief Processing function for the Q7 FIR filter.
- * @param[in] *S points to an instance of the Q7 FIR filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_q7(
- const arm_fir_instance_q7 * S,
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q7 FIR filter.
- * @param[in,out] *S points to an instance of the Q7 FIR structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed.
- * @return none
- */
- void arm_fir_init_q7(
- arm_fir_instance_q7 * S,
- uint16_t numTaps,
- q7_t * pCoeffs,
- q7_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 FIR filter.
- * @param[in] *S points to an instance of the Q15 FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_q15(
- const arm_fir_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q15 FIR filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_fast_q15(
- const arm_fir_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q15 FIR filter.
- * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
- * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
- * <code>numTaps</code> is not a supported value.
- */
-
- arm_status arm_fir_init_q15(
- arm_fir_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 FIR filter.
- * @param[in] *S points to an instance of the Q31 FIR filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_q31(
- const arm_fir_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q31 FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_fast_q31(
- const arm_fir_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q31 FIR filter.
- * @param[in,out] *S points to an instance of the Q31 FIR structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- * @return none.
- */
- void arm_fir_init_q31(
- arm_fir_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the floating-point FIR filter.
- * @param[in] *S points to an instance of the floating-point FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_f32(
- const arm_fir_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the floating-point FIR filter.
- * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- * @return none.
- */
- void arm_fir_init_f32(
- arm_fir_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 Biquad cascade filter.
- */
- typedef struct
- {
- int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
- int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
-
- } arm_biquad_casd_df1_inst_q15;
-
-
- /**
- * @brief Instance structure for the Q31 Biquad cascade filter.
- */
- typedef struct
- {
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
- uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
-
- } arm_biquad_casd_df1_inst_q31;
-
- /**
- * @brief Instance structure for the floating-point Biquad cascade filter.
- */
- typedef struct
- {
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
-
-
- } arm_biquad_casd_df1_inst_f32;
-
-
-
- /**
- * @brief Processing function for the Q15 Biquad cascade filter.
- * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df1_q15(
- const arm_biquad_casd_df1_inst_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q15 Biquad cascade filter.
- * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
- * @return none
- */
-
- void arm_biquad_cascade_df1_init_q15(
- arm_biquad_casd_df1_inst_q15 * S,
- uint8_t numStages,
- q15_t * pCoeffs,
- q15_t * pState,
- int8_t postShift);
-
-
- /**
- * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df1_fast_q15(
- const arm_biquad_casd_df1_inst_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 Biquad cascade filter
- * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df1_q31(
- const arm_biquad_casd_df1_inst_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df1_fast_q31(
- const arm_biquad_casd_df1_inst_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q31 Biquad cascade filter.
- * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
- * @return none
- */
-
- void arm_biquad_cascade_df1_init_q31(
- arm_biquad_casd_df1_inst_q31 * S,
- uint8_t numStages,
- q31_t * pCoeffs,
- q31_t * pState,
- int8_t postShift);
-
- /**
- * @brief Processing function for the floating-point Biquad cascade filter.
- * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df1_f32(
- const arm_biquad_casd_df1_inst_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the floating-point Biquad cascade filter.
- * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @return none
- */
-
- void arm_biquad_cascade_df1_init_f32(
- arm_biquad_casd_df1_inst_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Instance structure for the floating-point matrix structure.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- float32_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_f32;
-
- /**
- * @brief Instance structure for the Q15 matrix structure.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- q15_t *pData; /**< points to the data of the matrix. */
-
- } arm_matrix_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 matrix structure.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- q31_t *pData; /**< points to the data of the matrix. */
-
- } arm_matrix_instance_q31;
-
-
-
- /**
- * @brief Floating-point matrix addition.
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_add_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15 matrix addition.
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_add_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst);
-
- /**
- * @brief Q31 matrix addition.
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_add_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix transpose.
- * @param[in] *pSrc points to the input matrix
- * @param[out] *pDst points to the output matrix
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_trans_f32(
- const arm_matrix_instance_f32 * pSrc,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15 matrix transpose.
- * @param[in] *pSrc points to the input matrix
- * @param[out] *pDst points to the output matrix
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_trans_q15(
- const arm_matrix_instance_q15 * pSrc,
- arm_matrix_instance_q15 * pDst);
-
- /**
- * @brief Q31 matrix transpose.
- * @param[in] *pSrc points to the input matrix
- * @param[out] *pDst points to the output matrix
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_trans_q31(
- const arm_matrix_instance_q31 * pSrc,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix multiplication
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_mult_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15 matrix multiplication
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_mult_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pState);
-
- /**
- * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @param[in] *pState points to the array for storing intermediate results
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_mult_fast_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pState);
-
- /**
- * @brief Q31 matrix multiplication
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_mult_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
- /**
- * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_mult_fast_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix subtraction
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_sub_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15 matrix subtraction
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_sub_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst);
-
- /**
- * @brief Q31 matrix subtraction
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_sub_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
- /**
- * @brief Floating-point matrix scaling.
- * @param[in] *pSrc points to the input matrix
- * @param[in] scale scale factor
- * @param[out] *pDst points to the output matrix
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_scale_f32(
- const arm_matrix_instance_f32 * pSrc,
- float32_t scale,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15 matrix scaling.
- * @param[in] *pSrc points to input matrix
- * @param[in] scaleFract fractional portion of the scale factor
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to output matrix
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_scale_q15(
- const arm_matrix_instance_q15 * pSrc,
- q15_t scaleFract,
- int32_t shift,
- arm_matrix_instance_q15 * pDst);
-
- /**
- * @brief Q31 matrix scaling.
- * @param[in] *pSrc points to input matrix
- * @param[in] scaleFract fractional portion of the scale factor
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_scale_q31(
- const arm_matrix_instance_q31 * pSrc,
- q31_t scaleFract,
- int32_t shift,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Q31 matrix initialization.
- * @param[in,out] *S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] *pData points to the matrix data array.
- * @return none
- */
-
- void arm_mat_init_q31(
- arm_matrix_instance_q31 * S,
- uint16_t nRows,
- uint16_t nColumns,
- q31_t *pData);
-
- /**
- * @brief Q15 matrix initialization.
- * @param[in,out] *S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] *pData points to the matrix data array.
- * @return none
- */
-
- void arm_mat_init_q15(
- arm_matrix_instance_q15 * S,
- uint16_t nRows,
- uint16_t nColumns,
- q15_t *pData);
-
- /**
- * @brief Floating-point matrix initialization.
- * @param[in,out] *S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] *pData points to the matrix data array.
- * @return none
- */
-
- void arm_mat_init_f32(
- arm_matrix_instance_f32 * S,
- uint16_t nRows,
- uint16_t nColumns,
- float32_t *pData);
-
-
-
- /**
- * @brief Instance structure for the Q15 PID Control.
- */
- typedef struct
- {
- q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
- #ifdef ARM_MATH_CM0
- q15_t A1;
- q15_t A2;
- #else
- q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
- #endif
- q15_t state[3]; /**< The state array of length 3. */
- q15_t Kp; /**< The proportional gain. */
- q15_t Ki; /**< The integral gain. */
- q15_t Kd; /**< The derivative gain. */
- } arm_pid_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 PID Control.
- */
- typedef struct
- {
- q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
- q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
- q31_t A2; /**< The derived gain, A2 = Kd . */
- q31_t state[3]; /**< The state array of length 3. */
- q31_t Kp; /**< The proportional gain. */
- q31_t Ki; /**< The integral gain. */
- q31_t Kd; /**< The derivative gain. */
-
- } arm_pid_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point PID Control.
- */
- typedef struct
- {
- float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
- float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
- float32_t A2; /**< The derived gain, A2 = Kd . */
- float32_t state[3]; /**< The state array of length 3. */
- float32_t Kp; /**< The proportional gain. */
- float32_t Ki; /**< The integral gain. */
- float32_t Kd; /**< The derivative gain. */
- } arm_pid_instance_f32;
-
-
-
- /**
- * @brief Initialization function for the floating-point PID Control.
- * @param[in,out] *S points to an instance of the PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- * @return none.
- */
- void arm_pid_init_f32(
- arm_pid_instance_f32 * S,
- int32_t resetStateFlag);
-
- /**
- * @brief Reset function for the floating-point PID Control.
- * @param[in,out] *S is an instance of the floating-point PID Control structure
- * @return none
- */
- void arm_pid_reset_f32(
- arm_pid_instance_f32 * S);
-
-
- /**
- * @brief Initialization function for the Q31 PID Control.
- * @param[in,out] *S points to an instance of the Q15 PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- * @return none.
- */
- void arm_pid_init_q31(
- arm_pid_instance_q31 * S,
- int32_t resetStateFlag);
-
-
- /**
- * @brief Reset function for the Q31 PID Control.
- * @param[in,out] *S points to an instance of the Q31 PID Control structure
- * @return none
- */
-
- void arm_pid_reset_q31(
- arm_pid_instance_q31 * S);
-
- /**
- * @brief Initialization function for the Q15 PID Control.
- * @param[in,out] *S points to an instance of the Q15 PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- * @return none.
- */
- void arm_pid_init_q15(
- arm_pid_instance_q15 * S,
- int32_t resetStateFlag);
-
- /**
- * @brief Reset function for the Q15 PID Control.
- * @param[in,out] *S points to an instance of the q15 PID Control structure
- * @return none
- */
- void arm_pid_reset_q15(
- arm_pid_instance_q15 * S);
-
-
- /**
- * @brief Instance structure for the floating-point Linear Interpolate function.
- */
- typedef struct
- {
- uint32_t nValues;
- float32_t x1;
- float32_t xSpacing;
- float32_t *pYData; /**< pointer to the table of Y values */
- } arm_linear_interp_instance_f32;
-
- /**
- * @brief Instance structure for the floating-point bilinear interpolation function.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- float32_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_f32;
-
- /**
- * @brief Instance structure for the Q31 bilinear interpolation function.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q31_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q31;
-
- /**
- * @brief Instance structure for the Q15 bilinear interpolation function.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q15_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q15;
-
- /**
- * @brief Instance structure for the Q15 bilinear interpolation function.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q7_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q7;
-
-
- /**
- * @brief Q7 vector multiplication.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_mult_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q15 vector multiplication.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_mult_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q31 vector multiplication.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_mult_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Floating-point vector multiplication.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_mult_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q15_t *pTwiddle; /**< points to the twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix4_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q31_t *pTwiddle; /**< points to the twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix4_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- float32_t *pTwiddle; /**< points to the twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- float32_t onebyfftLen; /**< value of 1/fftLen. */
- } arm_cfft_radix4_instance_f32;
-
- /**
- * @brief Processing function for the Q15 CFFT/CIFFT.
- * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure.
- * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
- * @return none.
- */
-
- void arm_cfft_radix4_q15(
- const arm_cfft_radix4_instance_q15 * S,
- q15_t * pSrc);
-
- /**
- * @brief Initialization function for the Q15 CFFT/CIFFT.
- * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.
- * @param[in] fftLen length of the FFT.
- * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
- * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
- */
-
- arm_status arm_cfft_radix4_init_q15(
- arm_cfft_radix4_instance_q15 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Processing function for the Q31 CFFT/CIFFT.
- * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure.
- * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
- * @return none.
- */
-
- void arm_cfft_radix4_q31(
- const arm_cfft_radix4_instance_q31 * S,
- q31_t * pSrc);
-
- /**
- * @brief Initialization function for the Q31 CFFT/CIFFT.
- * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure.
- * @param[in] fftLen length of the FFT.
- * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
- * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
- */
-
- arm_status arm_cfft_radix4_init_q31(
- arm_cfft_radix4_instance_q31 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Processing function for the floating-point CFFT/CIFFT.
- * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure.
- * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
- * @return none.
- */
-
- void arm_cfft_radix4_f32(
- const arm_cfft_radix4_instance_f32 * S,
- float32_t * pSrc);
-
- /**
- * @brief Initialization function for the floating-point CFFT/CIFFT.
- * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.
- * @param[in] fftLen length of the FFT.
- * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
- * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
- */
-
- arm_status arm_cfft_radix4_init_f32(
- arm_cfft_radix4_instance_f32 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-
-
- /*----------------------------------------------------------------------
- * Internal functions prototypes FFT function
- ----------------------------------------------------------------------*/
-
- /**
- * @brief Core function for the floating-point CFFT butterfly process.
- * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
- * @param[in] fftLen length of the FFT.
- * @param[in] *pCoef points to the twiddle coefficient buffer.
- * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
- * @return none.
- */
-
- void arm_radix4_butterfly_f32(
- float32_t * pSrc,
- uint16_t fftLen,
- float32_t * pCoef,
- uint16_t twidCoefModifier);
-
- /**
- * @brief Core function for the floating-point CIFFT butterfly process.
- * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
- * @param[in] fftLen length of the FFT.
- * @param[in] *pCoef points to twiddle coefficient buffer.
- * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
- * @param[in] onebyfftLen value of 1/fftLen.
- * @return none.
- */
-
- void arm_radix4_butterfly_inverse_f32(
- float32_t * pSrc,
- uint16_t fftLen,
- float32_t * pCoef,
- uint16_t twidCoefModifier,
- float32_t onebyfftLen);
-
- /**
- * @brief In-place bit reversal function.
- * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
- * @param[in] fftSize length of the FFT.
- * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.
- * @param[in] *pBitRevTab points to the bit reversal table.
- * @return none.
- */
-
- void arm_bitreversal_f32(
- float32_t *pSrc,
- uint16_t fftSize,
- uint16_t bitRevFactor,
- uint16_t *pBitRevTab);
-
- /**
- * @brief Core function for the Q31 CFFT butterfly process.
- * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
- * @param[in] fftLen length of the FFT.
- * @param[in] *pCoef points to twiddle coefficient buffer.
- * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
- * @return none.
- */
-
- void arm_radix4_butterfly_q31(
- q31_t *pSrc,
- uint32_t fftLen,
- q31_t *pCoef,
- uint32_t twidCoefModifier);
-
- /**
- * @brief Core function for the Q31 CIFFT butterfly process.
- * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
- * @param[in] fftLen length of the FFT.
- * @param[in] *pCoef points to twiddle coefficient buffer.
- * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
- * @return none.
- */
-
- void arm_radix4_butterfly_inverse_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- q31_t * pCoef,
- uint32_t twidCoefModifier);
-
- /**
- * @brief In-place bit reversal function.
- * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
- * @param[in] fftLen length of the FFT.
- * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
- * @param[in] *pBitRevTab points to bit reversal table.
- * @return none.
- */
-
- void arm_bitreversal_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- uint16_t bitRevFactor,
- uint16_t *pBitRevTab);
-
- /**
- * @brief Core function for the Q15 CFFT butterfly process.
- * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.
- * @param[in] fftLen length of the FFT.
- * @param[in] *pCoef16 points to twiddle coefficient buffer.
- * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
- * @return none.
- */
-
- void arm_radix4_butterfly_q15(
- q15_t *pSrc16,
- uint32_t fftLen,
- q15_t *pCoef16,
- uint32_t twidCoefModifier);
-
- /**
- * @brief Core function for the Q15 CIFFT butterfly process.
- * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.
- * @param[in] fftLen length of the FFT.
- * @param[in] *pCoef16 points to twiddle coefficient buffer.
- * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
- * @return none.
- */
-
- void arm_radix4_butterfly_inverse_q15(
- q15_t *pSrc16,
- uint32_t fftLen,
- q15_t *pCoef16,
- uint32_t twidCoefModifier);
-
- /**
- * @brief In-place bit reversal function.
- * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
- * @param[in] fftLen length of the FFT.
- * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
- * @param[in] *pBitRevTab points to bit reversal table.
- * @return none.
- */
-
- void arm_bitreversal_q15(
- q15_t * pSrc,
- uint32_t fftLen,
- uint16_t bitRevFactor,
- uint16_t *pBitRevTab);
-
- /**
- * @brief Instance structure for the Q15 RFFT/RIFFT function.
- */
-
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint32_t fftLenBy2; /**< length of the complex FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 RFFT/RIFFT function.
- */
-
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint32_t fftLenBy2; /**< length of the complex FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point RFFT/RIFFT function.
- */
-
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint16_t fftLenBy2; /**< length of the complex FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_f32;
-
- /**
- * @brief Processing function for the Q15 RFFT/RIFFT.
- * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure.
- * @param[in] *pSrc points to the input buffer.
- * @param[out] *pDst points to the output buffer.
- * @return none.
- */
-
- void arm_rfft_q15(
- const arm_rfft_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst);
-
- /**
- * @brief Initialization function for the Q15 RFFT/RIFFT.
- * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure.
- * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure.
- * @param[in] fftLenReal length of the FFT.
- * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
- * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
- */
-
- arm_status arm_rfft_init_q15(
- arm_rfft_instance_q15 * S,
- arm_cfft_radix4_instance_q15 * S_CFFT,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- /**
- * @brief Processing function for the Q31 RFFT/RIFFT.
- * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure.
- * @param[in] *pSrc points to the input buffer.
- * @param[out] *pDst points to the output buffer.
- * @return none.
- */
-
- void arm_rfft_q31(
- const arm_rfft_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst);
-
- /**
- * @brief Initialization function for the Q31 RFFT/RIFFT.
- * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure.
- * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure.
- * @param[in] fftLenReal length of the FFT.
- * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
- * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
- */
-
- arm_status arm_rfft_init_q31(
- arm_rfft_instance_q31 * S,
- arm_cfft_radix4_instance_q31 * S_CFFT,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- /**
- * @brief Initialization function for the floating-point RFFT/RIFFT.
- * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure.
- * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure.
- * @param[in] fftLenReal length of the FFT.
- * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
- * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
- */
-
- arm_status arm_rfft_init_f32(
- arm_rfft_instance_f32 * S,
- arm_cfft_radix4_instance_f32 * S_CFFT,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- /**
- * @brief Processing function for the floating-point RFFT/RIFFT.
- * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure.
- * @param[in] *pSrc points to the input buffer.
- * @param[out] *pDst points to the output buffer.
- * @return none.
- */
-
- void arm_rfft_f32(
- const arm_rfft_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst);
-
- /**
- * @brief Instance structure for the floating-point DCT4/IDCT4 function.
- */
-
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- float32_t normalize; /**< normalizing factor. */
- float32_t *pTwiddle; /**< points to the twiddle factor table. */
- float32_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_f32;
-
- /**
- * @brief Initialization function for the floating-point DCT4/IDCT4.
- * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.
- * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
- * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
- */
-
- arm_status arm_dct4_init_f32(
- arm_dct4_instance_f32 * S,
- arm_rfft_instance_f32 * S_RFFT,
- arm_cfft_radix4_instance_f32 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- float32_t normalize);
-
- /**
- * @brief Processing function for the floating-point DCT4/IDCT4.
- * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.
- * @param[in] *pState points to state buffer.
- * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
- * @return none.
- */
-
- void arm_dct4_f32(
- const arm_dct4_instance_f32 * S,
- float32_t * pState,
- float32_t * pInlineBuffer);
-
- /**
- * @brief Instance structure for the Q31 DCT4/IDCT4 function.
- */
-
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- q31_t normalize; /**< normalizing factor. */
- q31_t *pTwiddle; /**< points to the twiddle factor table. */
- q31_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_q31;
-
- /**
- * @brief Initialization function for the Q31 DCT4/IDCT4.
- * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.
- * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure
- * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
- */
-
- arm_status arm_dct4_init_q31(
- arm_dct4_instance_q31 * S,
- arm_rfft_instance_q31 * S_RFFT,
- arm_cfft_radix4_instance_q31 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- q31_t normalize);
-
- /**
- * @brief Processing function for the Q31 DCT4/IDCT4.
- * @param[in] *S points to an instance of the Q31 DCT4 structure.
- * @param[in] *pState points to state buffer.
- * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
- * @return none.
- */
-
- void arm_dct4_q31(
- const arm_dct4_instance_q31 * S,
- q31_t * pState,
- q31_t * pInlineBuffer);
-
- /**
- * @brief Instance structure for the Q15 DCT4/IDCT4 function.
- */
-
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- q15_t normalize; /**< normalizing factor. */
- q15_t *pTwiddle; /**< points to the twiddle factor table. */
- q15_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_q15;
-
- /**
- * @brief Initialization function for the Q15 DCT4/IDCT4.
- * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.
- * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
- * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
- */
-
- arm_status arm_dct4_init_q15(
- arm_dct4_instance_q15 * S,
- arm_rfft_instance_q15 * S_RFFT,
- arm_cfft_radix4_instance_q15 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- q15_t normalize);
-
- /**
- * @brief Processing function for the Q15 DCT4/IDCT4.
- * @param[in] *S points to an instance of the Q15 DCT4 structure.
- * @param[in] *pState points to state buffer.
- * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
- * @return none.
- */
-
- void arm_dct4_q15(
- const arm_dct4_instance_q15 * S,
- q15_t * pState,
- q15_t * pInlineBuffer);
-
- /**
- * @brief Floating-point vector addition.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_add_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q7 vector addition.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_add_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q15 vector addition.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_add_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q31 vector addition.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_add_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Floating-point vector subtraction.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_sub_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q7 vector subtraction.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_sub_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q15 vector subtraction.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_sub_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q31 vector subtraction.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_sub_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Multiplies a floating-point vector by a scalar.
- * @param[in] *pSrc points to the input vector
- * @param[in] scale scale factor to be applied
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_scale_f32(
- float32_t * pSrc,
- float32_t scale,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Multiplies a Q7 vector by a scalar.
- * @param[in] *pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_scale_q7(
- q7_t * pSrc,
- q7_t scaleFract,
- int8_t shift,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Multiplies a Q15 vector by a scalar.
- * @param[in] *pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_scale_q15(
- q15_t * pSrc,
- q15_t scaleFract,
- int8_t shift,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Multiplies a Q31 vector by a scalar.
- * @param[in] *pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_scale_q31(
- q31_t * pSrc,
- q31_t scaleFract,
- int8_t shift,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q7 vector absolute value.
- * @param[in] *pSrc points to the input buffer
- * @param[out] *pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_abs_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Floating-point vector absolute value.
- * @param[in] *pSrc points to the input buffer
- * @param[out] *pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_abs_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q15 vector absolute value.
- * @param[in] *pSrc points to the input buffer
- * @param[out] *pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_abs_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q31 vector absolute value.
- * @param[in] *pSrc points to the input buffer
- * @param[out] *pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_abs_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Dot product of floating-point vectors.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] *result output result returned here
- * @return none.
- */
-
- void arm_dot_prod_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- uint32_t blockSize,
- float32_t * result);
-
- /**
- * @brief Dot product of Q7 vectors.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] *result output result returned here
- * @return none.
- */
-
- void arm_dot_prod_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- uint32_t blockSize,
- q31_t * result);
-
- /**
- * @brief Dot product of Q15 vectors.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] *result output result returned here
- * @return none.
- */
-
- void arm_dot_prod_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- uint32_t blockSize,
- q63_t * result);
-
- /**
- * @brief Dot product of Q31 vectors.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] *result output result returned here
- * @return none.
- */
-
- void arm_dot_prod_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- uint32_t blockSize,
- q63_t * result);
-
- /**
- * @brief Shifts the elements of a Q7 vector a specified number of bits.
- * @param[in] *pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_shift_q7(
- q7_t * pSrc,
- int8_t shiftBits,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Shifts the elements of a Q15 vector a specified number of bits.
- * @param[in] *pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_shift_q15(
- q15_t * pSrc,
- int8_t shiftBits,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Shifts the elements of a Q31 vector a specified number of bits.
- * @param[in] *pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_shift_q31(
- q31_t * pSrc,
- int8_t shiftBits,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Adds a constant offset to a floating-point vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_offset_f32(
- float32_t * pSrc,
- float32_t offset,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Adds a constant offset to a Q7 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_offset_q7(
- q7_t * pSrc,
- q7_t offset,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Adds a constant offset to a Q15 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_offset_q15(
- q15_t * pSrc,
- q15_t offset,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Adds a constant offset to a Q31 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_offset_q31(
- q31_t * pSrc,
- q31_t offset,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Negates the elements of a floating-point vector.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_negate_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Negates the elements of a Q7 vector.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_negate_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Negates the elements of a Q15 vector.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_negate_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Negates the elements of a Q31 vector.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_negate_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
- /**
- * @brief Copies the elements of a floating-point vector.
- * @param[in] *pSrc input pointer
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_copy_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Copies the elements of a Q7 vector.
- * @param[in] *pSrc input pointer
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_copy_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Copies the elements of a Q15 vector.
- * @param[in] *pSrc input pointer
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_copy_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Copies the elements of a Q31 vector.
- * @param[in] *pSrc input pointer
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_copy_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
- /**
- * @brief Fills a constant value into a floating-point vector.
- * @param[in] value input value to be filled
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_fill_f32(
- float32_t value,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Fills a constant value into a Q7 vector.
- * @param[in] value input value to be filled
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_fill_q7(
- q7_t value,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Fills a constant value into a Q15 vector.
- * @param[in] value input value to be filled
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_fill_q15(
- q15_t value,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Fills a constant value into a Q31 vector.
- * @param[in] value input value to be filled
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_fill_q31(
- q31_t value,
- q31_t * pDst,
- uint32_t blockSize);
-
-/**
- * @brief Convolution of floating-point sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- * @return none.
- */
-
- void arm_conv_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst);
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- * @return none.
- */
-
- void arm_conv_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
- /**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
- * @return none.
- */
-
- void arm_conv_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
- /**
- * @brief Convolution of Q31 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
- * @return none.
- */
-
- void arm_conv_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
- /**
- * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
- * @return none.
- */
-
- void arm_conv_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
- /**
- * @brief Convolution of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
- * @return none.
- */
-
- void arm_conv_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst);
-
- /**
- * @brief Partial convolution of floating-point sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
- /**
- * @brief Partial convolution of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
- /**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
- /**
- * @brief Partial convolution of Q31 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
- /**
- * @brief Partial convolution of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Instance structure for the Q15 FIR decimator.
- */
-
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- } arm_fir_decimate_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR decimator.
- */
-
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-
- } arm_fir_decimate_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR decimator.
- */
-
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-
- } arm_fir_decimate_instance_f32;
-
-
-
- /**
- * @brief Processing function for the floating-point FIR decimator.
- * @param[in] *S points to an instance of the floating-point FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- * @return none
- */
-
- void arm_fir_decimate_f32(
- const arm_fir_decimate_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point FIR decimator.
- * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
-
- arm_status arm_fir_decimate_init_f32(
- arm_fir_decimate_instance_f32 * S,
- uint16_t numTaps,
- uint8_t M,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q15 FIR decimator.
- * @param[in] *S points to an instance of the Q15 FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- * @return none
- */
-
- void arm_fir_decimate_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q15 FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- * @return none
- */
-
- void arm_fir_decimate_fast_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
-
- /**
- * @brief Initialization function for the Q15 FIR decimator.
- * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
-
- arm_status arm_fir_decimate_init_q15(
- arm_fir_decimate_instance_q15 * S,
- uint16_t numTaps,
- uint8_t M,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 FIR decimator.
- * @param[in] *S points to an instance of the Q31 FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- * @return none
- */
-
- void arm_fir_decimate_q31(
- const arm_fir_decimate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q31 FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- * @return none
- */
-
- void arm_fir_decimate_fast_q31(
- arm_fir_decimate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 FIR decimator.
- * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
-
- arm_status arm_fir_decimate_init_q31(
- arm_fir_decimate_instance_q31 * S,
- uint16_t numTaps,
- uint8_t M,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
-
- /**
- * @brief Instance structure for the Q15 FIR interpolator.
- */
-
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
- } arm_fir_interpolate_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR interpolator.
- */
-
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
- } arm_fir_interpolate_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR interpolator.
- */
-
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
- } arm_fir_interpolate_instance_f32;
-
-
- /**
- * @brief Processing function for the Q15 FIR interpolator.
- * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_interpolate_q15(
- const arm_fir_interpolate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 FIR interpolator.
- * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficient buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
-
- arm_status arm_fir_interpolate_init_q15(
- arm_fir_interpolate_instance_q15 * S,
- uint8_t L,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 FIR interpolator.
- * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_interpolate_q31(
- const arm_fir_interpolate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q31 FIR interpolator.
- * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficient buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
-
- arm_status arm_fir_interpolate_init_q31(
- arm_fir_interpolate_instance_q31 * S,
- uint8_t L,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point FIR interpolator.
- * @param[in] *S points to an instance of the floating-point FIR interpolator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_interpolate_f32(
- const arm_fir_interpolate_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the floating-point FIR interpolator.
- * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficient buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
-
- arm_status arm_fir_interpolate_init_f32(
- arm_fir_interpolate_instance_f32 * S,
- uint8_t L,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Instance structure for the high precision Q31 Biquad cascade filter.
- */
-
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
- q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
-
- } arm_biquad_cas_df1_32x64_ins_q31;
-
-
- /**
- * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cas_df1_32x64_q31(
- const arm_biquad_cas_df1_32x64_ins_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
- * @return none
- */
-
- void arm_biquad_cas_df1_32x64_init_q31(
- arm_biquad_cas_df1_32x64_ins_q31 * S,
- uint8_t numStages,
- q31_t * pCoeffs,
- q63_t * pState,
- uint8_t postShift);
-
-
-
- /**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
-
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
- float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_cascade_df2T_instance_f32;
-
-
- /**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in] *S points to an instance of the filter data structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df2T_f32(
- const arm_biquad_cascade_df2T_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] *S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @return none
- */
-
- void arm_biquad_cascade_df2T_init_f32(
- arm_biquad_cascade_df2T_instance_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
-
- /**
- * @brief Instance structure for the Q15 FIR lattice filter.
- */
-
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR lattice filter.
- */
-
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR lattice filter.
- */
-
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_f32;
-
- /**
- * @brief Initialization function for the Q15 FIR lattice filter.
- * @param[in] *S points to an instance of the Q15 FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] *pState points to the state buffer. The array is of length numStages.
- * @return none.
- */
-
- void arm_fir_lattice_init_q15(
- arm_fir_lattice_instance_q15 * S,
- uint16_t numStages,
- q15_t * pCoeffs,
- q15_t * pState);
-
-
- /**
- * @brief Processing function for the Q15 FIR lattice filter.
- * @param[in] *S points to an instance of the Q15 FIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_lattice_q15(
- const arm_fir_lattice_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q31 FIR lattice filter.
- * @param[in] *S points to an instance of the Q31 FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] *pState points to the state buffer. The array is of length numStages.
- * @return none.
- */
-
- void arm_fir_lattice_init_q31(
- arm_fir_lattice_instance_q31 * S,
- uint16_t numStages,
- q31_t * pCoeffs,
- q31_t * pState);
-
-
- /**
- * @brief Processing function for the Q31 FIR lattice filter.
- * @param[in] *S points to an instance of the Q31 FIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_fir_lattice_q31(
- const arm_fir_lattice_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] *S points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] *pState points to the state buffer. The array is of length numStages.
- * @return none.
- */
-
- void arm_fir_lattice_init_f32(
- arm_fir_lattice_instance_f32 * S,
- uint16_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
- /**
- * @brief Processing function for the floating-point FIR lattice filter.
- * @param[in] *S points to an instance of the floating-point FIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_fir_lattice_f32(
- const arm_fir_lattice_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Instance structure for the Q15 IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_f32;
-
- /**
- * @brief Processing function for the floating-point IIR lattice filter.
- * @param[in] *S points to an instance of the floating-point IIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_iir_lattice_f32(
- const arm_iir_lattice_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the floating-point IIR lattice filter.
- * @param[in] *S points to an instance of the floating-point IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
- * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_iir_lattice_init_f32(
- arm_iir_lattice_instance_f32 * S,
- uint16_t numStages,
- float32_t *pkCoeffs,
- float32_t *pvCoeffs,
- float32_t *pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 IIR lattice filter.
- * @param[in] *S points to an instance of the Q31 IIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_iir_lattice_q31(
- const arm_iir_lattice_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 IIR lattice filter.
- * @param[in] *S points to an instance of the Q31 IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
- * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_iir_lattice_init_q31(
- arm_iir_lattice_instance_q31 * S,
- uint16_t numStages,
- q31_t *pkCoeffs,
- q31_t *pvCoeffs,
- q31_t *pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 IIR lattice filter.
- * @param[in] *S points to an instance of the Q15 IIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_iir_lattice_q15(
- const arm_iir_lattice_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
- * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- */
-
- void arm_iir_lattice_init_q15(
- arm_iir_lattice_instance_q15 * S,
- uint16_t numStages,
- q15_t *pkCoeffs,
- q15_t *pvCoeffs,
- q15_t *pState,
- uint32_t blockSize);
-
- /**
- * @brief Instance structure for the floating-point LMS filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- float32_t mu; /**< step size that controls filter coefficient updates. */
- } arm_lms_instance_f32;
-
- /**
- * @brief Processing function for floating-point LMS filter.
- * @param[in] *S points to an instance of the floating-point LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_f32(
- const arm_lms_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pRef,
- float32_t * pOut,
- float32_t * pErr,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for floating-point LMS filter.
- * @param[in] *S points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to the coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_init_f32(
- arm_lms_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- float32_t mu,
- uint32_t blockSize);
-
- /**
- * @brief Instance structure for the Q15 LMS filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q15_t mu; /**< step size that controls filter coefficient updates. */
- uint32_t postShift; /**< bit shift applied to coefficients. */
- } arm_lms_instance_q15;
-
-
- /**
- * @brief Initialization function for the Q15 LMS filter.
- * @param[in] *S points to an instance of the Q15 LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to the coefficient buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- * @return none.
- */
-
- void arm_lms_init_q15(
- arm_lms_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- q15_t mu,
- uint32_t blockSize,
- uint32_t postShift);
-
- /**
- * @brief Processing function for Q15 LMS filter.
- * @param[in] *S points to an instance of the Q15 LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_q15(
- const arm_lms_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pRef,
- q15_t * pOut,
- q15_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q31 LMS filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q31_t mu; /**< step size that controls filter coefficient updates. */
- uint32_t postShift; /**< bit shift applied to coefficients. */
-
- } arm_lms_instance_q31;
-
- /**
- * @brief Processing function for Q31 LMS filter.
- * @param[in] *S points to an instance of the Q15 LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_q31(
- const arm_lms_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pRef,
- q31_t * pOut,
- q31_t * pErr,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for Q31 LMS filter.
- * @param[in] *S points to an instance of the Q31 LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- * @return none.
- */
-
- void arm_lms_init_q31(
- arm_lms_instance_q31 * S,
- uint16_t numTaps,
- q31_t *pCoeffs,
- q31_t *pState,
- q31_t mu,
- uint32_t blockSize,
- uint32_t postShift);
-
- /**
- * @brief Instance structure for the floating-point normalized LMS filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- float32_t mu; /**< step size that control filter coefficient updates. */
- float32_t energy; /**< saves previous frame energy. */
- float32_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_f32;
-
- /**
- * @brief Processing function for floating-point normalized LMS filter.
- * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_norm_f32(
- arm_lms_norm_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pRef,
- float32_t * pOut,
- float32_t * pErr,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for floating-point normalized LMS filter.
- * @param[in] *S points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_norm_init_f32(
- arm_lms_norm_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- float32_t mu,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q31 normalized LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q31_t mu; /**< step size that controls filter coefficient updates. */
- uint8_t postShift; /**< bit shift applied to coefficients. */
- q31_t *recipTable; /**< points to the reciprocal initial value table. */
- q31_t energy; /**< saves previous frame energy. */
- q31_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_q31;
-
- /**
- * @brief Processing function for Q31 normalized LMS filter.
- * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_norm_q31(
- arm_lms_norm_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pRef,
- q31_t * pOut,
- q31_t * pErr,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for Q31 normalized LMS filter.
- * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- * @return none.
- */
-
- void arm_lms_norm_init_q31(
- arm_lms_norm_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- q31_t mu,
- uint32_t blockSize,
- uint8_t postShift);
-
- /**
- * @brief Instance structure for the Q15 normalized LMS filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< Number of coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q15_t mu; /**< step size that controls filter coefficient updates. */
- uint8_t postShift; /**< bit shift applied to coefficients. */
- q15_t *recipTable; /**< Points to the reciprocal initial value table. */
- q15_t energy; /**< saves previous frame energy. */
- q15_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_q15;
-
- /**
- * @brief Processing function for Q15 normalized LMS filter.
- * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_norm_q15(
- arm_lms_norm_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pRef,
- q15_t * pOut,
- q15_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for Q15 normalized LMS filter.
- * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- * @return none.
- */
-
- void arm_lms_norm_init_q15(
- arm_lms_norm_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- q15_t mu,
- uint32_t blockSize,
- uint8_t postShift);
-
- /**
- * @brief Correlation of floating-point sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
- void arm_correlate_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst);
-
- /**
- * @brief Correlation of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
- void arm_correlate_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
- /**
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
- void arm_correlate_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
- /**
- * @brief Correlation of Q31 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
- void arm_correlate_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
- /**
- * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
- void arm_correlate_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
- /**
- * @brief Correlation of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
- void arm_correlate_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst);
-
- /**
- * @brief Instance structure for the floating-point sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_f32;
-
- /**
- * @brief Instance structure for the Q31 sparse FIR filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q31;
-
- /**
- * @brief Instance structure for the Q15 sparse FIR filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q15;
-
- /**
- * @brief Instance structure for the Q7 sparse FIR filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q7;
-
- /**
- * @brief Processing function for the floating-point sparse FIR filter.
- * @param[in] *S points to an instance of the floating-point sparse FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_sparse_f32(
- arm_fir_sparse_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- float32_t * pScratchIn,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the floating-point sparse FIR filter.
- * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] *pCoeffs points to the array of filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] *pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- * @return none
- */
-
- void arm_fir_sparse_init_f32(
- arm_fir_sparse_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 sparse FIR filter.
- * @param[in] *S points to an instance of the Q31 sparse FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_sparse_q31(
- arm_fir_sparse_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- q31_t * pScratchIn,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q31 sparse FIR filter.
- * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] *pCoeffs points to the array of filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] *pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- * @return none
- */
-
- void arm_fir_sparse_init_q31(
- arm_fir_sparse_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q15 sparse FIR filter.
- * @param[in] *S points to an instance of the Q15 sparse FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_sparse_q15(
- arm_fir_sparse_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- q15_t * pScratchIn,
- q31_t * pScratchOut,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 sparse FIR filter.
- * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] *pCoeffs points to the array of filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] *pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- * @return none
- */
-
- void arm_fir_sparse_init_q15(
- arm_fir_sparse_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q7 sparse FIR filter.
- * @param[in] *S points to an instance of the Q7 sparse FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_sparse_q7(
- arm_fir_sparse_instance_q7 * S,
- q7_t * pSrc,
- q7_t * pDst,
- q7_t * pScratchIn,
- q31_t * pScratchOut,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q7 sparse FIR filter.
- * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] *pCoeffs points to the array of filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] *pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- * @return none
- */
-
- void arm_fir_sparse_init_q7(
- arm_fir_sparse_instance_q7 * S,
- uint16_t numTaps,
- q7_t * pCoeffs,
- q7_t * pState,
- int32_t *pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /*
- * @brief Floating-point sin_cos function.
- * @param[in] theta input value in degrees
- * @param[out] *pSinVal points to the processed sine output.
- * @param[out] *pCosVal points to the processed cos output.
- * @return none.
- */
-
- void arm_sin_cos_f32(
- float32_t theta,
- float32_t *pSinVal,
- float32_t *pCcosVal);
-
- /*
- * @brief Q31 sin_cos function.
- * @param[in] theta scaled input value in degrees
- * @param[out] *pSinVal points to the processed sine output.
- * @param[out] *pCosVal points to the processed cosine output.
- * @return none.
- */
-
- void arm_sin_cos_q31(
- q31_t theta,
- q31_t *pSinVal,
- q31_t *pCosVal);
-
-
- /**
- * @brief Floating-point complex conjugate.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
- void arm_cmplx_conj_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex conjugate.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
- void arm_cmplx_conj_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q15 complex conjugate.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
- void arm_cmplx_conj_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
-
-
- /**
- * @brief Floating-point complex magnitude squared
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
- void arm_cmplx_mag_squared_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex magnitude squared
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
- void arm_cmplx_mag_squared_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q15 complex magnitude squared
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
- void arm_cmplx_mag_squared_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup PID PID Motor Control
- *
- * A Proportional Integral Derivative (PID) controller is a generic feedback control
- * loop mechanism widely used in industrial control systems.
- * A PID controller is the most commonly used type of feedback controller.
- *
- * This set of functions implements (PID) controllers
- * for Q15, Q31, and floating-point data types. The functions operate on a single sample
- * of data and each call to the function returns a single processed value.
- * <code>S</code> points to an instance of the PID control data structure. <code>in</code>
- * is the input sample value. The functions return the output value.
- *
- * \par Algorithm:
- * <pre>
- * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
- * A0 = Kp + Ki + Kd
- * A1 = (-Kp ) - (2 * Kd )
- * A2 = Kd </pre>
- *
- * \par
- * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
- *
- * \par
- * \image html PID.gif "Proportional Integral Derivative Controller"
- *
- * \par
- * The PID controller calculates an "error" value as the difference between
- * the measured output and the reference input.
- * The controller attempts to minimize the error by adjusting the process control inputs.
- * The proportional value determines the reaction to the current error,
- * the integral value determines the reaction based on the sum of recent errors,
- * and the derivative value determines the reaction based on the rate at which the error has been changing.
- *
- * \par Instance Structure
- * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
- * A separate instance structure must be defined for each PID Controller.
- * There are separate instance structure declarations for each of the 3 supported data types.
- *
- * \par Reset Functions
- * There is also an associated reset function for each data type which clears the state array.
- *
- * \par Initialization Functions
- * There is also an associated initialization function for each data type.
- * The initialization function performs the following operations:
- * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
- * - Zeros out the values in the state buffer.
- *
- * \par
- * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
- *
- * \par Fixed-Point Behavior
- * Care must be taken when using the fixed-point versions of the PID Controller functions.
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup PID
- * @{
- */
-
- /**
- * @brief Process function for the floating-point PID Control.
- * @param[in,out] *S is an instance of the floating-point PID Control structure
- * @param[in] in input sample to process
- * @return out processed output sample.
- */
-
-
- static __INLINE float32_t arm_pid_f32(
- arm_pid_instance_f32 * S,
- float32_t in)
- {
- float32_t out;
-
- /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
- out = (S->A0 * in) +
- (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
-
- }
-
- /**
- * @brief Process function for the Q31 PID Control.
- * @param[in,out] *S points to an instance of the Q31 PID Control structure
- * @param[in] in input sample to process
- * @return out processed output sample.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * Thus, if the accumulator result overflows it wraps around rather than clip.
- * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
- * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
- */
-
- static __INLINE q31_t arm_pid_q31(
- arm_pid_instance_q31 * S,
- q31_t in)
- {
- q63_t acc;
- q31_t out;
-
- /* acc = A0 * x[n] */
- acc = (q63_t) S->A0 * in;
-
- /* acc += A1 * x[n-1] */
- acc += (q63_t) S->A1 * S->state[0];
-
- /* acc += A2 * x[n-2] */
- acc += (q63_t) S->A2 * S->state[1];
-
- /* convert output to 1.31 format to add y[n-1] */
- out = (q31_t) (acc >> 31u);
-
- /* out += y[n-1] */
- out += S->state[2];
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
-
- }
-
- /**
- * @brief Process function for the Q15 PID Control.
- * @param[in,out] *S points to an instance of the Q15 PID Control structure
- * @param[in] in input sample to process
- * @return out processed output sample.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.
- */
-
- static __INLINE q15_t arm_pid_q15(
- arm_pid_instance_q15 * S,
- q15_t in)
- {
- q63_t acc;
- q15_t out;
-
- /* Implementation of PID controller */
-
- #ifdef ARM_MATH_CM0
-
- /* acc = A0 * x[n] */
- acc = ((q31_t) S->A0 )* in ;
-
- #else
-
- /* acc = A0 * x[n] */
- acc = (q31_t) __SMUAD(S->A0, in);
-
- #endif
-
- #ifdef ARM_MATH_CM0
-
- /* acc += A1 * x[n-1] + A2 * x[n-2] */
- acc += (q31_t) S->A1 * S->state[0] ;
- acc += (q31_t) S->A2 * S->state[1] ;
-
- #else
-
- /* acc += A1 * x[n-1] + A2 * x[n-2] */
- acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc);
-
- #endif
-
- /* acc += y[n-1] */
- acc += (q31_t) S->state[2] << 15;
-
- /* saturate the output */
- out = (q15_t) (__SSAT((acc >> 15), 16));
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
-
- }
-
- /**
- * @} end of PID group
- */
-
-
- /**
- * @brief Floating-point matrix inverse.
- * @param[in] *src points to the instance of the input floating-point matrix structure.
- * @param[out] *dst points to the instance of the output floating-point matrix structure.
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
- */
-
- arm_status arm_mat_inverse_f32(
- const arm_matrix_instance_f32 * src,
- arm_matrix_instance_f32 * dst);
-
-
-
- /**
- * @ingroup groupController
- */
-
-
- /**
- * @defgroup clarke Vector Clarke Transform
- * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
- * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
- * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
- * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
- * \image html clarke.gif Stator current space vector and its components in (a,b).
- * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
- * can be calculated using only <code>Ia</code> and <code>Ib</code>.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html clarkeFormula.gif
- * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
- * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Clarke transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup clarke
- * @{
- */
-
- /**
- *
- * @brief Floating-point Clarke transform
- * @param[in] Ia input three-phase coordinate <code>a</code>
- * @param[in] Ib input three-phase coordinate <code>b</code>
- * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
- * @return none.
- */
-
- static __INLINE void arm_clarke_f32(
- float32_t Ia,
- float32_t Ib,
- float32_t * pIalpha,
- float32_t * pIbeta)
- {
- /* Calculate pIalpha using the equation, pIalpha = Ia */
- *pIalpha = Ia;
-
- /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
- *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
-
- }
-
- /**
- * @brief Clarke transform for Q31 version
- * @param[in] Ia input three-phase coordinate <code>a</code>
- * @param[in] Ib input three-phase coordinate <code>b</code>
- * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
- * @return none.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition, hence there is no risk of overflow.
- */
-
- static __INLINE void arm_clarke_q31(
- q31_t Ia,
- q31_t Ib,
- q31_t * pIalpha,
- q31_t * pIbeta)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
-
- /* Calculating pIalpha from Ia by equation pIalpha = Ia */
- *pIalpha = Ia;
-
- /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
- product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
- /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
- product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
- /* pIbeta is calculated by adding the intermediate products */
- *pIbeta = __QADD(product1, product2);
- }
-
- /**
- * @} end of clarke group
- */
-
- /**
- * @brief Converts the elements of the Q7 vector to Q31 vector.
- * @param[in] *pSrc input pointer
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_q7_to_q31(
- q7_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup inv_clarke Vector Inverse Clarke Transform
- * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html clarkeInvFormula.gif
- * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
- * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Clarke transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup inv_clarke
- * @{
- */
-
- /**
- * @brief Floating-point Inverse Clarke transform
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha
- * @param[in] Ibeta input two-phase orthogonal vector axis beta
- * @param[out] *pIa points to output three-phase coordinate <code>a</code>
- * @param[out] *pIb points to output three-phase coordinate <code>b</code>
- * @return none.
- */
-
-
- static __INLINE void arm_inv_clarke_f32(
- float32_t Ialpha,
- float32_t Ibeta,
- float32_t * pIa,
- float32_t * pIb)
- {
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */
- *pIa = Ialpha;
-
- /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
- *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
-
- }
-
- /**
- * @brief Inverse Clarke transform for Q31 version
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha
- * @param[in] Ibeta input two-phase orthogonal vector axis beta
- * @param[out] *pIa points to output three-phase coordinate <code>a</code>
- * @param[out] *pIb points to output three-phase coordinate <code>b</code>
- * @return none.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the subtraction, hence there is no risk of overflow.
- */
-
- static __INLINE void arm_inv_clarke_q31(
- q31_t Ialpha,
- q31_t Ibeta,
- q31_t * pIa,
- q31_t * pIb)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
-
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */
- *pIa = Ialpha;
-
- /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
- product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
- /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
- product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
- /* pIb is calculated by subtracting the products */
- *pIb = __QSUB(product2, product1);
-
- }
-
- /**
- * @} end of inv_clarke group
- */
-
- /**
- * @brief Converts the elements of the Q7 vector to Q15 vector.
- * @param[in] *pSrc input pointer
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_q7_to_q15(
- q7_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup park Vector Park Transform
- *
- * Forward Park transform converts the input two-coordinate vector to flux and torque components.
- * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
- * from the stationary to the moving reference frame and control the spatial relationship between
- * the stator vector current and rotor flux vector.
- * If we consider the d axis aligned with the rotor flux, the diagram below shows the
- * current vector and the relationship from the two reference frames:
- * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html parkFormula.gif
- * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
- * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
- * cosine and sine values of theta (rotor flux position).
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Park transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup park
- * @{
- */
-
- /**
- * @brief Floating-point Park transform
- * @param[in] Ialpha input two-phase vector coordinate alpha
- * @param[in] Ibeta input two-phase vector coordinate beta
- * @param[out] *pId points to output rotor reference frame d
- * @param[out] *pIq points to output rotor reference frame q
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- * @return none.
- *
- * The function implements the forward Park transform.
- *
- */
-
- static __INLINE void arm_park_f32(
- float32_t Ialpha,
- float32_t Ibeta,
- float32_t * pId,
- float32_t * pIq,
- float32_t sinVal,
- float32_t cosVal)
- {
- /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
- *pId = Ialpha * cosVal + Ibeta * sinVal;
-
- /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
- *pIq = -Ialpha * sinVal + Ibeta * cosVal;
-
- }
-
- /**
- * @brief Park transform for Q31 version
- * @param[in] Ialpha input two-phase vector coordinate alpha
- * @param[in] Ibeta input two-phase vector coordinate beta
- * @param[out] *pId points to output rotor reference frame d
- * @param[out] *pIq points to output rotor reference frame q
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- * @return none.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition and subtraction, hence there is no risk of overflow.
- */
-
-
- static __INLINE void arm_park_q31(
- q31_t Ialpha,
- q31_t Ibeta,
- q31_t * pId,
- q31_t * pIq,
- q31_t sinVal,
- q31_t cosVal)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
- q31_t product3, product4; /* Temporary variables used to store intermediate results */
-
- /* Intermediate product is calculated by (Ialpha * cosVal) */
- product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
- /* Intermediate product is calculated by (Ibeta * sinVal) */
- product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
- /* Intermediate product is calculated by (Ialpha * sinVal) */
- product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
- /* Intermediate product is calculated by (Ibeta * cosVal) */
- product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
- /* Calculate pId by adding the two intermediate products 1 and 2 */
- *pId = __QADD(product1, product2);
-
- /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
- *pIq = __QSUB(product4, product3);
- }
-
- /**
- * @} end of park group
- */
-
- /**
- * @brief Converts the elements of the Q7 vector to floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q7_to_float(
- q7_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup inv_park Vector Inverse Park transform
- * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html parkInvFormula.gif
- * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
- * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
- * cosine and sine values of theta (rotor flux position).
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Park transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup inv_park
- * @{
- */
-
- /**
- * @brief Floating-point Inverse Park transform
- * @param[in] Id input coordinate of rotor reference frame d
- * @param[in] Iq input coordinate of rotor reference frame q
- * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- * @return none.
- */
-
- static __INLINE void arm_inv_park_f32(
- float32_t Id,
- float32_t Iq,
- float32_t * pIalpha,
- float32_t * pIbeta,
- float32_t sinVal,
- float32_t cosVal)
- {
- /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
- *pIalpha = Id * cosVal - Iq * sinVal;
-
- /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
- *pIbeta = Id * sinVal + Iq * cosVal;
-
- }
-
-
- /**
- * @brief Inverse Park transform for Q31 version
- * @param[in] Id input coordinate of rotor reference frame d
- * @param[in] Iq input coordinate of rotor reference frame q
- * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- * @return none.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition, hence there is no risk of overflow.
- */
-
-
- static __INLINE void arm_inv_park_q31(
- q31_t Id,
- q31_t Iq,
- q31_t * pIalpha,
- q31_t * pIbeta,
- q31_t sinVal,
- q31_t cosVal)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
- q31_t product3, product4; /* Temporary variables used to store intermediate results */
-
- /* Intermediate product is calculated by (Id * cosVal) */
- product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
- /* Intermediate product is calculated by (Iq * sinVal) */
- product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
- /* Intermediate product is calculated by (Id * sinVal) */
- product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
- /* Intermediate product is calculated by (Iq * cosVal) */
- product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
- /* Calculate pIalpha by using the two intermediate products 1 and 2 */
- *pIalpha = __QSUB(product1, product2);
-
- /* Calculate pIbeta by using the two intermediate products 3 and 4 */
- *pIbeta = __QADD(product4, product3);
-
- }
-
- /**
- * @} end of Inverse park group
- */
-
-
- /**
- * @brief Converts the elements of the Q31 vector to floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q31_to_float(
- q31_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @ingroup groupInterpolation
- */
-
- /**
- * @defgroup LinearInterpolate Linear Interpolation
- *
- * Linear interpolation is a method of curve fitting using linear polynomials.
- * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
- *
- * \par
- * \image html LinearInterp.gif "Linear interpolation"
- *
- * \par
- * A Linear Interpolate function calculates an output value(y), for the input(x)
- * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
- *
- * \par Algorithm:
- * <pre>
- * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
- * where x0, x1 are nearest values of input x
- * y0, y1 are nearest values to output y
- * </pre>
- *
- * \par
- * This set of functions implements Linear interpolation process
- * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
- * sample of data and each call to the function returns a single processed value.
- * <code>S</code> points to an instance of the Linear Interpolate function data structure.
- * <code>x</code> is the input sample value. The functions returns the output value.
- *
- * \par
- * if x is outside of the table boundary, Linear interpolation returns first value of the table
- * if x is below input range and returns last value of table if x is above range.
- */
-
- /**
- * @addtogroup LinearInterpolate
- * @{
- */
-
- /**
- * @brief Process function for the floating-point Linear Interpolation Function.
- * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
- * @param[in] x input sample to process
- * @return y processed output sample.
- *
- */
-
- static __INLINE float32_t arm_linear_interp_f32(
- arm_linear_interp_instance_f32 * S,
- float32_t x)
- {
-
- float32_t y;
- float32_t x0, x1; /* Nearest input values */
- float32_t y0, y1; /* Nearest output values */
- float32_t xSpacing = S->xSpacing; /* spacing between input values */
- int32_t i; /* Index variable */
- float32_t *pYData = S->pYData; /* pointer to output table */
-
- /* Calculation of index */
- i = (x - S->x1) / xSpacing;
-
- if(i < 0)
- {
- /* Iniatilize output for below specified range as least output value of table */
- y = pYData[0];
- }
- else if(i >= S->nValues)
- {
- /* Iniatilize output for above specified range as last output value of table */
- y = pYData[S->nValues-1];
- }
- else
- {
- /* Calculation of nearest input values */
- x0 = S->x1 + i * xSpacing;
- x1 = S->x1 + (i +1) * xSpacing;
-
- /* Read of nearest output values */
- y0 = pYData[i];
- y1 = pYData[i + 1];
-
- /* Calculation of output */
- y = y0 + (x - x0) * ((y1 - y0)/(x1-x0));
-
- }
-
- /* returns output value */
- return (y);
- }
-
- /**
- *
- * @brief Process function for the Q31 Linear Interpolation Function.
- * @param[in] *pYData pointer to Q31 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- *
- */
-
-
- static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData,
- q31_t x, uint32_t nValues)
- {
- q31_t y; /* output */
- q31_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- int32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- index = ((x & 0xFFF00000) >> 20);
-
- if(index >= (nValues - 1))
- {
- return(pYData[nValues - 1]);
- }
- else if(index < 0)
- {
- return(pYData[0]);
- }
- else
- {
-
- /* 20 bits for the fractional part */
- /* shift left by 11 to keep fract in 1.31 format */
- fract = (x & 0x000FFFFF) << 11;
-
- /* Read two nearest output values from the index in 1.31(q31) format */
- y0 = pYData[index];
- y1 = pYData[index + 1u];
-
- /* Calculation of y0 * (1-fract) and y is in 2.30 format */
- y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
- /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
- y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
- /* Convert y to 1.31 format */
- return (y << 1u);
-
- }
-
- }
-
- /**
- *
- * @brief Process function for the Q15 Linear Interpolation Function.
- * @param[in] *pYData pointer to Q15 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- *
- */
-
-
- static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues)
- {
- q63_t y; /* output */
- q15_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- int32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- index = ((x & 0xFFF00000) >> 20u);
-
- if(index >= (nValues - 1))
- {
- return(pYData[nValues - 1]);
- }
- else if(index < 0)
- {
- return(pYData[0]);
- }
- else
- {
- /* 20 bits for the fractional part */
- /* fract is in 12.20 format */
- fract = (x & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y0 = pYData[index];
- y1 = pYData[index + 1u];
-
- /* Calculation of y0 * (1-fract) and y is in 13.35 format */
- y = ((q63_t) y0 * (0xFFFFF - fract));
-
- /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
- y += ((q63_t) y1 * (fract));
-
- /* convert y to 1.15 format */
- return (y >> 20);
- }
-
-
- }
-
- /**
- *
- * @brief Process function for the Q7 Linear Interpolation Function.
- * @param[in] *pYData pointer to Q7 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- */
-
-
- static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues)
- {
- q31_t y; /* output */
- q7_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- int32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- index = ((x & 0xFFF00000) >> 20u);
-
-
- if(index >= (nValues - 1))
- {
- return(pYData[nValues - 1]);
- }
- else if(index < 0)
- {
- return(pYData[0]);
- }
- else
- {
-
- /* 20 bits for the fractional part */
- /* fract is in 12.20 format */
- fract = (x & 0x000FFFFF);
-
- /* Read two nearest output values from the index and are in 1.7(q7) format */
- y0 = pYData[index];
- y1 = pYData[index + 1u];
-
- /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
- y = ((y0 * (0xFFFFF - fract)));
-
- /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
- y += (y1 * fract);
-
- /* convert y to 1.7(q7) format */
- return (y >> 20u);
-
- }
-
- }
- /**
- * @} end of LinearInterpolate group
- */
-
- /**
- * @brief Fast approximation to the trigonometric sine function for floating-point data.
- * @param[in] x input value in radians.
- * @return sin(x).
- */
-
- float32_t arm_sin_f32(
- float32_t x);
-
- /**
- * @brief Fast approximation to the trigonometric sine function for Q31 data.
- * @param[in] x Scaled input value in radians.
- * @return sin(x).
- */
-
- q31_t arm_sin_q31(
- q31_t x);
-
- /**
- * @brief Fast approximation to the trigonometric sine function for Q15 data.
- * @param[in] x Scaled input value in radians.
- * @return sin(x).
- */
-
- q15_t arm_sin_q15(
- q15_t x);
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for floating-point data.
- * @param[in] x input value in radians.
- * @return cos(x).
- */
-
- float32_t arm_cos_f32(
- float32_t x);
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for Q31 data.
- * @param[in] x Scaled input value in radians.
- * @return cos(x).
- */
-
- q31_t arm_cos_q31(
- q31_t x);
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for Q15 data.
- * @param[in] x Scaled input value in radians.
- * @return cos(x).
- */
-
- q15_t arm_cos_q15(
- q15_t x);
-
-
- /**
- * @ingroup groupFastMath
- */
-
-
- /**
- * @defgroup SQRT Square Root
- *
- * Computes the square root of a number.
- * There are separate functions for Q15, Q31, and floating-point data types.
- * The square root function is computed using the Newton-Raphson algorithm.
- * This is an iterative algorithm of the form:
- * <pre>
- * x1 = x0 - f(x0)/f'(x0)
- * </pre>
- * where <code>x1</code> is the current estimate,
- * <code>x0</code> is the previous estimate and
- * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
- * For the square root function, the algorithm reduces to:
- * <pre>
- * x0 = in/2 [initial guess]
- * x1 = 1/2 * ( x0 + in / x0) [each iteration]
- * </pre>
- */
-
-
- /**
- * @addtogroup SQRT
- * @{
- */
-
- /**
- * @brief Floating-point square root function.
- * @param[in] in input value.
- * @param[out] *pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
-
- static __INLINE arm_status arm_sqrt_f32(
- float32_t in, float32_t *pOut)
- {
- if(in > 0)
- {
-
-// #if __FPU_USED
- #if (__FPU_USED == 1) && defined ( __CC_ARM )
- *pOut = __sqrtf(in);
- #else
- *pOut = sqrtf(in);
- #endif
-
- return (ARM_MATH_SUCCESS);
- }
- else
- {
- *pOut = 0.0f;
- return (ARM_MATH_ARGUMENT_ERROR);
- }
-
- }
-
-
- /**
- * @brief Q31 square root function.
- * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
- * @param[out] *pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
- arm_status arm_sqrt_q31(
- q31_t in, q31_t *pOut);
-
- /**
- * @brief Q15 square root function.
- * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
- * @param[out] *pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
- arm_status arm_sqrt_q15(
- q15_t in, q15_t *pOut);
-
- /**
- * @} end of SQRT group
- */
-
-
-
-
-
-
- /**
- * @brief floating-point Circular write function.
- */
-
- static __INLINE void arm_circularWrite_f32(
- int32_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const int32_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if(wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = wOffset;
- }
-
-
-
- /**
- * @brief floating-point Circular Read function.
- */
- static __INLINE void arm_circularRead_f32(
- int32_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- int32_t * dst,
- int32_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t rOffset, dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
- dst_end = (int32_t) (dst_base + dst_length);
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if(dst == (int32_t *) dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update rOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if(rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
- /**
- * @brief Q15 Circular write function.
- */
-
- static __INLINE void arm_circularWrite_q15(
- q15_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const q15_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if(wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = wOffset;
- }
-
-
-
- /**
- * @brief Q15 Circular Read function.
- */
- static __INLINE void arm_circularRead_q15(
- q15_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- q15_t * dst,
- q15_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0;
- int32_t rOffset, dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
-
- dst_end = (int32_t) (dst_base + dst_length);
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if(dst == (q15_t *) dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if(rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
-
- /**
- * @brief Q7 Circular write function.
- */
-
- static __INLINE void arm_circularWrite_q7(
- q7_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const q7_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if(wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = wOffset;
- }
-
-
-
- /**
- * @brief Q7 Circular Read function.
- */
- static __INLINE void arm_circularRead_q7(
- q7_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- q7_t * dst,
- q7_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0;
- int32_t rOffset, dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
-
- dst_end = (int32_t) (dst_base + dst_length);
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if(dst == (q7_t *) dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update rOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if(rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
-
- /**
- * @brief Sum of the squares of the elements of a Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_power_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
-
- /**
- * @brief Sum of the squares of the elements of a floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_power_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
- /**
- * @brief Sum of the squares of the elements of a Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_power_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
-
- /**
- * @brief Sum of the squares of the elements of a Q7 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_power_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
- /**
- * @brief Mean value of a Q7 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_mean_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult);
-
- /**
- * @brief Mean value of a Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
- void arm_mean_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
- /**
- * @brief Mean value of a Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
- void arm_mean_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
- /**
- * @brief Mean value of a floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
- void arm_mean_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
- /**
- * @brief Variance of the elements of a floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_var_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
- /**
- * @brief Variance of the elements of a Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_var_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
-
- /**
- * @brief Variance of the elements of a Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_var_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
- /**
- * @brief Root Mean Square of the elements of a floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_rms_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
- /**
- * @brief Root Mean Square of the elements of a Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_rms_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
- /**
- * @brief Root Mean Square of the elements of a Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_rms_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
- /**
- * @brief Standard deviation of the elements of a floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_std_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
- /**
- * @brief Standard deviation of the elements of a Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_std_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
- /**
- * @brief Standard deviation of the elements of a Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_std_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
- /**
- * @brief Floating-point complex magnitude
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
- void arm_cmplx_mag_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex magnitude
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
- void arm_cmplx_mag_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q15 complex magnitude
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
- void arm_cmplx_mag_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q15 complex dot product
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] *realResult real part of the result returned here
- * @param[out] *imagResult imaginary part of the result returned here
- * @return none.
- */
-
- void arm_cmplx_dot_prod_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- uint32_t numSamples,
- q31_t * realResult,
- q31_t * imagResult);
-
- /**
- * @brief Q31 complex dot product
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] *realResult real part of the result returned here
- * @param[out] *imagResult imaginary part of the result returned here
- * @return none.
- */
-
- void arm_cmplx_dot_prod_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- uint32_t numSamples,
- q63_t * realResult,
- q63_t * imagResult);
-
- /**
- * @brief Floating-point complex dot product
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] *realResult real part of the result returned here
- * @param[out] *imagResult imaginary part of the result returned here
- * @return none.
- */
-
- void arm_cmplx_dot_prod_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- uint32_t numSamples,
- float32_t * realResult,
- float32_t * imagResult);
-
- /**
- * @brief Q15 complex-by-real multiplication
- * @param[in] *pSrcCmplx points to the complex input vector
- * @param[in] *pSrcReal points to the real input vector
- * @param[out] *pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- * @return none.
- */
-
- void arm_cmplx_mult_real_q15(
- q15_t * pSrcCmplx,
- q15_t * pSrcReal,
- q15_t * pCmplxDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex-by-real multiplication
- * @param[in] *pSrcCmplx points to the complex input vector
- * @param[in] *pSrcReal points to the real input vector
- * @param[out] *pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- * @return none.
- */
-
- void arm_cmplx_mult_real_q31(
- q31_t * pSrcCmplx,
- q31_t * pSrcReal,
- q31_t * pCmplxDst,
- uint32_t numSamples);
-
- /**
- * @brief Floating-point complex-by-real multiplication
- * @param[in] *pSrcCmplx points to the complex input vector
- * @param[in] *pSrcReal points to the real input vector
- * @param[out] *pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- * @return none.
- */
-
- void arm_cmplx_mult_real_f32(
- float32_t * pSrcCmplx,
- float32_t * pSrcReal,
- float32_t * pCmplxDst,
- uint32_t numSamples);
-
- /**
- * @brief Minimum value of a Q7 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *result is output pointer
- * @param[in] index is the array index of the minimum value in the input buffer.
- * @return none.
- */
-
- void arm_min_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * result,
- uint32_t * index);
-
- /**
- * @brief Minimum value of a Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output pointer
- * @param[in] *pIndex is the array index of the minimum value in the input buffer.
- * @return none.
- */
-
- void arm_min_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult,
- uint32_t * pIndex);
-
- /**
- * @brief Minimum value of a Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output pointer
- * @param[out] *pIndex is the array index of the minimum value in the input buffer.
- * @return none.
- */
- void arm_min_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult,
- uint32_t * pIndex);
-
- /**
- * @brief Minimum value of a floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output pointer
- * @param[out] *pIndex is the array index of the minimum value in the input buffer.
- * @return none.
- */
-
- void arm_min_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult,
- uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in] *pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult maximum value returned here
- * @param[out] *pIndex index of maximum value returned here
- * @return none.
- */
-
- void arm_max_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult,
- uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in] *pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult maximum value returned here
- * @param[out] *pIndex index of maximum value returned here
- * @return none.
- */
-
- void arm_max_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult,
- uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in] *pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult maximum value returned here
- * @param[out] *pIndex index of maximum value returned here
- * @return none.
- */
-
- void arm_max_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult,
- uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in] *pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult maximum value returned here
- * @param[out] *pIndex index of maximum value returned here
- * @return none.
- */
-
- void arm_max_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult,
- uint32_t * pIndex);
-
- /**
- * @brief Q15 complex-by-complex multiplication
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
- void arm_cmplx_mult_cmplx_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex-by-complex multiplication
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
- void arm_cmplx_mult_cmplx_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Floating-point complex-by-complex multiplication
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
- void arm_cmplx_mult_cmplx_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Converts the elements of the floating-point vector to Q31 vector.
- * @param[in] *pSrc points to the floating-point input vector
- * @param[out] *pDst points to the Q31 output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- */
- void arm_float_to_q31(
- float32_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Converts the elements of the floating-point vector to Q15 vector.
- * @param[in] *pSrc points to the floating-point input vector
- * @param[out] *pDst points to the Q15 output vector
- * @param[in] blockSize length of the input vector
- * @return none
- */
- void arm_float_to_q15(
- float32_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Converts the elements of the floating-point vector to Q7 vector.
- * @param[in] *pSrc points to the floating-point input vector
- * @param[out] *pDst points to the Q7 output vector
- * @param[in] blockSize length of the input vector
- * @return none
- */
- void arm_float_to_q7(
- float32_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q31 vector to Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q31_to_q15(
- q31_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Converts the elements of the Q31 vector to Q7 vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q31_to_q7(
- q31_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Converts the elements of the Q15 vector to floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q15_to_float(
- q15_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q15 vector to Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q15_to_q31(
- q15_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q15 vector to Q7 vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q15_to_q7(
- q15_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @ingroup groupInterpolation
- */
-
- /**
- * @defgroup BilinearInterpolate Bilinear Interpolation
- *
- * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
- * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
- * determines values between the grid points.
- * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
- * Bilinear interpolation is often used in image processing to rescale images.
- * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
- *
- * <b>Algorithm</b>
- * \par
- * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
- * For floating-point, the instance structure is defined as:
- * <pre>
- * typedef struct
- * {
- * uint16_t numRows;
- * uint16_t numCols;
- * float32_t *pData;
- * } arm_bilinear_interp_instance_f32;
- * </pre>
- *
- * \par
- * where <code>numRows</code> specifies the number of rows in the table;
- * <code>numCols</code> specifies the number of columns in the table;
- * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
- * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
- * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
- *
- * \par
- * Let <code>(x, y)</code> specify the desired interpolation point. Then define:
- * <pre>
- * XF = floor(x)
- * YF = floor(y)
- * </pre>
- * \par
- * The interpolated output point is computed as:
- * <pre>
- * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
- * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
- * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
- * + f(XF+1, YF+1) * (x-XF)*(y-YF)
- * </pre>
- * Note that the coordinates (x, y) contain integer and fractional components.
- * The integer components specify which portion of the table to use while the
- * fractional components control the interpolation processor.
- *
- * \par
- * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
- */
-
- /**
- * @addtogroup BilinearInterpolate
- * @{
- */
-
- /**
- *
- * @brief Floating-point bilinear interpolation.
- * @param[in,out] *S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate.
- * @param[in] Y interpolation coordinate.
- * @return out interpolated value.
- */
-
-
- static __INLINE float32_t arm_bilinear_interp_f32(
- const arm_bilinear_interp_instance_f32 * S,
- float32_t X,
- float32_t Y)
- {
- float32_t out;
- float32_t f00, f01, f10, f11;
- float32_t *pData = S->pData;
- int32_t xIndex, yIndex, index;
- float32_t xdiff, ydiff;
- float32_t b1, b2, b3, b4;
-
- xIndex = (int32_t) X;
- yIndex = (int32_t) Y;
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1))
- {
- return(0);
- }
-
- /* Calculation of index for two nearest points in X-direction */
- index = (xIndex - 1) + (yIndex-1) * S->numCols ;
-
-
- /* Read two nearest points in X-direction */
- f00 = pData[index];
- f01 = pData[index + 1];
-
- /* Calculation of index for two nearest points in Y-direction */
- index = (xIndex-1) + (yIndex) * S->numCols;
-
-
- /* Read two nearest points in Y-direction */
- f10 = pData[index];
- f11 = pData[index + 1];
-
- /* Calculation of intermediate values */
- b1 = f00;
- b2 = f01 - f00;
- b3 = f10 - f00;
- b4 = f00 - f01 - f10 + f11;
-
- /* Calculation of fractional part in X */
- xdiff = X - xIndex;
-
- /* Calculation of fractional part in Y */
- ydiff = Y - yIndex;
-
- /* Calculation of bi-linear interpolated output */
- out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
- /* return to application */
- return (out);
-
- }
-
- /**
- *
- * @brief Q31 bilinear interpolation.
- * @param[in,out] *S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
-
- static __INLINE q31_t arm_bilinear_interp_q31(
- arm_bilinear_interp_instance_q31 * S,
- q31_t X,
- q31_t Y)
- {
- q31_t out; /* Temporary output */
- q31_t acc = 0; /* output */
- q31_t xfract, yfract; /* X, Y fractional parts */
- q31_t x1, x2, y1, y2; /* Nearest output values */
- int32_t rI, cI; /* Row and column indices */
- q31_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & 0xFFF00000) >> 20u);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & 0xFFF00000) >> 20u);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))
- {
- return(0);
- }
-
- /* 20 bits for the fractional part */
- /* shift left xfract by 11 to keep 1.31 format */
- xfract = (X & 0x000FFFFF) << 11u;
-
- /* Read two nearest output values from the index */
- x1 = pYData[(rI) + nCols * (cI)];
- x2 = pYData[(rI) + nCols * (cI) + 1u];
-
- /* 20 bits for the fractional part */
- /* shift left yfract by 11 to keep 1.31 format */
- yfract = (Y & 0x000FFFFF) << 11u;
-
- /* Read two nearest output values from the index */
- y1 = pYData[(rI) + nCols * (cI + 1)];
- y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
- out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
- acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
- /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
- /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
- /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
- /* Convert acc to 1.31(q31) format */
- return (acc << 2u);
-
- }
-
- /**
- * @brief Q15 bilinear interpolation.
- * @param[in,out] *S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
-
- static __INLINE q15_t arm_bilinear_interp_q15(
- arm_bilinear_interp_instance_q15 * S,
- q31_t X,
- q31_t Y)
- {
- q63_t acc = 0; /* output */
- q31_t out; /* Temporary output */
- q15_t x1, x2, y1, y2; /* Nearest output values */
- q31_t xfract, yfract; /* X, Y fractional parts */
- int32_t rI, cI; /* Row and column indices */
- q15_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & 0xFFF00000) >> 20);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & 0xFFF00000) >> 20);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))
- {
- return(0);
- }
-
- /* 20 bits for the fractional part */
- /* xfract should be in 12.20 format */
- xfract = (X & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- x1 = pYData[(rI) + nCols * (cI)];
- x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-
- /* 20 bits for the fractional part */
- /* yfract should be in 12.20 format */
- yfract = (Y & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y1 = pYData[(rI) + nCols * (cI + 1)];
- y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
- /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
- /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
- out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
- acc = ((q63_t) out * (0xFFFFF - yfract));
-
- /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
- acc += ((q63_t) out * (xfract));
-
- /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
- acc += ((q63_t) out * (yfract));
-
- /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
- acc += ((q63_t) out * (yfract));
-
- /* acc is in 13.51 format and down shift acc by 36 times */
- /* Convert out to 1.15 format */
- return (acc >> 36);
-
- }
-
- /**
- * @brief Q7 bilinear interpolation.
- * @param[in,out] *S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
-
- static __INLINE q7_t arm_bilinear_interp_q7(
- arm_bilinear_interp_instance_q7 * S,
- q31_t X,
- q31_t Y)
- {
- q63_t acc = 0; /* output */
- q31_t out; /* Temporary output */
- q31_t xfract, yfract; /* X, Y fractional parts */
- q7_t x1, x2, y1, y2; /* Nearest output values */
- int32_t rI, cI; /* Row and column indices */
- q7_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & 0xFFF00000) >> 20);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & 0xFFF00000) >> 20);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))
- {
- return(0);
- }
-
- /* 20 bits for the fractional part */
- /* xfract should be in 12.20 format */
- xfract = (X & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- x1 = pYData[(rI) + nCols * (cI)];
- x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-
- /* 20 bits for the fractional part */
- /* yfract should be in 12.20 format */
- yfract = (Y & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y1 = pYData[(rI) + nCols * (cI + 1)];
- y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
- out = ((x1 * (0xFFFFF - xfract)));
- acc = (((q63_t) out * (0xFFFFF - yfract)));
-
- /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
- out = ((x2 * (0xFFFFF - yfract)));
- acc += (((q63_t) out * (xfract)));
-
- /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
- out = ((y1 * (0xFFFFF - xfract)));
- acc += (((q63_t) out * (yfract)));
-
- /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
- out = ((y2 * (yfract)));
- acc += (((q63_t) out * (xfract)));
-
- /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
- return (acc >> 40);
-
- }
-
- /**
- * @} end of BilinearInterpolate group
- */
-
-
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* _ARM_MATH_H */
-
-
-/**
- *
- * End of file.
- */
+++ /dev/null
-/**************************************************************************//**
- * @file core_cm0.h
- * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version V2.10
- * @date 19. July 2011
- *
- * @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-
-/** \mainpage CMSIS Cortex-M0
-
- This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
- It consists of:
-
- - Cortex-M Core Register Definitions
- - Cortex-M functions
- - Cortex-M instructions
-
- The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease
- access to the Cortex-M Core
- */
-
-/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions
- CMSIS violates following MISRA-C2004 Rules:
-
- - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
-
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
- This file defines all structures and symbols for CMSIS core:
- - CMSIS version number
- - Cortex-M core
- - Cortex-M core Revision Number
- @{
- */
-
-/* CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x00) /*!< Cortex core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
-#define __FPU_USED 0
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- /* add preprocessor checks */
-#endif
-
-#include <stdint.h> /*!< standard types definitions */
-#include "core_cmInstr.h" /*!< Core Instruction Access */
-#include "core_cmFunc.h" /*!< Core Function Access */
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM0_REV
- #define __CM0_REV 0x0000
- #warning "__CM0_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-#ifdef __cplusplus
- #define __I volatile /*!< defines 'read only' permissions */
-#else
- #define __I volatile const /*!< defines 'read only' permissions */
-#endif
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
-
-/*@} end of group CMSIS_core_definitions */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE CMSIS Core
- Type definitions for the Cortex-M Core Registers
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC CMSIS NVIC
- Type definitions for the Cortex-M NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[31];
- __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31];
- __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[31];
- __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31];
- uint32_t RESERVED4[64];
- __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB CMSIS SCB
- Type definitions for the Cortex-M System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- uint32_t RESERVED0;
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick CMSIS SysTick
- Type definitions for the Cortex-M System Timer Registers
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug CMSIS Core Debug
- Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP
- and not via processor. Therefore they are not covered by the Cortex-M0 header file.
- @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- @{
- */
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
- @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
-#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
-#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
-
-
-/** \brief Enable External Interrupt
-
- This function enables a device specific interrupt in the NVIC interrupt controller.
- The interrupt number cannot be a negative value.
-
- \param [in] IRQn Number of the external interrupt to enable
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Disable External Interrupt
-
- This function disables a device specific interrupt in the NVIC interrupt controller.
- The interrupt number cannot be a negative value.
-
- \param [in] IRQn Number of the external interrupt to disable
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Get Pending Interrupt
-
- This function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Number of the interrupt for get pending
- \return 0 Interrupt status is not pending
- \return 1 Interrupt status is pending
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief Set Pending Interrupt
-
- This function sets the pending bit for the specified interrupt.
- The interrupt number cannot be a negative value.
-
- \param [in] IRQn Number of the interrupt for set pending
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Clear Pending Interrupt
-
- This function clears the pending bit for the specified interrupt.
- The interrupt number cannot be a negative value.
-
- \param [in] IRQn Number of the interrupt for clear pending
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief Set Interrupt Priority
-
- This function sets the priority for the specified interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
- Note: The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Number of the interrupt for set priority
- \param [in] priority Priority to set
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
- else {
- NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief Get Interrupt Priority
-
- This function reads the priority for the specified interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
- The returned priority value is automatically aligned to the implemented
- priority bits of the microcontroller.
-
- \param [in] IRQn Number of the interrupt for get priority
- \return Interrupt Priority
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
- else {
- return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/** \brief System Reset
-
- This function initiate a system reset request to reset the MCU.
- */
-static __INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief System Tick Configuration
-
- This function initialises the system tick timer and its interrupt and start the system tick timer.
- Counter is in free running mode to generate periodical interrupts.
-
- \param [in] ticks Number of ticks between two interrupts
- \return 0 Function succeeded
- \return 1 Function failed
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
+++ /dev/null
-/**************************************************************************//**
- * @file core_cm3.c
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
- * @version V1.30
- * @date 30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include <stdint.h>
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-__ASM uint32_t __get_PSP(void)
-{
- mrs r0, psp
- bx lr
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
- msr psp, r0
- bx lr
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-__ASM uint32_t __get_MSP(void)
-{
- mrs r0, msp
- bx lr
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
- msr msp, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-__ASM uint32_t __REV16(uint16_t value)
-{
- rev16 r0, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-__ASM int32_t __REVSH(int16_t value)
-{
- revsh r0, r0
- bx lr
-}
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-__ASM void __CLREX(void)
-{
- clrex
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-__ASM uint32_t __get_BASEPRI(void)
-{
- mrs r0, basepri
- bx lr
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-__ASM void __set_BASEPRI(uint32_t basePri)
-{
- msr basepri, r0
- bx lr
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-__ASM uint32_t __get_PRIMASK(void)
-{
- mrs r0, primask
- bx lr
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
- msr primask, r0
- bx lr
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-__ASM uint32_t __get_FAULTMASK(void)
-{
- mrs r0, faultmask
- bx lr
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-__ASM void __set_FAULTMASK(uint32_t faultMask)
-{
- msr faultmask, r0
- bx lr
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-__ASM uint32_t __get_CONTROL(void)
-{
- mrs r0, control
- bx lr
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-__ASM void __set_CONTROL(uint32_t control)
-{
- msr control, r0
- bx lr
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#pragma diag_suppress=Pe940
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
- __ASM("mrs r0, psp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM("msr psp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
- __ASM("mrs r0, msp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM("msr msp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- __ASM("rev16 r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- __ASM("rbit r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- __ASM("ldrexb r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- __ASM("ldrexh r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- __ASM("ldrex r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- __ASM("strexb r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- __ASM("strexh r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- __ASM("strex r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void) __attribute__( ( naked ) );
-uint32_t __get_PSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, psp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n\t"
- "BX lr \n\t" : : "r" (topOfProcStack) );
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void) __attribute__( ( naked ) );
-uint32_t __get_MSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, msp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n\t"
- "BX lr \n\t" : : "r" (topOfMainStack) );
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-uint32_t __get_BASEPRI(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-uint32_t __get_PRIMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-uint32_t __get_FAULTMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-uint32_t __get_CONTROL(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-uint32_t __REV(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-int32_t __REVSH(int16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- uint8_t result=0;
-
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- uint16_t result=0;
-
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
+++ /dev/null
-/**************************************************************************//**
- * @file core_cm3.h
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V2.10
- * @date 19. July 2011
- *
- * @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-
-/** \mainpage CMSIS Cortex-M3
-
- This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
- It consists of:
-
- - Cortex-M Core Register Definitions
- - Cortex-M functions
- - Cortex-M instructions
-
- The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
- access to the Cortex-M Core
- */
-
-/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions
- CMSIS violates following MISRA-C2004 Rules:
-
- - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
-
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
- This file defines all structures and symbols for CMSIS core:
- - CMSIS version number
- - Cortex-M core
- - Cortex-M core Revision Number
- @{
- */
-
-/* CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x03) /*!< Cortex core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
-#define __FPU_USED 0
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- /* add preprocessor checks */
-#endif
-
-#include <stdint.h> /*!< standard types definitions */
-#include "core_cmInstr.h" /*!< Core Instruction Access */
-#include "core_cmFunc.h" /*!< Core Function Access */
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM3_REV
- #define __CM3_REV 0x0200
- #warning "__CM3_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-#ifdef __cplusplus
- #define __I volatile /*!< defines 'read only' permissions */
-#else
- #define __I volatile const /*!< defines 'read only' permissions */
-#endif
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
-
-/*@} end of group CMSIS_core_definitions */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE CMSIS Core
- Type definitions for the Cortex-M Core Registers
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC CMSIS NVIC
- Type definitions for the Cortex-M NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB CMSIS SCB
- Type definitions for the Cortex-M System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5];
- __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB
- Type definitions for the Cortex-M System Control and ID Register not in the SCB
- @{
- */
-
-/** \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1];
- __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
- __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-#else
- uint32_t RESERVED1[1];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick CMSIS SysTick
- Type definitions for the Cortex-M System Timer Registers
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM CMSIS ITM
- Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __O union
- {
- __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */
-#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU CMSIS MPU
- Type definitions for the Cortex-M Memory Protection Unit (MPU)
- @{
- */
-
-/** \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug CMSIS Core Debug
- Type definitions for the Cortex-M Core Debug Registers
- @{
- */
-
-/** \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
- @{
- */
-
-/** \brief Set Priority Grouping
-
- This function sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
- \param [in] PriorityGroup Priority grouping field
- */
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/** \brief Get Priority Grouping
-
- This function gets the priority grouping from NVIC Interrupt Controller.
- Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
-
- \return Priority grouping field
- */
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
-}
-
-
-/** \brief Enable External Interrupt
-
- This function enables a device specific interrupt in the NVIC interrupt controller.
- The interrupt number cannot be a negative value.
-
- \param [in] IRQn Number of the external interrupt to enable
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-
-/** \brief Disable External Interrupt
-
- This function disables a device specific interrupt in the NVIC interrupt controller.
- The interrupt number cannot be a negative value.
-
- \param [in] IRQn Number of the external interrupt to disable
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief Get Pending Interrupt
-
- This function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Number of the interrupt for get pending
- \return 0 Interrupt status is not pending
- \return 1 Interrupt status is pending
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief Set Pending Interrupt
-
- This function sets the pending bit for the specified interrupt.
- The interrupt number cannot be a negative value.
-
- \param [in] IRQn Number of the interrupt for set pending
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief Clear Pending Interrupt
-
- This function clears the pending bit for the specified interrupt.
- The interrupt number cannot be a negative value.
-
- \param [in] IRQn Number of the interrupt for clear pending
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief Get Active Interrupt
-
- This function reads the active register in NVIC and returns the active bit.
- \param [in] IRQn Number of the interrupt for get active
- \return 0 Interrupt status is not active
- \return 1 Interrupt status is active
- */
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief Set Interrupt Priority
-
- This function sets the priority for the specified interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
- Note: The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Number of the interrupt for set priority
- \param [in] priority Priority to set
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
- else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
-}
-
-
-/** \brief Get Interrupt Priority
-
- This function reads the priority for the specified interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
- The returned priority value is automatically aligned to the implemented
- priority bits of the microcontroller.
-
- \param [in] IRQn Number of the interrupt for get priority
- \return Interrupt Priority
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
- else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/** \brief Encode Priority
-
- This function encodes the priority for an interrupt with the given priority group,
- preemptive priority value and sub priority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
- The returned priority value can be used for NVIC_SetPriority(...) function
-
- \param [in] PriorityGroup Used priority group
- \param [in] PreemptPriority Preemptive priority value (starting from 0)
- \param [in] SubPriority Sub priority value (starting from 0)
- \return Encoded priority for the interrupt
- */
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
- );
-}
-
-
-/** \brief Decode Priority
-
- This function decodes an interrupt priority value with the given priority group to
- preemptive priority value and sub priority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
- The priority value can be retrieved with NVIC_GetPriority(...) function
-
- \param [in] Priority Priority value
- \param [in] PriorityGroup Used priority group
- \param [out] pPreemptPriority Preemptive priority value (starting from 0)
- \param [out] pSubPriority Sub priority value (starting from 0)
- */
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
-}
-
-
-/** \brief System Reset
-
- This function initiate a system reset request to reset the MCU.
- */
-static __INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief System Tick Configuration
-
- This function initialises the system tick timer and its interrupt and start the system tick timer.
- Counter is in free running mode to generate periodical interrupts.
-
- \param [in] ticks Number of ticks between two interrupts
- \return 0 Function succeeded
- \return 1 Function failed
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
-
-
-/** \brief ITM Send Character
-
- This function transmits a character via the ITM channel 0.
- It just returns when no debugger is connected that has booked the output.
- It is blocking when a debugger is connected, but the previous character send is not transmitted.
-
- \param [in] ch Character to transmit
- \return Character to transmit
- */
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
- }
- return (ch);
-}
-
-
-/** \brief ITM Receive Character
-
- This function inputs a character via external variable ITM_RxBuffer.
- It just returns when no debugger is connected that has booked the output.
- It is blocking when a debugger is connected, but the previous character send is not transmitted.
-
- \return Received character
- \return -1 No character received
- */
-static __INLINE int32_t ITM_ReceiveChar (void) {
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/** \brief ITM Check Character
-
- This function checks external variable ITM_RxBuffer whether a character is available or not.
- It returns '1' if a character is available and '0' if no character is available.
-
- \return 0 No character available
- \return 1 Character available
- */
-static __INLINE int32_t ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
+++ /dev/null
-/**************************************************************************//**
- * @file core_cm4.h
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version V2.10
- * @date 19. July 2011
- *
- * @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-
-/** \mainpage CMSIS Cortex-M4
-
- This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
- It consists of:
-
- - Cortex-M Core Register Definitions
- - Cortex-M functions
- - Cortex-M instructions
- - Cortex-M SIMD instructions
-
- The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease
- access to the Cortex-M Core
- */
-
-/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions
- CMSIS violates following MISRA-C2004 Rules:
-
- - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
-
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
- This file defines all structures and symbols for CMSIS core:
- - CMSIS version number
- - Cortex-M core
- - Cortex-M core Revision Number
- @{
- */
-
-/* CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x04) /*!< Cortex core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __TASKING__ )
- /* add preprocessor checks to define __FPU_USED */
- #define __FPU_USED 0
-#endif
-
-#include <stdint.h> /*!< standard types definitions */
-#include <core_cmInstr.h> /*!< Core Instruction Access */
-#include <core_cmFunc.h> /*!< Core Function Access */
-#include <core_cm4_simd.h> /*!< Compiler specific SIMD Intrinsics */
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM4_REV
- #define __CM4_REV 0x0000
- #warning "__CM4_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-#ifdef __cplusplus
- #define __I volatile /*!< defines 'read only' permissions */
-#else
- #define __I volatile const /*!< defines 'read only' permissions */
-#endif
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
-
-/*@} end of group CMSIS_core_definitions */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core FPU Register
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE CMSIS Core
- Type definitions for the Cortex-M Core Registers
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC CMSIS NVIC
- Type definitions for the Cortex-M NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB CMSIS SCB
- Type definitions for the Cortex-M System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5];
- __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB
- Type definitions for the Cortex-M System Control and ID Register not in the SCB
- @{
- */
-
-/** \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1];
- __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick CMSIS SysTick
- Type definitions for the Cortex-M System Timer Registers
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM CMSIS ITM
- Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __O union
- {
- __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */
-#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU CMSIS MPU
- Type definitions for the Cortex-M Memory Protection Unit (MPU)
- @{
- */
-
-/** \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU CMSIS FPU
- Type definitions for the Cortex-M Floating Point Unit (FPU)
- @{
- */
-
-/** \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1];
- __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug CMSIS Core Debug
- Type definitions for the Cortex-M Core Debug Registers
- @{
- */
-
-/** \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-#if (__FPU_PRESENT == 1)
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
- @{
- */
-
-/** \brief Set Priority Grouping
-
- This function sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
- \param [in] PriorityGroup Priority grouping field
- */
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/** \brief Get Priority Grouping
-
- This function gets the priority grouping from NVIC Interrupt Controller.
- Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
-
- \return Priority grouping field
- */
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
-}
-
-
-/** \brief Enable External Interrupt
-
- This function enables a device specific interrupt in the NVIC interrupt controller.
- The interrupt number cannot be a negative value.
-
- \param [in] IRQn Number of the external interrupt to enable
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
- NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
-}
-
-
-/** \brief Disable External Interrupt
-
- This function disables a device specific interrupt in the NVIC interrupt controller.
- The interrupt number cannot be a negative value.
-
- \param [in] IRQn Number of the external interrupt to disable
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief Get Pending Interrupt
-
- This function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Number of the interrupt for get pending
- \return 0 Interrupt status is not pending
- \return 1 Interrupt status is pending
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief Set Pending Interrupt
-
- This function sets the pending bit for the specified interrupt.
- The interrupt number cannot be a negative value.
-
- \param [in] IRQn Number of the interrupt for set pending
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief Clear Pending Interrupt
-
- This function clears the pending bit for the specified interrupt.
- The interrupt number cannot be a negative value.
-
- \param [in] IRQn Number of the interrupt for clear pending
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief Get Active Interrupt
-
- This function reads the active register in NVIC and returns the active bit.
- \param [in] IRQn Number of the interrupt for get active
- \return 0 Interrupt status is not active
- \return 1 Interrupt status is active
- */
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief Set Interrupt Priority
-
- This function sets the priority for the specified interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
- Note: The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Number of the interrupt for set priority
- \param [in] priority Priority to set
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
- else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
-}
-
-
-/** \brief Get Interrupt Priority
-
- This function reads the priority for the specified interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
- The returned priority value is automatically aligned to the implemented
- priority bits of the microcontroller.
-
- \param [in] IRQn Number of the interrupt for get priority
- \return Interrupt Priority
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
- else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/** \brief Encode Priority
-
- This function encodes the priority for an interrupt with the given priority group,
- preemptive priority value and sub priority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
- The returned priority value can be used for NVIC_SetPriority(...) function
-
- \param [in] PriorityGroup Used priority group
- \param [in] PreemptPriority Preemptive priority value (starting from 0)
- \param [in] SubPriority Sub priority value (starting from 0)
- \return Encoded priority for the interrupt
- */
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
- );
-}
-
-
-/** \brief Decode Priority
-
- This function decodes an interrupt priority value with the given priority group to
- preemptive priority value and sub priority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
- The priority value can be retrieved with NVIC_GetPriority(...) function
-
- \param [in] Priority Priority value
- \param [in] PriorityGroup Used priority group
- \param [out] pPreemptPriority Preemptive priority value (starting from 0)
- \param [out] pSubPriority Sub priority value (starting from 0)
- */
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
-}
-
-
-/** \brief System Reset
-
- This function initiate a system reset request to reset the MCU.
- */
-static __INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief System Tick Configuration
-
- This function initialises the system tick timer and its interrupt and start the system tick timer.
- Counter is in free running mode to generate periodical interrupts.
-
- \param [in] ticks Number of ticks between two interrupts
- \return 0 Function succeeded
- \return 1 Function failed
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
-
-
-/** \brief ITM Send Character
-
- This function transmits a character via the ITM channel 0.
- It just returns when no debugger is connected that has booked the output.
- It is blocking when a debugger is connected, but the previous character send is not transmitted.
-
- \param [in] ch Character to transmit
- \return Character to transmit
- */
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
- }
- return (ch);
-}
-
-
-/** \brief ITM Receive Character
-
- This function inputs a character via external variable ITM_RxBuffer.
- It just returns when no debugger is connected that has booked the output.
- It is blocking when a debugger is connected, but the previous character send is not transmitted.
-
- \return Received character
- \return -1 No character received
- */
-static __INLINE int32_t ITM_ReceiveChar (void) {
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/** \brief ITM Check Character
-
- This function checks external variable ITM_RxBuffer whether a character is available or not.
- It returns '1' if a character is available and '0' if no character is available.
-
- \return 0 No character available
- \return 1 Character available
- */
-static __INLINE int32_t ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
+++ /dev/null
-/**************************************************************************//**
- * @file core_cm4_simd.h
- * @brief CMSIS Cortex-M4 SIMD Header File
- * @version V2.10
- * @date 19. July 2011
- *
- * @note
- * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM4_SIMD_H
-#define __CORE_CM4_SIMD_H
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- ******************************************************************************/
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
- Access to dedicated SIMD instructions
- @{
-*/
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/
-#define __SADD8 __sadd8
-#define __QADD8 __qadd8
-#define __SHADD8 __shadd8
-#define __UADD8 __uadd8
-#define __UQADD8 __uqadd8
-#define __UHADD8 __uhadd8
-#define __SSUB8 __ssub8
-#define __QSUB8 __qsub8
-#define __SHSUB8 __shsub8
-#define __USUB8 __usub8
-#define __UQSUB8 __uqsub8
-#define __UHSUB8 __uhsub8
-#define __SADD16 __sadd16
-#define __QADD16 __qadd16
-#define __SHADD16 __shadd16
-#define __UADD16 __uadd16
-#define __UQADD16 __uqadd16
-#define __UHADD16 __uhadd16
-#define __SSUB16 __ssub16
-#define __QSUB16 __qsub16
-#define __SHSUB16 __shsub16
-#define __USUB16 __usub16
-#define __UQSUB16 __uqsub16
-#define __UHSUB16 __uhsub16
-#define __SASX __sasx
-#define __QASX __qasx
-#define __SHASX __shasx
-#define __UASX __uasx
-#define __UQASX __uqasx
-#define __UHASX __uhasx
-#define __SSAX __ssax
-#define __QSAX __qsax
-#define __SHSAX __shsax
-#define __USAX __usax
-#define __UQSAX __uqsax
-#define __UHSAX __uhsax
-#define __USAD8 __usad8
-#define __USADA8 __usada8
-#define __SSAT16 __ssat16
-#define __USAT16 __usat16
-#define __UXTB16 __uxtb16
-#define __UXTAB16 __uxtab16
-#define __SXTB16 __sxtb16
-#define __SXTAB16 __sxtab16
-#define __SMUAD __smuad
-#define __SMUADX __smuadx
-#define __SMLAD __smlad
-#define __SMLADX __smladx
-#define __SMLALD __smlald
-#define __SMLALDX __smlaldx
-#define __SMUSD __smusd
-#define __SMUSDX __smusdx
-#define __SMLSD __smlsd
-#define __SMLSDX __smlsdx
-#define __SMLSLD __smlsld
-#define __SMLSLDX __smlsldx
-#define __SEL __sel
-#define __QADD __qadd
-#define __QSUB __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
- ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
-
-#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
- ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
-
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/
-/* intrinsic __SADD8 see intrinsics.h */
-/* intrinsic __QADD8 see intrinsics.h */
-/* intrinsic __SHADD8 see intrinsics.h */
-/* intrinsic __UADD8 see intrinsics.h */
-/* intrinsic __UQADD8 see intrinsics.h */
-/* intrinsic __UHADD8 see intrinsics.h */
-/* intrinsic __SSUB8 see intrinsics.h */
-/* intrinsic __QSUB8 see intrinsics.h */
-/* intrinsic __SHSUB8 see intrinsics.h */
-/* intrinsic __USUB8 see intrinsics.h */
-/* intrinsic __UQSUB8 see intrinsics.h */
-/* intrinsic __UHSUB8 see intrinsics.h */
-/* intrinsic __SADD16 see intrinsics.h */
-/* intrinsic __QADD16 see intrinsics.h */
-/* intrinsic __SHADD16 see intrinsics.h */
-/* intrinsic __UADD16 see intrinsics.h */
-/* intrinsic __UQADD16 see intrinsics.h */
-/* intrinsic __UHADD16 see intrinsics.h */
-/* intrinsic __SSUB16 see intrinsics.h */
-/* intrinsic __QSUB16 see intrinsics.h */
-/* intrinsic __SHSUB16 see intrinsics.h */
-/* intrinsic __USUB16 see intrinsics.h */
-/* intrinsic __UQSUB16 see intrinsics.h */
-/* intrinsic __UHSUB16 see intrinsics.h */
-/* intrinsic __SASX see intrinsics.h */
-/* intrinsic __QASX see intrinsics.h */
-/* intrinsic __SHASX see intrinsics.h */
-/* intrinsic __UASX see intrinsics.h */
-/* intrinsic __UQASX see intrinsics.h */
-/* intrinsic __UHASX see intrinsics.h */
-/* intrinsic __SSAX see intrinsics.h */
-/* intrinsic __QSAX see intrinsics.h */
-/* intrinsic __SHSAX see intrinsics.h */
-/* intrinsic __USAX see intrinsics.h */
-/* intrinsic __UQSAX see intrinsics.h */
-/* intrinsic __UHSAX see intrinsics.h */
-/* intrinsic __USAD8 see intrinsics.h */
-/* intrinsic __USADA8 see intrinsics.h */
-/* intrinsic __SSAT16 see intrinsics.h */
-/* intrinsic __USAT16 see intrinsics.h */
-/* intrinsic __UXTB16 see intrinsics.h */
-/* intrinsic __SXTB16 see intrinsics.h */
-/* intrinsic __UXTAB16 see intrinsics.h */
-/* intrinsic __SXTAB16 see intrinsics.h */
-/* intrinsic __SMUAD see intrinsics.h */
-/* intrinsic __SMUADX see intrinsics.h */
-/* intrinsic __SMLAD see intrinsics.h */
-/* intrinsic __SMLADX see intrinsics.h */
-/* intrinsic __SMLALD see intrinsics.h */
-/* intrinsic __SMLALDX see intrinsics.h */
-/* intrinsic __SMUSD see intrinsics.h */
-/* intrinsic __SMUSDX see intrinsics.h */
-/* intrinsic __SMLSD see intrinsics.h */
-/* intrinsic __SMLSDX see intrinsics.h */
-/* intrinsic __SMLSLD see intrinsics.h */
-/* intrinsic __SMLSLDX see intrinsics.h */
-/* intrinsic __SEL see intrinsics.h */
-/* intrinsic __QADD see intrinsics.h */
-/* intrinsic __QSUB see intrinsics.h */
-/* intrinsic __PKHBT see intrinsics.h */
-/* intrinsic __PKHTB see intrinsics.h */
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SMLALD(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
- (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLALDX(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
- (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SMLSLD(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
- (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLSLDX(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
- (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- if (ARG3 == 0) \
- __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
- else \
- __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-/* not yet supported */
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CORE_CM4_SIMD_H */
-
-#ifdef __cplusplus
-}
-#endif
+++ /dev/null
-/**************************************************************************//**
- * @file core_cmFunc.h
- * @brief CMSIS Cortex-M Core Function Access Header File
- * @version V2.10
- * @date 26. July 2011
- *
- * @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq(); */
-/* intrinsic void __disable_irq(); */
-
-/** \brief Get Control Register
-
- This function returns the content of the Control Register.
-
- \return Control Register value
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-
-/** \brief Set Control Register
-
- This function writes the given value to the Control Register.
-
- \param [in] control Control Register value to set
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-
-/** \brief Get ISPR Register
-
- This function returns the content of the ISPR Register.
-
- \return ISPR Register value
- */
-static __INLINE uint32_t __get_IPSR(void)
-{
- register uint32_t __regIPSR __ASM("ipsr");
- return(__regIPSR);
-}
-
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-static __INLINE uint32_t __get_APSR(void)
-{
- register uint32_t __regAPSR __ASM("apsr");
- return(__regAPSR);
-}
-
-
-/** \brief Get xPSR Register
-
- This function returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-static __INLINE uint32_t __get_xPSR(void)
-{
- register uint32_t __regXPSR __ASM("xpsr");
- return(__regXPSR);
-}
-
-
-/** \brief Get Process Stack Pointer
-
- This function returns the current value of the Process Stack Pointer (PSP).
-
- \return PSP Register value
- */
-static __INLINE uint32_t __get_PSP(void)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- return(__regProcessStackPointer);
-}
-
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the Process Stack Pointer (PSP).
-
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-static __INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief Get Main Stack Pointer
-
- This function returns the current value of the Main Stack Pointer (MSP).
-
- \return MSP Register value
- */
-static __INLINE uint32_t __get_MSP(void)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- return(__regMainStackPointer);
-}
-
-
-/** \brief Set Main Stack Pointer
-
- This function assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-static __INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief Get Priority Mask
-
- This function returns the current state of the priority mask bit from the Priority Mask Register.
-
- \return Priority Mask value
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-
-/** \brief Set Priority Mask
-
- This function assigns the given value to the Priority Mask Register.
-
- \param [in] priMask Priority Mask
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq
-
-
-/** \brief Get Base Priority
-
- This function returns the current value of the Base Priority register.
-
- \return Base Priority register value
- */
-static __INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-
-/** \brief Set Base Priority
-
- This function assigns the given value to the Base Priority register.
-
- \param [in] basePri Base Priority value to set
- */
-static __INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief Get Fault Mask
-
- This function returns the current value of the Fault Mask register.
-
- \return Fault Mask register value
- */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-
-/** \brief Set Fault Mask
-
- This function assigns the given value to the Fault Mask register.
-
- \param [in] faultMask Fault Mask value to set
- */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if (__CORTEX_M == 0x04)
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-static __INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- return(__regfpscr);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-static __INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief Enable IRQ Interrupts
-
- This function enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
-{
- __ASM volatile ("cpsie i");
-}
-
-
-/** \brief Disable IRQ Interrupts
-
- This function disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
-{
- __ASM volatile ("cpsid i");
-}
-
-
-/** \brief Get Control Register
-
- This function returns the content of the Control Register.
-
- \return Control Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Control Register
-
- This function writes the given value to the Control Register.
-
- \param [in] control Control Register value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/** \brief Get ISPR Register
-
- This function returns the content of the ISPR Register.
-
- \return ISPR Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get xPSR Register
-
- This function returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get Process Stack Pointer
-
- This function returns the current value of the Process Stack Pointer (PSP).
-
- \return PSP Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the Process Stack Pointer (PSP).
-
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
-}
-
-
-/** \brief Get Main Stack Pointer
-
- This function returns the current value of the Main Stack Pointer (MSP).
-
- \return MSP Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Main Stack Pointer
-
- This function assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
-}
-
-
-/** \brief Get Priority Mask
-
- This function returns the current state of the priority mask bit from the Priority Mask Register.
-
- \return Priority Mask value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Priority Mask
-
- This function assigns the given value to the Priority Mask Register.
-
- \param [in] priMask Priority Mask
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
-{
- __ASM volatile ("cpsie f");
-}
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
-{
- __ASM volatile ("cpsid f");
-}
-
-
-/** \brief Get Base Priority
-
- This function returns the current value of the Base Priority register.
-
- \return Base Priority register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Base Priority
-
- This function assigns the given value to the Base Priority register.
-
- \param [in] basePri Base Priority value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-
-/** \brief Get Fault Mask
-
- This function returns the current value of the Fault Mask register.
-
- \return Fault Mask register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Fault Mask
-
- This function assigns the given value to the Fault Mask register.
-
- \param [in] faultMask Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if (__CORTEX_M == 0x04)
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- uint32_t result;
-
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
- return(result);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CMFUNC_H */
+++ /dev/null
-/**************************************************************************//**
- * @file core_cmInstr.h
- * @brief CMSIS Cortex-M Core Instruction Access Header File
- * @version V2.10
- * @date 19. July 2011
- *
- * @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief No Operation
-
- No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP __nop
-
-
-/** \brief Wait For Interrupt
-
- Wait For Interrupt is a hint instruction that suspends execution
- until one of a number of events occurs.
- */
-#define __WFI __wfi
-
-
-/** \brief Wait For Event
-
- Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-#define __WFE __wfe
-
-
-/** \brief Send Event
-
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV __sev
-
-
-/** \brief Instruction Synchronization Barrier
-
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
- memory, after the instruction has been completed.
- */
-#define __ISB() __isb(0xF)
-
-
-/** \brief Data Synchronization Barrier
-
- This function acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() __dsb(0xF)
-
-
-/** \brief Data Memory Barrier
-
- This function ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-#define __DMB() __dmb(0xF)
-
-
-/** \brief Reverse byte order (32 bit)
-
- This function reverses the byte order in integer value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REV __rev
-
-
-/** \brief Reverse byte order (16 bit)
-
- This function reverses the byte order in two unsigned short values.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-static __INLINE __ASM uint32_t __REV16(uint32_t value)
-{
- rev16 r0, r0
- bx lr
-}
-
-
-/** \brief Reverse byte order in signed short value
-
- This function reverses the byte order in a signed short value with sign extension to integer.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-static __INLINE __ASM int32_t __REVSH(int32_t value)
-{
- revsh r0, r0
- bx lr
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Reverse bit order of value
-
- This function reverses the bit order of the given value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __RBIT __rbit
-
-
-/** \brief LDR Exclusive (8 bit)
-
- This function performs a exclusive LDR command for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief LDR Exclusive (16 bit)
-
- This function performs a exclusive LDR command for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
-
-
-/** \brief LDR Exclusive (32 bit)
-
- This function performs a exclusive LDR command for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief STR Exclusive (8 bit)
-
- This function performs a exclusive STR command for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXB(value, ptr) __strex(value, ptr)
-
-
-/** \brief STR Exclusive (16 bit)
-
- This function performs a exclusive STR command for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXH(value, ptr) __strex(value, ptr)
-
-
-/** \brief STR Exclusive (32 bit)
-
- This function performs a exclusive STR command for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXW(value, ptr) __strex(value, ptr)
-
-
-/** \brief Remove the exclusive lock
-
- This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX __clrex
-
-
-/** \brief Signed Saturate
-
- This function saturates a signed value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT __ssat
-
-
-/** \brief Unsigned Saturate
-
- This function saturates an unsigned value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT __usat
-
-
-/** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __clz
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief No Operation
-
- No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
-{
- __ASM volatile ("nop");
-}
-
-
-/** \brief Wait For Interrupt
-
- Wait For Interrupt is a hint instruction that suspends execution
- until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
-{
- __ASM volatile ("wfi");
-}
-
-
-/** \brief Wait For Event
-
- Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
-{
- __ASM volatile ("wfe");
-}
-
-
-/** \brief Send Event
-
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
-{
- __ASM volatile ("sev");
-}
-
-
-/** \brief Instruction Synchronization Barrier
-
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
- memory, after the instruction has been completed.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
-{
- __ASM volatile ("isb");
-}
-
-
-/** \brief Data Synchronization Barrier
-
- This function acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
-{
- __ASM volatile ("dsb");
-}
-
-
-/** \brief Data Memory Barrier
-
- This function ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
-{
- __ASM volatile ("dmb");
-}
-
-
-/** \brief Reverse byte order (32 bit)
-
- This function reverses the byte order in integer value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-
-/** \brief Reverse byte order (16 bit)
-
- This function reverses the byte order in two unsigned short values.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-
-/** \brief Reverse byte order in signed short value
-
- This function reverses the byte order in a signed short value with sign extension to integer.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Reverse bit order of value
-
- This function reverses the bit order of the given value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-
-/** \brief LDR Exclusive (8 bit)
-
- This function performs a exclusive LDR command for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
- uint8_t result;
-
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-
-/** \brief LDR Exclusive (16 bit)
-
- This function performs a exclusive LDR command for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
- uint16_t result;
-
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-
-/** \brief LDR Exclusive (32 bit)
-
- This function performs a exclusive LDR command for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (8 bit)
-
- This function performs a exclusive STR command for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (16 bit)
-
- This function performs a exclusive STR command for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (32 bit)
-
- This function performs a exclusive STR command for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-
-/** \brief Remove the exclusive lock
-
- This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
-{
- __ASM volatile ("clrex");
-}
-
-
-/** \brief Signed Saturate
-
- This function saturates a signed value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/** \brief Unsigned Saturate
-
- This function saturates an unsigned value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
-{
- uint8_t result;
-
- __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4_discovery.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief This file contains definitions for STM32F4-Discovery Kit's Leds and
- * push-button hardware resources.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4_DISCOVERY_H
-#define __STM32F4_DISCOVERY_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
- #include "stm32f4xx.h"
-
-/** @addtogroup Utilities
- * @{
- */
-
-/** @addtogroup STM32F4_DISCOVERY
- * @{
- */
-
-/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL
- * @{
- */
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Types
- * @{
- */
-typedef enum
-{
- LED4 = 0,
- LED3 = 1,
- LED5 = 2,
- LED6 = 3
-} Led_TypeDef;
-
-typedef enum
-{
- BUTTON_USER = 0,
-} Button_TypeDef;
-
-typedef enum
-{
- BUTTON_MODE_GPIO = 0,
- BUTTON_MODE_EXTI = 1
-} ButtonMode_TypeDef;
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Constants
- * @{
- */
-
-/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL_LED
- * @{
- */
-#define LEDn 4
-
-#define LED4_PIN GPIO_Pin_12
-#define LED4_GPIO_PORT GPIOD
-#define LED4_GPIO_CLK RCC_AHB1Periph_GPIOD
-
-#define LED3_PIN GPIO_Pin_13
-#define LED3_GPIO_PORT GPIOD
-#define LED3_GPIO_CLK RCC_AHB1Periph_GPIOD
-
-#define LED5_PIN GPIO_Pin_14
-#define LED5_GPIO_PORT GPIOD
-#define LED5_GPIO_CLK RCC_AHB1Periph_GPIOD
-
-#define LED6_PIN GPIO_Pin_15
-#define LED6_GPIO_PORT GPIOD
-#define LED6_GPIO_CLK RCC_AHB1Periph_GPIOD
-/**
- * @}
- */
-
-/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL_BUTTON
- * @{
- */
-#define BUTTONn 1
-
-/**
- * @brief Wakeup push-button
- */
-#define USER_BUTTON_PIN GPIO_Pin_0
-#define USER_BUTTON_GPIO_PORT GPIOA
-#define USER_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOA
-#define USER_BUTTON_EXTI_LINE EXTI_Line0
-#define USER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA
-#define USER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0
-#define USER_BUTTON_EXTI_IRQn EXTI0_IRQn
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Functions
- * @{
- */
-void STM_EVAL_LEDInit(Led_TypeDef Led);
-void STM_EVAL_LEDOn(Led_TypeDef Led);
-void STM_EVAL_LEDOff(Led_TypeDef Led);
-void STM_EVAL_LEDToggle(Led_TypeDef Led);
-void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
-uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4_DISCOVERY_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 30-September-2011
- * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
- * This file contains all the peripheral register's definitions, bits
- * definitions and memory mapping for STM32F4xx devices.
- *
- * The file is the unique include file that the application programmer
- * is using in the C source code, usually in main.c. This file contains:
- * - Configuration section that allows to select:
- * - The device used in the target application
- * - To use or not the peripheral\92s drivers in application code(i.e.
- * code will be based on direct access to peripheral\92s registers
- * rather than drivers API), this option is controlled by
- * "#define USE_STDPERIPH_DRIVER"
- * - To change few application-specific parameters such as the HSE
- * crystal frequency
- * - Data structures and the address mapping for all peripherals
- * - Peripheral's registers declarations and bits definition
- * - Macros to access peripheral\92s registers hardware
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f4xx
- * @{
- */
-
-#ifndef __STM32F4xx_H
-#define __STM32F4xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-#ifdef USE_FULL_ASSERT
-
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr: If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-
-/** @addtogroup Library_configuration_section
- * @{
- */
-
-/* Uncomment the line below according to the target STM32 device used in your
- application
- */
-
-#if !defined (STM32F4XX)
- #define STM32F4XX
-#endif
-
-/* Tip: To avoid modifying this file each time you need to switch between these
- devices, you can define the device in your toolchain compiler preprocessor.
- */
-
-#if !defined (STM32F4XX)
- #error "Please select first the target STM32F4XX device used in your application (in stm32f4xx.h file)"
-#endif
-
-#if !defined (USE_STDPERIPH_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
- */
- /*#define USE_STDPERIPH_DRIVER*/
-#endif /* USE_STDPERIPH_DRIVER */
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
- used in your application
-
- Tip: To avoid modifying this file each time you need to use different HSE, you
- can define the HSE value in your toolchain compiler preprocessor.
- */
-
-#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
- Timeout value
- */
-#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
- * @brief STM32F4XX Standard Peripherals Library version number V1.0.0
- */
-#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
-#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
- |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
- |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
- |(__STM32F4XX_STDPERIPH_VERSION_RC))
-
-/**
- * @}
- */
-
-/** @addtogroup Configuration_section_for_CMSIS
- * @{
- */
-
-/**
- * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
- */
-#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device
- * in @ref Library_configuration_section
- */
-typedef enum IRQn
-{
-/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
-/****** STM32 specific Interrupt Numbers **********************************************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
- TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
- RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */
- RCC_IRQn = 5, /*!< RCC global Interrupt */
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
- DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
- DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
- DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
- DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
- DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
- DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
- DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
- ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FSMC_IRQn = 48, /*!< FSMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
- HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
- FPU_IRQn = 81 /*!< FPU global interrupt */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Exported_types
- * @{
- */
-/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
-typedef int32_t s32;
-typedef int16_t s16;
-typedef int8_t s8;
-
-typedef const int32_t sc32; /*!< Read Only */
-typedef const int16_t sc16; /*!< Read Only */
-typedef const int8_t sc8; /*!< Read Only */
-
-typedef __IO int32_t vs32;
-typedef __IO int16_t vs16;
-typedef __IO int8_t vs8;
-
-typedef __I int32_t vsc32; /*!< Read Only */
-typedef __I int16_t vsc16; /*!< Read Only */
-typedef __I int8_t vsc8; /*!< Read Only */
-
-typedef uint32_t u32;
-typedef uint16_t u16;
-typedef uint8_t u8;
-
-typedef const uint32_t uc32; /*!< Read Only */
-typedef const uint16_t uc16; /*!< Read Only */
-typedef const uint8_t uc8; /*!< Read Only */
-
-typedef __IO uint32_t vu32;
-typedef __IO uint16_t vu16;
-typedef __IO uint8_t vu8;
-
-typedef __I uint32_t vuc32; /*!< Read Only */
-typedef __I uint16_t vuc16; /*!< Read Only */
-typedef __I uint8_t vuc8; /*!< Read Only */
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog to Digital Converter
- */
-
-typedef struct
-{
- __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
- __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
- __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
- __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
- __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
- __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
- __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
- __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
- __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
- __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
- __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
- __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
- __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
- __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
- __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
- __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
- __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
- __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
- __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
- __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
- __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
- __IO uint32_t CDR; /*!< ADC common regular data register for dual
- AND triple modes, Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/**
- * @brief Controller Area Network TxMailBox
- */
-
-typedef struct
-{
- __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
- __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
- __IO uint32_t TDLR; /*!< CAN mailbox data low register */
- __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FIFOMailBox
- */
-
-typedef struct
-{
- __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
- __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
- __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
- __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FilterRegister
- */
-
-typedef struct
-{
- __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
- __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/**
- * @brief Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
- __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
- __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
- __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
- __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
- __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
- __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
- __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
- uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
- CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
- CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
- uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
- __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
- __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
- uint32_t RESERVED2; /*!< Reserved, 0x208 */
- __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
- uint32_t RESERVED3; /*!< Reserved, 0x210 */
- __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
- uint32_t RESERVED4; /*!< Reserved, 0x218 */
- __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
- uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
- CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
-} CAN_TypeDef;
-
-/**
- * @brief CRC calculation unit
- */
-
-typedef struct
-{
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
- uint8_t RESERVED0; /*!< Reserved, 0x05 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
-} CRC_TypeDef;
-
-/**
- * @brief Digital to Analog Converter
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
- __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
- __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
- __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
- __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
- __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
- __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
- __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
- __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
- __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
- __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
- __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
- __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
- __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
-} DAC_TypeDef;
-
-/**
- * @brief Debug MCU
- */
-
-typedef struct
-{
- __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
- __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
- __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
- __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/**
- * @brief DCMI
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
- __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
- __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
- __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
- __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
- __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
- __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
- __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
- __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
- __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
- __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/**
- * @brief DMA Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DMA stream x configuration register */
- __IO uint32_t NDTR; /*!< DMA stream x number of data register */
- __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
- __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
- __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
- __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
- __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
- __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
- __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
- __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-/**
- * @brief Ethernet MAC
- */
-
-typedef struct
-{
- __IO uint32_t MACCR;
- __IO uint32_t MACFFR;
- __IO uint32_t MACHTHR;
- __IO uint32_t MACHTLR;
- __IO uint32_t MACMIIAR;
- __IO uint32_t MACMIIDR;
- __IO uint32_t MACFCR;
- __IO uint32_t MACVLANTR; /* 8 */
- uint32_t RESERVED0[2];
- __IO uint32_t MACRWUFFR; /* 11 */
- __IO uint32_t MACPMTCSR;
- uint32_t RESERVED1[2];
- __IO uint32_t MACSR; /* 15 */
- __IO uint32_t MACIMR;
- __IO uint32_t MACA0HR;
- __IO uint32_t MACA0LR;
- __IO uint32_t MACA1HR;
- __IO uint32_t MACA1LR;
- __IO uint32_t MACA2HR;
- __IO uint32_t MACA2LR;
- __IO uint32_t MACA3HR;
- __IO uint32_t MACA3LR; /* 24 */
- uint32_t RESERVED2[40];
- __IO uint32_t MMCCR; /* 65 */
- __IO uint32_t MMCRIR;
- __IO uint32_t MMCTIR;
- __IO uint32_t MMCRIMR;
- __IO uint32_t MMCTIMR; /* 69 */
- uint32_t RESERVED3[14];
- __IO uint32_t MMCTGFSCCR; /* 84 */
- __IO uint32_t MMCTGFMSCCR;
- uint32_t RESERVED4[5];
- __IO uint32_t MMCTGFCR;
- uint32_t RESERVED5[10];
- __IO uint32_t MMCRFCECR;
- __IO uint32_t MMCRFAECR;
- uint32_t RESERVED6[10];
- __IO uint32_t MMCRGUFCR;
- uint32_t RESERVED7[334];
- __IO uint32_t PTPTSCR;
- __IO uint32_t PTPSSIR;
- __IO uint32_t PTPTSHR;
- __IO uint32_t PTPTSLR;
- __IO uint32_t PTPTSHUR;
- __IO uint32_t PTPTSLUR;
- __IO uint32_t PTPTSAR;
- __IO uint32_t PTPTTHR;
- __IO uint32_t PTPTTLR;
- __IO uint32_t RESERVED8;
- __IO uint32_t PTPTSSR;
- uint32_t RESERVED9[565];
- __IO uint32_t DMABMR;
- __IO uint32_t DMATPDR;
- __IO uint32_t DMARPDR;
- __IO uint32_t DMARDLAR;
- __IO uint32_t DMATDLAR;
- __IO uint32_t DMASR;
- __IO uint32_t DMAOMR;
- __IO uint32_t DMAIER;
- __IO uint32_t DMAMFBOCR;
- __IO uint32_t DMARSWTR;
- uint32_t RESERVED10[8];
- __IO uint32_t DMACHTDR;
- __IO uint32_t DMACHRDR;
- __IO uint32_t DMACHTBAR;
- __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/**
- * @brief External Interrupt/Event Controller
- */
-
-typedef struct
-{
- __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
- __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
- __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
- __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
- __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
- __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/**
- * @brief FLASH Registers
- */
-
-typedef struct
-{
- __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
- __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
- __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
- __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
- __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */
-} FLASH_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller
- */
-
-typedef struct
-{
- __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FSMC_Bank1_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank1E
- */
-
-typedef struct
-{
- __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank2
- */
-
-typedef struct
-{
- __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
- __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
- __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
- __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
- uint32_t RESERVED0; /*!< Reserved, 0x70 */
- __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
-} FSMC_Bank2_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank3
- */
-
-typedef struct
-{
- __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
- __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
- __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
- __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
- uint32_t RESERVED0; /*!< Reserved, 0x90 */
- __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
-} FSMC_Bank3_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank4
- */
-
-typedef struct
-{
- __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
- __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
- __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
- __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
- __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
-} FSMC_Bank4_TypeDef;
-
-/**
- * @brief General Purpose I/O
- */
-
-typedef struct
-{
- __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
- __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
- __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
- __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
- __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
- __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
- __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
- __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/**
- * @brief System configuration controller
- */
-
-typedef struct
-{
- __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
- __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
- uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
- __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
-} SYSCFG_TypeDef;
-
-/**
- * @brief Inter-integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
-} I2C_TypeDef;
-
-/**
- * @brief Independent WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
- __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
- __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/**
- * @brief Power Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
- __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/**
- * @brief Reset and Clock Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
- __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
- __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
- __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
- __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
- __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
- __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
- uint32_t RESERVED0; /*!< Reserved, 0x1C */
- __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
- __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
- __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
- __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
- __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
- uint32_t RESERVED2; /*!< Reserved, 0x3C */
- __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
- __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
- uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
- __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
- __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
- __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
- uint32_t RESERVED4; /*!< Reserved, 0x5C */
- __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
- __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
- uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
- __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
- __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
- uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
- __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
- __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
-} RCC_TypeDef;
-
-/**
- * @brief Real-Time Clock
- */
-
-typedef struct
-{
- __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
- __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
- __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
- __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
- __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
- __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
- __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
- __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
- __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
- __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
- __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
- __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
- __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
- __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
- __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
- __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
- __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
- __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
- uint32_t RESERVED7; /*!< Reserved, 0x4C */
- __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
- __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
- __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
- __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
- __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
- __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
- __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
- __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
- __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
- __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
- __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
- __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
- __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
- __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
- __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
- __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
- __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
- __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
- __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
- __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
-} RTC_TypeDef;
-
-/**
- * @brief SD host Interface
- */
-
-typedef struct
-{
- __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
- __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
- __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
- __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
- __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
- __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
- __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
- __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
- __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
- __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
- __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
- __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
- __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
- __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
- __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
- __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
- uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
- __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
- uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
- __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/**
- * @brief Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
-} SPI_TypeDef;
-
-/**
- * @brief TIM
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
- __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
- uint16_t RESERVED9; /*!< Reserved, 0x2A */
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
- __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
- uint16_t RESERVED10; /*!< Reserved, 0x32 */
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
- __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
- uint16_t RESERVED11; /*!< Reserved, 0x46 */
- __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
- uint16_t RESERVED12; /*!< Reserved, 0x4A */
- __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
- uint16_t RESERVED13; /*!< Reserved, 0x4E */
- __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
- uint16_t RESERVED14; /*!< Reserved, 0x52 */
-} TIM_TypeDef;
-
-/**
- * @brief Universal Synchronous Asynchronous Receiver Transmitter
- */
-
-typedef struct
-{
- __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
-} USART_TypeDef;
-
-/**
- * @brief Window WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
- __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
- * @brief Crypto Processor
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
- __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
- __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
- __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
- __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
- __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
- __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
- __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
- __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
- __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
- __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
- __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
- __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
- __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
- __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
- __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
- __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
- __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
- __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
- __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
-} CRYP_TypeDef;
-
-/**
- * @brief HASH
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
- __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
- __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
- __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
- __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
- __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
- uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
- __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */
-} HASH_TypeDef;
-
-/**
- * @brief HASH
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
- __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
- __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
-} RNG_TypeDef;
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_memory_map
- * @{
- */
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
-#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
-#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
-#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
-#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
-#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
-
-/* Legacy defines */
-#define SRAM_BASE SRAM1_BASE
-#define SRAM_BB_BASE SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
-#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
-#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
-#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
-#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
-#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
-#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
-#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
-#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
-#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
-#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
-#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
-#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
-#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
-#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
-#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
-#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
-#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
-#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
-#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
-#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
-#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
-#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
-#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
-#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
-#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
-#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
-#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
-#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
-#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
-#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
-#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
-#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
-#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
-#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
-#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
-#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
-#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
-#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
-#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
-#define ETH_MAC_BASE (ETH_BASE)
-#define ETH_MMC_BASE (ETH_BASE + 0x0100)
-#define ETH_PTP_BASE (ETH_BASE + 0x0700)
-#define ETH_DMA_BASE (ETH_BASE + 0x1000)
-
-/*!< AHB2 peripherals */
-#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
-#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
-#define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
-#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
-
-/*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
-#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
-#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
-#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
-#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE ((uint32_t )0xE0042000)
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_declaration
- * @{
- */
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define UART4 ((USART_TypeDef *) UART4_BASE)
-#define UART5 ((USART_TypeDef *) UART5_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
-#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define USART6 ((USART_TypeDef *) USART6_BASE)
-#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH ((ETH_TypeDef *) ETH_BASE)
-#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
-#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
-#define HASH ((HASH_TypeDef *) HASH_BASE)
-#define RNG ((RNG_TypeDef *) RNG_BASE)
-#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
-#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
-#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_constants
- * @{
- */
-
- /** @addtogroup Peripheral_Registers_Bits_Definition
- * @{
- */
-
-/******************************************************************************/
-/* Peripheral Registers_Bits_Definition */
-/******************************************************************************/
-
-/******************************************************************************/
-/* */
-/* Analog to Digital Converter */
-/* */
-/******************************************************************************/
-/******************** Bit definition for ADC_SR register ********************/
-#define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */
-#define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */
-#define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */
-#define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */
-#define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */
-#define ADC_SR_OVR ((uint8_t)0x20) /*!<Overrun flag */
-
-/******************* Bit definition for ADC_CR1 register ********************/
-#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
-#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
-#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
-#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
-#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
-#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
-#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
-#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
-#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
-#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
-#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
-#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
-#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
-#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
-#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
-
-/******************* Bit definition for ADC_CR2 register ********************/
-#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
-#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
-#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
-#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
-#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
-#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
-#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
-#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
-#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
-
-/****************** Bit definition for ADC_SMPR1 register *******************/
-#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
-#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
-#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
-#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
-#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
-#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
-#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
-#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
-#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
-#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
-#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
-#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
-#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
-#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
-#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
-#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
-#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-
-/****************** Bit definition for ADC_SMPR2 register *******************/
-#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
-#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
-#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
-#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
-#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
-#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
-#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
-#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
-#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
-#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
-#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
-#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
-#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
-#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
-#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
-#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
-#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
-#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
-#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
-
-/****************** Bit definition for ADC_JOFR1 register *******************/
-#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */
-
-/****************** Bit definition for ADC_JOFR2 register *******************/
-#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */
-
-/****************** Bit definition for ADC_JOFR3 register *******************/
-#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */
-
-/****************** Bit definition for ADC_JOFR4 register *******************/
-#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */
-
-/******************* Bit definition for ADC_HTR register ********************/
-#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */
-
-/******************* Bit definition for ADC_LTR register ********************/
-#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */
-
-/******************* Bit definition for ADC_SQR1 register *******************/
-#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
-#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
-#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
-#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
-#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
-#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
-#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
-#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
-#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
-#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
-#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
-
-/******************* Bit definition for ADC_SQR2 register *******************/
-#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
-#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
-#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
-#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
-#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
-#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
-#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
-#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
-#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
-#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
-#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
-#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
-#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
-#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
-#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
-#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
-
-/******************* Bit definition for ADC_SQR3 register *******************/
-#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
-#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
-#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
-#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
-#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
-#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
-#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
-#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
-#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
-#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
-#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
-#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
-#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
-#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
-#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
-#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
-
-/******************* Bit definition for ADC_JSQR register *******************/
-#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
-#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
-#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
-#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
-#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
-#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
-#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
-#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
-#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
-#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
-#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
-#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-
-/******************* Bit definition for ADC_JDR1 register *******************/
-#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
-
-/******************* Bit definition for ADC_JDR2 register *******************/
-#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
-
-/******************* Bit definition for ADC_JDR3 register *******************/
-#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
-
-/******************* Bit definition for ADC_JDR4 register *******************/
-#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
-
-/******************** Bit definition for ADC_DR register ********************/
-#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
-#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
-
-/******************* Bit definition for ADC_CSR register ********************/
-#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
-#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
-#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
-#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
-#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
-#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
-#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
-#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
-#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
-#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
-#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
-#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
-#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
-#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
-#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
-#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
-#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
-#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
-
-/******************* Bit definition for ADC_CCR register ********************/
-#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
-#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
-#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
-#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
-#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
-#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
-#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
-#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
-#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
-
-/******************* Bit definition for ADC_CDR register ********************/
-#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
-#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/* */
-/* Controller Area Network */
-/* */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/******************* Bit definition for CAN_MCR register ********************/
-#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
-#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
-#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
-#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
-#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
-#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
-#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
-#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
-#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
-
-/******************* Bit definition for CAN_MSR register ********************/
-#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
-#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
-#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
-#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
-#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
-#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
-#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
-#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
-#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
-
-/******************* Bit definition for CAN_TSR register ********************/
-#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
-#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
-#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
-#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
-#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
-#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
-#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
-#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
-#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
-#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
-#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
-#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
-#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
-#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
-#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
-#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
-
-#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
-#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
-#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
-#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
-
-#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
-#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
-#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
-#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
-
-/******************* Bit definition for CAN_RF0R register *******************/
-#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
-#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
-#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
-#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
-
-/******************* Bit definition for CAN_RF1R register *******************/
-#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
-#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
-#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
-#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
-
-/******************** Bit definition for CAN_IER register *******************/
-#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
-#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
-#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
-#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
-#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
-#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
-#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
-#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
-#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
-#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
-
-/******************** Bit definition for CAN_ESR register *******************/
-#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
-#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
-#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
-
-#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
-#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-
-#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
-
-/******************* Bit definition for CAN_BTR register ********************/
-#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
-#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
-#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
-#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
-#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
-#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
-
-/*!<Mailbox registers */
-/****************** Bit definition for CAN_TI0R register ********************/
-#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
-#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
-#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
-
-/****************** Bit definition for CAN_TDT0R register *******************/
-#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
-#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
-
-/****************** Bit definition for CAN_TDL0R register *******************/
-#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
-
-/****************** Bit definition for CAN_TDH0R register *******************/
-#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
-
-/******************* Bit definition for CAN_TI1R register *******************/
-#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
-#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
-#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_TDT1R register ******************/
-#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
-#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
-
-/******************* Bit definition for CAN_TDL1R register ******************/
-#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
-
-/******************* Bit definition for CAN_TDH1R register ******************/
-#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
-
-/******************* Bit definition for CAN_TI2R register *******************/
-#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
-#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
-#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_TDT2R register ******************/
-#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
-#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
-
-/******************* Bit definition for CAN_TDL2R register ******************/
-#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
-
-/******************* Bit definition for CAN_TDH2R register ******************/
-#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
-
-/******************* Bit definition for CAN_RI0R register *******************/
-#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
-#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_RDT0R register ******************/
-#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
-#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
-
-/******************* Bit definition for CAN_RDL0R register ******************/
-#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
-
-/******************* Bit definition for CAN_RDH0R register ******************/
-#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
-
-/******************* Bit definition for CAN_RI1R register *******************/
-#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
-#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_RDT1R register ******************/
-#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
-#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
-
-/******************* Bit definition for CAN_RDL1R register ******************/
-#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
-
-/******************* Bit definition for CAN_RDH1R register ******************/
-#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/******************* Bit definition for CAN_FMR register ********************/
-#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
-
-/******************* Bit definition for CAN_FM1R register *******************/
-#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
-#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
-#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
-#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
-#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
-#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
-#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
-#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
-#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
-#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
-#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
-#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
-#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
-#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
-#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
-
-/******************* Bit definition for CAN_FS1R register *******************/
-#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
-#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
-#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
-#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
-#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
-#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
-#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
-#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
-#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
-#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
-#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
-#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
-#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
-#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
-#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
-
-/****************** Bit definition for CAN_FFA1R register *******************/
-#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
-#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
-#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
-#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
-#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
-#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
-#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
-#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
-#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
-#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
-#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
-#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
-#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
-#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
-
-/******************* Bit definition for CAN_FA1R register *******************/
-#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
-#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
-#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
-#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
-#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
-#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
-#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
-#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
-#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
-#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
-#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
-#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
-#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
-#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
-#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
-
-/******************* Bit definition for CAN_F0R1 register *******************/
-#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F1R1 register *******************/
-#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F2R1 register *******************/
-#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F3R1 register *******************/
-#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F4R1 register *******************/
-#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F5R1 register *******************/
-#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F6R1 register *******************/
-#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F7R1 register *******************/
-#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F8R1 register *******************/
-#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F9R1 register *******************/
-#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F10R1 register ******************/
-#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F11R1 register ******************/
-#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F12R1 register ******************/
-#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F13R1 register ******************/
-#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F0R2 register *******************/
-#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F1R2 register *******************/
-#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F2R2 register *******************/
-#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F3R2 register *******************/
-#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F4R2 register *******************/
-#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F5R2 register *******************/
-#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F6R2 register *******************/
-#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F7R2 register *******************/
-#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F8R2 register *******************/
-#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F9R2 register *******************/
-#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F10R2 register ******************/
-#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F11R2 register ******************/
-#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F12R2 register ******************/
-#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F13R2 register ******************/
-#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************************************************************************/
-/* */
-/* CRC calculation unit */
-/* */
-/******************************************************************************/
-/******************* Bit definition for CRC_DR register *********************/
-#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
-
-
-/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
-
-
-/******************** Bit definition for CRC_CR register ********************/
-#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
-
-/******************************************************************************/
-/* */
-/* Crypto Processor */
-/* */
-/******************************************************************************/
-/******************* Bits definition for CRYP_CR register ********************/
-#define CRYP_CR_ALGODIR ((uint32_t)0x00000004)
-
-#define CRYP_CR_ALGOMODE ((uint32_t)0x00000038)
-#define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)
-#define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)
-#define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)
-#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
-#define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)
-#define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)
-#define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)
-#define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)
-#define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)
-#define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)
-#define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)
-
-#define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)
-#define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)
-#define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)
-#define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)
-#define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)
-#define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)
-#define CRYP_CR_FFLUSH ((uint32_t)0x00004000)
-#define CRYP_CR_CRYPEN ((uint32_t)0x00008000)
-/****************** Bits definition for CRYP_SR register *********************/
-#define CRYP_SR_IFEM ((uint32_t)0x00000001)
-#define CRYP_SR_IFNF ((uint32_t)0x00000002)
-#define CRYP_SR_OFNE ((uint32_t)0x00000004)
-#define CRYP_SR_OFFU ((uint32_t)0x00000008)
-#define CRYP_SR_BUSY ((uint32_t)0x00000010)
-/****************** Bits definition for CRYP_DMACR register ******************/
-#define CRYP_DMACR_DIEN ((uint32_t)0x00000001)
-#define CRYP_DMACR_DOEN ((uint32_t)0x00000002)
-/***************** Bits definition for CRYP_IMSCR register ******************/
-#define CRYP_IMSCR_INIM ((uint32_t)0x00000001)
-#define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)
-/****************** Bits definition for CRYP_RISR register *******************/
-#define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)
-#define CRYP_RISR_INRIS ((uint32_t)0x00000002)
-/****************** Bits definition for CRYP_MISR register *******************/
-#define CRYP_MISR_INMIS ((uint32_t)0x00000001)
-#define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)
-
-/******************************************************************************/
-/* */
-/* Digital to Analog Converter */
-/* */
-/******************************************************************************/
-/******************** Bit definition for DAC_CR register ********************/
-#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
-#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
-#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
-
-#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
-#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
-
-#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-
-#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
-#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
-#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
-#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
-
-#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
-#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
-
-#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-
-#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
-
-/***************** Bit definition for DAC_SWTRIGR register ******************/
-#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
-
-/***************** Bit definition for DAC_DHR12R1 register ******************/
-#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
-
-/***************** Bit definition for DAC_DHR12L1 register ******************/
-#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
-
-/****************** Bit definition for DAC_DHR8R1 register ******************/
-#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
-
-/***************** Bit definition for DAC_DHR12R2 register ******************/
-#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
-
-/***************** Bit definition for DAC_DHR12L2 register ******************/
-#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
-
-/****************** Bit definition for DAC_DHR8R2 register ******************/
-#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
-
-/***************** Bit definition for DAC_DHR12RD register ******************/
-#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
-
-/***************** Bit definition for DAC_DHR12LD register ******************/
-#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
-
-/****************** Bit definition for DAC_DHR8RD register ******************/
-#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
-
-/******************* Bit definition for DAC_DOR1 register *******************/
-#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
-
-/******************* Bit definition for DAC_DOR2 register *******************/
-#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
-
-/******************** Bit definition for DAC_SR register ********************/
-#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/* */
-/* Debug MCU */
-/* */
-/******************************************************************************/
-
-/******************************************************************************/
-/* */
-/* DCMI */
-/* */
-/******************************************************************************/
-/******************** Bits definition for DCMI_CR register ******************/
-#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
-#define DCMI_CR_CM ((uint32_t)0x00000002)
-#define DCMI_CR_CROP ((uint32_t)0x00000004)
-#define DCMI_CR_JPEG ((uint32_t)0x00000008)
-#define DCMI_CR_ESS ((uint32_t)0x00000010)
-#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
-#define DCMI_CR_HSPOL ((uint32_t)0x00000040)
-#define DCMI_CR_VSPOL ((uint32_t)0x00000080)
-#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
-#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
-#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
-#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
-#define DCMI_CR_CRE ((uint32_t)0x00001000)
-#define DCMI_CR_ENABLE ((uint32_t)0x00004000)
-
-/******************** Bits definition for DCMI_SR register ******************/
-#define DCMI_SR_HSYNC ((uint32_t)0x00000001)
-#define DCMI_SR_VSYNC ((uint32_t)0x00000002)
-#define DCMI_SR_FNE ((uint32_t)0x00000004)
-
-/******************** Bits definition for DCMI_RISR register ****************/
-#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
-#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
-#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
-#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
-#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
-
-/******************** Bits definition for DCMI_IER register *****************/
-#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
-#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
-#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
-#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
-#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
-
-/******************** Bits definition for DCMI_MISR register ****************/
-#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
-#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
-#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
-#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
-#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
-
-/******************** Bits definition for DCMI_ICR register *****************/
-#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
-#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
-#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
-#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
-#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
-
-/******************************************************************************/
-/* */
-/* DMA Controller */
-/* */
-/******************************************************************************/
-/******************** Bits definition for DMA_SxCR register *****************/
-#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
-#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
-#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
-#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
-#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
-#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
-#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
-#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
-#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
-#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
-#define DMA_SxCR_ACK ((uint32_t)0x00100000)
-#define DMA_SxCR_CT ((uint32_t)0x00080000)
-#define DMA_SxCR_DBM ((uint32_t)0x00040000)
-#define DMA_SxCR_PL ((uint32_t)0x00030000)
-#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
-#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
-#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
-#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
-#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
-#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
-#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
-#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
-#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
-#define DMA_SxCR_MINC ((uint32_t)0x00000400)
-#define DMA_SxCR_PINC ((uint32_t)0x00000200)
-#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
-#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
-#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
-#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
-#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
-#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
-#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
-#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
-#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
-#define DMA_SxCR_EN ((uint32_t)0x00000001)
-
-/******************** Bits definition for DMA_SxCNDTR register **************/
-#define DMA_SxNDT ((uint32_t)0x0000FFFF)
-#define DMA_SxNDT_0 ((uint32_t)0x00000001)
-#define DMA_SxNDT_1 ((uint32_t)0x00000002)
-#define DMA_SxNDT_2 ((uint32_t)0x00000004)
-#define DMA_SxNDT_3 ((uint32_t)0x00000008)
-#define DMA_SxNDT_4 ((uint32_t)0x00000010)
-#define DMA_SxNDT_5 ((uint32_t)0x00000020)
-#define DMA_SxNDT_6 ((uint32_t)0x00000040)
-#define DMA_SxNDT_7 ((uint32_t)0x00000080)
-#define DMA_SxNDT_8 ((uint32_t)0x00000100)
-#define DMA_SxNDT_9 ((uint32_t)0x00000200)
-#define DMA_SxNDT_10 ((uint32_t)0x00000400)
-#define DMA_SxNDT_11 ((uint32_t)0x00000800)
-#define DMA_SxNDT_12 ((uint32_t)0x00001000)
-#define DMA_SxNDT_13 ((uint32_t)0x00002000)
-#define DMA_SxNDT_14 ((uint32_t)0x00004000)
-#define DMA_SxNDT_15 ((uint32_t)0x00008000)
-
-/******************** Bits definition for DMA_SxFCR register ****************/
-#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
-#define DMA_SxFCR_FS ((uint32_t)0x00000038)
-#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
-#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
-#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
-#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
-#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
-#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
-#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
-
-/******************** Bits definition for DMA_LISR register *****************/
-#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
-#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
-#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
-#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
-#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
-#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
-#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
-#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
-#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
-#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
-#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
-#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
-#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
-#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
-#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
-#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
-#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
-#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
-#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
-#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
-
-/******************** Bits definition for DMA_HISR register *****************/
-#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
-#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
-#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
-#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
-#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
-#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
-#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
-#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
-#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
-#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
-#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
-#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
-#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
-#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
-#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
-#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
-#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
-#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
-#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
-#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
-
-/******************** Bits definition for DMA_LIFCR register ****************/
-#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
-#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
-#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
-#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
-#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
-#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
-#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
-#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
-#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
-#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
-#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
-#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
-#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
-#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
-#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
-#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
-#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
-#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
-#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
-#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
-
-/******************** Bits definition for DMA_HIFCR register ****************/
-#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
-#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
-#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
-#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
-#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
-#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
-#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
-#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
-#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
-#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
-#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
-#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
-#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
-#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
-#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
-#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
-#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
-#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
-#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
-#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
-
-/******************************************************************************/
-/* */
-/* External Interrupt/Event Controller */
-/* */
-/******************************************************************************/
-/******************* Bit definition for EXTI_IMR register *******************/
-#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
-
-/******************* Bit definition for EXTI_EMR register *******************/
-#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
-
-/****************** Bit definition for EXTI_RTSR register *******************/
-#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
-
-/****************** Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
-
-/****************** Bit definition for EXTI_SWIER register ******************/
-#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
-
-/******************* Bit definition for EXTI_PR register ********************/
-#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
-
-/******************************************************************************/
-/* */
-/* FLASH */
-/* */
-/******************************************************************************/
-/******************* Bits definition for FLASH_ACR register *****************/
-#define FLASH_ACR_LATENCY ((uint32_t)0x00000007)
-#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
-#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
-#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
-#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
-#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
-#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
-#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
-#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
-
-#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
-#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
-#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
-#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
-#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
-#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
-#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
-
-/******************* Bits definition for FLASH_SR register ******************/
-#define FLASH_SR_EOP ((uint32_t)0x00000001)
-#define FLASH_SR_SOP ((uint32_t)0x00000002)
-#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
-#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
-#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
-#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
-#define FLASH_SR_BSY ((uint32_t)0x00010000)
-
-/******************* Bits definition for FLASH_CR register ******************/
-#define FLASH_CR_PG ((uint32_t)0x00000001)
-#define FLASH_CR_SER ((uint32_t)0x00000002)
-#define FLASH_CR_MER ((uint32_t)0x00000004)
-#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
-#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
-#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
-#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
-#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
-#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
-#define FLASH_CR_STRT ((uint32_t)0x00010000)
-#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
-#define FLASH_CR_LOCK ((uint32_t)0x80000000)
-
-/******************* Bits definition for FLASH_OPTCR register ***************/
-#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
-#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
-#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
-#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
-#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
-#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
-#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
-#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
-#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
-#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
-#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
-#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
-#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
-#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
-#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
-#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
-#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
-#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
-#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
-#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
-#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
-#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
-#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
-#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
-#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
-#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
-#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
-#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
-
-/******************************************************************************/
-/* */
-/* Flexible Static Memory Controller */
-/* */
-/******************************************************************************/
-/****************** Bit definition for FSMC_BCR1 register *******************/
-#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
-#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
-
-#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
-#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
-
-#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-
-#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
-#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
-#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
-#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
-#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
-#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
-#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
-#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
-#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
-#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
-
-/****************** Bit definition for FSMC_BCR2 register *******************/
-#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
-#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
-
-#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
-#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
-
-#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-
-#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
-#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
-#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
-#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
-#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
-#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
-#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
-#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
-#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
-#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
-
-/****************** Bit definition for FSMC_BCR3 register *******************/
-#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
-#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
-
-#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
-#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
-
-#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-
-#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
-#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
-#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit. */
-#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
-#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
-#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
-#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
-#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
-#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
-#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
-
-/****************** Bit definition for FSMC_BCR4 register *******************/
-#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
-#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
-
-#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
-#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
-
-#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-
-#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
-#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
-#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
-#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
-#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
-#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
-#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
-#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
-#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
-#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
-
-/****************** Bit definition for FSMC_BTR1 register ******************/
-#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-
-#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-
-#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-
-#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-
-#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
-
-#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-
-#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
-
-/****************** Bit definition for FSMC_BTR2 register *******************/
-#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-
-#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-
-#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-
-#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-
-#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
-
-#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-
-#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
-
-/******************* Bit definition for FSMC_BTR3 register *******************/
-#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-
-#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-
-#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-
-#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-
-#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
-
-#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-
-#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
-
-/****************** Bit definition for FSMC_BTR4 register *******************/
-#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-
-#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-
-#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-
-#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-
-#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
-
-#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-
-#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
-
-/****************** Bit definition for FSMC_BWTR1 register ******************/
-#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-
-#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-
-#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-
-#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
-
-#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-
-#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
-
-/****************** Bit definition for FSMC_BWTR2 register ******************/
-#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-
-#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-
-#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-
-#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
-#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
-
-#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-
-#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
-
-/****************** Bit definition for FSMC_BWTR3 register ******************/
-#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-
-#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-
-#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-
-#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
-
-#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-
-#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
-
-/****************** Bit definition for FSMC_BWTR4 register ******************/
-#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-
-#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-
-#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-
-#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
-
-#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-
-#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
-
-/****************** Bit definition for FSMC_PCR2 register *******************/
-#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
-#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
-#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
-
-#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-
-#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
-
-#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
-#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
-#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
-#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
-
-#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
-#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
-#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
-#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
-#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
-
-#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
-#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
-#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
-#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
-
-/****************** Bit definition for FSMC_PCR3 register *******************/
-#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
-#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
-#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
-
-#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-
-#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
-
-#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
-#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
-#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
-#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
-
-#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
-#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
-#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
-#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
-#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
-
-#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
-#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
-#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
-#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
-
-/****************** Bit definition for FSMC_PCR4 register *******************/
-#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
-#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
-#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
-
-#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-
-#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
-
-#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
-#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
-#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
-#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
-
-#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
-#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
-#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
-#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
-#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
-
-#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
-#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
-#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
-#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
-
-/******************* Bit definition for FSMC_SR2 register *******************/
-#define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
-#define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
-#define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
-#define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
-#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
-#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
-#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
-
-/******************* Bit definition for FSMC_SR3 register *******************/
-#define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
-#define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
-#define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
-#define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
-#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
-#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
-#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
-
-/******************* Bit definition for FSMC_SR4 register *******************/
-#define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
-#define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
-#define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
-#define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
-#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
-#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
-#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
-
-/****************** Bit definition for FSMC_PMEM2 register ******************/
-#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
-#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
-
-#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
-#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
-#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
-#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
-
-#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
-#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
-#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
-#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
-
-#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
-#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
-#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
-#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
-
-/****************** Bit definition for FSMC_PMEM3 register ******************/
-#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
-#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
-
-#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
-#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
-#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
-#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
-
-#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
-#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
-#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
-#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
-
-#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
-#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
-#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
-#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
-
-/****************** Bit definition for FSMC_PMEM4 register ******************/
-#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
-#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
-
-#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
-#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
-#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
-#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
-
-#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
-#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
-#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
-#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
-
-#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
-#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
-#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
-#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
-
-/****************** Bit definition for FSMC_PATT2 register ******************/
-#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
-#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
-
-#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
-#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
-#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
-#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
-
-#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
-#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
-#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
-#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
-
-#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
-#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
-#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
-#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
-
-/****************** Bit definition for FSMC_PATT3 register ******************/
-#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
-#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
-
-#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
-#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
-#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
-#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
-
-#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
-#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
-#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
-#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
-
-#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
-#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
-#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
-#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
-
-/****************** Bit definition for FSMC_PATT4 register ******************/
-#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
-#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
-
-#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
-#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
-#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
-#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
-
-#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
-#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
-#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
-#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
-
-#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
-#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
-#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
-#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
-
-/****************** Bit definition for FSMC_PIO4 register *******************/
-#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
-#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
-#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
-
-#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
-#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
-#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
-#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
-
-#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
-#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
-#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
-#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
-
-#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
-#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
-#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
-#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
-
-/****************** Bit definition for FSMC_ECCR2 register ******************/
-#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
-
-/****************** Bit definition for FSMC_ECCR3 register ******************/
-#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
-
-/******************************************************************************/
-/* */
-/* General Purpose I/O */
-/* */
-/******************************************************************************/
-/****************** Bits definition for GPIO_MODER register *****************/
-#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
-
-#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
-
-#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
-
-#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
-
-#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
-
-#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
-
-#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
-
-#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
-
-#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
-
-#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
-
-#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
-
-#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
-
-#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
-
-#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
-
-#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
-
-#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
-
-/****************** Bits definition for GPIO_OTYPER register ****************/
-#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
-
-/****************** Bits definition for GPIO_OSPEEDR register ***************/
-#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
-
-#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
-
-#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
-
-#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
-
-#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
-
-#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
-
-#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
-
-#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
-
-#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
-
-#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
-
-#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
-
-#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
-
-#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
-
-#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
-
-#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
-
-#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
-
-/****************** Bits definition for GPIO_PUPDR register *****************/
-#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
-
-#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
-
-#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
-
-#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
-
-#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
-
-#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
-
-#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
-
-#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
-
-#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
-
-#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
-
-#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
-
-#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
-
-#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
-
-#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
-
-#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
-
-#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
-
-/****************** Bits definition for GPIO_IDR register *******************/
-#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
-#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
-#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
-#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
-#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
-#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
-#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
-#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
-#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
-#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
-#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
-#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
-#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
-#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
-#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
-#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
-#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
-#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
-#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
-#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
-#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
-#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
-#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
-#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
-#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
-#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
-#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
-#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
-#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
-#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
-#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
-
-/****************** Bits definition for GPIO_ODR register *******************/
-#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
-#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
-#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
-#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
-#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
-#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
-#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
-#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
-#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
-#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
-#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
-#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
-#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
-#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
-#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
-#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
-#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
-#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
-#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
-#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
-#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
-#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
-#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
-#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
-#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
-#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
-#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
-#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
-#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
-#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
-#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
-
-/****************** Bits definition for GPIO_BSRR register ******************/
-#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
-
-/******************************************************************************/
-/* */
-/* HASH */
-/* */
-/******************************************************************************/
-/****************** Bits definition for HASH_CR register ********************/
-#define HASH_CR_INIT ((uint32_t)0x00000004)
-#define HASH_CR_DMAE ((uint32_t)0x00000008)
-#define HASH_CR_DATATYPE ((uint32_t)0x00000030)
-#define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)
-#define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)
-#define HASH_CR_MODE ((uint32_t)0x00000040)
-#define HASH_CR_ALGO ((uint32_t)0x00000080)
-#define HASH_CR_NBW ((uint32_t)0x00000F00)
-#define HASH_CR_NBW_0 ((uint32_t)0x00000100)
-#define HASH_CR_NBW_1 ((uint32_t)0x00000200)
-#define HASH_CR_NBW_2 ((uint32_t)0x00000400)
-#define HASH_CR_NBW_3 ((uint32_t)0x00000800)
-#define HASH_CR_DINNE ((uint32_t)0x00001000)
-#define HASH_CR_LKEY ((uint32_t)0x00010000)
-
-/****************** Bits definition for HASH_STR register *******************/
-#define HASH_STR_NBW ((uint32_t)0x0000001F)
-#define HASH_STR_NBW_0 ((uint32_t)0x00000001)
-#define HASH_STR_NBW_1 ((uint32_t)0x00000002)
-#define HASH_STR_NBW_2 ((uint32_t)0x00000004)
-#define HASH_STR_NBW_3 ((uint32_t)0x00000008)
-#define HASH_STR_NBW_4 ((uint32_t)0x00000010)
-#define HASH_STR_DCAL ((uint32_t)0x00000100)
-
-/****************** Bits definition for HASH_IMR register *******************/
-#define HASH_IMR_DINIM ((uint32_t)0x00000001)
-#define HASH_IMR_DCIM ((uint32_t)0x00000002)
-
-/****************** Bits definition for HASH_SR register ********************/
-#define HASH_SR_DINIS ((uint32_t)0x00000001)
-#define HASH_SR_DCIS ((uint32_t)0x00000002)
-#define HASH_SR_DMAS ((uint32_t)0x00000004)
-#define HASH_SR_BUSY ((uint32_t)0x00000008)
-
-/******************************************************************************/
-/* */
-/* Inter-integrated Circuit Interface */
-/* */
-/******************************************************************************/
-/******************* Bit definition for I2C_CR1 register ********************/
-#define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */
-#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */
-#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */
-#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */
-#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */
-#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */
-#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */
-#define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */
-#define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */
-#define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */
-#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */
-#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */
-
-/******************* Bit definition for I2C_CR2 register ********************/
-#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */
-#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */
-#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */
-#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */
-
-#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */
-#define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */
-
-/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */
-
-#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */
-#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */
-#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */
-#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */
-#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */
-#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */
-#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */
-#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */
-
-#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */
-
-/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */
-#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */
-
-/******************** Bit definition for I2C_DR register ********************/
-#define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */
-
-/******************* Bit definition for I2C_SR1 register ********************/
-#define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */
-#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */
-#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */
-#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */
-#define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */
-#define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */
-#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */
-#define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */
-#define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */
-#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */
-#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */
-
-/******************* Bit definition for I2C_SR2 register ********************/
-#define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */
-#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */
-#define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */
-#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */
-#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */
-
-/******************* Bit definition for I2C_CCR register ********************/
-#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */
-#define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */
-
-/****************** Bit definition for I2C_TRISE register *******************/
-#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/* */
-/* Independent WATCHDOG */
-/* */
-/******************************************************************************/
-/******************* Bit definition for IWDG_KR register ********************/
-#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */
-
-/******************* Bit definition for IWDG_PR register ********************/
-#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */
-#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */
-#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */
-
-/******************* Bit definition for IWDG_RLR register *******************/
-#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */
-
-/******************* Bit definition for IWDG_SR register ********************/
-#define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */
-#define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */
-
-/******************************************************************************/
-/* */
-/* Power Control */
-/* */
-/******************************************************************************/
-/******************** Bit definition for PWR_CR register ********************/
-#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */
-#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
-#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
-#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
-#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
-
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */
-
-#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
-#define PWR_CR_FPDS ((uint16_t)0x0200) /*!< Flash power down in Stop mode */
-#define PWR_CR_VOS ((uint16_t)0x4000) /*!< Regulator voltage scaling output selection */
-/* Legacy define */
-#define PWR_CR_PMODE PWR_CR_VOS
-
-/******************* Bit definition for PWR_CSR register ********************/
-#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
-#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
-#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
-#define PWR_CSR_BRR ((uint16_t)0x0008) /*!< Backup regulator ready */
-#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */
-#define PWR_CSR_BRE ((uint16_t)0x0200) /*!< Backup regulator enable */
-#define PWR_CSR_VOSRDY ((uint16_t)0x4000) /*!< Regulator voltage scaling output selection ready */
-/* Legacy define */
-#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/* */
-/* Reset and Clock Control */
-/* */
-/******************************************************************************/
-/******************** Bit definition for RCC_CR register ********************/
-#define RCC_CR_HSION ((uint32_t)0x00000001)
-#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
-
-#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
-#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
-#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
-#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
-#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
-#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
-
-#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
-#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
-#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
-#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
-#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
-#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
-#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
-#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
-#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
-
-#define RCC_CR_HSEON ((uint32_t)0x00010000)
-#define RCC_CR_HSERDY ((uint32_t)0x00020000)
-#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
-#define RCC_CR_CSSON ((uint32_t)0x00080000)
-#define RCC_CR_PLLON ((uint32_t)0x01000000)
-#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
-#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
-#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
-
-/******************** Bit definition for RCC_PLLCFGR register ***************/
-#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
-#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
-#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
-#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
-#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
-#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
-#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
-
-#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
-#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
-#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
-#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
-#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
-#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
-#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
-#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
-#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
-#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
-
-#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
-#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
-#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
-
-#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
-#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
-#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
-
-#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
-#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
-#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
-#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
-#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
-
-/******************** Bit definition for RCC_CFGR register ******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
-#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
-#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
-
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
-#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
-#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
-#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
-#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
-#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
-
-/*!< MCO1 configuration */
-#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
-#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
-#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
-
-#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
-
-#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
-#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
-#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
-#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
-
-#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
-#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
-#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
-#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
-
-#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
-#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
-#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
-
-/******************** Bit definition for RCC_CIR register *******************/
-#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
-#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
-#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
-#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
-#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
-#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
-#define RCC_CIR_CSSF ((uint32_t)0x00000080)
-#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
-#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
-#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
-#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
-#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
-#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
-#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
-#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
-#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
-#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
-#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
-#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
-#define RCC_CIR_CSSC ((uint32_t)0x00800000)
-
-/******************** Bit definition for RCC_AHB1RSTR register **************/
-#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
-#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
-#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
-#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
-#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
-#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
-#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
-#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
-#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
-#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
-#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
-#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
-#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
-
-/******************** Bit definition for RCC_AHB2RSTR register **************/
-#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
-#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
-#define RCC_AHB2RSTR_HSAHRST ((uint32_t)0x00000020)
-#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
-#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
-
-/******************** Bit definition for RCC_AHB3RSTR register **************/
-#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
-
-/******************** Bit definition for RCC_APB1RSTR register **************/
-#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
-#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
-#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
-#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
-#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
-#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
-#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
-#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
-#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
-#define RCC_APB1RSTR_WWDGEN ((uint32_t)0x00000800)
-#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00008000)
-#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00010000)
-#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
-#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
-#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
-#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
-#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
-#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
-#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
-#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
-#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
-#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
-#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
-
-/******************** Bit definition for RCC_APB2RSTR register **************/
-#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
-#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
-#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
-#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
-#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
-#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
-#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
-#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
-#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
-#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
-#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
-/* Old SPI1RST bit definition, maintained for legacy purpose */
-#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
-
-/******************** Bit definition for RCC_AHB1ENR register ***************/
-#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
-#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
-#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
-#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
-#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
-#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
-#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
-#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
-#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
-#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
-#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
-#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
-#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
-#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
-#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
-#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
-#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
-#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
-#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
-#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
-
-/******************** Bit definition for RCC_AHB2ENR register ***************/
-#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
-#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
-#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
-#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
-#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
-
-/******************** Bit definition for RCC_AHB3ENR register ***************/
-#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
-
-/******************** Bit definition for RCC_APB1ENR register ***************/
-#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
-#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
-#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
-#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
-#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
-#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
-#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
-#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
-#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
-#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
-#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
-#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
-#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
-#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
-#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
-#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
-#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
-#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
-#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
-#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
-#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
-#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
-#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
-
-/******************** Bit definition for RCC_APB2ENR register ***************/
-#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
-#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
-#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
-#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
-#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
-#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
-#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
-#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
-#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
-#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
-#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
-#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
-#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
-
-/******************** Bit definition for RCC_AHB1LPENR register *************/
-#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
-#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
-#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
-#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
-#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
-#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
-#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
-#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
-#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
-#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
-#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
-#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
-#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
-#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
-#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
-#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
-#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
-#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
-#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
-#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
-#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
-#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
-
-/******************** Bit definition for RCC_AHB2LPENR register *************/
-#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
-#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
-#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
-#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
-#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
-
-/******************** Bit definition for RCC_AHB3LPENR register *************/
-#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
-
-/******************** Bit definition for RCC_APB1LPENR register *************/
-#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
-#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
-#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
-#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
-#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
-#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
-#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
-#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
-#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
-#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
-#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
-#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
-#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
-#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
-#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
-#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
-#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
-#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
-#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
-#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
-#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
-#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
-#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
-
-/******************** Bit definition for RCC_APB2LPENR register *************/
-#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
-#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
-#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
-#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
-#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
-#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)
-#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
-#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
-#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
-#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
-#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
-#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
-#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
-
-/******************** Bit definition for RCC_BDCR register ******************/
-#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
-#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
-#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
-
-#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
-#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
-#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
-
-#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
-#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
-
-/******************** Bit definition for RCC_CSR register *******************/
-#define RCC_CSR_LSION ((uint32_t)0x00000001)
-#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
-#define RCC_CSR_RMVF ((uint32_t)0x01000000)
-#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
-#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
-#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
-#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
-#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
-#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
-#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
-
-/******************** Bit definition for RCC_SSCGR register *****************/
-#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
-#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
-#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
-#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
-
-/******************** Bit definition for RCC_PLLI2SCFGR register ************/
-#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
-#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
-
-/******************************************************************************/
-/* */
-/* RNG */
-/* */
-/******************************************************************************/
-/******************** Bits definition for RNG_CR register *******************/
-#define RNG_CR_RNGEN ((uint32_t)0x00000004)
-#define RNG_CR_IE ((uint32_t)0x00000008)
-
-/******************** Bits definition for RNG_SR register *******************/
-#define RNG_SR_DRDY ((uint32_t)0x00000001)
-#define RNG_SR_CECS ((uint32_t)0x00000002)
-#define RNG_SR_SECS ((uint32_t)0x00000004)
-#define RNG_SR_CEIS ((uint32_t)0x00000020)
-#define RNG_SR_SEIS ((uint32_t)0x00000040)
-
-/******************************************************************************/
-/* */
-/* Real-Time Clock (RTC) */
-/* */
-/******************************************************************************/
-/******************** Bits definition for RTC_TR register *******************/
-#define RTC_TR_PM ((uint32_t)0x00400000)
-#define RTC_TR_HT ((uint32_t)0x00300000)
-#define RTC_TR_HT_0 ((uint32_t)0x00100000)
-#define RTC_TR_HT_1 ((uint32_t)0x00200000)
-#define RTC_TR_HU ((uint32_t)0x000F0000)
-#define RTC_TR_HU_0 ((uint32_t)0x00010000)
-#define RTC_TR_HU_1 ((uint32_t)0x00020000)
-#define RTC_TR_HU_2 ((uint32_t)0x00040000)
-#define RTC_TR_HU_3 ((uint32_t)0x00080000)
-#define RTC_TR_MNT ((uint32_t)0x00007000)
-#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
-#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
-#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
-#define RTC_TR_MNU ((uint32_t)0x00000F00)
-#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
-#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
-#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
-#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
-#define RTC_TR_ST ((uint32_t)0x00000070)
-#define RTC_TR_ST_0 ((uint32_t)0x00000010)
-#define RTC_TR_ST_1 ((uint32_t)0x00000020)
-#define RTC_TR_ST_2 ((uint32_t)0x00000040)
-#define RTC_TR_SU ((uint32_t)0x0000000F)
-#define RTC_TR_SU_0 ((uint32_t)0x00000001)
-#define RTC_TR_SU_1 ((uint32_t)0x00000002)
-#define RTC_TR_SU_2 ((uint32_t)0x00000004)
-#define RTC_TR_SU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_DR register *******************/
-#define RTC_DR_YT ((uint32_t)0x00F00000)
-#define RTC_DR_YT_0 ((uint32_t)0x00100000)
-#define RTC_DR_YT_1 ((uint32_t)0x00200000)
-#define RTC_DR_YT_2 ((uint32_t)0x00400000)
-#define RTC_DR_YT_3 ((uint32_t)0x00800000)
-#define RTC_DR_YU ((uint32_t)0x000F0000)
-#define RTC_DR_YU_0 ((uint32_t)0x00010000)
-#define RTC_DR_YU_1 ((uint32_t)0x00020000)
-#define RTC_DR_YU_2 ((uint32_t)0x00040000)
-#define RTC_DR_YU_3 ((uint32_t)0x00080000)
-#define RTC_DR_WDU ((uint32_t)0x0000E000)
-#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
-#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
-#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
-#define RTC_DR_MT ((uint32_t)0x00001000)
-#define RTC_DR_MU ((uint32_t)0x00000F00)
-#define RTC_DR_MU_0 ((uint32_t)0x00000100)
-#define RTC_DR_MU_1 ((uint32_t)0x00000200)
-#define RTC_DR_MU_2 ((uint32_t)0x00000400)
-#define RTC_DR_MU_3 ((uint32_t)0x00000800)
-#define RTC_DR_DT ((uint32_t)0x00000030)
-#define RTC_DR_DT_0 ((uint32_t)0x00000010)
-#define RTC_DR_DT_1 ((uint32_t)0x00000020)
-#define RTC_DR_DU ((uint32_t)0x0000000F)
-#define RTC_DR_DU_0 ((uint32_t)0x00000001)
-#define RTC_DR_DU_1 ((uint32_t)0x00000002)
-#define RTC_DR_DU_2 ((uint32_t)0x00000004)
-#define RTC_DR_DU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_CR register *******************/
-#define RTC_CR_COE ((uint32_t)0x00800000)
-#define RTC_CR_OSEL ((uint32_t)0x00600000)
-#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
-#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
-#define RTC_CR_POL ((uint32_t)0x00100000)
-#define RTC_CR_COSEL ((uint32_t)0x00080000)
-#define RTC_CR_BCK ((uint32_t)0x00040000)
-#define RTC_CR_SUB1H ((uint32_t)0x00020000)
-#define RTC_CR_ADD1H ((uint32_t)0x00010000)
-#define RTC_CR_TSIE ((uint32_t)0x00008000)
-#define RTC_CR_WUTIE ((uint32_t)0x00004000)
-#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
-#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
-#define RTC_CR_TSE ((uint32_t)0x00000800)
-#define RTC_CR_WUTE ((uint32_t)0x00000400)
-#define RTC_CR_ALRBE ((uint32_t)0x00000200)
-#define RTC_CR_ALRAE ((uint32_t)0x00000100)
-#define RTC_CR_DCE ((uint32_t)0x00000080)
-#define RTC_CR_FMT ((uint32_t)0x00000040)
-#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
-#define RTC_CR_REFCKON ((uint32_t)0x00000010)
-#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
-#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
-#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
-#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
-#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
-
-/******************** Bits definition for RTC_ISR register ******************/
-#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
-#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
-#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
-#define RTC_ISR_TSF ((uint32_t)0x00000800)
-#define RTC_ISR_WUTF ((uint32_t)0x00000400)
-#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
-#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
-#define RTC_ISR_INIT ((uint32_t)0x00000080)
-#define RTC_ISR_INITF ((uint32_t)0x00000040)
-#define RTC_ISR_RSF ((uint32_t)0x00000020)
-#define RTC_ISR_INITS ((uint32_t)0x00000010)
-#define RTC_ISR_SHPF ((uint32_t)0x00000008)
-#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
-#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
-#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
-
-/******************** Bits definition for RTC_PRER register *****************/
-#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
-
-/******************** Bits definition for RTC_WUTR register *****************/
-#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
-
-/******************** Bits definition for RTC_CALIBR register ***************/
-#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
-#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
-
-/******************** Bits definition for RTC_ALRMAR register ***************/
-#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
-#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
-#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
-#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
-#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
-#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
-#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
-#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
-#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
-#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
-#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
-#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
-#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
-#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
-#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
-#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
-#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
-#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
-#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
-#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
-#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
-#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
-#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
-#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
-#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
-#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
-#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
-#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
-#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
-#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
-#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
-#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
-#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
-#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
-#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
-#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
-#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
-#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
-#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
-#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_ALRMBR register ***************/
-#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
-#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
-#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
-#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
-#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
-#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
-#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
-#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
-#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
-#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
-#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
-#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
-#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
-#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
-#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
-#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
-#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
-#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
-#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
-#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
-#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
-#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
-#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
-#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
-#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
-#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
-#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
-#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
-#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
-#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
-#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
-#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
-#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
-#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
-#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
-#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
-#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
-#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
-#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
-#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_WPR register ******************/
-#define RTC_WPR_KEY ((uint32_t)0x000000FF)
-
-/******************** Bits definition for RTC_SSR register ******************/
-#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
-
-/******************** Bits definition for RTC_SHIFTR register ***************/
-#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
-#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
-
-/******************** Bits definition for RTC_TSTR register *****************/
-#define RTC_TSTR_PM ((uint32_t)0x00400000)
-#define RTC_TSTR_HT ((uint32_t)0x00300000)
-#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
-#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
-#define RTC_TSTR_HU ((uint32_t)0x000F0000)
-#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
-#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
-#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
-#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
-#define RTC_TSTR_MNT ((uint32_t)0x00007000)
-#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
-#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
-#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
-#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
-#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
-#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
-#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
-#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
-#define RTC_TSTR_ST ((uint32_t)0x00000070)
-#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
-#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
-#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
-#define RTC_TSTR_SU ((uint32_t)0x0000000F)
-#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
-#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
-#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
-#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_TSDR register *****************/
-#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
-#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
-#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
-#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
-#define RTC_TSDR_MT ((uint32_t)0x00001000)
-#define RTC_TSDR_MU ((uint32_t)0x00000F00)
-#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
-#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
-#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
-#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
-#define RTC_TSDR_DT ((uint32_t)0x00000030)
-#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
-#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
-#define RTC_TSDR_DU ((uint32_t)0x0000000F)
-#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
-#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
-#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
-#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_TSSSR register ****************/
-#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
-
-/******************** Bits definition for RTC_CAL register *****************/
-#define RTC_CALR_CALP ((uint32_t)0x00008000)
-#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
-#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
-#define RTC_CALR_CALM ((uint32_t)0x000001FF)
-#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
-#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
-#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
-#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
-#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
-#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
-#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
-#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
-#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
-
-/******************** Bits definition for RTC_TAFCR register ****************/
-#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
-#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
-#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
-#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
-#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
-#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
-#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
-#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
-#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
-#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
-#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
-#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
-#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
-#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
-#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
-#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
-#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
-#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
-
-/******************** Bits definition for RTC_ALRMASSR register *************/
-#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
-
-/******************** Bits definition for RTC_ALRMBSSR register *************/
-#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
-#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
-#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
-#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
-#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
-#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
-
-/******************** Bits definition for RTC_BKP0R register ****************/
-#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP1R register ****************/
-#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP2R register ****************/
-#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP3R register ****************/
-#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP4R register ****************/
-#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP5R register ****************/
-#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP6R register ****************/
-#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP7R register ****************/
-#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP8R register ****************/
-#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP9R register ****************/
-#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP10R register ***************/
-#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP11R register ***************/
-#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP12R register ***************/
-#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP13R register ***************/
-#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP14R register ***************/
-#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP15R register ***************/
-#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP16R register ***************/
-#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP17R register ***************/
-#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP18R register ***************/
-#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP19R register ***************/
-#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
-
-/******************************************************************************/
-/* */
-/* SD host Interface */
-/* */
-/******************************************************************************/
-/****************** Bit definition for SDIO_POWER register ******************/
-#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */
-#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */
-
-/****************** Bit definition for SDIO_CLKCR register ******************/
-#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */
-#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */
-#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */
-#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */
-
-#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */
-#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */
-
-#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */
-#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */
-
-/******************* Bit definition for SDIO_ARG register *******************/
-#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
-
-/******************* Bit definition for SDIO_CMD register *******************/
-#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */
-
-#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
-#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
-
-#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */
-#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
-#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */
-#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */
-#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */
-#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */
-
-/***************** Bit definition for SDIO_RESPCMD register *****************/
-#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */
-
-/****************** Bit definition for SDIO_RESP0 register ******************/
-#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
-
-/****************** Bit definition for SDIO_RESP1 register ******************/
-#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
-
-/****************** Bit definition for SDIO_RESP2 register ******************/
-#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
-
-/****************** Bit definition for SDIO_RESP3 register ******************/
-#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
-
-/****************** Bit definition for SDIO_RESP4 register ******************/
-#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
-
-/****************** Bit definition for SDIO_DTIMER register *****************/
-#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
-
-/****************** Bit definition for SDIO_DLEN register *******************/
-#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
-
-/****************** Bit definition for SDIO_DCTRL register ******************/
-#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */
-#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */
-#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */
-#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */
-
-#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */
-#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */
-
-#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */
-#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */
-#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */
-#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */
-
-/****************** Bit definition for SDIO_DCOUNT register *****************/
-#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
-
-/****************** Bit definition for SDIO_STA register ********************/
-#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
-#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
-#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
-#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
-#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
-#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
-#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
-#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
-#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
-#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
-#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
-#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
-#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
-#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
-#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
-#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
-#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
-#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
-#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
-#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
-#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
-#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
-
-/******************* Bit definition for SDIO_ICR register *******************/
-#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
-#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
-#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
-#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
-#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
-#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
-#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
-#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
-#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
-#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
-#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
-#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
-#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
-
-/****************** Bit definition for SDIO_MASK register *******************/
-#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
-#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
-#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
-#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
-#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
-#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
-#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
-#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
-#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
-#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
-#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
-#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
-#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
-#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
-#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
-#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
-#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
-#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
-#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
-#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
-#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/***************** Bit definition for SDIO_FIFOCNT register *****************/
-#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
-
-/****************** Bit definition for SDIO_FIFO register *******************/
-#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/* */
-/* Serial Peripheral Interface */
-/* */
-/******************************************************************************/
-/******************* Bit definition for SPI_CR1 register ********************/
-#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */
-#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */
-#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */
-
-#define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */
-#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */
-#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */
-
-#define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */
-#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */
-#define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */
-#define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */
-#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */
-#define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */
-#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */
-#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */
-
-/******************* Bit definition for SPI_CR2 register ********************/
-#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */
-#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */
-#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */
-
-/******************** Bit definition for SPI_SR register ********************/
-#define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */
-#define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */
-#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */
-#define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */
-#define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */
-#define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */
-#define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */
-#define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */
-
-/******************** Bit definition for SPI_DR register ********************/
-#define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */
-
-/******************* Bit definition for SPI_CRCPR register ******************/
-#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */
-
-/****************** Bit definition for SPI_RXCRCR register ******************/
-#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */
-
-/****************** Bit definition for SPI_TXCRCR register ******************/
-#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */
-
-/****************** Bit definition for SPI_I2SCFGR register *****************/
-#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
-#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
-
-#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
-
-#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
-
-#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
-
-/****************** Bit definition for SPI_I2SPR register *******************/
-#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/* */
-/* SYSCFG */
-/* */
-/******************************************************************************/
-/****************** Bit definition for SYSCFG_MEMRMP register ***************/
-#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*!<SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
-#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
-
-/****************** Bit definition for SYSCFG_PMC register ******************/
-#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
-/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
-#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
-
-/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
-#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!<EXTI 3 configuration */
-/**
- * @brief EXTI0 configuration
- */
-#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) /*!<PI[0] pin */
-/**
- * @brief EXTI1 configuration
- */
-#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) /*!<PI[1] pin */
-/**
- * @brief EXTI2 configuration
- */
-#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) /*!<PI[2] pin */
-/**
- * @brief EXTI3 configuration
- */
-#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) /*!<PI[3] pin */
-
-/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
-#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!<EXTI 7 configuration */
-/**
- * @brief EXTI4 configuration
- */
-#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) /*!<PI[4] pin */
-/**
- * @brief EXTI5 configuration
- */
-#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) /*!<PI[5] pin */
-/**
- * @brief EXTI6 configuration
- */
-#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) /*!<PI[6] pin */
-/**
- * @brief EXTI7 configuration
- */
-#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) /*!<PI[7] pin */
-
-/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
-#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!<EXTI 11 configuration */
-
-/**
- * @brief EXTI8 configuration
- */
-#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) /*!<PI[8] pin */
-/**
- * @brief EXTI9 configuration
- */
-#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) /*!<PI[9] pin */
-/**
- * @brief EXTI10 configuration
- */
-#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) /*!<PI[10] pin */
-/**
- * @brief EXTI11 configuration
- */
-#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) /*!<PI[11] pin */
-
-/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
-#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!<EXTI 15 configuration */
-/**
- * @brief EXTI12 configuration
- */
-#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!<PG[12] pin */
-#define SYSCFG_EXTICR3_EXTI12_PH ((uint16_t)0x0007) /*!<PH[12] pin */
-/**
- * @brief EXTI13 configuration
- */
-#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!<PG[13] pin */
-#define SYSCFG_EXTICR3_EXTI13_PH ((uint16_t)0x0070) /*!<PH[13] pin */
-/**
- * @brief EXTI14 configuration
- */
-#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!<PG[14] pin */
-#define SYSCFG_EXTICR3_EXTI14_PH ((uint16_t)0x0700) /*!<PH[14] pin */
-/**
- * @brief EXTI15 configuration
- */
-#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!<PG[15] pin */
-#define SYSCFG_EXTICR3_EXTI15_PH ((uint16_t)0x7000) /*!<PH[15] pin */
-
-/****************** Bit definition for SYSCFG_CMPCR register ****************/
-#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
-
-/******************************************************************************/
-/* */
-/* TIM */
-/* */
-/******************************************************************************/
-/******************* Bit definition for TIM_CR1 register ********************/
-#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
-#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
-#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
-#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
-#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
-
-#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
-#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
-
-#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
-
-/******************* Bit definition for TIM_CR2 register ********************/
-#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
-
-#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
-#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
-
-/******************* Bit definition for TIM_SMCR register *******************/
-#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
-
-#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
-
-#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
-#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
-#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
-
-#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
-
-#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
-#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
-
-/******************* Bit definition for TIM_DIER register *******************/
-#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
-#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
-#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
-#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
-#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
-
-/******************** Bit definition for TIM_SR register ********************/
-#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
-#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
-#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
-#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
-
-/******************* Bit definition for TIM_EGR register ********************/
-#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
-#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
-#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
-
-/****************** Bit definition for TIM_CCMR1 register *******************/
-#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
-
-#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
-
-#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
-
-#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
-
-#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
-#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
-
-#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
-#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
-
-#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
-
-#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
-#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
-
-/****************** Bit definition for TIM_CCMR2 register *******************/
-#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
-
-#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
-
-#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
-
-#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
-
-#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
-#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
-
-#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
-#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
-
-#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
-
-#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
-#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
-
-/******************* Bit definition for TIM_CCER register *******************/
-#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
-
-/******************* Bit definition for TIM_CNT register ********************/
-#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
-
-/******************* Bit definition for TIM_PSC register ********************/
-#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
-
-/******************* Bit definition for TIM_ARR register ********************/
-#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
-
-/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
-
-/******************* Bit definition for TIM_CCR1 register *******************/
-#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
-
-/******************* Bit definition for TIM_CCR2 register *******************/
-#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
-
-/******************* Bit definition for TIM_CCR3 register *******************/
-#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
-
-/******************* Bit definition for TIM_CCR4 register *******************/
-#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
-
-/******************* Bit definition for TIM_BDTR register *******************/
-#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
-#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
-#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
-#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
-#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
-#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
-
-#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
-
-#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
-#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
-#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
-#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
-#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
-
-/******************* Bit definition for TIM_DCR register ********************/
-#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
-#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
-#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
-
-#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
-#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
-#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
-#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
-
-/******************* Bit definition for TIM_DMAR register *******************/
-#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
-
-/******************* Bit definition for TIM_OR register *********************/
-#define TIM_OR_TI4_RMP ((uint16_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
-#define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) /*!<Bit 1 */
-
-
-/******************************************************************************/
-/* */
-/* Universal Synchronous Asynchronous Receiver Transmitter */
-/* */
-/******************************************************************************/
-/******************* Bit definition for USART_SR register *******************/
-#define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */
-#define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */
-#define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */
-#define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */
-#define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */
-#define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */
-#define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */
-#define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */
-#define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */
-#define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */
-
-/******************* Bit definition for USART_DR register *******************/
-#define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */
-
-/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */
-#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */
-
-/****************** Bit definition for USART_CR1 register *******************/
-#define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */
-#define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */
-#define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */
-#define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */
-#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */
-#define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */
-#define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */
-#define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */
-#define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */
-#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */
-#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */
-#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */
-#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversampling by 8 enable */
-
-/****************** Bit definition for USART_CR2 register *******************/
-#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */
-#define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */
-#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */
-#define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */
-#define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */
-#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */
-
-#define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */
-
-#define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */
-
-/****************** Bit definition for USART_CR3 register *******************/
-#define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */
-#define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */
-#define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */
-#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */
-#define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */
-#define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */
-#define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */
-#define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */
-#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */
-#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */
-#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */
-#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<USART One bit method enable */
-
-/****************** Bit definition for USART_GTPR register ******************/
-#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */
-#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */
-#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */
-#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */
-#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */
-#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */
-
-#define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */
-
-/******************************************************************************/
-/* */
-/* Window WATCHDOG */
-/* */
-/******************************************************************************/
-/******************* Bit definition for WWDG_CR register ********************/
-#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */
-#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */
-#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */
-#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */
-#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */
-#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */
-#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */
-
-#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */
-
-/******************* Bit definition for WWDG_CFR register *******************/
-#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */
-#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */
-#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */
-#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */
-#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */
-
-#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */
-#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */
-
-#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */
-
-/******************* Bit definition for WWDG_SR register ********************/
-#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/* */
-/* DBG */
-/* */
-/******************************************************************************/
-/******************** Bit definition for DBGMCU_IDCODE register *************/
-#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
-#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
-
-/******************** Bit definition for DBGMCU_CR register *****************/
-#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
-#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
-#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
-#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
-
-#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
-#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
-#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
-
-/******************** Bit definition for DBGMCU_APB1_FZ register ************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
-#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
-#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
-#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
-#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
-#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
-#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */
-#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
-
-/******************** Bit definition for DBGMCU_APB2_FZ register ************/
-#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
-#define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
-#define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
-#define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
-#define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
-
-/******************************************************************************/
-/* */
-/* Ethernet MAC Registers bits definitions */
-/* */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
-#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
-#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
- #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
- #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
- #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
- #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
- #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
- #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
- #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
-#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
-#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
-#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
-#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
-#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
-#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
-#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
- a transmission attempt during retries after a collision: 0 =< r <2^k */
- #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
- #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
- #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
- #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
-#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
-#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
-#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
-#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
-#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
-#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
-#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
- #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
- #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
- #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
-#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
-#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
-#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
-#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
-#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
-#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
-#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
-#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
- #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
- #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
- #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
- #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
- #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
-#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
-#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
-
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
-#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
- #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
- #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
- #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
- #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
-#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
-#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
-#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
- Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
- Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
- Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
- Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
- Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
- RSVD - Filter1 Command - RSVD - Filter0 Command
- Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
- Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
- Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */
-#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
-#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
-#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
-#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
-#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
-#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
-#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
- #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
- #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
- #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
- #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
- #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
- #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
-#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
-#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
-#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
- #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
- #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
- #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
- #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
- #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
- #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
-#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
-#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
- #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
- #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
- #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
- #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
- #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
- #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
-
-/******************************************************************************/
-/* Ethernet MMC Registers bits definition */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
-#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
-#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
-#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/* Ethernet PTP Registers bits definition */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
-
-#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
-#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
-
-/* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
-
-/******************************************************************************/
-/* Ethernet DMA Registers bits definition */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
-#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
-#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
-#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
- #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
- #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
- #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
- #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
- #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
- #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
- #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
- #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
- #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
- #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
- #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
- #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
-#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
-#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
- #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
- #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
- #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
- #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
-#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
- #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
- #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
- #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
- #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
- #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
- #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
- #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
- #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
- #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
- #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
- #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
- #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
-#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
-#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
-#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
-#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
- /* combination with EBS[2:0] for GetFlagStatus function */
- #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
- #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
- #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
- #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
- #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
- #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
- #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
- #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
- #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
- #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
- #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
- #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
- #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
- #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
- #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
-#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
-#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
-#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
-#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
-#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
-#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
-#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
-#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
-#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
-#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
-#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
-#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
- #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
- #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
- #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
- #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
- #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
- #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
- #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
- #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
-#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
- #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
- #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
- #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
- #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
-#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
-
-/**
- * @}
- */
-
- /**
- * @}
- */
-
-#ifdef USE_STDPERIPH_DRIVER
- #include "stm32f4xx_conf.h"
-#endif /* USE_STDPERIPH_DRIVER */
-
-/** @addtogroup Exported_macro
- * @{
- */
-
-#define SET_BIT(REG, BIT) ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT) ((REG) & (BIT))
-
-#define CLEAR_REG(REG) ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL) ((REG) = (VAL))
-
-#define READ_REG(REG) ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F4xx_H */
-
-/**
- * @}
- */
-
- /**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-//#include "stm32f4xx_conf.h"
-/**
- ******************************************************************************
- * @file system_stm32f4xx.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 30-September-2011
- * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f4xx_system
- * @{
- */
-
-/**
- * @brief Define to prevent recursive inclusion
- */
-#ifndef __SYSTEM_STM32F4XX_H
-#define __SYSTEM_STM32F4XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup STM32F4xx_System_Includes
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @addtogroup STM32F4xx_System_Exported_types
- * @{
- */
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Exported_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Exported_Functions
- * @{
- */
-
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F4XX_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file misc.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the miscellaneous
- * firmware library functions (add-on to CMSIS functions).
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MISC_H
-#define __MISC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup MISC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief NVIC Init Structure definition
- */
-
-typedef struct
-{
- uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
- This parameter can be an enumerator of @ref IRQn_Type
- enumeration (For the complete STM32 Devices IRQ Channels
- list, please refer to stm32f4xx.h file) */
-
- uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
- specified in NVIC_IRQChannel. This parameter can be a value
- between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
- A lower priority value indicates a higher priority */
-
- uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
- in NVIC_IRQChannel. This parameter can be a value
- between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
- A lower priority value indicates a higher priority */
-
- FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
- will be enabled or disabled.
- This parameter can be set either to ENABLE or DISABLE */
-} NVIC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup MISC_Exported_Constants
- * @{
- */
-
-/** @defgroup MISC_Vector_Table_Base
- * @{
- */
-
-#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
-#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
-#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
- ((VECTTAB) == NVIC_VectTab_FLASH))
-/**
- * @}
- */
-
-/** @defgroup MISC_System_Low_Power
- * @{
- */
-
-#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
-#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
-#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
-#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
- ((LP) == NVIC_LP_SLEEPDEEP) || \
- ((LP) == NVIC_LP_SLEEPONEXIT))
-/**
- * @}
- */
-
-/** @defgroup MISC_Preemption_Priority_Group
- * @{
- */
-
-#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
- 4 bits for subpriority */
-#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
- 3 bits for subpriority */
-#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
- 2 bits for subpriority */
-#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
- 1 bits for subpriority */
-#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
- 0 bits for subpriority */
-
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
- ((GROUP) == NVIC_PriorityGroup_1) || \
- ((GROUP) == NVIC_PriorityGroup_2) || \
- ((GROUP) == NVIC_PriorityGroup_3) || \
- ((GROUP) == NVIC_PriorityGroup_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
-
-#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
-
-/**
- * @}
- */
-
-/** @defgroup MISC_SysTick_clock_source
- * @{
- */
-
-#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
-#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
- ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __MISC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_adc.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the ADC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_ADC_H
-#define __STM32F4xx_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup ADC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief ADC Init structure definition
- */
-typedef struct
-{
- uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode.
- This parameter can be a value of @ref ADC_resolution */
- FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion
- is performed in Scan (multichannels)
- or Single (one channel) mode.
- This parameter can be set to ENABLE or DISABLE */
- FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion
- is performed in Continuous or Single mode.
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and
- enable the trigger of a regular group.
- This parameter can be a value of
- @ref ADC_external_trigger_edge_for_regular_channels_conversion */
- uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger
- the start of conversion of a regular group.
- This parameter can be a value of
- @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
- uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment
- is left or right. This parameter can be
- a value of @ref ADC_data_align */
- uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions
- that will be done using the sequencer for
- regular channel group.
- This parameter must range from 1 to 16. */
-}ADC_InitTypeDef;
-
-/**
- * @brief ADC Common Init structure definition
- */
-typedef struct
-{
- uint32_t ADC_Mode; /*!< Configures the ADC to operate in
- independent or multi mode.
- This parameter can be a value of @ref ADC_Common_mode */
- uint32_t ADC_Prescaler; /*!< Select the frequency of the clock
- to the ADC. The clock is common for all the ADCs.
- This parameter can be a value of @ref ADC_Prescaler */
- uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access
- mode for multi ADC mode.
- This parameter can be a value of
- @ref ADC_Direct_memory_access_mode_for_multi_mode */
- uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
- This parameter can be a value of
- @ref ADC_delay_between_2_sampling_phases */
-
-}ADC_CommonInitTypeDef;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants
- * @{
- */
-#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
- ((PERIPH) == ADC2) || \
- ((PERIPH) == ADC3))
-
-/** @defgroup ADC_Common_mode
- * @{
- */
-#define ADC_Mode_Independent ((uint32_t)0x00000000)
-#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001)
-#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002)
-#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005)
-#define ADC_DualMode_RegSimult ((uint32_t)0x00000006)
-#define ADC_DualMode_Interl ((uint32_t)0x00000007)
-#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009)
-#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011)
-#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012)
-#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015)
-#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016)
-#define ADC_TripleMode_Interl ((uint32_t)0x00000017)
-#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019)
-#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
- ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
- ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
- ((MODE) == ADC_DualMode_InjecSimult) || \
- ((MODE) == ADC_DualMode_RegSimult) || \
- ((MODE) == ADC_DualMode_Interl) || \
- ((MODE) == ADC_DualMode_AlterTrig) || \
- ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
- ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
- ((MODE) == ADC_TripleMode_InjecSimult) || \
- ((MODE) == ADC_TripleMode_RegSimult) || \
- ((MODE) == ADC_TripleMode_Interl) || \
- ((MODE) == ADC_TripleMode_AlterTrig))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_Prescaler
- * @{
- */
-#define ADC_Prescaler_Div2 ((uint32_t)0x00000000)
-#define ADC_Prescaler_Div4 ((uint32_t)0x00010000)
-#define ADC_Prescaler_Div6 ((uint32_t)0x00020000)
-#define ADC_Prescaler_Div8 ((uint32_t)0x00030000)
-#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
- ((PRESCALER) == ADC_Prescaler_Div4) || \
- ((PRESCALER) == ADC_Prescaler_Div6) || \
- ((PRESCALER) == ADC_Prescaler_Div8))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode
- * @{
- */
-#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */
-#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
-#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
-#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
-#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
- ((MODE) == ADC_DMAAccessMode_1) || \
- ((MODE) == ADC_DMAAccessMode_2) || \
- ((MODE) == ADC_DMAAccessMode_3))
-
-/**
- * @}
- */
-
-
-/** @defgroup ADC_delay_between_2_sampling_phases
- * @{
- */
-#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000)
-#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100)
-#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200)
-#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300)
-#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400)
-#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500)
-#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600)
-#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700)
-#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800)
-#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900)
-#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00)
-#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00)
-#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00)
-#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00)
-#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00)
-#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00)
-#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_20Cycles))
-
-/**
- * @}
- */
-
-
-/** @defgroup ADC_resolution
- * @{
- */
-#define ADC_Resolution_12b ((uint32_t)0x00000000)
-#define ADC_Resolution_10b ((uint32_t)0x01000000)
-#define ADC_Resolution_8b ((uint32_t)0x02000000)
-#define ADC_Resolution_6b ((uint32_t)0x03000000)
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
- ((RESOLUTION) == ADC_Resolution_10b) || \
- ((RESOLUTION) == ADC_Resolution_8b) || \
- ((RESOLUTION) == ADC_Resolution_6b))
-
-/**
- * @}
- */
-
-
-/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
- * @{
- */
-#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
-#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)
-#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)
-#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
-#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
- ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
- ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
- ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion
- * @{
- */
-#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
-#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000)
-#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000)
-#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)
-#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000)
-#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000)
-#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)
-#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)
-#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000)
-#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000)
-#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000)
-#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000)
-#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000)
-#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000)
-#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000)
-#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)
-#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
- ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_data_align
- * @{
- */
-#define ADC_DataAlign_Right ((uint32_t)0x00000000)
-#define ADC_DataAlign_Left ((uint32_t)0x00000800)
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
- ((ALIGN) == ADC_DataAlign_Left))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_channels
- * @{
- */
-#define ADC_Channel_0 ((uint8_t)0x00)
-#define ADC_Channel_1 ((uint8_t)0x01)
-#define ADC_Channel_2 ((uint8_t)0x02)
-#define ADC_Channel_3 ((uint8_t)0x03)
-#define ADC_Channel_4 ((uint8_t)0x04)
-#define ADC_Channel_5 ((uint8_t)0x05)
-#define ADC_Channel_6 ((uint8_t)0x06)
-#define ADC_Channel_7 ((uint8_t)0x07)
-#define ADC_Channel_8 ((uint8_t)0x08)
-#define ADC_Channel_9 ((uint8_t)0x09)
-#define ADC_Channel_10 ((uint8_t)0x0A)
-#define ADC_Channel_11 ((uint8_t)0x0B)
-#define ADC_Channel_12 ((uint8_t)0x0C)
-#define ADC_Channel_13 ((uint8_t)0x0D)
-#define ADC_Channel_14 ((uint8_t)0x0E)
-#define ADC_Channel_15 ((uint8_t)0x0F)
-#define ADC_Channel_16 ((uint8_t)0x10)
-#define ADC_Channel_17 ((uint8_t)0x11)
-#define ADC_Channel_18 ((uint8_t)0x12)
-
-#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
-#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
-#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18)
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
- ((CHANNEL) == ADC_Channel_1) || \
- ((CHANNEL) == ADC_Channel_2) || \
- ((CHANNEL) == ADC_Channel_3) || \
- ((CHANNEL) == ADC_Channel_4) || \
- ((CHANNEL) == ADC_Channel_5) || \
- ((CHANNEL) == ADC_Channel_6) || \
- ((CHANNEL) == ADC_Channel_7) || \
- ((CHANNEL) == ADC_Channel_8) || \
- ((CHANNEL) == ADC_Channel_9) || \
- ((CHANNEL) == ADC_Channel_10) || \
- ((CHANNEL) == ADC_Channel_11) || \
- ((CHANNEL) == ADC_Channel_12) || \
- ((CHANNEL) == ADC_Channel_13) || \
- ((CHANNEL) == ADC_Channel_14) || \
- ((CHANNEL) == ADC_Channel_15) || \
- ((CHANNEL) == ADC_Channel_16) || \
- ((CHANNEL) == ADC_Channel_17) || \
- ((CHANNEL) == ADC_Channel_18))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_sampling_times
- * @{
- */
-#define ADC_SampleTime_3Cycles ((uint8_t)0x00)
-#define ADC_SampleTime_15Cycles ((uint8_t)0x01)
-#define ADC_SampleTime_28Cycles ((uint8_t)0x02)
-#define ADC_SampleTime_56Cycles ((uint8_t)0x03)
-#define ADC_SampleTime_84Cycles ((uint8_t)0x04)
-#define ADC_SampleTime_112Cycles ((uint8_t)0x05)
-#define ADC_SampleTime_144Cycles ((uint8_t)0x06)
-#define ADC_SampleTime_480Cycles ((uint8_t)0x07)
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
- ((TIME) == ADC_SampleTime_15Cycles) || \
- ((TIME) == ADC_SampleTime_28Cycles) || \
- ((TIME) == ADC_SampleTime_56Cycles) || \
- ((TIME) == ADC_SampleTime_84Cycles) || \
- ((TIME) == ADC_SampleTime_112Cycles) || \
- ((TIME) == ADC_SampleTime_144Cycles) || \
- ((TIME) == ADC_SampleTime_480Cycles))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion
- * @{
- */
-#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)
-#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)
-#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)
-#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
-#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
- ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
- ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
- ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
-
-/**
- * @}
- */
-
-
-/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion
- * @{
- */
-#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000)
-#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000)
-#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000)
-#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000)
-#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000)
-#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000)
-#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)
-#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)
-#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)
-#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000)
-#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000)
-#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000)
-#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000)
-#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000)
-#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000)
-#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)
-#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_injected_channel_selection
- * @{
- */
-#define ADC_InjectedChannel_1 ((uint8_t)0x14)
-#define ADC_InjectedChannel_2 ((uint8_t)0x18)
-#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
-#define ADC_InjectedChannel_4 ((uint8_t)0x20)
-#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
- ((CHANNEL) == ADC_InjectedChannel_2) || \
- ((CHANNEL) == ADC_InjectedChannel_3) || \
- ((CHANNEL) == ADC_InjectedChannel_4))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_analog_watchdog_selection
- * @{
- */
-#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
-#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
-#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
-#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
-#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
-#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
-#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
-#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_None))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_interrupts_definition
- * @{
- */
-#define ADC_IT_EOC ((uint16_t)0x0205)
-#define ADC_IT_AWD ((uint16_t)0x0106)
-#define ADC_IT_JEOC ((uint16_t)0x0407)
-#define ADC_IT_OVR ((uint16_t)0x201A)
-#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
- ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_flags_definition
- * @{
- */
-#define ADC_FLAG_AWD ((uint8_t)0x01)
-#define ADC_FLAG_EOC ((uint8_t)0x02)
-#define ADC_FLAG_JEOC ((uint8_t)0x04)
-#define ADC_FLAG_JSTRT ((uint8_t)0x08)
-#define ADC_FLAG_STRT ((uint8_t)0x10)
-#define ADC_FLAG_OVR ((uint8_t)0x20)
-
-#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))
-#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
- ((FLAG) == ADC_FLAG_EOC) || \
- ((FLAG) == ADC_FLAG_JEOC) || \
- ((FLAG)== ADC_FLAG_JSTRT) || \
- ((FLAG) == ADC_FLAG_STRT) || \
- ((FLAG)== ADC_FLAG_OVR))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_thresholds
- * @{
- */
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
-/**
- * @}
- */
-
-
-/** @defgroup ADC_injected_offset
- * @{
- */
-#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
-/**
- * @}
- */
-
-
-/** @defgroup ADC_injected_length
- * @{
- */
-#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_injected_rank
- * @{
- */
-#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_regular_length
- * @{
- */
-#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_regular_rank
- * @{
- */
-#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_regular_discontinuous_mode_number
- * @{
- */
-#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the ADC configuration to the default reset state *****/
-void ADC_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
-void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
-void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-
-/* Analog Watchdog configuration functions ************************************/
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
-
-/* Temperature Sensor, Vrefint and VBAT management functions ******************/
-void ADC_TempSensorVrefintCmd(FunctionalState NewState);
-void ADC_VBATCmd(FunctionalState NewState);
-
-/* Regular Channels Configuration functions ***********************************/
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
-void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
-void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
-uint32_t ADC_GetMultiModeConversionValue(void);
-
-/* Regular Channels DMA Configuration functions *******************************/
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);
-
-/* Injected channels Configuration functions **********************************/
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
-void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
-void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
-
-/* Interrupts and flags management functions **********************************/
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_ADC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_can.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the CAN firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_CAN_H
-#define __STM32F4xx_CAN_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CAN
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
- ((PERIPH) == CAN2))
-
-/**
- * @brief CAN init structure definition
- */
-typedef struct
-{
- uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
- It ranges from 1 to 1024. */
-
- uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
- This parameter can be a value of @ref CAN_operating_mode */
-
- uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
- the CAN hardware is allowed to lengthen or
- shorten a bit to perform resynchronization.
- This parameter can be a value of @ref CAN_synchronisation_jump_width */
-
- uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
- Segment 1. This parameter can be a value of
- @ref CAN_time_quantum_in_bit_segment_1 */
-
- uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-
- FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
- This parameter can be set either to ENABLE or DISABLE. */
-} CAN_InitTypeDef;
-
-/**
- * @brief CAN filter init structure definition
- */
-typedef struct
-{
- uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
- configuration, first one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
- configuration, second one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
- according to the mode (MSBs for a 32-bit configuration,
- first one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
- according to the mode (LSBs for a 32-bit configuration,
- second one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
- This parameter can be a value of @ref CAN_filter_FIFO */
-
- uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
-
- uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
- This parameter can be a value of @ref CAN_filter_mode */
-
- uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
- This parameter can be a value of @ref CAN_filter_scale */
-
- FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
- This parameter can be set either to ENABLE or DISABLE. */
-} CAN_FilterInitTypeDef;
-
-/**
- * @brief CAN Tx message structure definition
- */
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter can be a value between 0 to 0x7FF. */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter can be a value between 0 to 0x1FFFFFFF. */
-
- uint8_t IDE; /*!< Specifies the type of identifier for the message that
- will be transmitted. This parameter can be a value
- of @ref CAN_identifier_type */
-
- uint8_t RTR; /*!< Specifies the type of frame for the message that will
- be transmitted. This parameter can be a value of
- @ref CAN_remote_transmission_request */
-
- uint8_t DLC; /*!< Specifies the length of the frame that will be
- transmitted. This parameter can be a value between
- 0 to 8 */
-
- uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
- to 0xFF. */
-} CanTxMsg;
-
-/**
- * @brief CAN Rx message structure definition
- */
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter can be a value between 0 to 0x7FF. */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter can be a value between 0 to 0x1FFFFFFF. */
-
- uint8_t IDE; /*!< Specifies the type of identifier for the message that
- will be received. This parameter can be a value of
- @ref CAN_identifier_type */
-
- uint8_t RTR; /*!< Specifies the type of frame for the received message.
- This parameter can be a value of
- @ref CAN_remote_transmission_request */
-
- uint8_t DLC; /*!< Specifies the length of the frame that will be received.
- This parameter can be a value between 0 to 8 */
-
- uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
- 0xFF. */
-
- uint8_t FMI; /*!< Specifies the index of the filter the message stored in
- the mailbox passes through. This parameter can be a
- value between 0 to 0xFF */
-} CanRxMsg;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CAN_Exported_Constants
- * @{
- */
-
-/** @defgroup CAN_InitStatus
- * @{
- */
-
-#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
-#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
-
-
-/* Legacy defines */
-#define CANINITFAILED CAN_InitStatus_Failed
-#define CANINITOK CAN_InitStatus_Success
-/**
- * @}
- */
-
-/** @defgroup CAN_operating_mode
- * @{
- */
-
-#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
-#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
-#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
-#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
-
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
- ((MODE) == CAN_Mode_LoopBack)|| \
- ((MODE) == CAN_Mode_Silent) || \
- ((MODE) == CAN_Mode_Silent_LoopBack))
-/**
- * @}
- */
-
-
- /**
- * @defgroup CAN_operating_mode
- * @{
- */
-#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
-#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
-#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
-
-
-#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
- ((MODE) == CAN_OperatingMode_Normal)|| \
- ((MODE) == CAN_OperatingMode_Sleep))
-/**
- * @}
- */
-
-/**
- * @defgroup CAN_operating_mode_status
- * @{
- */
-
-#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
-#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
-/**
- * @}
- */
-
-/** @defgroup CAN_synchronisation_jump_width
- * @{
- */
-#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
-#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
-#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
-#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
-
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
- ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_1
- * @{
- */
-#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
-#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
-#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
-#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
-#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
-#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
-#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
-#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
-#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
-#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
-#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
-#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
-#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
-#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
-#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
-#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
-
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_2
- * @{
- */
-#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
-#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
-#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
-#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
-#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
-#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
-#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
-#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
-
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
-/**
- * @}
- */
-
-/** @defgroup CAN_clock_prescaler
- * @{
- */
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_number
- * @{
- */
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_mode
- * @{
- */
-#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
-#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
-
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
- ((MODE) == CAN_FilterMode_IdList))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_scale
- * @{
- */
-#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
-#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
-
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
- ((SCALE) == CAN_FilterScale_32bit))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_FIFO
- * @{
- */
-#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
- ((FIFO) == CAN_FilterFIFO1))
-
-/* Legacy defines */
-#define CAN_FilterFIFO0 CAN_Filter_FIFO0
-#define CAN_FilterFIFO1 CAN_Filter_FIFO1
-/**
- * @}
- */
-
-/** @defgroup CAN_Start_bank_filter_for_slave_CAN
- * @{
- */
-#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
-/**
- * @}
- */
-
-/** @defgroup CAN_Tx
- * @{
- */
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
-/**
- * @}
- */
-
-/** @defgroup CAN_identifier_type
- * @{
- */
-#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
-#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
- ((IDTYPE) == CAN_Id_Extended))
-
-/* Legacy defines */
-#define CAN_ID_STD CAN_Id_Standard
-#define CAN_ID_EXT CAN_Id_Extended
-/**
- * @}
- */
-
-/** @defgroup CAN_remote_transmission_request
- * @{
- */
-#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
-#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
-
-/* Legacy defines */
-#define CAN_RTR_DATA CAN_RTR_Data
-#define CAN_RTR_REMOTE CAN_RTR_Remote
-/**
- * @}
- */
-
-/** @defgroup CAN_transmit_constants
- * @{
- */
-#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
-#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
-#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
-#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide
- an empty mailbox */
-/* Legacy defines */
-#define CANTXFAILED CAN_TxStatus_Failed
-#define CANTXOK CAN_TxStatus_Ok
-#define CANTXPENDING CAN_TxStatus_Pending
-#define CAN_NO_MB CAN_TxStatus_NoMailBox
-/**
- * @}
- */
-
-/** @defgroup CAN_receive_FIFO_number_constants
- * @{
- */
-#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
-
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
-/**
- * @}
- */
-
-/** @defgroup CAN_sleep_constants
- * @{
- */
-#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
-#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
-
-/* Legacy defines */
-#define CANSLEEPFAILED CAN_Sleep_Failed
-#define CANSLEEPOK CAN_Sleep_Ok
-/**
- * @}
- */
-
-/** @defgroup CAN_wake_up_constants
- * @{
- */
-#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
-#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
-
-/* Legacy defines */
-#define CANWAKEUPFAILED CAN_WakeUp_Failed
-#define CANWAKEUPOK CAN_WakeUp_Ok
-/**
- * @}
- */
-
-/**
- * @defgroup CAN_Error_Code_constants
- * @{
- */
-#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
-#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
-#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
-#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
-#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
-#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
-#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
-#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
-/**
- * @}
- */
-
-/** @defgroup CAN_flags
- * @{
- */
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
- and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with
- CAN_GetFlagStatus() function. */
-
-/* Transmit Flags */
-#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
-#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
-#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
-
-/* Receive Flags */
-#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
-#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
-#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
-#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
-#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
-#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
-
-/* Operating Mode Flags */
-#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
-#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
- In this case the SLAK bit can be polled.*/
-
-/* Error Flags */
-#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
-#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
-#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
-#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
-
-#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
- ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
- ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
- ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
- ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
- ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
- ((FLAG) == CAN_FLAG_SLAK ))
-
-#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
- ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
- ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
- ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
-/**
- * @}
- */
-
-
-/** @defgroup CAN_interrupts
- * @{
- */
-#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
-
-/* Receive Interrupts */
-#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
-#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
-#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
-#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
-#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
-#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
-
-/* Operating Mode Interrupts */
-#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
-#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
-
-/* Error Interrupts */
-#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
-#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
-#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
-#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
-#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
-
-/* Flags named as Interrupts : kept only for FW compatibility */
-#define CAN_IT_RQCP0 CAN_IT_TME
-#define CAN_IT_RQCP1 CAN_IT_TME
-#define CAN_IT_RQCP2 CAN_IT_TME
-
-
-#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
- ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
- ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-
-#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
- ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the CAN configuration to the default reset state *****/
-void CAN_DeInit(CAN_TypeDef* CANx);
-
-/* Initialization and Configuration functions *********************************/
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
-void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
-
-/* CAN Frames Transmission functions ******************************************/
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
-
-/* CAN Frames Reception functions *********************************************/
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
-
-/* Operation modes functions **************************************************/
-uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
-uint8_t CAN_Sleep(CAN_TypeDef* CANx);
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
-
-/* CAN Bus Error management functions *****************************************/
-uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
-uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
-uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
-
-/* Interrupts and flags management functions **********************************/
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_CAN_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_crc.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the CRC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_CRC_H
-#define __STM32F4xx_CRC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CRC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRC_Exported_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-void CRC_ResetDR(void);
-uint32_t CRC_CalcCRC(uint32_t Data);
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t CRC_GetCRC(void);
-void CRC_SetIDRegister(uint8_t IDValue);
-uint8_t CRC_GetIDRegister(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_CRC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_cryp.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the Cryptographic
- * processor(CRYP) firmware library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_CRYP_H
-#define __STM32F4xx_CRYP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CRYP
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief CRYP Init structure definition
- */
-typedef struct
-{
- uint16_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a
- value of @ref CRYP_Algorithm_Direction */
- uint16_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB,
- AES-CBC, AES-CTR, AES-Key. This parameter can be
- a value of @ref CRYP_Algorithm_Mode */
- uint16_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit-string.
- This parameter can be a value of @ref CRYP_Data_Type */
- uint16_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit
- key length. This parameter can be a value of
- @ref CRYP_Key_Size_for_AES_only */
-}CRYP_InitTypeDef;
-
-/**
- * @brief CRYP Key(s) structure definition
- */
-typedef struct
-{
- uint32_t CRYP_Key0Left; /*!< Key 0 Left */
- uint32_t CRYP_Key0Right; /*!< Key 0 Right */
- uint32_t CRYP_Key1Left; /*!< Key 1 left */
- uint32_t CRYP_Key1Right; /*!< Key 1 Right */
- uint32_t CRYP_Key2Left; /*!< Key 2 left */
- uint32_t CRYP_Key2Right; /*!< Key 2 Right */
- uint32_t CRYP_Key3Left; /*!< Key 3 left */
- uint32_t CRYP_Key3Right; /*!< Key 3 Right */
-}CRYP_KeyInitTypeDef;
-/**
- * @brief CRYP Initialization Vectors (IV) structure definition
- */
-typedef struct
-{
- uint32_t CRYP_IV0Left; /*!< Init Vector 0 Left */
- uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */
- uint32_t CRYP_IV1Left; /*!< Init Vector 1 left */
- uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */
-}CRYP_IVInitTypeDef;
-
-/**
- * @brief CRYP context swapping structure definition
- */
-typedef struct
-{
- /*!< Configuration */
- uint32_t CR_bits9to2;
- /*!< KEY */
- uint32_t CRYP_IV0LR;
- uint32_t CRYP_IV0RR;
- uint32_t CRYP_IV1LR;
- uint32_t CRYP_IV1RR;
- /*!< IV */
- uint32_t CRYP_K0LR;
- uint32_t CRYP_K0RR;
- uint32_t CRYP_K1LR;
- uint32_t CRYP_K1RR;
- uint32_t CRYP_K2LR;
- uint32_t CRYP_K2RR;
- uint32_t CRYP_K3LR;
- uint32_t CRYP_K3RR;
-}CRYP_Context;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRYP_Exported_Constants
- * @{
- */
-
-/** @defgroup CRYP_Algorithm_Direction
- * @{
- */
-#define CRYP_AlgoDir_Encrypt ((uint16_t)0x0000)
-#define CRYP_AlgoDir_Decrypt ((uint16_t)0x0004)
-#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \
- ((ALGODIR) == CRYP_AlgoDir_Decrypt))
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_Algorithm_Mode
- * @{
- */
-
-/*!< TDES Modes */
-#define CRYP_AlgoMode_TDES_ECB ((uint16_t)0x0000)
-#define CRYP_AlgoMode_TDES_CBC ((uint16_t)0x0008)
-
-/*!< DES Modes */
-#define CRYP_AlgoMode_DES_ECB ((uint16_t)0x0010)
-#define CRYP_AlgoMode_DES_CBC ((uint16_t)0x0018)
-
-/*!< AES Modes */
-#define CRYP_AlgoMode_AES_ECB ((uint16_t)0x0020)
-#define CRYP_AlgoMode_AES_CBC ((uint16_t)0x0028)
-#define CRYP_AlgoMode_AES_CTR ((uint16_t)0x0030)
-#define CRYP_AlgoMode_AES_Key ((uint16_t)0x0038)
-
-#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \
- ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \
- ((ALGOMODE) == CRYP_AlgoMode_DES_ECB)|| \
- ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \
- ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \
- ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \
- ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \
- ((ALGOMODE) == CRYP_AlgoMode_AES_Key))
-/**
- * @}
- */
-
-/** @defgroup CRYP_Data_Type
- * @{
- */
-#define CRYP_DataType_32b ((uint16_t)0x0000)
-#define CRYP_DataType_16b ((uint16_t)0x0040)
-#define CRYP_DataType_8b ((uint16_t)0x0080)
-#define CRYP_DataType_1b ((uint16_t)0x00C0)
-#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \
- ((DATATYPE) == CRYP_DataType_16b)|| \
- ((DATATYPE) == CRYP_DataType_8b)|| \
- ((DATATYPE) == CRYP_DataType_1b))
-/**
- * @}
- */
-
-/** @defgroup CRYP_Key_Size_for_AES_only
- * @{
- */
-#define CRYP_KeySize_128b ((uint16_t)0x0000)
-#define CRYP_KeySize_192b ((uint16_t)0x0100)
-#define CRYP_KeySize_256b ((uint16_t)0x0200)
-#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \
- ((KEYSIZE) == CRYP_KeySize_192b)|| \
- ((KEYSIZE) == CRYP_KeySize_256b))
-/**
- * @}
- */
-
-/** @defgroup CRYP_flags_definition
- * @{
- */
-#define CRYP_FLAG_BUSY ((uint8_t)0x10) /*!< The CRYP core is currently
- processing a block of data
- or a key preparation (for
- AES decryption). */
-#define CRYP_FLAG_IFEM ((uint8_t)0x01) /*!< Input Fifo Empty */
-#define CRYP_FLAG_IFNF ((uint8_t)0x02) /*!< Input Fifo is Not Full */
-#define CRYP_FLAG_INRIS ((uint8_t)0x22) /*!< Raw interrupt pending */
-#define CRYP_FLAG_OFNE ((uint8_t)0x04) /*!< Input Fifo service raw
- interrupt status */
-#define CRYP_FLAG_OFFU ((uint8_t)0x08) /*!< Output Fifo is Full */
-#define CRYP_FLAG_OUTRIS ((uint8_t)0x21) /*!< Output Fifo service raw
- interrupt status */
-
-#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM) || \
- ((FLAG) == CRYP_FLAG_IFNF) || \
- ((FLAG) == CRYP_FLAG_OFNE) || \
- ((FLAG) == CRYP_FLAG_OFFU) || \
- ((FLAG) == CRYP_FLAG_BUSY) || \
- ((FLAG) == CRYP_FLAG_OUTRIS)|| \
- ((FLAG) == CRYP_FLAG_INRIS))
-/**
- * @}
- */
-
-/** @defgroup CRYP_interrupts_definition
- * @{
- */
-#define CRYP_IT_INI ((uint8_t)0x01) /*!< IN Fifo Interrupt */
-#define CRYP_IT_OUTI ((uint8_t)0x02) /*!< OUT Fifo Interrupt */
-#define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))
-#define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI))
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_Encryption_Decryption_modes_definition
- * @{
- */
-#define MODE_ENCRYPT ((uint8_t)0x01)
-#define MODE_DECRYPT ((uint8_t)0x00)
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_DMA_transfer_requests
- * @{
- */
-#define CRYP_DMAReq_DataIN ((uint8_t)0x01)
-#define CRYP_DMAReq_DataOUT ((uint8_t)0x02)
-#define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the CRYP configuration to the default reset state ****/
-void CRYP_DeInit(void);
-
-/* CRYP Initialization and Configuration functions ****************************/
-void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct);
-void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct);
-void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
-void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
-void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
-void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
-void CRYP_Cmd(FunctionalState NewState);
-
-/* CRYP Data processing functions *********************************************/
-void CRYP_DataIn(uint32_t Data);
-uint32_t CRYP_DataOut(void);
-void CRYP_FIFOFlush(void);
-
-/* CRYP Context swapping functions ********************************************/
-ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
- CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
-void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore);
-
-/* CRYP's DMA interface function **********************************************/
-void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState);
-ITStatus CRYP_GetITStatus(uint8_t CRYP_IT);
-FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG);
-
-/* High Level AES functions **************************************************/
-ErrorStatus CRYP_AES_ECB(uint8_t Mode,
- uint8_t *Key, uint16_t Keysize,
- uint8_t *Input, uint32_t Ilength,
- uint8_t *Output);
-
-ErrorStatus CRYP_AES_CBC(uint8_t Mode,
- uint8_t InitVectors[16],
- uint8_t *Key, uint16_t Keysize,
- uint8_t *Input, uint32_t Ilength,
- uint8_t *Output);
-
-ErrorStatus CRYP_AES_CTR(uint8_t Mode,
- uint8_t InitVectors[16],
- uint8_t *Key, uint16_t Keysize,
- uint8_t *Input, uint32_t Ilength,
- uint8_t *Output);
-
-/* High Level TDES functions **************************************************/
-ErrorStatus CRYP_TDES_ECB(uint8_t Mode,
- uint8_t Key[24],
- uint8_t *Input, uint32_t Ilength,
- uint8_t *Output);
-
-ErrorStatus CRYP_TDES_CBC(uint8_t Mode,
- uint8_t Key[24],
- uint8_t InitVectors[8],
- uint8_t *Input, uint32_t Ilength,
- uint8_t *Output);
-
-/* High Level DES functions **************************************************/
-ErrorStatus CRYP_DES_ECB(uint8_t Mode,
- uint8_t Key[8],
- uint8_t *Input, uint32_t Ilength,
- uint8_t *Output);
-
-ErrorStatus CRYP_DES_CBC(uint8_t Mode,
- uint8_t Key[8],
- uint8_t InitVectors[8],
- uint8_t *Input,uint32_t Ilength,
- uint8_t *Output);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_CRYP_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_dac.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the DAC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_DAC_H
-#define __STM32F4xx_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DAC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief DAC Init structure definition
- */
-
-typedef struct
-{
- uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
- This parameter can be a value of @ref DAC_trigger_selection */
-
- uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
- are generated, or whether no wave is generated.
- This parameter can be a value of @ref DAC_wave_generation */
-
- uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
- the maximum amplitude triangle generation for the DAC channel.
- This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
-
- uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
- This parameter can be a value of @ref DAC_output_buffer */
-}DAC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants
- * @{
- */
-
-/** @defgroup DAC_trigger_selection
- * @{
- */
-
-#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
- has been loaded, and not by external trigger */
-#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
-
-#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
- ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
- ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
- ((TRIGGER) == DAC_Trigger_Software))
-
-/**
- * @}
- */
-
-/** @defgroup DAC_wave_generation
- * @{
- */
-
-#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
-#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
-#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
-#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
- ((WAVE) == DAC_WaveGeneration_Noise) || \
- ((WAVE) == DAC_WaveGeneration_Triangle))
-/**
- * @}
- */
-
-/** @defgroup DAC_lfsrunmask_triangleamplitude
- * @{
- */
-
-#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
-#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
-#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
-#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
-#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
-#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
-#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
-#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
-#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
-#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
- ((VALUE) == DAC_TriangleAmplitude_1) || \
- ((VALUE) == DAC_TriangleAmplitude_3) || \
- ((VALUE) == DAC_TriangleAmplitude_7) || \
- ((VALUE) == DAC_TriangleAmplitude_15) || \
- ((VALUE) == DAC_TriangleAmplitude_31) || \
- ((VALUE) == DAC_TriangleAmplitude_63) || \
- ((VALUE) == DAC_TriangleAmplitude_127) || \
- ((VALUE) == DAC_TriangleAmplitude_255) || \
- ((VALUE) == DAC_TriangleAmplitude_511) || \
- ((VALUE) == DAC_TriangleAmplitude_1023) || \
- ((VALUE) == DAC_TriangleAmplitude_2047) || \
- ((VALUE) == DAC_TriangleAmplitude_4095))
-/**
- * @}
- */
-
-/** @defgroup DAC_output_buffer
- * @{
- */
-
-#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
-#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
- ((STATE) == DAC_OutputBuffer_Disable))
-/**
- * @}
- */
-
-/** @defgroup DAC_Channel_selection
- * @{
- */
-
-#define DAC_Channel_1 ((uint32_t)0x00000000)
-#define DAC_Channel_2 ((uint32_t)0x00000010)
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
- ((CHANNEL) == DAC_Channel_2))
-/**
- * @}
- */
-
-/** @defgroup DAC_data_alignement
- * @{
- */
-
-#define DAC_Align_12b_R ((uint32_t)0x00000000)
-#define DAC_Align_12b_L ((uint32_t)0x00000004)
-#define DAC_Align_8b_R ((uint32_t)0x00000008)
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
- ((ALIGN) == DAC_Align_12b_L) || \
- ((ALIGN) == DAC_Align_8b_R))
-/**
- * @}
- */
-
-/** @defgroup DAC_wave_generation
- * @{
- */
-
-#define DAC_Wave_Noise ((uint32_t)0x00000040)
-#define DAC_Wave_Triangle ((uint32_t)0x00000080)
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
- ((WAVE) == DAC_Wave_Triangle))
-/**
- * @}
- */
-
-/** @defgroup DAC_data
- * @{
- */
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
-/**
- * @}
- */
-
-/** @defgroup DAC_interrupts_definition
- * @{
- */
-#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
-#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
-
-/**
- * @}
- */
-
-/** @defgroup DAC_flags_definition
- * @{
- */
-
-#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
-#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the DAC configuration to the default reset state *****/
-void DAC_DeInit(void);
-
-/* DAC channels configuration: trigger, output buffer, data format functions */
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
-
-/* DMA management functions ***************************************************/
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_DAC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_dbgmcu.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the DBGMCU firmware library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_DBGMCU_H
-#define __STM32F4xx_DBGMCU_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DBGMCU
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DBGMCU_Exported_Constants
- * @{
- */
-#define DBGMCU_SLEEP ((uint32_t)0x00000001)
-#define DBGMCU_STOP ((uint32_t)0x00000002)
-#define DBGMCU_STANDBY ((uint32_t)0x00000004)
-#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
-
-#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
-#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
-#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
-#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008)
-#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
-#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
-#define DBGMCU_TIM12_STOP ((uint32_t)0x00000040)
-#define DBGMCU_TIM13_STOP ((uint32_t)0x00000080)
-#define DBGMCU_TIM14_STOP ((uint32_t)0x00000100)
-#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)
-#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
-#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
-#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
-#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
-#define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
-#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000)
-#define DBGMCU_CAN2_STOP ((uint32_t)0x04000000)
-#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00))
-
-#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001)
-#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002)
-#define DBGMCU_TIM9_STOP ((uint32_t)0x00010000)
-#define DBGMCU_TIM10_STOP ((uint32_t)0x00020000)
-#define DBGMCU_TIM11_STOP ((uint32_t)0x00040000)
-#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-uint32_t DBGMCU_GetREVID(void);
-uint32_t DBGMCU_GetDEVID(void);
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_DBGMCU_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_dcmi.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the DCMI firmware library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_DCMI_H
-#define __STM32F4xx_DCMI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DCMI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/**
- * @brief DCMI Init structure definition
- */
-typedef struct
-{
- uint16_t DCMI_CaptureMode; /*!< Specifies the Capture Mode: Continuous or Snapshot.
- This parameter can be a value of @ref DCMI_Capture_Mode */
-
- uint16_t DCMI_SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
- This parameter can be a value of @ref DCMI_Synchronization_Mode */
-
- uint16_t DCMI_PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
- This parameter can be a value of @ref DCMI_PIXCK_Polarity */
-
- uint16_t DCMI_VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
- This parameter can be a value of @ref DCMI_VSYNC_Polarity */
-
- uint16_t DCMI_HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
- This parameter can be a value of @ref DCMI_HSYNC_Polarity */
-
- uint16_t DCMI_CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
- This parameter can be a value of @ref DCMI_Capture_Rate */
-
- uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
- This parameter can be a value of @ref DCMI_Extended_Data_Mode */
-} DCMI_InitTypeDef;
-
-/**
- * @brief DCMI CROP Init structure definition
- */
-typedef struct
-{
- uint16_t DCMI_VerticalStartLine; /*!< Specifies the Vertical start line count from which the image capture
- will start. This parameter can be a value between 0x00 and 0x1FFF */
-
- uint16_t DCMI_HorizontalOffsetCount; /*!< Specifies the number of pixel clocks to count before starting a capture.
- This parameter can be a value between 0x00 and 0x3FFF */
-
- uint16_t DCMI_VerticalLineCount; /*!< Specifies the number of lines to be captured from the starting point.
- This parameter can be a value between 0x00 and 0x3FFF */
-
- uint16_t DCMI_CaptureCount; /*!< Specifies the number of pixel clocks to be captured from the starting
- point on the same line.
- This parameter can be a value between 0x00 and 0x3FFF */
-} DCMI_CROPInitTypeDef;
-
-/**
- * @brief DCMI Embedded Synchronisation CODE Init structure definition
- */
-typedef struct
-{
- uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
- uint8_t DCMI_LineStartCode; /*!< Specifies the code of the line start delimiter. */
- uint8_t DCMI_LineEndCode; /*!< Specifies the code of the line end delimiter. */
- uint8_t DCMI_FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
-} DCMI_CodesInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DCMI_Exported_Constants
- * @{
- */
-
-/** @defgroup DCMI_Capture_Mode
- * @{
- */
-#define DCMI_CaptureMode_Continuous ((uint16_t)0x0000) /*!< The received data are transferred continuously
- into the destination memory through the DMA */
-#define DCMI_CaptureMode_SnapShot ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of
- frame and then transfers a single frame through the DMA */
-#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \
- ((MODE) == DCMI_CaptureMode_SnapShot))
-/**
- * @}
- */
-
-
-/** @defgroup DCMI_Synchronization_Mode
- * @{
- */
-#define DCMI_SynchroMode_Hardware ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop)
- is synchronized with the HSYNC/VSYNC signals */
-#define DCMI_SynchroMode_Embedded ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with
- synchronization codes embedded in the data flow */
-#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \
- ((MODE) == DCMI_SynchroMode_Embedded))
-/**
- * @}
- */
-
-
-/** @defgroup DCMI_PIXCK_Polarity
- * @{
- */
-#define DCMI_PCKPolarity_Falling ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */
-#define DCMI_PCKPolarity_Rising ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */
-#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \
- ((POLARITY) == DCMI_PCKPolarity_Rising))
-/**
- * @}
- */
-
-
-/** @defgroup DCMI_VSYNC_Polarity
- * @{
- */
-#define DCMI_VSPolarity_Low ((uint16_t)0x0000) /*!< Vertical synchronization active Low */
-#define DCMI_VSPolarity_High ((uint16_t)0x0080) /*!< Vertical synchronization active High */
-#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \
- ((POLARITY) == DCMI_VSPolarity_High))
-/**
- * @}
- */
-
-
-/** @defgroup DCMI_HSYNC_Polarity
- * @{
- */
-#define DCMI_HSPolarity_Low ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */
-#define DCMI_HSPolarity_High ((uint16_t)0x0040) /*!< Horizontal synchronization active High */
-#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \
- ((POLARITY) == DCMI_HSPolarity_High))
-/**
- * @}
- */
-
-
-/** @defgroup DCMI_Capture_Rate
- * @{
- */
-#define DCMI_CaptureRate_All_Frame ((uint16_t)0x0000) /*!< All frames are captured */
-#define DCMI_CaptureRate_1of2_Frame ((uint16_t)0x0100) /*!< Every alternate frame captured */
-#define DCMI_CaptureRate_1of4_Frame ((uint16_t)0x0200) /*!< One frame in 4 frames captured */
-#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \
- ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\
- ((RATE) == DCMI_CaptureRate_1of4_Frame))
-/**
- * @}
- */
-
-
-/** @defgroup DCMI_Extended_Data_Mode
- * @{
- */
-#define DCMI_ExtendedDataMode_8b ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */
-#define DCMI_ExtendedDataMode_10b ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */
-#define DCMI_ExtendedDataMode_12b ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */
-#define DCMI_ExtendedDataMode_14b ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */
-#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \
- ((DATA) == DCMI_ExtendedDataMode_10b) ||\
- ((DATA) == DCMI_ExtendedDataMode_12b) ||\
- ((DATA) == DCMI_ExtendedDataMode_14b))
-/**
- * @}
- */
-
-
-/** @defgroup DCMI_interrupt_sources
- * @{
- */
-#define DCMI_IT_FRAME ((uint16_t)0x0001)
-#define DCMI_IT_OVF ((uint16_t)0x0002)
-#define DCMI_IT_ERR ((uint16_t)0x0004)
-#define DCMI_IT_VSYNC ((uint16_t)0x0008)
-#define DCMI_IT_LINE ((uint16_t)0x0010)
-#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))
-#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \
- ((IT) == DCMI_IT_OVF) || \
- ((IT) == DCMI_IT_ERR) || \
- ((IT) == DCMI_IT_VSYNC) || \
- ((IT) == DCMI_IT_LINE))
-/**
- * @}
- */
-
-
-/** @defgroup DCMI_Flags
- * @{
- */
-/**
- * @brief DCMI SR register
- */
-#define DCMI_FLAG_HSYNC ((uint16_t)0x2001)
-#define DCMI_FLAG_VSYNC ((uint16_t)0x2002)
-#define DCMI_FLAG_FNE ((uint16_t)0x2004)
-/**
- * @brief DCMI RISR register
- */
-#define DCMI_FLAG_FRAMERI ((uint16_t)0x0001)
-#define DCMI_FLAG_OVFRI ((uint16_t)0x0002)
-#define DCMI_FLAG_ERRRI ((uint16_t)0x0004)
-#define DCMI_FLAG_VSYNCRI ((uint16_t)0x0008)
-#define DCMI_FLAG_LINERI ((uint16_t)0x0010)
-/**
- * @brief DCMI MISR register
- */
-#define DCMI_FLAG_FRAMEMI ((uint16_t)0x1001)
-#define DCMI_FLAG_OVFMI ((uint16_t)0x1002)
-#define DCMI_FLAG_ERRMI ((uint16_t)0x1004)
-#define DCMI_FLAG_VSYNCMI ((uint16_t)0x1008)
-#define DCMI_FLAG_LINEMI ((uint16_t)0x1010)
-#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \
- ((FLAG) == DCMI_FLAG_VSYNC) || \
- ((FLAG) == DCMI_FLAG_FNE) || \
- ((FLAG) == DCMI_FLAG_FRAMERI) || \
- ((FLAG) == DCMI_FLAG_OVFRI) || \
- ((FLAG) == DCMI_FLAG_ERRRI) || \
- ((FLAG) == DCMI_FLAG_VSYNCRI) || \
- ((FLAG) == DCMI_FLAG_LINERI) || \
- ((FLAG) == DCMI_FLAG_FRAMEMI) || \
- ((FLAG) == DCMI_FLAG_OVFMI) || \
- ((FLAG) == DCMI_FLAG_ERRMI) || \
- ((FLAG) == DCMI_FLAG_VSYNCMI) || \
- ((FLAG) == DCMI_FLAG_LINEMI))
-
-#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the DCMI configuration to the default reset state ****/
-void DCMI_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct);
-void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct);
-void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct);
-void DCMI_CROPCmd(FunctionalState NewState);
-void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct);
-void DCMI_JPEGCmd(FunctionalState NewState);
-
-/* Image capture functions ****************************************************/
-void DCMI_Cmd(FunctionalState NewState);
-void DCMI_CaptureCmd(FunctionalState NewState);
-uint32_t DCMI_ReadData(void);
-
-/* Interrupts and flags management functions **********************************/
-void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState);
-FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG);
-void DCMI_ClearFlag(uint16_t DCMI_FLAG);
-ITStatus DCMI_GetITStatus(uint16_t DCMI_IT);
-void DCMI_ClearITPendingBit(uint16_t DCMI_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_DCMI_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_dma.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the DMA firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_DMA_H
-#define __STM32F4xx_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DMA
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief DMA Init structure definition
- */
-
-typedef struct
-{
- uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream.
- This parameter can be a value of @ref DMA_channel */
-
- uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */
-
- uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx.
- This memory is the default memory used when double buffer mode is
- not enabled. */
-
- uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral,
- from memory to memory or from peripheral to memory.
- This parameter can be a value of @ref DMA_data_transfer_direction */
-
- uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream.
- The data unit is equal to the configuration set in DMA_PeripheralDataSize
- or DMA_MemoryDataSize members depending in the transfer direction. */
-
- uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
- This parameter can be a value of @ref DMA_peripheral_incremented_mode */
-
- uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not.
- This parameter can be a value of @ref DMA_memory_incremented_mode */
-
- uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
- This parameter can be a value of @ref DMA_peripheral_data_size */
-
- uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
- This parameter can be a value of @ref DMA_memory_data_size */
-
- uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx.
- This parameter can be a value of @ref DMA_circular_normal_mode
- @note The circular buffer mode cannot be used if the memory-to-memory
- data transfer is configured on the selected Stream */
-
- uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx.
- This parameter can be a value of @ref DMA_priority_level */
-
- uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.
- This parameter can be a value of @ref DMA_fifo_direct_mode
- @note The Direct mode (FIFO mode disabled) cannot be used if the
- memory-to-memory data transfer is configured on the selected Stream */
-
- uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level.
- This parameter can be a value of @ref DMA_fifo_threshold_level */
-
- uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
- It specifies the amount of data to be transferred in a single non interruptable
- transaction. This parameter can be a value of @ref DMA_memory_burst
- @note The burst mode is possible only if the address Increment mode is enabled. */
-
- uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
- It specifies the amount of data to be transferred in a single non interruptable
- transaction. This parameter can be a value of @ref DMA_peripheral_burst
- @note The burst mode is possible only if the address Increment mode is enabled. */
-}DMA_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants
- * @{
- */
-
-#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \
- ((PERIPH) == DMA1_Stream1) || \
- ((PERIPH) == DMA1_Stream2) || \
- ((PERIPH) == DMA1_Stream3) || \
- ((PERIPH) == DMA1_Stream4) || \
- ((PERIPH) == DMA1_Stream5) || \
- ((PERIPH) == DMA1_Stream6) || \
- ((PERIPH) == DMA1_Stream7) || \
- ((PERIPH) == DMA2_Stream0) || \
- ((PERIPH) == DMA2_Stream1) || \
- ((PERIPH) == DMA2_Stream2) || \
- ((PERIPH) == DMA2_Stream3) || \
- ((PERIPH) == DMA2_Stream4) || \
- ((PERIPH) == DMA2_Stream5) || \
- ((PERIPH) == DMA2_Stream6) || \
- ((PERIPH) == DMA2_Stream7))
-
-#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \
- ((CONTROLLER) == DMA2))
-
-/** @defgroup DMA_channel
- * @{
- */
-#define DMA_Channel_0 ((uint32_t)0x00000000)
-#define DMA_Channel_1 ((uint32_t)0x02000000)
-#define DMA_Channel_2 ((uint32_t)0x04000000)
-#define DMA_Channel_3 ((uint32_t)0x06000000)
-#define DMA_Channel_4 ((uint32_t)0x08000000)
-#define DMA_Channel_5 ((uint32_t)0x0A000000)
-#define DMA_Channel_6 ((uint32_t)0x0C000000)
-#define DMA_Channel_7 ((uint32_t)0x0E000000)
-
-#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \
- ((CHANNEL) == DMA_Channel_1) || \
- ((CHANNEL) == DMA_Channel_2) || \
- ((CHANNEL) == DMA_Channel_3) || \
- ((CHANNEL) == DMA_Channel_4) || \
- ((CHANNEL) == DMA_Channel_5) || \
- ((CHANNEL) == DMA_Channel_6) || \
- ((CHANNEL) == DMA_Channel_7))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_data_transfer_direction
- * @{
- */
-#define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000)
-#define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040)
-#define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080)
-
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
- ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \
- ((DIRECTION) == DMA_DIR_MemoryToMemory))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_data_buffer_size
- * @{
- */
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_peripheral_incremented_mode
- * @{
- */
-#define DMA_PeripheralInc_Enable ((uint32_t)0x00000200)
-#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
- ((STATE) == DMA_PeripheralInc_Disable))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_memory_incremented_mode
- * @{
- */
-#define DMA_MemoryInc_Enable ((uint32_t)0x00000400)
-#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
- ((STATE) == DMA_MemoryInc_Disable))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_peripheral_data_size
- * @{
- */
-#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
-#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800)
-#define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000)
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
- ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
- ((SIZE) == DMA_PeripheralDataSize_Word))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_memory_data_size
- * @{
- */
-#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
-#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000)
-#define DMA_MemoryDataSize_Word ((uint32_t)0x00004000)
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
- ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
- ((SIZE) == DMA_MemoryDataSize_Word ))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_circular_normal_mode
- * @{
- */
-#define DMA_Mode_Normal ((uint32_t)0x00000000)
-#define DMA_Mode_Circular ((uint32_t)0x00000100)
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \
- ((MODE) == DMA_Mode_Circular))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_priority_level
- * @{
- */
-#define DMA_Priority_Low ((uint32_t)0x00000000)
-#define DMA_Priority_Medium ((uint32_t)0x00010000)
-#define DMA_Priority_High ((uint32_t)0x00020000)
-#define DMA_Priority_VeryHigh ((uint32_t)0x00030000)
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \
- ((PRIORITY) == DMA_Priority_Medium) || \
- ((PRIORITY) == DMA_Priority_High) || \
- ((PRIORITY) == DMA_Priority_VeryHigh))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_fifo_direct_mode
- * @{
- */
-#define DMA_FIFOMode_Disable ((uint32_t)0x00000000)
-#define DMA_FIFOMode_Enable ((uint32_t)0x00000004)
-
-#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \
- ((STATE) == DMA_FIFOMode_Enable))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_fifo_threshold_level
- * @{
- */
-#define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000)
-#define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001)
-#define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002)
-#define DMA_FIFOThreshold_Full ((uint32_t)0x00000003)
-
-#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
- ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \
- ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \
- ((THRESHOLD) == DMA_FIFOThreshold_Full))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_memory_burst
- * @{
- */
-#define DMA_MemoryBurst_Single ((uint32_t)0x00000000)
-#define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000)
-#define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000)
-#define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000)
-
-#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
- ((BURST) == DMA_MemoryBurst_INC4) || \
- ((BURST) == DMA_MemoryBurst_INC8) || \
- ((BURST) == DMA_MemoryBurst_INC16))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_peripheral_burst
- * @{
- */
-#define DMA_PeripheralBurst_Single ((uint32_t)0x00000000)
-#define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000)
-#define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000)
-#define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000)
-
-#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
- ((BURST) == DMA_PeripheralBurst_INC4) || \
- ((BURST) == DMA_PeripheralBurst_INC8) || \
- ((BURST) == DMA_PeripheralBurst_INC16))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_fifo_status_level
- * @{
- */
-#define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3)
-#define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3)
-#define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3)
-#define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3)
-#define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3)
-#define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3)
-
-#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
- ((STATUS) == DMA_FIFOStatus_HalfFull) || \
- ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \
- ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \
- ((STATUS) == DMA_FIFOStatus_Full) || \
- ((STATUS) == DMA_FIFOStatus_Empty))
-/**
- * @}
- */
-
-/** @defgroup DMA_flags_definition
- * @{
- */
-#define DMA_FLAG_FEIF0 ((uint32_t)0x10800001)
-#define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004)
-#define DMA_FLAG_TEIF0 ((uint32_t)0x10000008)
-#define DMA_FLAG_HTIF0 ((uint32_t)0x10000010)
-#define DMA_FLAG_TCIF0 ((uint32_t)0x10000020)
-#define DMA_FLAG_FEIF1 ((uint32_t)0x10000040)
-#define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100)
-#define DMA_FLAG_TEIF1 ((uint32_t)0x10000200)
-#define DMA_FLAG_HTIF1 ((uint32_t)0x10000400)
-#define DMA_FLAG_TCIF1 ((uint32_t)0x10000800)
-#define DMA_FLAG_FEIF2 ((uint32_t)0x10010000)
-#define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000)
-#define DMA_FLAG_TEIF2 ((uint32_t)0x10080000)
-#define DMA_FLAG_HTIF2 ((uint32_t)0x10100000)
-#define DMA_FLAG_TCIF2 ((uint32_t)0x10200000)
-#define DMA_FLAG_FEIF3 ((uint32_t)0x10400000)
-#define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000)
-#define DMA_FLAG_TEIF3 ((uint32_t)0x12000000)
-#define DMA_FLAG_HTIF3 ((uint32_t)0x14000000)
-#define DMA_FLAG_TCIF3 ((uint32_t)0x18000000)
-#define DMA_FLAG_FEIF4 ((uint32_t)0x20000001)
-#define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004)
-#define DMA_FLAG_TEIF4 ((uint32_t)0x20000008)
-#define DMA_FLAG_HTIF4 ((uint32_t)0x20000010)
-#define DMA_FLAG_TCIF4 ((uint32_t)0x20000020)
-#define DMA_FLAG_FEIF5 ((uint32_t)0x20000040)
-#define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100)
-#define DMA_FLAG_TEIF5 ((uint32_t)0x20000200)
-#define DMA_FLAG_HTIF5 ((uint32_t)0x20000400)
-#define DMA_FLAG_TCIF5 ((uint32_t)0x20000800)
-#define DMA_FLAG_FEIF6 ((uint32_t)0x20010000)
-#define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000)
-#define DMA_FLAG_TEIF6 ((uint32_t)0x20080000)
-#define DMA_FLAG_HTIF6 ((uint32_t)0x20100000)
-#define DMA_FLAG_TCIF6 ((uint32_t)0x20200000)
-#define DMA_FLAG_FEIF7 ((uint32_t)0x20400000)
-#define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000)
-#define DMA_FLAG_TEIF7 ((uint32_t)0x22000000)
-#define DMA_FLAG_HTIF7 ((uint32_t)0x24000000)
-#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000)
-
-#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
- (((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00))
-
-#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \
- ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \
- ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \
- ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \
- ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \
- ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \
- ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \
- ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \
- ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \
- ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \
- ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \
- ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \
- ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \
- ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \
- ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \
- ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \
- ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \
- ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \
- ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \
- ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_interrupt_enable_definitions
- * @{
- */
-#define DMA_IT_TC ((uint32_t)0x00000010)
-#define DMA_IT_HT ((uint32_t)0x00000008)
-#define DMA_IT_TE ((uint32_t)0x00000004)
-#define DMA_IT_DME ((uint32_t)0x00000002)
-#define DMA_IT_FE ((uint32_t)0x00000080)
-
-#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_interrupts_definitions
- * @{
- */
-#define DMA_IT_FEIF0 ((uint32_t)0x90000001)
-#define DMA_IT_DMEIF0 ((uint32_t)0x10001004)
-#define DMA_IT_TEIF0 ((uint32_t)0x10002008)
-#define DMA_IT_HTIF0 ((uint32_t)0x10004010)
-#define DMA_IT_TCIF0 ((uint32_t)0x10008020)
-#define DMA_IT_FEIF1 ((uint32_t)0x90000040)
-#define DMA_IT_DMEIF1 ((uint32_t)0x10001100)
-#define DMA_IT_TEIF1 ((uint32_t)0x10002200)
-#define DMA_IT_HTIF1 ((uint32_t)0x10004400)
-#define DMA_IT_TCIF1 ((uint32_t)0x10008800)
-#define DMA_IT_FEIF2 ((uint32_t)0x90010000)
-#define DMA_IT_DMEIF2 ((uint32_t)0x10041000)
-#define DMA_IT_TEIF2 ((uint32_t)0x10082000)
-#define DMA_IT_HTIF2 ((uint32_t)0x10104000)
-#define DMA_IT_TCIF2 ((uint32_t)0x10208000)
-#define DMA_IT_FEIF3 ((uint32_t)0x90400000)
-#define DMA_IT_DMEIF3 ((uint32_t)0x11001000)
-#define DMA_IT_TEIF3 ((uint32_t)0x12002000)
-#define DMA_IT_HTIF3 ((uint32_t)0x14004000)
-#define DMA_IT_TCIF3 ((uint32_t)0x18008000)
-#define DMA_IT_FEIF4 ((uint32_t)0xA0000001)
-#define DMA_IT_DMEIF4 ((uint32_t)0x20001004)
-#define DMA_IT_TEIF4 ((uint32_t)0x20002008)
-#define DMA_IT_HTIF4 ((uint32_t)0x20004010)
-#define DMA_IT_TCIF4 ((uint32_t)0x20008020)
-#define DMA_IT_FEIF5 ((uint32_t)0xA0000040)
-#define DMA_IT_DMEIF5 ((uint32_t)0x20001100)
-#define DMA_IT_TEIF5 ((uint32_t)0x20002200)
-#define DMA_IT_HTIF5 ((uint32_t)0x20004400)
-#define DMA_IT_TCIF5 ((uint32_t)0x20008800)
-#define DMA_IT_FEIF6 ((uint32_t)0xA0010000)
-#define DMA_IT_DMEIF6 ((uint32_t)0x20041000)
-#define DMA_IT_TEIF6 ((uint32_t)0x20082000)
-#define DMA_IT_HTIF6 ((uint32_t)0x20104000)
-#define DMA_IT_TCIF6 ((uint32_t)0x20208000)
-#define DMA_IT_FEIF7 ((uint32_t)0xA0400000)
-#define DMA_IT_DMEIF7 ((uint32_t)0x21001000)
-#define DMA_IT_TEIF7 ((uint32_t)0x22002000)
-#define DMA_IT_HTIF7 ((uint32_t)0x24004000)
-#define DMA_IT_TCIF7 ((uint32_t)0x28008000)
-
-#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \
- (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \
- (((IT) & 0x40820082) == 0x00))
-
-#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \
- ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \
- ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \
- ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \
- ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \
- ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \
- ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \
- ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \
- ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \
- ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \
- ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \
- ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \
- ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \
- ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \
- ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \
- ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \
- ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \
- ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \
- ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \
- ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_peripheral_increment_offset
- * @{
- */
-#define DMA_PINCOS_Psize ((uint32_t)0x00000000)
-#define DMA_PINCOS_WordAligned ((uint32_t)0x00008000)
-
-#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
- ((SIZE) == DMA_PINCOS_WordAligned))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_flow_controller_definitions
- * @{
- */
-#define DMA_FlowCtrl_Memory ((uint32_t)0x00000000)
-#define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020)
-
-#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
- ((CTRL) == DMA_FlowCtrl_Peripheral))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_memory_targets_definitions
- * @{
- */
-#define DMA_Memory_0 ((uint32_t)0x00000000)
-#define DMA_Memory_1 ((uint32_t)0x00080000)
-
-#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the DMA configuration to the default reset state *****/
-void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);
-
-/* Initialization and Configuration functions *********************************/
-void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
-void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
-
-/* Optional Configuration functions *******************************************/
-void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);
-void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);
-
-/* Data Counter functions *****************************************************/
-void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
-uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
-
-/* Double Buffer mode functions ***********************************************/
-void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
- uint32_t DMA_CurrentMemory);
-void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
-void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
- uint32_t DMA_MemoryTarget);
-uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
-
-/* Interrupts and flags management functions **********************************/
-FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
-uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
-FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
-void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
-void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
-ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
-void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_DMA_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_exti.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the EXTI firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_EXTI_H
-#define __STM32F4xx_EXTI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup EXTI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief EXTI mode enumeration
- */
-
-typedef enum
-{
- EXTI_Mode_Interrupt = 0x00,
- EXTI_Mode_Event = 0x04
-}EXTIMode_TypeDef;
-
-#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
-
-/**
- * @brief EXTI Trigger enumeration
- */
-
-typedef enum
-{
- EXTI_Trigger_Rising = 0x08,
- EXTI_Trigger_Falling = 0x0C,
- EXTI_Trigger_Rising_Falling = 0x10
-}EXTITrigger_TypeDef;
-
-#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
- ((TRIGGER) == EXTI_Trigger_Falling) || \
- ((TRIGGER) == EXTI_Trigger_Rising_Falling))
-/**
- * @brief EXTI Init Structure definition
- */
-
-typedef struct
-{
- uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
- This parameter can be any combination value of @ref EXTI_Lines */
-
- EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
- This parameter can be a value of @ref EXTIMode_TypeDef */
-
- EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
- This parameter can be a value of @ref EXTITrigger_TypeDef */
-
- FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
- This parameter can be set either to ENABLE or DISABLE */
-}EXTI_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup EXTI_Exported_Constants
- * @{
- */
-
-/** @defgroup EXTI_Lines
- * @{
- */
-
-#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
-#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
-#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
-#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
-#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
-#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
-#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
-#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
-#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
-#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
-#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
-#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
-#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
-#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
-#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
-#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
-#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
-#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
-#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
-#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
-#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
-#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
-
-#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
-
-#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
- ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
- ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
- ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
- ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
- ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
- ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
- ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
- ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
- ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
- ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\
- ((LINE) == EXTI_Line22))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the EXTI configuration to the default reset state *****/
-void EXTI_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
-void EXTI_ClearFlag(uint32_t EXTI_Line);
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_EXTI_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_flash.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the FLASH
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_FLASH_H
-#define __STM32F4xx_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup FLASH
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/**
- * @brief FLASH Status
- */
-typedef enum
-{
- FLASH_BUSY = 1,
- FLASH_ERROR_PGS,
- FLASH_ERROR_PGP,
- FLASH_ERROR_PGA,
- FLASH_ERROR_WRP,
- FLASH_ERROR_PROGRAM,
- FLASH_ERROR_OPERATION,
- FLASH_COMPLETE
-}FLASH_Status;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FLASH_Exported_Constants
- * @{
- */
-
-/** @defgroup Flash_Latency
- * @{
- */
-#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
-#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */
-#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */
-#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */
-#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */
-#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */
-#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */
-#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */
-
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
- ((LATENCY) == FLASH_Latency_1) || \
- ((LATENCY) == FLASH_Latency_2) || \
- ((LATENCY) == FLASH_Latency_3) || \
- ((LATENCY) == FLASH_Latency_4) || \
- ((LATENCY) == FLASH_Latency_5) || \
- ((LATENCY) == FLASH_Latency_6) || \
- ((LATENCY) == FLASH_Latency_7))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Voltage_Range
- * @{
- */
-#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */
-#define VoltageRange_2 ((uint8_t)0x01) /*!<Device operating range: 2.1V to 2.7V */
-#define VoltageRange_3 ((uint8_t)0x02) /*!<Device operating range: 2.7V to 3.6V */
-#define VoltageRange_4 ((uint8_t)0x03) /*!<Device operating range: 2.7V to 3.6V + External Vpp */
-
-#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) || \
- ((RANGE) == VoltageRange_2) || \
- ((RANGE) == VoltageRange_3) || \
- ((RANGE) == VoltageRange_4))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Sectors
- * @{
- */
-#define FLASH_Sector_0 ((uint16_t)0x0000) /*!< Sector Number 0 */
-#define FLASH_Sector_1 ((uint16_t)0x0008) /*!< Sector Number 1 */
-#define FLASH_Sector_2 ((uint16_t)0x0010) /*!< Sector Number 2 */
-#define FLASH_Sector_3 ((uint16_t)0x0018) /*!< Sector Number 3 */
-#define FLASH_Sector_4 ((uint16_t)0x0020) /*!< Sector Number 4 */
-#define FLASH_Sector_5 ((uint16_t)0x0028) /*!< Sector Number 5 */
-#define FLASH_Sector_6 ((uint16_t)0x0030) /*!< Sector Number 6 */
-#define FLASH_Sector_7 ((uint16_t)0x0038) /*!< Sector Number 7 */
-#define FLASH_Sector_8 ((uint16_t)0x0040) /*!< Sector Number 8 */
-#define FLASH_Sector_9 ((uint16_t)0x0048) /*!< Sector Number 9 */
-#define FLASH_Sector_10 ((uint16_t)0x0050) /*!< Sector Number 10 */
-#define FLASH_Sector_11 ((uint16_t)0x0058) /*!< Sector Number 11 */
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0) || ((SECTOR) == FLASH_Sector_1) ||\
- ((SECTOR) == FLASH_Sector_2) || ((SECTOR) == FLASH_Sector_3) ||\
- ((SECTOR) == FLASH_Sector_4) || ((SECTOR) == FLASH_Sector_5) ||\
- ((SECTOR) == FLASH_Sector_6) || ((SECTOR) == FLASH_Sector_7) ||\
- ((SECTOR) == FLASH_Sector_8) || ((SECTOR) == FLASH_Sector_9) ||\
- ((SECTOR) == FLASH_Sector_10) || ((SECTOR) == FLASH_Sector_11))
-#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\
- (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
-/**
- * @}
- */
-
-/** @defgroup Option_Bytes_Write_Protection
- * @{
- */
-#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
-#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
-#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
-#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
-#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
-#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
-#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
-#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
-#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
-#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
-#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
-#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
-#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
-
-#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_Read_Protection
- * @{
- */
-#define OB_RDP_Level_0 ((uint8_t)0xAA)
-#define OB_RDP_Level_1 ((uint8_t)0x55)
-/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2
- it's no more possible to go back to level 1 or 0 */
-#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
- ((LEVEL) == OB_RDP_Level_1))/*||\
- ((LEVEL) == OB_RDP_Level_2))*/
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_IWatchdog
- * @{
- */
-#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */
-#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_nRST_STOP
- * @{
- */
-#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
-/**
- * @}
- */
-
-
-/** @defgroup FLASH_Option_Bytes_nRST_STDBY
- * @{
- */
-#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
-/**
- * @}
- */
-
-/** @defgroup FLASH_BOR_Reset_Level
- * @{
- */
-#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */
-#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */
-#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */
-#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */
-#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
- ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Interrupts
- * @{
- */
-#define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */
-#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */
-#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Flags
- * @{
- */
-#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */
-#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */
-#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
-#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */
-#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */
-#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */
-#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */
-#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000))
-#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \
- ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
- ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \
- ((FLAG) == FLASH_FLAG_BSY))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Program_Parallelism
- * @{
- */
-#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000)
-#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100)
-#define FLASH_PSIZE_WORD ((uint32_t)0x00000200)
-#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300)
-#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF)
-/**
- * @}
- */
-
-/** @defgroup FLASH_Keys
- * @{
- */
-#define RDP_KEY ((uint16_t)0x00A5)
-#define FLASH_KEY1 ((uint32_t)0x45670123)
-#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
-#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B)
-#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F)
-/**
- * @}
- */
-
-/**
- * @brief ACR register byte 0 (Bits[8:0]) base address
- */
-#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
-/**
- * @brief OPTCR register byte 3 (Bits[24:16]) base address
- */
-#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14)
-#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
-#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16)
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* FLASH Interface configuration functions ************************************/
-void FLASH_SetLatency(uint32_t FLASH_Latency);
-void FLASH_PrefetchBufferCmd(FunctionalState NewState);
-void FLASH_InstructionCacheCmd(FunctionalState NewState);
-void FLASH_DataCacheCmd(FunctionalState NewState);
-void FLASH_InstructionCacheReset(void);
-void FLASH_DataCacheReset(void);
-
-/* FLASH Memory Programming functions *****************************************/
-void FLASH_Unlock(void);
-void FLASH_Lock(void);
-FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);
-FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);
-FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
-FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
-
-/* Option Bytes Programming functions *****************************************/
-void FLASH_OB_Unlock(void);
-void FLASH_OB_Lock(void);
-void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
-void FLASH_OB_RDPConfig(uint8_t OB_RDP);
-void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
-void FLASH_OB_BORConfig(uint8_t OB_BOR);
-FLASH_Status FLASH_OB_Launch(void);
-uint8_t FLASH_OB_GetUser(void);
-uint16_t FLASH_OB_GetWRP(void);
-FlagStatus FLASH_OB_GetRDP(void);
-uint8_t FLASH_OB_GetBOR(void);
-
-/* Interrupts and flags management functions **********************************/
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
-void FLASH_ClearFlag(uint32_t FLASH_FLAG);
-FLASH_Status FLASH_GetStatus(void);
-FLASH_Status FLASH_WaitForLastOperation(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_FLASH_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_fsmc.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the FSMC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_FSMC_H
-#define __STM32F4xx_FSMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup FSMC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief Timing parameters For NOR/SRAM Banks
- */
-typedef struct
-{
- uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address setup time.
- This parameter can be a value between 0 and 0xF.
- @note This parameter is not used with synchronous NOR Flash memories. */
-
- uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address hold time.
- This parameter can be a value between 0 and 0xF.
- @note This parameter is not used with synchronous NOR Flash memories.*/
-
- uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the data setup time.
- This parameter can be a value between 0 and 0xFF.
- @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
-
- uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
- the duration of the bus turnaround.
- This parameter can be a value between 0 and 0xF.
- @note This parameter is only used for multiplexed NOR Flash memories. */
-
- uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
- This parameter can be a value between 1 and 0xF.
- @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
-
- uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
- to the memory before getting the first data.
- The parameter value depends on the memory type as shown below:
- - It must be set to 0 in case of a CRAM
- - It is don't care in asynchronous NOR, SRAM or ROM accesses
- - It may assume a value between 0 and 0xF in NOR Flash memories
- with synchronous burst mode enable */
-
- uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
- This parameter can be a value of @ref FSMC_Access_Mode */
-}FSMC_NORSRAMTimingInitTypeDef;
-
-/**
- * @brief FSMC NOR/SRAM Init structure definition
- */
-typedef struct
-{
- uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
- This parameter can be a value of @ref FSMC_NORSRAM_Bank */
-
- uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
- multiplexed on the databus or not.
- This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
-
- uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
- the corresponding memory bank.
- This parameter can be a value of @ref FSMC_Memory_Type */
-
- uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be a value of @ref FSMC_Data_Width */
-
- uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
- valid only with synchronous burst Flash memories.
- This parameter can be a value of @ref FSMC_Burst_Access_Mode */
-
- uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
- valid only with asynchronous Flash memories.
- This parameter can be a value of @ref FSMC_AsynchronousWait */
-
- uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
- the Flash memory in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
-
- uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
- memory, valid only when accessing Flash memories in burst mode.
- This parameter can be a value of @ref FSMC_Wrap_Mode */
-
- uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
- clock cycle before the wait state or during the wait state,
- valid only when accessing memories in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Timing */
-
- uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
- This parameter can be a value of @ref FSMC_Write_Operation */
-
- uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
- signal, valid for Flash memory access in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal */
-
- uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
- This parameter can be a value of @ref FSMC_Extended_Mode */
-
- uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FSMC_Write_Burst */
-
- FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
-
- FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
-}FSMC_NORSRAMInitTypeDef;
-
-/**
- * @brief Timing parameters For FSMC NAND and PCCARD Banks
- */
-typedef struct
-{
- uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
- the command assertion for NAND-Flash read or write access
- to common/Attribute or I/O memory space (depending on
- the memory space timing to be configured).
- This parameter can be a value between 0 and 0xFF.*/
-
- uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
- command for NAND-Flash read or write access to
- common/Attribute or I/O memory space (depending on the
- memory space timing to be configured).
- This parameter can be a number between 0x00 and 0xFF */
-
- uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
- (and data for write access) after the command deassertion
- for NAND-Flash read or write access to common/Attribute
- or I/O memory space (depending on the memory space timing
- to be configured).
- This parameter can be a number between 0x00 and 0xFF */
-
- uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
- databus is kept in HiZ after the start of a NAND-Flash
- write access to common/Attribute or I/O memory space (depending
- on the memory space timing to be configured).
- This parameter can be a number between 0x00 and 0xFF */
-}FSMC_NAND_PCCARDTimingInitTypeDef;
-
-/**
- * @brief FSMC NAND Init structure definition
- */
-typedef struct
-{
- uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
- This parameter can be a value of @ref FSMC_NAND_Bank */
-
- uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
- This parameter can be any value of @ref FSMC_Wait_feature */
-
- uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be any value of @ref FSMC_Data_Width */
-
- uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
- This parameter can be any value of @ref FSMC_ECC */
-
- uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
- This parameter can be any value of @ref FSMC_ECC_Page_Size */
-
- uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between 0 and 0xFF. */
-
- uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between 0x0 and 0xFF */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
-}FSMC_NANDInitTypeDef;
-
-/**
- * @brief FSMC PCCARD Init structure definition
- */
-
-typedef struct
-{
- uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
- This parameter can be any value of @ref FSMC_Wait_feature */
-
- uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between 0 and 0xFF. */
-
- uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between 0x0 and 0xFF */
-
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
-}FSMC_PCCARDInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FSMC_Exported_Constants
- * @{
- */
-
-/** @defgroup FSMC_NORSRAM_Bank
- * @{
- */
-#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
-#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
-#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
-#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
-/**
- * @}
- */
-
-/** @defgroup FSMC_NAND_Bank
- * @{
- */
-#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
-#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
-/**
- * @}
- */
-
-/** @defgroup FSMC_PCCARD_Bank
- * @{
- */
-#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
-/**
- * @}
- */
-
-#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
- ((BANK) == FSMC_Bank1_NORSRAM2) || \
- ((BANK) == FSMC_Bank1_NORSRAM3) || \
- ((BANK) == FSMC_Bank1_NORSRAM4))
-
-#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
- ((BANK) == FSMC_Bank3_NAND))
-
-#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
- ((BANK) == FSMC_Bank3_NAND) || \
- ((BANK) == FSMC_Bank4_PCCARD))
-
-#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
- ((BANK) == FSMC_Bank3_NAND) || \
- ((BANK) == FSMC_Bank4_PCCARD))
-
-/** @defgroup FSMC_NOR_SRAM_Controller
- * @{
- */
-
-/** @defgroup FSMC_Data_Address_Bus_Multiplexing
- * @{
- */
-
-#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
-#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
-#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
- ((MUX) == FSMC_DataAddressMux_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Memory_Type
- * @{
- */
-
-#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
-#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
-#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
-#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
- ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
- ((MEMORY) == FSMC_MemoryType_NOR))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Width
- * @{
- */
-
-#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
-#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
-#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
- ((WIDTH) == FSMC_MemoryDataWidth_16b))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Burst_Access_Mode
- * @{
- */
-
-#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
-#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
-#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
- ((STATE) == FSMC_BurstAccessMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_AsynchronousWait
- * @{
- */
-#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
-#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
-#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
- ((STATE) == FSMC_AsynchronousWait_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Signal_Polarity
- * @{
- */
-#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
-#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
-#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
- ((POLARITY) == FSMC_WaitSignalPolarity_High))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wrap_Mode
- * @{
- */
-#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
-#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
-#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
- ((MODE) == FSMC_WrapMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Timing
- * @{
- */
-#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
-#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
- ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Write_Operation
- * @{
- */
-#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
-#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
-#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
- ((OPERATION) == FSMC_WriteOperation_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Signal
- * @{
- */
-#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
-#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
-#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
- ((SIGNAL) == FSMC_WaitSignal_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Extended_Mode
- * @{
- */
-#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
-#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
-
-#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
- ((MODE) == FSMC_ExtendedMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Write_Burst
- * @{
- */
-
-#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
-#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
-#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
- ((BURST) == FSMC_WriteBurst_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Address_Setup_Time
- * @{
- */
-#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Address_Hold_Time
- * @{
- */
-#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Setup_Time
- * @{
- */
-#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Bus_Turn_around_Duration
- * @{
- */
-#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_CLK_Division
- * @{
- */
-#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Latency
- * @{
- */
-#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Access_Mode
- * @{
- */
-#define FSMC_AccessMode_A ((uint32_t)0x00000000)
-#define FSMC_AccessMode_B ((uint32_t)0x10000000)
-#define FSMC_AccessMode_C ((uint32_t)0x20000000)
-#define FSMC_AccessMode_D ((uint32_t)0x30000000)
-#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
- ((MODE) == FSMC_AccessMode_B) || \
- ((MODE) == FSMC_AccessMode_C) || \
- ((MODE) == FSMC_AccessMode_D))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_NAND_PCCARD_Controller
- * @{
- */
-
-/** @defgroup FSMC_Wait_feature
- * @{
- */
-#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
-#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
-#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
- ((FEATURE) == FSMC_Waitfeature_Enable))
-/**
- * @}
- */
-
-
-/** @defgroup FSMC_ECC
- * @{
- */
-#define FSMC_ECC_Disable ((uint32_t)0x00000000)
-#define FSMC_ECC_Enable ((uint32_t)0x00000040)
-#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
- ((STATE) == FSMC_ECC_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_ECC_Page_Size
- * @{
- */
-#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
-#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
-#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
-#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
-#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
-#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
-#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_8192Bytes))
-/**
- * @}
- */
-
-/** @defgroup FSMC_TCLR_Setup_Time
- * @{
- */
-#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_TAR_Setup_Time
- * @{
- */
-#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Setup_Time
- * @{
- */
-#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Setup_Time
- * @{
- */
-#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Hold_Setup_Time
- * @{
- */
-#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_HiZ_Setup_Time
- * @{
- */
-#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Interrupt_sources
- * @{
- */
-#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
-#define FSMC_IT_Level ((uint32_t)0x00000010)
-#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
-#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
-#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
- ((IT) == FSMC_IT_Level) || \
- ((IT) == FSMC_IT_FallingEdge))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Flags
- * @{
- */
-#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
-#define FSMC_FLAG_Level ((uint32_t)0x00000002)
-#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
-#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
-#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
- ((FLAG) == FSMC_FLAG_Level) || \
- ((FLAG) == FSMC_FLAG_FallingEdge) || \
- ((FLAG) == FSMC_FLAG_FEMPT))
-
-#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* NOR/SRAM Controller functions **********************************************/
-void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
-void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
-void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
-void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-
-/* NAND Controller functions **************************************************/
-void FSMC_NANDDeInit(uint32_t FSMC_Bank);
-void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
-void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
-void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
-
-/* PCCARD Controller functions ************************************************/
-void FSMC_PCCARDDeInit(void);
-void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
-void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
-void FSMC_PCCARDCmd(FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
-FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
-void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
-ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
-void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_FSMC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_gpio.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the GPIO firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_GPIO_H
-#define __STM32F4xx_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup GPIO
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
- ((PERIPH) == GPIOB) || \
- ((PERIPH) == GPIOC) || \
- ((PERIPH) == GPIOD) || \
- ((PERIPH) == GPIOE) || \
- ((PERIPH) == GPIOF) || \
- ((PERIPH) == GPIOG) || \
- ((PERIPH) == GPIOH) || \
- ((PERIPH) == GPIOI))
-
-/**
- * @brief GPIO Configuration Mode enumeration
- */
-typedef enum
-{
- GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
- GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
- GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
- GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */
-}GPIOMode_TypeDef;
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \
- ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
-
-/**
- * @brief GPIO Output type enumeration
- */
-typedef enum
-{
- GPIO_OType_PP = 0x00,
- GPIO_OType_OD = 0x01
-}GPIOOType_TypeDef;
-#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
-
-
-/**
- * @brief GPIO Output Maximum frequency enumeration
- */
-typedef enum
-{
- GPIO_Speed_2MHz = 0x00, /*!< Low speed */
- GPIO_Speed_25MHz = 0x01, /*!< Medium speed */
- GPIO_Speed_50MHz = 0x02, /*!< Fast speed */
- GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */
-}GPIOSpeed_TypeDef;
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \
- ((SPEED) == GPIO_Speed_50MHz)|| ((SPEED) == GPIO_Speed_100MHz))
-
-/**
- * @brief GPIO Configuration PullUp PullDown enumeration
- */
-typedef enum
-{
- GPIO_PuPd_NOPULL = 0x00,
- GPIO_PuPd_UP = 0x01,
- GPIO_PuPd_DOWN = 0x02
-}GPIOPuPd_TypeDef;
-#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
- ((PUPD) == GPIO_PuPd_DOWN))
-
-/**
- * @brief GPIO Bit SET and Bit RESET enumeration
- */
-typedef enum
-{
- Bit_RESET = 0,
- Bit_SET
-}BitAction;
-#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
-
-
-/**
- * @brief GPIO Init structure definition
- */
-typedef struct
-{
- uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_pins_define */
-
- GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIOMode_TypeDef */
-
- GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIOSpeed_TypeDef */
-
- GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
- This parameter can be a value of @ref GPIOOType_TypeDef */
-
- GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
- This parameter can be a value of @ref GPIOPuPd_TypeDef */
-}GPIO_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants
- * @{
- */
-
-/** @defgroup GPIO_pins_define
- * @{
- */
-#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
-#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
-#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
-#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
-#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
-#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
-#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
-#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
-#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
-#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
-#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
-#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
-#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
-#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
-#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
-#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
-#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
-
-#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
-#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
- ((PIN) == GPIO_Pin_1) || \
- ((PIN) == GPIO_Pin_2) || \
- ((PIN) == GPIO_Pin_3) || \
- ((PIN) == GPIO_Pin_4) || \
- ((PIN) == GPIO_Pin_5) || \
- ((PIN) == GPIO_Pin_6) || \
- ((PIN) == GPIO_Pin_7) || \
- ((PIN) == GPIO_Pin_8) || \
- ((PIN) == GPIO_Pin_9) || \
- ((PIN) == GPIO_Pin_10) || \
- ((PIN) == GPIO_Pin_11) || \
- ((PIN) == GPIO_Pin_12) || \
- ((PIN) == GPIO_Pin_13) || \
- ((PIN) == GPIO_Pin_14) || \
- ((PIN) == GPIO_Pin_15))
-/**
- * @}
- */
-
-
-/** @defgroup GPIO_Pin_sources
- * @{
- */
-#define GPIO_PinSource0 ((uint8_t)0x00)
-#define GPIO_PinSource1 ((uint8_t)0x01)
-#define GPIO_PinSource2 ((uint8_t)0x02)
-#define GPIO_PinSource3 ((uint8_t)0x03)
-#define GPIO_PinSource4 ((uint8_t)0x04)
-#define GPIO_PinSource5 ((uint8_t)0x05)
-#define GPIO_PinSource6 ((uint8_t)0x06)
-#define GPIO_PinSource7 ((uint8_t)0x07)
-#define GPIO_PinSource8 ((uint8_t)0x08)
-#define GPIO_PinSource9 ((uint8_t)0x09)
-#define GPIO_PinSource10 ((uint8_t)0x0A)
-#define GPIO_PinSource11 ((uint8_t)0x0B)
-#define GPIO_PinSource12 ((uint8_t)0x0C)
-#define GPIO_PinSource13 ((uint8_t)0x0D)
-#define GPIO_PinSource14 ((uint8_t)0x0E)
-#define GPIO_PinSource15 ((uint8_t)0x0F)
-
-#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
- ((PINSOURCE) == GPIO_PinSource1) || \
- ((PINSOURCE) == GPIO_PinSource2) || \
- ((PINSOURCE) == GPIO_PinSource3) || \
- ((PINSOURCE) == GPIO_PinSource4) || \
- ((PINSOURCE) == GPIO_PinSource5) || \
- ((PINSOURCE) == GPIO_PinSource6) || \
- ((PINSOURCE) == GPIO_PinSource7) || \
- ((PINSOURCE) == GPIO_PinSource8) || \
- ((PINSOURCE) == GPIO_PinSource9) || \
- ((PINSOURCE) == GPIO_PinSource10) || \
- ((PINSOURCE) == GPIO_PinSource11) || \
- ((PINSOURCE) == GPIO_PinSource12) || \
- ((PINSOURCE) == GPIO_PinSource13) || \
- ((PINSOURCE) == GPIO_PinSource14) || \
- ((PINSOURCE) == GPIO_PinSource15))
-/**
- * @}
- */
-
-/** @defgroup GPIO_Alternat_function_selection_define
- * @{
- */
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
-#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
-#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
-#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
-#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
-#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-#define GPIO_AF_I2S3ext ((uint8_t)0x07) /* I2S3ext Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
-#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
-#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
-#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
-#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
-#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
-#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
-#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
-
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
-#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
-
-/**
- * @brief AF 13 selection
- */
-#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
- ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
- ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
- ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
- ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
- ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
- ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
- ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
- ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
- ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
- ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
- ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
- ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
- ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
- ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
- ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_FSMC) || \
- ((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO) || \
- ((AF) == GPIO_AF_DCMI) || ((AF) == GPIO_AF_EVENTOUT))
-/**
- * @}
- */
-
-/** @defgroup GPIO_Legacy
- * @{
- */
-
-#define GPIO_Mode_AIN GPIO_Mode_AN
-
-#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS
-#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS
-#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the GPIO configuration to the default reset state ****/
-void GPIO_DeInit(GPIO_TypeDef* GPIOx);
-
-/* Initialization and Configuration functions *********************************/
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-
-/* GPIO Read and Write functions **********************************************/
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
-void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-
-/* GPIO Alternate functions configuration function ****************************/
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_GPIO_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_hash.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the HASH
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HASH_H
-#define __STM32F4xx_HASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup HASH
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief HASH Init structure definition
- */
-typedef struct
-{
- uint32_t HASH_AlgoSelection; /*!< SHA-1 or MD5. This parameter can be a value
- of @ref HASH_Algo_Selection */
- uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value
- of @ref HASH_processor_Algorithm_Mode */
- uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or
- bit-string. This parameter can be a value of
- @ref HASH_Data_Type */
- uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter
- can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */
-}HASH_InitTypeDef;
-
-/**
- * @brief HASH message digest result structure definition
- */
-typedef struct
-{
- uint32_t Data[5]; /*!< Message digest result : 5x 32bit words for SHA1 or
- 4x 32bit words for MD5 */
-} HASH_MsgDigest;
-
-/**
- * @brief HASH context swapping structure definition
- */
-typedef struct
-{
- uint32_t HASH_IMR;
- uint32_t HASH_STR;
- uint32_t HASH_CR;
- uint32_t HASH_CSR[51];
-}HASH_Context;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HASH_Exported_Constants
- * @{
- */
-
-/** @defgroup HASH_Algo_Selection
- * @{
- */
-#define HASH_AlgoSelection_SHA1 ((uint16_t)0x0000) /*!< HASH function is SHA1 */
-#define HASH_AlgoSelection_MD5 ((uint16_t)0x0080) /*!< HASH function is MD5 */
-
-#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \
- ((ALGOSELECTION) == HASH_AlgoSelection_MD5))
-/**
- * @}
- */
-
-/** @defgroup HASH_processor_Algorithm_Mode
- * @{
- */
-#define HASH_AlgoMode_HASH ((uint16_t)0x0000) /*!< Algorithm is HASH */
-#define HASH_AlgoMode_HMAC ((uint16_t)0x0040) /*!< Algorithm is HMAC */
-
-#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \
- ((ALGOMODE) == HASH_AlgoMode_HMAC))
-/**
- * @}
- */
-
-/** @defgroup HASH_Data_Type
- * @{
- */
-#define HASH_DataType_32b ((uint16_t)0x0000)
-#define HASH_DataType_16b ((uint16_t)0x0010)
-#define HASH_DataType_8b ((uint16_t)0x0020)
-#define HASH_DataType_1b ((uint16_t)0x0030)
-
-#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \
- ((DATATYPE) == HASH_DataType_16b)|| \
- ((DATATYPE) == HASH_DataType_8b)|| \
- ((DATATYPE) == HASH_DataType_1b))
-/**
- * @}
- */
-
-/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode
- * @{
- */
-#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
-#define HASH_HMACKeyType_LongKey ((uint32_t)0x00010000) /*!< HMAC Key is > 64 bytes */
-
-#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \
- ((KEYTYPE) == HASH_HMACKeyType_LongKey))
-/**
- * @}
- */
-
-/** @defgroup Number_of_valid_bits_in_last_word_of_the_message
- * @{
- */
-#define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F)
-
-/**
- * @}
- */
-
-/** @defgroup HASH_interrupts_definition
- * @{
- */
-#define HASH_IT_DINI ((uint8_t)0x01) /*!< A new block can be entered into the input buffer (DIN)*/
-#define HASH_IT_DCI ((uint8_t)0x02) /*!< Digest calculation complete */
-
-#define IS_HASH_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))
-#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI))
-
-/**
- * @}
- */
-
-/** @defgroup HASH_flags_definition
- * @{
- */
-#define HASH_FLAG_DINIS ((uint16_t)0x0001) /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer.*/
-#define HASH_FLAG_DCIS ((uint16_t)0x0002) /*!< Digest calculation complete */
-#define HASH_FLAG_DMAS ((uint16_t)0x0004) /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
-#define HASH_FLAG_BUSY ((uint16_t)0x0008) /*!< The hash core is Busy : processing a block of data */
-#define HASH_FLAG_DINNE ((uint16_t)0x1000) /*!< DIN not empty : The input buffer contains at least one word of data */
-
-#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \
- ((FLAG) == HASH_FLAG_DCIS) || \
- ((FLAG) == HASH_FLAG_DMAS) || \
- ((FLAG) == HASH_FLAG_BUSY) || \
- ((FLAG) == HASH_FLAG_DINNE))
-
-#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \
- ((FLAG) == HASH_FLAG_DCIS))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the HASH configuration to the default reset state ****/
-void HASH_DeInit(void);
-
-/* HASH Configuration function ************************************************/
-void HASH_Init(HASH_InitTypeDef* HASH_InitStruct);
-void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct);
-void HASH_Reset(void);
-
-/* HASH Message Digest generation functions ***********************************/
-void HASH_DataIn(uint32_t Data);
-uint8_t HASH_GetInFIFOWordsNbr(void);
-void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber);
-void HASH_StartDigest(void);
-void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest);
-
-/* HASH Context swapping functions ********************************************/
-void HASH_SaveContext(HASH_Context* HASH_ContextSave);
-void HASH_RestoreContext(HASH_Context* HASH_ContextRestore);
-
-/* HASH's DMA interface function **********************************************/
-void HASH_DMACmd(FunctionalState NewState);
-
-/* HASH Interrupts and flags management functions *****************************/
-void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState);
-FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG);
-void HASH_ClearFlag(uint16_t HASH_FLAG);
-ITStatus HASH_GetITStatus(uint8_t HASH_IT);
-void HASH_ClearITPendingBit(uint8_t HASH_IT);
-
-/* High Level SHA1 functions **************************************************/
-ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]);
-ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen,
- uint8_t *Input, uint32_t Ilen,
- uint8_t Output[20]);
-
-/* High Level MD5 functions ***************************************************/
-ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]);
-ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen,
- uint8_t *Input, uint32_t Ilen,
- uint8_t Output[16]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_HASH_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_i2c.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the I2C firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_I2C_H
-#define __STM32F4xx_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup I2C
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief I2C Init structure definition
- */
-
-typedef struct
-{
- uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
- This parameter must be set to a value lower than 400kHz */
-
- uint16_t I2C_Mode; /*!< Specifies the I2C mode.
- This parameter can be a value of @ref I2C_mode */
-
- uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
- This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
-
- uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
- This parameter can be a 7-bit or 10-bit address. */
-
- uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
- This parameter can be a value of @ref I2C_acknowledgement */
-
- uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
- This parameter can be a value of @ref I2C_acknowledged_address */
-}I2C_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup I2C_Exported_Constants
- * @{
- */
-
-#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
- ((PERIPH) == I2C2) || \
- ((PERIPH) == I2C3))
-/** @defgroup I2C_mode
- * @{
- */
-
-#define I2C_Mode_I2C ((uint16_t)0x0000)
-#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
-#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
-#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
- ((MODE) == I2C_Mode_SMBusDevice) || \
- ((MODE) == I2C_Mode_SMBusHost))
-/**
- * @}
- */
-
-/** @defgroup I2C_duty_cycle_in_fast_mode
- * @{
- */
-
-#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
-#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
- ((CYCLE) == I2C_DutyCycle_2))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledgement
- * @{
- */
-
-#define I2C_Ack_Enable ((uint16_t)0x0400)
-#define I2C_Ack_Disable ((uint16_t)0x0000)
-#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
- ((STATE) == I2C_Ack_Disable))
-/**
- * @}
- */
-
-/** @defgroup I2C_transfer_direction
- * @{
- */
-
-#define I2C_Direction_Transmitter ((uint8_t)0x00)
-#define I2C_Direction_Receiver ((uint8_t)0x01)
-#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
- ((DIRECTION) == I2C_Direction_Receiver))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledged_address
- * @{
- */
-
-#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
-#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
-#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
- ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
-/**
- * @}
- */
-
-/** @defgroup I2C_registers
- * @{
- */
-
-#define I2C_Register_CR1 ((uint8_t)0x00)
-#define I2C_Register_CR2 ((uint8_t)0x04)
-#define I2C_Register_OAR1 ((uint8_t)0x08)
-#define I2C_Register_OAR2 ((uint8_t)0x0C)
-#define I2C_Register_DR ((uint8_t)0x10)
-#define I2C_Register_SR1 ((uint8_t)0x14)
-#define I2C_Register_SR2 ((uint8_t)0x18)
-#define I2C_Register_CCR ((uint8_t)0x1C)
-#define I2C_Register_TRISE ((uint8_t)0x20)
-#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
- ((REGISTER) == I2C_Register_CR2) || \
- ((REGISTER) == I2C_Register_OAR1) || \
- ((REGISTER) == I2C_Register_OAR2) || \
- ((REGISTER) == I2C_Register_DR) || \
- ((REGISTER) == I2C_Register_SR1) || \
- ((REGISTER) == I2C_Register_SR2) || \
- ((REGISTER) == I2C_Register_CCR) || \
- ((REGISTER) == I2C_Register_TRISE))
-/**
- * @}
- */
-
-/** @defgroup I2C_NACK_position
- * @{
- */
-
-#define I2C_NACKPosition_Next ((uint16_t)0x0800)
-#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
-#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
- ((POSITION) == I2C_NACKPosition_Current))
-/**
- * @}
- */
-
-/** @defgroup I2C_SMBus_alert_pin_level
- * @{
- */
-
-#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
-#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
-#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
- ((ALERT) == I2C_SMBusAlert_High))
-/**
- * @}
- */
-
-/** @defgroup I2C_PEC_position
- * @{
- */
-
-#define I2C_PECPosition_Next ((uint16_t)0x0800)
-#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
-#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
- ((POSITION) == I2C_PECPosition_Current))
-/**
- * @}
- */
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_BUF ((uint16_t)0x0400)
-#define I2C_IT_EVT ((uint16_t)0x0200)
-#define I2C_IT_ERR ((uint16_t)0x0100)
-#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
-#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
-#define I2C_IT_PECERR ((uint32_t)0x01001000)
-#define I2C_IT_OVR ((uint32_t)0x01000800)
-#define I2C_IT_AF ((uint32_t)0x01000400)
-#define I2C_IT_ARLO ((uint32_t)0x01000200)
-#define I2C_IT_BERR ((uint32_t)0x01000100)
-#define I2C_IT_TXE ((uint32_t)0x06000080)
-#define I2C_IT_RXNE ((uint32_t)0x06000040)
-#define I2C_IT_STOPF ((uint32_t)0x02000010)
-#define I2C_IT_ADD10 ((uint32_t)0x02000008)
-#define I2C_IT_BTF ((uint32_t)0x02000004)
-#define I2C_IT_ADDR ((uint32_t)0x02000002)
-#define I2C_IT_SB ((uint32_t)0x02000001)
-
-#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
-
-#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
- ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
- ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
- ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
- ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
- ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
- ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
-/**
- * @}
- */
-
-/** @defgroup I2C_flags_definition
- * @{
- */
-
-/**
- * @brief SR2 register flags
- */
-
-#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
-#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
-#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
-#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
-#define I2C_FLAG_TRA ((uint32_t)0x00040000)
-#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
-#define I2C_FLAG_MSL ((uint32_t)0x00010000)
-
-/**
- * @brief SR1 register flags
- */
-
-#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
-#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
-#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
-#define I2C_FLAG_OVR ((uint32_t)0x10000800)
-#define I2C_FLAG_AF ((uint32_t)0x10000400)
-#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
-#define I2C_FLAG_BERR ((uint32_t)0x10000100)
-#define I2C_FLAG_TXE ((uint32_t)0x10000080)
-#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
-#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
-#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
-#define I2C_FLAG_BTF ((uint32_t)0x10000004)
-#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
-#define I2C_FLAG_SB ((uint32_t)0x10000001)
-
-#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
-
-#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
- ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
- ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
- ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
- ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
- ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
- ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
- ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
- ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
- ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
- ((FLAG) == I2C_FLAG_SB))
-/**
- * @}
- */
-
-/** @defgroup I2C_Events
- * @{
- */
-
-/**
- ===============================================================================
- I2C Master Events (Events grouped in order of communication)
- ===============================================================================
- */
-
-/**
- * @brief Communication start
- *
- * After sending the START condition (I2C_GenerateSTART() function) the master
- * has to wait for this event. It means that the Start condition has been correctly
- * released on the I2C bus (the bus is free, no other devices is communicating).
- *
- */
-/* --EV5 */
-#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
-
-/**
- * @brief Address Acknowledge
- *
- * After checking on EV5 (start condition correctly released on the bus), the
- * master sends the address of the slave(s) with which it will communicate
- * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
- * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
- * his address. If an acknowledge is sent on the bus, one of the following events will
- * be set:
- *
- * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
- * event is set.
- *
- * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
- * is set
- *
- * 3) In case of 10-Bit addressing mode, the master (just after generating the START
- * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
- * function). Then master should wait on EV9. It means that the 10-bit addressing
- * header has been correctly sent on the bus. Then master should send the second part of
- * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
- * should wait for event EV6.
- *
- */
-
-/* --EV6 */
-#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
-#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
-/* --EV9 */
-#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
-
-/**
- * @brief Communication events
- *
- * If a communication is established (START condition generated and slave address
- * acknowledged) then the master has to check on one of the following events for
- * communication procedures:
- *
- * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
- * the data received from the slave (I2C_ReceiveData() function).
- *
- * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
- * function) then to wait on event EV8 or EV8_2.
- * These two events are similar:
- * - EV8 means that the data has been written in the data register and is
- * being shifted out.
- * - EV8_2 means that the data has been physically shifted out and output
- * on the bus.
- * In most cases, using EV8 is sufficient for the application.
- * Using EV8_2 leads to a slower communication but ensure more reliable test.
- * EV8_2 is also more suitable than EV8 for testing on the last data transmission
- * (before Stop condition generation).
- *
- * @note In case the user software does not guarantee that this event EV7 is
- * managed before the current byte end of transfer, then user may check on EV7
- * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
- * In this case the communication may be slower.
- *
- */
-
-/* Master RECEIVER mode -----------------------------*/
-/* --EV7 */
-#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
-
-/* Master TRANSMITTER mode --------------------------*/
-/* --EV8 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
-/* --EV8_2 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
-
-
-/**
- ===============================================================================
- I2C Slave Events (Events grouped in order of communication)
- ===============================================================================
- */
-
-
-/**
- * @brief Communication start events
- *
- * Wait on one of these events at the start of the communication. It means that
- * the I2C peripheral detected a Start condition on the bus (generated by master
- * device) followed by the peripheral address. The peripheral generates an ACK
- * condition on the bus (if the acknowledge feature is enabled through function
- * I2C_AcknowledgeConfig()) and the events listed above are set :
- *
- * 1) In normal case (only one address managed by the slave), when the address
- * sent by the master matches the own address of the peripheral (configured by
- * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
- * (where XXX could be TRANSMITTER or RECEIVER).
- *
- * 2) In case the address sent by the master matches the second address of the
- * peripheral (configured by the function I2C_OwnAddress2Config() and enabled
- * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
- * (where XXX could be TRANSMITTER or RECEIVER) are set.
- *
- * 3) In case the address sent by the master is General Call (address 0x00) and
- * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
- * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
- *
- */
-
-/* --EV1 (all the events below are variants of EV1) */
-/* 1) Case of One Single Address managed by the slave */
-#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
-#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
-
-/* 2) Case of Dual address managed by the slave */
-#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
-#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
-
-/* 3) Case of General Call enabled for the slave */
-#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
-
-/**
- * @brief Communication events
- *
- * Wait on one of these events when EV1 has already been checked and:
- *
- * - Slave RECEIVER mode:
- * - EV2: When the application is expecting a data byte to be received.
- * - EV4: When the application is expecting the end of the communication: master
- * sends a stop condition and data transmission is stopped.
- *
- * - Slave Transmitter mode:
- * - EV3: When a byte has been transmitted by the slave and the application is expecting
- * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
- * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
- * used when the user software doesn't guarantee the EV3 is managed before the
- * current byte end of transfer.
- * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
- * shall end (before sending the STOP condition). In this case slave has to stop sending
- * data bytes and expect a Stop condition on the bus.
- *
- * @note In case the user software does not guarantee that the event EV2 is
- * managed before the current byte end of transfer, then user may check on EV2
- * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
- * In this case the communication may be slower.
- *
- */
-
-/* Slave RECEIVER mode --------------------------*/
-/* --EV2 */
-#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
-/* --EV4 */
-#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
-
-/* Slave TRANSMITTER mode -----------------------*/
-/* --EV3 */
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
-/* --EV3_2 */
-#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
-
-/*
- ===============================================================================
- End of Events Description
- ===============================================================================
- */
-
-#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
- ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
- ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
- ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
- ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
-/**
- * @}
- */
-
-/** @defgroup I2C_own_address1
- * @{
- */
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
-/**
- * @}
- */
-
-/** @defgroup I2C_clock_speed
- * @{
- */
-
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the I2C configuration to the default reset state *****/
-void I2C_DeInit(I2C_TypeDef* I2Cx);
-
-/* Initialization and Configuration functions *********************************/
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
-void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-
-/* Data transfers functions ***************************************************/
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
-
-/* PEC management functions ***************************************************/
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
-
-/* DMA transfers management functions *****************************************/
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-
-/* Interrupts, events and flags management functions **************************/
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
-
-/*
- ===============================================================================
- I2C State Monitoring Functions
- ===============================================================================
- This I2C driver provides three different ways for I2C state monitoring
- depending on the application requirements and constraints:
-
-
- 1. Basic state monitoring (Using I2C_CheckEvent() function)
- -----------------------------------------------------------
- It compares the status registers (SR1 and SR2) content to a given event
- (can be the combination of one or more flags).
- It returns SUCCESS if the current status includes the given flags
- and returns ERROR if one or more flags are missing in the current status.
-
- - When to use
- - This function is suitable for most applications as well as for startup
- activity since the events are fully described in the product reference
- manual (RM0090).
- - It is also suitable for users who need to define their own events.
-
- - Limitations
- - If an error occurs (ie. error flags are set besides to the monitored
- flags), the I2C_CheckEvent() function may return SUCCESS despite
- the communication hold or corrupted real state.
- In this case, it is advised to use error interrupts to monitor
- the error events and handle them in the interrupt IRQ handler.
-
- Note
- For error management, it is advised to use the following functions:
- - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
- Where x is the peripheral instance (I2C1, I2C2 ...)
- - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
- I2Cx_ER_IRQHandler() function in order to determine which error occurred.
- - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
- and/or I2C_GenerateStop() in order to clear the error flag and source
- and return to correct communication status.
-
-
- 2. Advanced state monitoring (Using the function I2C_GetLastEvent())
- --------------------------------------------------------------------
- Using the function I2C_GetLastEvent() which returns the image of both status
- registers in a single word (uint32_t) (Status Register 2 value is shifted left
- by 16 bits and concatenated to Status Register 1).
-
- - When to use
- - This function is suitable for the same applications above but it
- allows to overcome the mentioned limitation of I2C_GetFlagStatus()
- function.
- - The returned value could be compared to events already defined in
- this file or to custom values defined by user.
- This function is suitable when multiple flags are monitored at the
- same time.
- - At the opposite of I2C_CheckEvent() function, this function allows
- user to choose when an event is accepted (when all events flags are
- set and no other flags are set or just when the needed flags are set
- like I2C_CheckEvent() function.
-
- - Limitations
- - User may need to define his own events.
- - Same remark concerning the error management is applicable for this
- function if user decides to check only regular communication flags
- (and ignores error flags).
-
-
- 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
- -----------------------------------------------------------------------
-
- Using the function I2C_GetFlagStatus() which simply returns the status of
- one single flag (ie. I2C_FLAG_RXNE ...).
-
- - When to use
- - This function could be used for specific applications or in debug
- phase.
- - It is suitable when only one flag checking is needed (most I2C
- events are monitored through multiple flags).
- - Limitations:
- - When calling this function, the Status register is accessed.
- Some flags are cleared when the status register is accessed.
- So checking the status of one Flag, may clear other ones.
- - Function may need to be called twice or more in order to monitor
- one single event.
- */
-
-/*
- ===============================================================================
- 1. Basic state monitoring
- ===============================================================================
- */
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
-/*
- ===============================================================================
- 2. Advanced state monitoring
- ===============================================================================
- */
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
-/*
- ===============================================================================
- 3. Flag-based state monitoring
- ===============================================================================
- */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-
-
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_I2C_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_iwdg.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the IWDG
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_IWDG_H
-#define __STM32F4xx_IWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup IWDG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup IWDG_Exported_Constants
- * @{
- */
-
-/** @defgroup IWDG_WriteAccess
- * @{
- */
-#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
-#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
-#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
- ((ACCESS) == IWDG_WriteAccess_Disable))
-/**
- * @}
- */
-
-/** @defgroup IWDG_prescaler
- * @{
- */
-#define IWDG_Prescaler_4 ((uint8_t)0x00)
-#define IWDG_Prescaler_8 ((uint8_t)0x01)
-#define IWDG_Prescaler_16 ((uint8_t)0x02)
-#define IWDG_Prescaler_32 ((uint8_t)0x03)
-#define IWDG_Prescaler_64 ((uint8_t)0x04)
-#define IWDG_Prescaler_128 ((uint8_t)0x05)
-#define IWDG_Prescaler_256 ((uint8_t)0x06)
-#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
- ((PRESCALER) == IWDG_Prescaler_8) || \
- ((PRESCALER) == IWDG_Prescaler_16) || \
- ((PRESCALER) == IWDG_Prescaler_32) || \
- ((PRESCALER) == IWDG_Prescaler_64) || \
- ((PRESCALER) == IWDG_Prescaler_128)|| \
- ((PRESCALER) == IWDG_Prescaler_256))
-/**
- * @}
- */
-
-/** @defgroup IWDG_Flag
- * @{
- */
-#define IWDG_FLAG_PVU ((uint16_t)0x0001)
-#define IWDG_FLAG_RVU ((uint16_t)0x0002)
-#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
-#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Prescaler and Counter configuration functions ******************************/
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
-void IWDG_SetReload(uint16_t Reload);
-void IWDG_ReloadCounter(void);
-
-/* IWDG activation function ***************************************************/
-void IWDG_Enable(void);
-
-/* Flag management function ***************************************************/
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_IWDG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_pwr.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the PWR firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_PWR_H
-#define __STM32F4xx_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup PWR
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Constants
- * @{
- */
-
-/** @defgroup PWR_PVD_detection_level
- * @{
- */
-
-#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
-#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
-#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
-#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
-#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
-#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
-#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
-#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7
-
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
- ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
- ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
- ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
-/**
- * @}
- */
-
-
-/** @defgroup PWR_Regulator_state_in_STOP_mode
- * @{
- */
-
-#define PWR_Regulator_ON ((uint32_t)0x00000000)
-#define PWR_Regulator_LowPower PWR_CR_LPDS
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
- ((REGULATOR) == PWR_Regulator_LowPower))
-/**
- * @}
- */
-
-/** @defgroup PWR_STOP_mode_entry
- * @{
- */
-
-#define PWR_STOPEntry_WFI ((uint8_t)0x01)
-#define PWR_STOPEntry_WFE ((uint8_t)0x02)
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Flag
- * @{
- */
-
-#define PWR_FLAG_WU PWR_CSR_WUF
-#define PWR_FLAG_SB PWR_CSR_SBF
-#define PWR_FLAG_PVDO PWR_CSR_PVDO
-#define PWR_FLAG_BRR PWR_CSR_BRR
-#define PWR_FLAG_REGRDY PWR_CSR_REGRDY
-
-#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
- ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \
- ((FLAG) == PWR_FLAG_REGRDY))
-
-#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the PWR configuration to the default reset state ******/
-void PWR_DeInit(void);
-
-/* Backup Domain Access function **********************************************/
-void PWR_BackupAccessCmd(FunctionalState NewState);
-
-/* PVD configuration functions ************************************************/
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
-void PWR_PVDCmd(FunctionalState NewState);
-
-/* WakeUp pins configuration functions ****************************************/
-void PWR_WakeUpPinCmd(FunctionalState NewState);
-
-/* Backup Regulator configuration functions ***********************************/
-void PWR_BackupRegulatorCmd(FunctionalState NewState);
-
-/* Performance Mode and FLASH Power Down configuration functions **************/
-void PWR_HighPerformanceModeCmd(FunctionalState NewState);
-void PWR_FlashPowerDownCmd(FunctionalState NewState);
-
-/* Low Power modes configuration functions ************************************/
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
-void PWR_EnterSTANDBYMode(void);
-
-/* Flags management functions *************************************************/
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
-void PWR_ClearFlag(uint32_t PWR_FLAG);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_PWR_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_rcc.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the RCC firmware library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_RCC_H
-#define __STM32F4xx_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup RCC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-typedef struct
-{
- uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
- uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
- uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
- uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
-}RCC_ClocksTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Constants
- * @{
- */
-
-/** @defgroup RCC_HSE_configuration
- * @{
- */
-#define RCC_HSE_OFF ((uint8_t)0x00)
-#define RCC_HSE_ON ((uint8_t)0x01)
-#define RCC_HSE_Bypass ((uint8_t)0x05)
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
- ((HSE) == RCC_HSE_Bypass))
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Clock_Source
- * @{
- */
-#define RCC_PLLSource_HSI ((uint32_t)0x00000000)
-#define RCC_PLLSource_HSE ((uint32_t)0x00400000)
-#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
- ((SOURCE) == RCC_PLLSource_HSE))
-#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
-#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
-#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
-
-#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source
- * @{
- */
-#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
-#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
-#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
-#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
- ((SOURCE) == RCC_SYSCLKSource_HSE) || \
- ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Clock_Source
- * @{
- */
-#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
-#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
-#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
-#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
-#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
-#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
-#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
-#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
-#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
- ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
- ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
- ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
- ((HCLK) == RCC_SYSCLK_Div512))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_APB2_Clock_Source
- * @{
- */
-#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
-#define RCC_HCLK_Div2 ((uint32_t)0x00001000)
-#define RCC_HCLK_Div4 ((uint32_t)0x00001400)
-#define RCC_HCLK_Div8 ((uint32_t)0x00001800)
-#define RCC_HCLK_Div16 ((uint32_t)0x00001C00)
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
- ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
- ((PCLK) == RCC_HCLK_Div16))
-/**
- * @}
- */
-
-/** @defgroup RCC_Interrupt_Source
- * @{
- */
-#define RCC_IT_LSIRDY ((uint8_t)0x01)
-#define RCC_IT_LSERDY ((uint8_t)0x02)
-#define RCC_IT_HSIRDY ((uint8_t)0x04)
-#define RCC_IT_HSERDY ((uint8_t)0x08)
-#define RCC_IT_PLLRDY ((uint8_t)0x10)
-#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
-#define RCC_IT_CSS ((uint8_t)0x80)
-#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
-#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
- ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
- ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
- ((IT) == RCC_IT_PLLI2SRDY))
-#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_Configuration
- * @{
- */
-#define RCC_LSE_OFF ((uint8_t)0x00)
-#define RCC_LSE_ON ((uint8_t)0x01)
-#define RCC_LSE_Bypass ((uint8_t)0x04)
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
- ((LSE) == RCC_LSE_Bypass))
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_Clock_Source
- * @{
- */
-#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
-#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
-#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
-#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
-#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
-#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
-#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
-#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
-#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
-#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
-#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
-#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
-#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
-#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)
-#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
-#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
-#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
-#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
-#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
-#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)
-#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
-#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
-#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
-#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
-#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
-#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
-#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
-#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
-#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
-#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)
-#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
-#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
-#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
- ((SOURCE) == RCC_RTCCLKSource_LSI) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
-/**
- * @}
- */
-
-/** @defgroup RCC_I2S_Clock_Source
- * @{
- */
-#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)
-#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
-
-#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB1_Peripherals
- * @{
- */
-#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
-#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
-#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)
-#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
-#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)
-#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
-#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
-#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
-#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
-#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
-#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
-#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
-#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
-#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
-#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
-#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
-#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
-#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
-#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
-#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
-#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
-#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
-#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x819BEE00) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_Peripherals
- * @{
- */
-#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
-#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
-#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
-#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
-#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
-#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB3_Peripherals
- * @{
- */
-#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
-#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Peripherals
- * @{
- */
-#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
-#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
-#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
-#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
-#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
-#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
-#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
-#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
-#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
-#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
-#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
-#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
-#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
-#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
-#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
-#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
-#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
-#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
-#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
-#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
-#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
-#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
-#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
-#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Peripherals
- * @{
- */
-#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
-#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
-#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
-#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
-#define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
-#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
-#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)
-#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
-#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
-#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
-#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
-#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
-#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
-#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
-#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup RCC_MCO1_Clock_Source_Prescaler
- * @{
- */
-#define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
-#define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
-#define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
-#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
-#define RCC_MCO1Div_1 ((uint32_t)0x00000000)
-#define RCC_MCO1Div_2 ((uint32_t)0x04000000)
-#define RCC_MCO1Div_3 ((uint32_t)0x05000000)
-#define RCC_MCO1Div_4 ((uint32_t)0x06000000)
-#define RCC_MCO1Div_5 ((uint32_t)0x07000000)
-#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
- ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
-
-#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
- ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
- ((DIV) == RCC_MCO1Div_5))
-/**
- * @}
- */
-
-/** @defgroup RCC_MCO2_Clock_Source_Prescaler
- * @{
- */
-#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
-#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)
-#define RCC_MCO2Source_HSE ((uint32_t)0x80000000)
-#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)
-#define RCC_MCO2Div_1 ((uint32_t)0x00000000)
-#define RCC_MCO2Div_2 ((uint32_t)0x20000000)
-#define RCC_MCO2Div_3 ((uint32_t)0x28000000)
-#define RCC_MCO2Div_4 ((uint32_t)0x30000000)
-#define RCC_MCO2Div_5 ((uint32_t)0x38000000)
-#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
- ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
-
-#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
- ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
- ((DIV) == RCC_MCO2Div_5))
-/**
- * @}
- */
-
-/** @defgroup RCC_Flag
- * @{
- */
-#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
-#define RCC_FLAG_HSERDY ((uint8_t)0x31)
-#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
-#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
-#define RCC_FLAG_LSERDY ((uint8_t)0x41)
-#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
-#define RCC_FLAG_BORRST ((uint8_t)0x79)
-#define RCC_FLAG_PINRST ((uint8_t)0x7A)
-#define RCC_FLAG_PORRST ((uint8_t)0x7B)
-#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
-#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
-#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
-#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
-#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
- ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
- ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
- ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
- ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
- ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
- ((FLAG) == RCC_FLAG_PLLI2SRDY))
-#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the RCC clock configuration to the default reset state */
-void RCC_DeInit(void);
-
-/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
-void RCC_HSEConfig(uint8_t RCC_HSE);
-ErrorStatus RCC_WaitForHSEStartUp(void);
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
-void RCC_HSICmd(FunctionalState NewState);
-void RCC_LSEConfig(uint8_t RCC_LSE);
-void RCC_LSICmd(FunctionalState NewState);
-
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
-void RCC_PLLCmd(FunctionalState NewState);
-void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
-void RCC_PLLI2SCmd(FunctionalState NewState);
-
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
-void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
-void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
-
-/* System, AHB and APB busses clocks configuration functions ******************/
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
-uint8_t RCC_GetSYSCLKSource(void);
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
-void RCC_PCLK1Config(uint32_t RCC_HCLK);
-void RCC_PCLK2Config(uint32_t RCC_HCLK);
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
-
-/* Peripheral clocks configuration functions **********************************/
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
-void RCC_RTCCLKCmd(FunctionalState NewState);
-void RCC_BackupResetCmd(FunctionalState NewState);
-void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
-
-void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
-void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
-void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-
-void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
-void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
-void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-
-void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
-void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
-void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
-void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
-void RCC_ClearFlag(void);
-ITStatus RCC_GetITStatus(uint8_t RCC_IT);
-void RCC_ClearITPendingBit(uint8_t RCC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_RCC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_rng.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the Random
- * Number Generator(RNG) firmware library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_RNG_H
-#define __STM32F4xx_RNG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup RNG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RNG_Exported_Constants
- * @{
- */
-
-/** @defgroup RNG_flags_definition
- * @{
- */
-#define RNG_FLAG_DRDY ((uint8_t)0x0001) /*!< Data ready */
-#define RNG_FLAG_CECS ((uint8_t)0x0002) /*!< Clock error current status */
-#define RNG_FLAG_SECS ((uint8_t)0x0004) /*!< Seed error current status */
-
-#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \
- ((RNG_FLAG) == RNG_FLAG_CECS) || \
- ((RNG_FLAG) == RNG_FLAG_SECS))
-#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \
- ((RNG_FLAG) == RNG_FLAG_SECS))
-/**
- * @}
- */
-
-/** @defgroup RNG_interrupts_definition
- * @{
- */
-#define RNG_IT_CEI ((uint8_t)0x20) /*!< Clock error interrupt */
-#define RNG_IT_SEI ((uint8_t)0x40) /*!< Seed error interrupt */
-
-#define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00))
-#define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the RNG configuration to the default reset state *****/
-void RNG_DeInit(void);
-
-/* Configuration function *****************************************************/
-void RNG_Cmd(FunctionalState NewState);
-
-/* Get 32 bit Random number function ******************************************/
-uint32_t RNG_GetRandomNumber(void);
-
-/* Interrupts and flags management functions **********************************/
-void RNG_ITConfig(FunctionalState NewState);
-FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG);
-void RNG_ClearFlag(uint8_t RNG_FLAG);
-ITStatus RNG_GetITStatus(uint8_t RNG_IT);
-void RNG_ClearITPendingBit(uint8_t RNG_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_RNG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_rtc.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the RTC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_RTC_H
-#define __STM32F4xx_RTC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup RTC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief RTC Init structures definition
- */
-typedef struct
-{
- uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
- This parameter can be a value of @ref RTC_Hour_Formats */
-
- uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
- This parameter must be set to a value lower than 0x7F */
-
- uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
- This parameter must be set to a value lower than 0x7FFF */
-}RTC_InitTypeDef;
-
-/**
- * @brief RTC Time structure definition
- */
-typedef struct
-{
- uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.
- This parameter must be set to a value in the 0-12 range
- if the RTC_HourFormat_12 is selected or 0-23 range if
- the RTC_HourFormat_24 is selected. */
-
- uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.
- This parameter must be set to a value in the 0-59 range. */
-
- uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.
- This parameter must be set to a value in the 0-59 range. */
-
- uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.
- This parameter can be a value of @ref RTC_AM_PM_Definitions */
-}RTC_TimeTypeDef;
-
-/**
- * @brief RTC Date structure definition
- */
-typedef struct
-{
- uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
- This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
- uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format).
- This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
- uint8_t RTC_Date; /*!< Specifies the RTC Date.
- This parameter must be set to a value in the 1-31 range. */
-
- uint8_t RTC_Year; /*!< Specifies the RTC Date Year.
- This parameter must be set to a value in the 0-99 range. */
-}RTC_DateTypeDef;
-
-/**
- * @brief RTC Alarm structure definition
- */
-typedef struct
-{
- RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */
-
- uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.
- This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-
- uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
- This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-
- uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
- If the Alarm Date is selected, this parameter
- must be set to a value in the 1-31 range.
- If the Alarm WeekDay is selected, this
- parameter can be a value of @ref RTC_WeekDay_Definitions */
-}RTC_AlarmTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RTC_Exported_Constants
- * @{
- */
-
-
-/** @defgroup RTC_Hour_Formats
- * @{
- */
-#define RTC_HourFormat_24 ((uint32_t)0x00000000)
-#define RTC_HourFormat_12 ((uint32_t)0x00000040)
-#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
- ((FORMAT) == RTC_HourFormat_24))
-/**
- * @}
- */
-
-/** @defgroup RTC_Asynchronous_Predivider
- * @{
- */
-#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Synchronous_Predivider
- * @{
- */
-#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Time_Definitions
- * @{
- */
-#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
-#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
-#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_AM_PM_Definitions
- * @{
- */
-#define RTC_H12_AM ((uint8_t)0x00)
-#define RTC_H12_PM ((uint8_t)0x40)
-#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Year_Date_Definitions
- * @{
- */
-#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Month_Date_Definitions
- * @{
- */
-
-/* Coded in BCD format */
-#define RTC_Month_January ((uint8_t)0x01)
-#define RTC_Month_February ((uint8_t)0x02)
-#define RTC_Month_March ((uint8_t)0x03)
-#define RTC_Month_April ((uint8_t)0x04)
-#define RTC_Month_May ((uint8_t)0x05)
-#define RTC_Month_June ((uint8_t)0x06)
-#define RTC_Month_July ((uint8_t)0x07)
-#define RTC_Month_August ((uint8_t)0x08)
-#define RTC_Month_September ((uint8_t)0x09)
-#define RTC_Month_October ((uint8_t)0x10)
-#define RTC_Month_November ((uint8_t)0x11)
-#define RTC_Month_December ((uint8_t)0x12)
-#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
-#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_WeekDay_Definitions
- * @{
- */
-
-#define RTC_Weekday_Monday ((uint8_t)0x01)
-#define RTC_Weekday_Tuesday ((uint8_t)0x02)
-#define RTC_Weekday_Wednesday ((uint8_t)0x03)
-#define RTC_Weekday_Thursday ((uint8_t)0x04)
-#define RTC_Weekday_Friday ((uint8_t)0x05)
-#define RTC_Weekday_Saturday ((uint8_t)0x06)
-#define RTC_Weekday_Sunday ((uint8_t)0x07)
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
- ((WEEKDAY) == RTC_Weekday_Tuesday) || \
- ((WEEKDAY) == RTC_Weekday_Wednesday) || \
- ((WEEKDAY) == RTC_Weekday_Thursday) || \
- ((WEEKDAY) == RTC_Weekday_Friday) || \
- ((WEEKDAY) == RTC_Weekday_Saturday) || \
- ((WEEKDAY) == RTC_Weekday_Sunday))
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Alarm_Definitions
- * @{
- */
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
- ((WEEKDAY) == RTC_Weekday_Tuesday) || \
- ((WEEKDAY) == RTC_Weekday_Wednesday) || \
- ((WEEKDAY) == RTC_Weekday_Thursday) || \
- ((WEEKDAY) == RTC_Weekday_Friday) || \
- ((WEEKDAY) == RTC_Weekday_Saturday) || \
- ((WEEKDAY) == RTC_Weekday_Sunday))
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions
- * @{
- */
-#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
-#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
- ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_AlarmMask_Definitions
- * @{
- */
-#define RTC_AlarmMask_None ((uint32_t)0x00000000)
-#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
-#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)
-#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
-#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)
-#define RTC_AlarmMask_All ((uint32_t)0x80808080)
-#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarms_Definitions
- * @{
- */
-#define RTC_Alarm_A ((uint32_t)0x00000100)
-#define RTC_Alarm_B ((uint32_t)0x00000200)
-#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
-#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
-
-/**
- * @}
- */
-
- /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
- * @{
- */
-#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
- There is no comparison on sub seconds
- for Alarm */
-#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
- comparison. Only SS[0] is compared. */
-#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
- comparison. Only SS[1:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
- comparison. Only SS[2:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
- comparison. Only SS[3:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
- comparison. Only SS[4:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
- comparison. Only SS[5:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
- comparison. Only SS[6:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
- comparison. Only SS[7:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
- comparison. Only SS[8:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
- comparison. Only SS[9:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
- comparison. Only SS[10:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
- comparison.Only SS[11:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
- comparison. Only SS[12:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
- comparison.Only SS[13:0] are compared */
-#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
- to activate alarm. */
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
- ((MASK) == RTC_AlarmSubSecondMask_None))
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Value
- * @{
- */
-
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Wakeup_Timer_Definitions
- * @{
- */
-#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)
-#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)
-#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)
-#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)
-#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)
-#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)
-#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
- ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
- ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
-#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
-/**
- * @}
- */
-
-/** @defgroup RTC_Time_Stamp_Edges_definitions
- * @{
- */
-#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)
-#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)
-#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
- ((EDGE) == RTC_TimeStampEdge_Falling))
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_selection_Definitions
- * @{
- */
-#define RTC_Output_Disable ((uint32_t)0x00000000)
-#define RTC_Output_AlarmA ((uint32_t)0x00200000)
-#define RTC_Output_AlarmB ((uint32_t)0x00400000)
-#define RTC_Output_WakeUp ((uint32_t)0x00600000)
-
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
- ((OUTPUT) == RTC_Output_AlarmA) || \
- ((OUTPUT) == RTC_Output_AlarmB) || \
- ((OUTPUT) == RTC_Output_WakeUp))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Polarity_Definitions
- * @{
- */
-#define RTC_OutputPolarity_High ((uint32_t)0x00000000)
-#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
- ((POL) == RTC_OutputPolarity_Low))
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Digital_Calibration_Definitions
- * @{
- */
-#define RTC_CalibSign_Positive ((uint32_t)0x00000000)
-#define RTC_CalibSign_Negative ((uint32_t)0x00000080)
-#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
- ((SIGN) == RTC_CalibSign_Negative))
-#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
-
-/**
- * @}
- */
-
- /** @defgroup RTC_Calib_Output_selection_Definitions
- * @{
- */
-#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000)
-#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)
-#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \
- ((OUTPUT) == RTC_CalibOutput_1Hz))
-/**
- * @}
- */
-
-/** @defgroup RTC_Smooth_calib_period_Definitions
- * @{
- */
-#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
- period is 32s, else 2exp20 RTCCLK seconds */
-#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
- period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
- period is 8s, else 2exp18 RTCCLK seconds */
-#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
- ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
- ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions
- * @{
- */
-#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
- during a X -second window = Y - CALM[8:0].
- with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
- during a 32-second window = CALM[8:0]. */
-#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
- ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions
- * @{
- */
-#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_DayLightSaving_Definitions
- * @{
- */
-#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)
-#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)
-#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
- ((SAVE) == RTC_DayLightSaving_ADD1H))
-
-#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)
-#define RTC_StoreOperation_Set ((uint32_t)0x00040000)
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
- ((OPERATION) == RTC_StoreOperation_Set))
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Trigger_Definitions
- * @{
- */
-#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
-#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)
-#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
-#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
- ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
- ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
- ((TRIGGER) == RTC_TamperTrigger_HighLevel))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Filter_Definitions
- * @{
- */
-#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
-
-#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2
- consecutive samples at the active level */
-#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4
- consecutive samples at the active level */
-#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8
- consecutive samples at the active leve. */
-#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
- ((FILTER) == RTC_TamperFilter_2Sample) || \
- ((FILTER) == RTC_TamperFilter_4Sample) || \
- ((FILTER) == RTC_TamperFilter_8Sample))
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
- * @{
- */
-#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 32768 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 16384 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 8192 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 4096 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 2048 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 1024 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 512 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 256 */
-#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
-
-/**
- * @}
- */
-
- /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
- * @{
- */
-#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
- sampling during 1 RTCCLK cycle */
-#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
- sampling during 2 RTCCLK cycles */
-#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
- sampling during 4 RTCCLK cycles */
-#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
- sampling during 8 RTCCLK cycles */
-
-#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
- ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
- ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
- ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Pins_Definitions
- * @{
- */
-#define RTC_Tamper_1 RTC_TAFCR_TAMP1E
-#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Pin_Selection
- * @{
- */
-#define RTC_TamperPin_PC13 ((uint32_t)0x00000000)
-#define RTC_TamperPin_PI8 ((uint32_t)0x00010000)
-#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \
- ((PIN) == RTC_TamperPin_PI8))
-/**
- * @}
- */
-
-/** @defgroup RTC_TimeStamp_Pin_Selection
- * @{
- */
-#define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000)
-#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000)
-#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \
- ((PIN) == RTC_TimeStampPin_PI8))
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Type_ALARM_OUT
- * @{
- */
-#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)
-#define RTC_OutputType_PushPull ((uint32_t)0x00040000)
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
- ((TYPE) == RTC_OutputType_PushPull))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Add_1_Second_Parameter_Definitions
- * @{
- */
-#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)
-#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)
-#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
- ((SEL) == RTC_ShiftAdd1S_Set))
-/**
- * @}
- */
-
-/** @defgroup RTC_Substract_Fraction_Of_Second_Value
- * @{
- */
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Backup_Registers_Definitions
- * @{
- */
-
-#define RTC_BKP_DR0 ((uint32_t)0x00000000)
-#define RTC_BKP_DR1 ((uint32_t)0x00000001)
-#define RTC_BKP_DR2 ((uint32_t)0x00000002)
-#define RTC_BKP_DR3 ((uint32_t)0x00000003)
-#define RTC_BKP_DR4 ((uint32_t)0x00000004)
-#define RTC_BKP_DR5 ((uint32_t)0x00000005)
-#define RTC_BKP_DR6 ((uint32_t)0x00000006)
-#define RTC_BKP_DR7 ((uint32_t)0x00000007)
-#define RTC_BKP_DR8 ((uint32_t)0x00000008)
-#define RTC_BKP_DR9 ((uint32_t)0x00000009)
-#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
-#define RTC_BKP_DR11 ((uint32_t)0x0000000B)
-#define RTC_BKP_DR12 ((uint32_t)0x0000000C)
-#define RTC_BKP_DR13 ((uint32_t)0x0000000D)
-#define RTC_BKP_DR14 ((uint32_t)0x0000000E)
-#define RTC_BKP_DR15 ((uint32_t)0x0000000F)
-#define RTC_BKP_DR16 ((uint32_t)0x00000010)
-#define RTC_BKP_DR17 ((uint32_t)0x00000011)
-#define RTC_BKP_DR18 ((uint32_t)0x00000012)
-#define RTC_BKP_DR19 ((uint32_t)0x00000013)
-#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
- ((BKP) == RTC_BKP_DR1) || \
- ((BKP) == RTC_BKP_DR2) || \
- ((BKP) == RTC_BKP_DR3) || \
- ((BKP) == RTC_BKP_DR4) || \
- ((BKP) == RTC_BKP_DR5) || \
- ((BKP) == RTC_BKP_DR6) || \
- ((BKP) == RTC_BKP_DR7) || \
- ((BKP) == RTC_BKP_DR8) || \
- ((BKP) == RTC_BKP_DR9) || \
- ((BKP) == RTC_BKP_DR10) || \
- ((BKP) == RTC_BKP_DR11) || \
- ((BKP) == RTC_BKP_DR12) || \
- ((BKP) == RTC_BKP_DR13) || \
- ((BKP) == RTC_BKP_DR14) || \
- ((BKP) == RTC_BKP_DR15) || \
- ((BKP) == RTC_BKP_DR16) || \
- ((BKP) == RTC_BKP_DR17) || \
- ((BKP) == RTC_BKP_DR18) || \
- ((BKP) == RTC_BKP_DR19))
-/**
- * @}
- */
-
-/** @defgroup RTC_Input_parameter_format_definitions
- * @{
- */
-#define RTC_Format_BIN ((uint32_t)0x000000000)
-#define RTC_Format_BCD ((uint32_t)0x000000001)
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Flags_Definitions
- * @{
- */
-#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
-#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
-#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
-#define RTC_FLAG_TSF ((uint32_t)0x00000800)
-#define RTC_FLAG_WUTF ((uint32_t)0x00000400)
-#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)
-#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)
-#define RTC_FLAG_INITF ((uint32_t)0x00000040)
-#define RTC_FLAG_RSF ((uint32_t)0x00000020)
-#define RTC_FLAG_INITS ((uint32_t)0x00000010)
-#define RTC_FLAG_SHPF ((uint32_t)0x00000008)
-#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)
-#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)
-#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)
-#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
- ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
- ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
- ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
- ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
- ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \
- ((FLAG) == RTC_FLAG_SHPF))
-#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
-/**
- * @}
- */
-
-/** @defgroup RTC_Interrupts_Definitions
- * @{
- */
-#define RTC_IT_TS ((uint32_t)0x00008000)
-#define RTC_IT_WUT ((uint32_t)0x00004000)
-#define RTC_IT_ALRB ((uint32_t)0x00002000)
-#define RTC_IT_ALRA ((uint32_t)0x00001000)
-#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
-
-#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
-#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
- ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
- ((IT) == RTC_IT_TAMP1))
-#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Legacy
- * @{
- */
-#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig
-#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the RTC configuration to the default reset state *****/
-ErrorStatus RTC_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
-void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
-void RTC_WriteProtectionCmd(FunctionalState NewState);
-ErrorStatus RTC_EnterInitMode(void);
-void RTC_ExitInitMode(void);
-ErrorStatus RTC_WaitForSynchro(void);
-ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
-void RTC_BypassShadowCmd(FunctionalState NewState);
-
-/* Time and Date configuration functions **************************************/
-ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
-void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
-void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
-uint32_t RTC_GetSubSecond(void);
-ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
-void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
-void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
-
-/* Alarms (Alarm A and Alarm B) configuration functions **********************/
-void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
-void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
-void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
-ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
-void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
-uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
-
-/* WakeUp Timer configuration functions ***************************************/
-void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
-void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
-uint32_t RTC_GetWakeUpCounter(void);
-ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
-
-/* Daylight Saving configuration functions ************************************/
-void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
-uint32_t RTC_GetStoreOperation(void);
-
-/* Output pin Configuration function ******************************************/
-void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
-
-/* Digital Calibration configuration functions *********************************/
-ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);
-ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState);
-void RTC_CalibOutputCmd(FunctionalState NewState);
-void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
-ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
- uint32_t RTC_SmoothCalibPlusPulses,
- uint32_t RTC_SmouthCalibMinusPulsesValue);
-
-/* TimeStamp configuration functions ******************************************/
-void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
-void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
- RTC_DateTypeDef* RTC_StampDateStruct);
-uint32_t RTC_GetTimeStampSubSecond(void);
-
-/* Tampers configuration functions ********************************************/
-void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
-void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
-void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
-void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
-void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
-void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
-void RTC_TamperPullUpCmd(FunctionalState NewState);
-
-/* Backup Data Registers configuration functions ******************************/
-void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
-uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
-
-/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
- functions ******************************************************************/
-void RTC_TamperPinSelection(uint32_t RTC_TamperPin);
-void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin);
-void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
-
-/* RTC_Shift_control_synchonisation_functions *********************************/
-ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
-
-/* Interrupts and flags management functions **********************************/
-void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
-FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
-void RTC_ClearFlag(uint32_t RTC_FLAG);
-ITStatus RTC_GetITStatus(uint32_t RTC_IT);
-void RTC_ClearITPendingBit(uint32_t RTC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_RTC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_sdio.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the SDIO firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_SDIO_H
-#define __STM32F4xx_SDIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SDIO
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-typedef struct
-{
- uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref SDIO_Clock_Edge */
-
- uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
- enabled or disabled.
- This parameter can be a value of @ref SDIO_Clock_Bypass */
-
- uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
- disabled when the bus is idle.
- This parameter can be a value of @ref SDIO_Clock_Power_Save */
-
- uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
- This parameter can be a value of @ref SDIO_Bus_Wide */
-
- uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
- This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
-
- uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
- This parameter can be a value between 0x00 and 0xFF. */
-
-} SDIO_InitTypeDef;
-
-typedef struct
-{
- uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
- to a card as part of a command message. If a command
- contains an argument, it must be loaded into this register
- before writing the command to the command register */
-
- uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
-
- uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
- This parameter can be a value of @ref SDIO_Response_Type */
-
- uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
- This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
-
- uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
- is enabled or disabled.
- This parameter can be a value of @ref SDIO_CPSM_State */
-} SDIO_CmdInitTypeDef;
-
-typedef struct
-{
- uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
-
- uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
-
- uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
- This parameter can be a value of @ref SDIO_Data_Block_Size */
-
- uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
- is a read or write.
- This parameter can be a value of @ref SDIO_Transfer_Direction */
-
- uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
- This parameter can be a value of @ref SDIO_Transfer_Type */
-
- uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
- is enabled or disabled.
- This parameter can be a value of @ref SDIO_DPSM_State */
-} SDIO_DataInitTypeDef;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SDIO_Exported_Constants
- * @{
- */
-
-/** @defgroup SDIO_Clock_Edge
- * @{
- */
-
-#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
-#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
-#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
- ((EDGE) == SDIO_ClockEdge_Falling))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Clock_Bypass
- * @{
- */
-
-#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
-#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
-#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
- ((BYPASS) == SDIO_ClockBypass_Enable))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Clock_Power_Save
- * @{
- */
-
-#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
-#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
-#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
- ((SAVE) == SDIO_ClockPowerSave_Enable))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Bus_Wide
- * @{
- */
-
-#define SDIO_BusWide_1b ((uint32_t)0x00000000)
-#define SDIO_BusWide_4b ((uint32_t)0x00000800)
-#define SDIO_BusWide_8b ((uint32_t)0x00001000)
-#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
- ((WIDE) == SDIO_BusWide_8b))
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Hardware_Flow_Control
- * @{
- */
-
-#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
-#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
-#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
- ((CONTROL) == SDIO_HardwareFlowControl_Enable))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Power_State
- * @{
- */
-
-#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
-#define SDIO_PowerState_ON ((uint32_t)0x00000003)
-#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
-/**
- * @}
- */
-
-
-/** @defgroup SDIO_Interrupt_sources
- * @{
- */
-
-#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
-#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
-#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
-#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
-#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
-#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
-#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
-#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
-#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
-#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
-#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
-#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
-#define SDIO_IT_TXACT ((uint32_t)0x00001000)
-#define SDIO_IT_RXACT ((uint32_t)0x00002000)
-#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
-#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
-#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
-#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
-#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
-#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
-#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
-#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
-#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
-#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
-#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Command_Index
- * @{
- */
-
-#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
-/**
- * @}
- */
-
-/** @defgroup SDIO_Response_Type
- * @{
- */
-
-#define SDIO_Response_No ((uint32_t)0x00000000)
-#define SDIO_Response_Short ((uint32_t)0x00000040)
-#define SDIO_Response_Long ((uint32_t)0x000000C0)
-#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
- ((RESPONSE) == SDIO_Response_Short) || \
- ((RESPONSE) == SDIO_Response_Long))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Wait_Interrupt_State
- * @{
- */
-
-#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
-#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
-#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
-#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
- ((WAIT) == SDIO_Wait_Pend))
-/**
- * @}
- */
-
-/** @defgroup SDIO_CPSM_State
- * @{
- */
-
-#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
-#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
-#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Response_Registers
- * @{
- */
-
-#define SDIO_RESP1 ((uint32_t)0x00000000)
-#define SDIO_RESP2 ((uint32_t)0x00000004)
-#define SDIO_RESP3 ((uint32_t)0x00000008)
-#define SDIO_RESP4 ((uint32_t)0x0000000C)
-#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
- ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Data_Length
- * @{
- */
-
-#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
-/**
- * @}
- */
-
-/** @defgroup SDIO_Data_Block_Size
- * @{
- */
-
-#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
-#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
-#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
-#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
-#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
-#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
-#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
-#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
-#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
-#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
-#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
-#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
-#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
-#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
-#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
-#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
- ((SIZE) == SDIO_DataBlockSize_2b) || \
- ((SIZE) == SDIO_DataBlockSize_4b) || \
- ((SIZE) == SDIO_DataBlockSize_8b) || \
- ((SIZE) == SDIO_DataBlockSize_16b) || \
- ((SIZE) == SDIO_DataBlockSize_32b) || \
- ((SIZE) == SDIO_DataBlockSize_64b) || \
- ((SIZE) == SDIO_DataBlockSize_128b) || \
- ((SIZE) == SDIO_DataBlockSize_256b) || \
- ((SIZE) == SDIO_DataBlockSize_512b) || \
- ((SIZE) == SDIO_DataBlockSize_1024b) || \
- ((SIZE) == SDIO_DataBlockSize_2048b) || \
- ((SIZE) == SDIO_DataBlockSize_4096b) || \
- ((SIZE) == SDIO_DataBlockSize_8192b) || \
- ((SIZE) == SDIO_DataBlockSize_16384b))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Transfer_Direction
- * @{
- */
-
-#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
-#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
-#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
- ((DIR) == SDIO_TransferDir_ToSDIO))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Transfer_Type
- * @{
- */
-
-#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
-#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
-#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
- ((MODE) == SDIO_TransferMode_Block))
-/**
- * @}
- */
-
-/** @defgroup SDIO_DPSM_State
- * @{
- */
-
-#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
-#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
-#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Flags
- * @{
- */
-
-#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
-#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
-#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
-#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
-#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
-#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
-#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
-#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
-#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
-#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
-#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
-#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
-#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
-#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
-#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
-#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
-#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
-#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
-#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
-#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
-#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
-#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
-#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
-#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
-#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
- ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
- ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
- ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
- ((FLAG) == SDIO_FLAG_TXUNDERR) || \
- ((FLAG) == SDIO_FLAG_RXOVERR) || \
- ((FLAG) == SDIO_FLAG_CMDREND) || \
- ((FLAG) == SDIO_FLAG_CMDSENT) || \
- ((FLAG) == SDIO_FLAG_DATAEND) || \
- ((FLAG) == SDIO_FLAG_STBITERR) || \
- ((FLAG) == SDIO_FLAG_DBCKEND) || \
- ((FLAG) == SDIO_FLAG_CMDACT) || \
- ((FLAG) == SDIO_FLAG_TXACT) || \
- ((FLAG) == SDIO_FLAG_RXACT) || \
- ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
- ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
- ((FLAG) == SDIO_FLAG_TXFIFOF) || \
- ((FLAG) == SDIO_FLAG_RXFIFOF) || \
- ((FLAG) == SDIO_FLAG_TXFIFOE) || \
- ((FLAG) == SDIO_FLAG_RXFIFOE) || \
- ((FLAG) == SDIO_FLAG_TXDAVL) || \
- ((FLAG) == SDIO_FLAG_RXDAVL) || \
- ((FLAG) == SDIO_FLAG_SDIOIT) || \
- ((FLAG) == SDIO_FLAG_CEATAEND))
-
-#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
-
-#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
- ((IT) == SDIO_IT_DCRCFAIL) || \
- ((IT) == SDIO_IT_CTIMEOUT) || \
- ((IT) == SDIO_IT_DTIMEOUT) || \
- ((IT) == SDIO_IT_TXUNDERR) || \
- ((IT) == SDIO_IT_RXOVERR) || \
- ((IT) == SDIO_IT_CMDREND) || \
- ((IT) == SDIO_IT_CMDSENT) || \
- ((IT) == SDIO_IT_DATAEND) || \
- ((IT) == SDIO_IT_STBITERR) || \
- ((IT) == SDIO_IT_DBCKEND) || \
- ((IT) == SDIO_IT_CMDACT) || \
- ((IT) == SDIO_IT_TXACT) || \
- ((IT) == SDIO_IT_RXACT) || \
- ((IT) == SDIO_IT_TXFIFOHE) || \
- ((IT) == SDIO_IT_RXFIFOHF) || \
- ((IT) == SDIO_IT_TXFIFOF) || \
- ((IT) == SDIO_IT_RXFIFOF) || \
- ((IT) == SDIO_IT_TXFIFOE) || \
- ((IT) == SDIO_IT_RXFIFOE) || \
- ((IT) == SDIO_IT_TXDAVL) || \
- ((IT) == SDIO_IT_RXDAVL) || \
- ((IT) == SDIO_IT_SDIOIT) || \
- ((IT) == SDIO_IT_CEATAEND))
-
-#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Read_Wait_Mode
- * @{
- */
-
-#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000)
-#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001)
-#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
- ((MODE) == SDIO_ReadWaitMode_DATA2))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/* Function used to set the SDIO configuration to the default reset state ****/
-void SDIO_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
-void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
-void SDIO_ClockCmd(FunctionalState NewState);
-void SDIO_SetPowerState(uint32_t SDIO_PowerState);
-uint32_t SDIO_GetPowerState(void);
-
-/* Command path state machine (CPSM) management functions *********************/
-void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
-void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
-uint8_t SDIO_GetCommandResponse(void);
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
-
-/* Data path state machine (DPSM) management functions ************************/
-void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
-void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
-uint32_t SDIO_GetDataCounter(void);
-uint32_t SDIO_ReadData(void);
-void SDIO_WriteData(uint32_t Data);
-uint32_t SDIO_GetFIFOCount(void);
-
-/* SDIO IO Cards mode management functions ************************************/
-void SDIO_StartSDIOReadWait(FunctionalState NewState);
-void SDIO_StopSDIOReadWait(FunctionalState NewState);
-void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
-void SDIO_SetSDIOOperation(FunctionalState NewState);
-void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
-
-/* CE-ATA mode management functions *******************************************/
-void SDIO_CommandCompletionCmd(FunctionalState NewState);
-void SDIO_CEATAITCmd(FunctionalState NewState);
-void SDIO_SendCEATACmd(FunctionalState NewState);
-
-/* DMA transfers management functions *****************************************/
-void SDIO_DMACmd(FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
-FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
-void SDIO_ClearFlag(uint32_t SDIO_FLAG);
-ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
-void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_SDIO_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_spi.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the SPI
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_SPI_H
-#define __STM32F4xx_SPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SPI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief SPI Init structure definition
- */
-
-typedef struct
-{
- uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
- This parameter can be a value of @ref SPI_data_direction */
-
- uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
- This parameter can be a value of @ref SPI_mode */
-
- uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
- This parameter can be a value of @ref SPI_data_size */
-
- uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref SPI_Clock_Polarity */
-
- uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_Clock_Phase */
-
- uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
- hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref SPI_Slave_Select_management */
-
- uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
- used to configure the transmit and receive SCK clock.
- This parameter can be a value of @ref SPI_BaudRate_Prescaler
- @note The communication clock is derived from the master
- clock. The slave clock does not need to be set. */
-
- uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
- uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
-}SPI_InitTypeDef;
-
-/**
- * @brief I2S Init structure definition
- */
-
-typedef struct
-{
-
- uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
- This parameter can be a value of @ref I2S_Mode */
-
- uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
- This parameter can be a value of @ref I2S_Standard */
-
- uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
- This parameter can be a value of @ref I2S_Data_Format */
-
- uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
- This parameter can be a value of @ref I2S_MCLK_Output */
-
- uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
- This parameter can be a value of @ref I2S_Audio_Frequency */
-
- uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
- This parameter can be a value of @ref I2S_Clock_Polarity */
-}I2S_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SPI_Exported_Constants
- * @{
- */
-
-#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
- ((PERIPH) == SPI2) || \
- ((PERIPH) == SPI3))
-
-#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
- ((PERIPH) == SPI2) || \
- ((PERIPH) == SPI3) || \
- ((PERIPH) == I2S2ext) || \
- ((PERIPH) == I2S3ext))
-
-#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
- ((PERIPH) == SPI3))
-
-#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \
- ((PERIPH) == SPI3) || \
- ((PERIPH) == I2S2ext) || \
- ((PERIPH) == I2S3ext))
-
-#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \
- ((PERIPH) == I2S2ext))
-
-
-/** @defgroup SPI_data_direction
- * @{
- */
-
-#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
-#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
-#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
-#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
-#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
- ((MODE) == SPI_Direction_2Lines_RxOnly) || \
- ((MODE) == SPI_Direction_1Line_Rx) || \
- ((MODE) == SPI_Direction_1Line_Tx))
-/**
- * @}
- */
-
-/** @defgroup SPI_mode
- * @{
- */
-
-#define SPI_Mode_Master ((uint16_t)0x0104)
-#define SPI_Mode_Slave ((uint16_t)0x0000)
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
- ((MODE) == SPI_Mode_Slave))
-/**
- * @}
- */
-
-/** @defgroup SPI_data_size
- * @{
- */
-
-#define SPI_DataSize_16b ((uint16_t)0x0800)
-#define SPI_DataSize_8b ((uint16_t)0x0000)
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
- ((DATASIZE) == SPI_DataSize_8b))
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Polarity
- * @{
- */
-
-#define SPI_CPOL_Low ((uint16_t)0x0000)
-#define SPI_CPOL_High ((uint16_t)0x0002)
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
- ((CPOL) == SPI_CPOL_High))
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Phase
- * @{
- */
-
-#define SPI_CPHA_1Edge ((uint16_t)0x0000)
-#define SPI_CPHA_2Edge ((uint16_t)0x0001)
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
- ((CPHA) == SPI_CPHA_2Edge))
-/**
- * @}
- */
-
-/** @defgroup SPI_Slave_Select_management
- * @{
- */
-
-#define SPI_NSS_Soft ((uint16_t)0x0200)
-#define SPI_NSS_Hard ((uint16_t)0x0000)
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
- ((NSS) == SPI_NSS_Hard))
-/**
- * @}
- */
-
-/** @defgroup SPI_BaudRate_Prescaler
- * @{
- */
-
-#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
-#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
-#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
-#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
-#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
-#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
-#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
-#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_256))
-/**
- * @}
- */
-
-/** @defgroup SPI_MSB_LSB_transmission
- * @{
- */
-
-#define SPI_FirstBit_MSB ((uint16_t)0x0000)
-#define SPI_FirstBit_LSB ((uint16_t)0x0080)
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
- ((BIT) == SPI_FirstBit_LSB))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Mode
- * @{
- */
-
-#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
-#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
-#define I2S_Mode_MasterTx ((uint16_t)0x0200)
-#define I2S_Mode_MasterRx ((uint16_t)0x0300)
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
- ((MODE) == I2S_Mode_SlaveRx) || \
- ((MODE) == I2S_Mode_MasterTx)|| \
- ((MODE) == I2S_Mode_MasterRx))
-/**
- * @}
- */
-
-
-/** @defgroup SPI_I2S_Standard
- * @{
- */
-
-#define I2S_Standard_Phillips ((uint16_t)0x0000)
-#define I2S_Standard_MSB ((uint16_t)0x0010)
-#define I2S_Standard_LSB ((uint16_t)0x0020)
-#define I2S_Standard_PCMShort ((uint16_t)0x0030)
-#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
- ((STANDARD) == I2S_Standard_MSB) || \
- ((STANDARD) == I2S_Standard_LSB) || \
- ((STANDARD) == I2S_Standard_PCMShort) || \
- ((STANDARD) == I2S_Standard_PCMLong))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Data_Format
- * @{
- */
-
-#define I2S_DataFormat_16b ((uint16_t)0x0000)
-#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
-#define I2S_DataFormat_24b ((uint16_t)0x0003)
-#define I2S_DataFormat_32b ((uint16_t)0x0005)
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
- ((FORMAT) == I2S_DataFormat_16bextended) || \
- ((FORMAT) == I2S_DataFormat_24b) || \
- ((FORMAT) == I2S_DataFormat_32b))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_MCLK_Output
- * @{
- */
-
-#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
-#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
- ((OUTPUT) == I2S_MCLKOutput_Disable))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Audio_Frequency
- * @{
- */
-
-#define I2S_AudioFreq_192k ((uint32_t)192000)
-#define I2S_AudioFreq_96k ((uint32_t)96000)
-#define I2S_AudioFreq_48k ((uint32_t)48000)
-#define I2S_AudioFreq_44k ((uint32_t)44100)
-#define I2S_AudioFreq_32k ((uint32_t)32000)
-#define I2S_AudioFreq_22k ((uint32_t)22050)
-#define I2S_AudioFreq_16k ((uint32_t)16000)
-#define I2S_AudioFreq_11k ((uint32_t)11025)
-#define I2S_AudioFreq_8k ((uint32_t)8000)
-#define I2S_AudioFreq_Default ((uint32_t)2)
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
- ((FREQ) <= I2S_AudioFreq_192k)) || \
- ((FREQ) == I2S_AudioFreq_Default))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Clock_Polarity
- * @{
- */
-
-#define I2S_CPOL_Low ((uint16_t)0x0000)
-#define I2S_CPOL_High ((uint16_t)0x0008)
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
- ((CPOL) == I2S_CPOL_High))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_DMA_transfer_requests
- * @{
- */
-
-#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
-#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
-#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup SPI_NSS_internal_software_management
- * @{
- */
-
-#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
-#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
-#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
- ((INTERNAL) == SPI_NSSInternalSoft_Reset))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_Transmit_Receive
- * @{
- */
-
-#define SPI_CRC_Tx ((uint8_t)0x00)
-#define SPI_CRC_Rx ((uint8_t)0x01)
-#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
-/**
- * @}
- */
-
-/** @defgroup SPI_direction_transmit_receive
- * @{
- */
-
-#define SPI_Direction_Rx ((uint16_t)0xBFFF)
-#define SPI_Direction_Tx ((uint16_t)0x4000)
-#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
- ((DIRECTION) == SPI_Direction_Tx))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_interrupts_definition
- * @{
- */
-
-#define SPI_I2S_IT_TXE ((uint8_t)0x71)
-#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
-#define SPI_I2S_IT_ERR ((uint8_t)0x50)
-#define I2S_IT_UDR ((uint8_t)0x53)
-#define SPI_I2S_IT_TIFRFE ((uint8_t)0x58)
-
-#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
- ((IT) == SPI_I2S_IT_RXNE) || \
- ((IT) == SPI_I2S_IT_ERR))
-
-#define SPI_I2S_IT_OVR ((uint8_t)0x56)
-#define SPI_IT_MODF ((uint8_t)0x55)
-#define SPI_IT_CRCERR ((uint8_t)0x54)
-
-#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
-
-#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \
- ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \
- ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\
- ((IT) == SPI_I2S_IT_TIFRFE))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_flags_definition
- * @{
- */
-
-#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
-#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
-#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
-#define I2S_FLAG_UDR ((uint16_t)0x0008)
-#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
-#define SPI_FLAG_MODF ((uint16_t)0x0020)
-#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
-#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
-#define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100)
-
-#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
-#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
- ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
- ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
- ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
- ((FLAG) == SPI_I2S_FLAG_TIFRFE))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_polynomial
- * @{
- */
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Legacy
- * @{
- */
-
-#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx
-#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx
-#define SPI_IT_TXE SPI_I2S_IT_TXE
-#define SPI_IT_RXNE SPI_I2S_IT_RXNE
-#define SPI_IT_ERR SPI_I2S_IT_ERR
-#define SPI_IT_OVR SPI_I2S_IT_OVR
-#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE
-#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE
-#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR
-#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY
-#define SPI_DeInit SPI_I2S_DeInit
-#define SPI_ITConfig SPI_I2S_ITConfig
-#define SPI_DMACmd SPI_I2S_DMACmd
-#define SPI_SendData SPI_I2S_SendData
-#define SPI_ReceiveData SPI_I2S_ReceiveData
-#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus
-#define SPI_ClearFlag SPI_I2S_ClearFlag
-#define SPI_GetITStatus SPI_I2S_GetITStatus
-#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the SPI configuration to the default reset state *****/
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
-
-/* Initialization and Configuration functions *********************************/
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-
-void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);
-
-/* Data transfers functions ***************************************************/
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
-
-/* Hardware CRC Calculation functions *****************************************/
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_TransmitCRC(SPI_TypeDef* SPIx);
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
-
-/* DMA transfers management functions *****************************************/
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_SPI_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_syscfg.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the SYSCFG firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_SYSCFG_H
-#define __STM32F4xx_SYSCFG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SYSCFG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SYSCFG_Exported_Constants
- * @{
- */
-
-/** @defgroup SYSCFG_EXTI_Port_Sources
- * @{
- */
-#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
-#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
-#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
-#define EXTI_PortSourceGPIOD ((uint8_t)0x03)
-#define EXTI_PortSourceGPIOE ((uint8_t)0x04)
-#define EXTI_PortSourceGPIOF ((uint8_t)0x05)
-#define EXTI_PortSourceGPIOG ((uint8_t)0x06)
-#define EXTI_PortSourceGPIOH ((uint8_t)0x07)
-#define EXTI_PortSourceGPIOI ((uint8_t)0x08)
-
-#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOI))
-/**
- * @}
- */
-
-
-/** @defgroup SYSCFG_EXTI_Pin_Sources
- * @{
- */
-#define EXTI_PinSource0 ((uint8_t)0x00)
-#define EXTI_PinSource1 ((uint8_t)0x01)
-#define EXTI_PinSource2 ((uint8_t)0x02)
-#define EXTI_PinSource3 ((uint8_t)0x03)
-#define EXTI_PinSource4 ((uint8_t)0x04)
-#define EXTI_PinSource5 ((uint8_t)0x05)
-#define EXTI_PinSource6 ((uint8_t)0x06)
-#define EXTI_PinSource7 ((uint8_t)0x07)
-#define EXTI_PinSource8 ((uint8_t)0x08)
-#define EXTI_PinSource9 ((uint8_t)0x09)
-#define EXTI_PinSource10 ((uint8_t)0x0A)
-#define EXTI_PinSource11 ((uint8_t)0x0B)
-#define EXTI_PinSource12 ((uint8_t)0x0C)
-#define EXTI_PinSource13 ((uint8_t)0x0D)
-#define EXTI_PinSource14 ((uint8_t)0x0E)
-#define EXTI_PinSource15 ((uint8_t)0x0F)
-#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
- ((PINSOURCE) == EXTI_PinSource1) || \
- ((PINSOURCE) == EXTI_PinSource2) || \
- ((PINSOURCE) == EXTI_PinSource3) || \
- ((PINSOURCE) == EXTI_PinSource4) || \
- ((PINSOURCE) == EXTI_PinSource5) || \
- ((PINSOURCE) == EXTI_PinSource6) || \
- ((PINSOURCE) == EXTI_PinSource7) || \
- ((PINSOURCE) == EXTI_PinSource8) || \
- ((PINSOURCE) == EXTI_PinSource9) || \
- ((PINSOURCE) == EXTI_PinSource10) || \
- ((PINSOURCE) == EXTI_PinSource11) || \
- ((PINSOURCE) == EXTI_PinSource12) || \
- ((PINSOURCE) == EXTI_PinSource13) || \
- ((PINSOURCE) == EXTI_PinSource14) || \
- ((PINSOURCE) == EXTI_PinSource15))
-/**
- * @}
- */
-
-
-/** @defgroup SYSCFG_Memory_Remap_Config
- * @{
- */
-#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
-#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
-#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
-#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
-
-#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
- ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
- ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
- ((REMAP) == SYSCFG_MemoryRemap_FSMC))
-/**
- * @}
- */
-
-
-/** @defgroup SYSCFG_ETHERNET_Media_Interface
- * @{
- */
-#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000)
-#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001)
-
-#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \
- ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-void SYSCFG_DeInit(void);
-void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
-void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
-void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface);
-void SYSCFG_CompensationCellCmd(FunctionalState NewState);
-FlagStatus SYSCFG_GetCompensationCellStatus(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_SYSCFG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_tim.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the TIM firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_TIM_H
-#define __STM32F4xx_TIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup TIM
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief TIM Time Base Init structure definition
- * @note This structure is used with all TIMx except for TIM6 and TIM7.
- */
-
-typedef struct
-{
- uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between 0x0000 and 0xFFFF */
-
- uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref TIM_Counter_Mode */
-
- uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
- Auto-Reload Register at the next update event.
- This parameter must be a number between 0x0000 and 0xFFFF. */
-
- uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref TIM_Clock_Division_CKD */
-
- uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
- reaches zero, an update event is generated and counting restarts
- from the RCR value (N).
- This means in PWM mode that (N+1) corresponds to:
- - the number of PWM periods in edge-aligned mode
- - the number of half PWM period in center-aligned mode
- This parameter must be a number between 0x00 and 0xFF.
- @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_TimeBaseInitTypeDef;
-
-/**
- * @brief TIM Output Compare Init structure definition
- */
-
-typedef struct
-{
- uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
- uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
- This parameter can be a value of @ref TIM_Output_Compare_State */
-
- uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
- This parameter can be a value of @ref TIM_Output_Compare_N_State
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between 0x0000 and 0xFFFF */
-
- uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
- uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_OCInitTypeDef;
-
-/**
- * @brief TIM Input Capture Init structure definition
- */
-
-typedef struct
-{
-
- uint16_t TIM_Channel; /*!< Specifies the TIM channel.
- This parameter can be a value of @ref TIM_Channel */
-
- uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint16_t TIM_ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between 0x0 and 0xF */
-} TIM_ICInitTypeDef;
-
-/**
- * @brief BDTR structure definition
- * @note This structure is used only with TIM1 and TIM8.
- */
-
-typedef struct
-{
-
- uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
- This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
-
- uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
- This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
-
- uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
- This parameter can be a value of @ref TIM_Lock_level */
-
- uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
- switching-on of the outputs.
- This parameter can be a number between 0x00 and 0xFF */
-
- uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
- This parameter can be a value of @ref TIM_Break_Input_enable_disable */
-
- uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
- This parameter can be a value of @ref TIM_Break_Polarity */
-
- uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-} TIM_BDTRInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup TIM_Exported_constants
- * @{
- */
-
-#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM5) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM9) || \
- ((PERIPH) == TIM10) || \
- ((PERIPH) == TIM11) || \
- ((PERIPH) == TIM12) || \
- (((PERIPH) == TIM13) || \
- ((PERIPH) == TIM14)))
-/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */
-#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM5) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM9) || \
- ((PERIPH) == TIM10) || \
- ((PERIPH) == TIM11) || \
- ((PERIPH) == TIM12) || \
- ((PERIPH) == TIM13) || \
- ((PERIPH) == TIM14))
-
-/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */
-#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM5) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM9) || \
- ((PERIPH) == TIM12))
-/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */
-#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM5) || \
- ((PERIPH) == TIM8))
-/* LIST4: TIM1 and TIM8 */
-#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM8))
-/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
-#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM5) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM8))
-/* LIST6: TIM2, TIM5 and TIM11 */
-#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \
- ((TIMx) == TIM5) || \
- ((TIMx) == TIM11))
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes
- * @{
- */
-
-#define TIM_OCMode_Timing ((uint16_t)0x0000)
-#define TIM_OCMode_Active ((uint16_t)0x0010)
-#define TIM_OCMode_Inactive ((uint16_t)0x0020)
-#define TIM_OCMode_Toggle ((uint16_t)0x0030)
-#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
-#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
- ((MODE) == TIM_OCMode_Active) || \
- ((MODE) == TIM_OCMode_Inactive) || \
- ((MODE) == TIM_OCMode_Toggle)|| \
- ((MODE) == TIM_OCMode_PWM1) || \
- ((MODE) == TIM_OCMode_PWM2))
-#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
- ((MODE) == TIM_OCMode_Active) || \
- ((MODE) == TIM_OCMode_Inactive) || \
- ((MODE) == TIM_OCMode_Toggle)|| \
- ((MODE) == TIM_OCMode_PWM1) || \
- ((MODE) == TIM_OCMode_PWM2) || \
- ((MODE) == TIM_ForcedAction_Active) || \
- ((MODE) == TIM_ForcedAction_InActive))
-/**
- * @}
- */
-
-/** @defgroup TIM_One_Pulse_Mode
- * @{
- */
-
-#define TIM_OPMode_Single ((uint16_t)0x0008)
-#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
- ((MODE) == TIM_OPMode_Repetitive))
-/**
- * @}
- */
-
-/** @defgroup TIM_Channel
- * @{
- */
-
-#define TIM_Channel_1 ((uint16_t)0x0000)
-#define TIM_Channel_2 ((uint16_t)0x0004)
-#define TIM_Channel_3 ((uint16_t)0x0008)
-#define TIM_Channel_4 ((uint16_t)0x000C)
-
-#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2) || \
- ((CHANNEL) == TIM_Channel_3) || \
- ((CHANNEL) == TIM_Channel_4))
-
-#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2))
-#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2) || \
- ((CHANNEL) == TIM_Channel_3))
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Division_CKD
- * @{
- */
-
-#define TIM_CKD_DIV1 ((uint16_t)0x0000)
-#define TIM_CKD_DIV2 ((uint16_t)0x0100)
-#define TIM_CKD_DIV4 ((uint16_t)0x0200)
-#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
- ((DIV) == TIM_CKD_DIV2) || \
- ((DIV) == TIM_CKD_DIV4))
-/**
- * @}
- */
-
-/** @defgroup TIM_Counter_Mode
- * @{
- */
-
-#define TIM_CounterMode_Up ((uint16_t)0x0000)
-#define TIM_CounterMode_Down ((uint16_t)0x0010)
-#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
-#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
-#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
- ((MODE) == TIM_CounterMode_Down) || \
- ((MODE) == TIM_CounterMode_CenterAligned1) || \
- ((MODE) == TIM_CounterMode_CenterAligned2) || \
- ((MODE) == TIM_CounterMode_CenterAligned3))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Polarity
- * @{
- */
-
-#define TIM_OCPolarity_High ((uint16_t)0x0000)
-#define TIM_OCPolarity_Low ((uint16_t)0x0002)
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
- ((POLARITY) == TIM_OCPolarity_Low))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Polarity
- * @{
- */
-
-#define TIM_OCNPolarity_High ((uint16_t)0x0000)
-#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
- ((POLARITY) == TIM_OCNPolarity_Low))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_State
- * @{
- */
-
-#define TIM_OutputState_Disable ((uint16_t)0x0000)
-#define TIM_OutputState_Enable ((uint16_t)0x0001)
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
- ((STATE) == TIM_OutputState_Enable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_State
- * @{
- */
-
-#define TIM_OutputNState_Disable ((uint16_t)0x0000)
-#define TIM_OutputNState_Enable ((uint16_t)0x0004)
-#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
- ((STATE) == TIM_OutputNState_Enable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Capture_Compare_State
- * @{
- */
-
-#define TIM_CCx_Enable ((uint16_t)0x0001)
-#define TIM_CCx_Disable ((uint16_t)0x0000)
-#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
- ((CCX) == TIM_CCx_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Capture_Compare_N_State
- * @{
- */
-
-#define TIM_CCxN_Enable ((uint16_t)0x0004)
-#define TIM_CCxN_Disable ((uint16_t)0x0000)
-#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
- ((CCXN) == TIM_CCxN_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Input_enable_disable
- * @{
- */
-
-#define TIM_Break_Enable ((uint16_t)0x1000)
-#define TIM_Break_Disable ((uint16_t)0x0000)
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
- ((STATE) == TIM_Break_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Polarity
- * @{
- */
-
-#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
-#define TIM_BreakPolarity_High ((uint16_t)0x2000)
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
- ((POLARITY) == TIM_BreakPolarity_High))
-/**
- * @}
- */
-
-/** @defgroup TIM_AOE_Bit_Set_Reset
- * @{
- */
-
-#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
-#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
- ((STATE) == TIM_AutomaticOutput_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Lock_level
- * @{
- */
-
-#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
-#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
-#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
-#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
- ((LEVEL) == TIM_LOCKLevel_1) || \
- ((LEVEL) == TIM_LOCKLevel_2) || \
- ((LEVEL) == TIM_LOCKLevel_3))
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
- * @{
- */
-
-#define TIM_OSSIState_Enable ((uint16_t)0x0400)
-#define TIM_OSSIState_Disable ((uint16_t)0x0000)
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
- ((STATE) == TIM_OSSIState_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
- * @{
- */
-
-#define TIM_OSSRState_Enable ((uint16_t)0x0800)
-#define TIM_OSSRState_Disable ((uint16_t)0x0000)
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
- ((STATE) == TIM_OSSRState_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Idle_State
- * @{
- */
-
-#define TIM_OCIdleState_Set ((uint16_t)0x0100)
-#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
- ((STATE) == TIM_OCIdleState_Reset))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Idle_State
- * @{
- */
-
-#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
-#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
- ((STATE) == TIM_OCNIdleState_Reset))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Polarity
- * @{
- */
-
-#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
-#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
-#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
- ((POLARITY) == TIM_ICPolarity_Falling)|| \
- ((POLARITY) == TIM_ICPolarity_BothEdge))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Selection
- * @{
- */
-
-#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC2, IC1, IC4 or IC3, respectively. */
-#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
- ((SELECTION) == TIM_ICSelection_IndirectTI) || \
- ((SELECTION) == TIM_ICSelection_TRC))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Prescaler
- * @{
- */
-
-#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
-#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
-#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
-#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
- ((PRESCALER) == TIM_ICPSC_DIV2) || \
- ((PRESCALER) == TIM_ICPSC_DIV4) || \
- ((PRESCALER) == TIM_ICPSC_DIV8))
-/**
- * @}
- */
-
-/** @defgroup TIM_interrupt_sources
- * @{
- */
-
-#define TIM_IT_Update ((uint16_t)0x0001)
-#define TIM_IT_CC1 ((uint16_t)0x0002)
-#define TIM_IT_CC2 ((uint16_t)0x0004)
-#define TIM_IT_CC3 ((uint16_t)0x0008)
-#define TIM_IT_CC4 ((uint16_t)0x0010)
-#define TIM_IT_COM ((uint16_t)0x0020)
-#define TIM_IT_Trigger ((uint16_t)0x0040)
-#define TIM_IT_Break ((uint16_t)0x0080)
-#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
-
-#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
- ((IT) == TIM_IT_CC1) || \
- ((IT) == TIM_IT_CC2) || \
- ((IT) == TIM_IT_CC3) || \
- ((IT) == TIM_IT_CC4) || \
- ((IT) == TIM_IT_COM) || \
- ((IT) == TIM_IT_Trigger) || \
- ((IT) == TIM_IT_Break))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Base_address
- * @{
- */
-
-#define TIM_DMABase_CR1 ((uint16_t)0x0000)
-#define TIM_DMABase_CR2 ((uint16_t)0x0001)
-#define TIM_DMABase_SMCR ((uint16_t)0x0002)
-#define TIM_DMABase_DIER ((uint16_t)0x0003)
-#define TIM_DMABase_SR ((uint16_t)0x0004)
-#define TIM_DMABase_EGR ((uint16_t)0x0005)
-#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
-#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
-#define TIM_DMABase_CCER ((uint16_t)0x0008)
-#define TIM_DMABase_CNT ((uint16_t)0x0009)
-#define TIM_DMABase_PSC ((uint16_t)0x000A)
-#define TIM_DMABase_ARR ((uint16_t)0x000B)
-#define TIM_DMABase_RCR ((uint16_t)0x000C)
-#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
-#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
-#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
-#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
-#define TIM_DMABase_BDTR ((uint16_t)0x0011)
-#define TIM_DMABase_DCR ((uint16_t)0x0012)
-#define TIM_DMABase_OR ((uint16_t)0x0013)
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
- ((BASE) == TIM_DMABase_CR2) || \
- ((BASE) == TIM_DMABase_SMCR) || \
- ((BASE) == TIM_DMABase_DIER) || \
- ((BASE) == TIM_DMABase_SR) || \
- ((BASE) == TIM_DMABase_EGR) || \
- ((BASE) == TIM_DMABase_CCMR1) || \
- ((BASE) == TIM_DMABase_CCMR2) || \
- ((BASE) == TIM_DMABase_CCER) || \
- ((BASE) == TIM_DMABase_CNT) || \
- ((BASE) == TIM_DMABase_PSC) || \
- ((BASE) == TIM_DMABase_ARR) || \
- ((BASE) == TIM_DMABase_RCR) || \
- ((BASE) == TIM_DMABase_CCR1) || \
- ((BASE) == TIM_DMABase_CCR2) || \
- ((BASE) == TIM_DMABase_CCR3) || \
- ((BASE) == TIM_DMABase_CCR4) || \
- ((BASE) == TIM_DMABase_BDTR) || \
- ((BASE) == TIM_DMABase_DCR) || \
- ((BASE) == TIM_DMABase_OR))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Burst_Length
- * @{
- */
-
-#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
-#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
-#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
-#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
-#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
-#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
-#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
-#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
-#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
-#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
-#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
-#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
-#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
-#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
-#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
-#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
-#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
-#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
- ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_18Transfers))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_sources
- * @{
- */
-
-#define TIM_DMA_Update ((uint16_t)0x0100)
-#define TIM_DMA_CC1 ((uint16_t)0x0200)
-#define TIM_DMA_CC2 ((uint16_t)0x0400)
-#define TIM_DMA_CC3 ((uint16_t)0x0800)
-#define TIM_DMA_CC4 ((uint16_t)0x1000)
-#define TIM_DMA_COM ((uint16_t)0x2000)
-#define TIM_DMA_Trigger ((uint16_t)0x4000)
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Prescaler
- * @{
- */
-
-#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
-#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
-#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
-#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
-#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
-/**
- * @}
- */
-
-/** @defgroup TIM_Internal_Trigger_Selection
- * @{
- */
-
-#define TIM_TS_ITR0 ((uint16_t)0x0000)
-#define TIM_TS_ITR1 ((uint16_t)0x0010)
-#define TIM_TS_ITR2 ((uint16_t)0x0020)
-#define TIM_TS_ITR3 ((uint16_t)0x0030)
-#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
-#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
-#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
-#define TIM_TS_ETRF ((uint16_t)0x0070)
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_TI1F_ED) || \
- ((SELECTION) == TIM_TS_TI1FP1) || \
- ((SELECTION) == TIM_TS_TI2FP2) || \
- ((SELECTION) == TIM_TS_ETRF))
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3))
-/**
- * @}
- */
-
-/** @defgroup TIM_TIx_External_Clock_Source
- * @{
- */
-
-#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
-#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
-#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Polarity
- * @{
- */
-#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
-#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
-#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
- ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
-/**
- * @}
- */
-
-/** @defgroup TIM_Prescaler_Reload_Mode
- * @{
- */
-
-#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
-#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
-#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
- ((RELOAD) == TIM_PSCReloadMode_Immediate))
-/**
- * @}
- */
-
-/** @defgroup TIM_Forced_Action
- * @{
- */
-
-#define TIM_ForcedAction_Active ((uint16_t)0x0050)
-#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
-#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
- ((ACTION) == TIM_ForcedAction_InActive))
-/**
- * @}
- */
-
-/** @defgroup TIM_Encoder_Mode
- * @{
- */
-
-#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
-#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
-#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
- ((MODE) == TIM_EncoderMode_TI2) || \
- ((MODE) == TIM_EncoderMode_TI12))
-/**
- * @}
- */
-
-
-/** @defgroup TIM_Event_Source
- * @{
- */
-
-#define TIM_EventSource_Update ((uint16_t)0x0001)
-#define TIM_EventSource_CC1 ((uint16_t)0x0002)
-#define TIM_EventSource_CC2 ((uint16_t)0x0004)
-#define TIM_EventSource_CC3 ((uint16_t)0x0008)
-#define TIM_EventSource_CC4 ((uint16_t)0x0010)
-#define TIM_EventSource_COM ((uint16_t)0x0020)
-#define TIM_EventSource_Trigger ((uint16_t)0x0040)
-#define TIM_EventSource_Break ((uint16_t)0x0080)
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Update_Source
- * @{
- */
-
-#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
- or the setting of UG bit, or an update generation
- through the slave mode controller. */
-#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
-#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
- ((SOURCE) == TIM_UpdateSource_Regular))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Preload_State
- * @{
- */
-
-#define TIM_OCPreload_Enable ((uint16_t)0x0008)
-#define TIM_OCPreload_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
- ((STATE) == TIM_OCPreload_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Fast_State
- * @{
- */
-
-#define TIM_OCFast_Enable ((uint16_t)0x0004)
-#define TIM_OCFast_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
- ((STATE) == TIM_OCFast_Disable))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Clear_State
- * @{
- */
-
-#define TIM_OCClear_Enable ((uint16_t)0x0080)
-#define TIM_OCClear_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
- ((STATE) == TIM_OCClear_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Output_Source
- * @{
- */
-
-#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
-#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
-#define TIM_TRGOSource_Update ((uint16_t)0x0020)
-#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
-#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
-#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
-#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
-#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
- ((SOURCE) == TIM_TRGOSource_Enable) || \
- ((SOURCE) == TIM_TRGOSource_Update) || \
- ((SOURCE) == TIM_TRGOSource_OC1) || \
- ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC4Ref))
-/**
- * @}
- */
-
-/** @defgroup TIM_Slave_Mode
- * @{
- */
-
-#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
-#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
-#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
-#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
- ((MODE) == TIM_SlaveMode_Gated) || \
- ((MODE) == TIM_SlaveMode_Trigger) || \
- ((MODE) == TIM_SlaveMode_External1))
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Slave_Mode
- * @{
- */
-
-#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
-#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
- ((STATE) == TIM_MasterSlaveMode_Disable))
-/**
- * @}
- */
-/** @defgroup TIM_Remap
- * @{
- */
-
-#define TIM2_TIM8_TRGO ((uint16_t)0x0000)
-#define TIM2_ETH_PTP ((uint16_t)0x0400)
-#define TIM2_USBFS_SOF ((uint16_t)0x0800)
-#define TIM2_USBHS_SOF ((uint16_t)0x0C00)
-
-#define TIM5_GPIO ((uint16_t)0x0000)
-#define TIM5_LSI ((uint16_t)0x0040)
-#define TIM5_LSE ((uint16_t)0x0080)
-#define TIM5_RTC ((uint16_t)0x00C0)
-
-#define TIM11_GPIO ((uint16_t)0x0000)
-#define TIM11_HSE ((uint16_t)0x0002)
-
-#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\
- ((TIM_REMAP) == TIM2_ETH_PTP)||\
- ((TIM_REMAP) == TIM2_USBFS_SOF)||\
- ((TIM_REMAP) == TIM2_USBHS_SOF)||\
- ((TIM_REMAP) == TIM5_GPIO)||\
- ((TIM_REMAP) == TIM5_LSI)||\
- ((TIM_REMAP) == TIM5_LSE)||\
- ((TIM_REMAP) == TIM5_RTC)||\
- ((TIM_REMAP) == TIM11_GPIO)||\
- ((TIM_REMAP) == TIM11_HSE))
-
-/**
- * @}
- */
-/** @defgroup TIM_Flags
- * @{
- */
-
-#define TIM_FLAG_Update ((uint16_t)0x0001)
-#define TIM_FLAG_CC1 ((uint16_t)0x0002)
-#define TIM_FLAG_CC2 ((uint16_t)0x0004)
-#define TIM_FLAG_CC3 ((uint16_t)0x0008)
-#define TIM_FLAG_CC4 ((uint16_t)0x0010)
-#define TIM_FLAG_COM ((uint16_t)0x0020)
-#define TIM_FLAG_Trigger ((uint16_t)0x0040)
-#define TIM_FLAG_Break ((uint16_t)0x0080)
-#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
-#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
-#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
-#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
-#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
- ((FLAG) == TIM_FLAG_CC1) || \
- ((FLAG) == TIM_FLAG_CC2) || \
- ((FLAG) == TIM_FLAG_CC3) || \
- ((FLAG) == TIM_FLAG_CC4) || \
- ((FLAG) == TIM_FLAG_COM) || \
- ((FLAG) == TIM_FLAG_Trigger) || \
- ((FLAG) == TIM_FLAG_Break) || \
- ((FLAG) == TIM_FLAG_CC1OF) || \
- ((FLAG) == TIM_FLAG_CC2OF) || \
- ((FLAG) == TIM_FLAG_CC3OF) || \
- ((FLAG) == TIM_FLAG_CC4OF))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Filer_Value
- * @{
- */
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Filter
- * @{
- */
-
-#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_Legacy
- * @{
- */
-
-#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
-#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
-#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
-#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
-#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
-#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
-#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
-#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
-#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
-#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
-#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
-#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
-#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
-#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
-#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
-#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
-#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
-#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* TimeBase management ********************************************************/
-void TIM_DeInit(TIM_TypeDef* TIMx);
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Output Compare management **************************************************/
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
-
-/* Input Capture management ***************************************************/
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-
-/* Advanced-control timers (TIM1 and TIM8) specific features ******************/
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Interrupts, DMA and flags management ***************************************/
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Clocks management **********************************************************/
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
- uint16_t TIM_ICPolarity, uint16_t ICFilter);
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
-
-/* Synchronization management *************************************************/
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
-
-/* Specific interface management **********************************************/
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Specific remapping management **********************************************/
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_TIM_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_usart.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the USART
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_USART_H
-#define __STM32F4xx_USART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup USART
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief USART Init Structure definition
- */
-
-typedef struct
-{
- uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
- The baud rate is computed using the following formula:
- - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))
- - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
- Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
-
- uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref USART_Word_Length */
-
- uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref USART_Stop_Bits */
-
- uint16_t USART_Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref USART_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref USART_Mode */
-
- uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
- or disabled.
- This parameter can be a value of @ref USART_Hardware_Flow_Control */
-} USART_InitTypeDef;
-
-/**
- * @brief USART Clock Init Structure definition
- */
-
-typedef struct
-{
-
- uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
- This parameter can be a value of @ref USART_Clock */
-
- uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref USART_Clock_Polarity */
-
- uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref USART_Clock_Phase */
-
- uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref USART_Last_Bit */
-} USART_ClockInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup USART_Exported_Constants
- * @{
- */
-
-#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
- ((PERIPH) == USART2) || \
- ((PERIPH) == USART3) || \
- ((PERIPH) == UART4) || \
- ((PERIPH) == UART5) || \
- ((PERIPH) == USART6))
-
-#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \
- ((PERIPH) == USART2) || \
- ((PERIPH) == USART3) || \
- ((PERIPH) == USART6))
-
-/** @defgroup USART_Word_Length
- * @{
- */
-
-#define USART_WordLength_8b ((uint16_t)0x0000)
-#define USART_WordLength_9b ((uint16_t)0x1000)
-
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
- ((LENGTH) == USART_WordLength_9b))
-/**
- * @}
- */
-
-/** @defgroup USART_Stop_Bits
- * @{
- */
-
-#define USART_StopBits_1 ((uint16_t)0x0000)
-#define USART_StopBits_0_5 ((uint16_t)0x1000)
-#define USART_StopBits_2 ((uint16_t)0x2000)
-#define USART_StopBits_1_5 ((uint16_t)0x3000)
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
- ((STOPBITS) == USART_StopBits_0_5) || \
- ((STOPBITS) == USART_StopBits_2) || \
- ((STOPBITS) == USART_StopBits_1_5))
-/**
- * @}
- */
-
-/** @defgroup USART_Parity
- * @{
- */
-
-#define USART_Parity_No ((uint16_t)0x0000)
-#define USART_Parity_Even ((uint16_t)0x0400)
-#define USART_Parity_Odd ((uint16_t)0x0600)
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
- ((PARITY) == USART_Parity_Even) || \
- ((PARITY) == USART_Parity_Odd))
-/**
- * @}
- */
-
-/** @defgroup USART_Mode
- * @{
- */
-
-#define USART_Mode_Rx ((uint16_t)0x0004)
-#define USART_Mode_Tx ((uint16_t)0x0008)
-#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
-/**
- * @}
- */
-
-/** @defgroup USART_Hardware_Flow_Control
- * @{
- */
-#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
-#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
-#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
-#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
-#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
- (((CONTROL) == USART_HardwareFlowControl_None) || \
- ((CONTROL) == USART_HardwareFlowControl_RTS) || \
- ((CONTROL) == USART_HardwareFlowControl_CTS) || \
- ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
-/**
- * @}
- */
-
-/** @defgroup USART_Clock
- * @{
- */
-#define USART_Clock_Disable ((uint16_t)0x0000)
-#define USART_Clock_Enable ((uint16_t)0x0800)
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
- ((CLOCK) == USART_Clock_Enable))
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Polarity
- * @{
- */
-
-#define USART_CPOL_Low ((uint16_t)0x0000)
-#define USART_CPOL_High ((uint16_t)0x0400)
-#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
-
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Phase
- * @{
- */
-
-#define USART_CPHA_1Edge ((uint16_t)0x0000)
-#define USART_CPHA_2Edge ((uint16_t)0x0200)
-#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
-
-/**
- * @}
- */
-
-/** @defgroup USART_Last_Bit
- * @{
- */
-
-#define USART_LastBit_Disable ((uint16_t)0x0000)
-#define USART_LastBit_Enable ((uint16_t)0x0100)
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
- ((LASTBIT) == USART_LastBit_Enable))
-/**
- * @}
- */
-
-/** @defgroup USART_Interrupt_definition
- * @{
- */
-
-#define USART_IT_PE ((uint16_t)0x0028)
-#define USART_IT_TXE ((uint16_t)0x0727)
-#define USART_IT_TC ((uint16_t)0x0626)
-#define USART_IT_RXNE ((uint16_t)0x0525)
-#define USART_IT_IDLE ((uint16_t)0x0424)
-#define USART_IT_LBD ((uint16_t)0x0846)
-#define USART_IT_CTS ((uint16_t)0x096A)
-#define USART_IT_ERR ((uint16_t)0x0060)
-#define USART_IT_ORE ((uint16_t)0x0360)
-#define USART_IT_NE ((uint16_t)0x0260)
-#define USART_IT_FE ((uint16_t)0x0160)
-#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
-#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
- ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
-#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
- ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
-/**
- * @}
- */
-
-/** @defgroup USART_DMA_Requests
- * @{
- */
-
-#define USART_DMAReq_Tx ((uint16_t)0x0080)
-#define USART_DMAReq_Rx ((uint16_t)0x0040)
-#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
-
-/**
- * @}
- */
-
-/** @defgroup USART_WakeUp_methods
- * @{
- */
-
-#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
-#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
-#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
- ((WAKEUP) == USART_WakeUp_AddressMark))
-/**
- * @}
- */
-
-/** @defgroup USART_LIN_Break_Detection_Length
- * @{
- */
-
-#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
-#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
-#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
- (((LENGTH) == USART_LINBreakDetectLength_10b) || \
- ((LENGTH) == USART_LINBreakDetectLength_11b))
-/**
- * @}
- */
-
-/** @defgroup USART_IrDA_Low_Power
- * @{
- */
-
-#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
-#define USART_IrDAMode_Normal ((uint16_t)0x0000)
-#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
- ((MODE) == USART_IrDAMode_Normal))
-/**
- * @}
- */
-
-/** @defgroup USART_Flags
- * @{
- */
-
-#define USART_FLAG_CTS ((uint16_t)0x0200)
-#define USART_FLAG_LBD ((uint16_t)0x0100)
-#define USART_FLAG_TXE ((uint16_t)0x0080)
-#define USART_FLAG_TC ((uint16_t)0x0040)
-#define USART_FLAG_RXNE ((uint16_t)0x0020)
-#define USART_FLAG_IDLE ((uint16_t)0x0010)
-#define USART_FLAG_ORE ((uint16_t)0x0008)
-#define USART_FLAG_NE ((uint16_t)0x0004)
-#define USART_FLAG_FE ((uint16_t)0x0002)
-#define USART_FLAG_PE ((uint16_t)0x0001)
-#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
- ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
- ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
- ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
- ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
-
-#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
-
-#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001))
-#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
-#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the USART configuration to the default reset state ***/
-void USART_DeInit(USART_TypeDef* USARTx);
-
-/* Initialization and Configuration functions *********************************/
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* Data transfers functions ***************************************************/
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
-
-/* Multi-Processor Communication functions ************************************/
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* LIN mode functions *********************************************************/
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SendBreak(USART_TypeDef* USARTx);
-
-/* Half-duplex mode function **************************************************/
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* Smartcard mode functions ***************************************************/
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
-
-/* IrDA mode functions ********************************************************/
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* DMA transfers management functions *****************************************/
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_USART_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_wwdg.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file contains all the functions prototypes for the WWDG firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_WWDG_H
-#define __STM32F4xx_WWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup WWDG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Constants
- * @{
- */
-
-/** @defgroup WWDG_Prescaler
- * @{
- */
-
-#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
-#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
-#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
-#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
-#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
- ((PRESCALER) == WWDG_Prescaler_2) || \
- ((PRESCALER) == WWDG_Prescaler_4) || \
- ((PRESCALER) == WWDG_Prescaler_8))
-#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
-#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the WWDG configuration to the default reset state ****/
-void WWDG_DeInit(void);
-
-/* Prescaler, Refresh window and Counter configuration functions **************/
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
-void WWDG_SetWindowValue(uint8_t WindowValue);
-void WWDG_EnableIT(void);
-void WWDG_SetCounter(uint8_t Counter);
-
-/* WWDG activation function ***************************************************/
-void WWDG_Enable(uint8_t Counter);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus WWDG_GetFlagStatus(void);
-void WWDG_ClearFlag(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_WWDG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file misc.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides all the miscellaneous firmware functions (add-on
- * to CMSIS functions).
- *
- * @verbatim
- *
- * ===================================================================
- * How to configure Interrupts using driver
- * ===================================================================
- *
- * This section provide functions allowing to configure the NVIC interrupts (IRQ).
- * The Cortex-M4 exceptions are managed by CMSIS functions.
- *
- * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
- * function according to the following table.
-
- * The table below gives the allowed values of the pre-emption priority and subpriority according
- * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
- * ==========================================================================================================================
- * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
- * ==========================================================================================================================
- * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
- * | | | 4 bits for subpriority
- * --------------------------------------------------------------------------------------------------------------------------
- * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
- * | | | 3 bits for subpriority
- * --------------------------------------------------------------------------------------------------------------------------
- * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
- * | | | 2 bits for subpriority
- * --------------------------------------------------------------------------------------------------------------------------
- * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
- * | | | 1 bits for subpriority
- * --------------------------------------------------------------------------------------------------------------------------
- * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
- * | | | 0 bits for subpriority
- * ==========================================================================================================================
- *
- * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init()
- *
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
- * The pending IRQ priority will be managed only by the subpriority.
- *
- * @note IRQ priority order (sorted by highest to lowest priority):
- * - Lowest pre-emption priority
- * - Lowest subpriority
- * - Lowest hardware priority (IRQ number)
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "misc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup MISC
- * @brief MISC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup MISC_Private_Functions
- * @{
- */
-
-/**
- * @brief Configures the priority grouping: pre-emption priority and subpriority.
- * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
- * This parameter can be one of the following values:
- * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
- * 4 bits for subpriority
- * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
- * 3 bits for subpriority
- * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
- * 2 bits for subpriority
- * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
- * 1 bits for subpriority
- * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
- * 0 bits for subpriority
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
- * The pending IRQ priority will be managed only by the subpriority.
- * @retval None
- */
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
-
- /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
- SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
-}
-
-/**
- * @brief Initializes the NVIC peripheral according to the specified
- * parameters in the NVIC_InitStruct.
- * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
- * function should be called before.
- * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
- * the configuration information for the specified NVIC peripheral.
- * @retval None
- */
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
-{
- uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
- assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
-
- if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
- {
- /* Compute the Corresponding IRQ Priority --------------------------------*/
- tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
- tmppre = (0x4 - tmppriority);
- tmpsub = tmpsub >> tmppriority;
-
- tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
- tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
-
- tmppriority = tmppriority << 0x04;
-
- NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
-
- /* Enable the Selected IRQ Channels --------------------------------------*/
- NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
- }
- else
- {
- /* Disable the Selected IRQ Channels -------------------------------------*/
- NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
- }
-}
-
-/**
- * @brief Sets the vector table location and Offset.
- * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
- * This parameter can be one of the following values:
- * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
- * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
- * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
- * @retval None
- */
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
- assert_param(IS_NVIC_OFFSET(Offset));
-
- SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
-}
-
-/**
- * @brief Selects the condition for the system to enter low power mode.
- * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
- * This parameter can be one of the following values:
- * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
- * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
- * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
- * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_LP(LowPowerMode));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- SCB->SCR |= LowPowerMode;
- }
- else
- {
- SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
- }
-}
-
-/**
- * @brief Configures the SysTick clock source.
- * @param SysTick_CLKSource: specifies the SysTick clock source.
- * This parameter can be one of the following values:
- * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
- * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
- * @retval None
- */
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
-{
- /* Check the parameters */
- assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
- if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
- {
- SysTick->CTRL |= SysTick_CLKSource_HCLK;
- }
- else
- {
- SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_adc.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC) peripheral:
- * - Initialization and Configuration (in addition to ADC multi mode
- * selection)
- * - Analog Watchdog configuration
- * - Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT
- * management
- * - Regular Channels Configuration
- * - Regular Channels DMA Configuration
- * - Injected channels Configuration
- * - Interrupts and flags management
- *
- * @verbatim
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
-
- * 1. Enable the ADC interface clock using
- * RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE);
- *
- * 2. ADC pins configuration
- * - Enable the clock for the ADC GPIOs using the following function:
- * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
- * - Configure these ADC pins in analog mode using GPIO_Init();
- *
- * 3. Configure the ADC Prescaler, conversion resolution and data
- * alignment using the ADC_Init() function.
- * 4. Activate the ADC peripheral using ADC_Cmd() function.
- *
- * Regular channels group configuration
- * ====================================
- * - To configure the ADC regular channels group features, use
- * ADC_Init() and ADC_RegularChannelConfig() functions.
- * - To activate the continuous mode, use the ADC_continuousModeCmd()
- * function.
- * - To configurate and activate the Discontinuous mode, use the
- * ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
- * - To read the ADC converted values, use the ADC_GetConversionValue()
- * function.
- *
- * Multi mode ADCs Regular channels configuration
- * ===============================================
- * - Refer to "Regular channels group configuration" description to
- * configure the ADC1, ADC2 and ADC3 regular channels.
- * - Select the Multi mode ADC regular channels features (dual or
- * triple mode) using ADC_CommonInit() function and configure
- * the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd()
- * functions.
- * - Read the ADCs converted values using the
- * ADC_GetMultiModeConversionValue() function.
- *
- * DMA for Regular channels group features configuration
- * ======================================================
- * - To enable the DMA mode for regular channels group, use the
- * ADC_DMACmd() function.
- * - To enable the generation of DMA requests continuously at the end
- * of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd()
- * function.
- *
- * Injected channels group configuration
- * =====================================
- * - To configure the ADC Injected channels group features, use
- * ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()
- * functions.
- * - To activate the continuous mode, use the ADC_continuousModeCmd()
- * function.
- * - To activate the Injected Discontinuous mode, use the
- * ADC_InjectedDiscModeCmd() function.
- * - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd()
- * function.
- * - To read the ADC converted values, use the ADC_GetInjectedConversionValue()
- * function.
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_adc.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup ADC
- * @brief ADC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ADC DISCNUM mask */
-#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)
-
-/* ADC AWDCH mask */
-#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0)
-
-/* ADC Analog watchdog enable mode mask */
-#define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF)
-
-/* CR1 register Mask */
-#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF)
-
-/* ADC EXTEN mask */
-#define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF)
-
-/* ADC JEXTEN mask */
-#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)
-
-/* ADC JEXTSEL mask */
-#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)
-
-/* CR2 register Mask */
-#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)
-
-/* ADC SQx mask */
-#define SQR3_SQ_SET ((uint32_t)0x0000001F)
-#define SQR2_SQ_SET ((uint32_t)0x0000001F)
-#define SQR1_SQ_SET ((uint32_t)0x0000001F)
-
-/* ADC L Mask */
-#define SQR1_L_RESET ((uint32_t)0xFF0FFFFF)
-
-/* ADC JSQx mask */
-#define JSQR_JSQ_SET ((uint32_t)0x0000001F)
-
-/* ADC JL mask */
-#define JSQR_JL_SET ((uint32_t)0x00300000)
-#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF)
-
-/* ADC SMPx mask */
-#define SMPR1_SMP_SET ((uint32_t)0x00000007)
-#define SMPR2_SMP_SET ((uint32_t)0x00000007)
-
-/* ADC JDRx registers offset */
-#define JDR_OFFSET ((uint8_t)0x28)
-
-/* ADC CDR register base address */
-#define CDR_ADDRESS ((uint32_t)0x40012308)
-
-/* ADC CCR register Mask */
-#define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Functions
- * @{
- */
-
-/** @defgroup ADC_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- Initialization and Configuration functions
- ===============================================================================
- This section provides functions allowing to:
- - Initialize and configure the ADC Prescaler
- - ADC Conversion Resolution (12bit..6bit)
- - Scan Conversion Mode (multichannels or one channel) for regular group
- - ADC Continuous Conversion Mode (Continuous or Single conversion) for
- regular group
- - External trigger Edge and source of regular group,
- - Converted data alignment (left or right)
- - The number of ADC conversions that will be done using the sequencer for
- regular channel group
- - Multi ADC mode selection
- - Direct memory access mode selection for multi ADC mode
- - Delay between 2 sampling phases (used in dual or triple interleaved modes)
- - Enable or disable the ADC peripheral
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes all ADCs peripherals registers to their default reset
- * values.
- * @param None
- * @retval None
- */
-void ADC_DeInit(void)
-{
- /* Enable all ADCs reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE);
-
- /* Release all ADCs from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE);
-}
-
-/**
- * @brief Initializes the ADCx peripheral according to the specified parameters
- * in the ADC_InitStruct.
- * @note This function is used to configure the global features of the ADC (
- * Resolution and Data Alignment), however, the rest of the configuration
- * parameters are specific to the regular channels group (scan mode
- * activation, continuous mode activation, External trigger source and
- * edge, number of conversion in the regular channels group sequencer).
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
- * the configuration information for the specified ADC peripheral.
- * @retval None
- */
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
-{
- uint32_t tmpreg1 = 0;
- uint8_t tmpreg2 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
- assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge));
- assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
- assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
- assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));
-
- /*---------------------------- ADCx CR1 Configuration -----------------*/
- /* Get the ADCx CR1 value */
- tmpreg1 = ADCx->CR1;
-
- /* Clear RES and SCAN bits */
- tmpreg1 &= CR1_CLEAR_MASK;
-
- /* Configure ADCx: scan conversion mode and resolution */
- /* Set SCAN bit according to ADC_ScanConvMode value */
- /* Set RES bit according to ADC_Resolution value */
- tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \
- ADC_InitStruct->ADC_Resolution);
- /* Write to ADCx CR1 */
- ADCx->CR1 = tmpreg1;
- /*---------------------------- ADCx CR2 Configuration -----------------*/
- /* Get the ADCx CR2 value */
- tmpreg1 = ADCx->CR2;
-
- /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */
- tmpreg1 &= CR2_CLEAR_MASK;
-
- /* Configure ADCx: external trigger event and edge, data alignment and
- continuous conversion mode */
- /* Set ALIGN bit according to ADC_DataAlign value */
- /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */
- /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
- /* Set CONT bit according to ADC_ContinuousConvMode value */
- tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \
- ADC_InitStruct->ADC_ExternalTrigConv |
- ADC_InitStruct->ADC_ExternalTrigConvEdge | \
- ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
-
- /* Write to ADCx CR2 */
- ADCx->CR2 = tmpreg1;
- /*---------------------------- ADCx SQR1 Configuration -----------------*/
- /* Get the ADCx SQR1 value */
- tmpreg1 = ADCx->SQR1;
-
- /* Clear L bits */
- tmpreg1 &= SQR1_L_RESET;
-
- /* Configure ADCx: regular channel sequence length */
- /* Set L bits according to ADC_NbrOfConversion value */
- tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);
- tmpreg1 |= ((uint32_t)tmpreg2 << 20);
-
- /* Write to ADCx SQR1 */
- ADCx->SQR1 = tmpreg1;
-}
-
-/**
- * @brief Fills each ADC_InitStruct member with its default value.
- * @note This function is used to initialize the global features of the ADC (
- * Resolution and Data Alignment), however, the rest of the configuration
- * parameters are specific to the regular channels group (scan mode
- * activation, continuous mode activation, External trigger source and
- * edge, number of conversion in the regular channels group sequencer).
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
-{
- /* Initialize the ADC_Mode member */
- ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
-
- /* initialize the ADC_ScanConvMode member */
- ADC_InitStruct->ADC_ScanConvMode = DISABLE;
-
- /* Initialize the ADC_ContinuousConvMode member */
- ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
-
- /* Initialize the ADC_ExternalTrigConvEdge member */
- ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
-
- /* Initialize the ADC_ExternalTrigConv member */
- ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
-
- /* Initialize the ADC_DataAlign member */
- ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
-
- /* Initialize the ADC_NbrOfConversion member */
- ADC_InitStruct->ADC_NbrOfConversion = 1;
-}
-
-/**
- * @brief Initializes the ADCs peripherals according to the specified parameters
- * in the ADC_CommonInitStruct.
- * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
- * that contains the configuration information for All ADCs peripherals.
- * @retval None
- */
-void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
-{
- uint32_t tmpreg1 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode));
- assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));
- assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode));
- assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay));
- /*---------------------------- ADC CCR Configuration -----------------*/
- /* Get the ADC CCR value */
- tmpreg1 = ADC->CCR;
-
- /* Clear MULTI, DELAY, DMA and ADCPRE bits */
- tmpreg1 &= CR_CLEAR_MASK;
-
- /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler,
- and DMA access mode for multimode */
- /* Set MULTI bits according to ADC_Mode value */
- /* Set ADCPRE bits according to ADC_Prescaler value */
- /* Set DMA bits according to ADC_DMAAccessMode value */
- /* Set DELAY bits according to ADC_TwoSamplingDelay value */
- tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode |
- ADC_CommonInitStruct->ADC_Prescaler |
- ADC_CommonInitStruct->ADC_DMAAccessMode |
- ADC_CommonInitStruct->ADC_TwoSamplingDelay);
-
- /* Write to ADC CCR */
- ADC->CCR = tmpreg1;
-}
-
-/**
- * @brief Fills each ADC_CommonInitStruct member with its default value.
- * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
-{
- /* Initialize the ADC_Mode member */
- ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent;
-
- /* initialize the ADC_Prescaler member */
- ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2;
-
- /* Initialize the ADC_DMAAccessMode member */
- ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
-
- /* Initialize the ADC_TwoSamplingDelay member */
- ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
-}
-
-/**
- * @brief Enables or disables the specified ADC peripheral.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the ADCx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the ADON bit to wake up the ADC from power down mode */
- ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;
- }
- else
- {
- /* Disable the selected ADC peripheral */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);
- }
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group2 Analog Watchdog configuration functions
- * @brief Analog Watchdog configuration functions
- *
-@verbatim
- ===============================================================================
- Analog Watchdog configuration functions
- ===============================================================================
-
- This section provides functions allowing to configure the Analog Watchdog
- (AWD) feature in the ADC.
-
- A typical configuration Analog Watchdog is done following these steps :
- 1. the ADC guarded channel(s) is (are) selected using the
- ADC_AnalogWatchdogSingleChannelConfig() function.
- 2. The Analog watchdog lower and higher threshold are configured using the
- ADC_AnalogWatchdogThresholdsConfig() function.
- 3. The Analog watchdog is enabled and configured to enable the check, on one
- or more channels, using the ADC_AnalogWatchdogCmd() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the analog watchdog on single/all regular or
- * injected channels
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
- * This parameter can be one of the following values:
- * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
- * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
- * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
- * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
- * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
- * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
- * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
- * @retval None
- */
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
-
- /* Get the old register value */
- tmpreg = ADCx->CR1;
-
- /* Clear AWDEN, JAWDEN and AWDSGL bits */
- tmpreg &= CR1_AWDMode_RESET;
-
- /* Set the analog watchdog enable mode */
- tmpreg |= ADC_AnalogWatchdog;
-
- /* Store the new register value */
- ADCx->CR1 = tmpreg;
-}
-
-/**
- * @brief Configures the high and low thresholds of the analog watchdog.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param HighThreshold: the ADC analog watchdog High threshold value.
- * This parameter must be a 12-bit value.
- * @param LowThreshold: the ADC analog watchdog Low threshold value.
- * This parameter must be a 12-bit value.
- * @retval None
- */
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
- uint16_t LowThreshold)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_THRESHOLD(HighThreshold));
- assert_param(IS_ADC_THRESHOLD(LowThreshold));
-
- /* Set the ADCx high threshold */
- ADCx->HTR = HighThreshold;
-
- /* Set the ADCx low threshold */
- ADCx->LTR = LowThreshold;
-}
-
-/**
- * @brief Configures the analog watchdog guarded single channel
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_0: ADC Channel0 selected
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @retval None
- */
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
-
- /* Get the old register value */
- tmpreg = ADCx->CR1;
-
- /* Clear the Analog watchdog channel select bits */
- tmpreg &= CR1_AWDCH_RESET;
-
- /* Set the Analog watchdog channel */
- tmpreg |= ADC_Channel;
-
- /* Store the new register value */
- ADCx->CR1 = tmpreg;
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal)
- * and VBAT (Voltage BATtery) management functions
- * @brief Temperature Sensor, Vrefint and VBAT management functions
- *
-@verbatim
- ===============================================================================
- Temperature Sensor, Vrefint and VBAT management functions
- ===============================================================================
-
- This section provides functions allowing to enable/ disable the internal
- connections between the ADC and the Temperature Sensor, the Vrefint and the
- Vbat sources.
-
- A typical configuration to get the Temperature sensor and Vrefint channels
- voltages is done following these steps :
- 1. Enable the internal connection of Temperature sensor and Vrefint sources
- with the ADC channels using ADC_TempSensorVrefintCmd() function.
- 2. Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using
- ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions
- 3. Get the voltage values, using ADC_GetConversionValue() or
- ADC_GetInjectedConversionValue().
-
- A typical configuration to get the VBAT channel voltage is done following
- these steps :
- 1. Enable the internal connection of VBAT source with the ADC channel using
- ADC_VBATCmd() function.
- 2. Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or
- ADC_InjectedChannelConfig() functions
- 3. Get the voltage value, using ADC_GetConversionValue() or
- ADC_GetInjectedConversionValue().
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Enables or disables the temperature sensor and Vrefint channels.
- * @param NewState: new state of the temperature sensor and Vrefint channels.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_TempSensorVrefintCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the temperature sensor and Vrefint channel*/
- ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;
- }
- else
- {
- /* Disable the temperature sensor and Vrefint channel*/
- ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);
- }
-}
-
-/**
- * @brief Enables or disables the VBAT (Voltage Battery) channel.
- * @param NewState: new state of the VBAT channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_VBATCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the VBAT channel*/
- ADC->CCR |= (uint32_t)ADC_CCR_VBATE;
- }
- else
- {
- /* Disable the VBAT channel*/
- ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group4 Regular Channels Configuration functions
- * @brief Regular Channels Configuration functions
- *
-@verbatim
- ===============================================================================
- Regular Channels Configuration functions
- ===============================================================================
-
- This section provides functions allowing to manage the ADC's regular channels,
- it is composed of 2 sub sections :
-
- 1. Configuration and management functions for regular channels: This subsection
- provides functions allowing to configure the ADC regular channels :
- - Configure the rank in the regular group sequencer for each channel
- - Configure the sampling time for each channel
- - select the conversion Trigger for regular channels
- - select the desired EOC event behavior configuration
- - Activate the continuous Mode (*)
- - Activate the Discontinuous Mode
- Please Note that the following features for regular channels are configurated
- using the ADC_Init() function :
- - scan mode activation
- - continuous mode activation (**)
- - External trigger source
- - External trigger edge
- - number of conversion in the regular channels group sequencer.
-
- @note (*) and (**) are performing the same configuration
-
- 2. Get the conversion data: This subsection provides an important function in
- the ADC peripheral since it returns the converted data of the current
- regular channel. When the Conversion value is read, the EOC Flag is
- automatically cleared.
-
- @note For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions
- results data (in the selected multi mode) can be returned in the same
- time using ADC_GetMultiModeConversionValue() function.
-
-
-@endverbatim
- * @{
- */
-/**
- * @brief Configures for the selected ADC regular channel its corresponding
- * rank in the sequencer and its sample time.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_0: ADC Channel0 selected
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @param Rank: The rank in the regular group sequencer.
- * This parameter must be between 1 to 16.
- * @param ADC_SampleTime: The sample time value to be set for the selected channel.
- * This parameter can be one of the following values:
- * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
- * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
- * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
- * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
- * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
- * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
- * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
- * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
- * @retval None
- */
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
-{
- uint32_t tmpreg1 = 0, tmpreg2 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_REGULAR_RANK(Rank));
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
-
- /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
- if (ADC_Channel > ADC_Channel_9)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR1;
-
- /* Calculate the mask to clear */
- tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10));
-
- /* Clear the old sample time */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
-
- /* Set the new sample time */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SMPR1 = tmpreg1;
- }
- else /* ADC_Channel include in ADC_Channel_[0..9] */
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR2;
-
- /* Calculate the mask to clear */
- tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
-
- /* Clear the old sample time */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
-
- /* Set the new sample time */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SMPR2 = tmpreg1;
- }
- /* For Rank 1 to 6 */
- if (Rank < 7)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR3;
-
- /* Calculate the mask to clear */
- tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1));
-
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
-
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SQR3 = tmpreg1;
- }
- /* For Rank 7 to 12 */
- else if (Rank < 13)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR2;
-
- /* Calculate the mask to clear */
- tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7));
-
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
-
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SQR2 = tmpreg1;
- }
- /* For Rank 13 to 16 */
- else
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR1;
-
- /* Calculate the mask to clear */
- tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13));
-
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
-
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SQR1 = tmpreg1;
- }
-}
-
-/**
- * @brief Enables the selected ADC software start conversion of the regular channels.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval None
- */
-void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Enable the selected ADC conversion for regular group */
- ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;
-}
-
-/**
- * @brief Gets the selected ADC Software start regular conversion Status.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval The new state of ADC software start conversion (SET or RESET).
- */
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Check the status of SWSTART bit */
- if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
- {
- /* SWSTART bit is set */
- bitstatus = SET;
- }
- else
- {
- /* SWSTART bit is reset */
- bitstatus = RESET;
- }
-
- /* Return the SWSTART bit status */
- return bitstatus;
-}
-
-
-/**
- * @brief Enables or disables the EOC on each regular channel conversion
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC EOC flag rising
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC EOC rising on each regular channel conversion */
- ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS;
- }
- else
- {
- /* Disable the selected ADC EOC rising on each regular channel conversion */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS);
- }
-}
-
-/**
- * @brief Enables or disables the ADC continuous conversion mode
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC continuous conversion mode
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC continuous conversion mode */
- ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;
- }
- else
- {
- /* Disable the selected ADC continuous conversion mode */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);
- }
-}
-
-/**
- * @brief Configures the discontinuous mode for the selected ADC regular group
- * channel.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param Number: specifies the discontinuous mode regular channel count value.
- * This number must be between 1 and 8.
- * @retval None
- */
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
-{
- uint32_t tmpreg1 = 0;
- uint32_t tmpreg2 = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
-
- /* Get the old register value */
- tmpreg1 = ADCx->CR1;
-
- /* Clear the old discontinuous mode channel count */
- tmpreg1 &= CR1_DISCNUM_RESET;
-
- /* Set the discontinuous mode channel count */
- tmpreg2 = Number - 1;
- tmpreg1 |= tmpreg2 << 13;
-
- /* Store the new register value */
- ADCx->CR1 = tmpreg1;
-}
-
-/**
- * @brief Enables or disables the discontinuous mode on regular group channel
- * for the specified ADC
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC discontinuous mode on
- * regular group channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC regular discontinuous mode */
- ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;
- }
- else
- {
- /* Disable the selected ADC regular discontinuous mode */
- ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);
- }
-}
-
-/**
- * @brief Returns the last ADCx conversion result data for regular channel.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval The Data conversion value.
- */
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Return the selected ADC conversion value */
- return (uint16_t) ADCx->DR;
-}
-
-/**
- * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results
- * data in the selected multi mode.
- * @param None
- * @retval The Data conversion value.
- * @note In dual mode, the value returned by this function is as following
- * Data[15:0] : these bits contain the regular data of ADC1.
- * Data[31:16]: these bits contain the regular data of ADC2.
- * @note In triple mode, the value returned by this function is as following
- * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2.
- * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3.
- */
-uint32_t ADC_GetMultiModeConversionValue(void)
-{
- /* Return the multi mode conversion value */
- return (*(__IO uint32_t *) CDR_ADDRESS);
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions
- * @brief Regular Channels DMA Configuration functions
- *
-@verbatim
- ===============================================================================
- Regular Channels DMA Configuration functions
- ===============================================================================
-
- This section provides functions allowing to configure the DMA for ADC regular
- channels.
- Since converted regular channel values are stored into a unique data register,
- it is useful to use DMA for conversion of more than one regular channel. This
- avoids the loss of the data already stored in the ADC Data register.
-
- When the DMA mode is enabled (using the ADC_DMACmd() function), after each
- conversion of a regular channel, a DMA request is generated.
-
- Depending on the "DMA disable selection for Independent ADC mode"
- configuration (using the ADC_DMARequestAfterLastTransferCmd() function),
- at the end of the last DMA transfer, two possibilities are allowed:
- - No new DMA request is issued to the DMA controller (feature DISABLED)
- - Requests can continue to be generated (feature ENABLED).
-
- Depending on the "DMA disable selection for multi ADC mode" configuration
- (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function),
- at the end of the last DMA transfer, two possibilities are allowed:
- - No new DMA request is issued to the DMA controller (feature DISABLED)
- - Requests can continue to be generated (feature ENABLED).
-
-@endverbatim
- * @{
- */
-
- /**
- * @brief Enables or disables the specified ADC DMA request.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC DMA transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC DMA request */
- ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;
- }
- else
- {
- /* Disable the selected ADC DMA request */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);
- }
-}
-
-/**
- * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode)
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC DMA request after last transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC DMA request after last transfer */
- ADCx->CR2 |= (uint32_t)ADC_CR2_DDS;
- }
- else
- {
- /* Disable the selected ADC DMA request after last transfer */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS);
- }
-}
-
-/**
- * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode
- * @param NewState: new state of the selected ADC DMA request after last transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @note if Enabled, DMA requests are issued as long as data are converted and
- * DMA mode for multi ADC mode (selected using ADC_CommonInit() function
- * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is
- * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3.
- * @retval None
- */
-void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC DMA request after last transfer */
- ADC->CCR |= (uint32_t)ADC_CCR_DDS;
- }
- else
- {
- /* Disable the selected ADC DMA request after last transfer */
- ADC->CCR &= (uint32_t)(~ADC_CCR_DDS);
- }
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group6 Injected channels Configuration functions
- * @brief Injected channels Configuration functions
- *
-@verbatim
- ===============================================================================
- Injected channels Configuration functions
- ===============================================================================
-
- This section provide functions allowing to configure the ADC Injected channels,
- it is composed of 2 sub sections :
-
- 1. Configuration functions for Injected channels: This subsection provides
- functions allowing to configure the ADC injected channels :
- - Configure the rank in the injected group sequencer for each channel
- - Configure the sampling time for each channel
- - Activate the Auto injected Mode
- - Activate the Discontinuous Mode
- - scan mode activation
- - External/software trigger source
- - External trigger edge
- - injected channels sequencer.
-
- 2. Get the Specified Injected channel conversion data: This subsection
- provides an important function in the ADC peripheral since it returns the
- converted data of the specific injected channel.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Configures for the selected ADC injected channel its corresponding
- * rank in the sequencer and its sample time.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_0: ADC Channel0 selected
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @param Rank: The rank in the injected group sequencer.
- * This parameter must be between 1 to 4.
- * @param ADC_SampleTime: The sample time value to be set for the selected channel.
- * This parameter can be one of the following values:
- * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
- * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
- * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
- * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
- * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
- * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
- * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
- * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
- * @retval None
- */
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
-{
- uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_INJECTED_RANK(Rank));
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
- /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
- if (ADC_Channel > ADC_Channel_9)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR1;
- /* Calculate the mask to clear */
- tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10));
- /* Clear the old sample time */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
- /* Set the new sample time */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SMPR1 = tmpreg1;
- }
- else /* ADC_Channel include in ADC_Channel_[0..9] */
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR2;
- /* Calculate the mask to clear */
- tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
- /* Clear the old sample time */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
- /* Set the new sample time */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SMPR2 = tmpreg1;
- }
- /* Rank configuration */
- /* Get the old register value */
- tmpreg1 = ADCx->JSQR;
- /* Get JL value: Number = JL+1 */
- tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20;
- /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
- tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
- /* Clear the old JSQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
- /* Set the JSQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->JSQR = tmpreg1;
-}
-
-/**
- * @brief Configures the sequencer length for injected channels
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param Length: The sequencer length.
- * This parameter must be a number between 1 to 4.
- * @retval None
- */
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
-{
- uint32_t tmpreg1 = 0;
- uint32_t tmpreg2 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_LENGTH(Length));
-
- /* Get the old register value */
- tmpreg1 = ADCx->JSQR;
-
- /* Clear the old injected sequence length JL bits */
- tmpreg1 &= JSQR_JL_RESET;
-
- /* Set the injected sequence length JL bits */
- tmpreg2 = Length - 1;
- tmpreg1 |= tmpreg2 << 20;
-
- /* Store the new register value */
- ADCx->JSQR = tmpreg1;
-}
-
-/**
- * @brief Set the injected channels conversion value offset
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_InjectedChannel: the ADC injected channel to set its offset.
- * This parameter can be one of the following values:
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected
- * @param Offset: the offset value for the selected ADC injected channel
- * This parameter must be a 12bit value.
- * @retval None
- */
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
-{
- __IO uint32_t tmp = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
- assert_param(IS_ADC_OFFSET(Offset));
-
- tmp = (uint32_t)ADCx;
- tmp += ADC_InjectedChannel;
-
- /* Set the selected injected channel data offset */
- *(__IO uint32_t *) tmp = (uint32_t)Offset;
-}
-
- /**
- * @brief Configures the ADCx external trigger for injected channels conversion.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.
- * This parameter can be one of the following values:
- * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected
- * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected
- * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected
- * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected
- * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected
- * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected
- * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected
- * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected
- * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected
- * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected
- * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected
- * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected
- * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected
- * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected
- * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected
- * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected
- * @retval None
- */
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
-
- /* Get the old register value */
- tmpreg = ADCx->CR2;
-
- /* Clear the old external event selection for injected group */
- tmpreg &= CR2_JEXTSEL_RESET;
-
- /* Set the external event selection for injected group */
- tmpreg |= ADC_ExternalTrigInjecConv;
-
- /* Store the new register value */
- ADCx->CR2 = tmpreg;
-}
-
-/**
- * @brief Configures the ADCx external trigger edge for injected channels conversion.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge
- * to start injected conversion.
- * This parameter can be one of the following values:
- * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for
- * injected conversion
- * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge
- * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge
- * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising
- * and falling edge
- * @retval None
- */
-void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));
- /* Get the old register value */
- tmpreg = ADCx->CR2;
- /* Clear the old external trigger edge for injected group */
- tmpreg &= CR2_JEXTEN_RESET;
- /* Set the new external trigger edge for injected group */
- tmpreg |= ADC_ExternalTrigInjecConvEdge;
- /* Store the new register value */
- ADCx->CR2 = tmpreg;
-}
-
-/**
- * @brief Enables the selected ADC software start conversion of the injected channels.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval None
- */
-void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- /* Enable the selected ADC conversion for injected group */
- ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;
-}
-
-/**
- * @brief Gets the selected ADC Software start injected conversion Status.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval The new state of ADC software start injected conversion (SET or RESET).
- */
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Check the status of JSWSTART bit */
- if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
- {
- /* JSWSTART bit is set */
- bitstatus = SET;
- }
- else
- {
- /* JSWSTART bit is reset */
- bitstatus = RESET;
- }
- /* Return the JSWSTART bit status */
- return bitstatus;
-}
-
-/**
- * @brief Enables or disables the selected ADC automatic injected group
- * conversion after regular one.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC auto injected conversion
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC automatic injected group conversion */
- ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;
- }
- else
- {
- /* Disable the selected ADC automatic injected group conversion */
- ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);
- }
-}
-
-/**
- * @brief Enables or disables the discontinuous mode for injected group
- * channel for the specified ADC
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC discontinuous mode on injected
- * group channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC injected discontinuous mode */
- ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;
- }
- else
- {
- /* Disable the selected ADC injected discontinuous mode */
- ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);
- }
-}
-
-/**
- * @brief Returns the ADC injected channel conversion result
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_InjectedChannel: the converted ADC injected channel.
- * This parameter can be one of the following values:
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected
- * @retval The Data conversion value.
- */
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
-
- tmp = (uint32_t)ADCx;
- tmp += ADC_InjectedChannel + JDR_OFFSET;
-
- /* Returns the selected injected channel conversion data value */
- return (uint16_t) (*(__IO uint32_t*) tmp);
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group7 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
-
- This section provides functions allowing to configure the ADC Interrupts and
- to get the status and clear flags and Interrupts pending bits.
-
- Each ADC provides 4 Interrupts sources and 6 Flags which can be divided into
- 3 groups:
-
- I. Flags and Interrupts for ADC regular channels
- =================================================
- Flags :
- ----------
- 1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost
-
- 2. ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate (depending
- on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of:
- ==> a regular CHANNEL conversion
- ==> sequence of regular GROUP conversions .
-
- 3. ADC_FLAG_STRT: Regular channel start ==> to indicate when regular CHANNEL
- conversion starts.
-
- Interrupts :
- ------------
- 1. ADC_IT_OVR : specifies the interrupt source for Overrun detection event.
- 2. ADC_IT_EOC : specifies the interrupt source for Regular channel end of
- conversion event.
-
-
- II. Flags and Interrupts for ADC Injected channels
- =================================================
- Flags :
- ----------
- 1. ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate at
- the end of injected GROUP conversion
-
- 2. ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when
- injected GROUP conversion starts.
-
- Interrupts :
- ------------
- 1. ADC_IT_JEOC : specifies the interrupt source for Injected channel end of
- conversion event.
-
- III. General Flags and Interrupts for the ADC
- =================================================
- Flags :
- ----------
- 1. ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage
- crosses the programmed thresholds values.
-
- Interrupts :
- ------------
- 1. ADC_IT_AWD : specifies the interrupt source for Analog watchdog event.
-
-
- The user should identify which mode will be used in his application to manage
- the ADC controller events: Polling mode or Interrupt mode.
-
- In the Polling Mode it is advised to use the following functions:
- - ADC_GetFlagStatus() : to check if flags events occur.
- - ADC_ClearFlag() : to clear the flags events.
-
- In the Interrupt Mode it is advised to use the following functions:
- - ADC_ITConfig() : to enable or disable the interrupt source.
- - ADC_GetITStatus() : to check if Interrupt occurs.
- - ADC_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
-@endverbatim
- * @{
- */
-/**
- * @brief Enables or disables the specified ADC interrupts.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ADC_IT_EOC: End of conversion interrupt mask
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
- * @arg ADC_IT_OVR: Overrun interrupt enable
- * @param NewState: new state of the specified ADC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
-{
- uint32_t itmask = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_ADC_IT(ADC_IT));
-
- /* Get the ADC IT index */
- itmask = (uint8_t)ADC_IT;
- itmask = (uint32_t)0x01 << itmask;
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC interrupts */
- ADCx->CR1 |= itmask;
- }
- else
- {
- /* Disable the selected ADC interrupts */
- ADCx->CR1 &= (~(uint32_t)itmask);
- }
-}
-
-/**
- * @brief Checks whether the specified ADC flag is set or not.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg ADC_FLAG_AWD: Analog watchdog flag
- * @arg ADC_FLAG_EOC: End of conversion flag
- * @arg ADC_FLAG_JEOC: End of injected group conversion flag
- * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
- * @arg ADC_FLAG_STRT: Start of regular group conversion flag
- * @arg ADC_FLAG_OVR: Overrun flag
- * @retval The new state of ADC_FLAG (SET or RESET).
- */
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
-
- /* Check the status of the specified ADC flag */
- if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
- {
- /* ADC_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* ADC_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the ADC_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the ADCx's pending flags.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg ADC_FLAG_AWD: Analog watchdog flag
- * @arg ADC_FLAG_EOC: End of conversion flag
- * @arg ADC_FLAG_JEOC: End of injected group conversion flag
- * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
- * @arg ADC_FLAG_STRT: Start of regular group conversion flag
- * @arg ADC_FLAG_OVR: Overrun flag
- * @retval None
- */
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
-
- /* Clear the selected ADC flags */
- ADCx->SR = ~(uint32_t)ADC_FLAG;
-}
-
-/**
- * @brief Checks whether the specified ADC interrupt has occurred or not.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg ADC_IT_EOC: End of conversion interrupt mask
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
- * @arg ADC_IT_OVR: Overrun interrupt mask
- * @retval The new state of ADC_IT (SET or RESET).
- */
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t itmask = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_IT(ADC_IT));
-
- /* Get the ADC IT index */
- itmask = ADC_IT >> 8;
-
- /* Get the ADC_IT enable bit status */
- enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ;
-
- /* Check the status of the specified ADC interrupt */
- if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
- {
- /* ADC_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* ADC_IT is reset */
- bitstatus = RESET;
- }
- /* Return the ADC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the ADCx's interrupt pending bits.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg ADC_IT_EOC: End of conversion interrupt mask
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
- * @arg ADC_IT_OVR: Overrun interrupt mask
- * @retval None
- */
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
-{
- uint8_t itmask = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_IT(ADC_IT));
- /* Get the ADC IT index */
- itmask = (uint8_t)(ADC_IT >> 8);
- /* Clear the selected ADC interrupt pending bits */
- ADCx->SR = ~(uint32_t)itmask;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_can.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Controller area network (CAN) peripheral:
- * - Initialization and Configuration
- * - CAN Frames Transmission
- * - CAN Frames Reception
- * - Operation modes switch
- * - Error management
- * - Interrupts and flags
- *
- * @verbatim
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
-
- * 1. Enable the CAN controller interface clock using
- * RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1
- * and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2
- * @note In case you are using CAN2 only, you have to enable the CAN1 clock.
- *
- * 2. CAN pins configuration
- * - Enable the clock for the CAN GPIOs using the following function:
- * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
- * - Connect the involved CAN pins to AF9 using the following function
- * GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx);
- * - Configure these CAN pins in alternate function mode by calling
- * the function GPIO_Init();
- *
- * 3. Initialise and configure the CAN using CAN_Init() and
- * CAN_FilterInit() functions.
- *
- * 4. Transmit the desired CAN frame using CAN_Transmit() function.
- *
- * 5. Check the transmission of a CAN frame using CAN_TransmitStatus()
- * function.
- *
- * 6. Cancel the transmission of a CAN frame using CAN_CancelTransmit()
- * function.
- *
- * 7. Receive a CAN frame using CAN_Recieve() function.
- *
- * 8. Release the receive FIFOs using CAN_FIFORelease() function.
- *
- * 9. Return the number of pending received frames using
- * CAN_MessagePending() function.
- *
- * 10. To control CAN events you can use one of the following two methods:
- * - Check on CAN flags using the CAN_GetFlagStatus() function.
- * - Use CAN interrupts through the function CAN_ITConfig() at
- * initialization phase and CAN_GetITStatus() function into
- * interrupt routines to check if the event has occurred or not.
- * After checking on a flag you should clear it using CAN_ClearFlag()
- * function. And after checking on an interrupt event you should
- * clear it using CAN_ClearITPendingBit() function.
- *
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_can.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CAN
- * @brief CAN driver modules
- * @{
- */
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* CAN Master Control Register bits */
-#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */
-
-/* CAN Mailbox Transmit Request */
-#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
-
-/* CAN Filter Master Register bits */
-#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */
-
-/* Time out for INAK bit */
-#define INAK_TIMEOUT ((uint32_t)0x0000FFFF)
-/* Time out for SLAK bit */
-#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)
-
-/* Flags in TSR register */
-#define CAN_FLAGS_TSR ((uint32_t)0x08000000)
-/* Flags in RF1R register */
-#define CAN_FLAGS_RF1R ((uint32_t)0x04000000)
-/* Flags in RF0R register */
-#define CAN_FLAGS_RF0R ((uint32_t)0x02000000)
-/* Flags in MSR register */
-#define CAN_FLAGS_MSR ((uint32_t)0x01000000)
-/* Flags in ESR register */
-#define CAN_FLAGS_ESR ((uint32_t)0x00F00000)
-
-/* Mailboxes definition */
-#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
-#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
-#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
-
-#define CAN_MODE_MASK ((uint32_t) 0x00000003)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
-
-/** @defgroup CAN_Private_Functions
- * @{
- */
-
-/** @defgroup CAN_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- Initialization and Configuration functions
- ===============================================================================
- This section provides functions allowing to
- - Initialize the CAN peripherals : Prescaler, operating mode, the maximum number
- of time quanta to perform resynchronization, the number of time quanta in
- Bit Segment 1 and 2 and many other modes.
- Refer to @ref CAN_InitTypeDef for more details.
- - Configures the CAN reception filter.
- - Select the start bank filter for slave CAN.
- - Enables or disables the Debug Freeze mode for CAN
- - Enables or disables the CAN Time Trigger Operation communication mode
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the CAN peripheral registers to their default reset values.
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
- * @retval None.
- */
-void CAN_DeInit(CAN_TypeDef* CANx)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- if (CANx == CAN1)
- {
- /* Enable CAN1 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
- /* Release CAN1 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
- }
- else
- {
- /* Enable CAN2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
- /* Release CAN2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
- }
-}
-
-/**
- * @brief Initializes the CAN peripheral according to the specified
- * parameters in the CAN_InitStruct.
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
- * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains
- * the configuration information for the CAN peripheral.
- * @retval Constant indicates initialization succeed which will be
- * CAN_InitStatus_Failed or CAN_InitStatus_Success.
- */
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
-{
- uint8_t InitStatus = CAN_InitStatus_Failed;
- uint32_t wait_ack = 0x00000000;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
- assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
- assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
- assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
- assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
- assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
-
- /* Exit from sleep mode */
- CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
-
- /* Request initialisation */
- CANx->MCR |= CAN_MCR_INRQ ;
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
- {
- wait_ack++;
- }
-
- /* Check acknowledge */
- if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
- {
- InitStatus = CAN_InitStatus_Failed;
- }
- else
- {
- /* Set the time triggered communication mode */
- if (CAN_InitStruct->CAN_TTCM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_TTCM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
- }
-
- /* Set the automatic bus-off management */
- if (CAN_InitStruct->CAN_ABOM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_ABOM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
- }
-
- /* Set the automatic wake-up mode */
- if (CAN_InitStruct->CAN_AWUM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_AWUM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
- }
-
- /* Set the no automatic retransmission */
- if (CAN_InitStruct->CAN_NART == ENABLE)
- {
- CANx->MCR |= CAN_MCR_NART;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
- }
-
- /* Set the receive FIFO locked mode */
- if (CAN_InitStruct->CAN_RFLM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_RFLM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
- }
-
- /* Set the transmit FIFO priority */
- if (CAN_InitStruct->CAN_TXFP == ENABLE)
- {
- CANx->MCR |= CAN_MCR_TXFP;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
- }
-
- /* Set the bit timing register */
- CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
- ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
- ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
- ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
- ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
-
- /* Request leave initialisation */
- CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
-
- /* Wait the acknowledge */
- wait_ack = 0;
-
- while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
- {
- wait_ack++;
- }
-
- /* ...and check acknowledged */
- if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
- {
- InitStatus = CAN_InitStatus_Failed;
- }
- else
- {
- InitStatus = CAN_InitStatus_Success ;
- }
- }
-
- /* At this step, return the status of initialization */
- return InitStatus;
-}
-
-/**
- * @brief Configures the CAN reception filter according to the specified
- * parameters in the CAN_FilterInitStruct.
- * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that
- * contains the configuration information.
- * @retval None
- */
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
-{
- uint32_t filter_number_bit_pos = 0;
- /* Check the parameters */
- assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
- assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
- assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
- assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
- assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
-
- filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
-
- /* Initialisation mode for the filter */
- CAN1->FMR |= FMR_FINIT;
-
- /* Filter Deactivation */
- CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
-
- /* Filter Scale */
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
- {
- /* 16-bit scale for the filter */
- CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
-
- /* First 16-bit identifier and First 16-bit mask */
- /* Or First 16-bit identifier and Second 16-bit identifier */
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
-
- /* Second 16-bit identifier and Second 16-bit mask */
- /* Or Third 16-bit identifier and Fourth 16-bit identifier */
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
- }
-
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
- {
- /* 32-bit scale for the filter */
- CAN1->FS1R |= filter_number_bit_pos;
- /* 32-bit identifier or First 32-bit identifier */
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
- /* 32-bit mask or Second 32-bit identifier */
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
- }
-
- /* Filter Mode */
- if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
- {
- /*Id/Mask mode for the filter*/
- CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
- }
- else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
- {
- /*Identifier list mode for the filter*/
- CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
- }
-
- /* Filter FIFO assignment */
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
- {
- /* FIFO 0 assignation for the filter */
- CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
- }
-
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
- {
- /* FIFO 1 assignation for the filter */
- CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
- }
-
- /* Filter activation */
- if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
- {
- CAN1->FA1R |= filter_number_bit_pos;
- }
-
- /* Leave the initialisation mode for the filter */
- CAN1->FMR &= ~FMR_FINIT;
-}
-
-/**
- * @brief Fills each CAN_InitStruct member with its default value.
- * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized.
- * @retval None
- */
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
-{
- /* Reset CAN init structure parameters values */
-
- /* Initialize the time triggered communication mode */
- CAN_InitStruct->CAN_TTCM = DISABLE;
-
- /* Initialize the automatic bus-off management */
- CAN_InitStruct->CAN_ABOM = DISABLE;
-
- /* Initialize the automatic wake-up mode */
- CAN_InitStruct->CAN_AWUM = DISABLE;
-
- /* Initialize the no automatic retransmission */
- CAN_InitStruct->CAN_NART = DISABLE;
-
- /* Initialize the receive FIFO locked mode */
- CAN_InitStruct->CAN_RFLM = DISABLE;
-
- /* Initialize the transmit FIFO priority */
- CAN_InitStruct->CAN_TXFP = DISABLE;
-
- /* Initialize the CAN_Mode member */
- CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
-
- /* Initialize the CAN_SJW member */
- CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
-
- /* Initialize the CAN_BS1 member */
- CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
-
- /* Initialize the CAN_BS2 member */
- CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
-
- /* Initialize the CAN_Prescaler member */
- CAN_InitStruct->CAN_Prescaler = 1;
-}
-
-/**
- * @brief Select the start bank filter for slave CAN.
- * @param CAN_BankNumber: Select the start slave bank filter from 1..27.
- * @retval None
- */
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
-
- /* Enter Initialisation mode for the filter */
- CAN1->FMR |= FMR_FINIT;
-
- /* Select the start slave bank */
- CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
- CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
-
- /* Leave Initialisation mode for the filter */
- CAN1->FMR &= ~FMR_FINIT;
-}
-
-/**
- * @brief Enables or disables the DBG Freeze for CAN.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param NewState: new state of the CAN peripheral.
- * This parameter can be: ENABLE (CAN reception/transmission is frozen
- * during debug. Reception FIFOs can still be accessed/controlled normally)
- * or DISABLE (CAN is working during debug).
- * @retval None
- */
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Debug Freeze */
- CANx->MCR |= MCR_DBF;
- }
- else
- {
- /* Disable Debug Freeze */
- CANx->MCR &= ~MCR_DBF;
- }
-}
-
-
-/**
- * @brief Enables or disables the CAN Time TriggerOperation communication mode.
- * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
- * sent over the CAN bus.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE.
- * When enabled, Time stamp (TIME[15:0]) value is sent in the last two
- * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8]
- * in data byte 7.
- * @retval None
- */
-void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the TTCM mode */
- CANx->MCR |= CAN_MCR_TTCM;
-
- /* Set TGT bits */
- CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
- CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
- CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
- }
- else
- {
- /* Disable the TTCM mode */
- CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
-
- /* Reset TGT bits */
- CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
- CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
- CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
- }
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group2 CAN Frames Transmission functions
- * @brief CAN Frames Transmission functions
- *
-@verbatim
- ===============================================================================
- CAN Frames Transmission functions
- ===============================================================================
- This section provides functions allowing to
- - Initiate and transmit a CAN frame message (if there is an empty mailbox).
- - Check the transmission status of a CAN Frame
- - Cancel a transmit request
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initiates and transmits a CAN frame message.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data.
- * @retval The number of the mailbox that is used for transmission or
- * CAN_TxStatus_NoMailBox if there is no empty mailbox.
- */
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
-{
- uint8_t transmit_mailbox = 0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
- assert_param(IS_CAN_RTR(TxMessage->RTR));
- assert_param(IS_CAN_DLC(TxMessage->DLC));
-
- /* Select one empty transmit mailbox */
- if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
- {
- transmit_mailbox = 0;
- }
- else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
- {
- transmit_mailbox = 1;
- }
- else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
- {
- transmit_mailbox = 2;
- }
- else
- {
- transmit_mailbox = CAN_TxStatus_NoMailBox;
- }
-
- if (transmit_mailbox != CAN_TxStatus_NoMailBox)
- {
- /* Set up the Id */
- CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
- if (TxMessage->IDE == CAN_Id_Standard)
- {
- assert_param(IS_CAN_STDID(TxMessage->StdId));
- CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
- TxMessage->RTR);
- }
- else
- {
- assert_param(IS_CAN_EXTID(TxMessage->ExtId));
- CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
- TxMessage->IDE | \
- TxMessage->RTR);
- }
-
- /* Set up the DLC */
- TxMessage->DLC &= (uint8_t)0x0000000F;
- CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
- CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
-
- /* Set up the data field */
- CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) |
- ((uint32_t)TxMessage->Data[2] << 16) |
- ((uint32_t)TxMessage->Data[1] << 8) |
- ((uint32_t)TxMessage->Data[0]));
- CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) |
- ((uint32_t)TxMessage->Data[6] << 16) |
- ((uint32_t)TxMessage->Data[5] << 8) |
- ((uint32_t)TxMessage->Data[4]));
- /* Request transmission */
- CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
- }
- return transmit_mailbox;
-}
-
-/**
- * @brief Checks the transmission status of a CAN Frame.
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
- * @param TransmitMailbox: the number of the mailbox that is used for transmission.
- * @retval CAN_TxStatus_Ok if the CAN driver transmits the message,
- * CAN_TxStatus_Failed in an other case.
- */
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
-{
- uint32_t state = 0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
-
- switch (TransmitMailbox)
- {
- case (CAN_TXMAILBOX_0):
- state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
- break;
- case (CAN_TXMAILBOX_1):
- state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
- break;
- case (CAN_TXMAILBOX_2):
- state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
- break;
- default:
- state = CAN_TxStatus_Failed;
- break;
- }
- switch (state)
- {
- /* transmit pending */
- case (0x0): state = CAN_TxStatus_Pending;
- break;
- /* transmit failed */
- case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
- break;
- case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
- break;
- case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
- break;
- /* transmit succeeded */
- case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
- break;
- case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
- break;
- case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
- break;
- default: state = CAN_TxStatus_Failed;
- break;
- }
- return (uint8_t) state;
-}
-
-/**
- * @brief Cancels a transmit request.
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
- * @param Mailbox: Mailbox number.
- * @retval None
- */
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
- /* abort transmission */
- switch (Mailbox)
- {
- case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
- break;
- case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
- break;
- case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
- break;
- default:
- break;
- }
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group3 CAN Frames Reception functions
- * @brief CAN Frames Reception functions
- *
-@verbatim
- ===============================================================================
- CAN Frames Reception functions
- ===============================================================================
- This section provides functions allowing to
- - Receive a correct CAN frame
- - Release a specified receive FIFO (2 FIFOs are available)
- - Return the number of the pending received CAN frames
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Receives a correct CAN frame.
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @param RxMessage: pointer to a structure receive frame which contains CAN Id,
- * CAN DLC, CAN data and FMI number.
- * @retval None
- */
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- /* Get the Id */
- RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
- if (RxMessage->IDE == CAN_Id_Standard)
- {
- RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
- }
- else
- {
- RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
- }
-
- RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
- /* Get the DLC */
- RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
- /* Get the FMI */
- RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
- /* Get the data field */
- RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
- RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
- RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
- RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
- RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
- RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
- RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
- RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
- /* Release the FIFO */
- /* Release FIFO0 */
- if (FIFONumber == CAN_FIFO0)
- {
- CANx->RF0R |= CAN_RF0R_RFOM0;
- }
- /* Release FIFO1 */
- else /* FIFONumber == CAN_FIFO1 */
- {
- CANx->RF1R |= CAN_RF1R_RFOM1;
- }
-}
-
-/**
- * @brief Releases the specified receive FIFO.
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
- * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
- * @retval None
- */
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- /* Release FIFO0 */
- if (FIFONumber == CAN_FIFO0)
- {
- CANx->RF0R |= CAN_RF0R_RFOM0;
- }
- /* Release FIFO1 */
- else /* FIFONumber == CAN_FIFO1 */
- {
- CANx->RF1R |= CAN_RF1R_RFOM1;
- }
-}
-
-/**
- * @brief Returns the number of pending received messages.
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval NbMessage : which is the number of pending message.
- */
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
-{
- uint8_t message_pending=0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- if (FIFONumber == CAN_FIFO0)
- {
- message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
- }
- else if (FIFONumber == CAN_FIFO1)
- {
- message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
- }
- else
- {
- message_pending = 0;
- }
- return message_pending;
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group4 CAN Operation modes functions
- * @brief CAN Operation modes functions
- *
-@verbatim
- ===============================================================================
- CAN Operation modes functions
- ===============================================================================
- This section provides functions allowing to select the CAN Operation modes
- - sleep mode
- - normal mode
- - initialization mode
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Selects the CAN Operation mode.
- * @param CAN_OperatingMode: CAN Operating Mode.
- * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration.
- * @retval status of the requested mode which can be
- * - CAN_ModeStatus_Failed: CAN failed entering the specific mode
- * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode
- */
-uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
-{
- uint8_t status = CAN_ModeStatus_Failed;
-
- /* Timeout for INAK or also for SLAK bits*/
- uint32_t timeout = INAK_TIMEOUT;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
-
- if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
- {
- /* Request initialisation */
- CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
- {
- timeout--;
- }
- if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
- {
- status = CAN_ModeStatus_Failed;
- }
- else
- {
- status = CAN_ModeStatus_Success;
- }
- }
- else if (CAN_OperatingMode == CAN_OperatingMode_Normal)
- {
- /* Request leave initialisation and sleep mode and enter Normal mode */
- CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
- {
- timeout--;
- }
- if ((CANx->MSR & CAN_MODE_MASK) != 0)
- {
- status = CAN_ModeStatus_Failed;
- }
- else
- {
- status = CAN_ModeStatus_Success;
- }
- }
- else if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
- {
- /* Request Sleep mode */
- CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
- {
- timeout--;
- }
- if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
- {
- status = CAN_ModeStatus_Failed;
- }
- else
- {
- status = CAN_ModeStatus_Success;
- }
- }
- else
- {
- status = CAN_ModeStatus_Failed;
- }
-
- return (uint8_t) status;
-}
-
-/**
- * @brief Enters the Sleep (low power) mode.
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
- * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise.
- */
-uint8_t CAN_Sleep(CAN_TypeDef* CANx)
-{
- uint8_t sleepstatus = CAN_Sleep_Failed;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Request Sleep mode */
- CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-
- /* Sleep mode status */
- if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
- {
- /* Sleep mode not entered */
- sleepstatus = CAN_Sleep_Ok;
- }
- /* return sleep mode status */
- return (uint8_t)sleepstatus;
-}
-
-/**
- * @brief Wakes up the CAN peripheral from sleep mode .
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
- * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise.
- */
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
-{
- uint32_t wait_slak = SLAK_TIMEOUT;
- uint8_t wakeupstatus = CAN_WakeUp_Failed;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Wake up request */
- CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
-
- /* Sleep mode status */
- while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
- {
- wait_slak--;
- }
- if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
- {
- /* wake up done : Sleep mode exited */
- wakeupstatus = CAN_WakeUp_Ok;
- }
- /* return wakeup status */
- return (uint8_t)wakeupstatus;
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group5 CAN Bus Error management functions
- * @brief CAN Bus Error management functions
- *
-@verbatim
- ===============================================================================
- CAN Bus Error management functions
- ===============================================================================
- This section provides functions allowing to
- - Return the CANx's last error code (LEC)
- - Return the CANx Receive Error Counter (REC)
- - Return the LSB of the 9-bit CANx Transmit Error Counter(TEC).
-
- @note If TEC is greater than 255, The CAN is in bus-off state.
- @note if REC or TEC are greater than 96, an Error warning flag occurs.
- @note if REC or TEC are greater than 127, an Error Passive Flag occurs.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the CANx's last error code (LEC).
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
- * @retval Error code:
- * - CAN_ERRORCODE_NoErr: No Error
- * - CAN_ERRORCODE_StuffErr: Stuff Error
- * - CAN_ERRORCODE_FormErr: Form Error
- * - CAN_ERRORCODE_ACKErr : Acknowledgment Error
- * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error
- * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error
- * - CAN_ERRORCODE_CRCErr: CRC Error
- * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error
- */
-uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
-{
- uint8_t errorcode=0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Get the error code*/
- errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
-
- /* Return the error code*/
- return errorcode;
-}
-
-/**
- * @brief Returns the CANx Receive Error Counter (REC).
- * @note In case of an error during reception, this counter is incremented
- * by 1 or by 8 depending on the error condition as defined by the CAN
- * standard. After every successful reception, the counter is
- * decremented by 1 or reset to 120 if its value was higher than 128.
- * When the counter value exceeds 127, the CAN controller enters the
- * error passive state.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @retval CAN Receive Error Counter.
- */
-uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
-{
- uint8_t counter=0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Get the Receive Error Counter*/
- counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
-
- /* Return the Receive Error Counter*/
- return counter;
-}
-
-
-/**
- * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @retval LSB of the 9-bit CAN Transmit Error Counter.
- */
-uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
-{
- uint8_t counter=0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
- counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
-
- /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
- return counter;
-}
-/**
- * @}
- */
-
-/** @defgroup CAN_Group6 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
-
- This section provides functions allowing to configure the CAN Interrupts and
- to get the status and clear flags and Interrupts pending bits.
-
- The CAN provides 14 Interrupts sources and 15 Flags:
-
- ===============
- Flags :
- ===============
- The 15 flags can be divided on 4 groups:
-
- A. Transmit Flags
- -----------------------
- CAN_FLAG_RQCP0,
- CAN_FLAG_RQCP1,
- CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags
- Set when when the last request (transmit or abort) has
- been performed.
-
- B. Receive Flags
- -----------------------
-
- CAN_FLAG_FMP0,
- CAN_FLAG_FMP1 : FIFO 0 and 1 Message Pending Flags
- set to signal that messages are pending in the receive
- FIFO.
- These Flags are cleared only by hardware.
-
- CAN_FLAG_FF0,
- CAN_FLAG_FF1 : FIFO 0 and 1 Full Flags
- set when three messages are stored in the selected
- FIFO.
-
- CAN_FLAG_FOV0
- CAN_FLAG_FOV1 : FIFO 0 and 1 Overrun Flags
- set when a new message has been received and passed
- the filter while the FIFO was full.
-
- C. Operating Mode Flags
- -----------------------
- CAN_FLAG_WKU : Wake up Flag
- set to signal that a SOF bit has been detected while
- the CAN hardware was in Sleep mode.
-
- CAN_FLAG_SLAK : Sleep acknowledge Flag
- Set to signal that the CAN has entered Sleep Mode.
-
- D. Error Flags
- -----------------------
- CAN_FLAG_EWG : Error Warning Flag
- Set when the warning limit has been reached (Receive
- Error Counter or Transmit Error Counter greater than 96).
- This Flag is cleared only by hardware.
-
- CAN_FLAG_EPV : Error Passive Flag
- Set when the Error Passive limit has been reached
- (Receive Error Counter or Transmit Error Counter
- greater than 127).
- This Flag is cleared only by hardware.
-
- CAN_FLAG_BOF : Bus-Off Flag
- set when CAN enters the bus-off state. The bus-off
- state is entered on TEC overflow, greater than 255.
- This Flag is cleared only by hardware.
-
- CAN_FLAG_LEC : Last error code Flag
- set If a message has been transferred (reception or
- transmission) with error, and the error code is hold.
-
- ===============
- Interrupts :
- ===============
- The 14 interrupts can be divided on 4 groups:
-
- A. Transmit interrupt
- -----------------------
- CAN_IT_TME : Transmit mailbox empty Interrupt
- if enabled, this interrupt source is pending when
- no transmit request are pending for Tx mailboxes.
-
- B. Receive Interrupts
- -----------------------
- CAN_IT_FMP0,
- CAN_IT_FMP1 : FIFO 0 and FIFO1 message pending Interrupts
- if enabled, these interrupt sources are pending when
- messages are pending in the receive FIFO.
- The corresponding interrupt pending bits are cleared
- only by hardware.
-
- CAN_IT_FF0,
- CAN_IT_FF1 : FIFO 0 and FIFO1 full Interrupts
- if enabled, these interrupt sources are pending when
- three messages are stored in the selected FIFO.
-
- CAN_IT_FOV0,
- CAN_IT_FOV1 : FIFO 0 and FIFO1 overrun Interrupts
- if enabled, these interrupt sources are pending when
- a new message has been received and passed the filter
- while the FIFO was full.
-
- C. Operating Mode Interrupts
- -------------------------------
- CAN_IT_WKU : Wake-up Interrupt
- if enabled, this interrupt source is pending when
- a SOF bit has been detected while the CAN hardware was
- in Sleep mode.
-
- CAN_IT_SLK : Sleep acknowledge Interrupt
- if enabled, this interrupt source is pending when
- the CAN has entered Sleep Mode.
-
- D. Error Interrupts
- -----------------------
- CAN_IT_EWG : Error warning Interrupt
- if enabled, this interrupt source is pending when
- the warning limit has been reached (Receive Error
- Counter or Transmit Error Counter=96).
-
- CAN_IT_EPV : Error passive Interrupt
- if enabled, this interrupt source is pending when
- the Error Passive limit has been reached (Receive
- Error Counter or Transmit Error Counter>127).
-
- CAN_IT_BOF : Bus-off Interrupt
- if enabled, this interrupt source is pending when
- CAN enters the bus-off state. The bus-off state is
- entered on TEC overflow, greater than 255.
- This Flag is cleared only by hardware.
-
- CAN_IT_LEC : Last error code Interrupt
- if enabled, this interrupt source is pending when
- a message has been transferred (reception or
- transmission) with error, and the error code is hold.
-
- CAN_IT_ERR : Error Interrupt
- if enabled, this interrupt source is pending when
- an error condition is pending.
-
-
- Managing the CAN controller events :
- ------------------------------------
- The user should identify which mode will be used in his application to manage
- the CAN controller events: Polling mode or Interrupt mode.
-
- 1. In the Polling Mode it is advised to use the following functions:
- - CAN_GetFlagStatus() : to check if flags events occur.
- - CAN_ClearFlag() : to clear the flags events.
-
-
-
- 2. In the Interrupt Mode it is advised to use the following functions:
- - CAN_ITConfig() : to enable or disable the interrupt source.
- - CAN_GetITStatus() : to check if Interrupt occurs.
- - CAN_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag).
- @note This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts
- pending bits since there are cleared only by hardware.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Enables or disables the specified CANx interrupts.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
- * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt
- * @arg CAN_IT_FF0: FIFO 0 full Interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
- * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt
- * @arg CAN_IT_FF1: FIFO 1 full Interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
- * @arg CAN_IT_WKU: Wake-up Interrupt
- * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
- * @arg CAN_IT_EWG: Error warning Interrupt
- * @arg CAN_IT_EPV: Error passive Interrupt
- * @arg CAN_IT_BOF: Bus-off Interrupt
- * @arg CAN_IT_LEC: Last error code Interrupt
- * @arg CAN_IT_ERR: Error Interrupt
- * @param NewState: new state of the CAN interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IT(CAN_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected CANx interrupt */
- CANx->IER |= CAN_IT;
- }
- else
- {
- /* Disable the selected CANx interrupt */
- CANx->IER &= ~CAN_IT;
- }
-}
-/**
- * @brief Checks whether the specified CAN flag is set or not.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
- * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
- * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_EWG: Error Warning Flag
- * @arg CAN_FLAG_EPV: Error Passive Flag
- * @arg CAN_FLAG_BOF: Bus-Off Flag
- * @arg CAN_FLAG_LEC: Last error code Flag
- * @retval The new state of CAN_FLAG (SET or RESET).
- */
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
-
-
- if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
- {
- /* Check the status of the specified CAN flag */
- if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- /* Return the CAN_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the CAN's pending flags.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_FLAG: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
- * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
- * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_LEC: Last error code Flag
- * @retval None
- */
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
-{
- uint32_t flagtmp=0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
-
- if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
- {
- /* Clear the selected CAN flags */
- CANx->ESR = (uint32_t)RESET;
- }
- else /* MSR or TSR or RF0R or RF1R */
- {
- flagtmp = CAN_FLAG & 0x000FFFFF;
-
- if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
- {
- /* Receive Flags */
- CANx->RF0R = (uint32_t)(flagtmp);
- }
- else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
- {
- /* Receive Flags */
- CANx->RF1R = (uint32_t)(flagtmp);
- }
- else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
- {
- /* Transmit Flags */
- CANx->TSR = (uint32_t)(flagtmp);
- }
- else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
- {
- /* Operating mode Flags */
- CANx->MSR = (uint32_t)(flagtmp);
- }
- }
-}
-
-/**
- * @brief Checks whether the specified CANx interrupt has occurred or not.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_IT: specifies the CAN interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
- * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt
- * @arg CAN_IT_FF0: FIFO 0 full Interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
- * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt
- * @arg CAN_IT_FF1: FIFO 1 full Interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
- * @arg CAN_IT_WKU: Wake-up Interrupt
- * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
- * @arg CAN_IT_EWG: Error warning Interrupt
- * @arg CAN_IT_EPV: Error passive Interrupt
- * @arg CAN_IT_BOF: Bus-off Interrupt
- * @arg CAN_IT_LEC: Last error code Interrupt
- * @arg CAN_IT_ERR: Error Interrupt
- * @retval The current state of CAN_IT (SET or RESET).
- */
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
-{
- ITStatus itstatus = RESET;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IT(CAN_IT));
-
- /* check the interrupt enable bit */
- if((CANx->IER & CAN_IT) != RESET)
- {
- /* in case the Interrupt is enabled, .... */
- switch (CAN_IT)
- {
- case CAN_IT_TME:
- /* Check CAN_TSR_RQCPx bits */
- itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);
- break;
- case CAN_IT_FMP0:
- /* Check CAN_RF0R_FMP0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);
- break;
- case CAN_IT_FF0:
- /* Check CAN_RF0R_FULL0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);
- break;
- case CAN_IT_FOV0:
- /* Check CAN_RF0R_FOVR0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);
- break;
- case CAN_IT_FMP1:
- /* Check CAN_RF1R_FMP1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);
- break;
- case CAN_IT_FF1:
- /* Check CAN_RF1R_FULL1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);
- break;
- case CAN_IT_FOV1:
- /* Check CAN_RF1R_FOVR1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);
- break;
- case CAN_IT_WKU:
- /* Check CAN_MSR_WKUI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);
- break;
- case CAN_IT_SLK:
- /* Check CAN_MSR_SLAKI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);
- break;
- case CAN_IT_EWG:
- /* Check CAN_ESR_EWGF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);
- break;
- case CAN_IT_EPV:
- /* Check CAN_ESR_EPVF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);
- break;
- case CAN_IT_BOF:
- /* Check CAN_ESR_BOFF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);
- break;
- case CAN_IT_LEC:
- /* Check CAN_ESR_LEC bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);
- break;
- case CAN_IT_ERR:
- /* Check CAN_MSR_ERRI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI);
- break;
- default:
- /* in case of error, return RESET */
- itstatus = RESET;
- break;
- }
- }
- else
- {
- /* in case the Interrupt is not enabled, return RESET */
- itstatus = RESET;
- }
-
- /* Return the CAN_IT status */
- return itstatus;
-}
-
-/**
- * @brief Clears the CANx's interrupt pending bits.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
- * @arg CAN_IT_FF0: FIFO 0 full Interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
- * @arg CAN_IT_FF1: FIFO 1 full Interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
- * @arg CAN_IT_WKU: Wake-up Interrupt
- * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
- * @arg CAN_IT_EWG: Error warning Interrupt
- * @arg CAN_IT_EPV: Error passive Interrupt
- * @arg CAN_IT_BOF: Bus-off Interrupt
- * @arg CAN_IT_LEC: Last error code Interrupt
- * @arg CAN_IT_ERR: Error Interrupt
- * @retval None
- */
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_CLEAR_IT(CAN_IT));
-
- switch (CAN_IT)
- {
- case CAN_IT_TME:
- /* Clear CAN_TSR_RQCPx (rc_w1)*/
- CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;
- break;
- case CAN_IT_FF0:
- /* Clear CAN_RF0R_FULL0 (rc_w1)*/
- CANx->RF0R = CAN_RF0R_FULL0;
- break;
- case CAN_IT_FOV0:
- /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
- CANx->RF0R = CAN_RF0R_FOVR0;
- break;
- case CAN_IT_FF1:
- /* Clear CAN_RF1R_FULL1 (rc_w1)*/
- CANx->RF1R = CAN_RF1R_FULL1;
- break;
- case CAN_IT_FOV1:
- /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
- CANx->RF1R = CAN_RF1R_FOVR1;
- break;
- case CAN_IT_WKU:
- /* Clear CAN_MSR_WKUI (rc_w1)*/
- CANx->MSR = CAN_MSR_WKUI;
- break;
- case CAN_IT_SLK:
- /* Clear CAN_MSR_SLAKI (rc_w1)*/
- CANx->MSR = CAN_MSR_SLAKI;
- break;
- case CAN_IT_EWG:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
- break;
- case CAN_IT_EPV:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
- break;
- case CAN_IT_BOF:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
- break;
- case CAN_IT_LEC:
- /* Clear LEC bits */
- CANx->ESR = RESET;
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- break;
- case CAN_IT_ERR:
- /*Clear LEC bits */
- CANx->ESR = RESET;
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/
- break;
- default:
- break;
- }
-}
- /**
- * @}
- */
-
-/**
- * @brief Checks whether the CAN interrupt has occurred or not.
- * @param CAN_Reg: specifies the CAN interrupt register to check.
- * @param It_Bit: specifies the interrupt source bit to check.
- * @retval The new state of the CAN Interrupt (SET or RESET).
- */
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
-{
- ITStatus pendingbitstatus = RESET;
-
- if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
- {
- /* CAN_IT is set */
- pendingbitstatus = SET;
- }
- else
- {
- /* CAN_IT is reset */
- pendingbitstatus = RESET;
- }
- return pendingbitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_crc.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides all the CRC firmware functions.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_crc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRC
- * @brief CRC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRC_Private_Functions
- * @{
- */
-
-/**
- * @brief Resets the CRC Data register (DR).
- * @param None
- * @retval None
- */
-void CRC_ResetDR(void)
-{
- /* Reset CRC generator */
- CRC->CR = CRC_CR_RESET;
-}
-
-/**
- * @brief Computes the 32-bit CRC of a given data word(32-bit).
- * @param Data: data word(32-bit) to compute its CRC
- * @retval 32-bit CRC
- */
-uint32_t CRC_CalcCRC(uint32_t Data)
-{
- CRC->DR = Data;
-
- return (CRC->DR);
-}
-
-/**
- * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
- * @param pBuffer: pointer to the buffer containing the data to be computed
- * @param BufferLength: length of the buffer to be computed
- * @retval 32-bit CRC
- */
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t index = 0;
-
- for(index = 0; index < BufferLength; index++)
- {
- CRC->DR = pBuffer[index];
- }
- return (CRC->DR);
-}
-
-/**
- * @brief Returns the current CRC value.
- * @param None
- * @retval 32-bit CRC
- */
-uint32_t CRC_GetCRC(void)
-{
- return (CRC->DR);
-}
-
-/**
- * @brief Stores a 8-bit data in the Independent Data(ID) register.
- * @param IDValue: 8-bit value to be stored in the ID register
- * @retval None
- */
-void CRC_SetIDRegister(uint8_t IDValue)
-{
- CRC->IDR = IDValue;
-}
-
-/**
- * @brief Returns the 8-bit data stored in the Independent Data(ID) register
- * @param None
- * @retval 8-bit value of the ID register
- */
-uint8_t CRC_GetIDRegister(void)
-{
- return (CRC->IDR);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_cryp.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Cryptographic processor (CRYP) peripheral:
- * - Initialization and Configuration functions
- * - Data treatment functions
- * - Context swapping functions
- * - DMA interface function
- * - Interrupts and flags management
- *
- * @verbatim
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * 1. Enable the CRYP controller clock using
- * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
- *
- * 2. Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if
- * needed CRYP_IVInit().
- *
- * 3. Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function.
- *
- * 4. Enable the CRYP controller using the CRYP_Cmd() function.
- *
- * 5. If using DMA for Data input and output transfer,
- * Activate the needed DMA Requests using CRYP_DMACmd() function
-
- * 6. If DMA is not used for data transfer, use CRYP_DataIn() and
- * CRYP_DataOut() functions to enter data to IN FIFO and get result
- * from OUT FIFO.
- *
- * 7. To control CRYP events you can use one of the following
- * two methods:
- * - Check on CRYP flags using the CRYP_GetFlagStatus() function.
- * - Use CRYP interrupts through the function CRYP_ITConfig() at
- * initialization phase and CRYP_GetITStatus() function into
- * interrupt routines in processing phase.
- *
- * 8. Save and restore Cryptographic processor context using
- * CRYP_SaveContext() and CRYP_RestoreContext() functions.
- *
- *
- * ===================================================================
- * Procedure to perform an encryption or a decryption
- * ===================================================================
- *
- * Initialization
- * ===============
- * 1. Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and
- * CRYP_IVInit functions:
- * - Configure the key size (128-, 192- or 256-bit, in the AES only)
- * - Enter the symmetric key
- * - Configure the data type
- * - In case of decryption in AES-ECB or AES-CBC, you must prepare
- * the key: configure the key preparation mode. Then Enable the CRYP
- * peripheral using CRYP_Cmd() function: the BUSY flag is set.
- * Wait until BUSY flag is reset : the key is prepared for decryption
- * - Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the
- * AES in ECB/CBC/CTR)
- * - Configure the direction (encryption/decryption).
- * - Write the initialization vectors (in CBC or CTR modes only)
- *
- * 2. Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function
- *
- *
- * Basic Processing mode (polling mode)
- * ====================================
- * 1. Enable the cryptographic processor using CRYP_Cmd() function.
- *
- * 2. Write the first blocks in the input FIFO (2 to 8 words) using
- * CRYP_DataIn() function.
- *
- * 3. Repeat the following sequence until the complete message has been
- * processed:
- *
- * a) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus()
- * function), then read the OUT-FIFO using CRYP_DataOut() function
- * (1 block or until the FIFO is empty)
- *
- * b) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus()
- * function then write the IN FIFO using CRYP_DataIn() function
- * (1 block or until the FIFO is full)
- *
- * 4. At the end of the processing, CRYP_FLAG_BUSY flag will be reset and
- * both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is
- * reset). You can disable the peripheral using CRYP_Cmd() function.
- *
- * Interrupts Processing mode
- * ===========================
- * In this mode, Processing is done when the data are transferred by the
- * CPU during interrupts.
- *
- * 1. Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using
- * CRYP_ITConfig() function.
- *
- * 2. Enable the cryptographic processor using CRYP_Cmd() function.
- *
- * 3. In the CRYP_IT_INI interrupt handler : load the input message into the
- * IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a
- * time, or load data until the IN FIFO is full. When the last word of
- * the message has been entered into the IN FIFO, disable the CRYP_IT_INI
- * interrupt (using CRYP_ITConfig() function).
- *
- * 4. In the CRYP_IT_OUTI interrupt handler : read the output message from
- * the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or
- * 4 words) at a time or read data until the FIFO is empty.
- * When the last word has been read, INIM=0, BUSY=0 and both FIFOs are
- * empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset).
- * You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig()
- * function) and you can disable the peripheral using CRYP_Cmd() function.
- *
- * DMA Processing mode
- * ====================
- * In this mode, Processing is done when the DMA is used to transfer the
- * data from/to the memory.
- *
- * 1. Configure the DMA controller to transfer the input data from the
- * memory using DMA_Init() function.
- * The transfer length is the length of the message.
- * As message padding is not managed by the peripheral, the message
- * length must be an entire number of blocks. The data are transferred
- * in burst mode. The burst length is 4 words in the AES and 2 or 4
- * words in the DES/TDES. The DMA should be configured to set an
- * interrupt on transfer completion of the output data to indicate that
- * the processing is finished.
- * Refer to DMA peripheral driver for more details.
- *
- * 2. Enable the cryptographic processor using CRYP_Cmd() function.
- * Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT
- * using CRYP_DMACmd() function.
- *
- * 3. All the transfers and processing are managed by the DMA and the
- * cryptographic processor. The DMA transfer complete interrupt indicates
- * that the processing is complete. Both FIFOs are normally empty and
- * CRYP_FLAG_BUSY flag is reset.
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_cryp.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRYP
- * @brief CRYP driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define FLAG_MASK ((uint8_t)0x20)
-#define MAX_TIMEOUT ((uint16_t)0xFFFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRYP_Private_Functions
- * @{
- */
-
-/** @defgroup CRYP_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- Initialization and Configuration functions
- ===============================================================================
- This section provides functions allowing to
- - Initialize the cryptographic Processor using CRYP_Init() function
- - Encrypt or Decrypt
- - mode : TDES-ECB, TDES-CBC,
- DES-ECB, DES-CBC,
- AES-ECB, AES-CBC, AES-CTR, AES-Key
- - DataType : 32-bit data, 16-bit data, bit data or bit-string
- - Key Size (only in AES modes)
- - Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function
- - Configure the Initialization Vectors(IV) for CBC and CTR modes using
- CRYP_IVInit() function.
- - Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function.
- - Enable or disable the CRYP Processor using CRYP_Cmd() function
-
-
-@endverbatim
- * @{
- */
-/**
- * @brief Deinitializes the CRYP peripheral registers to their default reset values
- * @param None
- * @retval None
- */
-void CRYP_DeInit(void)
-{
- /* Enable CRYP reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE);
-
- /* Release CRYP from reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE);
-}
-
-/**
- * @brief Initializes the CRYP peripheral according to the specified parameters
- * in the CRYP_InitStruct.
- * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains
- * the configuration information for the CRYP peripheral.
- * @retval None
- */
-void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct)
-{
- /* Check the parameters */
- assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode));
- assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType));
- assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir));
-
- /* Select Algorithm mode*/
- CRYP->CR &= ~CRYP_CR_ALGOMODE;
- CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode;
-
- /* Select dataType */
- CRYP->CR &= ~CRYP_CR_DATATYPE;
- CRYP->CR |= CRYP_InitStruct->CRYP_DataType;
-
- /* select Key size (used only with AES algorithm) */
- if ((CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_ECB) ||
- (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CBC) ||
- (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CTR) ||
- (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_Key))
- {
- assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize));
- CRYP->CR &= ~CRYP_CR_KEYSIZE;
- CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be
- configured once the key has
- been prepared */
- }
-
- /* Select data Direction */
- CRYP->CR &= ~CRYP_CR_ALGODIR;
- CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir;
-}
-
-/**
- * @brief Fills each CRYP_InitStruct member with its default value.
- * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct)
-{
- /* Initialize the CRYP_AlgoDir member */
- CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
-
- /* initialize the CRYP_AlgoMode member */
- CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB;
-
- /* initialize the CRYP_DataType member */
- CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b;
-
- /* Initialize the CRYP_KeySize member */
- CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b;
-}
-
-/**
- * @brief Initializes the CRYP Keys according to the specified parameters in
- * the CRYP_KeyInitStruct.
- * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that
- * contains the configuration information for the CRYP Keys.
- * @retval None
- */
-void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
-{
- /* Key Initialisation */
- CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left;
- CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right;
- CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left;
- CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right;
- CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left;
- CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right;
- CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left;
- CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right;
-}
-
-/**
- * @brief Fills each CRYP_KeyInitStruct member with its default value.
- * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
-{
- CRYP_KeyInitStruct->CRYP_Key0Left = 0;
- CRYP_KeyInitStruct->CRYP_Key0Right = 0;
- CRYP_KeyInitStruct->CRYP_Key1Left = 0;
- CRYP_KeyInitStruct->CRYP_Key1Right = 0;
- CRYP_KeyInitStruct->CRYP_Key2Left = 0;
- CRYP_KeyInitStruct->CRYP_Key2Right = 0;
- CRYP_KeyInitStruct->CRYP_Key3Left = 0;
- CRYP_KeyInitStruct->CRYP_Key3Right = 0;
-}
-/**
- * @brief Initializes the CRYP Initialization Vectors(IV) according to the
- * specified parameters in the CRYP_IVInitStruct.
- * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains
- * the configuration information for the CRYP Initialization Vectors(IV).
- * @retval None
- */
-void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)
-{
- CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left;
- CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right;
- CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left;
- CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right;
-}
-
-/**
- * @brief Fills each CRYP_IVInitStruct member with its default value.
- * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization
- * Vectors(IV) structure which will be initialized.
- * @retval None
- */
-void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)
-{
- CRYP_IVInitStruct->CRYP_IV0Left = 0;
- CRYP_IVInitStruct->CRYP_IV0Right = 0;
- CRYP_IVInitStruct->CRYP_IV1Left = 0;
- CRYP_IVInitStruct->CRYP_IV1Right = 0;
-}
-
-/**
- * @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the
- * FIFOs are reset)
- * @note The FIFOs must be flushed only when BUSY flag is reset.
- * @param None
- * @retval None
- */
-void CRYP_FIFOFlush(void)
-{
- /* Reset the read and write pointers of the FIFOs */
- CRYP->CR |= CRYP_CR_FFLUSH;
-}
-
-/**
- * @brief Enables or disables the CRYP peripheral.
- * @param NewState: new state of the CRYP peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRYP_Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Cryptographic processor */
- CRYP->CR |= CRYP_CR_CRYPEN;
- }
- else
- {
- /* Disable the Cryptographic processor */
- CRYP->CR &= ~CRYP_CR_CRYPEN;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup CRYP_Group2 CRYP Data processing functions
- * @brief CRYP Data processing functions
- *
-@verbatim
- ===============================================================================
- CRYP Data processing functions
- ===============================================================================
- This section provides functions allowing the encryption and decryption
- operations:
- - Enter data to be treated in the IN FIFO : using CRYP_DataIn() function.
- - Get the data result from the OUT FIFO : using CRYP_DataOut() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes data in the Data Input register (DIN).
- * @note After the DIN register has been read once or several times,
- * the FIFO must be flushed (using CRYP_FIFOFlush() function).
- * @param Data: data to write in Data Input register
- * @retval None
- */
-void CRYP_DataIn(uint32_t Data)
-{
- CRYP->DR = Data;
-}
-
-/**
- * @brief Returns the last data entered into the output FIFO.
- * @param None
- * @retval Last data entered into the output FIFO.
- */
-uint32_t CRYP_DataOut(void)
-{
- return CRYP->DOUT;
-}
-/**
- * @}
- */
-
-/** @defgroup CRYP_Group3 Context swapping functions
- * @brief Context swapping functions
- *
-@verbatim
- ===============================================================================
- Context swapping functions
- ===============================================================================
-
- This section provides functions allowing to save and store CRYP Context
-
- It is possible to interrupt an encryption/ decryption/ key generation process
- to perform another processing with a higher priority, and to complete the
- interrupted process later on, when the higher-priority task is complete. To do
- so, the context of the interrupted task must be saved from the CRYP registers
- to memory, and then be restored from memory to the CRYP registers.
-
- 1. To save the current context, use CRYP_SaveContext() function
- 2. To restore the saved context, use CRYP_RestoreContext() function
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Saves the CRYP peripheral Context.
- * @note This function stops DMA transfer before to save the context. After
- * restoring the context, you have to enable the DMA again (if the DMA
- * was previously used).
- * @param CRYP_ContextSave: pointer to a CRYP_Context structure that contains
- * the repository for current context.
- * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that
- * contains the configuration information for the CRYP Keys.
- * @retval None
- */
-ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
- CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
-{
- __IO uint32_t timeout = 0;
- uint32_t ckeckmask = 0, bitstatus;
- ErrorStatus status = ERROR;
-
- /* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */
- CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN;
-
- /* Wait until both the IN and OUT FIFOs are empty
- (IFEM=1 and OFNE=0 in the CRYP_SR register) and the
- BUSY bit is cleared. */
-
- if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */
- {
- ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY ;
- }
- else /* AES or DES */
- {
- ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE;
- }
-
- do
- {
- bitstatus = CRYP->SR & ckeckmask;
- timeout++;
- }
- while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM));
-
- if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM)
- {
- status = ERROR;
- }
- else
- {
- /* Stop DMA transfers on the OUT FIFO by
- - writing the DOEN bit to 0 in the CRYP_DMACR register
- - and clear the CRYPEN bit. */
-
- CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN;
- CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN;
-
- /* Save the current configuration (bits [9:2] in the CRYP_CR register) */
- CRYP_ContextSave->CR_bits9to2 = CRYP->CR & (CRYP_CR_KEYSIZE |
- CRYP_CR_DATATYPE |
- CRYP_CR_ALGOMODE |
- CRYP_CR_ALGODIR);
-
- /* and, if not in ECB mode, the initialization vectors. */
- CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR;
- CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR;
- CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR;
- CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR;
-
- /* save The key value */
- CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left;
- CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right;
- CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left;
- CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right;
- CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left;
- CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right;
- CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left;
- CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right;
-
- /* When needed, save the DMA status (pointers for IN and OUT messages,
- number of remaining bytes, etc.) */
-
- status = SUCCESS;
- }
-
- return status;
-}
-
-/**
- * @brief Restores the CRYP peripheral Context.
- * @note Since teh DMA transfer is stopped in CRYP_SaveContext() function,
- * after restoring the context, you have to enable the DMA again (if the
- * DMA was previously used).
- * @param CRYP_ContextRestore: pointer to a CRYP_Context structure that contains
- * the repository for saved context.
- * @note The data that were saved during context saving must be rewrited into
- * the IN FIFO.
- * @retval None
- */
-void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore)
-{
-
- /* Configure the processor with the saved configuration */
- CRYP->CR = CRYP_ContextRestore->CR_bits9to2;
-
- /* restore The key value */
- CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR;
- CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR;
- CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR;
- CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR;
- CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR;
- CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR;
- CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR;
- CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR;
-
- /* and the initialization vectors. */
- CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR;
- CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR;
- CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR;
- CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR;
-
- /* Enable the cryptographic processor */
- CRYP->CR |= CRYP_CR_CRYPEN;
-}
-/**
- * @}
- */
-
-/** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function
- * @brief CRYP's DMA interface Configuration function
- *
-@verbatim
- ===============================================================================
- CRYP's DMA interface Configuration function
- ===============================================================================
-
- This section provides functions allowing to configure the DMA interface for
- CRYP data input and output transfer.
-
- When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be
- transferred:
- - From memory to the CRYP IN FIFO using the DMA peripheral by enabling
- the CRYP_DMAReq_DataIN request.
- - From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling
- the CRYP_DMAReq_DataOUT request.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the CRYP DMA interface.
- * @param CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer
- * @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer
- * @param NewState: new state of the selected CRYP DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected CRYP DMA request */
- CRYP->DMACR |= CRYP_DMAReq;
- }
- else
- {
- /* Disable the selected CRYP DMA request */
- CRYP->DMACR &= (uint8_t)~CRYP_DMAReq;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup CRYP_Group5 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
-
- This section provides functions allowing to configure the CRYP Interrupts and
- to get the status and Interrupts pending bits.
-
- The CRYP provides 2 Interrupts sources and 7 Flags:
-
- Flags :
- -------
-
- 1. CRYP_FLAG_IFEM : Set when Input FIFO is empty.
- This Flag is cleared only by hardware.
-
- 2. CRYP_FLAG_IFNF : Set when Input FIFO is not full.
- This Flag is cleared only by hardware.
-
-
- 3. CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending
- it gives the raw interrupt state prior to masking
- of the input FIFO service interrupt.
- This Flag is cleared only by hardware.
-
- 4. CRYP_FLAG_OFNE : Set when Output FIFO not empty.
- This Flag is cleared only by hardware.
-
- 5. CRYP_FLAG_OFFU : Set when Output FIFO is full.
- This Flag is cleared only by hardware.
-
- 6. CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending
- it gives the raw interrupt state prior to masking
- of the output FIFO service interrupt.
- This Flag is cleared only by hardware.
-
- 7. CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a
- block of data or a key preparation (for AES
- decryption).
- This Flag is cleared only by hardware.
- To clear it, the CRYP core must be disabled and the
- last processing has completed.
-
- Interrupts :
- ------------
-
- 1. CRYP_IT_INI : The input FIFO service interrupt is asserted when there
- are less than 4 words in the input FIFO.
- This interrupt is associated to CRYP_FLAG_INRIS flag.
-
- @note This interrupt is cleared by performing write operations
- to the input FIFO until it holds 4 or more words. The
- input FIFO service interrupt INMIS is enabled with the
- CRYP enable bit. Consequently, when CRYP is disabled, the
- INMIS signal is low even if the input FIFO is empty.
-
-
-
- 2. CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there
- is one or more (32-bit word) data items in the output FIFO.
- This interrupt is associated to CRYP_FLAG_OUTRIS flag.
-
- @note This interrupt is cleared by reading data from the output
- FIFO until there is no valid (32-bit) word left (that is,
- the interrupt follows the state of the OFNE (output FIFO
- not empty) flag).
-
-
- Managing the CRYP controller events :
- ------------------------------------
- The user should identify which mode will be used in his application to manage
- the CRYP controller events: Polling mode or Interrupt mode.
-
- 1. In the Polling Mode it is advised to use the following functions:
- - CRYP_GetFlagStatus() : to check if flags events occur.
-
- @note The CRYPT flags do not need to be cleared since they are cleared as
- soon as the associated event are reset.
-
-
- 2. In the Interrupt Mode it is advised to use the following functions:
- - CRYP_ITConfig() : to enable or disable the interrupt source.
- - CRYP_GetITStatus() : to check if Interrupt occurs.
-
- @note The CRYPT interrupts have no pending bits, the interrupt is cleared as
- soon as the associated event is reset.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified CRYP interrupts.
- * @param CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg CRYP_IT_INI: Input FIFO interrupt
- * @arg CRYP_IT_OUTI: Output FIFO interrupt
- * @param NewState: new state of the specified CRYP interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CRYP_CONFIG_IT(CRYP_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected CRYP interrupt */
- CRYP->IMSCR |= CRYP_IT;
- }
- else
- {
- /* Disable the selected CRYP interrupt */
- CRYP->IMSCR &= (uint8_t)~CRYP_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified CRYP interrupt has occurred or not.
- * @note This function checks the status of the masked interrupt (i.e the
- * interrupt should be previously enabled).
- * @param CRYP_IT: specifies the CRYP (masked) interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CRYP_IT_INI: Input FIFO interrupt
- * @arg CRYP_IT_OUTI: Output FIFO interrupt
- * @retval The new state of CRYP_IT (SET or RESET).
- */
-ITStatus CRYP_GetITStatus(uint8_t CRYP_IT)
-{
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_CRYP_GET_IT(CRYP_IT));
-
- /* Check the status of the specified CRYP interrupt */
- if ((CRYP->MISR & CRYP_IT) != (uint8_t)RESET)
- {
- /* CRYP_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* CRYP_IT is reset */
- bitstatus = RESET;
- }
- /* Return the CRYP_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Checks whether the specified CRYP flag is set or not.
- * @param CRYP_FLAG: specifies the CRYP flag to check.
- * This parameter can be one of the following values:
- * @arg CRYP_FLAG_IFEM: Input FIFO Empty flag.
- * @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag.
- * @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag.
- * @arg CRYP_FLAG_OFFU: Output FIFO Full flag.
- * @arg CRYP_FLAG_BUSY: Busy flag.
- * @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag.
- * @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag.
- * @retval The new state of CRYP_FLAG (SET or RESET).
- */
-FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tempreg = 0;
-
- /* Check the parameters */
- assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG));
-
- /* check if the FLAG is in RISR register */
- if ((CRYP_FLAG & FLAG_MASK) != 0x00)
- {
- tempreg = CRYP->RISR;
- }
- else /* The FLAG is in SR register */
- {
- tempreg = CRYP->SR;
- }
-
-
- /* Check the status of the specified CRYP flag */
- if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET)
- {
- /* CRYP_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CRYP_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the CRYP_FLAG status */
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_cryp_aes.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides high level functions to encrypt and decrypt an
- * input message using AES in ECB/CBC/CTR modes.
- * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
- * peripheral.
- *
- * @verbatim
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * 1. Enable The CRYP controller clock using
- * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
- *
- * 2. Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB()
- * function.
- *
- * 3. Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC()
- * function.
- *
- * 4. Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR()
- * function.
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_cryp.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRYP
- * @brief CRYP driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define AESBUSY_TIMEOUT ((uint32_t) 0x00010000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRYP_Private_Functions
- * @{
- */
-
-/** @defgroup CRYP_Group6 High Level AES functions
- * @brief High Level AES functions
- *
-@verbatim
- ===============================================================================
- High Level AES functions
- ===============================================================================
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Encrypt and decrypt using AES in ECB Mode
- * @param Mode: encryption or decryption Mode.
- * This parameter can be one of the following values:
- * @arg MODE_ENCRYPT: Encryption
- * @arg MODE_DECRYPT: Decryption
- * @param Key: Key used for AES algorithm.
- * @param Keysize: length of the Key, must be a 128, 192 or 256.
- * @param Input: pointer to the Input buffer.
- * @param Ilength: length of the Input buffer, must be a multiple of 16.
- * @param Output: pointer to the returned buffer.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Operation done
- * - ERROR: Operation failed
- */
-ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize,
- uint8_t* Input, uint32_t Ilength, uint8_t* Output)
-{
- CRYP_InitTypeDef AES_CRYP_InitStructure;
- CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
- __IO uint32_t counter = 0;
- uint32_t busystatus = 0;
- ErrorStatus status = SUCCESS;
- uint32_t keyaddr = (uint32_t)Key;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
- uint32_t i = 0;
-
- /* Crypto structures initialisation*/
- CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
-
- switch(Keysize)
- {
- case 128:
- AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
- AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
- break;
- case 192:
- AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b;
- AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
- break;
- case 256:
- AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b;
- AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
- break;
- default:
- break;
- }
-
- /*------------------ AES Decryption ------------------*/
- if(Mode == MODE_DECRYPT) /* AES decryption */
- {
- /* Flush IN/OUT FIFOs */
- CRYP_FIFOFlush();
-
- /* Crypto Init for Key preparation for decryption process */
- AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
- AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key;
- AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b;
- CRYP_Init(&AES_CRYP_InitStructure);
-
- /* Key Initialisation */
- CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- /* wait until the Busy flag is RESET */
- do
- {
- busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
- counter++;
- }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
- /* Crypto Init for decryption process */
- AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
- }
- }
- /*------------------ AES Encryption ------------------*/
- else /* AES encryption */
- {
-
- CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
-
- /* Crypto Init for Encryption process */
- AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
- }
-
- AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB;
- AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
- CRYP_Init(&AES_CRYP_InitStructure);
-
- /* Flush IN/OUT FIFOs */
- CRYP_FIFOFlush();
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- for(i=0; ((i<Ilength) && (status != ERROR)); i+=16)
- {
-
- /* Write the Input block in the IN FIFO */
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
-
- /* Wait until the complete message has been processed */
- counter = 0;
- do
- {
- busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
- counter++;
- }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
-
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- }
- }
-
- /* Disable Crypto */
- CRYP_Cmd(DISABLE);
-
- return status;
-}
-
-/**
- * @brief Encrypt and decrypt using AES in CBC Mode
- * @param Mode: encryption or decryption Mode.
- * This parameter can be one of the following values:
- * @arg MODE_ENCRYPT: Encryption
- * @arg MODE_DECRYPT: Decryption
- * @param InitVectors: Initialisation Vectors used for AES algorithm.
- * @param Key: Key used for AES algorithm.
- * @param Keysize: length of the Key, must be a 128, 192 or 256.
- * @param Input: pointer to the Input buffer.
- * @param Ilength: length of the Input buffer, must be a multiple of 16.
- * @param Output: pointer to the returned buffer.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Operation done
- * - ERROR: Operation failed
- */
-ErrorStatus CRYP_AES_CBC(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key,
- uint16_t Keysize, uint8_t *Input, uint32_t Ilength,
- uint8_t *Output)
-{
- CRYP_InitTypeDef AES_CRYP_InitStructure;
- CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
- CRYP_IVInitTypeDef AES_CRYP_IVInitStructure;
- __IO uint32_t counter = 0;
- uint32_t busystatus = 0;
- ErrorStatus status = SUCCESS;
- uint32_t keyaddr = (uint32_t)Key;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
- uint32_t ivaddr = (uint32_t)InitVectors;
- uint32_t i = 0;
-
- /* Crypto structures initialisation*/
- CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
-
- switch(Keysize)
- {
- case 128:
- AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
- AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
- break;
- case 192:
- AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b;
- AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
- break;
- case 256:
- AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b;
- AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
- break;
- default:
- break;
- }
-
- /* CRYP Initialization Vectors */
- AES_CRYP_IVInitStructure.CRYP_IV0Left = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- AES_CRYP_IVInitStructure.CRYP_IV0Right= __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- AES_CRYP_IVInitStructure.CRYP_IV1Left = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- AES_CRYP_IVInitStructure.CRYP_IV1Right= __REV(*(uint32_t*)(ivaddr));
-
-
- /*------------------ AES Decryption ------------------*/
- if(Mode == MODE_DECRYPT) /* AES decryption */
- {
- /* Flush IN/OUT FIFOs */
- CRYP_FIFOFlush();
-
- /* Crypto Init for Key preparation for decryption process */
- AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
- AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key;
- AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b;
-
- CRYP_Init(&AES_CRYP_InitStructure);
-
- /* Key Initialisation */
- CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- /* wait until the Busy flag is RESET */
- do
- {
- busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
- counter++;
- }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
- /* Crypto Init for decryption process */
- AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
- }
- }
- /*------------------ AES Encryption ------------------*/
- else /* AES encryption */
- {
- CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
-
- /* Crypto Init for Encryption process */
- AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
- }
- AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CBC;
- AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
- CRYP_Init(&AES_CRYP_InitStructure);
-
- /* CRYP Initialization Vectors */
- CRYP_IVInit(&AES_CRYP_IVInitStructure);
-
- /* Flush IN/OUT FIFOs */
- CRYP_FIFOFlush();
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
-
- for(i=0; ((i<Ilength) && (status != ERROR)); i+=16)
- {
-
- /* Write the Input block in the IN FIFO */
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- /* Wait until the complete message has been processed */
- counter = 0;
- do
- {
- busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
- counter++;
- }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
-
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- }
- }
-
- /* Disable Crypto */
- CRYP_Cmd(DISABLE);
-
- return status;
-}
-
-/**
- * @brief Encrypt and decrypt using AES in CTR Mode
- * @param Mode: encryption or decryption Mode.
- * This parameter can be one of the following values:
- * @arg MODE_ENCRYPT: Encryption
- * @arg MODE_DECRYPT: Decryption
- * @param InitVectors: Initialisation Vectors used for AES algorithm.
- * @param Key: Key used for AES algorithm.
- * @param Keysize: length of the Key, must be a 128, 192 or 256.
- * @param Input: pointer to the Input buffer.
- * @param Ilength: length of the Input buffer, must be a multiple of 16.
- * @param Output: pointer to the returned buffer.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Operation done
- * - ERROR: Operation failed
- */
-ErrorStatus CRYP_AES_CTR(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key,
- uint16_t Keysize, uint8_t *Input, uint32_t Ilength,
- uint8_t *Output)
-{
- CRYP_InitTypeDef AES_CRYP_InitStructure;
- CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
- CRYP_IVInitTypeDef AES_CRYP_IVInitStructure;
- __IO uint32_t counter = 0;
- uint32_t busystatus = 0;
- ErrorStatus status = SUCCESS;
- uint32_t keyaddr = (uint32_t)Key;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
- uint32_t ivaddr = (uint32_t)InitVectors;
- uint32_t i = 0;
-
- /* Crypto structures initialisation*/
- CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
-
- switch(Keysize)
- {
- case 128:
- AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
- AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
- break;
- case 192:
- AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b;
- AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
- break;
- case 256:
- AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b;
- AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
- break;
- default:
- break;
- }
- /* CRYP Initialization Vectors */
- AES_CRYP_IVInitStructure.CRYP_IV0Left = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- AES_CRYP_IVInitStructure.CRYP_IV0Right= __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- AES_CRYP_IVInitStructure.CRYP_IV1Left = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- AES_CRYP_IVInitStructure.CRYP_IV1Right= __REV(*(uint32_t*)(ivaddr));
-
- /* Key Initialisation */
- CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
-
- /*------------------ AES Decryption ------------------*/
- if(Mode == MODE_DECRYPT) /* AES decryption */
- {
- /* Crypto Init for decryption process */
- AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
- }
- /*------------------ AES Encryption ------------------*/
- else /* AES encryption */
- {
- /* Crypto Init for Encryption process */
- AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
- }
- AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CTR;
- AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
- CRYP_Init(&AES_CRYP_InitStructure);
-
- /* CRYP Initialization Vectors */
- CRYP_IVInit(&AES_CRYP_IVInitStructure);
-
- /* Flush IN/OUT FIFOs */
- CRYP_FIFOFlush();
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- for(i=0; ((i<Ilength) && (status != ERROR)); i+=16)
- {
-
- /* Write the Input block in the IN FIFO */
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- /* Wait until the complete message has been processed */
- counter = 0;
- do
- {
- busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
- counter++;
- }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
-
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- }
- }
- /* Disable Crypto */
- CRYP_Cmd(DISABLE);
-
- return status;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_cryp_des.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides high level functions to encrypt and decrypt an
- * input message using DES in ECB/CBC modes.
- * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
- * peripheral.
- *
- * @verbatim
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * 1. Enable The CRYP controller clock using
- * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
- *
- * 2. Encrypt and decrypt using DES in ECB Mode using CRYP_DES_ECB()
- * function.
- *
- * 3. Encrypt and decrypt using DES in CBC Mode using CRYP_DES_CBC()
- * function.
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_cryp.h"
-
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRYP
- * @brief CRYP driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define DESBUSY_TIMEOUT ((uint32_t) 0x00010000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-
-/** @defgroup CRYP_Private_Functions
- * @{
- */
-
-/** @defgroup CRYP_Group8 High Level DES functions
- * @brief High Level DES functions
- *
-@verbatim
- ===============================================================================
- High Level DES functions
- ===============================================================================
-@endverbatim
- * @{
- */
-
-/**
- * @brief Encrypt and decrypt using DES in ECB Mode
- * @param Mode: encryption or decryption Mode.
- * This parameter can be one of the following values:
- * @arg MODE_ENCRYPT: Encryption
- * @arg MODE_DECRYPT: Decryption
- * @param Key: Key used for DES algorithm.
- * @param Ilength: length of the Input buffer, must be a multiple of 8.
- * @param Input: pointer to the Input buffer.
- * @param Output: pointer to the returned buffer.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Operation done
- * - ERROR: Operation failed
- */
-ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input,
- uint32_t Ilength, uint8_t *Output)
-{
- CRYP_InitTypeDef DES_CRYP_InitStructure;
- CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure;
- __IO uint32_t counter = 0;
- uint32_t busystatus = 0;
- ErrorStatus status = SUCCESS;
- uint32_t keyaddr = (uint32_t)Key;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
- uint32_t i = 0;
-
- /* Crypto structures initialisation*/
- CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure);
-
- /* Crypto Init for Encryption process */
- if( Mode == MODE_ENCRYPT ) /* DES encryption */
- {
- DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
- }
- else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */
- {
- DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
- }
-
- DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB;
- DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
- CRYP_Init(&DES_CRYP_InitStructure);
-
- /* Key Initialisation */
- DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
- CRYP_KeyInit(& DES_CRYP_KeyInitStructure);
-
- /* Flush IN/OUT FIFO */
- CRYP_FIFOFlush();
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
- {
-
- /* Write the Input block in the Input FIFO */
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
-
-/* Wait until the complete message has been processed */
- counter = 0;
- do
- {
- busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
- counter++;
- }while ((counter != DESBUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
-
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- }
- }
-
- /* Disable Crypto */
- CRYP_Cmd(DISABLE);
-
- return status;
-}
-
-/**
- * @brief Encrypt and decrypt using DES in CBC Mode
- * @param Mode: encryption or decryption Mode.
- * This parameter can be one of the following values:
- * @arg MODE_ENCRYPT: Encryption
- * @arg MODE_DECRYPT: Decryption
- * @param Key: Key used for DES algorithm.
- * @param InitVectors: Initialisation Vectors used for DES algorithm.
- * @param Ilength: length of the Input buffer, must be a multiple of 8.
- * @param Input: pointer to the Input buffer.
- * @param Output: pointer to the returned buffer.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Operation done
- * - ERROR: Operation failed
- */
-ErrorStatus CRYP_DES_CBC(uint8_t Mode, uint8_t Key[8], uint8_t InitVectors[8],
- uint8_t *Input, uint32_t Ilength, uint8_t *Output)
-{
- CRYP_InitTypeDef DES_CRYP_InitStructure;
- CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure;
- CRYP_IVInitTypeDef DES_CRYP_IVInitStructure;
- __IO uint32_t counter = 0;
- uint32_t busystatus = 0;
- ErrorStatus status = SUCCESS;
- uint32_t keyaddr = (uint32_t)Key;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
- uint32_t ivaddr = (uint32_t)InitVectors;
- uint32_t i = 0;
-
- /* Crypto structures initialisation*/
- CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure);
-
- /* Crypto Init for Encryption process */
- if(Mode == MODE_ENCRYPT) /* DES encryption */
- {
- DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
- }
- else /*if(Mode == MODE_DECRYPT)*/ /* DES decryption */
- {
- DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
- }
-
- DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_CBC;
- DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
- CRYP_Init(&DES_CRYP_InitStructure);
-
- /* Key Initialisation */
- DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
- CRYP_KeyInit(& DES_CRYP_KeyInitStructure);
-
- /* Initialization Vectors */
- DES_CRYP_IVInitStructure.CRYP_IV0Left = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- DES_CRYP_IVInitStructure.CRYP_IV0Right= __REV(*(uint32_t*)(ivaddr));
- CRYP_IVInit(&DES_CRYP_IVInitStructure);
-
- /* Flush IN/OUT FIFO */
- CRYP_FIFOFlush();
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
- {
- /* Write the Input block in the Input FIFO */
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
-
- /* Wait until the complete message has been processed */
- counter = 0;
- do
- {
- busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
- counter++;
- }while ((counter != DESBUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- }
- }
-
- /* Disable Crypto */
- CRYP_Cmd(DISABLE);
-
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_cryp_tdes.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides high level functions to encrypt and decrypt an
- * input message using TDES in ECB/CBC modes .
- * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
- * peripheral.
- *
- * @verbatim
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * 1. Enable The CRYP controller clock using
- * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
- *
- * 2. Encrypt and decrypt using TDES in ECB Mode using CRYP_TDES_ECB()
- * function.
- *
- * 3. Encrypt and decrypt using TDES in CBC Mode using CRYP_TDES_CBC()
- * function.
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_cryp.h"
-
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRYP
- * @brief CRYP driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define TDESBUSY_TIMEOUT ((uint32_t) 0x00010000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-
-/** @defgroup CRYP_Private_Functions
- * @{
- */
-
-/** @defgroup CRYP_Group7 High Level TDES functions
- * @brief High Level TDES functions
- *
-@verbatim
- ===============================================================================
- High Level TDES functions
- ===============================================================================
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Encrypt and decrypt using TDES in ECB Mode
- * @param Mode: encryption or decryption Mode.
- * This parameter can be one of the following values:
- * @arg MODE_ENCRYPT: Encryption
- * @arg MODE_DECRYPT: Decryption
- * @param Key: Key used for TDES algorithm.
- * @param Ilength: length of the Input buffer, must be a multiple of 8.
- * @param Input: pointer to the Input buffer.
- * @param Output: pointer to the returned buffer.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Operation done
- * - ERROR: Operation failed
- */
-ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input,
- uint32_t Ilength, uint8_t *Output)
-{
- CRYP_InitTypeDef TDES_CRYP_InitStructure;
- CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure;
- __IO uint32_t counter = 0;
- uint32_t busystatus = 0;
- ErrorStatus status = SUCCESS;
- uint32_t keyaddr = (uint32_t)Key;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
- uint32_t i = 0;
-
- /* Crypto structures initialisation*/
- CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure);
-
- /* Crypto Init for Encryption process */
- if(Mode == MODE_ENCRYPT) /* TDES encryption */
- {
- TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
- }
- else /*if(Mode == MODE_DECRYPT)*/ /* TDES decryption */
- {
- TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
- }
-
- TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB;
- TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
- CRYP_Init(&TDES_CRYP_InitStructure);
-
- /* Key Initialisation */
- TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
- CRYP_KeyInit(& TDES_CRYP_KeyInitStructure);
-
- /* Flush IN/OUT FIFO */
- CRYP_FIFOFlush();
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
- {
- /* Write the Input block in the Input FIFO */
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
-
- /* Wait until the complete message has been processed */
- counter = 0;
- do
- {
- busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
- counter++;
- }while ((counter != TDESBUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
-
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- }
- }
-
- /* Disable Crypto */
- CRYP_Cmd(DISABLE);
-
- return status;
-}
-
-/**
- * @brief Encrypt and decrypt using TDES in CBC Mode
- * @param Mode: encryption or decryption Mode.
- * This parameter can be one of the following values:
- * @arg MODE_ENCRYPT: Encryption
- * @arg MODE_DECRYPT: Decryption
- * @param Key: Key used for TDES algorithm.
- * @param InitVectors: Initialisation Vectors used for TDES algorithm.
- * @param Input: pointer to the Input buffer.
- * @param Ilength: length of the Input buffer, must be a multiple of 8.
- * @param Output: pointer to the returned buffer.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Operation done
- * - ERROR: Operation failed
- */
-ErrorStatus CRYP_TDES_CBC(uint8_t Mode, uint8_t Key[24], uint8_t InitVectors[8],
- uint8_t *Input, uint32_t Ilength, uint8_t *Output)
-{
- CRYP_InitTypeDef TDES_CRYP_InitStructure;
- CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure;
- CRYP_IVInitTypeDef TDES_CRYP_IVInitStructure;
- __IO uint32_t counter = 0;
- uint32_t busystatus = 0;
- ErrorStatus status = SUCCESS;
- uint32_t keyaddr = (uint32_t)Key;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
- uint32_t ivaddr = (uint32_t)InitVectors;
- uint32_t i = 0;
-
- /* Crypto structures initialisation*/
- CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure);
-
- /* Crypto Init for Encryption process */
- if(Mode == MODE_ENCRYPT) /* TDES encryption */
- {
- TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
- }
- else
- {
- TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
- }
- TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_CBC;
- TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
-
- CRYP_Init(&TDES_CRYP_InitStructure);
-
- /* Key Initialisation */
- TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
- CRYP_KeyInit(& TDES_CRYP_KeyInitStructure);
-
- /* Initialization Vectors */
- TDES_CRYP_IVInitStructure.CRYP_IV0Left = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- TDES_CRYP_IVInitStructure.CRYP_IV0Right= __REV(*(uint32_t*)(ivaddr));
- CRYP_IVInit(&TDES_CRYP_IVInitStructure);
-
- /* Flush IN/OUT FIFO */
- CRYP_FIFOFlush();
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
- {
- /* Write the Input block in the Input FIFO */
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
-
- /* Wait until the complete message has been processed */
- counter = 0;
- do
- {
- busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
- counter++;
- }while ((counter != TDESBUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
-
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- }
- }
-
- /* Disable Crypto */
- CRYP_Cmd(DISABLE);
-
- return status;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_dac.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Digital-to-Analog Converter (DAC) peripheral:
- * - DAC channels configuration: trigger, output buffer, data format
- * - DMA management
- * - Interrupts and flags management
- *
- * @verbatim
- *
- * ===================================================================
- * DAC Peripheral features
- * ===================================================================
- *
- * DAC Channels
- * =============
- * The device integrates two 12-bit Digital Analog Converters that can
- * be used independently or simultaneously (dual mode):
- * 1- DAC channel1 with DAC_OUT1 (PA4) as output
- * 1- DAC channel2 with DAC_OUT2 (PA5) as output
- *
- * DAC Triggers
- * =============
- * Digital to Analog conversion can be non-triggered using DAC_Trigger_None
- * and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register
- * using DAC_SetChannel1Data() / DAC_SetChannel2Data() functions.
- *
- * Digital to Analog conversion can be triggered by:
- * 1- External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
- * The used pin (GPIOx_Pin9) must be configured in input mode.
- *
- * 2- Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
- * (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
- * The timer TRGO event should be selected using TIM_SelectOutputTrigger()
- *
- * 3- Software using DAC_Trigger_Software
- *
- * DAC Buffer mode feature
- * ========================
- * Each DAC channel integrates an output buffer that can be used to
- * reduce the output impedance, and to drive external loads directly
- * without having to add an external operational amplifier.
- * To enable, the output buffer use
- * DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
- *
- * Refer to the device datasheet for more details about output
- * impedance value with and without output buffer.
- *
- * DAC wave generation feature
- * =============================
- * Both DAC channels can be used to generate
- * 1- Noise wave using DAC_WaveGeneration_Noise
- * 2- Triangle wave using DAC_WaveGeneration_Triangle
- *
- * Wave generation can be disabled using DAC_WaveGeneration_None
- *
- * DAC data format
- * ================
- * The DAC data format can be:
- * 1- 8-bit right alignment using DAC_Align_8b_R
- * 2- 12-bit left alignment using DAC_Align_12b_L
- * 3- 12-bit right alignment using DAC_Align_12b_R
- *
- * DAC data value to voltage correspondence
- * ========================================
- * The analog output voltage on each DAC channel pin is determined
- * by the following equation:
- * DAC_OUTx = VREF+ * DOR / 4095
- * with DOR is the Data Output Register
- * VEF+ is the input voltage reference (refer to the device datasheet)
- * e.g. To set DAC_OUT1 to 0.7V, use
- * DAC_SetChannel1Data(DAC_Align_12b_R, 868);
- * Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
- *
- * DMA requests
- * =============
- * A DMA1 request can be generated when an external trigger (but not
- * a software trigger) occurs if DMA1 requests are enabled using
- * DAC_DMACmd()
- * DMA1 requests are mapped as following:
- * 1- DAC channel1 : mapped on DMA1 Stream5 channel7 which must be
- * already configured
- * 2- DAC channel2 : mapped on DMA1 Stream6 channel7 which must be
- * already configured
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * - DAC APB clock must be enabled to get write access to DAC
- * registers using
- * RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
- * - Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
- * - Configure the DAC channel using DAC_Init() function
- * - Enable the DAC channel using DAC_Cmd() function
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_dac.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DAC
- * @brief DAC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* CR register Mask */
-#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
-
-/* DAC Dual Channels SWTRIG masks */
-#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
-#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
-
-/* DHR registers offsets */
-#define DHR12R1_OFFSET ((uint32_t)0x00000008)
-#define DHR12R2_OFFSET ((uint32_t)0x00000014)
-#define DHR12RD_OFFSET ((uint32_t)0x00000020)
-
-/* DOR register offset */
-#define DOR_OFFSET ((uint32_t)0x0000002C)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DAC_Private_Functions
- * @{
- */
-
-/** @defgroup DAC_Group1 DAC channels configuration
- * @brief DAC channels configuration: trigger, output buffer, data format
- *
-@verbatim
- ===============================================================================
- DAC channels configuration: trigger, output buffer, data format
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the DAC peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void DAC_DeInit(void)
-{
- /* Enable DAC reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
- /* Release DAC from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
-}
-
-/**
- * @brief Initializes the DAC peripheral according to the specified parameters
- * in the DAC_InitStruct.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains
- * the configuration information for the specified DAC channel.
- * @retval None
- */
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
-{
- uint32_t tmpreg1 = 0, tmpreg2 = 0;
-
- /* Check the DAC parameters */
- assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
- assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
- assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
- assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
-
-/*---------------------------- DAC CR Configuration --------------------------*/
- /* Get the DAC CR value */
- tmpreg1 = DAC->CR;
- /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
- tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
- /* Configure for the selected DAC channel: buffer output, trigger,
- wave generation, mask/amplitude for wave generation */
- /* Set TSELx and TENx bits according to DAC_Trigger value */
- /* Set WAVEx bits according to DAC_WaveGeneration value */
- /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
- /* Set BOFFx bit according to DAC_OutputBuffer value */
- tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \
- DAC_InitStruct->DAC_OutputBuffer);
- /* Calculate CR register value depending on DAC_Channel */
- tmpreg1 |= tmpreg2 << DAC_Channel;
- /* Write to DAC CR */
- DAC->CR = tmpreg1;
-}
-
-/**
- * @brief Fills each DAC_InitStruct member with its default value.
- * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
-{
-/*--------------- Reset DAC init structure parameters values -----------------*/
- /* Initialize the DAC_Trigger member */
- DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
- /* Initialize the DAC_WaveGeneration member */
- DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
- /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
- /* Initialize the DAC_OutputBuffer member */
- DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
-}
-
-/**
- * @brief Enables or disables the specified DAC channel.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param NewState: new state of the DAC channel.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the DAC channel is enabled the trigger source can no more be modified.
- * @retval None
- */
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC channel */
- DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
- }
- else
- {
- /* Disable the selected DAC channel */
- DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
- }
-}
-
-/**
- * @brief Enables or disables the selected DAC channel software trigger.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param NewState: new state of the selected DAC channel software trigger.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable software trigger for the selected DAC channel */
- DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
- }
- else
- {
- /* Disable software trigger for the selected DAC channel */
- DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
- }
-}
-
-/**
- * @brief Enables or disables simultaneously the two DAC channels software triggers.
- * @param NewState: new state of the DAC channels software triggers.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable software trigger for both DAC channels */
- DAC->SWTRIGR |= DUAL_SWTRIG_SET;
- }
- else
- {
- /* Disable software trigger for both DAC channels */
- DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
- }
-}
-
-/**
- * @brief Enables or disables the selected DAC channel wave generation.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_Wave: specifies the wave type to enable or disable.
- * This parameter can be one of the following values:
- * @arg DAC_Wave_Noise: noise wave generation
- * @arg DAC_Wave_Triangle: triangle wave generation
- * @param NewState: new state of the selected DAC channel wave generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_WAVE(DAC_Wave));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected wave generation for the selected DAC channel */
- DAC->CR |= DAC_Wave << DAC_Channel;
- }
- else
- {
- /* Disable the selected wave generation for the selected DAC channel */
- DAC->CR &= ~(DAC_Wave << DAC_Channel);
- }
-}
-
-/**
- * @brief Set the specified data holding register value for DAC channel1.
- * @param DAC_Align: Specifies the data alignment for DAC channel1.
- * This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
- * @param Data: Data to be loaded in the selected data holding register.
- * @retval None
- */
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data));
-
- tmp = (uint32_t)DAC_BASE;
- tmp += DHR12R1_OFFSET + DAC_Align;
-
- /* Set the DAC channel1 selected data holding register */
- *(__IO uint32_t *) tmp = Data;
-}
-
-/**
- * @brief Set the specified data holding register value for DAC channel2.
- * @param DAC_Align: Specifies the data alignment for DAC channel2.
- * This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
- * @param Data: Data to be loaded in the selected data holding register.
- * @retval None
- */
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data));
-
- tmp = (uint32_t)DAC_BASE;
- tmp += DHR12R2_OFFSET + DAC_Align;
-
- /* Set the DAC channel2 selected data holding register */
- *(__IO uint32_t *)tmp = Data;
-}
-
-/**
- * @brief Set the specified data holding register value for dual channel DAC.
- * @param DAC_Align: Specifies the data alignment for dual channel DAC.
- * This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
- * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register.
- * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register.
- * @note In dual mode, a unique register access is required to write in both
- * DAC channels at the same time.
- * @retval None
- */
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
-{
- uint32_t data = 0, tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data1));
- assert_param(IS_DAC_DATA(Data2));
-
- /* Calculate and set dual DAC data holding register value */
- if (DAC_Align == DAC_Align_8b_R)
- {
- data = ((uint32_t)Data2 << 8) | Data1;
- }
- else
- {
- data = ((uint32_t)Data2 << 16) | Data1;
- }
-
- tmp = (uint32_t)DAC_BASE;
- tmp += DHR12RD_OFFSET + DAC_Align;
-
- /* Set the dual DAC selected data holding register */
- *(__IO uint32_t *)tmp = data;
-}
-
-/**
- * @brief Returns the last data output value of the selected DAC channel.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @retval The selected DAC channel data output value.
- */
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
-
- tmp = (uint32_t) DAC_BASE ;
- tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
-
- /* Returns the DAC channel data output register value */
- return (uint16_t) (*(__IO uint32_t*) tmp);
-}
-/**
- * @}
- */
-
-/** @defgroup DAC_Group2 DMA management functions
- * @brief DMA management functions
- *
-@verbatim
- ===============================================================================
- DMA management functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified DAC channel DMA request.
- * @note When enabled DMA1 is generated when an external trigger (EXTI Line9,
- * TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param NewState: new state of the selected DAC channel DMA request.
- * This parameter can be: ENABLE or DISABLE.
- * @note The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be
- * already configured.
- * @note The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be
- * already configured.
- * @retval None
- */
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC channel DMA request */
- DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
- }
- else
- {
- /* Disable the selected DAC channel DMA request */
- DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
- }
-}
-/**
- * @}
- */
-
-/** @defgroup DAC_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified DAC interrupts.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
- * This parameter can be the following values:
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
- * @note The DMA underrun occurs when a second external trigger arrives before the
- * acknowledgement for the first external trigger is received (first request).
- * @param NewState: new state of the specified DAC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_DAC_IT(DAC_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC interrupts */
- DAC->CR |= (DAC_IT << DAC_Channel);
- }
- else
- {
- /* Disable the selected DAC interrupts */
- DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
- }
-}
-
-/**
- * @brief Checks whether the specified DAC flag is set or not.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_FLAG: specifies the flag to check.
- * This parameter can be only of the following value:
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag
- * @note The DMA underrun occurs when a second external trigger arrives before the
- * acknowledgement for the first external trigger is received (first request).
- * @retval The new state of DAC_FLAG (SET or RESET).
- */
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_FLAG(DAC_FLAG));
-
- /* Check the status of the specified DAC flag */
- if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
- {
- /* DAC_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* DAC_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the DAC_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DAC channel's pending flags.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_FLAG: specifies the flag to clear.
- * This parameter can be of the following value:
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag
- * @note The DMA underrun occurs when a second external trigger arrives before the
- * acknowledgement for the first external trigger is received (first request).
- * @retval None
- */
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_FLAG(DAC_FLAG));
-
- /* Clear the selected DAC flags */
- DAC->SR = (DAC_FLAG << DAC_Channel);
-}
-
-/**
- * @brief Checks whether the specified DAC interrupt has occurred or not.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_IT: specifies the DAC interrupt source to check.
- * This parameter can be the following values:
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
- * @note The DMA underrun occurs when a second external trigger arrives before the
- * acknowledgement for the first external trigger is received (first request).
- * @retval The new state of DAC_IT (SET or RESET).
- */
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_IT(DAC_IT));
-
- /* Get the DAC_IT enable bit status */
- enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
-
- /* Check the status of the specified DAC interrupt */
- if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
- {
- /* DAC_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* DAC_IT is reset */
- bitstatus = RESET;
- }
- /* Return the DAC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DAC channel's interrupt pending bits.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_IT: specifies the DAC interrupt pending bit to clear.
- * This parameter can be the following values:
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
- * @note The DMA underrun occurs when a second external trigger arrives before the
- * acknowledgement for the first external trigger is received (first request).
- * @retval None
- */
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_IT(DAC_IT));
-
- /* Clear the selected DAC interrupt pending bits */
- DAC->SR = (DAC_IT << DAC_Channel);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_dbgmcu.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides all the DBGMCU firmware functions.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_dbgmcu.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DBGMCU
- * @brief DBGMCU driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DBGMCU_Private_Functions
- * @{
- */
-
-/**
- * @brief Returns the device revision identifier.
- * @param None
- * @retval Device revision identifier
- */
-uint32_t DBGMCU_GetREVID(void)
-{
- return(DBGMCU->IDCODE >> 16);
-}
-
-/**
- * @brief Returns the device identifier.
- * @param None
- * @retval Device identifier
- */
-uint32_t DBGMCU_GetDEVID(void)
-{
- return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
-}
-
-/**
- * @brief Configures low power mode behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the low power mode.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
- * @arg DBGMCU_STOP: Keep debugger connection during STOP mode
- * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
- * @param NewState: new state of the specified low power mode in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- DBGMCU->CR |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->CR &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the APB1 peripheral.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
- * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
- * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
- * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
- * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
- * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
- * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
- * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
- * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
- * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted.
- * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
- * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
- * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
- * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
- * @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted
- * @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted
- * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- DBGMCU->APB1FZ |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->APB1FZ &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the APB2 peripheral.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
- * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
- * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
- * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
- * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
- * @param NewState: new state of the specified peripheral in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- DBGMCU->APB2FZ |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->APB2FZ &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_dcmi.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the DCMI peripheral:
- * - Initialization and Configuration
- * - Image capture functions
- * - Interrupts and flags management
- *
- * @verbatim
- *
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- *
- * The sequence below describes how to use this driver to capture image
- * from a camera module connected to the DCMI Interface.
- * This sequence does not take into account the configuration of the
- * camera module, which should be made before to configure and enable
- * the DCMI to capture images.
- *
- * 1. Enable the clock for the DCMI and associated GPIOs using the following functions:
- * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE);
- * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
- *
- * 2. DCMI pins configuration
- * - Connect the involved DCMI pins to AF13 using the following function
- * GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI);
- * - Configure these DCMI pins in alternate function mode by calling the function
- * GPIO_Init();
- *
- * 3. Declare a DCMI_InitTypeDef structure, for example:
- * DCMI_InitTypeDef DCMI_InitStructure;
- * and fill the DCMI_InitStructure variable with the allowed values
- * of the structure member.
- *
- * 4. Initialize the DCMI interface by calling the function
- * DCMI_Init(&DCMI_InitStructure);
- *
- * 5. Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
- * register to the destination memory buffer.
- *
- * 6. Enable DCMI interface using the function
- * DCMI_Cmd(ENABLE);
- *
- * 7. Start the image capture using the function
- * DCMI_CaptureCmd(ENABLE);
- *
- * 8. At this stage the DCMI interface waits for the first start of frame,
- * then a DMA request is generated continuously/once (depending on the
- * mode used, Continuous/Snapshot) to transfer the received data into
- * the destination memory.
- *
- * @note If you need to capture only a rectangular window from the received
- * image, you have to use the DCMI_CROPConfig() function to configure
- * the coordinates and size of the window to be captured, then enable
- * the Crop feature using DCMI_CROPCmd(ENABLE);
- * In this case, the Crop configuration should be made before to enable
- * and start the DCMI interface.
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_dcmi.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DCMI
- * @brief DCMI driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DCMI_Private_Functions
- * @{
- */
-
-/** @defgroup DCMI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- Initialization and Configuration functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the DCMI registers to their default reset values.
- * @param None
- * @retval None
- */
-void DCMI_DeInit(void)
-{
- DCMI->CR = 0x0;
- DCMI->IER = 0x0;
- DCMI->ICR = 0x1F;
- DCMI->ESCR = 0x0;
- DCMI->ESUR = 0x0;
- DCMI->CWSTRTR = 0x0;
- DCMI->CWSIZER = 0x0;
-}
-
-/**
- * @brief Initializes the DCMI according to the specified parameters in the DCMI_InitStruct.
- * @param DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains
- * the configuration information for the DCMI.
- * @retval None
- */
-void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct)
-{
- uint32_t temp = 0x0;
-
- /* Check the parameters */
- assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode));
- assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode));
- assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity));
- assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity));
- assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity));
- assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate));
- assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode));
-
- /* The DCMI configuration registers should be programmed correctly before
- enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */
- DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE);
-
- /* Reset the old DCMI configuration */
- temp = DCMI->CR;
-
- temp &= ~((uint32_t)DCMI_CR_CM | DCMI_CR_ESS | DCMI_CR_PCKPOL |
- DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 |
- DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1);
-
- /* Sets the new configuration of the DCMI peripheral */
- temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode |
- DCMI_InitStruct->DCMI_SynchroMode |
- DCMI_InitStruct->DCMI_PCKPolarity |
- DCMI_InitStruct->DCMI_VSPolarity |
- DCMI_InitStruct->DCMI_HSPolarity |
- DCMI_InitStruct->DCMI_CaptureRate |
- DCMI_InitStruct->DCMI_ExtendedDataMode);
-
- DCMI->CR = temp;
-}
-
-/**
- * @brief Fills each DCMI_InitStruct member with its default value.
- * @param DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct)
-{
- /* Set the default configuration */
- DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous;
- DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware;
- DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling;
- DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low;
- DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low;
- DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame;
- DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b;
-}
-
-/**
- * @brief Initializes the DCMI peripheral CROP mode according to the specified
- * parameters in the DCMI_CROPInitStruct.
- * @note This function should be called before to enable and start the DCMI interface.
- * @param DCMI_CROPInitStruct: pointer to a DCMI_CROPInitTypeDef structure that
- * contains the configuration information for the DCMI peripheral CROP mode.
- * @retval None
- */
-void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct)
-{
- /* Sets the CROP window coordinates */
- DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount |
- ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16));
-
- /* Sets the CROP window size */
- DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount |
- ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16));
-}
-
-/**
- * @brief Enables or disables the DCMI Crop feature.
- * @note This function should be called before to enable and start the DCMI interface.
- * @param NewState: new state of the DCMI Crop feature.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_CROPCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DCMI Crop feature */
- DCMI->CR |= (uint32_t)DCMI_CR_CROP;
- }
- else
- {
- /* Disable the DCMI Crop feature */
- DCMI->CR &= ~(uint32_t)DCMI_CR_CROP;
- }
-}
-
-/**
- * @brief Sets the embedded synchronization codes
- * @param DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that
- * contains the embedded synchronization codes for the DCMI peripheral.
- * @retval None
- */
-void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct)
-{
- DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode |
- ((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)|
- ((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)|
- ((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24));
-}
-
-/**
- * @brief Enables or disables the DCMI JPEG format.
- * @note The Crop and Embedded Synchronization features cannot be used in this mode.
- * @param NewState: new state of the DCMI JPEG format.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_JPEGCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DCMI JPEG format */
- DCMI->CR |= (uint32_t)DCMI_CR_JPEG;
- }
- else
- {
- /* Disable the DCMI JPEG format */
- DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup DCMI_Group2 Image capture functions
- * @brief Image capture functions
- *
-@verbatim
- ===============================================================================
- Image capture functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the DCMI interface.
- * @param NewState: new state of the DCMI interface.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DCMI by setting ENABLE bit */
- DCMI->CR |= (uint32_t)DCMI_CR_ENABLE;
- }
- else
- {
- /* Disable the DCMI by clearing ENABLE bit */
- DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE;
- }
-}
-
-/**
- * @brief Enables or disables the DCMI Capture.
- * @param NewState: new state of the DCMI capture.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_CaptureCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DCMI Capture */
- DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE;
- }
- else
- {
- /* Disable the DCMI Capture */
- DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE;
- }
-}
-
-/**
- * @brief Reads the data stored in the DR register.
- * @param None
- * @retval Data register value
- */
-uint32_t DCMI_ReadData(void)
-{
- return DCMI->DR;
-}
-/**
- * @}
- */
-
-/** @defgroup DCMI_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the DCMI interface interrupts.
- * @param DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
- * @arg DCMI_IT_OVF: Overflow interrupt mask
- * @arg DCMI_IT_ERR: Synchronization error interrupt mask
- * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
- * @arg DCMI_IT_LINE: Line interrupt mask
- * @param NewState: new state of the specified DCMI interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DCMI_CONFIG_IT(DCMI_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt sources */
- DCMI->IER |= DCMI_IT;
- }
- else
- {
- /* Disable the Interrupt sources */
- DCMI->IER &= (uint16_t)(~DCMI_IT);
- }
-}
-
-/**
- * @brief Checks whether the DCMI interface flag is set or not.
- * @param DCMI_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
- * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask
- * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
- * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
- * @arg DCMI_FLAG_LINERI: Line Raw flag mask
- * @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask
- * @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask
- * @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask
- * @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask
- * @arg DCMI_FLAG_LINEMI: Line Masked flag mask
- * @arg DCMI_FLAG_HSYNC: HSYNC flag mask
- * @arg DCMI_FLAG_VSYNC: VSYNC flag mask
- * @arg DCMI_FLAG_FNE: Fifo not empty flag mask
- * @retval The new state of DCMI_FLAG (SET or RESET).
- */
-FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t dcmireg, tempreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG));
-
- /* Get the DCMI register index */
- dcmireg = (((uint16_t)DCMI_FLAG) >> 12);
-
- if (dcmireg == 0x01) /* The FLAG is in RISR register */
- {
- tempreg= DCMI->RISR;
- }
- else if (dcmireg == 0x02) /* The FLAG is in SR register */
- {
- tempreg = DCMI->SR;
- }
- else /* The FLAG is in MISR register */
- {
- tempreg = DCMI->MISR;
- }
-
- if ((tempreg & DCMI_FLAG) != (uint16_t)RESET )
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the DCMI_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DCMI's pending flags.
- * @param DCMI_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
- * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask
- * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
- * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
- * @arg DCMI_FLAG_LINERI: Line Raw flag mask
- * @retval None
- */
-void DCMI_ClearFlag(uint16_t DCMI_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG));
-
- /* Clear the flag by writing in the ICR register 1 in the corresponding
- Flag position*/
-
- DCMI->ICR = DCMI_FLAG;
-}
-
-/**
- * @brief Checks whether the DCMI interrupt has occurred or not.
- * @param DCMI_IT: specifies the DCMI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
- * @arg DCMI_IT_OVF: Overflow interrupt mask
- * @arg DCMI_IT_ERR: Synchronization error interrupt mask
- * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
- * @arg DCMI_IT_LINE: Line interrupt mask
- * @retval The new state of DCMI_IT (SET or RESET).
- */
-ITStatus DCMI_GetITStatus(uint16_t DCMI_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t itstatus = 0;
-
- /* Check the parameters */
- assert_param(IS_DCMI_GET_IT(DCMI_IT));
-
- itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */
-
- if ((itstatus != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the DCMI's interrupt pending bits.
- * @param DCMI_IT: specifies the DCMI interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
- * @arg DCMI_IT_OVF: Overflow interrupt mask
- * @arg DCMI_IT_ERR: Synchronization error interrupt mask
- * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
- * @arg DCMI_IT_LINE: Line interrupt mask
- * @retval None
- */
-void DCMI_ClearITPendingBit(uint16_t DCMI_IT)
-{
- /* Clear the interrupt pending Bit by writing in the ICR register 1 in the
- corresponding pending Bit position*/
-
- DCMI->ICR = DCMI_IT;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_dma.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Direct Memory Access controller (DMA):
- * - Initialization and Configuration
- * - Data Counter
- * - Double Buffer mode configuration and command
- * - Interrupts and flags management
- *
- * @verbatim
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * 1. Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE)
- * function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE)
- * function for DMA2.
- *
- * 2. Enable and configure the peripheral to be connected to the DMA Stream
- * (except for internal SRAM / FLASH memories: no initialization is
- * necessary).
- *
- * 3. For a given Stream, program the required configuration through following parameters:
- * Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination
- * data formats, Circular or Normal mode, Stream Priority level, Source and Destination
- * Incrementation mode, FIFO mode and its Threshold (if needed), Burst mode for Source and/or
- * Destination (if needed) using the DMA_Init() function.
- * To avoid filling un-nesecessary fields, you can call DMA_StructInit() function
- * to initialize a given structure with default values (reset values), the modify
- * only necessary fields (ie. Source and Destination addresses, Transfer size and Data Formats).
- *
- * 4. Enable the NVIC and the corresponding interrupt(s) using the function
- * DMA_ITConfig() if you need to use DMA interrupts.
- *
- * 5. Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring
- * the second Memory address and the first Memory to be used through the function
- * DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function
- * DMA_DoubleBufferModeCmd(). These operations must be done before step 6.
- *
- * 6. Enable the DMA stream using the DMA_Cmd() function.
- *
- * 7. Activate the needed Stream Request using PPP_DMACmd() function for
- * any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
- * The function allowing this operation is provided in each PPP peripheral
- * driver (ie. SPI_DMACmd for SPI peripheral).
- * Once the Stream is enabled, it is not possible to modify its configuration
- * unless the stream is stopped and disabled.
- * After enabling the Stream, it is advised to monitor the EN bit status using
- * the function DMA_GetCmdStatus(). In case of configuration errors or bus errors
- * this bit will remain reset and all transfers on this Stream will remain on hold.
- *
- * 8. Optionally, you can configure the number of data to be transferred
- * when the Stream is disabled (ie. after each Transfer Complete event
- * or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
- * And you can get the number of remaining data to be transferred using
- * the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is
- * enabled and running).
- *
- * 9. To control DMA events you can use one of the following
- * two methods:
- * a- Check on DMA Stream flags using the function DMA_GetFlagStatus().
- * b- Use DMA interrupts through the function DMA_ITConfig() at initialization
- * phase and DMA_GetITStatus() function into interrupt routines in
- * communication phase.
- * After checking on a flag you should clear it using DMA_ClearFlag()
- * function. And after checking on an interrupt event you should
- * clear it using DMA_ClearITPendingBit() function.
- *
- * 10. Optionally, if Circular mode and Double Buffer mode are enabled, you can modify
- * the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that
- * the Memory Address to be modified is not the one currently in use by DMA Stream.
- * This condition can be monitored using the function DMA_GetCurrentMemoryTarget().
- *
- * 11. Optionally, Pause-Resume operations may be performed:
- * The DMA_Cmd() function may be used to perform Pause-Resume operation. When a
- * transfer is ongoing, calling this function to disable the Stream will cause the
- * transfer to be paused. All configuration registers and the number of remaining
- * data will be preserved. When calling again this function to re-enable the Stream,
- * the transfer will be resumed from the point where it was paused.
- *
- * @note Memory-to-Memory transfer is possible by setting the address of the memory into
- * the Peripheral registers. In this mode, Circular mode and Double Buffer mode
- * are not allowed.
- *
- * @note The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
- * possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
- * Half-Word data size for the peripheral to access its data register and set Word data size
- * for the Memory to gain in access time. Each two Half-words will be packed and written in
- * a single access to a Word in the Memory).
- *
- * @note When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
- * and Destination. In this case the Peripheral Data Size will be applied to both Source
- * and Destination.
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_dma.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DMA
- * @brief DMA driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* Masks Definition */
-#define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \
- DMA_SxCR_TEIE | DMA_SxCR_DMEIE)
-
-#define DMA_Stream0_IT_MASK (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \
- DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \
- DMA_LISR_TCIF0)
-
-#define DMA_Stream1_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 6)
-#define DMA_Stream2_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 16)
-#define DMA_Stream3_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 22)
-#define DMA_Stream4_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000)
-#define DMA_Stream5_IT_MASK (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000)
-#define DMA_Stream6_IT_MASK (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000)
-#define DMA_Stream7_IT_MASK (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000)
-#define TRANSFER_IT_MASK (uint32_t)0x0F3C0F3C
-#define HIGH_ISR_MASK (uint32_t)0x20000000
-#define RESERVED_MASK (uint32_t)0x0F7D0F7D
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-
-/** @defgroup DMA_Private_Functions
- * @{
- */
-
-/** @defgroup DMA_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- Initialization and Configuration functions
- ===============================================================================
-
- This subsection provides functions allowing to initialize the DMA Stream source
- and destination addresses, incrementation and data sizes, transfer direction,
- buffer size, circular/normal mode selection, memory-to-memory mode selection
- and Stream priority value.
-
- The DMA_Init() function follows the DMA configuration procedures as described in
- reference manual (RM0090) except the first point: waiting on EN bit to be reset.
- This condition should be checked by user application using the function DMA_GetCmdStatus()
- before calling the DMA_Init() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitialize the DMAy Streamx registers to their default reset values.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @retval None
- */
-void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Disable the selected DMAy Streamx */
- DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN);
-
- /* Reset DMAy Streamx control register */
- DMAy_Streamx->CR = 0;
-
- /* Reset DMAy Streamx Number of Data to Transfer register */
- DMAy_Streamx->NDTR = 0;
-
- /* Reset DMAy Streamx peripheral address register */
- DMAy_Streamx->PAR = 0;
-
- /* Reset DMAy Streamx memory 0 address register */
- DMAy_Streamx->M0AR = 0;
-
- /* Reset DMAy Streamx memory 1 address register */
- DMAy_Streamx->M1AR = 0;
-
- /* Reset DMAy Streamx FIFO control register */
- DMAy_Streamx->FCR = (uint32_t)0x00000021;
-
- /* Reset interrupt pending bits for the selected stream */
- if (DMAy_Streamx == DMA1_Stream0)
- {
- /* Reset interrupt pending bits for DMA1 Stream0 */
- DMA1->LIFCR = DMA_Stream0_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream1)
- {
- /* Reset interrupt pending bits for DMA1 Stream1 */
- DMA1->LIFCR = DMA_Stream1_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream2)
- {
- /* Reset interrupt pending bits for DMA1 Stream2 */
- DMA1->LIFCR = DMA_Stream2_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream3)
- {
- /* Reset interrupt pending bits for DMA1 Stream3 */
- DMA1->LIFCR = DMA_Stream3_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream4)
- {
- /* Reset interrupt pending bits for DMA1 Stream4 */
- DMA1->HIFCR = DMA_Stream4_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream5)
- {
- /* Reset interrupt pending bits for DMA1 Stream5 */
- DMA1->HIFCR = DMA_Stream5_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream6)
- {
- /* Reset interrupt pending bits for DMA1 Stream6 */
- DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream7)
- {
- /* Reset interrupt pending bits for DMA1 Stream7 */
- DMA1->HIFCR = DMA_Stream7_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream0)
- {
- /* Reset interrupt pending bits for DMA2 Stream0 */
- DMA2->LIFCR = DMA_Stream0_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream1)
- {
- /* Reset interrupt pending bits for DMA2 Stream1 */
- DMA2->LIFCR = DMA_Stream1_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream2)
- {
- /* Reset interrupt pending bits for DMA2 Stream2 */
- DMA2->LIFCR = DMA_Stream2_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream3)
- {
- /* Reset interrupt pending bits for DMA2 Stream3 */
- DMA2->LIFCR = DMA_Stream3_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream4)
- {
- /* Reset interrupt pending bits for DMA2 Stream4 */
- DMA2->HIFCR = DMA_Stream4_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream5)
- {
- /* Reset interrupt pending bits for DMA2 Stream5 */
- DMA2->HIFCR = DMA_Stream5_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream6)
- {
- /* Reset interrupt pending bits for DMA2 Stream6 */
- DMA2->HIFCR = DMA_Stream6_IT_MASK;
- }
- else
- {
- if (DMAy_Streamx == DMA2_Stream7)
- {
- /* Reset interrupt pending bits for DMA2 Stream7 */
- DMA2->HIFCR = DMA_Stream7_IT_MASK;
- }
- }
-}
-
-/**
- * @brief Initializes the DMAy Streamx according to the specified parameters in
- * the DMA_InitStruct structure.
- * @note Before calling this function, it is recommended to check that the Stream
- * is actually disabled using the function DMA_GetCmdStatus().
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval None
- */
-void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel));
- assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR));
- assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
- assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
- assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
- assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
- assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
- assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode));
- assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold));
- assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst));
- assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst));
-
- /*------------------------- DMAy Streamx CR Configuration ------------------*/
- /* Get the DMAy_Streamx CR value */
- tmpreg = DMAy_Streamx->CR;
-
- /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
- tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
- DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
- DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
- DMA_SxCR_DIR));
-
- /* Configure DMAy Streamx: */
- /* Set CHSEL bits according to DMA_CHSEL value */
- /* Set DIR bits according to DMA_DIR value */
- /* Set PINC bit according to DMA_PeripheralInc value */
- /* Set MINC bit according to DMA_MemoryInc value */
- /* Set PSIZE bits according to DMA_PeripheralDataSize value */
- /* Set MSIZE bits according to DMA_MemoryDataSize value */
- /* Set CIRC bit according to DMA_Mode value */
- /* Set PL bits according to DMA_Priority value */
- /* Set MBURST bits according to DMA_MemoryBurst value */
- /* Set PBURST bits according to DMA_PeripheralBurst value */
- tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR |
- DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
- DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
- DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority |
- DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst;
-
- /* Write to DMAy Streamx CR register */
- DMAy_Streamx->CR = tmpreg;
-
- /*------------------------- DMAy Streamx FCR Configuration -----------------*/
- /* Get the DMAy_Streamx FCR value */
- tmpreg = DMAy_Streamx->FCR;
-
- /* Clear DMDIS and FTH bits */
- tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
-
- /* Configure DMAy Streamx FIFO:
- Set DMDIS bits according to DMA_FIFOMode value
- Set FTH bits according to DMA_FIFOThreshold value */
- tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold;
-
- /* Write to DMAy Streamx CR */
- DMAy_Streamx->FCR = tmpreg;
-
- /*------------------------- DMAy Streamx NDTR Configuration ----------------*/
- /* Write to DMAy Streamx NDTR register */
- DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize;
-
- /*------------------------- DMAy Streamx PAR Configuration -----------------*/
- /* Write to DMAy Streamx PAR */
- DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
-
- /*------------------------- DMAy Streamx M0AR Configuration ----------------*/
- /* Write to DMAy Streamx M0AR */
- DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr;
-}
-
-/**
- * @brief Fills each DMA_InitStruct member with its default value.
- * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
-{
- /*-------------- Reset DMA init structure parameters values ----------------*/
- /* Initialize the DMA_Channel member */
- DMA_InitStruct->DMA_Channel = 0;
-
- /* Initialize the DMA_PeripheralBaseAddr member */
- DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
-
- /* Initialize the DMA_Memory0BaseAddr member */
- DMA_InitStruct->DMA_Memory0BaseAddr = 0;
-
- /* Initialize the DMA_DIR member */
- DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory;
-
- /* Initialize the DMA_BufferSize member */
- DMA_InitStruct->DMA_BufferSize = 0;
-
- /* Initialize the DMA_PeripheralInc member */
- DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-
- /* Initialize the DMA_MemoryInc member */
- DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
-
- /* Initialize the DMA_PeripheralDataSize member */
- DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-
- /* Initialize the DMA_MemoryDataSize member */
- DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-
- /* Initialize the DMA_Mode member */
- DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
-
- /* Initialize the DMA_Priority member */
- DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
-
- /* Initialize the DMA_FIFOMode member */
- DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable;
-
- /* Initialize the DMA_FIFOThreshold member */
- DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
-
- /* Initialize the DMA_MemoryBurst member */
- DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single;
-
- /* Initialize the DMA_PeripheralBurst member */
- DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
-}
-
-/**
- * @brief Enables or disables the specified DMAy Streamx.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param NewState: new state of the DMAy Streamx.
- * This parameter can be: ENABLE or DISABLE.
- *
- * @note This function may be used to perform Pause-Resume operation. When a
- * transfer is ongoing, calling this function to disable the Stream will
- * cause the transfer to be paused. All configuration registers and the
- * number of remaining data will be preserved. When calling again this
- * function to re-enable the Stream, the transfer will be resumed from
- * the point where it was paused.
- *
- * @note After configuring the DMA Stream (DMA_Init() function) and enabling the
- * stream, it is recommended to check (or wait until) the DMA Stream is
- * effectively enabled. A Stream may remain disabled if a configuration
- * parameter is wrong.
- * After disabling a DMA Stream, it is also recommended to check (or wait
- * until) the DMA Stream is effectively disabled. If a Stream is disabled
- * while a data transfer is ongoing, the current data will be transferred
- * and the Stream will be effectively disabled only after the transfer of
- * this single data is finished.
- *
- * @retval None
- */
-void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DMAy Streamx by setting EN bit */
- DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN;
- }
- else
- {
- /* Disable the selected DMAy Streamx by clearing EN bit */
- DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN;
- }
-}
-
-/**
- * @brief Configures, when the PINC (Peripheral Increment address mode) bit is
- * set, if the peripheral address should be incremented with the data
- * size (configured with PSIZE bits) or by a fixed offset equal to 4
- * (32-bit aligned addresses).
- *
- * @note This function has no effect if the Peripheral Increment mode is disabled.
- *
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_Pincos: specifies the Peripheral increment offset size.
- * This parameter can be one of the following values:
- * @arg DMA_PINCOS_Psize: Peripheral address increment is done
- * accordingly to PSIZE parameter.
- * @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is
- * fixed to 4 (32-bit aligned addresses).
- * @retval None
- */
-void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos));
-
- /* Check the needed Peripheral increment offset */
- if(DMA_Pincos != DMA_PINCOS_Psize)
- {
- /* Configure DMA_SxCR_PINCOS bit with the input parameter */
- DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS;
- }
- else
- {
- /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */
- DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS;
- }
-}
-
-/**
- * @brief Configures, when the DMAy Streamx is disabled, the flow controller for
- * the next transactions (Peripheral or Memory).
- *
- * @note Before enabling this feature, check if the used peripheral supports
- * the Flow Controller mode or not.
- *
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_FlowCtrl: specifies the DMA flow controller.
- * This parameter can be one of the following values:
- * @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is
- * the DMA controller.
- * @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller
- * is the peripheral.
- * @retval None
- */
-void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl));
-
- /* Check the needed flow controller */
- if(DMA_FlowCtrl != DMA_FlowCtrl_Memory)
- {
- /* Configure DMA_SxCR_PFCTRL bit with the input parameter */
- DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL;
- }
- else
- {
- /* Clear the PFCTRL bit: Memory is the flow controller */
- DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup DMA_Group2 Data Counter functions
- * @brief Data Counter functions
- *
-@verbatim
- ===============================================================================
- Data Counter functions
- ===============================================================================
-
- This subsection provides function allowing to configure and read the buffer size
- (number of data to be transferred).
-
- The DMA data counter can be written only when the DMA Stream is disabled
- (ie. after transfer complete event).
-
- The following function can be used to write the Stream data counter value:
- - void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
-
-@note It is advised to use this function rather than DMA_Init() in situations where
- only the Data buffer needs to be reloaded.
-
-@note If the Source and Destination Data Sizes are different, then the value written in
- data counter, expressing the number of transfers, is relative to the number of
- transfers from the Peripheral point of view.
- ie. If Memory data size is Word, Peripheral data size is Half-Words, then the value
- to be configured in the data counter is the number of Half-Words to be transferred
- from/to the peripheral.
-
- The DMA data counter can be read to indicate the number of remaining transfers for
- the relative DMA Stream. This counter is decremented at the end of each data
- transfer and when the transfer is complete:
- - If Normal mode is selected: the counter is set to 0.
- - If Circular mode is selected: the counter is reloaded with the initial value
- (configured before enabling the DMA Stream)
-
- The following function can be used to read the Stream data counter value:
- - uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes the number of data units to be transferred on the DMAy Streamx.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param Counter: Number of data units to be transferred (from 0 to 65535)
- * Number of data items depends only on the Peripheral data format.
- *
- * @note If Peripheral data format is Bytes: number of data units is equal
- * to total number of bytes to be transferred.
- *
- * @note If Peripheral data format is Half-Word: number of data units is
- * equal to total number of bytes to be transferred / 2.
- *
- * @note If Peripheral data format is Word: number of data units is equal
- * to total number of bytes to be transferred / 4.
- *
- * @note In Memory-to-Memory transfer mode, the memory buffer pointed by
- * DMAy_SxPAR register is considered as Peripheral.
- *
- * @retval The number of remaining data units in the current DMAy Streamx transfer.
- */
-void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Write the number of data units to be transferred */
- DMAy_Streamx->NDTR = (uint16_t)Counter;
-}
-
-/**
- * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @retval The number of remaining data units in the current DMAy Streamx transfer.
- */
-uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Return the number of remaining data units for DMAy Streamx */
- return ((uint16_t)(DMAy_Streamx->NDTR));
-}
-/**
- * @}
- */
-
-/** @defgroup DMA_Group3 Double Buffer mode functions
- * @brief Double Buffer mode functions
- *
-@verbatim
- ===============================================================================
- Double Buffer mode functions
- ===============================================================================
-
- This subsection provides function allowing to configure and control the double
- buffer mode parameters.
-
- The Double Buffer mode can be used only when Circular mode is enabled.
- The Double Buffer mode cannot be used when transferring data from Memory to Memory.
-
- The Double Buffer mode allows to set two different Memory addresses from/to which
- the DMA controller will access alternatively (after completing transfer to/from target
- memory 0, it will start transfer to/from target memory 1).
- This allows to reduce software overhead for double buffering and reduce the CPU
- access time.
-
- Two functions must be called before calling the DMA_Init() function:
- - void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
- uint32_t DMA_CurrentMemory);
- - void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
-
- DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address and the first
- Memory target from/to which the transfer will start after enabling the DMA Stream.
- Then DMA_DoubleBufferModeCmd() must be called to enable the Double Buffer mode (or disable
- it when it should not be used).
-
-
- Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is
- stopped) to modify on of the target Memories addresses or to check wich Memory target is currently
- used:
- - void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
- uint32_t DMA_MemoryTarget);
- - uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
-
- DMA_MemoryTargetConfig() can be called to modify the base address of one of the two target Memories.
- The Memory of which the base address will be modified must not be currently be used by the DMA Stream
- (ie. if the DMA Stream is currently transferring from Memory 1 then you can only modify base address
- of target Memory 0 and vice versa).
- To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which
- returns the index of the Memory target currently in use by the DMA Stream.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures, when the DMAy Streamx is disabled, the double buffer mode
- * and the current memory target.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param Memory1BaseAddr: the base address of the second buffer (Memory 1)
- * @param DMA_CurrentMemory: specifies which memory will be first buffer for
- * the transactions when the Stream will be enabled.
- * This parameter can be one of the following values:
- * @arg DMA_Memory_0: Memory 0 is the current buffer.
- * @arg DMA_Memory_1: Memory 1 is the current buffer.
- *
- * @note Memory0BaseAddr is set by the DMA structure configuration in DMA_Init().
- *
- * @retval None
- */
-void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
- uint32_t DMA_CurrentMemory)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory));
-
- if (DMA_CurrentMemory != DMA_Memory_0)
- {
- /* Set Memory 1 as current memory address */
- DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT);
- }
- else
- {
- /* Set Memory 0 as current memory address */
- DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT);
- }
-
- /* Write to DMAy Streamx M1AR */
- DMAy_Streamx->M1AR = Memory1BaseAddr;
-}
-
-/**
- * @brief Enables or disables the double buffer mode for the selected DMA stream.
- * @note This function can be called only when the DMA Stream is disabled.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param NewState: new state of the DMAy Streamx double buffer mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Configure the Double Buffer mode */
- if (NewState != DISABLE)
- {
- /* Enable the Double buffer mode */
- DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM;
- }
- else
- {
- /* Disable the Double buffer mode */
- DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM;
- }
-}
-
-/**
- * @brief Configures the Memory address for the next buffer transfer in double
- * buffer mode (for dynamic use). This function can be called when the
- * DMA Stream is enabled and when the transfer is ongoing.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param MemoryBaseAddr: The base address of the target memory buffer
- * @param DMA_MemoryTarget: Next memory target to be used.
- * This parameter can be one of the following values:
- * @arg DMA_Memory_0: To use the memory address 0
- * @arg DMA_Memory_1: To use the memory address 1
- *
- * @note It is not allowed to modify the Base Address of a target Memory when
- * this target is involved in the current transfer. ie. If the DMA Stream
- * is currently transferring to/from Memory 1, then it not possible to
- * modify Base address of Memory 1, but it is possible to modify Base
- * address of Memory 0.
- * To know which Memory is currently used, you can use the function
- * DMA_GetCurrentMemoryTarget().
- *
- * @retval None
- */
-void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
- uint32_t DMA_MemoryTarget)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget));
-
- /* Check the Memory target to be configured */
- if (DMA_MemoryTarget != DMA_Memory_0)
- {
- /* Write to DMAy Streamx M1AR */
- DMAy_Streamx->M1AR = MemoryBaseAddr;
- }
- else
- {
- /* Write to DMAy Streamx M0AR */
- DMAy_Streamx->M0AR = MemoryBaseAddr;
- }
-}
-
-/**
- * @brief Returns the current memory target used by double buffer transfer.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @retval The memory target number: 0 for Memory0 or 1 for Memory1.
- */
-uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Get the current memory target */
- if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0)
- {
- /* Current memory buffer used is Memory 1 */
- tmp = 1;
- }
- else
- {
- /* Current memory buffer used is Memory 0 */
- tmp = 0;
- }
- return tmp;
-}
-/**
- * @}
- */
-
-/** @defgroup DMA_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
-
- This subsection provides functions allowing to
- - Check the DMA enable status
- - Check the FIFO status
- - Configure the DMA Interrupts sources and check or clear the flags or pending bits status.
-
- 1. DMA Enable status:
- After configuring the DMA Stream (DMA_Init() function) and enabling the stream,
- it is recommended to check (or wait until) the DMA Stream is effectively enabled.
- A Stream may remain disabled if a configuration parameter is wrong.
- After disabling a DMA Stream, it is also recommended to check (or wait until) the DMA
- Stream is effectively disabled. If a Stream is disabled while a data transfer is ongoing,
- the current data will be transferred and the Stream will be effectively disabled only after
- this data transfer completion.
- To monitor this state it is possible to use the following function:
- - FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
-
- 2. FIFO Status:
- It is possible to monitor the FIFO status when a transfer is ongoing using the following
- function:
- - uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
-
- 3. DMA Interrupts and Flags:
- The user should identify which mode will be used in his application to manage the
- DMA controller events: Polling mode or Interrupt mode.
-
- Polling Mode
- =============
- Each DMA stream can be managed through 4 event Flags:
- (x : DMA Stream number )
- 1. DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred.
- 2. DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred.
- 3. DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred.
- 4. DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred.
- 5. DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred .
-
- In this Mode it is advised to use the following functions:
- - FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
- - void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
-
- Interrupt Mode
- ===============
- Each DMA Stream can be managed through 4 Interrupts:
-
- Interrupt Source
- ----------------
- 1. DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event.
- 2. DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event.
- 3. DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event.
- 4. DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event.
- 5. DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event.
-
- In this Mode it is advised to use the following functions:
- - void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
- - ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
- - void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the status of EN bit for the specified DMAy Streamx.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- *
- * @note After configuring the DMA Stream (DMA_Init() function) and enabling
- * the stream, it is recommended to check (or wait until) the DMA Stream
- * is effectively enabled. A Stream may remain disabled if a configuration
- * parameter is wrong.
- * After disabling a DMA Stream, it is also recommended to check (or wait
- * until) the DMA Stream is effectively disabled. If a Stream is disabled
- * while a data transfer is ongoing, the current data will be transferred
- * and the Stream will be effectively disabled only after the transfer
- * of this single data is finished.
- *
- * @retval Current state of the DMAy Streamx (ENABLE or DISABLE).
- */
-FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- FunctionalState state = DISABLE;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0)
- {
- /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */
- state = ENABLE;
- }
- else
- {
- /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and
- all transfers are complete) */
- state = DISABLE;
- }
- return state;
-}
-
-/**
- * @brief Returns the current DMAy Streamx FIFO filled level.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @retval The FIFO filling state.
- * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
- * and not empty.
- * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
- * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
- * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
- * - DMA_FIFOStatus_Empty: when FIFO is empty
- * - DMA_FIFOStatus_Full: when FIFO is full
- */
-uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Get the FIFO level bits */
- tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS));
-
- return tmpreg;
-}
-
-/**
- * @brief Checks whether the specified DMAy Streamx flag is set or not.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag
- * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag
- * @arg DMA_FLAG_TEIFx: Streamx transfer error flag
- * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
- * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag
- * Where x can be 0 to 7 to select the DMA Stream.
- * @retval The new state of DMA_FLAG (SET or RESET).
- */
-FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
-{
- FlagStatus bitstatus = RESET;
- DMA_TypeDef* DMAy;
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
-
- /* Determine the DMA to which belongs the stream */
- if (DMAy_Streamx < DMA2_Stream0)
- {
- /* DMAy_Streamx belongs to DMA1 */
- DMAy = DMA1;
- }
- else
- {
- /* DMAy_Streamx belongs to DMA2 */
- DMAy = DMA2;
- }
-
- /* Check if the flag is in HISR or LISR */
- if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
- {
- /* Get DMAy HISR register value */
- tmpreg = DMAy->HISR;
- }
- else
- {
- /* Get DMAy LISR register value */
- tmpreg = DMAy->LISR;
- }
-
- /* Mask the reserved bits */
- tmpreg &= (uint32_t)RESERVED_MASK;
-
- /* Check the status of the specified DMA flag */
- if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
- {
- /* DMA_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* DMA_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the DMA_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DMAy Streamx's pending flags.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag
- * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag
- * @arg DMA_FLAG_TEIFx: Streamx transfer error flag
- * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
- * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag
- * Where x can be 0 to 7 to select the DMA Stream.
- * @retval None
- */
-void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
-{
- DMA_TypeDef* DMAy;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
-
- /* Determine the DMA to which belongs the stream */
- if (DMAy_Streamx < DMA2_Stream0)
- {
- /* DMAy_Streamx belongs to DMA1 */
- DMAy = DMA1;
- }
- else
- {
- /* DMAy_Streamx belongs to DMA2 */
- DMAy = DMA2;
- }
-
- /* Check if LIFCR or HIFCR register is targeted */
- if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
- {
- /* Set DMAy HIFCR register clear flag bits */
- DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
- }
- else
- {
- /* Set DMAy LIFCR register clear flag bits */
- DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
- }
-}
-
-/**
- * @brief Enables or disables the specified DMAy Streamx interrupts.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer complete interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @arg DMA_IT_FE: FIFO error interrupt mask
- * @param NewState: new state of the specified DMA interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CONFIG_IT(DMA_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Check if the DMA_IT parameter contains a FIFO interrupt */
- if ((DMA_IT & DMA_IT_FE) != 0)
- {
- if (NewState != DISABLE)
- {
- /* Enable the selected DMA FIFO interrupts */
- DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE;
- }
- else
- {
- /* Disable the selected DMA FIFO interrupts */
- DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE;
- }
- }
-
- /* Check if the DMA_IT parameter contains a Transfer interrupt */
- if (DMA_IT != DMA_IT_FE)
- {
- if (NewState != DISABLE)
- {
- /* Enable the selected DMA transfer interrupts */
- DMAy_Streamx->CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);
- }
- else
- {
- /* Disable the selected DMA transfer interrupts */
- DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);
- }
- }
-}
-
-/**
- * @brief Checks whether the specified DMAy Streamx interrupt has occurred or not.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_IT: specifies the DMA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt
- * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt
- * @arg DMA_IT_TEIFx: Streamx transfer error interrupt
- * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt
- * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt
- * Where x can be 0 to 7 to select the DMA Stream.
- * @retval The new state of DMA_IT (SET or RESET).
- */
-ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
-{
- ITStatus bitstatus = RESET;
- DMA_TypeDef* DMAy;
- uint32_t tmpreg = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_GET_IT(DMA_IT));
-
- /* Determine the DMA to which belongs the stream */
- if (DMAy_Streamx < DMA2_Stream0)
- {
- /* DMAy_Streamx belongs to DMA1 */
- DMAy = DMA1;
- }
- else
- {
- /* DMAy_Streamx belongs to DMA2 */
- DMAy = DMA2;
- }
-
- /* Check if the interrupt enable bit is in the CR or FCR register */
- if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET)
- {
- /* Get the interrupt enable position mask in CR register */
- tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK);
-
- /* Check the enable bit in CR register */
- enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg);
- }
- else
- {
- /* Check the enable bit in FCR register */
- enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE);
- }
-
- /* Check if the interrupt pending flag is in LISR or HISR */
- if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
- {
- /* Get DMAy HISR register value */
- tmpreg = DMAy->HISR ;
- }
- else
- {
- /* Get DMAy LISR register value */
- tmpreg = DMAy->LISR ;
- }
-
- /* mask all reserved bits */
- tmpreg &= (uint32_t)RESERVED_MASK;
-
- /* Check the status of the specified DMA interrupt */
- if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
- {
- /* DMA_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* DMA_IT is reset */
- bitstatus = RESET;
- }
-
- /* Return the DMA_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DMAy Streamx's interrupt pending bits.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt
- * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt
- * @arg DMA_IT_TEIFx: Streamx transfer error interrupt
- * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt
- * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt
- * Where x can be 0 to 7 to select the DMA Stream.
- * @retval None
- */
-void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
-{
- DMA_TypeDef* DMAy;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CLEAR_IT(DMA_IT));
-
- /* Determine the DMA to which belongs the stream */
- if (DMAy_Streamx < DMA2_Stream0)
- {
- /* DMAy_Streamx belongs to DMA1 */
- DMAy = DMA1;
- }
- else
- {
- /* DMAy_Streamx belongs to DMA2 */
- DMAy = DMA2;
- }
-
- /* Check if LIFCR or HIFCR register is targeted */
- if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
- {
- /* Set DMAy HIFCR register clear interrupt bits */
- DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
- }
- else
- {
- /* Set DMAy LIFCR register clear interrupt bits */
- DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_exti.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the EXTI peripheral:
- * - Initialization and Configuration
- * - Interrupts and flags management
- *
- * @verbatim
- *
- * ===================================================================
- * EXTI features
- * ===================================================================
- *
- * External interrupt/event lines are mapped as following:
- * 1- All available GPIO pins are connected to the 16 external
- * interrupt/event lines from EXTI0 to EXTI15.
- * 2- EXTI line 16 is connected to the PVD Output
- * 3- EXTI line 17 is connected to the RTC Alarm event
- * 4- EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event
- * 5- EXTI line 19 is connected to the Ethernet Wakeup event
- * 6- EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event
- * 7- EXTI line 21 is connected to the RTC Tamper and Time Stamp events
- * 8- EXTI line 22 is connected to the RTC Wakeup event
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- *
- * In order to use an I/O pin as an external interrupt source, follow
- * steps below:
- * 1- Configure the I/O in input mode using GPIO_Init()
- * 2- Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig()
- * 3- Select the mode(interrupt, event) and configure the trigger
- * selection (Rising, falling or both) using EXTI_Init()
- * 4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
- *
- * @note SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
- * registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_exti.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup EXTI
- * @brief EXTI driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup EXTI_Private_Functions
- * @{
- */
-
-/** @defgroup EXTI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- Initialization and Configuration functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the EXTI peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void EXTI_DeInit(void)
-{
- EXTI->IMR = 0x00000000;
- EXTI->EMR = 0x00000000;
- EXTI->RTSR = 0x00000000;
- EXTI->FTSR = 0x00000000;
- EXTI->PR = 0x007FFFFF;
-}
-
-/**
- * @brief Initializes the EXTI peripheral according to the specified
- * parameters in the EXTI_InitStruct.
- * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
- * that contains the configuration information for the EXTI peripheral.
- * @retval None
- */
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
- assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
- assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
- assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
-
- tmp = (uint32_t)EXTI_BASE;
-
- if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
- {
- /* Clear EXTI line configuration */
- EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
- EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
-
- tmp += EXTI_InitStruct->EXTI_Mode;
-
- *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
-
- /* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
- EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
-
- /* Select the trigger for the selected external interrupts */
- if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
- {
- /* Rising Falling edge */
- EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
- EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
- }
- else
- {
- tmp = (uint32_t)EXTI_BASE;
- tmp += EXTI_InitStruct->EXTI_Trigger;
-
- *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
- }
- }
- else
- {
- tmp += EXTI_InitStruct->EXTI_Mode;
-
- /* Disable the selected external lines */
- *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
- }
-}
-
-/**
- * @brief Fills each EXTI_InitStruct member with its reset value.
- * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
-{
- EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
- EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
- EXTI_InitStruct->EXTI_LineCmd = DISABLE;
-}
-
-/**
- * @brief Generates a Software interrupt on selected EXTI line.
- * @param EXTI_Line: specifies the EXTI line on which the software interrupt
- * will be generated.
- * This parameter can be any combination of EXTI_Linex where x can be (0..22)
- * @retval None
- */
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(EXTI_Line));
-
- EXTI->SWIER |= EXTI_Line;
-}
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Group2 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified EXTI line flag is set or not.
- * @param EXTI_Line: specifies the EXTI line flag to check.
- * This parameter can be EXTI_Linex where x can be(0..22)
- * @retval The new state of EXTI_Line (SET or RESET).
- */
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-
- if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the EXTI's line pending flags.
- * @param EXTI_Line: specifies the EXTI lines flags to clear.
- * This parameter can be any combination of EXTI_Linex where x can be (0..22)
- * @retval None
- */
-void EXTI_ClearFlag(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(EXTI_Line));
-
- EXTI->PR = EXTI_Line;
-}
-
-/**
- * @brief Checks whether the specified EXTI line is asserted or not.
- * @param EXTI_Line: specifies the EXTI line to check.
- * This parameter can be EXTI_Linex where x can be(0..22)
- * @retval The new state of EXTI_Line (SET or RESET).
- */
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
- /* Check the parameters */
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-
- enablestatus = EXTI->IMR & EXTI_Line;
- if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the EXTI's line pending bits.
- * @param EXTI_Line: specifies the EXTI lines to clear.
- * This parameter can be any combination of EXTI_Linex where x can be (0..22)
- * @retval None
- */
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(EXTI_Line));
-
- EXTI->PR = EXTI_Line;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_flash.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the FLASH peripheral:
- * - FLASH Interface configuration
- * - FLASH Memory Programming
- * - Option Bytes Programming
- * - Interrupts and flags management
- *
- * @verbatim
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- *
- * This driver provides functions to configure and program the FLASH
- * memory of all STM32F4xx devices.
- * These functions are split in 4 groups:
- *
- * 1. FLASH Interface configuration functions: this group includes the
- * management of the following features:
- * - Set the latency
- * - Enable/Disable the prefetch buffer
- * - Enable/Disable the Instruction cache and the Data cache
- * - Reset the Instruction cache and the Data cache
- *
- * 2. FLASH Memory Programming functions: this group includes all needed
- * functions to erase and program the main memory:
- * - Lock and Unlock the FLASH interface
- * - Erase function: Erase sector, erase all sectors
- * - Program functions: byte, half word, word and double word
- *
- * 3. Option Bytes Programming functions: this group includes all needed
- * functions to manage the Option Bytes:
- * - Set/Reset the write protection
- * - Set the Read protection Level
- * - Set the BOR level
- * - Program the user Option Bytes
- * - Launch the Option Bytes loader
- *
- * 4. Interrupts and flags management functions: this group
- * includes all needed functions to:
- * - Enable/Disable the FLASH interrupt sources
- * - Get flags status
- * - Clear flags
- * - Get FLASH operation status
- * - Wait for last FLASH operation
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_flash.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup FLASH
- * @brief FLASH driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FLASH_Private_Functions
- * @{
- */
-
-/** @defgroup FLASH_Group1 FLASH Interface configuration functions
- * @brief FLASH Interface configuration functions
- *
-
-@verbatim
- ===============================================================================
- FLASH Interface configuration functions
- ===============================================================================
-
- This group includes the following functions:
- - void FLASH_SetLatency(uint32_t FLASH_Latency)
- To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
- (HCLK) and the supply voltage of the device.
- +-------------------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
- | | voltage range | voltage range | voltage range | voltage range |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
- |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120|
- |***************|****************|****************|*****************|*****************|*****************************+
- | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V |
- |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
- |Max Parallelism| x32 | x16 | x8 | x64 |
- |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
- |PSIZE[1:0] | 10 | 01 | 00 | 11 |
- +-------------------------------------------------------------------------------------------------------------------+
-
- - void FLASH_PrefetchBufferCmd(FunctionalState NewState)
- - void FLASH_InstructionCacheCmd(FunctionalState NewState)
- - void FLASH_DataCacheCmd(FunctionalState NewState)
- - void FLASH_InstructionCacheReset(void)
- - void FLASH_DataCacheReset(void)
-
- The unlock sequence is not needed for these functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the code latency value.
- * @param FLASH_Latency: specifies the FLASH Latency value.
- * This parameter can be one of the following values:
- * @arg FLASH_Latency_0: FLASH Zero Latency cycle
- * @arg FLASH_Latency_1: FLASH One Latency cycle
- * @arg FLASH_Latency_2: FLASH Two Latency cycles
- * @arg FLASH_Latency_3: FLASH Three Latency cycles
- * @arg FLASH_Latency_4: FLASH Four Latency cycles
- * @arg FLASH_Latency_5: FLASH Five Latency cycles
- * @arg FLASH_Latency_6: FLASH Six Latency cycles
- * @arg FLASH_Latency_7: FLASH Seven Latency cycles
- * @retval None
- */
-void FLASH_SetLatency(uint32_t FLASH_Latency)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_LATENCY(FLASH_Latency));
-
- /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */
- *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency;
-}
-
-/**
- * @brief Enables or disables the Prefetch Buffer.
- * @param NewState: new state of the Prefetch Buffer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_PrefetchBufferCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Enable or disable the Prefetch Buffer */
- if(NewState != DISABLE)
- {
- FLASH->ACR |= FLASH_ACR_PRFTEN;
- }
- else
- {
- FLASH->ACR &= (~FLASH_ACR_PRFTEN);
- }
-}
-
-/**
- * @brief Enables or disables the Instruction Cache feature.
- * @param NewState: new state of the Instruction Cache.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_InstructionCacheCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- FLASH->ACR |= FLASH_ACR_ICEN;
- }
- else
- {
- FLASH->ACR &= (~FLASH_ACR_ICEN);
- }
-}
-
-/**
- * @brief Enables or disables the Data Cache feature.
- * @param NewState: new state of the Data Cache.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_DataCacheCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- FLASH->ACR |= FLASH_ACR_DCEN;
- }
- else
- {
- FLASH->ACR &= (~FLASH_ACR_DCEN);
- }
-}
-
-/**
- * @brief Resets the Instruction Cache.
- * @note This function must be used only when the Instruction Cache is disabled.
- * @param None
- * @retval None
- */
-void FLASH_InstructionCacheReset(void)
-{
- FLASH->ACR |= FLASH_ACR_ICRST;
-}
-
-/**
- * @brief Resets the Data Cache.
- * @note This function must be used only when the Data Cache is disabled.
- * @param None
- * @retval None
- */
-void FLASH_DataCacheReset(void)
-{
- FLASH->ACR |= FLASH_ACR_DCRST;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group2 FLASH Memory Programming functions
- * @brief FLASH Memory Programming functions
- *
-@verbatim
- ===============================================================================
- FLASH Memory Programming functions
- ===============================================================================
-
- This group includes the following functions:
- - void FLASH_Unlock(void)
- - void FLASH_Lock(void)
- - FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
- - FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
- - FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
- - FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
- - FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
- - FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
-
- Any operation of erase or program should follow these steps:
- 1. Call the FLASH_Unlock() function to enable the FLASH control register access
-
- 2. Call the desired function to erase sector(s) or program data
-
- 3. Call the FLASH_Lock() function to disable the FLASH control register access
- (recommended to protect the FLASH memory against possible unwanted operation)
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlocks the FLASH control register access
- * @param None
- * @retval None
- */
-void FLASH_Unlock(void)
-{
- if((FLASH->CR & FLASH_CR_LOCK) != RESET)
- {
- /* Authorize the FLASH Registers access */
- FLASH->KEYR = FLASH_KEY1;
- FLASH->KEYR = FLASH_KEY2;
- }
-}
-
-/**
- * @brief Locks the FLASH control register access
- * @param None
- * @retval None
- */
-void FLASH_Lock(void)
-{
- /* Set the LOCK Bit to lock the FLASH Registers access */
- FLASH->CR |= FLASH_CR_LOCK;
-}
-
-/**
- * @brief Erases a specified FLASH Sector.
- *
- * @param FLASH_Sector: The Sector number to be erased.
- * This parameter can be a value between FLASH_Sector_0 and FLASH_Sector_11
- *
- * @param VoltageRange: The device voltage range which defines the erase parallelism.
- * This parameter can be one of the following values:
- * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
- * the operation will be done by byte (8-bit)
- * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
- * the operation will be done by half word (16-bit)
- * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
- * the operation will be done by word (32-bit)
- * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
- * the operation will be done by double word (64-bit)
- *
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
-{
- uint32_t tmp_psize = 0x0;
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_SECTOR(FLASH_Sector));
- assert_param(IS_VOLTAGERANGE(VoltageRange));
-
- if(VoltageRange == VoltageRange_1)
- {
- tmp_psize = FLASH_PSIZE_BYTE;
- }
- else if(VoltageRange == VoltageRange_2)
- {
- tmp_psize = FLASH_PSIZE_HALF_WORD;
- }
- else if(VoltageRange == VoltageRange_3)
- {
- tmp_psize = FLASH_PSIZE_WORD;
- }
- else
- {
- tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
- }
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase the sector */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= tmp_psize;
- FLASH->CR &= SECTOR_MASK;
- FLASH->CR |= FLASH_CR_SER | FLASH_Sector;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the erase operation is completed, disable the SER Bit */
- FLASH->CR &= (~FLASH_CR_SER);
- FLASH->CR &= SECTOR_MASK;
- }
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Erases all FLASH Sectors.
- *
- * @param VoltageRange: The device voltage range which defines the erase parallelism.
- * This parameter can be one of the following values:
- * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
- * the operation will be done by byte (8-bit)
- * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
- * the operation will be done by half word (16-bit)
- * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
- * the operation will be done by word (32-bit)
- * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
- * the operation will be done by double word (64-bit)
- *
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
-{
- uint32_t tmp_psize = 0x0;
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
- assert_param(IS_VOLTAGERANGE(VoltageRange));
-
- if(VoltageRange == VoltageRange_1)
- {
- tmp_psize = FLASH_PSIZE_BYTE;
- }
- else if(VoltageRange == VoltageRange_2)
- {
- tmp_psize = FLASH_PSIZE_HALF_WORD;
- }
- else if(VoltageRange == VoltageRange_3)
- {
- tmp_psize = FLASH_PSIZE_WORD;
- }
- else
- {
- tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
- }
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all sectors */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= tmp_psize;
- FLASH->CR |= FLASH_CR_MER;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the erase operation is completed, disable the MER Bit */
- FLASH->CR &= (~FLASH_CR_MER);
-
- }
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Programs a double word (64-bit) at a specified address.
- * @note This function must be used when the device voltage range is from
- * 2.7V to 3.6V and an External Vpp is present.
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint64_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
- }
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a word (32-bit) at a specified address.
- * @param Address: specifies the address to be programmed.
- * This parameter can be any address in Program memory zone or in OTP zone.
- * @note This function must be used when the device voltage range is from 2.7V to 3.6V.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= FLASH_PSIZE_WORD;
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint32_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
- }
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a half word (16-bit) at a specified address.
- * @note This function must be used when the device voltage range is from 2.1V to 3.6V.
- * @param Address: specifies the address to be programmed.
- * This parameter can be any address in Program memory zone or in OTP zone.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= FLASH_PSIZE_HALF_WORD;
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint16_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
- }
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a byte (8-bit) at a specified address.
- * @note This function can be used within all the device supply voltage ranges.
- * @param Address: specifies the address to be programmed.
- * This parameter can be any address in Program memory zone or in OTP zone.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= FLASH_PSIZE_BYTE;
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint8_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
- }
-
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group3 Option Bytes Programming functions
- * @brief Option Bytes Programming functions
- *
-@verbatim
- ===============================================================================
- Option Bytes Programming functions
- ===============================================================================
-
- This group includes the following functions:
- - void FLASH_OB_Unlock(void)
- - void FLASH_OB_Lock(void)
- - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
- - void FLASH_OB_RDPConfig(uint8_t OB_RDP)
- - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
- - void FLASH_OB_BORConfig(uint8_t OB_BOR)
- - FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data)
- - FLASH_Status FLASH_OB_Launch(void)
- - uint32_t FLASH_OB_GetUser(void)
- - uint8_t FLASH_OB_GetWRP(void)
- - uint8_t FLASH_OB_GetRDP(void)
- - uint8_t FLASH_OB_GetBOR(void)
-
- Any operation of erase or program should follow these steps:
- 1. Call the FLASH_OB_Unlock() function to enable the FLASH option control register access
-
- 2. Call one or several functions to program the desired Option Bytes:
- - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable
- the desired sector write protection
- - void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level
- - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure
- the user Option Bytes.
- - void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level
-
- 3. Once all needed Option Bytes to be programmed are correctly written, call the
- FLASH_OB_Launch() function to launch the Option Bytes programming process.
-
- @note When changing the IWDG mode from HW to SW or from SW to HW, a system
- reset is needed to make the change effective.
-
- 4. Call the FLASH_OB_Lock() function to disable the FLASH option control register
- access (recommended to protect the Option Bytes against possible unwanted operations)
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlocks the FLASH Option Control Registers access.
- * @param None
- * @retval None
- */
-void FLASH_OB_Unlock(void)
-{
- if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
- {
- /* Authorizes the Option Byte register programming */
- FLASH->OPTKEYR = FLASH_OPT_KEY1;
- FLASH->OPTKEYR = FLASH_OPT_KEY2;
- }
-}
-
-/**
- * @brief Locks the FLASH Option Control Registers access.
- * @param None
- * @retval None
- */
-void FLASH_OB_Lock(void)
-{
- /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
- FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
-}
-
-/**
- * @brief Enables or disables the write protection of the desired sectors
- * @param OB_WRP: specifies the sector(s) to be write protected or unprotected.
- * This parameter can be one of the following values:
- * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11
- * @arg OB_WRP_Sector_All
- * @param Newstate: new state of the Write Protection.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_WRP(OB_WRP));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- if(NewState != DISABLE)
- {
- *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP);
- }
- else
- {
- *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
- }
- }
-}
-
-/**
- * @brief Sets the read protection level.
- * @param OB_RDP: specifies the read protection level.
- * This parameter can be one of the following values:
- * @arg OB_RDP_Level_0: No protection
- * @arg OB_RDP_Level_1: Read protection of the memory
- * @arg OB_RDP_Level_2: Full chip protection
- *
- * !!!Warning!!! When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
- *
- * @retval None
- */
-void FLASH_OB_RDPConfig(uint8_t OB_RDP)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_RDP(OB_RDP));
-
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP;
-
- }
-}
-
-/**
- * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
- * @param OB_IWDG: Selects the IWDG mode
- * This parameter can be one of the following values:
- * @arg OB_IWDG_SW: Software IWDG selected
- * @arg OB_IWDG_HW: Hardware IWDG selected
- * @param OB_STOP: Reset event when entering STOP mode.
- * This parameter can be one of the following values:
- * @arg OB_STOP_NoRST: No reset generated when entering in STOP
- * @arg OB_STOP_RST: Reset generated when entering in STOP
- * @param OB_STDBY: Reset event when entering Standby mode.
- * This parameter can be one of the following values:
- * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
- * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
- * @retval None
- */
-void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
-{
- uint8_t optiontmp = 0xFF;
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
- assert_param(IS_OB_STOP_SOURCE(OB_STOP));
- assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */
- optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F);
-
- /* Update User Option Byte */
- *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp)));
- }
-}
-
-/**
- * @brief Sets the BOR Level.
- * @param OB_BOR: specifies the Option Bytes BOR Reset Level.
- * This parameter can be one of the following values:
- * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
- * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
- * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
- * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
- * @retval None
- */
-void FLASH_OB_BORConfig(uint8_t OB_BOR)
-{
- /* Check the parameters */
- assert_param(IS_OB_BOR(OB_BOR));
-
- /* Set the BOR Level */
- *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
- *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR;
-
-}
-
-/**
- * @brief Launch the option byte loading.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_OB_Launch(void)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Set the OPTSTRT bit in OPTCR register */
- *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- return status;
-}
-
-/**
- * @brief Returns the FLASH User Option Bytes values.
- * @param None
- * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
- * and RST_STDBY(Bit2).
- */
-uint8_t FLASH_OB_GetUser(void)
-{
- /* Return the User Option Byte */
- return (uint8_t)(FLASH->OPTCR >> 5);
-}
-
-/**
- * @brief Returns the FLASH Write Protection Option Bytes value.
- * @param None
- * @retval The FLASH Write Protection Option Bytes value
- */
-uint16_t FLASH_OB_GetWRP(void)
-{
- /* Return the FLASH write protection Register value */
- return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
-}
-
-/**
- * @brief Returns the FLASH Read Protection level.
- * @param None
- * @retval FLASH ReadOut Protection Status:
- * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
- * - RESET, when OB_RDP_Level_0 is set
- */
-FlagStatus FLASH_OB_GetRDP(void)
-{
- FlagStatus readstatus = RESET;
-
- if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0))
- {
- readstatus = SET;
- }
- else
- {
- readstatus = RESET;
- }
- return readstatus;
-}
-
-/**
- * @brief Returns the FLASH BOR level.
- * @param None
- * @retval The FLASH BOR level:
- * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
- * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
- * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
- * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
- */
-uint8_t FLASH_OB_GetBOR(void)
-{
- /* Return the FLASH BOR level */
- return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified FLASH interrupts.
- * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg FLASH_IT_ERR: FLASH Error Interrupt
- * @arg FLASH_IT_EOP: FLASH end of operation Interrupt
- * @retval None
- */
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_IT(FLASH_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- /* Enable the interrupt sources */
- FLASH->CR |= FLASH_IT;
- }
- else
- {
- /* Disable the interrupt sources */
- FLASH->CR &= ~(uint32_t)FLASH_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified FLASH flag is set or not.
- * @param FLASH_FLAG: specifies the FLASH flag to check.
- * This parameter can be one of the following values:
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
- * @arg FLASH_FLAG_OPERR: FLASH operation Error flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
- * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
- * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
- * @arg FLASH_FLAG_BSY: FLASH Busy flag
- * @retval The new state of FLASH_FLAG (SET or RESET).
- */
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
-
- if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the new state of FLASH_FLAG (SET or RESET) */
- return bitstatus;
-}
-
-/**
- * @brief Clears the FLASH's pending flags.
- * @param FLASH_FLAG: specifies the FLASH flags to clear.
- * This parameter can be any combination of the following values:
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
- * @arg FLASH_FLAG_OPERR: FLASH operation Error flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
- * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
- * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
- * @retval None
- */
-void FLASH_ClearFlag(uint32_t FLASH_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
-
- /* Clear the flags */
- FLASH->SR = FLASH_FLAG;
-}
-
-/**
- * @brief Returns the FLASH Status.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_GetStatus(void)
-{
- FLASH_Status flashstatus = FLASH_COMPLETE;
-
- if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
- {
- flashstatus = FLASH_BUSY;
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00)
- {
- flashstatus = FLASH_ERROR_WRP;
- }
- else
- {
- if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00)
- {
- flashstatus = FLASH_ERROR_PROGRAM;
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00)
- {
- flashstatus = FLASH_ERROR_OPERATION;
- }
- else
- {
- flashstatus = FLASH_COMPLETE;
- }
- }
- }
- }
- /* Return the FLASH Status */
- return flashstatus;
-}
-
-/**
- * @brief Waits for a FLASH operation to complete.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_WaitForLastOperation(void)
-{
- __IO FLASH_Status status = FLASH_COMPLETE;
-
- /* Check for the FLASH Status */
- status = FLASH_GetStatus();
-
- /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
- Even if the FLASH operation fails, the BUSY flag will be reset and an error
- flag will be set */
- while(status == FLASH_BUSY)
- {
- status = FLASH_GetStatus();
- }
- /* Return the operation status */
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_fsmc.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the FSMC peripheral:
- * - Interface with SRAM, PSRAM, NOR and OneNAND memories
- * - Interface with NAND memories
- * - Interface with 16-bit PC Card compatible memories
- * - Interrupts and flags management
- *
- ******************************************************************************
-
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_fsmc.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup FSMC
- * @brief FSMC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* --------------------- FSMC registers bit mask ---------------------------- */
-/* FSMC BCRx Mask */
-#define BCR_MBKEN_SET ((uint32_t)0x00000001)
-#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE)
-#define BCR_FACCEN_SET ((uint32_t)0x00000040)
-
-/* FSMC PCRx Mask */
-#define PCR_PBKEN_SET ((uint32_t)0x00000004)
-#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB)
-#define PCR_ECCEN_SET ((uint32_t)0x00000040)
-#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF)
-#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FSMC_Private_Functions
- * @{
- */
-
-/** @defgroup FSMC_Group1 NOR/SRAM Controller functions
- * @brief NOR/SRAM Controller functions
- *
-@verbatim
- ===============================================================================
- NOR/SRAM Controller functions
- ===============================================================================
-
- The following sequence should be followed to configure the FSMC to interface with
- SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:
-
- 1. Enable the clock for the FSMC and associated GPIOs using the following functions:
- RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-
- 2. FSMC pins configuration
- - Connect the involved FSMC pins to AF12 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
- - Configure these FSMC pins in alternate function mode by calling the function
- GPIO_Init();
-
- 3. Declare a FSMC_NORSRAMInitTypeDef structure, for example:
- FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
- and fill the FSMC_NORSRAMInitStructure variable with the allowed values of
- the structure member.
-
- 4. Initialize the NOR/SRAM Controller by calling the function
- FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
-
- 5. Then enable the NOR/SRAM Bank, for example:
- FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
-
- 6. At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
- * reset values.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
- * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
- * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
- * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
- * @retval None
- */
-void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
-{
- /* Check the parameter */
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
-
- /* FSMC_Bank1_NORSRAM1 */
- if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
- {
- FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
- }
- /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
- else
- {
- FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
- }
- FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
- FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
-}
-
-/**
- * @brief Initializes the FSMC NOR/SRAM Banks according to the specified
- * parameters in the FSMC_NORSRAMInitStruct.
- * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure
- * that contains the configuration information for the FSMC NOR/SRAM
- * specified Banks.
- * @retval None
- */
-void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
- assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
- assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
- assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
- assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
- assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
- assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
- assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
- assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
- assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
- assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
- assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
- assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
- assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
- assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
- assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
- assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
- assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
- assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
- assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
-
- /* Bank1 NOR/SRAM control register configuration */
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
- (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
- FSMC_NORSRAMInitStruct->FSMC_MemoryType |
- FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
- FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
- FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
- FSMC_NORSRAMInitStruct->FSMC_WrapMode |
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
- FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
- FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
- FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
- FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
- if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
- {
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
- }
- /* Bank1 NOR/SRAM timing register configuration */
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
- (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
-
-
- /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
- if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
- {
- assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
- assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
- assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
- assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
- assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
- assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
- FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
- (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
- }
- else
- {
- FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
- }
-}
-
-/**
- * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
- * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
-{
- /* Reset NOR/SRAM Init structure parameters values */
- FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
- FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
- FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
- FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
- FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
- FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
- FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
- FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
- FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
- FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
- FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
-}
-
-/**
- * @brief Enables or disables the specified NOR/SRAM Memory Bank.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
- * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
- * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
- * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
- * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
-{
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
- FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET;
- }
- else
- {
- /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
- FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup FSMC_Group2 NAND Controller functions
- * @brief NAND Controller functions
- *
-@verbatim
- ===============================================================================
- NAND Controller functions
- ===============================================================================
-
- The following sequence should be followed to configure the FSMC to interface with
- 8-bit or 16-bit NAND memory connected to the NAND Bank:
-
- 1. Enable the clock for the FSMC and associated GPIOs using the following functions:
- RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-
- 2. FSMC pins configuration
- - Connect the involved FSMC pins to AF12 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
- - Configure these FSMC pins in alternate function mode by calling the function
- GPIO_Init();
-
- 3. Declare a FSMC_NANDInitTypeDef structure, for example:
- FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
- and fill the FSMC_NANDInitStructure variable with the allowed values of
- the structure member.
-
- 4. Initialize the NAND Controller by calling the function
- FSMC_NANDInit(&FSMC_NANDInitStructure);
-
- 5. Then enable the NAND Bank, for example:
- FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE);
-
- 6. At this stage you can read/write from/to the memory connected to the NAND Bank.
-
-@note To enable the Error Correction Code (ECC), you have to use the function
- FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE);
- and to get the current ECC value you have to use the function
- ECCval = FSMC_GetECC(FSMC_Bank3_NAND);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @retval None
- */
-void FSMC_NANDDeInit(uint32_t FSMC_Bank)
-{
- /* Check the parameter */
- assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- /* Set the FSMC_Bank2 registers to their reset values */
- FSMC_Bank2->PCR2 = 0x00000018;
- FSMC_Bank2->SR2 = 0x00000040;
- FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
- FSMC_Bank2->PATT2 = 0xFCFCFCFC;
- }
- /* FSMC_Bank3_NAND */
- else
- {
- /* Set the FSMC_Bank3 registers to their reset values */
- FSMC_Bank3->PCR3 = 0x00000018;
- FSMC_Bank3->SR3 = 0x00000040;
- FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
- FSMC_Bank3->PATT3 = 0xFCFCFCFC;
- }
-}
-
-/**
- * @brief Initializes the FSMC NAND Banks according to the specified parameters
- * in the FSMC_NANDInitStruct.
- * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that
- * contains the configuration information for the FSMC NAND specified Banks.
- * @retval None
- */
-void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
-{
- uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
-
- /* Check the parameters */
- assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
- assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
- assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
- assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
- assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
- assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
- assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
- assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
- assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
-
- /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
- tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
- PCR_MEMORYTYPE_NAND |
- FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
- FSMC_NANDInitStruct->FSMC_ECC |
- FSMC_NANDInitStruct->FSMC_ECCPageSize |
- (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
- (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
-
- /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
- tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
- /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
- tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
- if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
- {
- /* FSMC_Bank2_NAND registers configuration */
- FSMC_Bank2->PCR2 = tmppcr;
- FSMC_Bank2->PMEM2 = tmppmem;
- FSMC_Bank2->PATT2 = tmppatt;
- }
- else
- {
- /* FSMC_Bank3_NAND registers configuration */
- FSMC_Bank3->PCR3 = tmppcr;
- FSMC_Bank3->PMEM3 = tmppmem;
- FSMC_Bank3->PATT3 = tmppatt;
- }
-}
-
-
-/**
- * @brief Fills each FSMC_NANDInitStruct member with its default value.
- * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
-{
- /* Reset NAND Init structure parameters values */
- FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
- FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
- FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
- FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
- FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
- FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
- FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
-}
-
-/**
- * @brief Enables or disables the specified NAND Memory Bank.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
-{
- assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->PCR2 |= PCR_PBKEN_SET;
- }
- else
- {
- FSMC_Bank3->PCR3 |= PCR_PBKEN_SET;
- }
- }
- else
- {
- /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET;
- }
- else
- {
- FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET;
- }
- }
-}
-/**
- * @brief Enables or disables the FSMC NAND ECC feature.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @param NewState: new state of the FSMC NAND ECC feature.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
-{
- assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->PCR2 |= PCR_ECCEN_SET;
- }
- else
- {
- FSMC_Bank3->PCR3 |= PCR_ECCEN_SET;
- }
- }
- else
- {
- /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET;
- }
- else
- {
- FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET;
- }
- }
-}
-
-/**
- * @brief Returns the error correction code register value.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @retval The Error Correction Code (ECC) value.
- */
-uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
-{
- uint32_t eccval = 0x00000000;
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- /* Get the ECCR2 register value */
- eccval = FSMC_Bank2->ECCR2;
- }
- else
- {
- /* Get the ECCR3 register value */
- eccval = FSMC_Bank3->ECCR3;
- }
- /* Return the error correction code value */
- return(eccval);
-}
-/**
- * @}
- */
-
-/** @defgroup FSMC_Group3 PCCARD Controller functions
- * @brief PCCARD Controller functions
- *
-@verbatim
- ===============================================================================
- PCCARD Controller functions
- ===============================================================================
-
- The following sequence should be followed to configure the FSMC to interface with
- 16-bit PC Card compatible memory connected to the PCCARD Bank:
-
- 1. Enable the clock for the FSMC and associated GPIOs using the following functions:
- RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-
- 2. FSMC pins configuration
- - Connect the involved FSMC pins to AF12 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
- - Configure these FSMC pins in alternate function mode by calling the function
- GPIO_Init();
-
- 3. Declare a FSMC_PCCARDInitTypeDef structure, for example:
- FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure;
- and fill the FSMC_PCCARDInitStructure variable with the allowed values of
- the structure member.
-
- 4. Initialize the PCCARD Controller by calling the function
- FSMC_PCCARDInit(&FSMC_PCCARDInitStructure);
-
- 5. Then enable the PCCARD Bank:
- FSMC_PCCARDCmd(ENABLE);
-
- 6. At this stage you can read/write from/to the memory connected to the PCCARD Bank.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
- * @param None
- * @retval None
- */
-void FSMC_PCCARDDeInit(void)
-{
- /* Set the FSMC_Bank4 registers to their reset values */
- FSMC_Bank4->PCR4 = 0x00000018;
- FSMC_Bank4->SR4 = 0x00000000;
- FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
- FSMC_Bank4->PATT4 = 0xFCFCFCFC;
- FSMC_Bank4->PIO4 = 0xFCFCFCFC;
-}
-
-/**
- * @brief Initializes the FSMC PCCARD Bank according to the specified parameters
- * in the FSMC_PCCARDInitStruct.
- * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure
- * that contains the configuration information for the FSMC PCCARD Bank.
- * @retval None
- */
-void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
- assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
- assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
-
- assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
-
- assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
- assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
-
- /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
- FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
- FSMC_MemoryDataWidth_16b |
- (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
- (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
-
- /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
- FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
- /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
- FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
- /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
- FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-}
-
-/**
- * @brief Fills each FSMC_PCCARDInitStruct member with its default value.
- * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
-{
- /* Reset PCCARD Init structure parameters values */
- FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
- FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
- FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
-}
-
-/**
- * @brief Enables or disables the PCCARD Memory Bank.
- * @param NewState: new state of the PCCARD Memory Bank.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FSMC_PCCARDCmd(FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
- FSMC_Bank4->PCR4 |= PCR_PBKEN_SET;
- }
- else
- {
- /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
- FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup FSMC_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified FSMC interrupts.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
- * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
- * @arg FSMC_IT_Level: Level edge detection interrupt.
- * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
- * @param NewState: new state of the specified FSMC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
-{
- assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
- assert_param(IS_FSMC_IT(FSMC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected FSMC_Bank2 interrupts */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->SR2 |= FSMC_IT;
- }
- /* Enable the selected FSMC_Bank3 interrupts */
- else if (FSMC_Bank == FSMC_Bank3_NAND)
- {
- FSMC_Bank3->SR3 |= FSMC_IT;
- }
- /* Enable the selected FSMC_Bank4 interrupts */
- else
- {
- FSMC_Bank4->SR4 |= FSMC_IT;
- }
- }
- else
- {
- /* Disable the selected FSMC_Bank2 interrupts */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
-
- FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
- }
- /* Disable the selected FSMC_Bank3 interrupts */
- else if (FSMC_Bank == FSMC_Bank3_NAND)
- {
- FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
- }
- /* Disable the selected FSMC_Bank4 interrupts */
- else
- {
- FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
- }
- }
-}
-
-/**
- * @brief Checks whether the specified FSMC flag is set or not.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
- * @param FSMC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.
- * @arg FSMC_FLAG_Level: Level detection Flag.
- * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.
- * @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
- * @retval The new state of FSMC_FLAG (SET or RESET).
- */
-FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tmpsr = 0x00000000;
-
- /* Check the parameters */
- assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
- assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- tmpsr = FSMC_Bank2->SR2;
- }
- else if(FSMC_Bank == FSMC_Bank3_NAND)
- {
- tmpsr = FSMC_Bank3->SR3;
- }
- /* FSMC_Bank4_PCCARD*/
- else
- {
- tmpsr = FSMC_Bank4->SR4;
- }
-
- /* Get the flag status */
- if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the FSMC's pending flags.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
- * @param FSMC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.
- * @arg FSMC_FLAG_Level: Level detection Flag.
- * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.
- * @retval None
- */
-void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
- assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->SR2 &= ~FSMC_FLAG;
- }
- else if(FSMC_Bank == FSMC_Bank3_NAND)
- {
- FSMC_Bank3->SR3 &= ~FSMC_FLAG;
- }
- /* FSMC_Bank4_PCCARD*/
- else
- {
- FSMC_Bank4->SR4 &= ~FSMC_FLAG;
- }
-}
-
-/**
- * @brief Checks whether the specified FSMC interrupt has occurred or not.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
- * @param FSMC_IT: specifies the FSMC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
- * @arg FSMC_IT_Level: Level edge detection interrupt.
- * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
- * @retval The new state of FSMC_IT (SET or RESET).
- */
-ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
-
- /* Check the parameters */
- assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
- assert_param(IS_FSMC_GET_IT(FSMC_IT));
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- tmpsr = FSMC_Bank2->SR2;
- }
- else if(FSMC_Bank == FSMC_Bank3_NAND)
- {
- tmpsr = FSMC_Bank3->SR3;
- }
- /* FSMC_Bank4_PCCARD*/
- else
- {
- tmpsr = FSMC_Bank4->SR4;
- }
-
- itstatus = tmpsr & FSMC_IT;
-
- itenable = tmpsr & (FSMC_IT >> 3);
- if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the FSMC's interrupt pending bits.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
- * @param FSMC_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
- * @arg FSMC_IT_Level: Level edge detection interrupt.
- * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
- * @retval None
- */
-void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
- assert_param(IS_FSMC_IT(FSMC_IT));
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
- }
- else if(FSMC_Bank == FSMC_Bank3_NAND)
- {
- FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
- }
- /* FSMC_Bank4_PCCARD*/
- else
- {
- FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_gpio.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the GPIO peripheral:
- * - Initialization and Configuration
- * - GPIO Read and Write
- * - GPIO Alternate functions configuration
- *
- * @verbatim
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * 1. Enable the GPIO AHB clock using the following function
- * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
- *
- * 2. Configure the GPIO pin(s) using GPIO_Init()
- * Four possible configuration are available for each pin:
- * - Input: Floating, Pull-up, Pull-down.
- * - Output: Push-Pull (Pull-up, Pull-down or no Pull)
- * Open Drain (Pull-up, Pull-down or no Pull).
- * In output mode, the speed is configurable: 2 MHz, 25 MHz,
- * 50 MHz or 100 MHz.
- * - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)
- * Open Drain (Pull-up, Pull-down or no Pull).
- * - Analog: required mode when a pin is to be used as ADC channel
- * or DAC output.
- *
- * 3- Peripherals alternate function:
- * - For ADC and DAC, configure the desired pin in analog mode using
- * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN;
- * - For other peripherals (TIM, USART...):
- * - Connect the pin to the desired peripherals' Alternate
- * Function (AF) using GPIO_PinAFConfig() function
- * - Configure the desired pin in alternate function mode using
- * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- * - Select the type, pull-up/pull-down and output speed via
- * GPIO_PuPd, GPIO_OType and GPIO_Speed members
- * - Call GPIO_Init() function
- *
- * 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
- *
- * 5. To set/reset the level of a pin configured in output mode use
- * GPIO_SetBits()/GPIO_ResetBits()
- *
- * 6. During and just after reset, the alternate functions are not
- * active and the GPIO pins are configured in input floating mode
- * (except JTAG pins).
- *
- * 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as
- * general-purpose (PC14 and PC15, respectively) when the LSE
- * oscillator is off. The LSE has priority over the GPIO function.
- *
- * 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as
- * general-purpose PH0 and PH1, respectively, when the HSE
- * oscillator is off. The HSE has priority over the GPIO function.
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_gpio.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup GPIO
- * @brief GPIO driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup GPIO_Private_Functions
- * @{
- */
-
-/** @defgroup GPIO_Group1 Initialization and Configuration
- * @brief Initialization and Configuration
- *
-@verbatim
- ===============================================================================
- Initialization and Configuration
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the GPIOx peripheral registers to their default reset values.
- * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins).
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @retval None
- */
-void GPIO_DeInit(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- if (GPIOx == GPIOA)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);
- }
- else if (GPIOx == GPIOB)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);
- }
- else if (GPIOx == GPIOC)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);
- }
- else if (GPIOx == GPIOD)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);
- }
- else if (GPIOx == GPIOE)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);
- }
- else if (GPIOx == GPIOF)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);
- }
- else if (GPIOx == GPIOG)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);
- }
- else if (GPIOx == GPIOH)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);
- }
- else
- {
- if (GPIOx == GPIOI)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
- * the configuration information for the specified GPIO peripheral.
- * @retval None
- */
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
-{
- uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
- assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
- assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
-
- /* -------------------------Configure the port pins---------------- */
- /*-- GPIO Mode Configuration --*/
- for (pinpos = 0x00; pinpos < 0x10; pinpos++)
- {
- pos = ((uint32_t)0x01) << pinpos;
- /* Get the port pins position */
- currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
-
- if (currentpin == pos)
- {
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
- GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
-
- if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
- {
- /* Check Speed mode parameters */
- assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
-
- /* Speed mode configuration */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
- GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
-
- /* Check Output mode parameters */
- assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
-
- /* Output mode configuration*/
- GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
- GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
- }
-
- /* Pull-up Pull down resistor configuration*/
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
- GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
- }
- }
-}
-
-/**
- * @brief Fills each GPIO_InitStruct member with its default value.
- * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
-{
- /* Reset GPIO init structure parameters values */
- GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
- GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
- GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
-}
-
-/**
- * @brief Locks GPIO Pins configuration registers.
- * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
- * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
- * @note The configuration of the locked GPIO pins can no longer be modified
- * until the next reset.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to be locked.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- __IO uint32_t tmp = 0x00010000;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- tmp |= GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Reset LCKK bit */
- GPIOx->LCKR = GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Read LCKK bit*/
- tmp = GPIOx->LCKR;
- /* Read LCKK bit*/
- tmp = GPIOx->LCKR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Group2 GPIO Read and Write
- * @brief GPIO Read and Write
- *
-@verbatim
- ===============================================================================
- GPIO Read and Write
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads the specified input port pin.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to read.
- * This parameter can be GPIO_Pin_x where x can be (0..15).
- * @retval The input port pin value.
- */
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified GPIO input data port.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @retval GPIO input data port value.
- */
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->IDR);
-}
-
-/**
- * @brief Reads the specified output data port bit.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to read.
- * This parameter can be GPIO_Pin_x where x can be (0..15).
- * @retval The output port pin value.
- */
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified GPIO output data port.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @retval GPIO output data port value.
- */
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->ODR);
-}
-
-/**
- * @brief Sets the selected data port bits.
- * @note This functions uses GPIOx_BSRR register to allow atomic read/modify
- * accesses. In this way, there is no risk of an IRQ occurring between
- * the read and the modify access.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bits to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BSRRL = GPIO_Pin;
-}
-
-/**
- * @brief Clears the selected data port bits.
- * @note This functions uses GPIOx_BSRR register to allow atomic read/modify
- * accesses. In this way, there is no risk of an IRQ occurring between
- * the read and the modify access.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bits to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BSRRH = GPIO_Pin;
-}
-
-/**
- * @brief Sets or clears the selected data port bit.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to be written.
- * This parameter can be one of GPIO_Pin_x where x can be (0..15).
- * @param BitVal: specifies the value to be written to the selected bit.
- * This parameter can be one of the BitAction enum values:
- * @arg Bit_RESET: to clear the port pin
- * @arg Bit_SET: to set the port pin
- * @retval None
- */
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_BIT_ACTION(BitVal));
-
- if (BitVal != Bit_RESET)
- {
- GPIOx->BSRRL = GPIO_Pin;
- }
- else
- {
- GPIOx->BSRRH = GPIO_Pin ;
- }
-}
-
-/**
- * @brief Writes data to the specified GPIO data port.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param PortVal: specifies the value to be written to the port output data register.
- * @retval None
- */
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- GPIOx->ODR = PortVal;
-}
-
-/**
- * @brief Toggles the specified GPIO pins..
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param GPIO_Pin: Specifies the pins to be toggled.
- * @retval None
- */
-void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- GPIOx->ODR ^= GPIO_Pin;
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function
- * @brief GPIO Alternate functions configuration function
- *
-@verbatim
- ===============================================================================
- GPIO Alternate functions configuration function
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Changes the mapping of the specified pin.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param GPIO_PinSource: specifies the pin for the Alternate function.
- * This parameter can be GPIO_PinSourcex where x can be (0..15).
- * @param GPIO_AFSelection: selects the pin to used as Alternate function.
- * This parameter can be one of the following values:
- * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset)
- * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset)
- * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset)
- * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset)
- * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
- * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1
- * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1
- * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
- * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
- * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
- * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3
- * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
- * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
- * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
- * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
- * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
- * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4
- * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
- * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
- * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
- * @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
- * @arg GPIO_AF_USART1: Connect USART1 pins to AF7
- * @arg GPIO_AF_USART2: Connect USART2 pins to AF7
- * @arg GPIO_AF_USART3: Connect USART3 pins to AF7
- * @arg GPIO_AF_UART4: Connect UART4 pins to AF8
- * @arg GPIO_AF_UART5: Connect UART5 pins to AF8
- * @arg GPIO_AF_USART6: Connect USART6 pins to AF8
- * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9
- * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9
- * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9
- * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9
- * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9
- * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
- * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
- * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11
- * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
- * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
- * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
- * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
- * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
- * @retval None
- */
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
-{
- uint32_t temp = 0x00;
- uint32_t temp_2 = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
- assert_param(IS_GPIO_AF(GPIO_AF));
-
- temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
- GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
- temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
- GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_hash.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the HASH / HMAC Processor (HASH) peripheral:
- * - Initialization and Configuration functions
- * - Message Digest generation functions
- * - context swapping functions
- * - DMA interface function
- * - Interrupts and flags management
- *
- * @verbatim
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * HASH operation :
- * ----------------
- * 1. Enable the HASH controller clock using
- * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function.
- *
- * 2. Initialise the HASH using HASH_Init() function.
- *
- * 3 . Reset the HASH processor core, so that the HASH will be ready
- * to compute he message digest of a new message by using
- * HASH_Reset() function.
- *
- * 4. Enable the HASH controller using the HASH_Cmd() function.
- *
- * 5. if using DMA for Data input transfer, Activate the DMA Request
- * using HASH_DMACmd() function
- *
- * 6. if DMA is not used for data transfer, use HASH_DataIn() function
- * to enter data to IN FIFO.
- *
- *
- * 7. Configure the Number of valid bits in last word of the message
- * using HASH_SetLastWordValidBitsNbr() function.
- *
- * 8. if the message length is not an exact multiple of 512 bits,
- * then the function HASH_StartDigest() must be called to
- * launch the computation of the final digest.
- *
- * 9. Once computed, the digest can be read using HASH_GetDigest()
- * function.
- *
- * 10. To control HASH events you can use one of the following
- * two methods:
- * a- Check on HASH flags using the HASH_GetFlagStatus() function.
- * b- Use HASH interrupts through the function HASH_ITConfig() at
- * initialization phase and HASH_GetITStatus() function into
- * interrupt routines in hashing phase.
- * After checking on a flag you should clear it using HASH_ClearFlag()
- * function. And after checking on an interrupt event you should
- * clear it using HASH_ClearITPendingBit() function.
- *
- * 11. Save and restore hash processor context using
- * HASH_SaveContext() and HASH_RestoreContext() functions.
- *
- *
- *
- * HMAC operation :
- * ----------------
- * The HMAC algorithm is used for message authentication, by
- * irreversibly binding the message being processed to a key chosen
- * by the user.
- * For HMAC specifications, refer to "HMAC: keyed-hashing for message
- * authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997"
- *
- * Basically, the HMAC algorithm consists of two nested hash operations:
- * HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)]
- * where:
- * - "pad" is a sequence of zeroes needed to extend the key to the
- * length of the underlying hash function data block (that is
- * 512 bits for both the SHA-1 and MD5 hash algorithms)
- * - "|" represents the concatenation operator
- *
- *
- * To compute the HMAC, four different phases are required:
- *
- * 1. Initialise the HASH using HASH_Init() function to do HMAC
- * operation.
- *
- * 2. The key (to be used for the inner hash function) is then given
- * to the core. This operation follows the same mechanism as the
- * one used to send the message in the hash operation (that is,
- * by HASH_DataIn() function and, finally,
- * HASH_StartDigest() function.
- *
- * 3. Once the last word has been entered and computation has started,
- * the hash processor elaborates the key. It is then ready to
- * accept the message text using the same mechanism as the one
- * used to send the message in the hash operation.
- *
- * 4. After the first hash round, the hash processor returns "ready"
- * to indicate that it is ready to receive the key to be used for
- * the outer hash function (normally, this key is the same as the
- * one used for the inner hash function). When the last word of
- * the key is entered and computation starts, the HMAC result is
- * made available using HASH_GetDigest() function.
- *
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hash.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup HASH
- * @brief HASH driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HASH_Private_Functions
- * @{
- */
-
-/** @defgroup HASH_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- Initialization and Configuration functions
- ===============================================================================
- This section provides functions allowing to
- - Initialize the HASH peripheral
- - Configure the HASH Processor
- - MD5/SHA1,
- - HASH/HMAC,
- - datatype
- - HMAC Key (if mode = HMAC)
- - Reset the HASH Processor
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the HASH peripheral registers to their default reset values
- * @param None
- * @retval None
- */
-void HASH_DeInit(void)
-{
- /* Enable HASH reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE);
- /* Release HASH from reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE);
-}
-
-/**
- * @brief Initializes the HASH peripheral according to the specified parameters
- * in the HASH_InitStruct structure.
- * @note the hash processor is reset when calling this function so that the
- * HASH will be ready to compute the message digest of a new message.
- * There is no need to call HASH_Reset() function.
- * @param HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains
- * the configuration information for the HASH peripheral.
- * @note The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only
- * if the algorithm mode is HMAC.
- * @retval None
- */
-void HASH_Init(HASH_InitTypeDef* HASH_InitStruct)
-{
- /* Check the parameters */
- assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection));
- assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType));
- assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode));
-
- /* Configure the Algorithm used, algorithm mode and the datatype */
- HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE);
- HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \
- HASH_InitStruct->HASH_DataType | \
- HASH_InitStruct->HASH_AlgoMode);
-
- /* if algorithm mode is HMAC, set the Key */
- if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC)
- {
- assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType));
- HASH->CR &= ~HASH_CR_LKEY;
- HASH->CR |= HASH_InitStruct->HASH_HMACKeyType;
- }
-
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
-}
-
-/**
- * @brief Fills each HASH_InitStruct member with its default value.
- * @param HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will
- * be initialized.
- * @note The default values set are : Processor mode is HASH, Algorithm selected is SHA1,
- * Data type selected is 32b and HMAC Key Type is short key.
- * @retval None
- */
-void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct)
-{
- /* Initialize the HASH_AlgoSelection member */
- HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
-
- /* Initialize the HASH_AlgoMode member */
- HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH;
-
- /* Initialize the HASH_DataType member */
- HASH_InitStruct->HASH_DataType = HASH_DataType_32b;
-
- /* Initialize the HASH_HMACKeyType member */
- HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
-}
-
-/**
- * @brief Resets the HASH processor core, so that the HASH will be ready
- * to compute the message digest of a new message.
- * @note Calling this function will clear the HASH_SR_DCIS (Digest calculation
- * completion interrupt status) bit corresponding to HASH_IT_DCI
- * interrupt and HASH_FLAG_DCIS flag.
- * @param None
- * @retval None
- */
-void HASH_Reset(void)
-{
- /* Reset the HASH processor core */
- HASH->CR |= HASH_CR_INIT;
-}
-/**
- * @}
- */
-
-/** @defgroup HASH_Group2 Message Digest generation functions
- * @brief Message Digest generation functions
- *
-@verbatim
- ===============================================================================
- Message Digest generation functions
- ===============================================================================
- This section provides functions allowing the generation of message digest:
- - Push data in the IN FIFO : using HASH_DataIn()
- - Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr()
- - set the last word valid bits number using HASH_SetLastWordValidBitsNbr()
- - start digest calculation : using HASH_StartDigest()
- - Get the Digest message : using HASH_GetDigest()
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Configure the Number of valid bits in last word of the message
- * @param ValidNumber: Number of valid bits in last word of the message.
- * This parameter must be a number between 0 and 0x1F.
- * - 0x00: All 32 bits of the last data written are valid
- * - 0x01: Only bit [0] of the last data written is valid
- * - 0x02: Only bits[1:0] of the last data written are valid
- * - 0x03: Only bits[2:0] of the last data written are valid
- * - ...
- * - 0x1F: Only bits[30:0] of the last data written are valid
- * @note The Number of valid bits must be set before to start the message
- * digest competition (in Hash and HMAC) and key treatment(in HMAC).
- * @retval None
- */
-void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber)
-{
- /* Check the parameters */
- assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber));
-
- /* Configure the Number of valid bits in last word of the message */
- HASH->STR &= ~(HASH_STR_NBW);
- HASH->STR |= ValidNumber;
-}
-
-/**
- * @brief Writes data in the Data Input FIFO
- * @param Data: new data of the message to be processed.
- * @retval None
- */
-void HASH_DataIn(uint32_t Data)
-{
- /* Write in the DIN register a new data */
- HASH->DIN = Data;
-}
-
-/**
- * @brief Returns the number of words already pushed into the IN FIFO.
- * @param None
- * @retval The value of words already pushed into the IN FIFO.
- */
-uint8_t HASH_GetInFIFOWordsNbr(void)
-{
- /* Return the value of NBW bits */
- return ((HASH->CR & HASH_CR_NBW) >> 8);
-}
-
-/**
- * @brief Provides the message digest result.
- * @note In MD5 mode, Data[4] filed of HASH_MsgDigest structure is not used
- * and is read as zero.
- * @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will
- * hold the message digest result
- * @retval None
- */
-void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest)
-{
- /* Get the data field */
- HASH_MessageDigest->Data[0] = HASH->HR[0];
- HASH_MessageDigest->Data[1] = HASH->HR[1];
- HASH_MessageDigest->Data[2] = HASH->HR[2];
- HASH_MessageDigest->Data[3] = HASH->HR[3];
- HASH_MessageDigest->Data[4] = HASH->HR[4];
-}
-
-/**
- * @brief Starts the message padding and calculation of the final message
- * @param None
- * @retval None
- */
-void HASH_StartDigest(void)
-{
- /* Start the Digest calculation */
- HASH->STR |= HASH_STR_DCAL;
-}
-/**
- * @}
- */
-
-/** @defgroup HASH_Group3 Context swapping functions
- * @brief Context swapping functions
- *
-@verbatim
- ===============================================================================
- Context swapping functions
- ===============================================================================
-
- This section provides functions allowing to save and store HASH Context
-
- It is possible to interrupt a HASH/HMAC process to perform another processing
- with a higher priority, and to complete the interrupted process later on, when
- the higher priority task is complete. To do so, the context of the interrupted
- task must be saved from the HASH registers to memory, and then be restored
- from memory to the HASH registers.
-
- 1. To save the current context, use HASH_SaveContext() function
- 2. To restore the saved context, use HASH_RestoreContext() function
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Save the Hash peripheral Context.
- * @note The context can be saved only when no block is currently being
- * processed. So user must wait for DINIS = 1 (the last block has been
- * processed and the input FIFO is empty) or NBW != 0 (the FIFO is not
- * full and no processing is ongoing).
- * @param HASH_ContextSave: pointer to a HASH_Context structure that contains
- * the repository for current context.
- * @retval None
- */
-void HASH_SaveContext(HASH_Context* HASH_ContextSave)
-{
- uint8_t i = 0;
-
- /* save context registers */
- HASH_ContextSave->HASH_IMR = HASH->IMR;
- HASH_ContextSave->HASH_STR = HASH->STR;
- HASH_ContextSave->HASH_CR = HASH->CR;
- for(i=0; i<=50;i++)
- {
- HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i];
- }
-}
-
-/**
- * @brief Restore the Hash peripheral Context.
- * @note After calling this function, user can restart the processing from the
- * point where it has been interrupted.
- * @param HASH_ContextRestore: pointer to a HASH_Context structure that contains
- * the repository for saved context.
- * @retval None
- */
-void HASH_RestoreContext(HASH_Context* HASH_ContextRestore)
-{
- uint8_t i = 0;
-
- /* restore context registers */
- HASH->IMR = HASH_ContextRestore->HASH_IMR;
- HASH->STR = HASH_ContextRestore->HASH_STR;
- HASH->CR = HASH_ContextRestore->HASH_CR;
-
- /* Initialize the hash processor */
- HASH->CR |= HASH_CR_INIT;
-
- /* continue restoring context registers */
- for(i=0; i<=50;i++)
- {
- HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i];
- }
-}
-/**
- * @}
- */
-
-/** @defgroup HASH_Group4 HASH's DMA interface Configuration function
- * @brief HASH's DMA interface Configuration function
- *
-@verbatim
- ===============================================================================
- HASH's DMA interface Configuration function
- ===============================================================================
-
- This section provides functions allowing to configure the DMA interface for
- HASH/ HMAC data input transfer.
-
- When the DMA mode is enabled (using the HASH_DMACmd() function), data can be
- sent to the IN FIFO using the DMA peripheral.
-
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the HASH DMA interface.
- * @note The DMA is disabled by hardware after the end of transfer.
- * @param NewState: new state of the selected HASH DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void HASH_DMACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the HASH DMA request */
- HASH->CR |= HASH_CR_DMAE;
- }
- else
- {
- /* Disable the HASH DMA request */
- HASH->CR &= ~HASH_CR_DMAE;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup HASH_Group5 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
-
- This section provides functions allowing to configure the HASH Interrupts and
- to get the status and clear flags and Interrupts pending bits.
-
- The HASH provides 2 Interrupts sources and 5 Flags:
-
- Flags :
- ----------
- 1. HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO
- which means that a new block (512 bit) can be entered
- into the input buffer.
-
- 2. HASH_FLAG_DCIS : set when Digest calculation is complete
-
- 3. HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or
- a transfer is ongoing.
- This Flag is cleared only by hardware.
-
- 4. HASH_FLAG_BUSY : set when The hash core is processing a block of data
- This Flag is cleared only by hardware.
-
- 5. HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that
- the Data IN FIFO contains at least one word of data.
- This Flag is cleared only by hardware.
-
- Interrupts :
- ------------
-
- 1. HASH_IT_DINI : if enabled, this interrupt source is pending when 16
- locations are free in the Data IN FIFO which means that
- a new block (512 bit) can be entered into the input buffer.
- This interrupt source is cleared using
- HASH_ClearITPendingBit(HASH_IT_DINI) function.
-
- 2. HASH_IT_DCI : if enabled, this interrupt source is pending when Digest
- calculation is complete.
- This interrupt source is cleared using
- HASH_ClearITPendingBit(HASH_IT_DCI) function.
-
- Managing the HASH controller events :
- ------------------------------------
- The user should identify which mode will be used in his application to manage
- the HASH controller events: Polling mode or Interrupt mode.
-
- 1. In the Polling Mode it is advised to use the following functions:
- - HASH_GetFlagStatus() : to check if flags events occur.
- - HASH_ClearFlag() : to clear the flags events.
-
- 2. In the Interrupt Mode it is advised to use the following functions:
- - HASH_ITConfig() : to enable or disable the interrupt source.
- - HASH_GetITStatus() : to check if Interrupt occurs.
- - HASH_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified HASH interrupts.
- * @param HASH_IT: specifies the HASH interrupt source to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg HASH_IT_DINI: Data Input interrupt
- * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
- * @param NewState: new state of the specified HASH interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_HASH_IT(HASH_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected HASH interrupt */
- HASH->IMR |= HASH_IT;
- }
- else
- {
- /* Disable the selected HASH interrupt */
- HASH->IMR &= (uint8_t) ~HASH_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified HASH flag is set or not.
- * @param HASH_FLAG: specifies the HASH flag to check.
- * This parameter can be one of the following values:
- * @arg HASH_FLAG_DINIS: Data input interrupt status flag
- * @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag
- * @arg HASH_FLAG_BUSY: Busy flag
- * @arg HASH_FLAG_DMAS: DMAS Status flag
- * @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag
- * @retval The new state of HASH_FLAG (SET or RESET)
- */
-FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tempreg = 0;
-
- /* Check the parameters */
- assert_param(IS_HASH_GET_FLAG(HASH_FLAG));
-
- /* check if the FLAG is in CR register */
- if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint16_t)RESET )
- {
- tempreg = HASH->CR;
- }
- else /* The FLAG is in SR register */
- {
- tempreg = HASH->SR;
- }
-
- /* Check the status of the specified HASH flag */
- if ((tempreg & HASH_FLAG) != (uint16_t)RESET)
- {
- /* HASH is set */
- bitstatus = SET;
- }
- else
- {
- /* HASH_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the HASH_FLAG status */
- return bitstatus;
-}
-/**
- * @brief Clears the HASH flags.
- * @param HASH_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg HASH_FLAG_DINIS: Data Input Flag
- * @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag
- * @retval None
- */
-void HASH_ClearFlag(uint16_t HASH_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG));
-
- /* Clear the selected HASH flags */
- HASH->SR = ~(uint32_t)HASH_FLAG;
-}
-/**
- * @brief Checks whether the specified HASH interrupt has occurred or not.
- * @param HASH_IT: specifies the HASH interrupt source to check.
- * This parameter can be one of the following values:
- * @arg HASH_IT_DINI: Data Input interrupt
- * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
- * @retval The new state of HASH_IT (SET or RESET).
- */
-ITStatus HASH_GetITStatus(uint8_t HASH_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_HASH_GET_IT(HASH_IT));
-
-
- /* Check the status of the specified HASH interrupt */
- tmpreg = HASH->SR;
-
- if (((HASH->IMR & tmpreg) & HASH_IT) != RESET)
- {
- /* HASH_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* HASH_IT is reset */
- bitstatus = RESET;
- }
- /* Return the HASH_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the HASH interrupt pending bit(s).
- * @param HASH_IT: specifies the HASH interrupt pending bit(s) to clear.
- * This parameter can be any combination of the following values:
- * @arg HASH_IT_DINI: Data Input interrupt
- * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
- * @retval None
- */
-void HASH_ClearITPendingBit(uint8_t HASH_IT)
-{
- /* Check the parameters */
- assert_param(IS_HASH_IT(HASH_IT));
-
- /* Clear the selected HASH interrupt pending bit */
- HASH->SR = (uint8_t)~HASH_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_hash_md5.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides high level functions to compute the HASH MD5 and
- * HMAC MD5 Digest of an input message.
- * It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
- * peripheral.
- *
- * @verbatim
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * 1. Enable The HASH controller clock using
- * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.
- *
- * 2. Calculate the HASH MD5 Digest using HASH_MD5() function.
- *
- * 3. Calculate the HMAC MD5 Digest using HMAC_MD5() function.
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hash.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup HASH
- * @brief HASH driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define MD5BUSY_TIMEOUT ((uint32_t) 0x00010000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HASH_Private_Functions
- * @{
- */
-
-/** @defgroup HASH_Group7 High Level MD5 functions
- * @brief High Level MD5 Hash and HMAC functions
- *
-@verbatim
- ===============================================================================
- High Level MD5 Hash and HMAC functions
- ===============================================================================
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Compute the HASH MD5 digest.
- * @param Input: pointer to the Input buffer to be treated.
- * @param Ilen: length of the Input buffer.
- * @param Output: the returned digest
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: digest computation done
- * - ERROR: digest computation failed
- */
-ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16])
-{
- HASH_InitTypeDef MD5_HASH_InitStructure;
- HASH_MsgDigest MD5_MessageDigest;
- __IO uint16_t nbvalidbitsdata = 0;
- uint32_t i = 0;
- __IO uint32_t counter = 0;
- uint32_t busystatus = 0;
- ErrorStatus status = SUCCESS;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
-
-
- /* Number of valid bits in last word of the Input data */
- nbvalidbitsdata = 8 * (Ilen % 4);
-
- /* HASH peripheral initialization */
- HASH_DeInit();
-
- /* HASH Configuration */
- MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5;
- MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;
- MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
- HASH_Init(&MD5_HASH_InitStructure);
-
- /* Configure the number of valid bits in last word of the data */
- HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
-
- /* Write the Input block in the IN FIFO */
- for(i=0; i<Ilen; i+=4)
- {
- HASH_DataIn(*(uint32_t*)inputaddr);
- inputaddr+=4;
- }
-
- /* Start the HASH processor */
- HASH_StartDigest();
-
- /* wait until the Busy flag is RESET */
- do
- {
- busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
- counter++;
- }while ((counter != MD5BUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
- /* Read the message digest */
- HASH_GetDigest(&MD5_MessageDigest);
- *(uint32_t*)(outputaddr) = __REV(MD5_MessageDigest.Data[0]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(MD5_MessageDigest.Data[1]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(MD5_MessageDigest.Data[2]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(MD5_MessageDigest.Data[3]);
- }
- return status;
-}
-
-/**
- * @brief Compute the HMAC MD5 digest.
- * @param Key: pointer to the Key used for HMAC.
- * @param Keylen: length of the Key used for HMAC.
- * @param Input: pointer to the Input buffer to be treated.
- * @param Ilen: length of the Input buffer.
- * @param Output: the returned digest
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: digest computation done
- * - ERROR: digest computation failed
- */
-ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, uint8_t *Input,
- uint32_t Ilen, uint8_t Output[16])
-{
- HASH_InitTypeDef MD5_HASH_InitStructure;
- HASH_MsgDigest MD5_MessageDigest;
- __IO uint16_t nbvalidbitsdata = 0;
- __IO uint16_t nbvalidbitskey = 0;
- uint32_t i = 0;
- __IO uint32_t counter = 0;
- uint32_t busystatus = 0;
- ErrorStatus status = SUCCESS;
- uint32_t keyaddr = (uint32_t)Key;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
-
- /* Number of valid bits in last word of the Input data */
- nbvalidbitsdata = 8 * (Ilen % 4);
-
- /* Number of valid bits in last word of the Key */
- nbvalidbitskey = 8 * (Keylen % 4);
-
- /* HASH peripheral initialization */
- HASH_DeInit();
-
- /* HASH Configuration */
- MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5;
- MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HMAC;
- MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
- if(Keylen > 64)
- {
- /* HMAC long Key */
- MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;
- }
- else
- {
- /* HMAC short Key */
- MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
- }
- HASH_Init(&MD5_HASH_InitStructure);
-
- /* Configure the number of valid bits in last word of the Key */
- HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
-
- /* Write the Key */
- for(i=0; i<Keylen; i+=4)
- {
- HASH_DataIn(*(uint32_t*)keyaddr);
- keyaddr+=4;
- }
-
- /* Start the HASH processor */
- HASH_StartDigest();
-
- /* wait until the Busy flag is RESET */
- do
- {
- busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
- counter++;
- }while ((counter != MD5BUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
- /* Configure the number of valid bits in last word of the Input data */
- HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
-
- /* Write the Input block in the IN FIFO */
- for(i=0; i<Ilen; i+=4)
- {
- HASH_DataIn(*(uint32_t*)inputaddr);
- inputaddr+=4;
- }
-
- /* Start the HASH processor */
- HASH_StartDigest();
-
- /* wait until the Busy flag is RESET */
- counter =0;
- do
- {
- busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
- counter++;
- }while ((counter != MD5BUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
- /* Configure the number of valid bits in last word of the Key */
- HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
-
- /* Write the Key */
- keyaddr = (uint32_t)Key;
- for(i=0; i<Keylen; i+=4)
- {
- HASH_DataIn(*(uint32_t*)keyaddr);
- keyaddr+=4;
- }
-
- /* Start the HASH processor */
- HASH_StartDigest();
-
- /* wait until the Busy flag is RESET */
- counter =0;
- do
- {
- busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
- counter++;
- }while ((counter != MD5BUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
- /* Read the message digest */
- HASH_GetDigest(&MD5_MessageDigest);
- *(uint32_t*)(outputaddr) = __REV(MD5_MessageDigest.Data[0]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(MD5_MessageDigest.Data[1]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(MD5_MessageDigest.Data[2]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(MD5_MessageDigest.Data[3]);
- }
- }
- }
- return status;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_hash_sha1.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides high level functions to compute the HASH SHA1 and
- * HMAC SHA1 Digest of an input message.
- * It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
- * peripheral.
- *
- * @verbatim
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * 1. Enable The HASH controller clock using
- * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.
- *
- * 2. Calculate the HASH SHA1 Digest using HASH_SHA1() function.
- *
- * 3. Calculate the HMAC SHA1 Digest using HMAC_SHA1() function.
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hash.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup HASH
- * @brief HASH driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define SHA1BUSY_TIMEOUT ((uint32_t) 0x00010000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HASH_Private_Functions
- * @{
- */
-
-/** @defgroup HASH_Group6 High Level SHA1 functions
- * @brief High Level SHA1 Hash and HMAC functions
- *
-@verbatim
- ===============================================================================
- High Level SHA1 Hash and HMAC functions
- ===============================================================================
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Compute the HASH SHA1 digest.
- * @param Input: pointer to the Input buffer to be treated.
- * @param Ilen: length of the Input buffer.
- * @param Output: the returned digest
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: digest computation done
- * - ERROR: digest computation failed
- */
-ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
-{
- HASH_InitTypeDef SHA1_HASH_InitStructure;
- HASH_MsgDigest SHA1_MessageDigest;
- __IO uint16_t nbvalidbitsdata = 0;
- uint32_t i = 0;
- __IO uint32_t counter = 0;
- uint32_t busystatus = 0;
- ErrorStatus status = SUCCESS;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
-
- /* Number of valid bits in last word of the Input data */
- nbvalidbitsdata = 8 * (Ilen % 4);
-
- /* HASH peripheral initialization */
- HASH_DeInit();
-
- /* HASH Configuration */
- SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
- SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;
- SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
- HASH_Init(&SHA1_HASH_InitStructure);
-
- /* Configure the number of valid bits in last word of the data */
- HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
-
- /* Write the Input block in the IN FIFO */
- for(i=0; i<Ilen; i+=4)
- {
- HASH_DataIn(*(uint32_t*)inputaddr);
- inputaddr+=4;
- }
-
- /* Start the HASH processor */
- HASH_StartDigest();
-
- /* wait until the Busy flag is RESET */
- do
- {
- busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
- counter++;
- }while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
- /* Read the message digest */
- HASH_GetDigest(&SHA1_MessageDigest);
- *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[0]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[1]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[2]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[3]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[4]);
- }
- return status;
-}
-
-/**
- * @brief Compute the HMAC SHA1 digest.
- * @param Key: pointer to the Key used for HMAC.
- * @param Keylen: length of the Key used for HMAC.
- * @param Input: pointer to the Input buffer to be treated.
- * @param Ilen: length of the Input buffer.
- * @param Output: the returned digest
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: digest computation done
- * - ERROR: digest computation failed
- */
-ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, uint8_t *Input,
- uint32_t Ilen, uint8_t Output[20])
-{
- HASH_InitTypeDef SHA1_HASH_InitStructure;
- HASH_MsgDigest SHA1_MessageDigest;
- __IO uint16_t nbvalidbitsdata = 0;
- __IO uint16_t nbvalidbitskey = 0;
- uint32_t i = 0;
- __IO uint32_t counter = 0;
- uint32_t busystatus = 0;
- ErrorStatus status = SUCCESS;
- uint32_t keyaddr = (uint32_t)Key;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
-
- /* Number of valid bits in last word of the Input data */
- nbvalidbitsdata = 8 * (Ilen % 4);
-
- /* Number of valid bits in last word of the Key */
- nbvalidbitskey = 8 * (Keylen % 4);
-
- /* HASH peripheral initialization */
- HASH_DeInit();
-
- /* HASH Configuration */
- SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
- SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HMAC;
- SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
- if(Keylen > 64)
- {
- /* HMAC long Key */
- SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;
- }
- else
- {
- /* HMAC short Key */
- SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
- }
- HASH_Init(&SHA1_HASH_InitStructure);
-
- /* Configure the number of valid bits in last word of the Key */
- HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
-
- /* Write the Key */
- for(i=0; i<Keylen; i+=4)
- {
- HASH_DataIn(*(uint32_t*)keyaddr);
- keyaddr+=4;
- }
-
- /* Start the HASH processor */
- HASH_StartDigest();
-
- /* wait until the Busy flag is RESET */
- do
- {
- busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
- counter++;
- }while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
- /* Configure the number of valid bits in last word of the Input data */
- HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
-
- /* Write the Input block in the IN FIFO */
- for(i=0; i<Ilen; i+=4)
- {
- HASH_DataIn(*(uint32_t*)inputaddr);
- inputaddr+=4;
- }
-
- /* Start the HASH processor */
- HASH_StartDigest();
-
-
- /* wait until the Busy flag is RESET */
- counter =0;
- do
- {
- busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
- counter++;
- }while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
- /* Configure the number of valid bits in last word of the Key */
- HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
-
- /* Write the Key */
- keyaddr = (uint32_t)Key;
- for(i=0; i<Keylen; i+=4)
- {
- HASH_DataIn(*(uint32_t*)keyaddr);
- keyaddr+=4;
- }
-
- /* Start the HASH processor */
- HASH_StartDigest();
-
- /* wait until the Busy flag is RESET */
- counter =0;
- do
- {
- busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
- counter++;
- }while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
- /* Read the message digest */
- HASH_GetDigest(&SHA1_MessageDigest);
- *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[0]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[1]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[2]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[3]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[4]);
- }
- }
- }
- return status;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_i2c.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Inter-integrated circuit (I2C)
- * - Initialization and Configuration
- * - Data transfers
- * - PEC management
- * - DMA transfers management
- * - Interrupts, events and flags management
- *
- * @verbatim
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * 1. Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
- * function for I2C1, I2C2 or I2C3.
- *
- * 2. Enable SDA, SCL and SMBA (when used) GPIO clocks using
- * RCC_AHBPeriphClockCmd() function.
- *
- * 3. Peripherals alternate function:
- * - Connect the pin to the desired peripherals' Alternate
- * Function (AF) using GPIO_PinAFConfig() function
- * - Configure the desired pin in alternate function by:
- * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- * - Select the type, pull-up/pull-down and output speed via
- * GPIO_PuPd, GPIO_OType and GPIO_Speed members
- * - Call GPIO_Init() function
- * Recommended configuration is Push-Pull, Pull-up, Open-Drain.
- * Add an external pull up if necessary (typically 4.7 KOhm).
- *
- * 4. Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged
- * Address using the I2C_Init() function.
- *
- * 5. Optionally you can enable/configure the following parameters without
- * re-initialization (i.e there is no need to call again I2C_Init() function):
- * - Enable the acknowledge feature using I2C_AcknowledgeConfig() function
- * - Enable the dual addressing mode using I2C_DualAddressCmd() function
- * - Enable the general call using the I2C_GeneralCallCmd() function
- * - Enable the clock stretching using I2C_StretchClockCmd() function
- * - Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()
- * function.
- * - Configure the NACK position for Master Receiver mode in case of
- * 2 bytes reception using the function I2C_NACKPositionConfig().
- * - Enable the PEC Calculation using I2C_CalculatePEC() function
- * - For SMBus Mode:
- * - Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function
- * - Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function
- *
- * 6. Enable the NVIC and the corresponding interrupt using the function
- * I2C_ITConfig() if you need to use interrupt mode.
- *
- * 7. When using the DMA mode
- * - Configure the DMA using DMA_Init() function
- * - Active the needed channel Request using I2C_DMACmd() or
- * I2C_DMALastTransferCmd() function.
- * @note When using DMA mode, I2C interrupts may be used at the same time to
- * control the communication flow (Start/Stop/Ack... events and errors).
- *
- * 8. Enable the I2C using the I2C_Cmd() function.
- *
- * 9. Enable the DMA using the DMA_Cmd() function when using DMA mode in the
- * transfers.
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_i2c.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup I2C
- * @brief I2C driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*<! I2C registers Masks */
-#define FLAG_MASK ((uint32_t)0x00FFFFFF) /*<! I2C FLAG mask */
-#define ITEN_MASK ((uint32_t)0x07000000) /*<! I2C Interrupt Enable mask */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup I2C_Private_Functions
- * @{
- */
-
-/** @defgroup I2C_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- Initialization and Configuration functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitialize the I2Cx peripheral registers to their default reset values.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @retval None
- */
-void I2C_DeInit(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- if (I2Cx == I2C1)
- {
- /* Enable I2C1 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
- /* Release I2C1 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
- }
- else if (I2Cx == I2C2)
- {
- /* Enable I2C2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
- /* Release I2C2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
- }
- else
- {
- if (I2Cx == I2C3)
- {
- /* Enable I2C3 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C3, ENABLE);
- /* Release I2C3 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C3, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the I2Cx peripheral according to the specified
- * parameters in the I2C_InitStruct.
- *
- * @note To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency
- * (I2C peripheral input clock) must be a multiple of 10 MHz.
- *
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that contains
- * the configuration information for the specified I2C peripheral.
- * @retval None
- */
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
-{
- uint16_t tmpreg = 0, freqrange = 0;
- uint16_t result = 0x04;
- uint32_t pclk1 = 8000000;
- RCC_ClocksTypeDef rcc_clocks;
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
- assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
- assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
- assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
- assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
- assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
-
-/*---------------------------- I2Cx CR2 Configuration ------------------------*/
- /* Get the I2Cx CR2 value */
- tmpreg = I2Cx->CR2;
- /* Clear frequency FREQ[5:0] bits */
- tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ);
- /* Get pclk1 frequency value */
- RCC_GetClocksFreq(&rcc_clocks);
- pclk1 = rcc_clocks.PCLK1_Frequency;
- /* Set frequency bits depending on pclk1 value */
- freqrange = (uint16_t)(pclk1 / 1000000);
- tmpreg |= freqrange;
- /* Write to I2Cx CR2 */
- I2Cx->CR2 = tmpreg;
-
-/*---------------------------- I2Cx CCR Configuration ------------------------*/
- /* Disable the selected I2C peripheral to configure TRISE */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);
- /* Reset tmpreg value */
- /* Clear F/S, DUTY and CCR[11:0] bits */
- tmpreg = 0;
-
- /* Configure speed in standard mode */
- if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
- {
- /* Standard mode speed calculate */
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
- /* Test if CCR value is under 0x4*/
- if (result < 0x04)
- {
- /* Set minimum allowed value */
- result = 0x04;
- }
- /* Set speed value for standard mode */
- tmpreg |= result;
- /* Set Maximum Rise Time for standard mode */
- I2Cx->TRISE = freqrange + 1;
- }
- /* Configure speed in fast mode */
- /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral
- input clock) must be a multiple of 10 MHz */
- else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
- {
- if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
- {
- /* Fast mode speed calculate: Tlow/Thigh = 2 */
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
- }
- else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
- {
- /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
- /* Set DUTY bit */
- result |= I2C_DutyCycle_16_9;
- }
-
- /* Test if CCR value is under 0x1*/
- if ((result & I2C_CCR_CCR) == 0)
- {
- /* Set minimum allowed value */
- result |= (uint16_t)0x0001;
- }
- /* Set speed value and set F/S bit for fast mode */
- tmpreg |= (uint16_t)(result | I2C_CCR_FS);
- /* Set Maximum Rise Time for fast mode */
- I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
- }
-
- /* Write to I2Cx CCR */
- I2Cx->CCR = tmpreg;
- /* Enable the selected I2C peripheral */
- I2Cx->CR1 |= I2C_CR1_PE;
-
-/*---------------------------- I2Cx CR1 Configuration ------------------------*/
- /* Get the I2Cx CR1 value */
- tmpreg = I2Cx->CR1;
- /* Clear ACK, SMBTYPE and SMBUS bits */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure I2Cx: mode and acknowledgement */
- /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
- /* Set ACK bit according to I2C_Ack value */
- tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
- /* Write to I2Cx CR1 */
- I2Cx->CR1 = tmpreg;
-
-/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
- /* Set I2Cx Own Address1 and acknowledged address */
- I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
-}
-
-/**
- * @brief Fills each I2C_InitStruct member with its default value.
- * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
-{
-/*---------------- Reset I2C init structure parameters values ----------------*/
- /* initialize the I2C_ClockSpeed member */
- I2C_InitStruct->I2C_ClockSpeed = 5000;
- /* Initialize the I2C_Mode member */
- I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
- /* Initialize the I2C_DutyCycle member */
- I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
- /* Initialize the I2C_OwnAddress1 member */
- I2C_InitStruct->I2C_OwnAddress1 = 0;
- /* Initialize the I2C_Ack member */
- I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
- /* Initialize the I2C_AcknowledgedAddress member */
- I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
-}
-
-/**
- * @brief Enables or disables the specified I2C peripheral.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C peripheral */
- I2Cx->CR1 |= I2C_CR1_PE;
- }
- else
- {
- /* Disable the selected I2C peripheral */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);
- }
-}
-
-/**
- * @brief Generates I2Cx communication START condition.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C START condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Generate a START condition */
- I2Cx->CR1 |= I2C_CR1_START;
- }
- else
- {
- /* Disable the START condition generation */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START);
- }
-}
-
-/**
- * @brief Generates I2Cx communication STOP condition.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C STOP condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Generate a STOP condition */
- I2Cx->CR1 |= I2C_CR1_STOP;
- }
- else
- {
- /* Disable the STOP condition generation */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP);
- }
-}
-
-/**
- * @brief Transmits the address byte to select the slave device.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param Address: specifies the slave address which will be transmitted
- * @param I2C_Direction: specifies whether the I2C device will be a Transmitter
- * or a Receiver.
- * This parameter can be one of the following values
- * @arg I2C_Direction_Transmitter: Transmitter mode
- * @arg I2C_Direction_Receiver: Receiver mode
- * @retval None.
- */
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DIRECTION(I2C_Direction));
- /* Test on the direction to set/reset the read/write bit */
- if (I2C_Direction != I2C_Direction_Transmitter)
- {
- /* Set the address bit0 for read */
- Address |= I2C_OAR1_ADD0;
- }
- else
- {
- /* Reset the address bit0 for write */
- Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0);
- }
- /* Send the address */
- I2Cx->DR = Address;
-}
-
-/**
- * @brief Enables or disables the specified I2C acknowledge feature.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C Acknowledgement.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the acknowledgement */
- I2Cx->CR1 |= I2C_CR1_ACK;
- }
- else
- {
- /* Disable the acknowledgement */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK);
- }
-}
-
-/**
- * @brief Configures the specified I2C own address2.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param Address: specifies the 7bit I2C own address2.
- * @retval None.
- */
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
-{
- uint16_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Get the old register value */
- tmpreg = I2Cx->OAR2;
-
- /* Reset I2Cx Own address2 bit [7:1] */
- tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2);
-
- /* Set I2Cx Own address2 */
- tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
-
- /* Store the new register value */
- I2Cx->OAR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the specified I2C dual addressing mode.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C dual addressing mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable dual addressing mode */
- I2Cx->OAR2 |= I2C_OAR2_ENDUAL;
- }
- else
- {
- /* Disable dual addressing mode */
- I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL);
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C general call feature.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C General call.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable generall call */
- I2Cx->CR1 |= I2C_CR1_ENGC;
- }
- else
- {
- /* Disable generall call */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC);
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C software reset.
- * @note When software reset is enabled, the I2C IOs are released (this can
- * be useful to recover from bus errors).
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C software reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Peripheral under reset */
- I2Cx->CR1 |= I2C_CR1_SWRST;
- }
- else
- {
- /* Peripheral not under reset */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST);
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C Clock stretching.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx Clock stretching.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState == DISABLE)
- {
- /* Enable the selected I2C Clock stretching */
- I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
- }
- else
- {
- /* Disable the selected I2C Clock stretching */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH);
- }
-}
-
-/**
- * @brief Selects the specified I2C fast mode duty cycle.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_DutyCycle: specifies the fast mode duty cycle.
- * This parameter can be one of the following values:
- * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
- * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
- * @retval None
- */
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
- if (I2C_DutyCycle != I2C_DutyCycle_16_9)
- {
- /* I2C fast mode Tlow/Thigh=2 */
- I2Cx->CCR &= I2C_DutyCycle_2;
- }
- else
- {
- /* I2C fast mode Tlow/Thigh=16/9 */
- I2Cx->CCR |= I2C_DutyCycle_16_9;
- }
-}
-
-/**
- * @brief Selects the specified I2C NACK position in master receiver mode.
- * @note This function is useful in I2C Master Receiver mode when the number
- * of data to be received is equal to 2. In this case, this function
- * should be called (with parameter I2C_NACKPosition_Next) before data
- * reception starts,as described in the 2-byte reception procedure
- * recommended in Reference Manual in Section: Master receiver.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_NACKPosition: specifies the NACK position.
- * This parameter can be one of the following values:
- * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
- * received byte.
- * @arg I2C_NACKPosition_Current: indicates that current byte is the last
- * received byte.
- *
- * @note This function configures the same bit (POS) as I2C_PECPositionConfig()
- * but is intended to be used in I2C mode while I2C_PECPositionConfig()
- * is intended to used in SMBUS mode.
- *
- * @retval None
- */
-void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
-
- /* Check the input parameter */
- if (I2C_NACKPosition == I2C_NACKPosition_Next)
- {
- /* Next byte in shift register is the last received byte */
- I2Cx->CR1 |= I2C_NACKPosition_Next;
- }
- else
- {
- /* Current byte in shift register is the last received byte */
- I2Cx->CR1 &= I2C_NACKPosition_Current;
- }
-}
-
-/**
- * @brief Drives the SMBusAlert pin high or low for the specified I2C.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_SMBusAlert: specifies SMBAlert pin level.
- * This parameter can be one of the following values:
- * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
- * @arg I2C_SMBusAlert_High: SMBAlert pin driven high
- * @retval None
- */
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
- if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
- {
- /* Drive the SMBusAlert pin Low */
- I2Cx->CR1 |= I2C_SMBusAlert_Low;
- }
- else
- {
- /* Drive the SMBusAlert pin High */
- I2Cx->CR1 &= I2C_SMBusAlert_High;
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C ARP.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx ARP.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C ARP */
- I2Cx->CR1 |= I2C_CR1_ENARP;
- }
- else
- {
- /* Disable the selected I2C ARP */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP);
- }
-}
-/**
- * @}
- */
-
-/** @defgroup I2C_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- Data transfers functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sends a data byte through the I2Cx peripheral.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param Data: Byte to be transmitted..
- * @retval None
- */
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- /* Write in the DR register the data to be sent */
- I2Cx->DR = Data;
-}
-
-/**
- * @brief Returns the most recent received data by the I2Cx peripheral.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @retval The value of the received data.
- */
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- /* Return the data in the DR register */
- return (uint8_t)I2Cx->DR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Group3 PEC management functions
- * @brief PEC management functions
- *
-@verbatim
- ===============================================================================
- PEC management functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified I2C PEC transfer.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C PEC transmission.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C PEC transmission */
- I2Cx->CR1 |= I2C_CR1_PEC;
- }
- else
- {
- /* Disable the selected I2C PEC transmission */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC);
- }
-}
-
-/**
- * @brief Selects the specified I2C PEC position.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_PECPosition: specifies the PEC position.
- * This parameter can be one of the following values:
- * @arg I2C_PECPosition_Next: indicates that the next byte is PEC
- * @arg I2C_PECPosition_Current: indicates that current byte is PEC
- *
- * @note This function configures the same bit (POS) as I2C_NACKPositionConfig()
- * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig()
- * is intended to used in I2C mode.
- *
- * @retval None
- */
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
- if (I2C_PECPosition == I2C_PECPosition_Next)
- {
- /* Next byte in shift register is PEC */
- I2Cx->CR1 |= I2C_PECPosition_Next;
- }
- else
- {
- /* Current byte in shift register is PEC */
- I2Cx->CR1 &= I2C_PECPosition_Current;
- }
-}
-
-/**
- * @brief Enables or disables the PEC value calculation of the transferred bytes.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx PEC value calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C PEC calculation */
- I2Cx->CR1 |= I2C_CR1_ENPEC;
- }
- else
- {
- /* Disable the selected I2C PEC calculation */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC);
- }
-}
-
-/**
- * @brief Returns the PEC value for the specified I2C.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @retval The PEC value.
- */
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- /* Return the selected I2C PEC value */
- return ((I2Cx->SR2) >> 8);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Group4 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- DMA transfers management functions
- ===============================================================================
- This section provides functions allowing to configure the I2C DMA channels
- requests.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified I2C DMA requests.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C DMA transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C DMA requests */
- I2Cx->CR2 |= I2C_CR2_DMAEN;
- }
- else
- {
- /* Disable the selected I2C DMA requests */
- I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN);
- }
-}
-
-/**
- * @brief Specifies that the next DMA transfer is the last one.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C DMA last transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Next DMA transfer is the last transfer */
- I2Cx->CR2 |= I2C_CR2_LAST;
- }
- else
- {
- /* Next DMA transfer is not the last transfer */
- I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Group5 Interrupts events and flags management functions
- * @brief Interrupts, events and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts, events and flags management functions
- ===============================================================================
- This section provides functions allowing to configure the I2C Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode.
-
- ===============================================================================
- I2C State Monitoring Functions
- ===============================================================================
- This I2C driver provides three different ways for I2C state monitoring
- depending on the application requirements and constraints:
-
-
- 1. Basic state monitoring (Using I2C_CheckEvent() function)
- -----------------------------------------------------------
- It compares the status registers (SR1 and SR2) content to a given event
- (can be the combination of one or more flags).
- It returns SUCCESS if the current status includes the given flags
- and returns ERROR if one or more flags are missing in the current status.
-
- - When to use
- - This function is suitable for most applications as well as for startup
- activity since the events are fully described in the product reference
- manual (RM0090).
- - It is also suitable for users who need to define their own events.
-
- - Limitations
- - If an error occurs (ie. error flags are set besides to the monitored
- flags), the I2C_CheckEvent() function may return SUCCESS despite
- the communication hold or corrupted real state.
- In this case, it is advised to use error interrupts to monitor
- the error events and handle them in the interrupt IRQ handler.
-
- @note
- For error management, it is advised to use the following functions:
- - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
- Where x is the peripheral instance (I2C1, I2C2 ...)
- - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
- I2Cx_ER_IRQHandler() function in order to determine which error occurred.
- - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
- and/or I2C_GenerateStop() in order to clear the error flag and source
- and return to correct communication status.
-
-
- 2. Advanced state monitoring (Using the function I2C_GetLastEvent())
- --------------------------------------------------------------------
- Using the function I2C_GetLastEvent() which returns the image of both status
- registers in a single word (uint32_t) (Status Register 2 value is shifted left
- by 16 bits and concatenated to Status Register 1).
-
- - When to use
- - This function is suitable for the same applications above but it
- allows to overcome the mentioned limitation of I2C_GetFlagStatus()
- function.
- - The returned value could be compared to events already defined in
- the library (stm32f4xx_i2c.h) or to custom values defined by user.
- This function is suitable when multiple flags are monitored at the
- same time.
- - At the opposite of I2C_CheckEvent() function, this function allows
- user to choose when an event is accepted (when all events flags are
- set and no other flags are set or just when the needed flags are set
- like I2C_CheckEvent() function.
-
- - Limitations
- - User may need to define his own events.
- - Same remark concerning the error management is applicable for this
- function if user decides to check only regular communication flags
- (and ignores error flags).
-
-
- 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
- -----------------------------------------------------------------------
-
- Using the function I2C_GetFlagStatus() which simply returns the status of
- one single flag (ie. I2C_FLAG_RXNE ...).
-
- - When to use
- - This function could be used for specific applications or in debug
- phase.
- - It is suitable when only one flag checking is needed (most I2C
- events are monitored through multiple flags).
- - Limitations:
- - When calling this function, the Status register is accessed.
- Some flags are cleared when the status register is accessed.
- So checking the status of one Flag, may clear other ones.
- - Function may need to be called twice or more in order to monitor
- one single event.
-
- For detailed description of Events, please refer to section I2C_Events in
- stm32f4xx_i2c.h file.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads the specified I2C register and returns its value.
- * @param I2C_Register: specifies the register to read.
- * This parameter can be one of the following values:
- * @arg I2C_Register_CR1: CR1 register.
- * @arg I2C_Register_CR2: CR2 register.
- * @arg I2C_Register_OAR1: OAR1 register.
- * @arg I2C_Register_OAR2: OAR2 register.
- * @arg I2C_Register_DR: DR register.
- * @arg I2C_Register_SR1: SR1 register.
- * @arg I2C_Register_SR2: SR2 register.
- * @arg I2C_Register_CCR: CCR register.
- * @arg I2C_Register_TRISE: TRISE register.
- * @retval The value of the read register.
- */
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_REGISTER(I2C_Register));
-
- tmp = (uint32_t) I2Cx;
- tmp += I2C_Register;
-
- /* Return the selected register value */
- return (*(__IO uint16_t *) tmp);
-}
-
-/**
- * @brief Enables or disables the specified I2C interrupts.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg I2C_IT_BUF: Buffer interrupt mask
- * @arg I2C_IT_EVT: Event interrupt mask
- * @arg I2C_IT_ERR: Error interrupt mask
- * @param NewState: new state of the specified I2C interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_I2C_CONFIG_IT(I2C_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C interrupts */
- I2Cx->CR2 |= I2C_IT;
- }
- else
- {
- /* Disable the selected I2C interrupts */
- I2Cx->CR2 &= (uint16_t)~I2C_IT;
- }
-}
-
-/*
- ===============================================================================
- 1. Basic state monitoring
- ===============================================================================
- */
-
-/**
- * @brief Checks whether the last I2Cx Event is equal to the one passed
- * as parameter.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_EVENT: specifies the event to be checked.
- * This parameter can be one of the following values:
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2
- * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3
- * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2
- * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4
- * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5
- * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6
- * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6
- * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2
- * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9
- *
- * @note For detailed description of Events, please refer to section I2C_Events
- * in stm32f4xx_i2c.h file.
- *
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Last event is equal to the I2C_EVENT
- * - ERROR: Last event is different from the I2C_EVENT
- */
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
-{
- uint32_t lastevent = 0;
- uint32_t flag1 = 0, flag2 = 0;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_EVENT(I2C_EVENT));
-
- /* Read the I2Cx status register */
- flag1 = I2Cx->SR1;
- flag2 = I2Cx->SR2;
- flag2 = flag2 << 16;
-
- /* Get the last event value from I2C status register */
- lastevent = (flag1 | flag2) & FLAG_MASK;
-
- /* Check whether the last event contains the I2C_EVENT */
- if ((lastevent & I2C_EVENT) == I2C_EVENT)
- {
- /* SUCCESS: last event is equal to I2C_EVENT */
- status = SUCCESS;
- }
- else
- {
- /* ERROR: last event is different from I2C_EVENT */
- status = ERROR;
- }
- /* Return status */
- return status;
-}
-
-/*
- ===============================================================================
- 2. Advanced state monitoring
- ===============================================================================
- */
-
-/**
- * @brief Returns the last I2Cx Event.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- *
- * @note For detailed description of Events, please refer to section I2C_Events
- * in stm32f4xx_i2c.h file.
- *
- * @retval The last event
- */
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
-{
- uint32_t lastevent = 0;
- uint32_t flag1 = 0, flag2 = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Read the I2Cx status register */
- flag1 = I2Cx->SR1;
- flag2 = I2Cx->SR2;
- flag2 = flag2 << 16;
-
- /* Get the last event value from I2C status register */
- lastevent = (flag1 | flag2) & FLAG_MASK;
-
- /* Return status */
- return lastevent;
-}
-
-/*
- ===============================================================================
- 3. Flag-based state monitoring
- ===============================================================================
- */
-
-/**
- * @brief Checks whether the specified I2C flag is set or not.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
- * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
- * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
- * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
- * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
- * @arg I2C_FLAG_BUSY: Bus busy flag
- * @arg I2C_FLAG_MSL: Master/Slave flag
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_FLAG_PECERR: PEC error in reception flag
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_FLAG_AF: Acknowledge failure flag
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_FLAG_BERR: Bus error flag
- * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
- * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
- * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
- * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
- * @arg I2C_FLAG_BTF: Byte transfer finished flag
- * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
- * Address matched flag (Slave mode)"ENDAD"
- * @arg I2C_FLAG_SB: Start bit flag (Master mode)
- * @retval The new state of I2C_FLAG (SET or RESET).
- */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
- FlagStatus bitstatus = RESET;
- __IO uint32_t i2creg = 0, i2cxbase = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
-
- /* Get the I2Cx peripheral base address */
- i2cxbase = (uint32_t)I2Cx;
-
- /* Read flag register index */
- i2creg = I2C_FLAG >> 28;
-
- /* Get bit[23:0] of the flag */
- I2C_FLAG &= FLAG_MASK;
-
- if(i2creg != 0)
- {
- /* Get the I2Cx SR1 register address */
- i2cxbase += 0x14;
- }
- else
- {
- /* Flag in I2Cx SR2 Register */
- I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
- /* Get the I2Cx SR2 register address */
- i2cxbase += 0x18;
- }
-
- if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
- {
- /* I2C_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the I2C_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the I2Cx's pending flags.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_FLAG_PECERR: PEC error in reception flag
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_FLAG_AF: Acknowledge failure flag
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_FLAG_BERR: Bus error flag
- *
- * @note STOPF (STOP detection) is cleared by software sequence: a read operation
- * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation
- * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
- * @note ADD10 (10-bit header sent) is cleared by software sequence: a read
- * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the
- * second byte of the address in DR register.
- * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read
- * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a
- * read/write to I2C_DR register (I2C_SendData()).
- * @note ADDR (Address sent) is cleared by software sequence: a read operation to
- * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to
- * I2C_SR2 register ((void)(I2Cx->SR2)).
- * @note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
- * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
- * register (I2C_SendData()).
- *
- * @retval None
- */
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
- uint32_t flagpos = 0;
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
- /* Get the I2C flag position */
- flagpos = I2C_FLAG & FLAG_MASK;
- /* Clear the selected I2C flag */
- I2Cx->SR1 = (uint16_t)~flagpos;
-}
-
-/**
- * @brief Checks whether the specified I2C interrupt has occurred or not.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_IT: specifies the interrupt source to check.
- * This parameter can be one of the following values:
- * @arg I2C_IT_SMBALERT: SMBus Alert flag
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_IT_PECERR: PEC error in reception flag
- * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_IT_AF: Acknowledge failure flag
- * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_IT_BERR: Bus error flag
- * @arg I2C_IT_TXE: Data register empty flag (Transmitter)
- * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
- * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
- * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
- * @arg I2C_IT_BTF: Byte transfer finished flag
- * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"
- * Address matched flag (Slave mode)"ENDAD"
- * @arg I2C_IT_SB: Start bit flag (Master mode)
- * @retval The new state of I2C_IT (SET or RESET).
- */
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_IT(I2C_IT));
-
- /* Check if the interrupt source is enabled or not */
- enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ;
-
- /* Get bit[23:0] of the flag */
- I2C_IT &= FLAG_MASK;
-
- /* Check the status of the specified I2C flag */
- if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
- {
- /* I2C_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_IT is reset */
- bitstatus = RESET;
- }
- /* Return the I2C_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the I2Cx's interrupt pending bits.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_IT_SMBALERT: SMBus Alert interrupt
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
- * @arg I2C_IT_PECERR: PEC error in reception interrupt
- * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
- * @arg I2C_IT_AF: Acknowledge failure interrupt
- * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
- * @arg I2C_IT_BERR: Bus error interrupt
- *
- * @note STOPF (STOP detection) is cleared by software sequence: a read operation
- * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
- * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
- * @note ADD10 (10-bit header sent) is cleared by software sequence: a read
- * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second
- * byte of the address in I2C_DR register.
- * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read
- * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a
- * read/write to I2C_DR register (I2C_SendData()).
- * @note ADDR (Address sent) is cleared by software sequence: a read operation to
- * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to
- * I2C_SR2 register ((void)(I2Cx->SR2)).
- * @note SB (Start Bit) is cleared by software sequence: a read operation to
- * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
- * I2C_DR register (I2C_SendData()).
- * @retval None
- */
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
- uint32_t flagpos = 0;
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_IT(I2C_IT));
-
- /* Get the I2C flag position */
- flagpos = I2C_IT & FLAG_MASK;
-
- /* Clear the selected I2C flag */
- I2Cx->SR1 = (uint16_t)~flagpos;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_iwdg.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Independent watchdog (IWDG) peripheral:
- * - Prescaler and Counter configuration
- * - IWDG activation
- * - Flag management
- *
- * @verbatim
- *
- * ===================================================================
- * IWDG features
- * ===================================================================
- *
- * The IWDG can be started by either software or hardware (configurable
- * through option byte).
- *
- * The IWDG is clocked by its own dedicated low-speed clock (LSI) and
- * thus stays active even if the main clock fails.
- * Once the IWDG is started, the LSI is forced ON and cannot be disabled
- * (LSI cannot be disabled too), and the counter starts counting down from
- * the reset value of 0xFFF. When it reaches the end of count value (0x000)
- * a system reset is generated.
- * The IWDG counter should be reloaded at regular intervals to prevent
- * an MCU reset.
- *
- * The IWDG is implemented in the VDD voltage domain that is still functional
- * in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
- *
- * IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
- * reset occurs.
- *
- * Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
- * The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
- * devices provide the capability to measure the LSI frequency (LSI clock
- * connected internally to TIM5 CH4 input capture). The measured value
- * can be used to have an IWDG timeout with an acceptable accuracy.
- * For more information, please refer to the STM32F4xx Reference manual
- *
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * 1. Enable write access to IWDG_PR and IWDG_RLR registers using
- * IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function
- *
- * 2. Configure the IWDG prescaler using IWDG_SetPrescaler() function
- *
- * 3. Configure the IWDG counter value using IWDG_SetReload() function.
- * This value will be loaded in the IWDG counter each time the counter
- * is reloaded, then the IWDG will start counting down from this value.
- *
- * 4. Start the IWDG using IWDG_Enable() function, when the IWDG is used
- * in software mode (no need to enable the LSI, it will be enabled
- * by hardware)
- *
- * 5. Then the application program must reload the IWDG counter at regular
- * intervals during normal operation to prevent an MCU reset, using
- * IWDG_ReloadCounter() function.
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_iwdg.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup IWDG
- * @brief IWDG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* KR register bit mask */
-#define KR_KEY_RELOAD ((uint16_t)0xAAAA)
-#define KR_KEY_ENABLE ((uint16_t)0xCCCC)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup IWDG_Private_Functions
- * @{
- */
-
-/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
- * @brief Prescaler and Counter configuration functions
- *
-@verbatim
- ===============================================================================
- Prescaler and Counter configuration functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
- * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
- * This parameter can be one of the following values:
- * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
- * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
- * @retval None
- */
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
- IWDG->KR = IWDG_WriteAccess;
-}
-
-/**
- * @brief Sets IWDG Prescaler value.
- * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
- * This parameter can be one of the following values:
- * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
- * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
- * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
- * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
- * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
- * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
- * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
- * @retval None
- */
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
- IWDG->PR = IWDG_Prescaler;
-}
-
-/**
- * @brief Sets IWDG Reload value.
- * @param Reload: specifies the IWDG Reload value.
- * This parameter must be a number between 0 and 0x0FFF.
- * @retval None
- */
-void IWDG_SetReload(uint16_t Reload)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_RELOAD(Reload));
- IWDG->RLR = Reload;
-}
-
-/**
- * @brief Reloads IWDG counter with value defined in the reload register
- * (write access to IWDG_PR and IWDG_RLR registers disabled).
- * @param None
- * @retval None
- */
-void IWDG_ReloadCounter(void)
-{
- IWDG->KR = KR_KEY_RELOAD;
-}
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Group2 IWDG activation function
- * @brief IWDG activation function
- *
-@verbatim
- ===============================================================================
- IWDG activation function
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
- * @param None
- * @retval None
- */
-void IWDG_Enable(void)
-{
- IWDG->KR = KR_KEY_ENABLE;
-}
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Group3 Flag management function
- * @brief Flag management function
- *
-@verbatim
- ===============================================================================
- Flag management function
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified IWDG flag is set or not.
- * @param IWDG_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
- * @arg IWDG_FLAG_RVU: Reload Value Update on going
- * @retval The new state of IWDG_FLAG (SET or RESET).
- */
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_IWDG_FLAG(IWDG_FLAG));
- if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_pwr.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Power Controller (PWR) peripheral:
- * - Backup Domain Access
- * - PVD configuration
- * - WakeUp pin configuration
- * - Backup Regulator configuration
- * - Performance Mode and FLASH Power Down configuration functions
- * - Low Power modes configuration
- * - Flags management
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_pwr.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup PWR
- * @brief PWR driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* --------- PWR registers bit address in the alias region ---------- */
-#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
-
-/* --- CR Register ---*/
-
-/* Alias word address of DBP bit */
-#define CR_OFFSET (PWR_OFFSET + 0x00)
-#define DBP_BitNumber 0x08
-#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
-
-/* Alias word address of PVDE bit */
-#define PVDE_BitNumber 0x04
-#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
-
-/* Alias word address of FPDS bit */
-#define FPDS_BitNumber 0x09
-#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
-
-/* Alias word address of PMODE bit */
-#define PMODE_BitNumber 0x0E
-#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
-
-
-/* --- CSR Register ---*/
-
-/* Alias word address of EWUP bit */
-#define CSR_OFFSET (PWR_OFFSET + 0x04)
-#define EWUP_BitNumber 0x08
-#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
-
-/* Alias word address of BRE bit */
-#define BRE_BitNumber 0x09
-#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
-
-/* ------------------ PWR registers bit mask ------------------------ */
-
-/* CR register bit mask */
-#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
-#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PWR_Private_Functions
- * @{
- */
-
-/** @defgroup PWR_Group1 Backup Domain Access function
- * @brief Backup Domain Access function
- *
-@verbatim
- ===============================================================================
- Backup Domain Access function
- ===============================================================================
-
- After reset, the backup domain (RTC registers, RTC backup data
- registers and backup SRAM) is protected against possible unwanted
- write accesses.
- To enable access to the RTC Domain and RTC registers, proceed as follows:
- - Enable the Power Controller (PWR) APB1 interface clock using the
- RCC_APB1PeriphClockCmd() function.
- - Enable access to RTC domain using the PWR_BackupAccessCmd() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the PWR peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void PWR_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
-}
-
-/**
- * @brief Enables or disables access to the backup domain (RTC registers, RTC
- * backup data registers and backup SRAM).
- * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
- * Backup Domain Access should be kept enabled.
- * @param NewState: new state of the access to the backup domain.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_BackupAccessCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group2 PVD configuration functions
- * @brief PVD configuration functions
- *
-@verbatim
- ===============================================================================
- PVD configuration functions
- ===============================================================================
-
- - The PVD is used to monitor the VDD power supply by comparing it to a threshold
- selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
- - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the
- PVD threshold. This event is internally connected to the EXTI line16
- and can generate an interrupt if enabled through the EXTI registers.
- - The PVD is stopped in Standby mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
- * @param PWR_PVDLevel: specifies the PVD detection level
- * This parameter can be one of the following values:
- * @arg PWR_PVDLevel_0: PVD detection level set to 2.0V
- * @arg PWR_PVDLevel_1: PVD detection level set to 2.2V
- * @arg PWR_PVDLevel_2: PVD detection level set to 2.3V
- * @arg PWR_PVDLevel_3: PVD detection level set to 2.5V
- * @arg PWR_PVDLevel_4: PVD detection level set to 2.7V
- * @arg PWR_PVDLevel_5: PVD detection level set to 2.8V
- * @arg PWR_PVDLevel_6: PVD detection level set to 2.9V
- * @arg PWR_PVDLevel_7: PVD detection level set to 3.0V
- * @note Refer to the electrical characteristics of you device datasheet for more details.
- * @retval None
- */
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
-
- tmpreg = PWR->CR;
-
- /* Clear PLS[7:5] bits */
- tmpreg &= CR_PLS_MASK;
-
- /* Set PLS[7:5] bits according to PWR_PVDLevel value */
- tmpreg |= PWR_PVDLevel;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Power Voltage Detector(PVD).
- * @param NewState: new state of the PVD.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_PVDCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group3 WakeUp pin configuration functions
- * @brief WakeUp pin configuration functions
- *
-@verbatim
- ===============================================================================
- WakeUp pin configuration functions
- ===============================================================================
-
- - WakeUp pin is used to wakeup the system from Standby mode. This pin is
- forced in input pull down configuration and is active on rising edges.
- - There is only one WakeUp pin: WakeUp Pin 1 on PA.00.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the WakeUp Pin functionality.
- * @param NewState: new state of the WakeUp Pin functionality.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_WakeUpPinCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group4 Backup Regulator configuration functions
- * @brief Backup Regulator configuration functions
- *
-@verbatim
- ===============================================================================
- Backup Regulator configuration functions
- ===============================================================================
-
- - The backup domain includes 4 Kbytes of backup SRAM accessible only from the
- CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained
- even in Standby or VBAT mode when the low power backup regulator is enabled.
- It can be considered as an internal EEPROM when VBAT is always present.
- You can use the PWR_BackupRegulatorCmd() function to enable the low power
- backup regulator and use the PWR_GetFlagStatus(PWR_FLAG_BRR) to check if it is
- ready or not.
-
- - When the backup domain is supplied by VDD (analog switch connected to VDD)
- the backup SRAM is powered from VDD which replaces the VBAT power supply to
- save battery life.
-
- - The backup SRAM is not mass erased by an tamper event. It is read protected
- to prevent confidential data, such as cryptographic private key, from being
- accessed. The backup SRAM can be erased only through the Flash interface when
- a protection level change from level 1 to level 0 is requested.
- Refer to the description of Read protection (RDP) in the Flash programming manual.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the Backup Regulator.
- * @param NewState: new state of the Backup Regulator.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_BackupRegulatorCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group5 Performance Mode and FLASH Power Down configuration functions
- * @brief Performance Mode and FLASH Power Down configuration functions
- *
-@verbatim
- ===============================================================================
- Performance Mode and FLASH Power Down configuration functions
- ===============================================================================
-
- - By setting the PMODE bit in the PWR_CR register by using the PWR_HighPerformanceModeCmd()
- function, the high performance mode is selected and the high voltage regulator
- minimum value should be around 1.2V.
- When reset, the low performance mode is selected and the low voltage regulator
- minimum value should be around 1.08V.
-
- - By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd()
- function, the Flash memory also enters power down mode when the device enters
- Stop mode. When the Flash memory is in power down mode, an additional startup
- delay is incurred when waking up from Stop mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the high performance mode.
- * @param NewState: new state of the performance mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_HighPerformanceModeCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_PMODE_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the Flash Power Down in STOP mode.
- * @param NewState: new state of the Flash power mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_FlashPowerDownCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group6 Low Power modes configuration functions
- * @brief Low Power modes configuration functions
- *
-@verbatim
- ===============================================================================
- Low Power modes configuration functions
- ===============================================================================
-
- The devices feature 3 low-power modes:
- - Sleep mode: Cortex-M4 core stopped, peripherals kept running.
- - Stop mode: all clocks are stopped, regulator running, regulator in low power mode
- - Standby mode: 1.2V domain powered off.
-
- Sleep mode
- ===========
- - Entry:
- - The Sleep mode is entered by using the __WFI() or __WFE() functions.
- - Exit:
- - Any peripheral interrupt acknowledged by the nested vectored interrupt
- controller (NVIC) can wake up the device from Sleep mode.
-
- Stop mode
- ==========
- In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
- and the HSE RC oscillators are disabled. Internal SRAM and register contents
- are preserved.
- The voltage regulator can be configured either in normal or low-power mode.
- To minimize the consumption In Stop mode, FLASH can be powered off before
- entering the Stop mode. It can be switched on again by software after exiting
- the Stop mode using the PWR_FlashPowerDownCmd() function.
-
- - Entry:
- - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
- function with regulator in LowPower or with Regulator ON.
- - Exit:
- - Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
-
- Standby mode
- ============
- The Standby mode allows to achieve the lowest power consumption. It is based
- on the Cortex-M4 deepsleep mode, with the voltage regulator disabled.
- The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
- the HSE oscillator are also switched off. SRAM and register contents are lost
- except for the RTC registers, RTC backup registers, backup SRAM and Standby
- circuitry.
-
- The voltage regulator is OFF.
-
- - Entry:
- - The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
- - Exit:
- - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
- tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
-
- Auto-wakeup (AWU) from low-power mode
- =====================================
- The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
- Wakeup event, a tamper event, a time-stamp event, or a comparator event,
- without depending on an external interrupt (Auto-wakeup mode).
-
- - RTC auto-wakeup (AWU) from the Stop mode
- ----------------------------------------
-
- - To wake up from the Stop mode with an RTC alarm event, it is necessary to:
- - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
- or Event modes) using the EXTI_Init() function.
- - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
- - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
- and RTC_AlarmCmd() functions.
- - To wake up from the Stop mode with an RTC Tamper or time stamp event, it
- is necessary to:
- - Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt
- or Event modes) using the EXTI_Init() function.
- - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
- function
- - Configure the RTC to detect the tamper or time stamp event using the
- RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
- functions.
- - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
- - Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt
- or Event modes) using the EXTI_Init() function.
- - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
- - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
- RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
-
- - RTC auto-wakeup (AWU) from the Standby mode
- -------------------------------------------
- - To wake up from the Standby mode with an RTC alarm event, it is necessary to:
- - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
- - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
- and RTC_AlarmCmd() functions.
- - To wake up from the Standby mode with an RTC Tamper or time stamp event, it
- is necessary to:
- - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
- function
- - Configure the RTC to detect the tamper or time stamp event using the
- RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
- functions.
- - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
- - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
- - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
- RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enters STOP mode.
- *
- * @note In Stop mode, all I/O pins keep the same state as in Run mode.
- * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
- * the HSI RC oscillator is selected as system clock.
- * @note When the voltage regulator operates in low power mode, an additional
- * startup delay is incurred when waking up from Stop mode.
- * By keeping the internal regulator ON during Stop mode, the consumption
- * is higher although the startup time is reduced.
- *
- * @param PWR_Regulator: specifies the regulator state in STOP mode.
- * This parameter can be one of the following values:
- * @arg PWR_Regulator_ON: STOP mode with regulator ON
- * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
- * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
- * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
- * @retval None
- */
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(PWR_Regulator));
- assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
-
- /* Select the regulator state in STOP mode ---------------------------------*/
- tmpreg = PWR->CR;
- /* Clear PDDS and LPDSR bits */
- tmpreg &= CR_DS_MASK;
-
- /* Set LPDSR bit according to PWR_Regulator value */
- tmpreg |= PWR_Regulator;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* Select STOP mode entry --------------------------------------------------*/
- if(PWR_STOPEntry == PWR_STOPEntry_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __WFE();
- }
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-}
-
-/**
- * @brief Enters STANDBY mode.
- * @note In Standby mode, all I/O pins are high impedance except for:
- * - Reset pad (still available)
- * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
- * Alarm out, or RTC clock calibration out.
- * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
- * - WKUP pin 1 (PA0) if enabled.
- * @param None
- * @retval None
- */
-void PWR_EnterSTANDBYMode(void)
-{
- /* Clear Wakeup flag */
- PWR->CR |= PWR_CR_CWUF;
-
- /* Select STANDBY mode */
- PWR->CR |= PWR_CR_PDDS;
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
-/* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM )
- __force_stores();
-#endif
- /* Request Wait For Interrupt */
- __WFI();
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group7 Flags management functions
- * @brief Flags management functions
- *
-@verbatim
- ===============================================================================
- Flags management functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified PWR flag is set or not.
- * @param PWR_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
- * was received from the WKUP pin or from the RTC alarm (Alarm A
- * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
- * An additional wakeup event is detected if the WKUP pin is enabled
- * (by setting the EWUP bit) when the WKUP pin level is already high.
- * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
- * resumed from StandBy mode.
- * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
- * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode
- * For this reason, this bit is equal to 0 after Standby or reset
- * until the PVDE bit is set.
- * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
- * when the device wakes up from Standby mode or by a system reset
- * or power reset.
- * @arg PWR_FLAG_REGRDY: Main regulator ready flag.
- * @retval The new state of PWR_FLAG (SET or RESET).
- */
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
-
- if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the PWR's pending flags.
- * @param PWR_FLAG: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag
- * @arg PWR_FLAG_SB: StandBy flag
- * @retval None
- */
-void PWR_ClearFlag(uint32_t PWR_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
-
- PWR->CR |= PWR_FLAG << 2;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_rcc.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Reset and clock control (RCC) peripheral:
- * - Internal/external clocks, PLL, CSS and MCO configuration
- * - System, AHB and APB busses clocks configuration
- * - Peripheral clocks configuration
- * - Interrupts and flags management
- *
- * @verbatim
- *
- * ===================================================================
- * RCC specific features
- * ===================================================================
- *
- * After reset the device is running from Internal High Speed oscillator
- * (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
- * and I-Cache are disabled, and all peripherals are off except internal
- * SRAM, Flash and JTAG.
- * - There is no prescaler on High speed (AHB) and Low speed (APB) busses;
- * all peripherals mapped on these busses are running at HSI speed.
- * - The clock for all peripherals is switched off, except the SRAM and FLASH.
- * - All GPIOs are in input floating state, except the JTAG pins which
- * are assigned to be used for debug purpose.
- *
- * Once the device started from reset, the user application has to:
- * - Configure the clock source to be used to drive the System clock
- * (if the application needs higher frequency/performance)
- * - Configure the System clock frequency and Flash settings
- * - Configure the AHB and APB busses prescalers
- * - Enable the clock for the peripheral(s) to be used
- * - Configure the clock source(s) for peripherals which clocks are not
- * derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RCC
- * @brief RCC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ------------ RCC registers bit address in the alias region ----------- */
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-/* --- CR Register ---*/
-/* Alias word address of HSION bit */
-#define CR_OFFSET (RCC_OFFSET + 0x00)
-#define HSION_BitNumber 0x00
-#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
-/* Alias word address of CSSON bit */
-#define CSSON_BitNumber 0x13
-#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
-/* Alias word address of PLLON bit */
-#define PLLON_BitNumber 0x18
-#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
-/* Alias word address of PLLI2SON bit */
-#define PLLI2SON_BitNumber 0x1A
-#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
-
-/* --- CFGR Register ---*/
-/* Alias word address of I2SSRC bit */
-#define CFGR_OFFSET (RCC_OFFSET + 0x08)
-#define I2SSRC_BitNumber 0x17
-#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
-
-/* --- BDCR Register ---*/
-/* Alias word address of RTCEN bit */
-#define BDCR_OFFSET (RCC_OFFSET + 0x70)
-#define RTCEN_BitNumber 0x0F
-#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
-/* Alias word address of BDRST bit */
-#define BDRST_BitNumber 0x10
-#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
-/* --- CSR Register ---*/
-/* Alias word address of LSION bit */
-#define CSR_OFFSET (RCC_OFFSET + 0x74)
-#define LSION_BitNumber 0x00
-#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
-/* ---------------------- RCC registers bit mask ------------------------ */
-/* CFGR register bit mask */
-#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF)
-#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF)
-
-/* RCC Flag Mask */
-#define FLAG_MASK ((uint8_t)0x1F)
-
-/* CR register byte 3 (Bits[23:16]) base address */
-#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
-
-/* CIR register byte 2 (Bits[15:8]) base address */
-#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
-
-/* CIR register byte 3 (Bits[23:16]) base address */
-#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
-
-/* BDCR register base address */
-#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCC_Private_Functions
- * @{
- */
-
-/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
- * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
- *
-@verbatim
- ===============================================================================
- Internal/external clocks, PLL, CSS and MCO configuration functions
- ===============================================================================
-
- This section provide functions allowing to configure the internal/external clocks,
- PLLs, CSS and MCO pins.
-
- 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
- the PLL as System clock source.
-
- 2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
- clock source.
-
- 3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
- through the PLL as System clock source. Can be used also as RTC clock source.
-
- 4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
-
- 5. PLL (clocked by HSI or HSE), featuring two different output clocks:
- - The first output is used to generate the high speed system clock (up to 120 MHz)
- - The second output is used to generate the clock for the USB OTG FS (48 MHz),
- the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
-
- 6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve
- high-quality audio performance on the I2S interface.
-
- 7. CSS (Clock security system), once enable and if a HSE clock failure occurs
- (HSE used directly or through PLL as System clock source), the System clock
- is automatically switched to HSI and an interrupt is generated if enabled.
- The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
- exception vector.
-
- 8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
- clock (through a configurable prescaler) on PA8 pin.
-
- 9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
- clock (through a configurable prescaler) on PC9 pin.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Resets the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * - HSI ON and used as system clock source
- * - HSE, PLL and PLLI2S OFF
- * - AHB, APB1 and APB2 prescaler set to 1.
- * - CSS, MCO1 and MCO2 OFF
- * - All interrupts disabled
- * @note This function doesn't modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
- * @param None
- * @retval None
- */
-void RCC_DeInit(void)
-{
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-}
-
-/**
- * @brief Configures the External High Speed oscillator (HSE).
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
- * software should wait on HSERDY flag to be set indicating that HSE clock
- * is stable and can be used to clock the PLL and/or system clock.
- * @note HSE state can not be changed if it is used directly or through the
- * PLL as system clock. In this case, you have to select another source
- * of the system clock then change the HSE state (ex. disable it).
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
- * @note This function reset the CSSON bit, so if the Clock security system(CSS)
- * was previously enabled you have to enable it again after calling this
- * function.
- * @param RCC_HSE: specifies the new state of the HSE.
- * This parameter can be one of the following values:
- * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
- * 6 HSE oscillator clock cycles.
- * @arg RCC_HSE_ON: turn ON the HSE oscillator
- * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_HSEConfig(uint8_t RCC_HSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_HSE));
-
- /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
- *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
-
- /* Set the new HSE configuration -------------------------------------------*/
- *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
-}
-
-/**
- * @brief Waits for HSE start-up.
- * @note This functions waits on HSERDY flag to be set and return SUCCESS if
- * this flag is set, otherwise returns ERROR if the timeout is reached
- * and this flag is not set. The timeout value is defined by the constant
- * HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending
- * on the HSE crystal used in your application.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: HSE oscillator is stable and ready to use
- * - ERROR: HSE oscillator not yet ready
- */
-ErrorStatus RCC_WaitForHSEStartUp(void)
-{
- __IO uint32_t startupcounter = 0;
- ErrorStatus status = ERROR;
- FlagStatus hsestatus = RESET;
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
- startupcounter++;
- } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
-
- if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
- return (status);
-}
-
-/**
- * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * @param HSICalibrationValue: specifies the calibration trimming value.
- * This parameter must be a number between 0 and 0x1F.
- * @retval None
- */
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
-
- tmpreg = RCC->CR;
-
- /* Clear HSITRIM[4:0] bits */
- tmpreg &= ~RCC_CR_HSITRIM;
-
- /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
- tmpreg |= (uint32_t)HSICalibrationValue << 3;
-
- /* Store the new value */
- RCC->CR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Internal High Speed oscillator (HSI).
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * It is used (enabled by hardware) as system clock source after startup
- * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
- * of the HSE used directly or indirectly as system clock (if the Clock
- * Security System CSS is enabled).
- * @note HSI can not be stopped if it is used as system clock source. In this case,
- * you have to select another source of the system clock then stop the HSI.
- * @note After enabling the HSI, the application software should wait on HSIRDY
- * flag to be set indicating that HSI clock is stable and can be used as
- * system clock source.
- * @param NewState: new state of the HSI.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- * @retval None
- */
-void RCC_HSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the External Low Speed oscillator (LSE).
- * @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
- * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
- * (to be done once after reset).
- * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
- * software should wait on LSERDY flag to be set indicating that LSE clock
- * is stable and can be used to clock the RTC.
- * @param RCC_LSE: specifies the new state of the LSE.
- * This parameter can be one of the following values:
- * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
- * 6 LSE oscillator clock cycles.
- * @arg RCC_LSE_ON: turn ON the LSE oscillator
- * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_LSEConfig(uint8_t RCC_LSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_LSE));
-
- /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
- /* Reset LSEON bit */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
-
- /* Reset LSEBYP bit */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
-
- /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
- switch (RCC_LSE)
- {
- case RCC_LSE_ON:
- /* Set LSEON bit */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
- break;
- case RCC_LSE_Bypass:
- /* Set LSEBYP and LSEON bits */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Enables or disables the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
- * LSIRDY flag to be set indicating that LSI clock is stable and can
- * be used to clock the IWDG and/or the RTC.
- * @note LSI can not be disabled if the IWDG is running.
- * @param NewState: new state of the LSI.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
- * @retval None
- */
-void RCC_LSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the main PLL clock source, multiplication and division factors.
- * @note This function must be used only when the main PLL is disabled.
- *
- * @param RCC_PLLSource: specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
- * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
- * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
- *
- * @param PLLM: specifies the division factor for PLL VCO input clock
- * This parameter must be a number between 0 and 63.
- * @note You have to set the PLLM parameter correctly to ensure that the VCO input
- * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
- * of 2 MHz to limit PLL jitter.
- *
- * @param PLLN: specifies the multiplication factor for PLL VCO output clock
- * This parameter must be a number between 192 and 432.
- * @note You have to set the PLLN parameter correctly to ensure that the VCO
- * output frequency is between 192 and 432 MHz.
- *
- * @param PLLP: specifies the division factor for main system clock (SYSCLK)
- * This parameter must be a number in the range {2, 4, 6, or 8}.
- * @note You have to set the PLLP parameter correctly to not exceed 120 MHz on
- * the System clock frequency.
- *
- * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
- * This parameter must be a number between 4 and 15.
- * @note If the USB OTG FS is used in your application, you have to set the
- * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
- * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
- * correctly.
- *
- * @retval None
- */
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
- assert_param(IS_RCC_PLLM_VALUE(PLLM));
- assert_param(IS_RCC_PLLN_VALUE(PLLN));
- assert_param(IS_RCC_PLLP_VALUE(PLLP));
- assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
-
- RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
- (PLLQ << 24);
-}
-
-/**
- * @brief Enables or disables the main PLL.
- * @note After enabling the main PLL, the application software should wait on
- * PLLRDY flag to be set indicating that PLL clock is stable and can
- * be used as system clock source.
- * @note The main PLL can not be disabled if it is used as system clock source
- * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLLCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the PLLI2S clock multiplication and division factors.
- *
- * @note PLLI2S is available only in Silicon RevisionB and RevisionY.
- * @note This function must be used only when the PLLI2S is disabled.
- * @note PLLI2S clock source is common with the main PLL (configured in
- * RCC_PLLConfig function )
- *
- * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
- * This parameter must be a number between 192 and 432.
- * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
- * output frequency is between 192 and 432 MHz.
- *
- * @param PLLI2SR: specifies the division factor for I2S clock
- * This parameter must be a number between 2 and 7.
- * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
- * on the I2S clock frequency.
- *
- * @retval None
- */
-void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
- assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
-
- RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
-}
-
-/**
- * @brief Enables or disables the PLLI2S.
- * @note PLLI2S is available only in RevisionB and RevisionY
- * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLLI2SCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the Clock Security System.
- * @note If a failure is detected on the HSE oscillator clock, this oscillator
- * is automatically disabled and an interrupt is generated to inform the
- * software about the failure (Clock Security System Interrupt, CSSI),
- * allowing the MCU to perform rescue operations. The CSSI is linked to
- * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
- * @param NewState: new state of the Clock Security System.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Selects the clock source to output on MCO1 pin(PA8).
- * @note PA8 should be configured in alternate function mode.
- * @param RCC_MCO1Source: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
- * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
- * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
- * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source
- * @param RCC_MCO1Div: specifies the MCO1 prescaler.
- * This parameter can be one of the following values:
- * @arg RCC_MCO1Div_1: no division applied to MCO1 clock
- * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock
- * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock
- * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock
- * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock
- * @retval None
- */
-void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source));
- assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));
-
- tmpreg = RCC->CFGR;
-
- /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
- tmpreg &= CFGR_MCO1_RESET_MASK;
-
- /* Select MCO1 clock source and prescaler */
- tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Selects the clock source to output on MCO2 pin(PC9).
- * @note PC9 should be configured in alternate function mode.
- * @param RCC_MCO2Source: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
- * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source
- * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
- * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
- * @param RCC_MCO2Div: specifies the MCO2 prescaler.
- * This parameter can be one of the following values:
- * @arg RCC_MCO2Div_1: no division applied to MCO2 clock
- * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock
- * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock
- * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock
- * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock
- * @retval None
- */
-void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source));
- assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
-
- tmpreg = RCC->CFGR;
-
- /* Clear MCO2 and MCO2PRE[2:0] bits */
- tmpreg &= CFGR_MCO2_RESET_MASK;
-
- /* Select MCO2 clock source and prescaler */
- tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
- * @brief System, AHB and APB busses clocks configuration functions
- *
-@verbatim
- ===============================================================================
- System, AHB and APB busses clocks configuration functions
- ===============================================================================
-
- This section provide functions allowing to configure the System, AHB, APB1 and
- APB2 busses clocks.
-
- 1. Several clock sources can be used to drive the System clock (SYSCLK): HSI,
- HSE and PLL.
- The AHB clock (HCLK) is derived from System clock through configurable prescaler
- and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...).
- APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through
- configurable prescalers and used to clock the peripherals mapped on these busses.
- You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
-
-@note All the peripheral clocks are derived from the System clock (SYSCLK) except:
- - I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
- from an external clock mapped on the I2S_CKIN pin.
- You have to use RCC_I2SCLKConfig() function to configure this clock.
- - RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
- divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
- functions to configure this clock.
- - USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
- to work correctly, while the SDIO require a frequency equal or lower than
- to 48. This clock is derived of the main PLL through PLLQ divider.
- - IWDG clock which is always the LSI clock.
-
- 2. The maximum frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz.
- Depending on the device voltage range, the maximum frequency should be
- adapted accordingly:
- +-------------------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
- | | voltage range | voltage range | voltage range | voltage range |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
- |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120|
- +-------------------------------------------------------------------------------------+
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the system clock (SYSCLK).
- * @note The HSI is used (enabled by hardware) as system clock source after
- * startup from Reset, wake-up from STOP and STANDBY mode, or in case
- * of failure of the HSE used directly or indirectly as system clock
- * (if the Clock Security System CSS is enabled).
- * @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after startup delay or PLL locked).
- * If a clock source which is not yet ready is selected, the switch will
- * occur when the clock source will be ready.
- * You can use RCC_GetSYSCLKSource() function to know which clock is
- * currently used as system clock source.
- * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
- * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
- * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
- * @retval None
- */
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
-
- tmpreg = RCC->CFGR;
-
- /* Clear SW[1:0] bits */
- tmpreg &= ~RCC_CFGR_SW;
-
- /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
- tmpreg |= RCC_SYSCLKSource;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Returns the clock source used as system clock.
- * @param None
- * @retval The clock source used as system clock. The returned value can be one
- * of the following:
- * - 0x00: HSI used as system clock
- * - 0x04: HSE used as system clock
- * - 0x08: PLL used as system clock
- */
-uint8_t RCC_GetSYSCLKSource(void)
-{
- return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
-}
-
-/**
- * @brief Configures the AHB clock (HCLK).
- * @note Depending on the device voltage range, the software has to set correctly
- * these bits to ensure that HCLK not exceed the maximum allowed frequency
- * (for more details refer to section above
- * "CPU, AHB and APB busses clocks configuration functions")
- * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
- * the system clock (SYSCLK).
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
- * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
- * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
- * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
- * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
- * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
- * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
- * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
- * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
- * @retval None
- */
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_HCLK(RCC_SYSCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear HPRE[3:0] bits */
- tmpreg &= ~RCC_CFGR_HPRE;
-
- /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
- tmpreg |= RCC_SYSCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-
-/**
- * @brief Configures the Low Speed APB clock (PCLK1).
- * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
- * the AHB clock (HCLK).
- * This parameter can be one of the following values:
- * @arg RCC_HCLK_Div1: APB1 clock = HCLK
- * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
- * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
- * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
- * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
- * @retval None
- */
-void RCC_PCLK1Config(uint32_t RCC_HCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear PPRE1[2:0] bits */
- tmpreg &= ~RCC_CFGR_PPRE1;
-
- /* Set PPRE1[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Configures the High Speed APB clock (PCLK2).
- * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
- * the AHB clock (HCLK).
- * This parameter can be one of the following values:
- * @arg RCC_HCLK_Div1: APB2 clock = HCLK
- * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
- * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
- * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
- * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
- * @retval None
- */
-void RCC_PCLK2Config(uint32_t RCC_HCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear PPRE2[2:0] bits */
- tmpreg &= ~RCC_CFGR_PPRE2;
-
- /* Set PPRE2[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK << 3;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK,
- * PCLK1 and PCLK2.
- *
- * @note The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
- * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
- * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- * @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
- * 16 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- * @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
- * 25 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * @note The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
- * the clocks frequencies.
- *
- * @note This function can be used by the user application to compute the
- * baudrate for the communication peripherals or configure other parameters.
- * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
- * must be called to update the structure's field. Otherwise, any
- * configuration based on this function will be incorrect.
- *
- * @retval None
- */
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
-{
- uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock source */
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock source */
- RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock source */
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLP
- */
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-
- pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
- RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
- break;
- default:
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- }
- /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
-
- /* Get HCLK prescaler */
- tmp = RCC->CFGR & RCC_CFGR_HPRE;
- tmp = tmp >> 4;
- presc = APBAHBPrescTable[tmp];
- /* HCLK clock frequency */
- RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
-
- /* Get PCLK1 prescaler */
- tmp = RCC->CFGR & RCC_CFGR_PPRE1;
- tmp = tmp >> 10;
- presc = APBAHBPrescTable[tmp];
- /* PCLK1 clock frequency */
- RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-
- /* Get PCLK2 prescaler */
- tmp = RCC->CFGR & RCC_CFGR_PPRE2;
- tmp = tmp >> 13;
- presc = APBAHBPrescTable[tmp];
- /* PCLK2 clock frequency */
- RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group3 Peripheral clocks configuration functions
- * @brief Peripheral clocks configuration functions
- *
-@verbatim
- ===============================================================================
- Peripheral clocks configuration functions
- ===============================================================================
-
- This section provide functions allowing to configure the Peripheral clocks.
-
- 1. The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31.
-
- 2. After restart from Reset or wakeup from STANDBY, all peripherals are off
- except internal SRAM, Flash and JTAG. Before to start using a peripheral you
- have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd()
- , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
-
- 3. To reset the peripherals configuration (to the default state after device reset)
- you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and
- RCC_APB1PeriphResetCmd() functions.
-
- 4. To further reduce power consumption in SLEEP mode the peripheral clocks can
- be disabled prior to executing the WFI or WFE instructions. You can do this
- using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and
- RCC_APB1PeriphClockLPModeCmd() functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC clock (RTCCLK).
- * @note As the RTC clock configuration bits are in the Backup domain and write
- * access is denied to this domain after reset, you have to enable write
- * access using PWR_BackupAccessCmd(ENABLE) function before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it can't be changed unless the
- * Backup domain is reset using RCC_BackupResetCmd() function, or by
- * a Power On Reset (POR).
- *
- * @param RCC_RTCCLKSource: specifies the RTC clock source.
- * This parameter can be one of the following values:
- * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
- * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
- * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected
- * as RTC clock, where x:[2,31]
- *
- * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
- * work in STOP and STANDBY modes, and can be used as wakeup source.
- * However, when the HSE clock is used as RTC clock source, the RTC
- * cannot be used in STOP and STANDBY modes.
- * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
- * RTC clock source).
- *
- * @retval None
- */
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
-
- if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
- { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
- tmpreg = RCC->CFGR;
-
- /* Clear RTCPRE[4:0] bits */
- tmpreg &= ~RCC_CFGR_RTCPRE;
-
- /* Configure HSE division factor for RTC clock */
- tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
- }
-
- /* Select the RTC clock source */
- RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
-}
-
-/**
- * @brief Enables or disables the RTC clock.
- * @note This function must be used only after the RTC clock source was selected
- * using the RCC_RTCCLKConfig function.
- * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_RTCCLKCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Forces or releases the Backup domain reset.
- * @note This function resets the RTC peripheral (including the backup registers)
- * and the RTC clock source selection in RCC_CSR register.
- * @note The BKPSRAM is not affected by this reset.
- * @param NewState: new state of the Backup domain reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_BackupResetCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the I2S clock source (I2SCLK).
- *
- * @note This function must be called before enabling the I2S APB clock.
- * @note This function applies only to Silicon RevisionB and RevisionY.
- *
- * @param RCC_I2SCLKSource: specifies the I2S clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
- * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
- * used as I2S clock source
- * @retval None
- */
-void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
-
- *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
-}
-
-/**
- * @brief Enables or disables the AHB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
- * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
- * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
- * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
- * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
- * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
- * @arg RCC_AHB1Periph_CRC: CRC clock
- * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
- * @arg RCC_AHB1Periph_DMA1: DMA1 clock
- * @arg RCC_AHB1Periph_DMA2: DMA2 clock
- * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
- * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
- * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
- * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
- * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
- * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
-
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB1ENR |= RCC_AHB1Periph;
- }
- else
- {
- RCC->AHB1ENR &= ~RCC_AHB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB2Periph_DCMI: DCMI clock
- * @arg RCC_AHB2Periph_CRYP: CRYP clock
- * @arg RCC_AHB2Periph_HASH: HASH clock
- * @arg RCC_AHB2Periph_RNG: RNG clock
- * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB2ENR |= RCC_AHB2Periph;
- }
- else
- {
- RCC->AHB2ENR &= ~RCC_AHB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB3 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
- * This parameter must be: RCC_AHB3Periph_FSMC
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB3ENR |= RCC_AHB3Periph;
- }
- else
- {
- RCC->AHB3ENR &= ~RCC_AHB3Periph;
- }
-}
-
-/**
- * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM4: TIM4 clock
- * @arg RCC_APB1Periph_TIM5: TIM5 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock
- * @arg RCC_APB1Periph_TIM12: TIM12 clock
- * @arg RCC_APB1Periph_TIM13: TIM13 clock
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_SPI3: SPI3 clock
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock
- * @arg RCC_APB1Periph_UART4: UART4 clock
- * @arg RCC_APB1Periph_UART5: UART5 clock
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_I2C3: I2C3 clock
- * @arg RCC_APB1Periph_CAN1: CAN1 clock
- * @arg RCC_APB1Periph_CAN2: CAN2 clock
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB1ENR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1ENR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_TIM8: TIM8 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_USART6: USART6 clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_ADC2: ADC2 clock
- * @arg RCC_APB2Periph_ADC3: ADC3 clock
- * @arg RCC_APB2Periph_SDIO: SDIO clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_TIM9: TIM9 clock
- * @arg RCC_APB2Periph_TIM10: TIM10 clock
- * @arg RCC_APB2Periph_TIM11: TIM11 clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB2ENR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2ENR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB1 peripheral reset.
- * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
- * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
- * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
- * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
- * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
- * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
- * @arg RCC_AHB1Periph_CRC: CRC clock
- * @arg RCC_AHB1Periph_DMA1: DMA1 clock
- * @arg RCC_AHB1Periph_DMA2: DMA2 clock
- * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
- * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
- *
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB1RSTR |= RCC_AHB1Periph;
- }
- else
- {
- RCC->AHB1RSTR &= ~RCC_AHB1Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB2 peripheral reset.
- * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB2Periph_DCMI: DCMI clock
- * @arg RCC_AHB2Periph_CRYP: CRYP clock
- * @arg RCC_AHB2Periph_HASH: HASH clock
- * @arg RCC_AHB2Periph_RNG: RNG clock
- * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB2RSTR |= RCC_AHB2Periph;
- }
- else
- {
- RCC->AHB2RSTR &= ~RCC_AHB2Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB3 peripheral reset.
- * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
- * This parameter must be: RCC_AHB3Periph_FSMC
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB3RSTR |= RCC_AHB3Periph;
- }
- else
- {
- RCC->AHB3RSTR &= ~RCC_AHB3Periph;
- }
-}
-
-/**
- * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM4: TIM4 clock
- * @arg RCC_APB1Periph_TIM5: TIM5 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock
- * @arg RCC_APB1Periph_TIM12: TIM12 clock
- * @arg RCC_APB1Periph_TIM13: TIM13 clock
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_SPI3: SPI3 clock
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock
- * @arg RCC_APB1Periph_UART4: UART4 clock
- * @arg RCC_APB1Periph_UART5: UART5 clock
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_I2C3: I2C3 clock
- * @arg RCC_APB1Periph_CAN1: CAN1 clock
- * @arg RCC_APB1Periph_CAN2: CAN2 clock
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB1RSTR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1RSTR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Forces or releases High Speed APB (APB2) peripheral reset.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_TIM8: TIM8 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_USART6: USART6 clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_ADC2: ADC2 clock
- * @arg RCC_APB2Periph_ADC3: ADC3 clock
- * @arg RCC_APB2Periph_SDIO: SDIO clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_TIM9: TIM9 clock
- * @arg RCC_APB2Periph_TIM10: TIM10 clock
- * @arg RCC_APB2Periph_TIM11: TIM11 clock
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB2RSTR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2RSTR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
- * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
- * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
- * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
- * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
- * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
- * @arg RCC_AHB1Periph_CRC: CRC clock
- * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
- * @arg RCC_AHB1Periph_DMA1: DMA1 clock
- * @arg RCC_AHB1Periph_DMA2: DMA2 clock
- * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
- * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
- * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
- * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
- * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
- * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB1LPENR |= RCC_AHB1Periph;
- }
- else
- {
- RCC->AHB1LPENR &= ~RCC_AHB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB2Periph_DCMI: DCMI clock
- * @arg RCC_AHB2Periph_CRYP: CRYP clock
- * @arg RCC_AHB2Periph_HASH: HASH clock
- * @arg RCC_AHB2Periph_RNG: RNG clock
- * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB2LPENR |= RCC_AHB2Periph;
- }
- else
- {
- RCC->AHB2LPENR &= ~RCC_AHB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
- * This parameter must be: RCC_AHB3Periph_FSMC
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB3LPENR |= RCC_AHB3Periph;
- }
- else
- {
- RCC->AHB3LPENR &= ~RCC_AHB3Periph;
- }
-}
-
-/**
- * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM4: TIM4 clock
- * @arg RCC_APB1Periph_TIM5: TIM5 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock
- * @arg RCC_APB1Periph_TIM12: TIM12 clock
- * @arg RCC_APB1Periph_TIM13: TIM13 clock
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_SPI3: SPI3 clock
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock
- * @arg RCC_APB1Periph_UART4: UART4 clock
- * @arg RCC_APB1Periph_UART5: UART5 clock
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_I2C3: I2C3 clock
- * @arg RCC_APB1Periph_CAN1: CAN1 clock
- * @arg RCC_APB1Periph_CAN2: CAN2 clock
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB1LPENR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1LPENR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_TIM8: TIM8 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_USART6: USART6 clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_ADC2: ADC2 clock
- * @arg RCC_APB2Periph_ADC3: ADC3 clock
- * @arg RCC_APB2Periph_SDIO: SDIO clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_TIM9: TIM9 clock
- * @arg RCC_APB2Periph_TIM10: TIM10 clock
- * @arg RCC_APB2Periph_TIM11: TIM11 clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB2LPENR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2LPENR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified RCC interrupts.
- * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
- * @param NewState: new state of the specified RCC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_IT(RCC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
- }
- else
- {
- /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified RCC flag is set or not.
- * @param RCC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
- * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
- * @arg RCC_FLAG_PLLRDY: main PLL clock ready
- * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
- * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
- * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
- * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset
- * @arg RCC_FLAG_PINRST: Pin reset
- * @arg RCC_FLAG_PORRST: POR/PDR reset
- * @arg RCC_FLAG_SFTRST: Software reset
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
- * @arg RCC_FLAG_LPWRRST: Low Power reset
- * @retval The new state of RCC_FLAG (SET or RESET).
- */
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
-{
- uint32_t tmp = 0;
- uint32_t statusreg = 0;
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_FLAG(RCC_FLAG));
-
- /* Get the RCC register index */
- tmp = RCC_FLAG >> 5;
- if (tmp == 1) /* The flag to check is in CR register */
- {
- statusreg = RCC->CR;
- }
- else if (tmp == 2) /* The flag to check is in BDCR register */
- {
- statusreg = RCC->BDCR;
- }
- else /* The flag to check is in CSR register */
- {
- statusreg = RCC->CSR;
- }
-
- /* Get the flag position */
- tmp = RCC_FLAG & FLAG_MASK;
- if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC reset flags.
- * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
- * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
- * @param None
- * @retval None
- */
-void RCC_ClearFlag(void)
-{
- /* Set RMVF bit to clear the reset flags */
- RCC->CSR |= RCC_CSR_RMVF;
-}
-
-/**
- * @brief Checks whether the specified RCC interrupt has occurred or not.
- * @param RCC_IT: specifies the RCC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval The new state of RCC_IT (SET or RESET).
- */
-ITStatus RCC_GetITStatus(uint8_t RCC_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_GET_IT(RCC_IT));
-
- /* Check the status of the specified RCC interrupt */
- if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the RCC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC's interrupt pending bits.
- * @param RCC_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval None
- */
-void RCC_ClearITPendingBit(uint8_t RCC_IT)
-{
- /* Check the parameters */
- assert_param(IS_RCC_CLEAR_IT(RCC_IT));
-
- /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
- pending bits */
- *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_rng.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Random Number Generator (RNG) peripheral:
- * - Initialization and Configuration
- * - Get 32 bit Random number
- * - Interrupts and flags management
- *
- * @verbatim
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * 1. Enable The RNG controller clock using
- * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function.
- *
- * 2. Activate the RNG peripheral using RNG_Cmd() function.
- *
- * 3. Wait until the 32 bit Random number Generator contains a valid
- * random data (using polling/interrupt mode). For more details,
- * refer to "Interrupts and flags management functions" module
- * description.
- *
- * 4. Get the 32 bit Random number using RNG_GetRandomNumber() function
- *
- * 5. To get another 32 bit Random number, go to step 3.
- *
- *
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RNG
- * @brief RNG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RNG_Private_Functions
- * @{
- */
-
-/** @defgroup RNG_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- Initialization and Configuration functions
- ===============================================================================
- This section provides functions allowing to
- - Initialize the RNG peripheral
- - Enable or disable the RNG peripheral
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the RNG peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void RNG_DeInit(void)
-{
- /* Enable RNG reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE);
-
- /* Release RNG from reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE);
-}
-
-/**
- * @brief Enables or disables the RNG peripheral.
- * @param NewState: new state of the RNG peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RNG_Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the RNG */
- RNG->CR |= RNG_CR_RNGEN;
- }
- else
- {
- /* Disable the RNG */
- RNG->CR &= ~RNG_CR_RNGEN;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup RNG_Group2 Get 32 bit Random number function
- * @brief Get 32 bit Random number function
- *
-
-@verbatim
- ===============================================================================
- Get 32 bit Random number function
- ===============================================================================
- This section provides a function allowing to get the 32 bit Random number
-
- @note Before to call this function you have to wait till DRDY flag is set,
- using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Returns a 32-bit random number.
- *
- * @note Before to call this function you have to wait till DRDY (data ready)
- * flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.
- * @note Each time the the Random number data is read (using RNG_GetRandomNumber()
- * function), the RNG_FLAG_DRDY flag is automatically cleared.
- * @note In the case of a seed error, the generation of random numbers is
- * interrupted for as long as the SECS bit is '1'. If a number is
- * available in the RNG_DR register, it must not be used because it may
- * not have enough entropy. In this case, it is recommended to clear the
- * SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable
- * and enable the RNG peripheral (using RNG_Cmd() function) to
- * reinitialize and restart the RNG.
- * @note In the case of a clock error, the RNG is no more able to generate
- * random numbers because the PLL48CLK clock is not correct. User have
- * to check that the clock controller is correctly configured to provide
- * the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS)
- * function) . The clock error has no impact on the previously generated
- * random numbers, and the RNG_DR register contents can be used.
- *
- * @param None
- * @retval 32-bit random number.
- */
-uint32_t RNG_GetRandomNumber(void)
-{
- /* Return the 32 bit random number from the DR register */
- return RNG->DR;
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup RNG_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
-
- This section provides functions allowing to configure the RNG Interrupts and
- to get the status and clear flags and Interrupts pending bits.
-
- The RNG provides 3 Interrupts sources and 3 Flags:
-
- Flags :
- ----------
- 1. RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid
- random data. it is cleared by reading the valid data
- (using RNG_GetRandomNumber() function).
-
- 2. RNG_FLAG_CECS : In the case of a seed error detection.
-
- 3. RNG_FLAG_SECS : In the case of a clock error detection.
-
-
- Interrupts :
- ------------
- if enabled, an RNG interrupt is pending :
-
- 1. In the case of the RNG_DR register contains valid random data.
- This interrupt source is cleared once the RNG_DR register has been read
- (using RNG_GetRandomNumber() function) until a new valid value is
- computed.
-
- or
- 2. In the case of a seed error : One of the following faulty sequences has
- been detected:
- - More than 64 consecutive bits at the same value (0 or 1)
- - More than 32 consecutive alternance of 0 and 1 (0101010101...01)
- This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI)
- function.
-
- or
- 3. In the case of a clock error : the PLL48CLK (RNG peripheral clock source)
- was not correctly detected (fPLL48CLK< fHCLK/16).
- This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_CEI)
- function.
- @note In this case, User have to check that the clock controller is
- correctly configured to provide the RNG clock.
-
- Managing the RNG controller events :
- ------------------------------------
- The user should identify which mode will be used in his application to manage
- the RNG controller events: Polling mode or Interrupt mode.
-
- 1. In the Polling Mode it is advised to use the following functions:
- - RNG_GetFlagStatus() : to check if flags events occur.
- - RNG_ClearFlag() : to clear the flags events.
-
- @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only
- by reading the Random number data.
-
- 2. In the Interrupt Mode it is advised to use the following functions:
- - RNG_ITConfig() : to enable or disable the interrupt source.
- - RNG_GetITStatus() : to check if Interrupt occurs.
- - RNG_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the RNG interrupt.
- * @note The RNG provides 3 interrupt sources,
- * - Computed data is ready event (DRDY), and
- * - Seed error Interrupt (SEI) and
- * - Clock error Interrupt (CEI),
- * all these interrupts sources are enabled by setting the IE bit in
- * CR register. However, each interrupt have its specific status bit
- * (see RNG_GetITStatus() function) and clear bit except the DRDY event
- * (see RNG_ClearITPendingBit() function).
- * @param NewState: new state of the RNG interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RNG_ITConfig(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the RNG interrupt */
- RNG->CR |= RNG_CR_IE;
- }
- else
- {
- /* Disable the RNG interrupt */
- RNG->CR &= ~RNG_CR_IE;
- }
-}
-
-/**
- * @brief Checks whether the specified RNG flag is set or not.
- * @param RNG_FLAG: specifies the RNG flag to check.
- * This parameter can be one of the following values:
- * @arg RNG_FLAG_DRDY: Data Ready flag.
- * @arg RNG_FLAG_CECS: Clock Error Current flag.
- * @arg RNG_FLAG_SECS: Seed Error Current flag.
- * @retval The new state of RNG_FLAG (SET or RESET).
- */
-FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_RNG_GET_FLAG(RNG_FLAG));
-
- /* Check the status of the specified RNG flag */
- if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET)
- {
- /* RNG_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* RNG_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the RNG_FLAG status */
- return bitstatus;
-}
-
-
-/**
- * @brief Clears the RNG flags.
- * @param RNG_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg RNG_FLAG_CECS: Clock Error Current flag.
- * @arg RNG_FLAG_SECS: Seed Error Current flag.
- * @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function.
- * This flag is cleared only by reading the Random number data (using
- * RNG_GetRandomNumber() function).
- * @retval None
- */
-void RNG_ClearFlag(uint8_t RNG_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG));
- /* Clear the selected RNG flags */
- RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4);
-}
-
-/**
- * @brief Checks whether the specified RNG interrupt has occurred or not.
- * @param RNG_IT: specifies the RNG interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RNG_IT_CEI: Clock Error Interrupt.
- * @arg RNG_IT_SEI: Seed Error Interrupt.
- * @retval The new state of RNG_IT (SET or RESET).
- */
-ITStatus RNG_GetITStatus(uint8_t RNG_IT)
-{
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_RNG_GET_IT(RNG_IT));
-
- /* Check the status of the specified RNG interrupt */
- if ((RNG->SR & RNG_IT) != (uint8_t)RESET)
- {
- /* RNG_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* RNG_IT is reset */
- bitstatus = RESET;
- }
- /* Return the RNG_IT status */
- return bitstatus;
-}
-
-
-/**
- * @brief Clears the RNG interrupt pending bit(s).
- * @param RNG_IT: specifies the RNG interrupt pending bit(s) to clear.
- * This parameter can be any combination of the following values:
- * @arg RNG_IT_CEI: Clock Error Interrupt.
- * @arg RNG_IT_SEI: Seed Error Interrupt.
- * @retval None
- */
-void RNG_ClearITPendingBit(uint8_t RNG_IT)
-{
- /* Check the parameters */
- assert_param(IS_RNG_IT(RNG_IT));
-
- /* Clear the selected RNG interrupt pending bit */
- RNG->SR = (uint8_t)~RNG_IT;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_rtc.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Real-Time Clock (RTC) peripheral:
- * - Initialization
- * - Calendar (Time and Date) configuration
- * - Alarms (Alarm A and Alarm B) configuration
- * - WakeUp Timer configuration
- * - Daylight Saving configuration
- * - Output pin Configuration
- * - Coarse digital Calibration configuration
- * - Smooth digital Calibration configuration
- * - TimeStamp configuration
- * - Tampers configuration
- * - Backup Data Registers configuration
- * - Shift control synchronisation
- * - RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
- * - Interrupts and flags management
- *
- * @verbatim
- *
- * ===================================================================
- * Backup Domain Operating Condition
- * ===================================================================
- * The real-time clock (RTC), the RTC backup registers, and the backup
- * SRAM (BKP SRAM) can be powered from the VBAT voltage when the main
- * VDD supply is powered off.
- * To retain the content of the RTC backup registers, backup SRAM,
- * and supply the RTC when VDD is turned off, VBAT pin can be connected
- * to an optional standby voltage supplied by a battery or by another
- * source.
- *
- * To allow the RTC to operate even when the main digital supply (VDD)
- * is turned off, the VBAT pin powers the following blocks:
- * 1 - The RTC
- * 2 - The LSE oscillator
- * 3 - The backup SRAM when the low power backup regulator is enabled
- * 4 - PC13 to PC15 I/Os, plus PI8 I/O (when available)
- *
- * When the backup domain is supplied by VDD (analog switch connected
- * to VDD), the following functions are available:
- * 1 - PC14 and PC15 can be used as either GPIO or LSE pins
- * 2 - PC13 can be used as a GPIO or as the RTC_AF1 pin
- * 3 - PI8 can be used as a GPIO or as the RTC_AF2 pin
- *
- * When the backup domain is supplied by VBAT (analog switch connected
- * to VBAT because VDD is not present), the following functions are available:
- * 1 - PC14 and PC15 can be used as LSE pins only
- * 2 - PC13 can be used as the RTC_AF1 pin
- * 3 - PI8 can be used as the RTC_AF2 pin
- *
- * ===================================================================
- * Backup Domain Reset
- * ===================================================================
- * The backup domain reset sets all RTC registers and the RCC_BDCR
- * register to their reset values. The BKPSRAM is not affected by this
- * reset. The only way of resetting the BKPSRAM is through the Flash
- * interface by requesting a protection level change from 1 to 0.
- * A backup domain reset is generated when one of the following events
- * occurs:
- * 1 - Software reset, triggered by setting the BDRST bit in the
- * RCC Backup domain control register (RCC_BDCR). You can use the
- * RCC_BackupResetCmd().
- * 2 - VDD or VBAT power on, if both supplies have previously been
- * powered off.
- *
- * ===================================================================
- * Backup Domain Access
- * ===================================================================
- * After reset, the backup domain (RTC registers, RTC backup data
- * registers and backup SRAM) is protected against possible unwanted
- * write accesses.
- * To enable access to the RTC Domain and RTC registers, proceed as follows:
- * - Enable the Power Controller (PWR) APB1 interface clock using the
- * RCC_APB1PeriphClockCmd() function.
- * - Enable access to RTC domain using the PWR_BackupAccessCmd() function.
- * - Select the RTC clock source using the RCC_RTCCLKConfig() function.
- * - Enable RTC Clock using the RCC_RTCCLKCmd() function.
- *
- * ===================================================================
- * RTC Driver: how to use it
- * ===================================================================
- * - Enable the RTC domain access (see description in the section above)
- * - Configure the RTC Prescaler (Asynchronous and Synchronous) and
- * RTC hour format using the RTC_Init() function.
- *
- * Time and Date configuration
- * ===========================
- * - To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
- * and RTC_SetDate() functions.
- * - To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()
- * functions.
- * - Use the RTC_DayLightSavingConfig() function to add or sub one
- * hour to the RTC Calendar.
- *
- * Alarm configuration
- * ===================
- * - To configure the RTC Alarm use the RTC_SetAlarm() function.
- * - Enable the selected RTC Alarm using the RTC_AlarmCmd() function
- * - To read the RTC Alarm, use the RTC_GetAlarm() function.
- * - To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
- *
- * RTC Wakeup configuration
- * ========================
- * - Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
- * function.
- * - Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter()
- * function
- * - Enable the RTC WakeUp using the RTC_WakeUpCmd() function
- * - To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter()
- * function.
- *
- * Outputs configuration
- * =====================
- * The RTC has 2 different outputs:
- * - AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B
- * and WaKeUp signals.
- * To output the selected RTC signal on RTC_AF1 pin, use the
- * RTC_OutputConfig() function.
- * - AFO_CALIB: this output is 512Hz signal or 1Hz .
- * To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd()
- * function.
- *
- * Smooth digital Calibration configuration
- * =================================
- * - Configure the RTC Original Digital Calibration Value and the corresponding
- * calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig()
- * function.
- *
- * Coarse digital Calibration configuration
- * =================================
- * - Configure the RTC Coarse Calibration Value and the corresponding
- * sign using the RTC_CoarseCalibConfig() function.
- * - Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd()
- * function
- *
- * TimeStamp configuration
- * =======================
- * - Configure the RTC_AF1 trigger and enables the RTC TimeStamp
- * using the RTC_TimeStampCmd() function.
- * - To read the RTC TimeStamp Time and Date register, use the
- * RTC_GetTimeStamp() function.
- * - To read the RTC TimeStamp SubSecond register, use the
- * RTC_GetTimeStampSubSecond() function.
- * - The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13)
- * or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in
- * RTC_TAFCR register. You can use the RTC_TamperPinSelection()
- * function to select the corresponding pin.
- *
- * Tamper configuration
- * ====================
- * - Enable the RTC Tamper using the RTC_TamperCmd() function.
- * - Configure the Tamper filter count using RTC_TamperFilterConfig()
- * function.
- * - Configure the RTC Tamper trigger Edge or Level according to the Tamper
- * filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function.
- * - Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
- * function.
- * - Configure the Tamper precharge or discharge duration using
- * RTC_TamperPinsPrechargeDuration() function.
- * - Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
- * - Enable the Time stamp on Tamper detection event using
- * RTC_TSOnTamperDetecCmd() function.
- * - The TIMESTAMP alternate function can be mapped to either RTC_AF1
- * or RTC_AF2 depending on the value of the TSINSEL bit in the
- * RTC_TAFCR register. You can use the RTC_TimeStampPinSelection()
- * function to select the corresponding pin.
- *
- * Backup Data Registers configuration
- * ===================================
- * - To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
- * function.
- * - To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
- * function.
- *
- * ===================================================================
- * RTC and low power modes
- * ===================================================================
- * The MCU can be woken up from a low power mode by an RTC alternate
- * function.
- * The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
- * RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
- * These RTC alternate functions can wake up the system from the Stop
- * and Standby lowpower modes.
- * The system can also wake up from low power modes without depending
- * on an external interrupt (Auto-wakeup mode), by using the RTC alarm
- * or the RTC wakeup events.
- * The RTC provides a programmable time base for waking up from the
- * Stop or Standby mode at regular intervals.
- * Wakeup from STOP and Standby modes is possible only when the RTC
- * clock source is LSE or LSI.
- *
- * ===================================================================
- * Selection of RTC_AF1 alternate functions
- * ===================================================================
- * The RTC_AF1 pin (PC13) can be used for the following purposes:
- * - AFO_ALARM output
- * - AFO_CALIB output
- * - AFI_TAMPER
- * - AFI_TIMESTAMP
- *
- * +-------------------------------------------------------------------------------------------------------------+
- * | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE |
- * | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM |
- * | and function | | | | | selection | selection |Configuration |
- * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- * | Alarm out | | | | | Don't | Don't | |
- * | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 |
- * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- * | Alarm out | | | | | Don't | Don't | |
- * | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 |
- * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- * | Calibration out | | | | | Don't | Don't | |
- * | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care |
- * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- * | TAMPER input | | | | | | Don't | |
- * | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care |
- * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- * | TIMESTAMP and | | | | | | | |
- * | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care |
- * | floating | | | | | | | |
- * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- * | TIMESTAMP input | | | | | Don't | | |
- * | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care |
- * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- * | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care |
- * +-------------------------------------------------------------------------------------------------------------+
- *
- *
- * ===================================================================
- * Selection of RTC_AF2 alternate functions
- * ===================================================================
- * The RTC_AF2 pin (PI8) can be used for the following purposes:
- * - AFI_TAMPER
- * - AFI_TIMESTAMP
- *
- * +---------------------------------------------------------------------------------------+
- * | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE |
- * | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM |
- * | and function | | | selection | selection |Configuration |
- * |-----------------|-----------|--------------|------------|--------------|--------------|
- * | TAMPER input | | | | Don't | |
- * | floating | 1 | 0 | 1 | care | Don't care |
- * |-----------------|-----------|--------------|------------|--------------|--------------|
- * | TIMESTAMP and | | | | | |
- * | TAMPER input | 1 | 1 | 1 | 1 | Don't care |
- * | floating | | | | | |
- * |-----------------|-----------|--------------|------------|--------------|--------------|
- * | TIMESTAMP input | | | Don't | | |
- * | floating | 0 | 1 | care | 1 | Don't care |
- * |-----------------|-----------|--------------|------------|--------------|--------------|
- * | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care |
- * +---------------------------------------------------------------------------------------+
- *
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_rtc.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RTC
- * @brief RTC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* Masks Definition */
-#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
-#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
-#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
-#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
-#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
- RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
- RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
- RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F ))
-
-#define INITMODE_TIMEOUT ((uint32_t) 0x00010000)
-#define SYNCHRO_TIMEOUT ((uint32_t) 0x00020000)
-#define RECALPF_TIMEOUT ((uint32_t) 0x00020000)
-#define SHPF_TIMEOUT ((uint32_t) 0x00001000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static uint8_t RTC_ByteToBcd2(uint8_t Value);
-static uint8_t RTC_Bcd2ToByte(uint8_t Value);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RTC_Private_Functions
- * @{
- */
-
-/** @defgroup RTC_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- Initialization and Configuration functions
- ===============================================================================
-
- This section provide functions allowing to initialize and configure the RTC
- Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers
- Write protection, enter and exit the RTC initialization mode, RTC registers
- synchronization check and reference clock detection enable.
-
- 1. The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is
- split into 2 programmable prescalers to minimize power consumption.
- - A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
- - When both prescalers are used, it is recommended to configure the asynchronous
- prescaler to a high value to minimize consumption.
-
- 2. All RTC registers are Write protected. Writing to the RTC registers
- is enabled by writing a key into the Write Protection register, RTC_WPR.
-
- 3. To Configure the RTC Calendar, user application should enter initialization
- mode. In this mode, the calendar counter is stopped and its value can be
- updated. When the initialization sequence is complete, the calendar restarts
- counting after 4 RTCCLK cycles.
-
- 4. To read the calendar through the shadow registers after Calendar initialization,
- calendar update or after wakeup from low power modes the software must first
- clear the RSF flag. The software must then wait until it is set again before
- reading the calendar, which means that the calendar registers have been
- correctly copied into the RTC_TR and RTC_DR shadow registers.
- The RTC_WaitForSynchro() function implements the above software sequence
- (RSF clear and RSF check).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the RTC registers to their default reset values.
- * @note This function doesn't reset the RTC Clock source and RTC Backup Data
- * registers.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are deinitialized
- * - ERROR: RTC registers are not deinitialized
- */
-ErrorStatus RTC_DeInit(void)
-{
- __IO uint32_t wutcounter = 0x00;
- uint32_t wutwfstatus = 0x00;
- ErrorStatus status = ERROR;
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Reset TR, DR and CR registers */
- RTC->TR = (uint32_t)0x00000000;
- RTC->DR = (uint32_t)0x00002101;
- /* Reset All CR bits except CR[2:0] */
- RTC->CR &= (uint32_t)0x00000007;
-
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- do
- {
- wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
- wutcounter++;
- } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
-
- if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
- {
- status = ERROR;
- }
- else
- {
- /* Reset all RTC CR register bits */
- RTC->CR &= (uint32_t)0x00000000;
- RTC->WUTR = (uint32_t)0x0000FFFF;
- RTC->PRER = (uint32_t)0x007F00FF;
- RTC->CALIBR = (uint32_t)0x00000000;
- RTC->ALRMAR = (uint32_t)0x00000000;
- RTC->ALRMBR = (uint32_t)0x00000000;
-
- /* Reset ISR register and exit initialization mode */
- RTC->ISR = (uint32_t)0x00000000;
-
- /* Reset Tamper and alternate functions configuration register */
- RTC->TAFCR = 0x00000000;
-
- if(RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Initializes the RTC registers according to the specified parameters
- * in RTC_InitStruct.
- * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains
- * the configuration information for the RTC peripheral.
- * @note The RTC Prescaler register is write protected and can be written in
- * initialization mode only.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are initialized
- * - ERROR: RTC registers are not initialized
- */
-ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
- assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));
- assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Clear RTC CR FMT Bit */
- RTC->CR &= ((uint32_t)~(RTC_CR_FMT));
- /* Set RTC_CR register */
- RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
-
- /* Configure the RTC PRER */
- RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
- RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
-
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- status = SUCCESS;
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Fills each RTC_InitStruct member with its default value.
- * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be
- * initialized.
- * @retval None
- */
-void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)
-{
- /* Initialize the RTC_HourFormat member */
- RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;
-
- /* Initialize the RTC_AsynchPrediv member */
- RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
-
- /* Initialize the RTC_SynchPrediv member */
- RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF;
-}
-
-/**
- * @brief Enables or disables the RTC registers write protection.
- * @note All the RTC registers are write protected except for RTC_ISR[13:8],
- * RTC_TAFCR and RTC_BKPxR.
- * @note Writing a wrong key reactivates the write protection.
- * @note The protection mechanism is not affected by system reset.
- * @param NewState: new state of the write protection.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_WriteProtectionCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
- }
- else
- {
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
- }
-}
-
-/**
- * @brief Enters the RTC Initialization mode.
- * @note The RTC Initialization mode is write protected, use the
- * RTC_WriteProtectionCmd(DISABLE) before calling this function.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC is in Init mode
- * - ERROR: RTC is not in Init mode
- */
-ErrorStatus RTC_EnterInitMode(void)
-{
- __IO uint32_t initcounter = 0x00;
- ErrorStatus status = ERROR;
- uint32_t initstatus = 0x00;
-
- /* Check if the Initialization mode is set */
- if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
- {
- /* Set the Initialization mode */
- RTC->ISR = (uint32_t)RTC_INIT_MASK;
-
- /* Wait till RTC is in INIT state and if Time out is reached exit */
- do
- {
- initstatus = RTC->ISR & RTC_ISR_INITF;
- initcounter++;
- } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
-
- if ((RTC->ISR & RTC_ISR_INITF) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
- }
- else
- {
- status = SUCCESS;
- }
-
- return (status);
-}
-
-/**
- * @brief Exits the RTC Initialization mode.
- * @note When the initialization sequence is complete, the calendar restarts
- * counting after 4 RTCCLK cycles.
- * @note The RTC Initialization mode is write protected, use the
- * RTC_WriteProtectionCmd(DISABLE) before calling this function.
- * @param None
- * @retval None
- */
-void RTC_ExitInitMode(void)
-{
- /* Exit Initialization mode */
- RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
-}
-
-/**
- * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
- * synchronized with RTC APB clock.
- * @note The RTC Resynchronization mode is write protected, use the
- * RTC_WriteProtectionCmd(DISABLE) before calling this function.
- * @note To read the calendar through the shadow registers after Calendar
- * initialization, calendar update or after wakeup from low power modes
- * the software must first clear the RSF flag.
- * The software must then wait until it is set again before reading
- * the calendar, which means that the calendar registers have been
- * correctly copied into the RTC_TR and RTC_DR shadow registers.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are synchronised
- * - ERROR: RTC registers are not synchronised
- */
-ErrorStatus RTC_WaitForSynchro(void)
-{
- __IO uint32_t synchrocounter = 0;
- ErrorStatus status = ERROR;
- uint32_t synchrostatus = 0x00;
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear RSF flag */
- RTC->ISR &= (uint32_t)RTC_RSF_MASK;
-
- /* Wait the registers to be synchronised */
- do
- {
- synchrostatus = RTC->ISR & RTC_ISR_RSF;
- synchrocounter++;
- } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
-
- if ((RTC->ISR & RTC_ISR_RSF) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return (status);
-}
-
-/**
- * @brief Enables or disables the RTC reference clock detection.
- * @param NewState: new state of the RTC reference clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC reference clock detection is enabled
- * - ERROR: RTC reference clock detection is disabled
- */
-ErrorStatus RTC_RefClockCmd(FunctionalState NewState)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- if (NewState != DISABLE)
- {
- /* Enable the RTC reference clock detection */
- RTC->CR |= RTC_CR_REFCKON;
- }
- else
- {
- /* Disable the RTC reference clock detection */
- RTC->CR &= ~RTC_CR_REFCKON;
- }
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- status = SUCCESS;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Enables or Disables the Bypass Shadow feature.
- * @note When the Bypass Shadow is enabled the calendar value are taken
- * directly from the Calendar counter.
- * @param NewState: new state of the Bypass Shadow feature.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
-*/
-void RTC_BypassShadowCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Set the BYPSHAD bit */
- RTC->CR |= (uint8_t)RTC_CR_BYPSHAD;
- }
- else
- {
- /* Reset the BYPSHAD bit */
- RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group2 Time and Date configuration functions
- * @brief Time and Date configuration functions
- *
-@verbatim
- ===============================================================================
- Time and Date configuration functions
- ===============================================================================
-
- This section provide functions allowing to program and read the RTC Calendar
- (Time and Date).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set the RTC current time.
- * @param RTC_Format: specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains
- * the time configuration information for the RTC.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Time register is configured
- * - ERROR: RTC Time register is not configured
- */
-ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
-{
- uint32_t tmpreg = 0;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- if (RTC_Format == RTC_Format_BIN)
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));
- assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
- }
- else
- {
- RTC_TimeStruct->RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));
- }
- assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));
- assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));
- }
- else
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
- assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
- }
- else
- {
- RTC_TimeStruct->RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
- }
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));
- }
-
- /* Check the input parameters format */
- if (RTC_Format != RTC_Format_BIN)
- {
- tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \
- ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \
- ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \
- ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16));
- }
- else
- {
- tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \
- (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Set the RTC_TR register */
- RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
-
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- if(RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
-
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Fills each RTC_TimeStruct member with its default value
- * (Time = 00h:00min:00sec).
- * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be
- * initialized.
- * @retval None
- */
-void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)
-{
- /* Time = 00h:00min:00sec */
- RTC_TimeStruct->RTC_H12 = RTC_H12_AM;
- RTC_TimeStruct->RTC_Hours = 0;
- RTC_TimeStruct->RTC_Minutes = 0;
- RTC_TimeStruct->RTC_Seconds = 0;
-}
-
-/**
- * @brief Get the RTC current Time.
- * @param RTC_Format: specifies the format of the returned parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will
- * contain the returned current time configuration.
- * @retval None
- */
-void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- /* Get the RTC_TR register */
- tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK);
-
- /* Fill the structure fields with the read parameters */
- RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
- RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
- RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
- RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
-
- /* Check the input parameters format */
- if (RTC_Format == RTC_Format_BIN)
- {
- /* Convert the structure parameters to Binary format */
- RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
- RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);
- RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds);
- }
-}
-
-/**
- * @brief Gets the RTC current Calendar Subseconds value.
- * @note This function freeze the Time and Date registers after reading the
- * SSR register.
- * @param None
- * @retval RTC current Calendar Subseconds value.
- */
-uint32_t RTC_GetSubSecond(void)
-{
- uint32_t tmpreg = 0;
-
- /* Get subseconds values from the correspondent registers*/
- tmpreg = (uint32_t)(RTC->SSR);
-
- /* Read DR register to unfroze calendar registers */
- (void) (RTC->DR);
-
- return (tmpreg);
-}
-
-/**
- * @brief Set the RTC current date.
- * @param RTC_Format: specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
- * the date configuration information for the RTC.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Date register is configured
- * - ERROR: RTC Date register is not configured
- */
-ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
-{
- uint32_t tmpreg = 0;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))
- {
- RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;
- }
- if (RTC_Format == RTC_Format_BIN)
- {
- assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));
- assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));
- assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));
- }
- else
- {
- assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));
- tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
- assert_param(IS_RTC_MONTH(tmpreg));
- tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
- assert_param(IS_RTC_DATE(tmpreg));
- }
- assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));
-
- /* Check the input parameters format */
- if (RTC_Format != RTC_Format_BIN)
- {
- tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \
- (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \
- ((uint32_t)RTC_DateStruct->RTC_Date) | \
- (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13));
- }
- else
- {
- tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \
- ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Set the RTC_DR register */
- RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);
-
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- if(RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Fills each RTC_DateStruct member with its default value
- * (Monday, January 01 xx00).
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be
- * initialized.
- * @retval None
- */
-void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)
-{
- /* Monday, January 01 xx00 */
- RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;
- RTC_DateStruct->RTC_Date = 1;
- RTC_DateStruct->RTC_Month = RTC_Month_January;
- RTC_DateStruct->RTC_Year = 0;
-}
-
-/**
- * @brief Get the RTC current date.
- * @param RTC_Format: specifies the format of the returned parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will
- * contain the returned current date configuration.
- * @retval None
- */
-void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- /* Get the RTC_TR register */
- tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK);
-
- /* Fill the structure fields with the read parameters */
- RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
- RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
- RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));
- RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13);
-
- /* Check the input parameters format */
- if (RTC_Format == RTC_Format_BIN)
- {
- /* Convert the structure parameters to Binary format */
- RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);
- RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
- RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
- RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group3 Alarms configuration functions
- * @brief Alarms (Alarm A and Alarm B) configuration functions
- *
-@verbatim
- ===============================================================================
- Alarms (Alarm A and Alarm B) configuration functions
- ===============================================================================
-
- This section provide functions allowing to program and read the RTC Alarms.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set the specified RTC Alarm.
- * @note The Alarm register can only be written when the corresponding Alarm
- * is disabled (Use the RTC_AlarmCmd(DISABLE)).
- * @param RTC_Format: specifies the format of the returned parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_Alarm: specifies the alarm to be configured.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @arg RTC_Alarm_B: to select Alarm B
- * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that
- * contains the alarm configuration parameters.
- * @retval None
- */
-void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
- assert_param(IS_RTC_ALARM(RTC_Alarm));
- assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));
-
- if (RTC_Format == RTC_Format_BIN)
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
- assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
- }
- else
- {
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
- }
- assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));
- assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));
-
- if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
- }
- else
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
- }
- }
- else
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
- assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
- }
- else
- {
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
- }
-
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));
-
- if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
- {
- tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
- }
- else
- {
- tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
- }
- }
-
- /* Check the input parameters format */
- if (RTC_Format != RTC_Format_BIN)
- {
- tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask));
- }
- else
- {
- tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask));
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Alarm register */
- if (RTC_Alarm == RTC_Alarm_A)
- {
- RTC->ALRMAR = (uint32_t)tmpreg;
- }
- else
- {
- RTC->ALRMBR = (uint32_t)tmpreg;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Fills each RTC_AlarmStruct member with its default value
- * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
- * all fields are masked).
- * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)
-{
- /* Alarm Time Settings : Time = 00h:00mn:00sec */
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;
-
- /* Alarm Date Settings : Date = 1st day of the month */
- RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;
- RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;
-
- /* Alarm Masks Settings : Mask = all fields are not masked */
- RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;
-}
-
-/**
- * @brief Get the RTC Alarm value and masks.
- * @param RTC_Format: specifies the format of the output parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_Alarm: specifies the alarm to be read.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @arg RTC_Alarm_B: to select Alarm B
- * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will
- * contains the output alarm configuration values.
- * @retval None
- */
-void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
- assert_param(IS_RTC_ALARM(RTC_Alarm));
-
- /* Get the RTC_ALRMxR register */
- if (RTC_Alarm == RTC_Alarm_A)
- {
- tmpreg = (uint32_t)(RTC->ALRMAR);
- }
- else
- {
- tmpreg = (uint32_t)(RTC->ALRMBR);
- }
-
- /* Fill the structure with the read parameters */
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \
- RTC_ALRMAR_HU)) >> 16);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \
- RTC_ALRMAR_MNU)) >> 8);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \
- RTC_ALRMAR_SU));
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
- RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
- RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
- RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);
-
- if (RTC_Format == RTC_Format_BIN)
- {
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
- RTC_AlarmTime.RTC_Hours);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
- RTC_AlarmTime.RTC_Minutes);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
- RTC_AlarmTime.RTC_Seconds);
- RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
- }
-}
-
-/**
- * @brief Enables or disables the specified RTC Alarm.
- * @param RTC_Alarm: specifies the alarm to be configured.
- * This parameter can be any combination of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @arg RTC_Alarm_B: to select Alarm B
- * @param NewState: new state of the specified alarm.
- * This parameter can be: ENABLE or DISABLE.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Alarm is enabled/disabled
- * - ERROR: RTC Alarm is not enabled/disabled
- */
-ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)
-{
- __IO uint32_t alarmcounter = 0x00;
- uint32_t alarmstatus = 0x00;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Alarm state */
- if (NewState != DISABLE)
- {
- RTC->CR |= (uint32_t)RTC_Alarm;
-
- status = SUCCESS;
- }
- else
- {
- /* Disable the Alarm in RTC_CR register */
- RTC->CR &= (uint32_t)~RTC_Alarm;
-
- /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
- do
- {
- alarmstatus = RTC->ISR & (RTC_Alarm >> 8);
- alarmcounter++;
- } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
-
- if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Configure the RTC AlarmA/B Subseconds value and mask.*
- * @note This function is performed only when the Alarm is disabled.
- * @param RTC_Alarm: specifies the alarm to be configured.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @arg RTC_Alarm_B: to select Alarm B
- * @param RTC_AlarmSubSecondValue: specifies the Subseconds value.
- * This parameter can be a value from 0 to 0x00007FFF.
- * @param RTC_AlarmSubSecondMask: specifies the Subseconds Mask.
- * This parameter can be any combination of the following values:
- * @arg RTC_AlarmSubSecondMask_All : All Alarm SS fields are masked.
- * There is no comparison on sub seconds for Alarm.
- * @arg RTC_AlarmSubSecondMask_SS14_1 : SS[14:1] are don't care in Alarm comparison.
- * Only SS[0] is compared
- * @arg RTC_AlarmSubSecondMask_SS14_2 : SS[14:2] are don't care in Alarm comparison.
- * Only SS[1:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_3 : SS[14:3] are don't care in Alarm comparison.
- * Only SS[2:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_4 : SS[14:4] are don't care in Alarm comparison.
- * Only SS[3:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_5 : SS[14:5] are don't care in Alarm comparison.
- * Only SS[4:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_6 : SS[14:6] are don't care in Alarm comparison.
- * Only SS[5:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_7 : SS[14:7] are don't care in Alarm comparison.
- * Only SS[6:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_8 : SS[14:8] are don't care in Alarm comparison.
- * Only SS[7:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_9 : SS[14:9] are don't care in Alarm comparison.
- * Only SS[8:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison.
- * Only SS[9:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison.
- * Only SS[10:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison.
- * Only SS[11:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison.
- * Only SS[12:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14 : SS[14] is don't care in Alarm comparison.
- * Only SS[13:0] are compared
- * @arg RTC_AlarmSubSecondMask_None : SS[14:0] are compared and must match
- * to activate alarm
- * @retval None
- */
-void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_ALARM(RTC_Alarm));
- assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
- assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Alarm A or Alarm B SubSecond registers */
- tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask);
-
- if (RTC_Alarm == RTC_Alarm_A)
- {
- /* Configure the AlarmA SubSecond register */
- RTC->ALRMASSR = tmpreg;
- }
- else
- {
- /* Configure the Alarm B SubSecond register */
- RTC->ALRMBSSR = tmpreg;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
-}
-
-/**
- * @brief Gets the RTC Alarm Subseconds value.
- * @param RTC_Alarm: specifies the alarm to be read.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @arg RTC_Alarm_B: to select Alarm B
- * @param None
- * @retval RTC Alarm Subseconds value.
- */
-uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
-{
- uint32_t tmpreg = 0;
-
- /* Get the RTC_ALRMxR register */
- if (RTC_Alarm == RTC_Alarm_A)
- {
- tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS);
- }
- else
- {
- tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS);
- }
-
- return (tmpreg);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group4 WakeUp Timer configuration functions
- * @brief WakeUp Timer configuration functions
- *
-@verbatim
- ===============================================================================
- WakeUp Timer configuration functions
- ===============================================================================
-
- This section provide functions allowing to program and read the RTC WakeUp.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC Wakeup clock source.
- * @note The WakeUp Clock source can only be changed when the RTC WakeUp
- * is disabled (Use the RTC_WakeUpCmd(DISABLE)).
- * @param RTC_WakeUpClock: Wakeup Clock source.
- * This parameter can be one of the following values:
- * @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16
- * @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8
- * @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4
- * @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2
- * @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE
- * @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE
- * @retval None
- */
-void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)
-{
- /* Check the parameters */
- assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear the Wakeup Timer clock source bits in CR register */
- RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
- /* Configure the clock source */
- RTC->CR |= (uint32_t)RTC_WakeUpClock;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Configures the RTC Wakeup counter.
- * @note The RTC WakeUp counter can only be written when the RTC WakeUp
- * is disabled (Use the RTC_WakeUpCmd(DISABLE)).
- * @param RTC_WakeUpCounter: specifies the WakeUp counter.
- * This parameter can be a value from 0x0000 to 0xFFFF.
- * @retval None
- */
-void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
-{
- /* Check the parameters */
- assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Wakeup Timer counter */
- RTC->WUTR = (uint32_t)RTC_WakeUpCounter;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Returns the RTC WakeUp timer counter value.
- * @param None
- * @retval The RTC WakeUp Counter value.
- */
-uint32_t RTC_GetWakeUpCounter(void)
-{
- /* Get the counter value */
- return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT));
-}
-
-/**
- * @brief Enables or Disables the RTC WakeUp timer.
- * @param NewState: new state of the WakeUp timer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)
-{
- __IO uint32_t wutcounter = 0x00;
- uint32_t wutwfstatus = 0x00;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Enable the Wakeup Timer */
- RTC->CR |= (uint32_t)RTC_CR_WUTE;
- status = SUCCESS;
- }
- else
- {
- /* Disable the Wakeup Timer */
- RTC->CR &= (uint32_t)~RTC_CR_WUTE;
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- do
- {
- wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
- wutcounter++;
- } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
-
- if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group5 Daylight Saving configuration functions
- * @brief Daylight Saving configuration functions
- *
-@verbatim
- ===============================================================================
- Daylight Saving configuration functions
- ===============================================================================
-
- This section provide functions allowing to configure the RTC DayLight Saving.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Adds or substract one hour from the current time.
- * @param RTC_DayLightSaveOperation: the value of hour adjustment.
- * This parameter can be one of the following values:
- * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)
- * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)
- * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit
- * in CR register to store the operation.
- * This parameter can be one of the following values:
- * @arg RTC_StoreOperation_Reset: BCK Bit Reset
- * @arg RTC_StoreOperation_Set: BCK Bit Set
- * @retval None
- */
-void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
-{
- /* Check the parameters */
- assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
- assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear the bits to be configured */
- RTC->CR &= (uint32_t)~(RTC_CR_BCK);
-
- /* Configure the RTC_CR register */
- RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Returns the RTC Day Light Saving stored operation.
- * @param None
- * @retval RTC Day Light Saving stored operation.
- * - RTC_StoreOperation_Reset
- * - RTC_StoreOperation_Set
- */
-uint32_t RTC_GetStoreOperation(void)
-{
- return (RTC->CR & RTC_CR_BCK);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group6 Output pin Configuration function
- * @brief Output pin Configuration function
- *
-@verbatim
- ===============================================================================
- Output pin Configuration function
- ===============================================================================
-
- This section provide functions allowing to configure the RTC Output source.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC output source (AFO_ALARM).
- * @param RTC_Output: Specifies which signal will be routed to the RTC output.
- * This parameter can be one of the following values:
- * @arg RTC_Output_Disable: No output selected
- * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output
- * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output
- * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output
- * @param RTC_OutputPolarity: Specifies the polarity of the output signal.
- * This parameter can be one of the following:
- * @arg RTC_OutputPolarity_High: The output pin is high when the
- * ALRAF/ALRBF/WUTF is high (depending on OSEL)
- * @arg RTC_OutputPolarity_Low: The output pin is low when the
- * ALRAF/ALRBF/WUTF is high (depending on OSEL)
- * @retval None
- */
-void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
-{
- /* Check the parameters */
- assert_param(IS_RTC_OUTPUT(RTC_Output));
- assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear the bits to be configured */
- RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);
-
- /* Configure the output selection and polarity */
- RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group7 Digital Calibration configuration functions
- * @brief Coarse Calibration configuration functions
- *
-@verbatim
- ===============================================================================
- Digital Calibration configuration functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the Coarse calibration parameters.
- * @param RTC_CalibSign: specifies the sign of the coarse calibration value.
- * This parameter can be one of the following values:
- * @arg RTC_CalibSign_Positive: The value sign is positive
- * @arg RTC_CalibSign_Negative: The value sign is negative
- * @param Value: value of coarse calibration expressed in ppm (coded on 5 bits).
- *
- * @note This Calibration value should be between 0 and 63 when using negative
- * sign with a 2-ppm step.
- *
- * @note This Calibration value should be between 0 and 126 when using positive
- * sign with a 4-ppm step.
- *
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Coarse calibration are initialized
- * - ERROR: RTC Coarse calibration are not initialized
- */
-ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign));
- assert_param(IS_RTC_CALIB_VALUE(Value));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Set the coarse calibration value */
- RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value);
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- status = SUCCESS;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Enables or disables the Coarse calibration process.
- * @param NewState: new state of the Coarse calibration.
- * This parameter can be: ENABLE or DISABLE.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Coarse calibration are enabled/disabled
- * - ERROR: RTC Coarse calibration are not enabled/disabled
- */
-ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- if (NewState != DISABLE)
- {
- /* Enable the Coarse Calibration */
- RTC->CR |= (uint32_t)RTC_CR_DCE;
- }
- else
- {
- /* Disable the Coarse Calibration */
- RTC->CR &= (uint32_t)~RTC_CR_DCE;
- }
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- status = SUCCESS;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Enables or disables the RTC clock to be output through the relative pin.
- * @param NewState: new state of the digital calibration Output.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_CalibOutputCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Enable the RTC clock output */
- RTC->CR |= (uint32_t)RTC_CR_COE;
- }
- else
- {
- /* Disable the RTC clock output */
- RTC->CR &= (uint32_t)~RTC_CR_COE;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param RTC_CalibOutput : Select the Calibration output Selection .
- * This parameter can be one of the following values:
- * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz.
- * @arg RTC_CalibOutput_1Hz : A signal has a regular waveform at 1Hz.
- * @retval None
-*/
-void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /*clear flags before config*/
- RTC->CR &= (uint32_t)~(RTC_CR_COSEL);
-
- /* Configure the RTC_CR register */
- RTC->CR |= (uint32_t)RTC_CalibOutput;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Configures the Smooth Calibration Settings.
- * @param RTC_SmoothCalibPeriod : Select the Smooth Calibration Period.
- * This parameter can be can be one of the following values:
- * @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration periode is 32s.
- * @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration periode is 16s.
- * @arg RTC_SmoothCalibPeriod_8sec : The smooth calibartion periode is 8s.
- * @param RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit.
- * This parameter can be one of the following values:
- * @arg RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK puls every 2**11 pulses.
- * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
- * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
- * This parameter can be one any value from 0 to 0x000001FF.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Calib registers are configured
- * - ERROR: RTC Calib registers are not configured
-*/
-ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
- uint32_t RTC_SmoothCalibPlusPulses,
- uint32_t RTC_SmouthCalibMinusPulsesValue)
-{
- ErrorStatus status = ERROR;
- uint32_t recalpfcount = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));
- assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
- assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* check if a calibration is pending*/
- if ((RTC->ISR & RTC_ISR_RECALPF) != RESET)
- {
- /* wait until the Calibration is completed*/
- while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
- {
- recalpfcount++;
- }
- }
-
- /* check if the calibration pending is completed or if there is no calibration operation at all*/
- if ((RTC->ISR & RTC_ISR_RECALPF) == RESET)
- {
- /* Configure the Smooth calibration settings */
- RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
-
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return (ErrorStatus)(status);
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Group8 TimeStamp configuration functions
- * @brief TimeStamp configuration functions
- *
-@verbatim
- ===============================================================================
- TimeStamp configuration functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or Disables the RTC TimeStamp functionality with the
- * specified time stamp pin stimulating edge.
- * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is
- * activated.
- * This parameter can be one of the following:
- * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising
- * edge of the related pin.
- * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the
- * falling edge of the related pin.
- * @param NewState: new state of the TimeStamp.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Get the RTC_CR register and clear the bits to be configured */
- tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
- /* Get the new configuration */
- if (NewState != DISABLE)
- {
- tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);
- }
- else
- {
- tmpreg |= (uint32_t)(RTC_TimeStampEdge);
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Time Stamp TSEDGE and Enable bits */
- RTC->CR = (uint32_t)tmpreg;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Get the RTC TimeStamp value and masks.
- * @param RTC_Format: specifies the format of the output parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will
- * contains the TimeStamp time values.
- * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will
- * contains the TimeStamp date values.
- * @retval None
- */
-void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
- RTC_DateTypeDef* RTC_StampDateStruct)
-{
- uint32_t tmptime = 0, tmpdate = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- /* Get the TimeStamp time and date registers values */
- tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);
- tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);
-
- /* Fill the Time structure fields with the read parameters */
- RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
- RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
- RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
- RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
-
- /* Fill the Date structure fields with the read parameters */
- RTC_StampDateStruct->RTC_Year = 0;
- RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
- RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
- RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
-
- /* Check the input parameters format */
- if (RTC_Format == RTC_Format_BIN)
- {
- /* Convert the Time structure parameters to Binary format */
- RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);
- RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);
- RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);
-
- /* Convert the Date structure parameters to Binary format */
- RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);
- RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);
- RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);
- }
-}
-
-/**
- * @brief Get the RTC timestamp Subseconds value.
- * @param None
- * @retval RTC current timestamp Subseconds value.
- */
-uint32_t RTC_GetTimeStampSubSecond(void)
-{
- /* Get timestamp subseconds values from the correspondent registers */
- return (uint32_t)(RTC->TSSSR);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group9 Tampers configuration functions
- * @brief Tampers configuration functions
- *
-@verbatim
- ===============================================================================
- Tampers configuration functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the select Tamper pin edge.
- * @param RTC_Tamper: Selected tamper pin.
- * This parameter can be RTC_Tamper_1.
- * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that
- * stimulates tamper event.
- * This parameter can be one of the following values:
- * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
- * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
- * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
- * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
- * @retval None
- */
-void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER(RTC_Tamper));
- assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
-
- if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)
- {
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1));
- }
- else
- {
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1);
- }
-}
-
-/**
- * @brief Enables or Disables the Tamper detection.
- * @param RTC_Tamper: Selected tamper pin.
- * This parameter can be RTC_Tamper_1.
- * @param NewState: new state of the tamper pin.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER(RTC_Tamper));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected Tamper pin */
- RTC->TAFCR |= (uint32_t)RTC_Tamper;
- }
- else
- {
- /* Disable the selected Tamper pin */
- RTC->TAFCR &= (uint32_t)~RTC_Tamper;
- }
-}
-
-/**
- * @brief Configures the Tampers Filter.
- * @param RTC_TamperFilter: Specifies the tampers filter.
- * This parameter can be one of the following values:
- * @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
- * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive
- * samples at the active level
- * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive
- * samples at the active level
- * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive
- * samples at the active level
- * @retval None
- */
-void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
-
- /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT);
-
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)RTC_TamperFilter;
-}
-
-/**
- * @brief Configures the Tampers Sampling Frequency.
- * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
- * This parameter can be one of the following values:
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 32768
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 16384
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 8192
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 4096
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 2048
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 1024
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 512
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 256
- * @retval None
- */
-void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
-
- /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ);
-
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq;
-}
-
-/**
- * @brief Configures the Tampers Pins input Precharge Duration.
- * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
- * Precharge Duration.
- * This parameter can be one of the following values:
- * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle
- * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle
- * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle
- * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle
- * @retval None
- */
-void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
-
- /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH);
-
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration;
-}
-
-/**
- * @brief Enables or Disables the TimeStamp on Tamper Detection Event.
- * @note The timestamp is valid even the TSE bit in tamper control register
- * is reset.
- * @param NewState: new state of the timestamp on tamper event.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Save timestamp on tamper detection event */
- RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS;
- }
- else
- {
- /* Tamper detection does not cause a timestamp to be saved */
- RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS;
- }
-}
-
-/**
- * @brief Enables or Disables the Precharge of Tamper pin.
- * @param NewState: new state of tamper pull up.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TamperPullUpCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable precharge of the selected Tamper pin */
- RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS;
- }
- else
- {
- /* Disable precharge of the selected Tamper pin */
- RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group10 Backup Data Registers configuration functions
- * @brief Backup Data Registers configuration functions
- *
-@verbatim
- ===============================================================================
- Backup Data Registers configuration functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes a data in a specified RTC Backup data register.
- * @param RTC_BKP_DR: RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
- * specify the register.
- * @param Data: Data to be written in the specified RTC Backup data register.
- * @retval None
- */
-void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_BKP(RTC_BKP_DR));
-
- tmp = RTC_BASE + 0x50;
- tmp += (RTC_BKP_DR * 4);
-
- /* Write the specified register */
- *(__IO uint32_t *)tmp = (uint32_t)Data;
-}
-
-/**
- * @brief Reads data from the specified RTC Backup data Register.
- * @param RTC_BKP_DR: RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
- * specify the register.
- * @retval None
- */
-uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_BKP(RTC_BKP_DR));
-
- tmp = RTC_BASE + 0x50;
- tmp += (RTC_BKP_DR * 4);
-
- /* Read the specified register */
- return (*(__IO uint32_t *)tmp);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group11 RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions
- * @brief RTC Tamper and TimeStamp Pins Selection and Output Type Config
- * configuration functions
- *
-@verbatim
- ===============================================================================
- RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
- functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Selects the RTC Tamper Pin.
- * @param RTC_TamperPin: specifies the RTC Tamper Pin.
- * This parameter can be one of the following values:
- * @arg RTC_TamperPin_PC13: PC13 is selected as RTC Tamper Pin.
- * @arg RTC_TamperPin_PI8: PI8 is selected as RTC Tamper Pin.
- * @retval None
- */
-void RTC_TamperPinSelection(uint32_t RTC_TamperPin)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER_PIN(RTC_TamperPin));
-
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPINSEL);
- RTC->TAFCR |= (uint32_t)(RTC_TamperPin);
-}
-
-/**
- * @brief Selects the RTC TimeStamp Pin.
- * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
- * This parameter can be one of the following values:
- * @arg RTC_TimeStampPin_PC13: PC13 is selected as RTC TimeStamp Pin.
- * @arg RTC_TimeStampPin_PI8: PI8 is selected as RTC TimeStamp Pin.
- * @retval None
- */
-void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
-
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TSINSEL);
- RTC->TAFCR |= (uint32_t)(RTC_TimeStampPin);
-}
-
-/**
- * @brief Configures the RTC Output Pin mode.
- * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode.
- * This parameter can be one of the following values:
- * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in
- * Open Drain mode.
- * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in
- * Push Pull mode.
- * @retval None
- */
-void RTC_OutputTypeConfig(uint32_t RTC_OutputType)
-{
- /* Check the parameters */
- assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
-
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);
- RTC->TAFCR |= (uint32_t)(RTC_OutputType);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group12 Shift control synchronisation functions
- * @brief Shift control synchronisation functions
- *
-@verbatim
- ===============================================================================
- Shift control synchronisation functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the Synchronization Shift Control Settings.
- * @note When REFCKON is set, firmware must not write to Shift control register
- * @param RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar.
- * This parameter can be one of the following values :
- * @arg RTC_ShiftAdd1S_Set : Add one second to the clock calendar.
- * @arg RTC_ShiftAdd1S_Reset: No effect.
- * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.
- * This parameter can be one any value from 0 to 0x7FFF.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Shift registers are configured
- * - ERROR: RTC Shift registers are not configured
-*/
-ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
-{
- ErrorStatus status = ERROR;
- uint32_t shpfcount = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
- assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Check if a Shift is pending*/
- if ((RTC->ISR & RTC_ISR_SHPF) != RESET)
- {
- /* Wait until the shift is completed*/
- while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
- {
- shpfcount++;
- }
- }
-
- /* Check if the Shift pending is completed or if there is no Shift operation at all*/
- if ((RTC->ISR & RTC_ISR_SHPF) == RESET)
- {
- /* check if the reference clock detection is disabled */
- if((RTC->CR & RTC_CR_REFCKON) == RESET)
- {
- /* Configure the Shift settings */
- RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
-
- if(RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
- else
- {
- status = ERROR;
- }
- }
- else
- {
- status = ERROR;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return (ErrorStatus)(status);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group13 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
- All RTC interrupts are connected to the EXTI controller.
-
- - To enable the RTC Alarm interrupt, the following sequence is required:
- - Configure and enable the EXTI Line 17 in interrupt mode and select the rising
- edge sensitivity using the EXTI_Init() function.
- - Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init()
- function.
- - Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using
- the RTC_SetAlarm() and RTC_AlarmCmd() functions.
-
- - To enable the RTC Wakeup interrupt, the following sequence is required:
- - Configure and enable the EXTI Line 22 in interrupt mode and select the rising
- edge sensitivity using the EXTI_Init() function.
- - Configure and enable the RTC_WKUP IRQ channel in the NVIC using the NVIC_Init()
- function.
- - Configure the RTC to generate the RTC wakeup timer event using the
- RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
-
- - To enable the RTC Tamper interrupt, the following sequence is required:
- - Configure and enable the EXTI Line 21 in interrupt mode and select the rising
- edge sensitivity using the EXTI_Init() function.
- - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()
- function.
- - Configure the RTC to detect the RTC tamper event using the
- RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
-
- - To enable the RTC TimeStamp interrupt, the following sequence is required:
- - Configure and enable the EXTI Line 21 in interrupt mode and select the rising
- edge sensitivity using the EXTI_Init() function.
- - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()
- function.
- - Configure the RTC to detect the RTC time-stamp event using the
- RTC_TimeStampCmd() functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified RTC interrupts.
- * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_TS: Time Stamp interrupt mask
- * @arg RTC_IT_WUT: WakeUp Timer interrupt mask
- * @arg RTC_IT_ALRB: Alarm B interrupt mask
- * @arg RTC_IT_ALRA: Alarm A interrupt mask
- * @arg RTC_IT_TAMP: Tamper event interrupt mask
- * @param NewState: new state of the specified RTC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CONFIG_IT(RTC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Configure the Interrupts in the RTC_CR register */
- RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);
- /* Configure the Tamper Interrupt in the RTC_TAFCR */
- RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);
- }
- else
- {
- /* Configure the Interrupts in the RTC_CR register */
- RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);
- /* Configure the Tamper Interrupt in the RTC_TAFCR */
- RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Checks whether the specified RTC flag is set or not.
- * @param RTC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
- * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag
- * @arg RTC_FLAG_TSF: Time Stamp event flag
- * @arg RTC_FLAG_WUTF: WakeUp Timer flag
- * @arg RTC_FLAG_ALRBF: Alarm B flag
- * @arg RTC_FLAG_ALRAF: Alarm A flag
- * @arg RTC_FLAG_INITF: Initialization mode flag
- * @arg RTC_FLAG_RSF: Registers Synchronized flag
- * @arg RTC_FLAG_INITS: Registers Configured flag
- * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag
- * @arg RTC_FLAG_ALRBWF: Alarm B Write flag
- * @arg RTC_FLAG_ALRAWF: Alarm A write flag
- * @retval The new state of RTC_FLAG (SET or RESET).
- */
-FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
-
- /* Get all the flags */
- tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);
-
- /* Return the status of the flag */
- if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the RTC's pending flags.
- * @param RTC_FLAG: specifies the RTC flag to clear.
- * This parameter can be any combination of the following values:
- * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
- * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag
- * @arg RTC_FLAG_TSF: Time Stamp event flag
- * @arg RTC_FLAG_WUTF: WakeUp Timer flag
- * @arg RTC_FLAG_ALRBF: Alarm B flag
- * @arg RTC_FLAG_ALRAF: Alarm A flag
- * @arg RTC_FLAG_RSF: Registers Synchronized flag
- * @retval None
- */
-void RTC_ClearFlag(uint32_t RTC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
-
- /* Clear the Flags in the RTC_ISR register */
- RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @brief Checks whether the specified RTC interrupt has occurred or not.
- * @param RTC_IT: specifies the RTC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RTC_IT_TS: Time Stamp interrupt
- * @arg RTC_IT_WUT: WakeUp Timer interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_TAMP1: Tamper 1 event interrupt
- * @retval The new state of RTC_IT (SET or RESET).
- */
-ITStatus RTC_GetITStatus(uint32_t RTC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t tmpreg = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_GET_IT(RTC_IT));
-
- /* Get the TAMPER Interrupt enable bit and pending bit */
- tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));
-
- /* Get the Interrupt enable Status */
- enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15)));
-
- /* Get the Interrupt pending bit */
- tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));
-
- /* Get the status of the Interrupt */
- if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the RTC's interrupt pending bits.
- * @param RTC_IT: specifies the RTC interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_TS: Time Stamp interrupt
- * @arg RTC_IT_WUT: WakeUp Timer interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_TAMP1: Tamper 1 event interrupt
- * @retval None
- */
-void RTC_ClearITPendingBit(uint32_t RTC_IT)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_CLEAR_IT(RTC_IT));
-
- /* Get the RTC_ISR Interrupt pending bits mask */
- tmpreg = (uint32_t)(RTC_IT >> 4);
-
- /* Clear the interrupt pending bits in the RTC_ISR register */
- RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @}
- */
-
-/**
- * @brief Converts a 2 digit decimal to BCD format.
- * @param Value: Byte to be converted.
- * @retval Converted byte
- */
-static uint8_t RTC_ByteToBcd2(uint8_t Value)
-{
- uint8_t bcdhigh = 0;
-
- while (Value >= 10)
- {
- bcdhigh++;
- Value -= 10;
- }
-
- return ((uint8_t)(bcdhigh << 4) | Value);
-}
-
-/**
- * @brief Convert from 2 digit BCD to Binary.
- * @param Value: BCD value to be converted.
- * @retval Converted word
- */
-static uint8_t RTC_Bcd2ToByte(uint8_t Value)
-{
- uint8_t tmp = 0;
- tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
- return (tmp + (Value & (uint8_t)0x0F));
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_sdio.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Secure digital input/output interface (SDIO)
- * peripheral:
- * - Initialization and Configuration
- * - Command path state machine (CPSM) management
- * - Data path state machine (DPSM) management
- * - SDIO IO Cards mode management
- * - CE-ATA mode management
- * - DMA transfers management
- * - Interrupts and flags management
- *
- * @verbatim
- *
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * 1. The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output
- * of PLL (PLL48CLK). Before to start working with SDIO peripheral
- * make sure that the PLL is well configured.
- * The SDIO peripheral uses two clock signals:
- * - SDIO adapter clock (SDIOCLK = 48 MHz)
- * - APB2 bus clock (PCLK2)
- * PCLK2 and SDIO_CK clock frequencies must respect the following condition:
- * Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
- *
- * 2. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE).
- *
- * 3. According to the SDIO mode, enable the GPIO clocks using
- * RCC_AHB1PeriphClockCmd() function.
- * The I/O can be one of the following configurations:
- * - 1-bit data length: SDIO_CMD, SDIO_CK and D0.
- * - 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0].
- * - 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0].
- *
- * 4. Peripheral's alternate function:
- * - Connect the pin to the desired peripherals' Alternate
- * Function (AF) using GPIO_PinAFConfig() function
- * - Configure the desired pin in alternate function by:
- * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- * - Select the type, pull-up/pull-down and output speed via
- * GPIO_PuPd, GPIO_OType and GPIO_Speed members
- * - Call GPIO_Init() function
- *
- * 5. Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide,
- * hardware, flow control and the Clock Divider using the SDIO_Init()
- * function.
- *
- * 6. Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON)
- * function.
- *
- * 7. Enable the clock using the SDIO_ClockCmd() function.
- *
- * 8. Enable the NVIC and the corresponding interrupt using the function
- * SDIO_ITConfig() if you need to use interrupt mode.
- *
- * 9. When using the DMA mode
- * - Configure the DMA using DMA_Init() function
- * - Active the needed channel Request using SDIO_DMACmd() function
- *
- * 10. Enable the DMA using the DMA_Cmd() function, when using DMA mode.
- *
- * 11. To control the CPSM (Command Path State Machine) and send
- * commands to the card use the SDIO_SendCommand(),
- * SDIO_GetCommandResponse() and SDIO_GetResponse() functions.
- * First, user has to fill the command structure (pointer to
- * SDIO_CmdInitTypeDef) according to the selected command to be sent.
- * The parameters that should be filled are:
- * - Command Argument
- * - Command Index
- * - Command Response type
- * - Command Wait
- * - CPSM Status (Enable or Disable)
- *
- * To check if the command is well received, read the SDIO_CMDRESP
- * register using the SDIO_GetCommandResponse().
- * The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
- * SDIO_GetResponse() function.
- *
- * 12. To control the DPSM (Data Path State Machine) and send/receive
- * data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
- * SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions.
- *
- * Read Operations
- * ---------------
- * a) First, user has to fill the data structure (pointer to
- * SDIO_DataInitTypeDef) according to the selected data type to
- * be received.
- * The parameters that should be filled are:
- * - Data TimeOut
- * - Data Length
- * - Data Block size
- * - Data Transfer direction: should be from card (To SDIO)
- * - Data Transfer mode
- * - DPSM Status (Enable or Disable)
- *
- * b) Configure the SDIO resources to receive the data from the card
- * according to selected transfer mode (Refer to Step 8, 9 and 10).
- *
- * c) Send the selected Read command (refer to step 11).
- *
- * d) Use the SDIO flags/interrupts to check the transfer status.
- *
- * Write Operations
- * ---------------
- * a) First, user has to fill the data structure (pointer to
- * SDIO_DataInitTypeDef) according to the selected data type to
- * be received.
- * The parameters that should be filled are:
- * - Data TimeOut
- * - Data Length
- * - Data Block size
- * - Data Transfer direction: should be to card (To CARD)
- * - Data Transfer mode
- * - DPSM Status (Enable or Disable)
- *
- * b) Configure the SDIO resources to send the data to the card
- * according to selected transfer mode (Refer to Step 8, 9 and 10).
- *
- * c) Send the selected Write command (refer to step 11).
- *
- * d) Use the SDIO flags/interrupts to check the transfer status.
- *
- *
- * @endverbatim
- *
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_sdio.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SDIO
- * @brief SDIO driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ------------ SDIO registers bit address in the alias region ----------- */
-#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
-
-/* --- CLKCR Register ---*/
-/* Alias word address of CLKEN bit */
-#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
-#define CLKEN_BitNumber 0x08
-#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
-
-/* --- CMD Register ---*/
-/* Alias word address of SDIOSUSPEND bit */
-#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
-#define SDIOSUSPEND_BitNumber 0x0B
-#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
-
-/* Alias word address of ENCMDCOMPL bit */
-#define ENCMDCOMPL_BitNumber 0x0C
-#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
-
-/* Alias word address of NIEN bit */
-#define NIEN_BitNumber 0x0D
-#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
-
-/* Alias word address of ATACMD bit */
-#define ATACMD_BitNumber 0x0E
-#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
-
-/* --- DCTRL Register ---*/
-/* Alias word address of DMAEN bit */
-#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
-#define DMAEN_BitNumber 0x03
-#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
-
-/* Alias word address of RWSTART bit */
-#define RWSTART_BitNumber 0x08
-#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
-
-/* Alias word address of RWSTOP bit */
-#define RWSTOP_BitNumber 0x09
-#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
-
-/* Alias word address of RWMOD bit */
-#define RWMOD_BitNumber 0x0A
-#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
-
-/* Alias word address of SDIOEN bit */
-#define SDIOEN_BitNumber 0x0B
-#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
-
-/* ---------------------- SDIO registers bit mask ------------------------ */
-/* --- CLKCR Register ---*/
-/* CLKCR register clear mask */
-#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
-
-/* --- PWRCTRL Register ---*/
-/* SDIO PWRCTRL Mask */
-#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
-
-/* --- DCTRL Register ---*/
-/* SDIO DCTRL Clear Mask */
-#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
-
-/* --- CMD Register ---*/
-/* CMD Register clear mask */
-#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
-
-/* SDIO RESP Registers Address */
-#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SDIO_Private_Functions
- * @{
- */
-
-/** @defgroup SDIO_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- Initialization and Configuration functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the SDIO peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void SDIO_DeInit(void)
-{
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE);
-}
-
-/**
- * @brief Initializes the SDIO peripheral according to the specified
- * parameters in the SDIO_InitStruct.
- * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
- * that contains the configuration information for the SDIO peripheral.
- * @retval None
- */
-void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
- assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
- assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
- assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
- assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
-
-/*---------------------------- SDIO CLKCR Configuration ------------------------*/
- /* Get the SDIO CLKCR value */
- tmpreg = SDIO->CLKCR;
-
- /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
- tmpreg &= CLKCR_CLEAR_MASK;
-
- /* Set CLKDIV bits according to SDIO_ClockDiv value */
- /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
- /* Set BYPASS bit according to SDIO_ClockBypass value */
- /* Set WIDBUS bits according to SDIO_BusWide value */
- /* Set NEGEDGE bits according to SDIO_ClockEdge value */
- /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
- tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
- SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
- SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
-
- /* Write to SDIO CLKCR */
- SDIO->CLKCR = tmpreg;
-}
-
-/**
- * @brief Fills each SDIO_InitStruct member with its default value.
- * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
-{
- /* SDIO_InitStruct members default value */
- SDIO_InitStruct->SDIO_ClockDiv = 0x00;
- SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
- SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
- SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
- SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
- SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
-}
-
-/**
- * @brief Enables or disables the SDIO Clock.
- * @param NewState: new state of the SDIO Clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_ClockCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Sets the power status of the controller.
- * @param SDIO_PowerState: new state of the Power state.
- * This parameter can be one of the following values:
- * @arg SDIO_PowerState_OFF: SDIO Power OFF
- * @arg SDIO_PowerState_ON: SDIO Power ON
- * @retval None
- */
-void SDIO_SetPowerState(uint32_t SDIO_PowerState)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
-
- SDIO->POWER = SDIO_PowerState;
-}
-
-/**
- * @brief Gets the power status of the controller.
- * @param None
- * @retval Power status of the controller. The returned value can be one of the
- * following values:
- * - 0x00: Power OFF
- * - 0x02: Power UP
- * - 0x03: Power ON
- */
-uint32_t SDIO_GetPowerState(void)
-{
- return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions
- * @brief Command path state machine (CPSM) management functions
- *
-@verbatim
- ===============================================================================
- Command path state machine (CPSM) management functions
- ===============================================================================
-
- This section provide functions allowing to program and read the Command path
- state machine (CPSM).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the SDIO Command according to the specified
- * parameters in the SDIO_CmdInitStruct and send the command.
- * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
- * structure that contains the configuration information for the SDIO
- * command.
- * @retval None
- */
-void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
- assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
- assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
- assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
-
-/*---------------------------- SDIO ARG Configuration ------------------------*/
- /* Set the SDIO Argument value */
- SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
-
-/*---------------------------- SDIO CMD Configuration ------------------------*/
- /* Get the SDIO CMD value */
- tmpreg = SDIO->CMD;
- /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
- tmpreg &= CMD_CLEAR_MASK;
- /* Set CMDINDEX bits according to SDIO_CmdIndex value */
- /* Set WAITRESP bits according to SDIO_Response value */
- /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
- /* Set CPSMEN bits according to SDIO_CPSM value */
- tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
- | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
-
- /* Write to SDIO CMD */
- SDIO->CMD = tmpreg;
-}
-
-/**
- * @brief Fills each SDIO_CmdInitStruct member with its default value.
- * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
-{
- /* SDIO_CmdInitStruct members default value */
- SDIO_CmdInitStruct->SDIO_Argument = 0x00;
- SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
- SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
- SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
- SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
-}
-
-/**
- * @brief Returns command index of last command for which response received.
- * @param None
- * @retval Returns the command index of the last command response received.
- */
-uint8_t SDIO_GetCommandResponse(void)
-{
- return (uint8_t)(SDIO->RESPCMD);
-}
-
-/**
- * @brief Returns response received from the card for the last command.
- * @param SDIO_RESP: Specifies the SDIO response register.
- * This parameter can be one of the following values:
- * @arg SDIO_RESP1: Response Register 1
- * @arg SDIO_RESP2: Response Register 2
- * @arg SDIO_RESP3: Response Register 3
- * @arg SDIO_RESP4: Response Register 4
- * @retval The Corresponding response register value.
- */
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_RESP(SDIO_RESP));
-
- tmp = SDIO_RESP_ADDR + SDIO_RESP;
-
- return (*(__IO uint32_t *) tmp);
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions
- * @brief Data path state machine (DPSM) management functions
- *
-@verbatim
- ===============================================================================
- Data path state machine (DPSM) management functions
- ===============================================================================
-
- This section provide functions allowing to program and read the Data path
- state machine (DPSM).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the SDIO data path according to the specified
- * parameters in the SDIO_DataInitStruct.
- * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure
- * that contains the configuration information for the SDIO command.
- * @retval None
- */
-void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
- assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
- assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
- assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
- assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
-
-/*---------------------------- SDIO DTIMER Configuration ---------------------*/
- /* Set the SDIO Data TimeOut value */
- SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
-
-/*---------------------------- SDIO DLEN Configuration -----------------------*/
- /* Set the SDIO DataLength value */
- SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
-
-/*---------------------------- SDIO DCTRL Configuration ----------------------*/
- /* Get the SDIO DCTRL value */
- tmpreg = SDIO->DCTRL;
- /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
- tmpreg &= DCTRL_CLEAR_MASK;
- /* Set DEN bit according to SDIO_DPSM value */
- /* Set DTMODE bit according to SDIO_TransferMode value */
- /* Set DTDIR bit according to SDIO_TransferDir value */
- /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
- tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
- | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
-
- /* Write to SDIO DCTRL */
- SDIO->DCTRL = tmpreg;
-}
-
-/**
- * @brief Fills each SDIO_DataInitStruct member with its default value.
- * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
-{
- /* SDIO_DataInitStruct members default value */
- SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
- SDIO_DataInitStruct->SDIO_DataLength = 0x00;
- SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
- SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
- SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
- SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
-}
-
-/**
- * @brief Returns number of remaining data bytes to be transferred.
- * @param None
- * @retval Number of remaining data bytes to be transferred
- */
-uint32_t SDIO_GetDataCounter(void)
-{
- return SDIO->DCOUNT;
-}
-
-/**
- * @brief Read one data word from Rx FIFO.
- * @param None
- * @retval Data received
- */
-uint32_t SDIO_ReadData(void)
-{
- return SDIO->FIFO;
-}
-
-/**
- * @brief Write one data word to Tx FIFO.
- * @param Data: 32-bit data word to write.
- * @retval None
- */
-void SDIO_WriteData(uint32_t Data)
-{
- SDIO->FIFO = Data;
-}
-
-/**
- * @brief Returns the number of words left to be written to or read from FIFO.
- * @param None
- * @retval Remaining number of words.
- */
-uint32_t SDIO_GetFIFOCount(void)
-{
- return SDIO->FIFOCNT;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group4 SDIO IO Cards mode management functions
- * @brief SDIO IO Cards mode management functions
- *
-@verbatim
- ===============================================================================
- SDIO IO Cards mode management functions
- ===============================================================================
-
- This section provide functions allowing to program and read the SDIO IO Cards.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the SD I/O Read Wait operation.
- * @param NewState: new state of the Start SDIO Read Wait operation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_StartSDIOReadWait(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
-}
-
-/**
- * @brief Stops the SD I/O Read Wait operation.
- * @param NewState: new state of the Stop SDIO Read Wait operation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_StopSDIOReadWait(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
-}
-
-/**
- * @brief Sets one of the two options of inserting read wait interval.
- * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
- * This parameter can be:
- * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
- * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
- * @retval None
- */
-void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
-
- *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
-}
-
-/**
- * @brief Enables or disables the SD I/O Mode Operation.
- * @param NewState: new state of SDIO specific operation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_SetSDIOOperation(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the SD I/O Mode suspend command sending.
- * @param NewState: new state of the SD I/O Mode suspend command.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group5 CE-ATA mode management functions
- * @brief CE-ATA mode management functions
- *
-@verbatim
- ===============================================================================
- CE-ATA mode management functions
- ===============================================================================
-
- This section provide functions allowing to program and read the CE-ATA card.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the command completion signal.
- * @param NewState: new state of command completion signal.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_CommandCompletionCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the CE-ATA interrupt.
- * @param NewState: new state of CE-ATA interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_CEATAITCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
-}
-
-/**
- * @brief Sends CE-ATA command (CMD61).
- * @param NewState: new state of CE-ATA command.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_SendCEATACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group6 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- DMA transfers management functions
- ===============================================================================
-
- This section provide functions allowing to program SDIO DMA transfer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the SDIO DMA request.
- * @param NewState: new state of the selected SDIO DMA request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_DMACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group7 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the SDIO interrupts.
- * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
- * @param NewState: new state of the specified SDIO interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_IT(SDIO_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the SDIO interrupts */
- SDIO->MASK |= SDIO_IT;
- }
- else
- {
- /* Disable the SDIO interrupts */
- SDIO->MASK &= ~SDIO_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified SDIO flag is set or not.
- * @param SDIO_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_CMDACT: Command transfer in progress
- * @arg SDIO_FLAG_TXACT: Data transmit in progress
- * @arg SDIO_FLAG_RXACT: Data receive in progress
- * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
- * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
- * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
- * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
- * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
- * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
- * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
- * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
- * @retval The new state of SDIO_FLAG (SET or RESET).
- */
-FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_SDIO_FLAG(SDIO_FLAG));
-
- if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the SDIO's pending flags.
- * @param SDIO_FLAG: specifies the flag to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
- * @retval None
- */
-void SDIO_ClearFlag(uint32_t SDIO_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
-
- SDIO->ICR = SDIO_FLAG;
-}
-
-/**
- * @brief Checks whether the specified SDIO interrupt has occurred or not.
- * @param SDIO_IT: specifies the SDIO interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
- * @retval The new state of SDIO_IT (SET or RESET).
- */
-ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_SDIO_GET_IT(SDIO_IT));
- if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the SDIO's interrupt pending bits.
- * @param SDIO_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
- * @retval None
- */
-void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
-
- SDIO->ICR = SDIO_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_spi.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Serial peripheral interface (SPI):
- * - Initialization and Configuration
- * - Data transfers functions
- * - Hardware CRC Calculation
- * - DMA transfers management
- * - Interrupts and flags management
- *
- * @verbatim
- *
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- *
- * 1. Enable peripheral clock using the following functions
- * RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1
- * RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2
- * RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3.
- *
- * 2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd()
- * function.
- * In I2S mode, if an external clock source is used then the I2S CKIN pin GPIO
- * clock should also be enabled.
- *
- * 3. Peripherals alternate function:
- * - Connect the pin to the desired peripherals' Alternate
- * Function (AF) using GPIO_PinAFConfig() function
- * - Configure the desired pin in alternate function by:
- * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- * - Select the type, pull-up/pull-down and output speed via
- * GPIO_PuPd, GPIO_OType and GPIO_Speed members
- * - Call GPIO_Init() function
- * In I2S mode, if an external clock source is used then the I2S CKIN pin
- * should be also configured in Alternate function Push-pull pull-up mode.
- *
- * 4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave
- * Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
- * function.
- * In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio
- * frequency and Polarity using I2S_Init() function.
- * For I2S mode, make sure that either:
- * - I2S PLL is configured using the functions RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S),
- * RCC_PLLI2SCmd(ENABLE) and RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY).
- * or
- * - External clock source is configured using the function
- * RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the define constant
- * I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file.
- *
- * 5. Enable the NVIC and the corresponding interrupt using the function
- * SPI_ITConfig() if you need to use interrupt mode.
- *
- * 6. When using the DMA mode
- * - Configure the DMA using DMA_Init() function
- * - Active the needed channel Request using SPI_I2S_DMACmd() function
- *
- * 7. Enable the SPI using the SPI_Cmd() function or enable the I2S using
- * I2S_Cmd().
- *
- * 8. Enable the DMA using the DMA_Cmd() function when using DMA mode.
- *
- * 9. Optionally, you can enable/configure the following parameters without
- * re-initialization (i.e there is no need to call again SPI_Init() function):
- * - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
- * is programmed as Data direction parameter using the SPI_Init() function
- * it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx
- * using the SPI_BiDirectionalLineConfig() function.
- * - When SPI_NSS_Soft is selected as Slave Select Management parameter
- * using the SPI_Init() function it can be possible to manage the
- * NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
- * - Reconfigure the data size using the SPI_DataSizeConfig() function
- * - Enable or disable the SS output using the SPI_SSOutputCmd() function
- *
- * 10. To use the CRC Hardware calculation feature refer to the Peripheral
- * CRC hardware Calculation subsection.
- *
- *
- * It is possible to use SPI in I2S full duplex mode, in this case, each SPI
- * peripheral is able to manage sending and receiving data simultaneously
- * using two data lines. Each SPI peripheral has an extended block called I2Sxext
- * (ie. I2S2ext for SPI2 and I2S3ext for SPI3).
- * The extension block is not a full SPI IP, it is used only as I2S slave to
- * implement full duplex mode. The extension block uses the same clock sources
- * as its master.
- * To configure I2S full duplex you have to:
- *
- * 1. Configure SPIx in I2S mode (I2S_Init() function) as described above.
- *
- * 2. Call the I2S_FullDuplexConfig() function using the same strucutre passed to
- * I2S_Init() function.
- *
- * 3. Call I2S_Cmd() for SPIx then for its extended block.
- *
- * 4. To configure interrupts or DMA requests and to get/clear flag status,
- * use I2Sxext instance for the extension block.
- *
- * Functions that can be called with I2Sxext instances are:
- * I2S_Cmd(), I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(),
- * SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), SPI_I2S_ClearFlag(),
- * SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit().
- *
- * Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx):
- *
- * RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
- * I2S_StructInit(&I2SInitStruct);
- * I2SInitStruct.Mode = I2S_Mode_MasterTx;
- * I2S_Init(SPI3, &I2SInitStruct);
- * I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct)
- * I2S_Cmd(SPI3, ENABLE);
- * I2S_Cmd(SPI3ext, ENABLE);
- * ...
- * while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
- * {}
- * SPI_I2S_SendData(SPI3, txdata[i]);
- * ...
- * while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET)
- * {}
- * rxdata[i] = SPI_I2S_ReceiveData(I2S3ext);
- * ...
- *
- *
- *
- * @note This driver supports only the I2S clock scheme available in Silicon
- * RevisionB and RevisionY.
- *
- * @note In I2S mode: if an external clock is used as source clock for the I2S,
- * then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should
- * be enabled and set to the value of the source clock frequency (in Hz).
- *
- * @note In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd()
- * just after calling the function SPI_Init().
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_spi.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SPI
- * @brief SPI driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* SPI registers Masks */
-#define CR1_CLEAR_MASK ((uint16_t)0x3040)
-#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040)
-
-/* RCC PLLs masks */
-#define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000)
-#define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0)
-
-#define SPI_CR2_FRF ((uint16_t)0x0010)
-#define SPI_SR_TIFRFE ((uint16_t)0x0100)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SPI_Private_Functions
- * @{
- */
-
-/** @defgroup SPI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- Initialization and Configuration functions
- ===============================================================================
-
- This section provides a set of functions allowing to initialize the SPI Direction,
- SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud
- Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
-
- The SPI_Init() function follows the SPI configuration procedures for Master mode
- and Slave mode (details for these procedures are available in reference manual
- (RM0090)).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitialize the SPIx peripheral registers to their default reset values.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode.
- *
- * @note The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are deinitialized
- * when the relative I2S peripheral is deinitialized (the extended block's clock
- * is managed by the I2S peripheral clock).
- *
- * @retval None
- */
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- if (SPIx == SPI1)
- {
- /* Enable SPI1 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
- /* Release SPI1 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
- }
- else if (SPIx == SPI2)
- {
- /* Enable SPI2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
- /* Release SPI2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
- }
- else
- {
- if (SPIx == SPI3)
- {
- /* Enable SPI3 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
- /* Release SPI3 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the SPI_InitStruct.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral.
- * @retval None
- */
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
-{
- uint16_t tmpreg = 0;
-
- /* check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Check the SPI parameters */
- assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
- assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
- assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
- assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
- assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
- assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
- assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
- assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
- assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
-
-/*---------------------------- SPIx CR1 Configuration ------------------------*/
- /* Get the SPIx CR1 value */
- tmpreg = SPIx->CR1;
- /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
- master/salve mode, CPOL and CPHA */
- /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
- /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
- /* Set LSBFirst bit according to SPI_FirstBit value */
- /* Set BR bits according to SPI_BaudRatePrescaler value */
- /* Set CPOL bit according to SPI_CPOL value */
- /* Set CPHA bit according to SPI_CPHA value */
- tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
- SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
- SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
- SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
- /* Write to SPIx CR1 */
- SPIx->CR1 = tmpreg;
-
- /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
- SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
-/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
- /* Write to SPIx CRCPOLY */
- SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the I2S_InitStruct.
- * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode).
- * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral
- * configured in I2S mode.
- *
- * @note The function calculates the optimal prescaler needed to obtain the most
- * accurate audio frequency (depending on the I2S clock source, the PLL values
- * and the product configuration). But in case the prescaler value is greater
- * than 511, the default value (0x02) will be configured instead.
- *
- * @note if an external clock is used as source clock for the I2S, then the define
- * I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should be enabled and set
- * to the value of the the source clock frequency (in Hz).
- *
- * @retval None
- */
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
-{
- uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
- uint32_t tmp = 0, i2sclk = 0;
-#ifndef I2S_EXTERNAL_CLOCK_VAL
- uint32_t pllm = 0, plln = 0, pllr = 0;
-#endif /* I2S_EXTERNAL_CLOCK_VAL */
-
- /* Check the I2S parameters */
- assert_param(IS_SPI_23_PERIPH(SPIx));
- assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
- assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
- assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
- assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
- assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
- assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
-
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK;
- SPIx->I2SPR = 0x0002;
-
- /* Get the I2SCFGR register value */
- tmpreg = SPIx->I2SCFGR;
-
- /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
- if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
- {
- i2sodd = (uint16_t)0;
- i2sdiv = (uint16_t)2;
- }
- /* If the requested audio frequency is not the default, compute the prescaler */
- else
- {
- /* Check the frame length (For the Prescaler computing) *******************/
- if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
- {
- /* Packet length is 16 bits */
- packetlength = 1;
- }
- else
- {
- /* Packet length is 32 bits */
- packetlength = 2;
- }
-
- /* Get I2S source Clock frequency (only in Silicon RevisionB and RevisionY) */
-
- /* If an external I2S clock has to be used, this define should be set
- in the project configuration or in the stm32f4xx_conf.h file */
- #ifdef I2S_EXTERNAL_CLOCK_VAL
- /* Set external clock as I2S clock source */
- if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0)
- {
- RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
- }
-
- /* Set the I2S clock to the external clock value */
- i2sclk = I2S_EXTERNAL_CLOCK_VAL;
-
- #else /* There is no define for External I2S clock source */
- /* Set PLLI2S as I2S clock source */
- if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0)
- {
- RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
- }
-
- /* Get the PLLI2SN value */
- plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \
- (RCC_PLLI2SCFGR_PLLI2SN >> 6));
-
- /* Get the PLLI2SR value */
- pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \
- (RCC_PLLI2SCFGR_PLLI2SR >> 28));
-
- /* Get the PLLM value */
- pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
-
- /* Get the I2S source clock value */
- i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr);
- #endif /* I2S_EXTERNAL_CLOCK_VAL */
-
- /* Compute the Real divider depending on the MCLK output state, with a floating point */
- if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
- {
- /* MCLK output is enabled */
- tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
- else
- {
- /* MCLK output is disabled */
- tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
-
- /* Remove the flatting point */
- tmp = tmp / 10;
-
- /* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
-
- /* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
-
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t) (i2sodd << 8);
- }
-
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if ((i2sdiv < 2) || (i2sdiv > 0xFF))
- {
- /* Set the default values */
- i2sdiv = 2;
- i2sodd = 0;
- }
-
- /* Write to SPIx I2SPR register the computed value */
- SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
-
- /* Configure the I2S with the SPI_InitStruct values */
- tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
- (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
- (uint16_t)I2S_InitStruct->I2S_CPOL))));
-
- /* Write to SPIx I2SCFGR */
- SPIx->I2SCFGR = tmpreg;
-}
-
-/**
- * @brief Fills each SPI_InitStruct member with its default value.
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
-{
-/*--------------- Reset SPI init structure parameters values -----------------*/
- /* Initialize the SPI_Direction member */
- SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
- /* initialize the SPI_Mode member */
- SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
- /* initialize the SPI_DataSize member */
- SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
- /* Initialize the SPI_CPOL member */
- SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
- /* Initialize the SPI_CPHA member */
- SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
- /* Initialize the SPI_NSS member */
- SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
- /* Initialize the SPI_BaudRatePrescaler member */
- SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
- /* Initialize the SPI_FirstBit member */
- SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
- /* Initialize the SPI_CRCPolynomial member */
- SPI_InitStruct->SPI_CRCPolynomial = 7;
-}
-
-/**
- * @brief Fills each I2S_InitStruct member with its default value.
- * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
-{
-/*--------------- Reset I2S init structure parameters values -----------------*/
- /* Initialize the I2S_Mode member */
- I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
-
- /* Initialize the I2S_Standard member */
- I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
-
- /* Initialize the I2S_DataFormat member */
- I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
-
- /* Initialize the I2S_MCLKOutput member */
- I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
-
- /* Initialize the I2S_AudioFreq member */
- I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
-
- /* Initialize the I2S_CPOL member */
- I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
-}
-
-/**
- * @brief Enables or disables the specified SPI peripheral.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral */
- SPIx->CR1 |= SPI_CR1_SPE;
- }
- else
- {
- /* Disable the selected SPI peripheral */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
- }
-}
-
-/**
- * @brief Enables or disables the specified SPI peripheral (in I2S mode).
- * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (or I2Sxext
- * for full duplex mode).
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_23_PERIPH_EXT(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral (in I2S mode) */
- SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
- }
- else
- {
- /* Disable the selected SPI peripheral in I2S mode */
- SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
- }
-}
-
-/**
- * @brief Configures the data size for the selected SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_DataSize: specifies the SPI data size.
- * This parameter can be one of the following values:
- * @arg SPI_DataSize_16b: Set data frame format to 16bit
- * @arg SPI_DataSize_8b: Set data frame format to 8bit
- * @retval None
- */
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DATASIZE(SPI_DataSize));
- /* Clear DFF bit */
- SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
- /* Set new DFF bit value */
- SPIx->CR1 |= SPI_DataSize;
-}
-
-/**
- * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_Direction: specifies the data transfer direction in bidirectional mode.
- * This parameter can be one of the following values:
- * @arg SPI_Direction_Tx: Selects Tx transmission direction
- * @arg SPI_Direction_Rx: Selects Rx receive direction
- * @retval None
- */
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DIRECTION(SPI_Direction));
- if (SPI_Direction == SPI_Direction_Tx)
- {
- /* Set the Tx only mode */
- SPIx->CR1 |= SPI_Direction_Tx;
- }
- else
- {
- /* Set the Rx only mode */
- SPIx->CR1 &= SPI_Direction_Rx;
- }
-}
-
-/**
- * @brief Configures internally by software the NSS pin for the selected SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
- * This parameter can be one of the following values:
- * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
- * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
- * @retval None
- */
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
- if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
- {
- /* Set NSS pin internally by software */
- SPIx->CR1 |= SPI_NSSInternalSoft_Set;
- }
- else
- {
- /* Reset NSS pin internally by software */
- SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the SS output for the selected SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param NewState: new state of the SPIx SS output.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI SS output */
- SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
- }
- else
- {
- /* Disable the selected SPI SS output */
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
- }
-}
-
-/**
- * @brief Enables or disables the SPIx/I2Sx DMA interface.
- *
- * @note This function can be called only after the SPI_Init() function has
- * been called.
- * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA
- * are not taken into consideration and are configured by hardware
- * respectively to the TI mode requirements.
- *
- * @param SPIx: where x can be 1, 2 or 3
- * @param NewState: new state of the selected SPI TI communication mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TI mode for the selected SPI peripheral */
- SPIx->CR2 |= SPI_CR2_FRF;
- }
- else
- {
- /* Disable the TI mode for the selected SPI peripheral */
- SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF;
- }
-}
-
-/**
- * @brief Configures the full duplex mode for the I2Sx peripheral using its
- * extension I2Sxext according to the specified parameters in the
- * I2S_InitStruct.
- * @param I2Sxext: where x can be 2 or 3 to select the I2S peripheral extension block.
- * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
- * contains the configuration information for the specified I2S peripheral
- * extension.
- *
- * @note The structure pointed by I2S_InitStruct parameter should be the same
- * used for the master I2S peripheral. In this case, if the master is
- * configured as transmitter, the slave will be receiver and vice versa.
- * Or you can force a different mode by modifying the field I2S_Mode to the
- * value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration.
- *
- * @note The I2S full duplex extension can be configured in slave mode only.
- *
- * @retval None
- */
-void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct)
-{
- uint16_t tmpreg = 0, tmp = 0;
-
- /* Check the I2S parameters */
- assert_param(IS_I2S_EXT_PERIPH(I2Sxext));
- assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
- assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
- assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
- assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
-
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK;
- I2Sxext->I2SPR = 0x0002;
-
- /* Get the I2SCFGR register value */
- tmpreg = I2Sxext->I2SCFGR;
-
- /* Get the mode to be configured for the extended I2S */
- if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx))
- {
- tmp = I2S_Mode_SlaveRx;
- }
- else
- {
- if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx))
- {
- tmp = I2S_Mode_SlaveTx;
- }
- }
-
-
- /* Configure the I2S with the SPI_InitStruct values */
- tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
- (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
- (uint16_t)I2S_InitStruct->I2S_CPOL))));
-
- /* Write to SPIx I2SCFGR */
- I2Sxext->I2SCFGR = tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- Data transfers functions
- ===============================================================================
-
- This section provides a set of functions allowing to manage the SPI data transfers
-
- In reception, data are received and then stored into an internal Rx buffer while
- In transmission, data are first stored into an internal Tx buffer before being
- transmitted.
-
- The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()
- function and returns the Rx buffered value. Whereas a write access to the SPI_DR
- can be done using SPI_I2S_SendData() function and stores the written data into
- Tx buffer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @retval The value of the received data.
- */
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
-
- /* Return the data in the DR register */
- return SPIx->DR;
-}
-
-/**
- * @brief Transmits a Data through the SPIx/I2Sx peripheral.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param Data: Data to be transmitted.
- * @retval None
- */
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
-
- /* Write in the DR register the data to be sent */
- SPIx->DR = Data;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group3 Hardware CRC Calculation functions
- * @brief Hardware CRC Calculation functions
- *
-@verbatim
- ===============================================================================
- Hardware CRC Calculation functions
- ===============================================================================
-
- This section provides a set of functions allowing to manage the SPI CRC hardware
- calculation
-
- SPI communication using CRC is possible through the following procedure:
- 1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler,
- Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
- function.
- 2. Enable the CRC calculation using the SPI_CalculateCRC() function.
- 3. Enable the SPI using the SPI_Cmd() function
- 4. Before writing the last data to the TX buffer, set the CRCNext bit using the
- SPI_TransmitCRC() function to indicate that after transmission of the last
- data, the CRC should be transmitted.
- 5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
- bit is reset. The CRC is also received and compared against the SPI_RXCRCR
- value.
- If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
- can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
-
-@note It is advised not to read the calculated CRC values during the communication.
-
-@note When the SPI is in slave mode, be careful to enable CRC calculation only
- when the clock is stable, that is, when the clock is in the steady state.
- If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive
- to the SCK slave input clock as soon as CRCEN is set, and this, whatever
- the value of the SPE bit.
-
-@note With high bitrate frequencies, be careful when transmitting the CRC.
- As the number of used CPU cycles has to be as low as possible in the CRC
- transfer phase, it is forbidden to call software functions in the CRC
- transmission sequence to avoid errors in the last data and CRC reception.
- In fact, CRCNEXT bit has to be written before the end of the transmission/reception
- of the last data.
-
-@note For high bit rate frequencies, it is advised to use the DMA mode to avoid the
- degradation of the SPI speed performance due to CPU accesses impacting the
- SPI bandwidth.
-
-@note When the STM32F4xx is configured as slave and the NSS hardware mode is
- used, the NSS pin needs to be kept low between the data phase and the CRC
- phase.
-
-@note When the SPI is configured in slave mode with the CRC feature enabled, CRC
- calculation takes place even if a high level is applied on the NSS pin.
- This may happen for example in case of a multi-slave environment where the
- communication master addresses slaves alternately.
-
-@note Between a slave de-selection (high level on NSS) and a new slave selection
- (low level on NSS), the CRC value should be cleared on both master and slave
- sides in order to resynchronize the master and slave for their respective
- CRC calculation.
-
-@note To clear the CRC, follow the procedure below:
- 1. Disable SPI using the SPI_Cmd() function
- 2. Disable the CRC calculation using the SPI_CalculateCRC() function.
- 3. Enable the CRC calculation using the SPI_CalculateCRC() function.
- 4. Enable SPI using the SPI_Cmd() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the CRC value calculation of the transferred bytes.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param NewState: new state of the SPIx CRC value calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI CRC calculation */
- SPIx->CR1 |= SPI_CR1_CRCEN;
- }
- else
- {
- /* Disable the selected SPI CRC calculation */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
- }
-}
-
-/**
- * @brief Transmit the SPIx CRC value.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @retval None
- */
-void SPI_TransmitCRC(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Enable the selected SPI CRC transmission */
- SPIx->CR1 |= SPI_CR1_CRCNEXT;
-}
-
-/**
- * @brief Returns the transmit or the receive CRC register value for the specified SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_CRC: specifies the CRC register to be read.
- * This parameter can be one of the following values:
- * @arg SPI_CRC_Tx: Selects Tx CRC register
- * @arg SPI_CRC_Rx: Selects Rx CRC register
- * @retval The selected CRC register value..
- */
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
-{
- uint16_t crcreg = 0;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_CRC(SPI_CRC));
- if (SPI_CRC != SPI_CRC_Rx)
- {
- /* Get the Tx CRC register */
- crcreg = SPIx->TXCRCR;
- }
- else
- {
- /* Get the Rx CRC register */
- crcreg = SPIx->RXCRCR;
- }
- /* Return the selected CRC register */
- return crcreg;
-}
-
-/**
- * @brief Returns the CRC Polynomial register value for the specified SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @retval The CRC Polynomial register value.
- */
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Return the CRC polynomial register */
- return SPIx->CRCPR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group4 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- DMA transfers management functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the SPIx/I2Sx DMA interface.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
- * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
- * @param NewState: new state of the selected SPI DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI DMA requests */
- SPIx->CR2 |= SPI_I2S_DMAReq;
- }
- else
- {
- /* Disable the selected SPI DMA requests */
- SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group5 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
-
- This section provides a set of functions allowing to configure the SPI Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode.
-
- Polling Mode
- =============
- In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
- 1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register
- 2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register
- 3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
- 4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur
- 5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur
- 6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur
- 7. I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs.
- 8. I2S_FLAG_UDR: to indicate an Underrun error occurs.
- 9. I2S_FLAG_CHSIDE: to indicate Channel Side.
-
-@note Do not use the BSY flag to handle each data transmission or reception. It is
- better to use the TXE and RXNE flags instead.
-
- In this Mode it is advised to use the following functions:
- - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
- - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-
- Interrupt Mode
- ===============
- In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources
- and 7 pending bits:
- Pending Bits:
- -------------
- 1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register
- 2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register
- 3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only)
- 4. SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only)
- 5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur
- 6. I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only).
- 7. I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only).
-
- Interrupt Source:
- -----------------
- 1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty
- interrupt.
- 2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not
- empty interrupt.
- 3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
-
- In this Mode it is advised to use the following functions:
- - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
- - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
- - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-
- DMA Mode
- ========
- In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:
- 1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request
- 2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request
-
- In this Mode it is advised to use the following function:
- - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified SPI/I2S interrupts.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
- * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
- * @arg SPI_I2S_IT_ERR: Error interrupt mask
- * @param NewState: new state of the specified SPI interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
-{
- uint16_t itpos = 0, itmask = 0 ;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
-
- /* Get the SPI IT index */
- itpos = SPI_I2S_IT >> 4;
-
- /* Set the IT mask */
- itmask = (uint16_t)1 << (uint16_t)itpos;
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI interrupt */
- SPIx->CR2 |= itmask;
- }
- else
- {
- /* Disable the selected SPI interrupt */
- SPIx->CR2 &= (uint16_t)~itmask;
- }
-}
-
-/**
- * @brief Checks whether the specified SPIx/I2Sx flag is set or not.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_FLAG: specifies the SPI flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
- * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
- * @arg SPI_I2S_FLAG_BSY: Busy flag.
- * @arg SPI_I2S_FLAG_OVR: Overrun flag.
- * @arg SPI_FLAG_MODF: Mode Fault flag.
- * @arg SPI_FLAG_CRCERR: CRC Error flag.
- * @arg SPI_I2S_FLAG_TIFRFE: Format Error.
- * @arg I2S_FLAG_UDR: Underrun Error flag.
- * @arg I2S_FLAG_CHSIDE: Channel Side flag.
- * @retval The new state of SPI_I2S_FLAG (SET or RESET).
- */
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
-
- /* Check the status of the specified SPI flag */
- if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
- {
- /* SPI_I2S_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SPIx CRC Error (CRCERR) flag.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
- * This function clears only CRCERR flag.
- * @arg SPI_FLAG_CRCERR: CRC Error flag.
- *
- * @note OVR (OverRun error) flag is cleared by software sequence: a read
- * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
- * @note UDR (UnderRun error) flag is cleared by a read operation to
- * SPI_SR register (SPI_I2S_GetFlagStatus()).
- * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
- * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
- *
- * @retval None
- */
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
-
- /* Clear the selected SPI CRC Error (CRCERR) flag */
- SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
-}
-
-/**
- * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_IT: specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
- * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
- * @arg SPI_I2S_IT_OVR: Overrun interrupt.
- * @arg SPI_IT_MODF: Mode Fault interrupt.
- * @arg SPI_IT_CRCERR: CRC Error interrupt.
- * @arg I2S_IT_UDR: Underrun interrupt.
- * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt.
- * @retval The new state of SPI_I2S_IT (SET or RESET).
- */
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itpos = 0, itmask = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
-
- /* Get the SPI_I2S_IT index */
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
- /* Get the SPI_I2S_IT IT mask */
- itmask = SPI_I2S_IT >> 4;
-
- /* Set the IT mask */
- itmask = 0x01 << itmask;
-
- /* Get the SPI_I2S_IT enable bit status */
- enablestatus = (SPIx->CR2 & itmask) ;
-
- /* Check the status of the specified SPI interrupt */
- if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
- {
- /* SPI_I2S_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_IT is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
- * This function clears only CRCERR interrupt pending bit.
- * @arg SPI_IT_CRCERR: CRC Error interrupt.
- *
- * @note OVR (OverRun Error) interrupt pending bit is cleared by software
- * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
- * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
- * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read
- * operation to SPI_SR register (SPI_I2S_GetITStatus()).
- * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
- * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus())
- * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
- * the SPI).
- * @retval None
- */
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
- uint16_t itpos = 0;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
-
- /* Get the SPI_I2S IT index */
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
- /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
- SPIx->SR = (uint16_t)~itpos;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_syscfg.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the SYSCFG peripheral.
- *
- * @verbatim
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- *
- * This driver provides functions for:
- *
- * 1. Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
- *
- * 2. Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig()
- *
- * 3. Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig()
- *
- * @note SYSCFG APB clock must be enabled to get write access to SYSCFG registers,
- * using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_syscfg.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SYSCFG
- * @brief SYSCFG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ------------ RCC registers bit address in the alias region ----------- */
-#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
-/* --- PMC Register ---*/
-/* Alias word address of MII_RMII_SEL bit */
-#define PMC_OFFSET (SYSCFG_OFFSET + 0x04)
-#define MII_RMII_SEL_BitNumber ((uint8_t)0x17)
-#define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
-
-/* --- CMPCR Register ---*/
-/* Alias word address of CMP_PD bit */
-#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20)
-#define CMP_PD_BitNumber ((uint8_t)0x00)
-#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4))
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SYSCFG_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the Alternate Functions (remap and EXTI configuration)
- * registers to their default reset values.
- * @param None
- * @retval None
- */
-void SYSCFG_DeInit(void)
-{
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);
-}
-
-/**
- * @brief Changes the mapping of the specified pin.
- * @param SYSCFG_Memory: selects the memory remapping.
- * This parameter can be one of the following values:
- * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000
- *
- * @note In remap mode, the FSMC addressing is fixed to the remap address area only
- * (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) and FSMC control registers are not
- * accessible. The FSMC remap function must be disabled to allows addressing
- * other memory devices through the FSMC and/or to access FSMC control
- * registers.
- *
- * @retval None
- */
-void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));
-
- SYSCFG->MEMRMP = SYSCFG_MemoryRemap;
-}
-
-/**
- * @brief Selects the GPIO pin used as EXTI Line.
- * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for
- * EXTI lines where x can be (A..I).
- * @param EXTI_PinSourcex: specifies the EXTI line to be configured.
- * This parameter can be EXTI_PinSourcex where x can be (0..15, except
- * for EXTI_PortSourceGPIOI x can be (0..11).
- * @retval None
- */
-void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
-{
- uint32_t tmp = 0x00;
-
- /* Check the parameters */
- assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
- assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
-
- tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
- SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
- SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
-}
-
-/**
- * @brief Selects the ETHERNET media interface
- * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode.
- * This parameter can be one of the following values:
- * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected
- * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected
- * @retval None
- */
-void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface)
-{
- assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface));
- /* Configure MII_RMII selection bit */
- *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface;
-}
-
-/**
- * @brief Enables or disables the I/O Compensation Cell.
- * @note The I/O compensation cell can be used only when the device supply
- * voltage ranges from 2.4 to 3.6 V.
- * @param NewState: new state of the I/O Compensation Cell.
- * This parameter can be one of the following values:
- * @arg ENABLE: I/O compensation cell enabled
- * @arg DISABLE: I/O compensation cell power-down mode
- * @retval None
- */
-void SYSCFG_CompensationCellCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Checks whether the I/O Compensation Cell ready flag is set or not.
- * @param None
- * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET)
- */
-FlagStatus SYSCFG_GetCompensationCellStatus(void)
-{
- FlagStatus bitstatus = RESET;
-
- if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_tim.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the TIM peripheral:
- * - TimeBase management
- * - Output Compare management
- * - Input Capture management
- * - Advanced-control timers (TIM1 and TIM8) specific features
- * - Interrupts, DMA and flags management
- * - Clocks management
- * - Synchronization management
- * - Specific interface management
- * - Specific remapping management
- *
- * @verbatim
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * This driver provides functions to configure and program the TIM
- * of all STM32F4xx devices.
- * These functions are split in 9 groups:
- *
- * 1. TIM TimeBase management: this group includes all needed functions
- * to configure the TM Timebase unit:
- * - Set/Get Prescaler
- * - Set/Get Autoreload
- * - Counter modes configuration
- * - Set Clock division
- * - Select the One Pulse mode
- * - Update Request Configuration
- * - Update Disable Configuration
- * - Auto-Preload Configuration
- * - Enable/Disable the counter
- *
- * 2. TIM Output Compare management: this group includes all needed
- * functions to configure the Capture/Compare unit used in Output
- * compare mode:
- * - Configure each channel, independently, in Output Compare mode
- * - Select the output compare modes
- * - Select the Polarities of each channel
- * - Set/Get the Capture/Compare register values
- * - Select the Output Compare Fast mode
- * - Select the Output Compare Forced mode
- * - Output Compare-Preload Configuration
- * - Clear Output Compare Reference
- * - Select the OCREF Clear signal
- * - Enable/Disable the Capture/Compare Channels
- *
- * 3. TIM Input Capture management: this group includes all needed
- * functions to configure the Capture/Compare unit used in
- * Input Capture mode:
- * - Configure each channel in input capture mode
- * - Configure Channel1/2 in PWM Input mode
- * - Set the Input Capture Prescaler
- * - Get the Capture/Compare values
- *
- * 4. Advanced-control timers (TIM1 and TIM8) specific features
- * - Configures the Break input, dead time, Lock level, the OSSI,
- * the OSSR State and the AOE(automatic output enable)
- * - Enable/Disable the TIM peripheral Main Outputs
- * - Select the Commutation event
- * - Set/Reset the Capture Compare Preload Control bit
- *
- * 5. TIM interrupts, DMA and flags management
- * - Enable/Disable interrupt sources
- * - Get flags status
- * - Clear flags/ Pending bits
- * - Enable/Disable DMA requests
- * - Configure DMA burst mode
- * - Select CaptureCompare DMA request
- *
- * 6. TIM clocks management: this group includes all needed functions
- * to configure the clock controller unit:
- * - Select internal/External clock
- * - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
- *
- * 7. TIM synchronization management: this group includes all needed
- * functions to configure the Synchronization unit:
- * - Select Input Trigger
- * - Select Output Trigger
- * - Select Master Slave Mode
- * - ETR Configuration when used as external trigger
- *
- * 8. TIM specific interface management, this group includes all
- * needed functions to use the specific TIM interface:
- * - Encoder Interface Configuration
- * - Select Hall Sensor
- *
- * 9. TIM specific remapping management includes the Remapping
- * configuration of specific timers
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_tim.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup TIM
- * @brief TIM driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ---------------------- TIM registers bit mask ------------------------ */
-#define SMCR_ETR_MASK ((uint16_t)0x00FF)
-#define CCMR_OFFSET ((uint16_t)0x0018)
-#define CCER_CCE_SET ((uint16_t)0x0001)
-#define CCER_CCNE_SET ((uint16_t)0x0004)
-#define CCMR_OC13M_MASK ((uint16_t)0xFF8F)
-#define CCMR_OC24M_MASK ((uint16_t)0x8FFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup TIM_Private_Functions
- * @{
- */
-
-/** @defgroup TIM_Group1 TimeBase management functions
- * @brief TimeBase management functions
- *
-@verbatim
- ===============================================================================
- TimeBase management functions
- ===============================================================================
-
- ===================================================================
- TIM Driver: how to use it in Timing(Time base) Mode
- ===================================================================
- To use the Timer in Timing(Time base) mode, the following steps are mandatory:
-
- 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
-
- 2. Fill the TIM_TimeBaseInitStruct with the desired parameters.
-
- 3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit
- with the corresponding configuration
-
- 4. Enable the NVIC if you need to generate the update interrupt.
-
- 5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update)
-
- 6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
-
- Note1: All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the TIMx peripheral registers to their default reset values.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @retval None
-
- */
-void TIM_DeInit(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- if (TIMx == TIM1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
- }
- else if (TIMx == TIM2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
- }
- else if (TIMx == TIM3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
- }
- else if (TIMx == TIM4)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
- }
- else if (TIMx == TIM5)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
- }
- else if (TIMx == TIM6)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
- }
- else if (TIMx == TIM7)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
- }
- else if (TIMx == TIM8)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
- }
- else if (TIMx == TIM9)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
- }
- else if (TIMx == TIM10)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
- }
- else if (TIMx == TIM11)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
- }
- else if (TIMx == TIM12)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);
- }
- else if (TIMx == TIM13)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);
- }
- else
- {
- if (TIMx == TIM14)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the TIMx Time Base Unit peripheral according to
- * the specified parameters in the TIM_TimeBaseInitStruct.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- uint16_t tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
- assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
-
- tmpcr1 = TIMx->CR1;
-
- if((TIMx == TIM1) || (TIMx == TIM8)||
- (TIMx == TIM2) || (TIMx == TIM3)||
- (TIMx == TIM4) || (TIMx == TIM5))
- {
- /* Select the Counter Mode */
- tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS));
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
- }
-
- if((TIMx != TIM6) && (TIMx != TIM7))
- {
- /* Set the clock division */
- tmpcr1 &= (uint16_t)(~TIM_CR1_CKD);
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
- }
-
- TIMx->CR1 = tmpcr1;
-
- /* Set the Autoreload value */
- TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
-
- /* Set the Prescaler value */
- TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
-
- if ((TIMx == TIM1) || (TIMx == TIM8))
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter(only for TIM1 and TIM8) value immediatly */
- TIMx->EGR = TIM_PSCReloadMode_Immediate;
-}
-
-/**
- * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
- * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- /* Set the default configuration */
- TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
- TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
- TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
- TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
- TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
-}
-
-/**
- * @brief Configures the TIMx Prescaler.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param Prescaler: specifies the Prescaler Register value
- * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
- * This parameter can be one of the following values:
- * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
- * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
- * @retval None
- */
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
- /* Set the Prescaler value */
- TIMx->PSC = Prescaler;
- /* Set or reset the UG Bit */
- TIMx->EGR = TIM_PSCReloadMode;
-}
-
-/**
- * @brief Specifies the TIMx Counter Mode to be used.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_CounterMode: specifies the Counter Mode to be used
- * This parameter can be one of the following values:
- * @arg TIM_CounterMode_Up: TIM Up Counting Mode
- * @arg TIM_CounterMode_Down: TIM Down Counting Mode
- * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
- * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
- * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
- * @retval None
- */
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
-{
- uint16_t tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
-
- tmpcr1 = TIMx->CR1;
-
- /* Reset the CMS and DIR Bits */
- tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS);
-
- /* Set the Counter Mode */
- tmpcr1 |= TIM_CounterMode;
-
- /* Write to TIMx CR1 register */
- TIMx->CR1 = tmpcr1;
-}
-
-/**
- * @brief Sets the TIMx Counter Register value
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param Counter: specifies the Counter register new value.
- * @retval None
- */
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Set the Counter Register value */
- TIMx->CNT = Counter;
-}
-
-/**
- * @brief Sets the TIMx Autoreload Register value
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param Autoreload: specifies the Autoreload register new value.
- * @retval None
- */
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Set the Autoreload Register value */
- TIMx->ARR = Autoreload;
-}
-
-/**
- * @brief Gets the TIMx Counter value.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @retval Counter Register value
- */
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Get the Counter Register value */
- return TIMx->CNT;
-}
-
-/**
- * @brief Gets the TIMx Prescaler value.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @retval Prescaler Register value.
- */
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Get the Prescaler Register value */
- return TIMx->PSC;
-}
-
-/**
- * @brief Enables or Disables the TIMx Update event.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param NewState: new state of the TIMx UDIS bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the Update Disable Bit */
- TIMx->CR1 |= TIM_CR1_UDIS;
- }
- else
- {
- /* Reset the Update Disable Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS;
- }
-}
-
-/**
- * @brief Configures the TIMx Update Request Interrupt source.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_UpdateSource: specifies the Update source.
- * This parameter can be one of the following values:
- * @arg TIM_UpdateSource_Regular: Source of update is the counter
- * overflow/underflow or the setting of UG bit, or an update
- * generation through the slave mode controller.
- * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
- * @retval None
- */
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
-
- if (TIM_UpdateSource != TIM_UpdateSource_Global)
- {
- /* Set the URS Bit */
- TIMx->CR1 |= TIM_CR1_URS;
- }
- else
- {
- /* Reset the URS Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_URS;
- }
-}
-
-/**
- * @brief Enables or disables TIMx peripheral Preload register on ARR.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param NewState: new state of the TIMx peripheral Preload register
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the ARR Preload Bit */
- TIMx->CR1 |= TIM_CR1_ARPE;
- }
- else
- {
- /* Reset the ARR Preload Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE;
- }
-}
-
-/**
- * @brief Selects the TIMx's One Pulse Mode.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_OPMode: specifies the OPM Mode to be used.
- * This parameter can be one of the following values:
- * @arg TIM_OPMode_Single
- * @arg TIM_OPMode_Repetitive
- * @retval None
- */
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
-
- /* Reset the OPM Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM;
-
- /* Configure the OPM Mode */
- TIMx->CR1 |= TIM_OPMode;
-}
-
-/**
- * @brief Sets the TIMx Clock Division value.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_CKD: specifies the clock division value.
- * This parameter can be one of the following value:
- * @arg TIM_CKD_DIV1: TDTS = Tck_tim
- * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
- * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
- * @retval None
- */
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_CKD_DIV(TIM_CKD));
-
- /* Reset the CKD Bits */
- TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD);
-
- /* Set the CKD value */
- TIMx->CR1 |= TIM_CKD;
-}
-
-/**
- * @brief Enables or disables the specified TIM peripheral.
- * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral.
- * @param NewState: new state of the TIMx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TIM Counter */
- TIMx->CR1 |= TIM_CR1_CEN;
- }
- else
- {
- /* Disable the TIM Counter */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group2 Output Compare management functions
- * @brief Output Compare management functions
- *
-@verbatim
- ===============================================================================
- Output Compare management functions
- ===============================================================================
-
- ===================================================================
- TIM Driver: how to use it in Output Compare Mode
- ===================================================================
- To use the Timer in Output Compare mode, the following steps are mandatory:
-
- 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
-
- 2. Configure the TIM pins by configuring the corresponding GPIO pins
-
- 2. Configure the Time base unit as described in the first part of this driver,
- if needed, else the Timer will run with the default configuration:
- - Autoreload value = 0xFFFF
- - Prescaler value = 0x0000
- - Counter mode = Up counting
- - Clock Division = TIM_CKD_DIV1
-
- 3. Fill the TIM_OCInitStruct with the desired parameters including:
- - The TIM Output Compare mode: TIM_OCMode
- - TIM Output State: TIM_OutputState
- - TIM Pulse value: TIM_Pulse
- - TIM Output Compare Polarity : TIM_OCPolarity
-
- 4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the
- corresponding configuration
-
- 5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
-
- Note1: All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
-
- Note2: In case of PWM mode, this function is mandatory:
- TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE);
-
- Note3: If the corresponding interrupt or DMA request are needed, the user should:
- 1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
- 2. Enable the corresponding interrupt (or DMA request) using the function
- TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIMx Channel1 according to the specified parameters in
- * the TIM_OCInitStruct.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M;
- tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S;
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC1P;
- /* Set the Output Compare Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
-
- /* Set the Output State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputState;
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
- /* Set the Output N Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
- /* Reset the Output N State */
- tmpccer &= (uint16_t)~TIM_CCER_CC1NE;
-
- /* Set the Output N State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS1;
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N;
- /* Set the Output Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
- /* Set the Output N Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel2 according to the specified parameters
- * in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M;
- tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC2P;
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
- /* Set the Output N Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
- /* Reset the Output N State */
- tmpccer &= (uint16_t)~TIM_CCER_CC2NE;
-
- /* Set the Output N State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS2;
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N;
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
- /* Set the Output N Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel3 according to the specified parameters
- * in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 3: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M;
- tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S;
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC3P;
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
- /* Set the Output N Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
- /* Reset the Output N State */
- tmpccer &= (uint16_t)~TIM_CCER_CC3NE;
-
- /* Set the Output N State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS3;
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N;
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
- /* Set the Output N Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel4 according to the specified parameters
- * in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M;
- tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC4P;
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
- /* Reset the Output Compare IDLE State */
- tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4;
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Fills each TIM_OCInitStruct member with its default value.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- /* Set the default configuration */
- TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
- TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
- TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
- TIM_OCInitStruct->TIM_Pulse = 0x00000000;
- TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
- TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
-}
-
-/**
- * @brief Selects the TIM Output Compare Mode.
- * @note This function disables the selected channel before changing the Output
- * Compare Mode. If needed, user has to enable this channel using
- * TIM_CCxCmd() and TIM_CCxNCmd() functions.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_OCMode: specifies the TIM Output Compare Mode.
- * This parameter can be one of the following values:
- * @arg TIM_OCMode_Timing
- * @arg TIM_OCMode_Active
- * @arg TIM_OCMode_Toggle
- * @arg TIM_OCMode_PWM1
- * @arg TIM_OCMode_PWM2
- * @arg TIM_ForcedAction_Active
- * @arg TIM_ForcedAction_InActive
- * @retval None
- */
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
-{
- uint32_t tmp = 0;
- uint16_t tmp1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_OCM(TIM_OCMode));
-
- tmp = (uint32_t) TIMx;
- tmp += CCMR_OFFSET;
-
- tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
-
- /* Disable the Channel: Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t) ~tmp1;
-
- if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
- {
- tmp += (TIM_Channel>>1);
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK;
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= TIM_OCMode;
- }
- else
- {
- tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK;
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
- }
-}
-
-/**
- * @brief Sets the TIMx Capture Compare1 Register value
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param Compare1: specifies the Capture Compare1 register new value.
- * @retval None
- */
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
-
- /* Set the Capture Compare1 Register value */
- TIMx->CCR1 = Compare1;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare2 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param Compare2: specifies the Capture Compare2 register new value.
- * @retval None
- */
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Set the Capture Compare2 Register value */
- TIMx->CCR2 = Compare2;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare3 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param Compare3: specifies the Capture Compare3 register new value.
- * @retval None
- */
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Set the Capture Compare3 Register value */
- TIMx->CCR3 = Compare3;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare4 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param Compare4: specifies the Capture Compare4 register new value.
- * @retval None
- */
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Set the Capture Compare4 Register value */
- TIMx->CCR4 = Compare4;
-}
-
-/**
- * @brief Forces the TIMx output 1 waveform to active or inactive level.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC1REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
- * @retval None
- */
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1M Bits */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M;
-
- /* Configure The Forced output Mode */
- tmpccmr1 |= TIM_ForcedAction;
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 2 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC2REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
- * @retval None
- */
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2M Bits */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M;
-
- /* Configure The Forced output Mode */
- tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 3 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC3REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
- * @retval None
- */
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC1M Bits */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M;
-
- /* Configure The Forced output Mode */
- tmpccmr2 |= TIM_ForcedAction;
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Forces the TIMx output 4 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC4REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
- * @retval None
- */
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC2M Bits */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M;
-
- /* Configure The Forced output Mode */
- tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1PE Bit */
- tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= TIM_OCPreload;
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2PE Bit */
- tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC3PE Bit */
- tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= TIM_OCPreload;
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC4PE Bit */
- tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 1 Fast feature.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1FE Bit */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE;
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= TIM_OCFast;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 2 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2FE Bit */
- tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE);
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 3 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC3FE Bit */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE;
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= TIM_OCFast;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 4 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC4FE Bit */
- tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE);
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF1 signal on an external event
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1CE Bit */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= TIM_OCClear;
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF2 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2CE Bit */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF3 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC3CE Bit */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= TIM_OCClear;
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF4 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC4CE Bit */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx channel 1 polarity.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC1 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC1P Bit */
- tmpccer &= (uint16_t)(~TIM_CCER_CC1P);
- tmpccer |= TIM_OCPolarity;
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 1N polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC1N Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC1NP Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
- tmpccer |= TIM_OCNPolarity;
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 2 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCPolarity: specifies the OC2 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC2P Bit */
- tmpccer &= (uint16_t)(~TIM_CCER_CC2P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 2N polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC2N Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC2NP Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 3 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC3 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC3P Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC3P;
- tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 3N polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC3N Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC3NP Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 4 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC4 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC4P Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC4P;
- tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
- * @retval None
- */
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
-{
- uint16_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_CCX(TIM_CCx));
-
- tmp = CCER_CCE_SET << TIM_Channel;
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t)~ tmp;
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel xN.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
- * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
- * @retval None
- */
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
-{
- uint16_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_CCXN(TIM_CCxN));
-
- tmp = CCER_CCNE_SET << TIM_Channel;
-
- /* Reset the CCxNE Bit */
- TIMx->CCER &= (uint16_t) ~tmp;
-
- /* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group3 Input Capture management functions
- * @brief Input Capture management functions
- *
-@verbatim
- ===============================================================================
- Input Capture management functions
- ===============================================================================
-
- ===================================================================
- TIM Driver: how to use it in Input Capture Mode
- ===================================================================
- To use the Timer in Input Capture mode, the following steps are mandatory:
-
- 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
-
- 2. Configure the TIM pins by configuring the corresponding GPIO pins
-
- 2. Configure the Time base unit as described in the first part of this driver,
- if needed, else the Timer will run with the default configuration:
- - Autoreload value = 0xFFFF
- - Prescaler value = 0x0000
- - Counter mode = Up counting
- - Clock Division = TIM_CKD_DIV1
-
- 3. Fill the TIM_ICInitStruct with the desired parameters including:
- - TIM Channel: TIM_Channel
- - TIM Input Capture polarity: TIM_ICPolarity
- - TIM Input Capture selection: TIM_ICSelection
- - TIM Input Capture Prescaler: TIM_ICPrescaler
- - TIM Input CApture filter value: TIM_ICFilter
-
- 4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the
- corresponding configuration and to measure only frequency or duty cycle of the input signal,
- or,
- Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the
- corresponding configuration and to measure the frequency and the duty cycle of the input signal
-
- 5. Enable the NVIC or the DMA to read the measured frequency.
-
- 6. Enable the corresponding interrupt (or DMA request) to read the Captured value,
- using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
-
- 7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
-
- 8. Use TIM_GetCapturex(TIMx); to read the captured value.
-
- Note1: All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIM peripheral according to the specified parameters
- * in the TIM_ICInitStruct.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
- assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
- assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
-
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
- {
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
- {
- /* TI3 Configuration */
- TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- /* TI4 Configuration */
- TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Fills each TIM_ICInitStruct member with its default value.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Set the default configuration */
- TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
- TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
- TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
- TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
- TIM_ICInitStruct->TIM_ICFilter = 0x00;
-}
-
-/**
- * @brief Configures the TIM peripheral according to the specified parameters
- * in the TIM_ICInitStruct to measure an external PWM signal.
- * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
- uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Select the Opposite Input Polarity */
- if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
- {
- icoppositepolarity = TIM_ICPolarity_Falling;
- }
- else
- {
- icoppositepolarity = TIM_ICPolarity_Rising;
- }
- /* Select the Opposite Input */
- if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
- {
- icoppositeselection = TIM_ICSelection_IndirectTI;
- }
- else
- {
- icoppositeselection = TIM_ICSelection_DirectTI;
- }
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI2 Configuration */
- TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI1 Configuration */
- TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Gets the TIMx Input Capture 1 value.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @retval Capture Compare 1 Register value.
- */
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
-
- /* Get the Capture 1 Register value */
- return TIMx->CCR1;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 2 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @retval Capture Compare 2 Register value.
- */
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Get the Capture 2 Register value */
- return TIMx->CCR2;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 3 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @retval Capture Compare 3 Register value.
- */
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Get the Capture 3 Register value */
- return TIMx->CCR3;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 4 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @retval Capture Compare 4 Register value.
- */
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Get the Capture 4 Register value */
- return TIMx->CCR4;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 1 prescaler.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC1PSC Bits */
- TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC;
-
- /* Set the IC1PSC value */
- TIMx->CCMR1 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 2 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC2PSC Bits */
- TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC;
-
- /* Set the IC2PSC value */
- TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
- * @brief Sets the TIMx Input Capture 3 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC3PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC;
-
- /* Set the IC3PSC value */
- TIMx->CCMR2 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 4 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC4PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC;
-
- /* Set the IC4PSC value */
- TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features
- * @brief Advanced-control timers (TIM1 and TIM8) specific features
- *
-@verbatim
- ===============================================================================
- Advanced-control timers (TIM1 and TIM8) specific features
- ===============================================================================
-
- ===================================================================
- TIM Driver: how to use the Break feature
- ===================================================================
- After configuring the Timer channel(s) in the appropriate Output Compare mode:
-
- 1. Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
- Break Polarity, dead time, Lock level, the OSSI/OSSR State and the
- AOE(automatic output enable).
-
- 2. Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
-
- 3. Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE)
-
- 4. Once the break even occurs, the Timer's output signals are put in reset
- state or in a known state (according to the configuration made in
- TIM_BDTRConfig() function).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
- * and the AOE(automatic output enable).
- * @param TIMx: where x can be 1 or 8 to select the TIM
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
- * contains the BDTR Register configuration information for the TIM peripheral.
- * @retval None
- */
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
- assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
- assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
- assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
- assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
-
- /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
- TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
- TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
- TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
- TIM_BDTRInitStruct->TIM_AutomaticOutput;
-}
-
-/**
- * @brief Fills each TIM_BDTRInitStruct member with its default value.
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
-{
- /* Set the default configuration */
- TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
- TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
- TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
- TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
- TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
- TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
- TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
-}
-
-/**
- * @brief Enables or disables the TIM peripheral Main Outputs.
- * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral.
- * @param NewState: new state of the TIM peripheral Main Outputs.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TIM Main Output */
- TIMx->BDTR |= TIM_BDTR_MOE;
- }
- else
- {
- /* Disable the TIM Main Output */
- TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE;
- }
-}
-
-/**
- * @brief Selects the TIM peripheral Commutation event.
- * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
- * @param NewState: new state of the Commutation event.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the COM Bit */
- TIMx->CR2 |= TIM_CR2_CCUS;
- }
- else
- {
- /* Reset the COM Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS;
- }
-}
-
-/**
- * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
- * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
- * @param NewState: new state of the Capture Compare Preload Control bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the CCPC Bit */
- TIMx->CR2 |= TIM_CR2_CCPC;
- }
- else
- {
- /* Reset the CCPC Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group5 Interrupts DMA and flags management functions
- * @brief Interrupts, DMA and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts, DMA and flags management functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified TIM interrupts.
- * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral.
- * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used
- * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update,
- * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
- * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can
- * be used: TIM_IT_Update or TIM_IT_CC1
- * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8
- *
- * @param NewState: new state of the TIM interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_IT(TIM_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt sources */
- TIMx->DIER |= TIM_IT;
- }
- else
- {
- /* Disable the Interrupt sources */
- TIMx->DIER &= (uint16_t)~TIM_IT;
- }
-}
-
-/**
- * @brief Configures the TIMx event to be generate by software.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_EventSource: specifies the event source.
- * This parameter can be one or more of the following values:
- * @arg TIM_EventSource_Update: Timer update Event source
- * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EventSource_COM: Timer COM event source
- * @arg TIM_EventSource_Trigger: Timer Trigger Event source
- * @arg TIM_EventSource_Break: Timer Break event source
- *
- * @note TIM6 and TIM7 can only generate an update event.
- * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
- *
- * @retval None
- */
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
-
- /* Set the event sources */
- TIMx->EGR = TIM_EventSource;
-}
-
-/**
- * @brief Checks whether the specified TIM flag is set or not.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_COM: TIM Commutation Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_Break: TIM Break Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
- *
- * @note TIM6 and TIM7 can have only one update flag.
- * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
- *
- * @retval The new state of TIM_FLAG (SET or RESET).
- */
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
-
-
- if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's pending flags.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_FLAG: specifies the flag bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_COM: TIM Commutation Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_Break: TIM Break Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
- *
- * @note TIM6 and TIM7 can have only one update flag.
- * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
- *
- * @retval None
- */
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Clear the flags */
- TIMx->SR = (uint16_t)~TIM_FLAG;
-}
-
-/**
- * @brief Checks whether the TIM interrupt has occurred or not.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_IT: specifies the TIM interrupt source to check.
- * This parameter can be one of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note TIM6 and TIM7 can generate only an update interrupt.
- * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
- *
- * @retval The new state of the TIM_IT(SET or RESET).
- */
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itstatus = 0x0, itenable = 0x0;
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_IT(TIM_IT));
-
- itstatus = TIMx->SR & TIM_IT;
-
- itenable = TIMx->DIER & TIM_IT;
- if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's interrupt pending bits.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_IT: specifies the pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM1 update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note TIM6 and TIM7 can generate only an update interrupt.
- * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
- *
- * @retval None
- */
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Clear the IT pending Bit */
- TIMx->SR = (uint16_t)~TIM_IT;
-}
-
-/**
- * @brief Configures the TIMx's DMA interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_DMABase: DMA Base address.
- * This parameter can be one of the following values:
- * @arg TIM_DMABase_CR1
- * @arg TIM_DMABase_CR2
- * @arg TIM_DMABase_SMCR
- * @arg TIM_DMABase_DIER
- * @arg TIM1_DMABase_SR
- * @arg TIM_DMABase_EGR
- * @arg TIM_DMABase_CCMR1
- * @arg TIM_DMABase_CCMR2
- * @arg TIM_DMABase_CCER
- * @arg TIM_DMABase_CNT
- * @arg TIM_DMABase_PSC
- * @arg TIM_DMABase_ARR
- * @arg TIM_DMABase_RCR
- * @arg TIM_DMABase_CCR1
- * @arg TIM_DMABase_CCR2
- * @arg TIM_DMABase_CCR3
- * @arg TIM_DMABase_CCR4
- * @arg TIM_DMABase_BDTR
- * @arg TIM_DMABase_DCR
- * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value
- * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
- * @retval None
- */
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
- assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
-
- /* Set the DMA Base and the DMA Burst Length */
- TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
-}
-
-/**
- * @brief Enables or disables the TIMx's DMA Requests.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
- * @param TIM_DMASource: specifies the DMA Request sources.
- * This parameter can be any combination of the following values:
- * @arg TIM_DMA_Update: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_Trigger: TIM Trigger DMA source
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA sources */
- TIMx->DIER |= TIM_DMASource;
- }
- else
- {
- /* Disable the DMA sources */
- TIMx->DIER &= (uint16_t)~TIM_DMASource;
- }
-}
-
-/**
- * @brief Selects the TIMx peripheral Capture Compare DMA source.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param NewState: new state of the Capture Compare DMA source
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the CCDS Bit */
- TIMx->CR2 |= TIM_CR2_CCDS;
- }
- else
- {
- /* Reset the CCDS Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group6 Clocks management functions
- * @brief Clocks management functions
- *
-@verbatim
- ===============================================================================
- Clocks management functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIMx internal Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @retval None
- */
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Disable slave mode to clock the prescaler directly with the internal clock */
- TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
-}
-
-/**
- * @brief Configures the TIMx Internal Trigger as External Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_InputTriggerSource: Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @retval None
- */
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
-
- /* Select the Internal Trigger */
- TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
-
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the TIMx Trigger as External Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
- * to select the TIM peripheral.
- * @param TIM_TIxExternalCLKSource: Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
- * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
- * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
- * @param TIM_ICPolarity: specifies the TIx Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param ICFilter: specifies the filter value.
- * This parameter must be a value between 0x0 and 0xF.
- * @retval None
- */
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
- uint16_t TIM_ICPolarity, uint16_t ICFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
- assert_param(IS_TIM_IC_FILTER(ICFilter));
-
- /* Configure the Timer Input Clock Source */
- if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
- {
- TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- else
- {
- TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- /* Select the Trigger source */
- TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the External clock Mode1
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the SMS Bits */
- tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
-
- /* Select the External clock mode1 */
- tmpsmcr |= TIM_SlaveMode_External1;
-
- /* Select the Trigger selection : ETRF */
- tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
- tmpsmcr |= TIM_TS_ETRF;
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Configures the External clock Mode2
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-
- /* Enable the External clock mode2 */
- TIMx->SMCR |= TIM_SMCR_ECE;
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group7 Synchronization management functions
- * @brief Synchronization management functions
- *
-@verbatim
- ===============================================================================
- Synchronization management functions
- ===============================================================================
-
- ===================================================================
- TIM Driver: how to use it in synchronization Mode
- ===================================================================
- Case of two/several Timers
- **************************
- 1. Configure the Master Timers using the following functions:
- - void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
- - void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
- 2. Configure the Slave Timers using the following functions:
- - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
- - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-
- Case of Timers and external trigger(ETR pin)
- ********************************************
- 1. Configure the External trigger using this function:
- - void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
- 2. Configure the Slave Timers using the following functions:
- - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
- - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Selects the Input Trigger source
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
- * to select the TIM peripheral.
- * @param TIM_InputTriggerSource: The Input Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the TS Bits */
- tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
-
- /* Set the Input Trigger source */
- tmpsmcr |= TIM_InputTriggerSource;
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Selects the TIMx Trigger Output Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
- *
- * @param TIM_TRGOSource: specifies the Trigger Output source.
- * This parameter can be one of the following values:
- *
- * - For all TIMx
- * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO)
- *
- * - For all TIMx except TIM6 and TIM7
- * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
- * is to be set, as soon as a capture or compare match occurs(TRGO)
- * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO)
- *
- * @retval None
- */
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));
- assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
-
- /* Reset the MMS Bits */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS;
- /* Select the TRGO source */
- TIMx->CR2 |= TIM_TRGOSource;
-}
-
-/**
- * @brief Selects the TIMx Slave Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
- * @param TIM_SlaveMode: specifies the Timer Slave Mode.
- * This parameter can be one of the following values:
- * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize
- * the counter and triggers an update of the registers
- * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high
- * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI
- * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter
- * @retval None
- */
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
-
- /* Reset the SMS Bits */
- TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
-
- /* Select the Slave Mode */
- TIMx->SMCR |= TIM_SlaveMode;
-}
-
-/**
- * @brief Sets or Resets the TIMx Master/Slave Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
- * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
- * This parameter can be one of the following values:
- * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
- * and its slaves (through TRGO)
- * @arg TIM_MasterSlaveMode_Disable: No action
- * @retval None
- */
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
-
- /* Reset the MSM Bit */
- TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM;
-
- /* Set or Reset the MSM Bit */
- TIMx->SMCR |= TIM_MasterSlaveMode;
-}
-
-/**
- * @brief Configures the TIMx External Trigger (ETR).
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the ETR Bits */
- tmpsmcr &= SMCR_ETR_MASK;
-
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group8 Specific interface management functions
- * @brief Specific interface management functions
- *
-@verbatim
- ===============================================================================
- Specific interface management functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIMx Encoder Interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
- * This parameter can be one of the following values:
- * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
- * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
- * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
- * on the level of the other input.
- * @param TIM_IC1Polarity: specifies the IC1 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @param TIM_IC2Polarity: specifies the IC2 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @retval None
- */
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
-{
- uint16_t tmpsmcr = 0;
- uint16_t tmpccmr1 = 0;
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
-
- /* Set the encoder Mode */
- tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
- tmpsmcr |= TIM_EncoderMode;
-
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S);
- tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
-
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P);
- tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Enables or disables the TIMx's Hall sensor interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param NewState: new state of the TIMx Hall sensor interface.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the TI1S Bit */
- TIMx->CR2 |= TIM_CR2_TI1S;
- }
- else
- {
- /* Reset the TI1S Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group9 Specific remapping management function
- * @brief Specific remapping management function
- *
-@verbatim
- ===============================================================================
- Specific remapping management function
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
- * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral.
- * @param TIM_Remap: specifies the TIM input remapping source.
- * This parameter can be one of the following values:
- * @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
- * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output.
- * @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
- * @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
- * @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
- * @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
- * @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
- * @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
- * @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
- * @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock
- * (HSE divided by a programmable prescaler)
- * @retval None
- */
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_REMAP(TIM_Remap));
-
- /* Set the Timer remapping configuration */
- TIMx->OR = TIM_Remap;
-}
-/**
- * @}
- */
-
-/**
- * @brief Configure the TI1 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
- * to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr1 = 0, tmpccer = 0;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input and set the filter */
- tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F);
- tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI2 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 4);
-
- /* Select the Input and set the filter */
- tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
- tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
- tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI3 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 8);
-
- /* Select the Input and set the filter */
- tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F);
- tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI4 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 12);
-
- /* Select the Input and set the filter */
- tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
- tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
- tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
-
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer ;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_usart.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Universal synchronous asynchronous receiver
- * transmitter (USART):
- * - Initialization and Configuration
- * - Data transfers
- * - Multi-Processor Communication
- * - LIN mode
- * - Half-duplex mode
- * - Smartcard mode
- * - IrDA mode
- * - DMA transfers management
- * - Interrupts and flags management
- *
- * @verbatim
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * 1. Enable peripheral clock using the follwoing functions
- * RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6
- * RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, UART4 or UART5.
- *
- * 2. According to the USART mode, enable the GPIO clocks using
- * RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS,
- * or/and SCLK).
- *
- * 3. Peripheral's alternate function:
- * - Connect the pin to the desired peripherals' Alternate
- * Function (AF) using GPIO_PinAFConfig() function
- * - Configure the desired pin in alternate function by:
- * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- * - Select the type, pull-up/pull-down and output speed via
- * GPIO_PuPd, GPIO_OType and GPIO_Speed members
- * - Call GPIO_Init() function
- *
- * 4. Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
- * flow control and Mode(Receiver/Transmitter) using the USART_Init()
- * function.
- *
- * 5. For synchronous mode, enable the clock and program the polarity,
- * phase and last bit using the USART_ClockInit() function.
- *
- * 5. Enable the NVIC and the corresponding interrupt using the function
- * USART_ITConfig() if you need to use interrupt mode.
- *
- * 6. When using the DMA mode
- * - Configure the DMA using DMA_Init() function
- * - Active the needed channel Request using USART_DMACmd() function
- *
- * 7. Enable the USART using the USART_Cmd() function.
- *
- * 8. Enable the DMA using the DMA_Cmd() function, when using DMA mode.
- *
- * Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
- * for more details
- *
- * In order to reach higher communication baudrates, it is possible to
- * enable the oversampling by 8 mode using the function USART_OverSampling8Cmd().
- * This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd())
- * and before calling the function USART_Init().
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_usart.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup USART
- * @brief USART driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */
-#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \
- USART_CR1_PS | USART_CR1_TE | \
- USART_CR1_RE))
-
-/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */
-#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
- USART_CR2_CPHA | USART_CR2_LBCL))
-
-/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */
-#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-
-/*!< USART Interrupts mask */
-#define IT_MASK ((uint16_t)0x001F)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup USART_Private_Functions
- * @{
- */
-
-/** @defgroup USART_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- Initialization and Configuration functions
- ===============================================================================
-
- This subsection provides a set of functions allowing to initialize the USART
- in asynchronous and in synchronous modes.
- - For the asynchronous mode only these parameters can be configured:
- - Baud Rate
- - Word Length
- - Stop Bit
- - Parity: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible USART frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | USART frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
- - Hardware flow control
- - Receiver/transmitter modes
-
- The USART_Init() function follows the USART asynchronous configuration procedure
- (details for the procedure are available in reference manual (RM0090)).
-
- - For the synchronous mode in addition to the asynchronous mode parameters these
- parameters should be also configured:
- - USART Clock Enabled
- - USART polarity
- - USART phase
- - USART LastBit
-
- These parameters can be configured using the USART_ClockInit() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the USARTx peripheral registers to their default reset values.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @retval None
- */
-void USART_DeInit(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- if (USARTx == USART1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
- }
- else if (USARTx == USART2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
- }
- else if (USARTx == USART3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
- }
- else if (USARTx == UART4)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
- }
- else if (USARTx == UART5)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
- }
- else
- {
- if (USARTx == USART6)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the USARTx peripheral according to the specified
- * parameters in the USART_InitStruct .
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains
- * the configuration information for the specified USART peripheral.
- * @retval None
- */
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
-{
- uint32_t tmpreg = 0x00, apbclock = 0x00;
- uint32_t integerdivider = 0x00;
- uint32_t fractionaldivider = 0x00;
- RCC_ClocksTypeDef RCC_ClocksStatus;
-
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
- assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
- assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
- assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
- assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
- assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
-
- /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
- if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
-
- /* Clear STOP[13:12] bits */
- tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
-
- /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit :
- Set STOP[13:12] bits according to USART_StopBits value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
-
- /* Write to USART CR2 */
- USARTx->CR2 = (uint16_t)tmpreg;
-
-/*---------------------------- USART CR1 Configuration -----------------------*/
- tmpreg = USARTx->CR1;
-
- /* Clear M, PCE, PS, TE and RE bits */
- tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);
-
- /* Configure the USART Word Length, Parity and mode:
- Set the M bits according to USART_WordLength value
- Set PCE and PS bits according to USART_Parity value
- Set TE and RE bits according to USART_Mode value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
- USART_InitStruct->USART_Mode;
-
- /* Write to USART CR1 */
- USARTx->CR1 = (uint16_t)tmpreg;
-
-/*---------------------------- USART CR3 Configuration -----------------------*/
- tmpreg = USARTx->CR3;
-
- /* Clear CTSE and RTSE bits */
- tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);
-
- /* Configure the USART HFC :
- Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
- tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
-
- /* Write to USART CR3 */
- USARTx->CR3 = (uint16_t)tmpreg;
-
-/*---------------------------- USART BRR Configuration -----------------------*/
- /* Configure the USART Baud Rate */
- RCC_GetClocksFreq(&RCC_ClocksStatus);
-
- if ((USARTx == USART1) || (USARTx == USART6))
- {
- apbclock = RCC_ClocksStatus.PCLK2_Frequency;
- }
- else
- {
- apbclock = RCC_ClocksStatus.PCLK1_Frequency;
- }
-
- /* Determine the integer part */
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
- {
- /* Integer part computing in case Oversampling mode is 8 Samples */
- integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
- }
- else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */
- {
- /* Integer part computing in case Oversampling mode is 16 Samples */
- integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
- }
- tmpreg = (integerdivider / 100) << 4;
-
- /* Determine the fractional part */
- fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
-
- /* Implement the fractional part in the register */
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
- {
- tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
- }
- else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */
- {
- tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
- }
-
- /* Write to USART BRR register */
- USARTx->BRR = (uint16_t)tmpreg;
-}
-
-/**
- * @brief Fills each USART_InitStruct member with its default value.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
-{
- /* USART_InitStruct members default value */
- USART_InitStruct->USART_BaudRate = 9600;
- USART_InitStruct->USART_WordLength = USART_WordLength_8b;
- USART_InitStruct->USART_StopBits = USART_StopBits_1;
- USART_InitStruct->USART_Parity = USART_Parity_No ;
- USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
- USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-}
-
-/**
- * @brief Initializes the USARTx peripheral Clock according to the
- * specified parameters in the USART_ClockInitStruct .
- * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that
- * contains the configuration information for the specified USART peripheral.
- * @note The Smart Card and Synchronous modes are not available for UART4 and UART5.
- * @retval None
- */
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- uint32_t tmpreg = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_1236_PERIPH(USARTx));
- assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
- assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
- assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
- assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
-
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
- /* Clear CLKEN, CPOL, CPHA and LBCL bits */
- tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);
- /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
- /* Set CLKEN bit according to USART_Clock value */
- /* Set CPOL bit according to USART_CPOL value */
- /* Set CPHA bit according to USART_CPHA value */
- /* Set LBCL bit according to USART_LastBit value */
- tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
- USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
- /* Write to USART CR2 */
- USARTx->CR2 = (uint16_t)tmpreg;
-}
-
-/**
- * @brief Fills each USART_ClockInitStruct member with its default value.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- /* USART_ClockInitStruct members default value */
- USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
- USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
- USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
- USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
-}
-
-/**
- * @brief Enables or disables the specified USART peripheral.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USARTx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected USART by setting the UE bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_UE;
- }
- else
- {
- /* Disable the selected USART by clearing the UE bit in the CR1 register */
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE);
- }
-}
-
-/**
- * @brief Sets the system clock prescaler.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param USART_Prescaler: specifies the prescaler clock.
- * @note The function is used for IrDA mode with UART4 and UART5.
- * @retval None
- */
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Clear the USART prescaler */
- USARTx->GTPR &= USART_GTPR_GT;
- /* Set the USART prescaler */
- USARTx->GTPR |= USART_Prescaler;
-}
-
-/**
- * @brief Enables or disables the USART's 8x oversampling mode.
- * @note This function has to be called before calling USART_Init() function
- * in order to have correct baudrate Divider value.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART 8x oversampling mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_OVER8;
- }
- else
- {
- /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8);
- }
-}
-
-/**
- * @brief Enables or disables the USART's one bit sampling method.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART one bit sampling method.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_ONEBIT;
- }
- else
- {
- /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- Data transfers functions
- ===============================================================================
-
- This subsection provides a set of functions allowing to manage the USART data
- transfers.
-
- During an USART reception, data shifts in least significant bit first through
- the RX pin. In this mode, the USART_DR register consists of a buffer (RDR)
- between the internal bus and the received shift register.
-
- When a transmission is taking place, a write instruction to the USART_DR register
- stores the data in the TDR register and which is copied in the shift register
- at the end of the current transmission.
-
- The read access of the USART_DR register can be done using the USART_ReceiveData()
- function and returns the RDR buffered value. Whereas a write access to the USART_DR
- can be done using USART_SendData() function and stores the written data into
- TDR buffer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmits single data through the USARTx peripheral.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param Data: the data to transmit.
- * @retval None
- */
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DATA(Data));
-
- /* Transmit Data */
- USARTx->DR = (Data & (uint16_t)0x01FF);
-}
-
-/**
- * @brief Returns the most recent received data by the USARTx peripheral.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @retval The received data.
- */
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Receive Data */
- return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group3 MultiProcessor Communication functions
- * @brief Multi-Processor Communication functions
- *
-@verbatim
- ===============================================================================
- Multi-Processor Communication functions
- ===============================================================================
-
- This subsection provides a set of functions allowing to manage the USART
- multiprocessor communication.
-
- For instance one of the USARTs can be the master, its TX output is connected to
- the RX input of the other USART. The others are slaves, their respective TX outputs
- are logically ANDed together and connected to the RX input of the master.
-
- USART multiprocessor communication is possible through the following procedure:
- 1. Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter
- or Mode receiver and hardware flow control values using the USART_Init()
- function.
- 2. Configures the USART address using the USART_SetAddress() function.
- 3. Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark)
- using USART_WakeUpConfig() function only for the slaves.
- 4. Enable the USART using the USART_Cmd() function.
- 5. Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function.
-
- The USART Slave exit from mute mode when receive the wake up condition.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the address of the USART node.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param USART_Address: Indicates the address of the USART node.
- * @retval None
- */
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_ADDRESS(USART_Address));
-
- /* Clear the USART address */
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD);
- /* Set the USART address node */
- USARTx->CR2 |= USART_Address;
-}
-
-/**
- * @brief Determines if the USART is in mute mode or not.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART mute mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the USART mute mode by setting the RWU bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_RWU;
- }
- else
- {
- /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU);
- }
-}
-/**
- * @brief Selects the USART WakeUp method.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param USART_WakeUp: specifies the USART wakeup method.
- * This parameter can be one of the following values:
- * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
- * @arg USART_WakeUp_AddressMark: WakeUp by an address mark
- * @retval None
- */
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_WAKEUP(USART_WakeUp));
-
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE);
- USARTx->CR1 |= USART_WakeUp;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group4 LIN mode functions
- * @brief LIN mode functions
- *
-@verbatim
- ===============================================================================
- LIN mode functions
- ===============================================================================
-
- This subsection provides a set of functions allowing to manage the USART LIN
- Mode communication.
-
- In LIN mode, 8-bit data format with 1 stop bit is required in accordance with
- the LIN standard.
-
- Only this LIN Feature is supported by the USART IP:
- - LIN Master Synchronous Break send capability and LIN slave break detection
- capability : 13-bit break generation and 10/11 bit break detection
-
-
- USART LIN Master transmitter communication is possible through the following procedure:
- 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
- Mode transmitter or Mode receiver and hardware flow control values using
- the USART_Init() function.
- 2. Enable the USART using the USART_Cmd() function.
- 3. Enable the LIN mode using the USART_LINCmd() function.
- 4. Send the break character using USART_SendBreak() function.
-
- USART LIN Master receiver communication is possible through the following procedure:
- 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
- Mode transmitter or Mode receiver and hardware flow control values using
- the USART_Init() function.
- 2. Enable the USART using the USART_Cmd() function.
- 3. Configures the break detection length using the USART_LINBreakDetectLengthConfig()
- function.
- 4. Enable the LIN mode using the USART_LINCmd() function.
-
-
-@note In LIN mode, the following bits must be kept cleared:
- - CLKEN in the USART_CR2 register,
- - STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the USART LIN Break detection length.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param USART_LINBreakDetectLength: specifies the LIN break detection length.
- * This parameter can be one of the following values:
- * @arg USART_LINBreakDetectLength_10b: 10-bit break detection
- * @arg USART_LINBreakDetectLength_11b: 11-bit break detection
- * @retval None
- */
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
-
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL);
- USARTx->CR2 |= USART_LINBreakDetectLength;
-}
-
-/**
- * @brief Enables or disables the USART's LIN mode.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART LIN mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
- USARTx->CR2 |= USART_CR2_LINEN;
- }
- else
- {
- /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN);
- }
-}
-
-/**
- * @brief Transmits break characters.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @retval None
- */
-void USART_SendBreak(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Send break characters */
- USARTx->CR1 |= USART_CR1_SBK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group5 Halfduplex mode function
- * @brief Half-duplex mode function
- *
-@verbatim
- ===============================================================================
- Half-duplex mode function
- ===============================================================================
-
- This subsection provides a set of functions allowing to manage the USART
- Half-duplex communication.
-
- The USART can be configured to follow a single-wire half-duplex protocol where
- the TX and RX lines are internally connected.
-
- USART Half duplex communication is possible through the following procedure:
- 1. Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter
- or Mode receiver and hardware flow control values using the USART_Init()
- function.
- 2. Configures the USART address using the USART_SetAddress() function.
- 3. Enable the USART using the USART_Cmd() function.
- 4. Enable the half duplex mode using USART_HalfDuplexCmd() function.
-
-
-@note The RX pin is no longer used
-@note In Half-duplex mode the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register.
- - SCEN and IREN bits in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the USART's Half Duplex communication.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART Communication.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_HDSEL;
- }
- else
- {
- /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL);
- }
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup USART_Group6 Smartcard mode functions
- * @brief Smartcard mode functions
- *
-@verbatim
- ===============================================================================
- Smartcard mode functions
- ===============================================================================
-
- This subsection provides a set of functions allowing to manage the USART
- Smartcard communication.
-
- The Smartcard interface is designed to support asynchronous protocol Smartcards as
- defined in the ISO 7816-3 standard.
-
- The USART can provide a clock to the smartcard through the SCLK output.
- In smartcard mode, SCLK is not associated to the communication but is simply derived
- from the internal peripheral input clock through a 5-bit prescaler.
-
- Smartcard communication is possible through the following procedure:
- 1. Configures the Smartcard Prescaler using the USART_SetPrescaler() function.
- 2. Configures the Smartcard Guard Time using the USART_SetGuardTime() function.
- 3. Program the USART clock using the USART_ClockInit() function as following:
- - USART Clock enabled
- - USART CPOL Low
- - USART CPHA on first edge
- - USART Last Bit Clock Enabled
- 4. Program the Smartcard interface using the USART_Init() function as following:
- - Word Length = 9 Bits
- - 1.5 Stop Bit
- - Even parity
- - BaudRate = 12096 baud
- - Hardware flow control disabled (RTS and CTS signals)
- - Tx and Rx enabled
- 5. Optionally you can enable the parity error interrupt using the USART_ITConfig()
- function
- 6. Enable the USART using the USART_Cmd() function.
- 7. Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
- 8. Enable the Smartcard interface using the USART_SmartCardCmd() function.
-
- Please refer to the ISO 7816-3 specification for more details.
-
-
-@note It is also possible to choose 0.5 stop bit for receiving but it is recommended
- to use 1.5 stop bits for both transmitting and receiving to avoid switching
- between the two configurations.
-@note In smartcard mode, the following bits must be kept cleared:
- - LINEN bit in the USART_CR2 register.
- - HDSEL and IREN bits in the USART_CR3 register.
-@note Smartcard mode is available on USART peripherals only (not available on UART4
- and UART5 peripherals).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the specified USART guard time.
- * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or
- * UART peripheral.
- * @param USART_GuardTime: specifies the guard time.
- * @retval None
- */
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
-{
- /* Check the parameters */
- assert_param(IS_USART_1236_PERIPH(USARTx));
-
- /* Clear the USART Guard time */
- USARTx->GTPR &= USART_GTPR_PSC;
- /* Set the USART guard time */
- USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
-}
-
-/**
- * @brief Enables or disables the USART's Smart Card mode.
- * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the Smart Card mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_1236_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the SC mode by setting the SCEN bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_SCEN;
- }
- else
- {
- /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN);
- }
-}
-
-/**
- * @brief Enables or disables NACK transmission.
- * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the NACK transmission.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_1236_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_NACK;
- }
- else
- {
- /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group7 IrDA mode functions
- * @brief IrDA mode functions
- *
-@verbatim
- ===============================================================================
- IrDA mode functions
- ===============================================================================
-
- This subsection provides a set of functions allowing to manage the USART
- IrDA communication.
-
- IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
- on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
- is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
- While receiving data, transmission should be avoided as the data to be transmitted
- could be corrupted.
-
- IrDA communication is possible through the following procedure:
- 1. Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver
- modes and hardware flow control values using the USART_Init() function.
- 2. Enable the USART using the USART_Cmd() function.
- 3. Configures the IrDA pulse width by configuring the prescaler using
- the USART_SetPrescaler() function.
- 4. Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode
- using the USART_IrDAConfig() function.
- 5. Enable the IrDA using the USART_IrDACmd() function.
-
-@note A pulse of width less than two and greater than one PSC period(s) may or may
- not be rejected.
-@note The receiver set up time should be managed by software. The IrDA physical layer
- specification specifies a minimum of 10 ms delay between transmission and
- reception (IrDA is a half duplex protocol).
-@note In IrDA mode, the following bits must be kept cleared:
- - LINEN, STOP and CLKEN bits in the USART_CR2 register.
- - SCEN and HDSEL bits in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the USART's IrDA interface.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param USART_IrDAMode: specifies the IrDA mode.
- * This parameter can be one of the following values:
- * @arg USART_IrDAMode_LowPower
- * @arg USART_IrDAMode_Normal
- * @retval None
- */
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
-
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP);
- USARTx->CR3 |= USART_IrDAMode;
-}
-
-/**
- * @brief Enables or disables the USART's IrDA interface.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the IrDA mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_IREN;
- }
- else
- {
- /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group8 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- DMA transfers management functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the USART's DMA interface.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param USART_DMAReq: specifies the DMA request.
- * This parameter can be any combination of the following values:
- * @arg USART_DMAReq_Tx: USART DMA transmit request
- * @arg USART_DMAReq_Rx: USART DMA receive request
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DMAREQ(USART_DMAReq));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA transfer for selected requests by setting the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 |= USART_DMAReq;
- }
- else
- {
- /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 &= (uint16_t)~USART_DMAReq;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group9 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
-
- This subsection provides a set of functions allowing to configure the USART
- Interrupts sources, DMA channels requests and check or clear the flags or
- pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode.
-
- Polling Mode
- =============
- In Polling Mode, the SPI communication can be managed by 10 flags:
- 1. USART_FLAG_TXE : to indicate the status of the transmit buffer register
- 2. USART_FLAG_RXNE : to indicate the status of the receive buffer register
- 3. USART_FLAG_TC : to indicate the status of the transmit operation
- 4. USART_FLAG_IDLE : to indicate the status of the Idle Line
- 5. USART_FLAG_CTS : to indicate the status of the nCTS input
- 6. USART_FLAG_LBD : to indicate the status of the LIN break detection
- 7. USART_FLAG_NE : to indicate if a noise error occur
- 8. USART_FLAG_FE : to indicate if a frame error occur
- 9. USART_FLAG_PE : to indicate if a parity error occur
- 10. USART_FLAG_ORE : to indicate if an Overrun error occur
-
- In this Mode it is advised to use the following functions:
- - FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
- - void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
-
- Interrupt Mode
- ===============
- In Interrupt Mode, the USART communication can be managed by 8 interrupt sources
- and 10 pending bits:
-
- Pending Bits:
- -------------
- 1. USART_IT_TXE : to indicate the status of the transmit buffer register
- 2. USART_IT_RXNE : to indicate the status of the receive buffer register
- 3. USART_IT_TC : to indicate the status of the transmit operation
- 4. USART_IT_IDLE : to indicate the status of the Idle Line
- 5. USART_IT_CTS : to indicate the status of the nCTS input
- 6. USART_IT_LBD : to indicate the status of the LIN break detection
- 7. USART_IT_NE : to indicate if a noise error occur
- 8. USART_IT_FE : to indicate if a frame error occur
- 9. USART_IT_PE : to indicate if a parity error occur
- 10. USART_IT_ORE : to indicate if an Overrun error occur
-
- Interrupt Source:
- -----------------
- 1. USART_IT_TXE : specifies the interrupt source for the Tx buffer empty
- interrupt.
- 2. USART_IT_RXNE : specifies the interrupt source for the Rx buffer not
- empty interrupt.
- 3. USART_IT_TC : specifies the interrupt source for the Transmit complete
- interrupt.
- 4. USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt.
- 5. USART_IT_CTS : specifies the interrupt source for the CTS interrupt.
- 6. USART_IT_LBD : specifies the interrupt source for the LIN break detection
- interrupt.
- 7. USART_IT_PE : specifies the interrupt source for the parity error interrupt.
- 8. USART_IT_ERR : specifies the interrupt source for the errors interrupt.
-
-@note Some parameters are coded in order to use them as interrupt source or as pending bits.
-
- In this Mode it is advised to use the following functions:
- - void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
- - ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
- - void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
-
- DMA Mode
- ========
- In DMA Mode, the USART communication can be managed by 2 DMA Channel requests:
- 1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request
- 2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request
-
- In this Mode it is advised to use the following function:
- - void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified USART interrupts.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @param NewState: new state of the specified USARTx interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
-{
- uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
- uint32_t usartxbase = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CONFIG_IT(USART_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* The CTS interrupt is not available for UART4 and UART5 */
- if (USART_IT == USART_IT_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- usartxbase = (uint32_t)USARTx;
-
- /* Get the USART register index */
- usartreg = (((uint8_t)USART_IT) >> 0x05);
-
- /* Get the interrupt position */
- itpos = USART_IT & IT_MASK;
- itmask = (((uint32_t)0x01) << itpos);
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- usartxbase += 0x0C;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- usartxbase += 0x10;
- }
- else /* The IT is in CR3 register */
- {
- usartxbase += 0x14;
- }
- if (NewState != DISABLE)
- {
- *(__IO uint32_t*)usartxbase |= itmask;
- }
- else
- {
- *(__IO uint32_t*)usartxbase &= ~itmask;
- }
-}
-
-/**
- * @brief Checks whether the specified USART flag is set or not.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param USART_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
- * @arg USART_FLAG_LBD: LIN Break detection flag
- * @arg USART_FLAG_TXE: Transmit data register empty flag
- * @arg USART_FLAG_TC: Transmission Complete flag
- * @arg USART_FLAG_RXNE: Receive data register not empty flag
- * @arg USART_FLAG_IDLE: Idle Line detection flag
- * @arg USART_FLAG_ORE: OverRun Error flag
- * @arg USART_FLAG_NE: Noise Error flag
- * @arg USART_FLAG_FE: Framing Error flag
- * @arg USART_FLAG_PE: Parity Error flag
- * @retval The new state of USART_FLAG (SET or RESET).
- */
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_FLAG(USART_FLAG));
-
- /* The CTS flag is not available for UART4 and UART5 */
- if (USART_FLAG == USART_FLAG_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTx's pending flags.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param USART_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
- * @arg USART_FLAG_LBD: LIN Break detection flag.
- * @arg USART_FLAG_TC: Transmission Complete flag.
- * @arg USART_FLAG_RXNE: Receive data register not empty flag.
- *
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) flags are cleared by software
- * sequence: a read operation to USART_SR register (USART_GetFlagStatus())
- * followed by a read operation to USART_DR register (USART_ReceiveData()).
- * @note RXNE flag can be also cleared by a read to the USART_DR register
- * (USART_ReceiveData()).
- * @note TC flag can be also cleared by software sequence: a read operation to
- * USART_SR register (USART_GetFlagStatus()) followed by a write operation
- * to USART_DR register (USART_SendData()).
- * @note TXE flag is cleared only by a write to the USART_DR register
- * (USART_SendData()).
- *
- * @retval None
- */
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
-
- /* The CTS flag is not available for UART4 and UART5 */
- if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- USARTx->SR = (uint16_t)~USART_FLAG;
-}
-
-/**
- * @brief Checks whether the specified USART interrupt has occurred or not.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param USART_IT: specifies the USART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_ORE: OverRun Error interrupt
- * @arg USART_IT_NE: Noise Error interrupt
- * @arg USART_IT_FE: Framing Error interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @retval The new state of USART_IT (SET or RESET).
- */
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
-{
- uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_GET_IT(USART_IT));
-
- /* The CTS interrupt is not available for UART4 and UART5 */
- if (USART_IT == USART_IT_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- /* Get the USART register index */
- usartreg = (((uint8_t)USART_IT) >> 0x05);
- /* Get the interrupt position */
- itmask = USART_IT & IT_MASK;
- itmask = (uint32_t)0x01 << itmask;
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- itmask &= USARTx->CR1;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- itmask &= USARTx->CR2;
- }
- else /* The IT is in CR3 register */
- {
- itmask &= USARTx->CR3;
- }
-
- bitpos = USART_IT >> 0x08;
- bitpos = (uint32_t)0x01 << bitpos;
- bitpos &= USARTx->SR;
- if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTx's interrupt pending bits.
- * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
- * UART peripheral.
- * @param USART_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TC: Transmission complete interrupt.
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
- *
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) pending bits are cleared by
- * software sequence: a read operation to USART_SR register
- * (USART_GetITStatus()) followed by a read operation to USART_DR register
- * (USART_ReceiveData()).
- * @note RXNE pending bit can be also cleared by a read to the USART_DR register
- * (USART_ReceiveData()).
- * @note TC pending bit can be also cleared by software sequence: a read
- * operation to USART_SR register (USART_GetITStatus()) followed by a write
- * operation to USART_DR register (USART_SendData()).
- * @note TXE pending bit is cleared only by a write to the USART_DR register
- * (USART_SendData()).
- *
- * @retval None
- */
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
-{
- uint16_t bitpos = 0x00, itmask = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_IT(USART_IT));
-
- /* The CTS interrupt is not available for UART4 and UART5 */
- if (USART_IT == USART_IT_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- bitpos = USART_IT >> 0x08;
- itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
- USARTx->SR = (uint16_t)~itmask;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4xx_wwdg.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 25-August-2011
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Window watchdog (WWDG) peripheral:
- * - Prescaler, Refresh window and Counter configuration
- * - WWDG activation
- * - Interrupts and flags management
- *
- * @verbatim
- *
- * ===================================================================
- * WWDG features
- * ===================================================================
- *
- * Once enabled the WWDG generates a system reset on expiry of a programmed
- * time period, unless the program refreshes the counter (downcounter)
- * before to reach 0x3F value (i.e. a reset is generated when the counter
- * value rolls over from 0x40 to 0x3F).
- * An MCU reset is also generated if the counter value is refreshed
- * before the counter has reached the refresh window value. This
- * implies that the counter must be refreshed in a limited window.
- *
- * Once enabled the WWDG cannot be disabled except by a system reset.
- *
- * WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
- * reset occurs.
- *
- * The WWDG counter input clock is derived from the APB clock divided
- * by a programmable prescaler.
- *
- * WWDG counter clock = PCLK1 / Prescaler
- * WWDG timeout = (WWDG counter clock) * (counter value)
- *
- * Min-max timeout value @30 MHz(PCLK1): ~136.5 us / ~69.9 ms
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * 1. Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function
- *
- * 2. Configure the WWDG prescaler using WWDG_SetPrescaler() function
- *
- * 3. Configure the WWDG refresh window using WWDG_SetWindowValue() function
- *
- * 4. Set the WWDG counter value and start it using WWDG_Enable() function.
- * When the WWDG is enabled the counter value should be configured to
- * a value greater than 0x40 to prevent generating an immediate reset.
- *
- * 5. Optionally you can enable the Early wakeup interrupt which is
- * generated when the counter reach 0x40.
- * Once enabled this interrupt cannot be disabled except by a system reset.
- *
- * 6. Then the application program must refresh the WWDG counter at regular
- * intervals during normal operation to prevent an MCU reset, using
- * WWDG_SetCounter() function. This operation must occur only when
- * the counter value is lower than the refresh window value,
- * programmed using WWDG_SetWindowValue().
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_wwdg.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup WWDG
- * @brief WWDG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ----------- WWDG registers bit address in the alias region ----------- */
-#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
-/* Alias word address of EWI bit */
-#define CFR_OFFSET (WWDG_OFFSET + 0x04)
-#define EWI_BitNumber 0x09
-#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
-
-/* --------------------- WWDG registers bit mask ------------------------ */
-/* CFR register bit mask */
-#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
-#define CFR_W_MASK ((uint32_t)0xFFFFFF80)
-#define BIT_MASK ((uint8_t)0x7F)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup WWDG_Private_Functions
- * @{
- */
-
-/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
- * @brief Prescaler, Refresh window and Counter configuration functions
- *
-@verbatim
- ===============================================================================
- Prescaler, Refresh window and Counter configuration functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the WWDG peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void WWDG_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
-}
-
-/**
- * @brief Sets the WWDG Prescaler.
- * @param WWDG_Prescaler: specifies the WWDG Prescaler.
- * This parameter can be one of the following values:
- * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
- * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
- * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
- * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
- * @retval None
- */
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
- /* Clear WDGTB[1:0] bits */
- tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
- /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
- tmpreg |= WWDG_Prescaler;
- /* Store the new value */
- WWDG->CFR = tmpreg;
-}
-
-/**
- * @brief Sets the WWDG window value.
- * @param WindowValue: specifies the window value to be compared to the downcounter.
- * This parameter value must be lower than 0x80.
- * @retval None
- */
-void WWDG_SetWindowValue(uint8_t WindowValue)
-{
- __IO uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
- /* Clear W[6:0] bits */
-
- tmpreg = WWDG->CFR & CFR_W_MASK;
-
- /* Set W[6:0] bits according to WindowValue value */
- tmpreg |= WindowValue & (uint32_t) BIT_MASK;
-
- /* Store the new value */
- WWDG->CFR = tmpreg;
-}
-
-/**
- * @brief Enables the WWDG Early Wakeup interrupt(EWI).
- * @note Once enabled this interrupt cannot be disabled except by a system reset.
- * @param None
- * @retval None
- */
-void WWDG_EnableIT(void)
-{
- *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
-}
-
-/**
- * @brief Sets the WWDG counter value.
- * @param Counter: specifies the watchdog counter value.
- * This parameter must be a number between 0x40 and 0x7F (to prevent generating
- * an immediate reset)
- * @retval None
- */
-void WWDG_SetCounter(uint8_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_WWDG_COUNTER(Counter));
- /* Write to T[6:0] bits to configure the counter value, no need to do
- a read-modify-write; writing a 0 to WDGA bit does nothing */
- WWDG->CR = Counter & BIT_MASK;
-}
-/**
- * @}
- */
-
-/** @defgroup WWDG_Group2 WWDG activation functions
- * @brief WWDG activation functions
- *
-@verbatim
- ===============================================================================
- WWDG activation function
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables WWDG and load the counter value.
- * @param Counter: specifies the watchdog counter value.
- * This parameter must be a number between 0x40 and 0x7F (to prevent generating
- * an immediate reset)
- * @retval None
- */
-void WWDG_Enable(uint8_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_WWDG_COUNTER(Counter));
- WWDG->CR = WWDG_CR_WDGA | Counter;
-}
-/**
- * @}
- */
-
-/** @defgroup WWDG_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the Early Wakeup interrupt flag is set or not.
- * @param None
- * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
- */
-FlagStatus WWDG_GetFlagStatus(void)
-{
- FlagStatus bitstatus = RESET;
-
- if ((WWDG->SR) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears Early Wakeup interrupt flag.
- * @param None
- * @retval None
- */
-void WWDG_ClearFlag(void)
-{
- WWDG->SR = (uint32_t)RESET;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_audio_core.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief header file for the usbd_audio_core.c file.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-
-#ifndef __USB_AUDIO_CORE_H_
-#define __USB_AUDIO_CORE_H_
-
-#include "usbd_ioreq.h"
-#include "usbd_req.h"
-#include "usbd_desc.h"
-
-
-
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup usbd_audio
- * @brief This file is the Header file for USBD_audio.c
- * @{
- */
-
-
-/** @defgroup usbd_audio_Exported_Defines
- * @{
- */
-
-/* AudioFreq * DataSize (2 bytes) * NumChannels (Stereo: 2) */
-#define AUDIO_OUT_PACKET (uint32_t)(((USBD_AUDIO_FREQ * 2 * 2) /1000))
-
-/* Number of sub-packets in the audio transfer buffer. You can modify this value but always make sure
- that it is an even number and higher than 3 */
-#define OUT_PACKET_NUM 4
-/* Total size of the audio transfer buffer */
-#define TOTAL_OUT_BUF_SIZE ((uint32_t)(AUDIO_OUT_PACKET * OUT_PACKET_NUM))
-
-#define AUDIO_CONFIG_DESC_SIZE 109
-#define AUDIO_INTERFACE_DESC_SIZE 9
-#define USB_AUDIO_DESC_SIZ 0x09
-#define AUDIO_STANDARD_ENDPOINT_DESC_SIZE 0x09
-#define AUDIO_STREAMING_ENDPOINT_DESC_SIZE 0x07
-
-#define AUDIO_DESCRIPTOR_TYPE 0x21
-#define USB_DEVICE_CLASS_AUDIO 0x01
-#define AUDIO_SUBCLASS_AUDIOCONTROL 0x01
-#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02
-#define AUDIO_PROTOCOL_UNDEFINED 0x00
-#define AUDIO_STREAMING_GENERAL 0x01
-#define AUDIO_STREAMING_FORMAT_TYPE 0x02
-
-/* Audio Descriptor Types */
-#define AUDIO_INTERFACE_DESCRIPTOR_TYPE 0x24
-#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE 0x25
-
-/* Audio Control Interface Descriptor Subtypes */
-#define AUDIO_CONTROL_HEADER 0x01
-#define AUDIO_CONTROL_INPUT_TERMINAL 0x02
-#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03
-#define AUDIO_CONTROL_FEATURE_UNIT 0x06
-
-#define AUDIO_INPUT_TERMINAL_DESC_SIZE 0x0C
-#define AUDIO_OUTPUT_TERMINAL_DESC_SIZE 0x09
-#define AUDIO_STREAMING_INTERFACE_DESC_SIZE 0x07
-
-#define AUDIO_CONTROL_MUTE 0x0001
-
-#define AUDIO_FORMAT_TYPE_I 0x01
-#define AUDIO_FORMAT_TYPE_III 0x03
-
-#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01
-#define AUDIO_ENDPOINT_GENERAL 0x01
-
-#define AUDIO_REQ_GET_CUR 0x81
-#define AUDIO_REQ_SET_CUR 0x01
-
-#define AUDIO_OUT_STREAMING_CTRL 0x02
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CORE_Exported_TypesDefinitions
- * @{
- */
-typedef struct _Audio_Fops
-{
- uint8_t (*Init) (uint32_t AudioFreq, uint32_t Volume, uint32_t options);
- uint8_t (*DeInit) (uint32_t options);
- uint8_t (*AudioCmd) (uint8_t* pbuf, uint32_t size, uint8_t cmd);
- uint8_t (*VolumeCtl) (uint8_t vol);
- uint8_t (*MuteCtl) (uint8_t cmd);
- uint8_t (*PeriodicTC) (uint8_t cmd);
- uint8_t (*GetState) (void);
-}AUDIO_FOPS_TypeDef;
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_CORE_Exported_Macros
- * @{
- */
-#define AUDIO_PACKET_SZE(frq) (uint8_t)(((frq * 2 * 2)/1000) & 0xFF), \
- (uint8_t)((((frq * 2 * 2)/1000) >> 8) & 0xFF)
-#define SAMPLE_FREQ(frq) (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16))
-/**
- * @}
- */
-
-/** @defgroup USBD_CORE_Exported_Variables
- * @{
- */
-
-extern USBD_Class_cb_TypeDef AUDIO_cb;
-
-/**
- * @}
- */
-
-/** @defgroup USB_CORE_Exported_Functions
- * @{
- */
-/**
- * @}
- */
-
-#endif // __USB_AUDIO_CORE_H_
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_audio_out_if.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief header file for the usbd_audio_out_if.c file.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-
-#ifndef __USB_AUDIO_OUT_IF_H_
-#define __USB_AUDIO_OUT_IF_H_
-
-#ifdef STM32F2XX
- #include "stm322xg_usb_audio_codec.h"
-#elif defined(STM32F10X_CL)
- #include "stm3210c_usb_audio_codec.h"
-#endif /* STM32F2XX */
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup usbd_audio
- * @brief This file is the Header file for USBD_audio.c
- * @{
- */
-
-
-/** @defgroup usbd_audio_Exported_Defines
- * @{
- */
-/* Audio Commands enmueration */
-typedef enum
-{
- AUDIO_CMD_PLAY = 1,
- AUDIO_CMD_PAUSE,
- AUDIO_CMD_STOP,
-}AUDIO_CMD_TypeDef;
-
-/* Mute commands */
-#define AUDIO_MUTE 0x01
-#define AUDIO_UNMUTE 0x00
-
-/* Functions return value */
-#define AUDIO_OK 0x00
-#define AUDIO_FAIL 0xFF
-
-/* Audio Machine States */
-#define AUDIO_STATE_INACTIVE 0x00
-#define AUDIO_STATE_ACTIVE 0x01
-#define AUDIO_STATE_PLAYING 0x02
-#define AUDIO_STATE_PAUSED 0x03
-#define AUDIO_STATE_STOPPED 0x04
-#define AUDIO_STATE_ERROR 0x05
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CORE_Exported_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_CORE_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBD_CORE_Exported_Variables
- * @{
- */
-
-extern AUDIO_FOPS_TypeDef AUDIO_OUT_fops;
-
-/**
- * @}
- */
-
-/** @defgroup USB_CORE_Exported_Functions
- * @{
- */
-/**
- * @}
- */
-
-#endif /* __USB_AUDIO_OUT_IF_H_ */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_audio_core.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief This file provides the high layer firmware functions to manage the
- * following functionalities of the USB Audio Class:
- * - Initialization and Configuration of high and low layer
- * - Enumeration as Audio Streaming Device
- * - Audio Streaming data transfer
- * - AudioControl requests management
- * - Error management
- *
- * @verbatim
- *
- * ===================================================================
- * Audio Class Driver Description
- * ===================================================================
- * This driver manages the Audio Class 1.0 following the "USB Device Class Definition for
- * Audio Devices V1.0 Mar 18, 98".
- * This driver implements the following aspects of the specification:
- * - Device descriptor management
- * - Configuration descriptor management
- * - Standard AC Interface Descriptor management
- * - 1 Audio Streaming Interface (with single channel, PCM, Stereo mode)
- * - 1 Audio Streaming Endpoint
- * - 1 Audio Terminal Input (1 channel)
- * - Audio Class-Specific AC Interfaces
- * - Audio Class-Specific AS Interfaces
- * - AudioControl Requests: only SET_CUR and GET_CUR requests are supported (for Mute)
- * - Audio Feature Unit (limited to Mute control)
- * - Audio Synchronization type: Asynchronous
- * - Single fixed audio sampling rate (configurable in usbd_conf.h file)
- *
- * @note
- * The Audio Class 1.0 is based on USB Specification 1.0 and thus supports only
- * Low and Full speed modes and does not allow High Speed transfers.
- * Please refer to "USB Device Class Definition for Audio Devices V1.0 Mar 18, 98"
- * for more details.
- *
- * These aspects may be enriched or modified for a specific user application.
- *
- * This driver doesn't implement the following aspects of the specification
- * (but it is possible to manage these features with some modifications on this driver):
- * - AudioControl Endpoint management
- * - AudioControl requsests other than SET_CUR and GET_CUR
- * - Abstraction layer for AudioControl requests (only Mute functionality is managed)
- * - Audio Synchronization type: Adaptive
- * - Audio Compression modules and interfaces
- * - MIDI interfaces and modules
- * - Mixer/Selector/Processing/Extension Units (Feature unit is limited to Mute control)
- * - Any other application-specific modules
- * - Multiple and Variable audio sampling rates
- * - Out Streaming Endpoint/Interface (microphone)
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-
-#include "usbd_audio_core.h"
-#include "usbd_audio_out_if.h"
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup usbd_audio
- * @brief usbd core module
- * @{
- */
-
-/** @defgroup usbd_audio_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup usbd_audio_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup usbd_audio_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup usbd_audio_Private_FunctionPrototypes
- * @{
- */
-
-/*********************************************
- AUDIO Device library callbacks
- *********************************************/
-static uint8_t usbd_audio_Init (void *pdev, uint8_t cfgidx);
-static uint8_t usbd_audio_DeInit (void *pdev, uint8_t cfgidx);
-static uint8_t usbd_audio_Setup (void *pdev, USB_SETUP_REQ *req);
-static uint8_t usbd_audio_EP0_RxReady(void *pdev);
-static uint8_t usbd_audio_DataIn (void *pdev, uint8_t epnum);
-static uint8_t usbd_audio_DataOut (void *pdev, uint8_t epnum);
-static uint8_t usbd_audio_SOF (void *pdev);
-static uint8_t usbd_audio_OUT_Incplt (void *pdev);
-
-/*********************************************
- AUDIO Requests management functions
- *********************************************/
-static void AUDIO_Req_GetCurrent(void *pdev, USB_SETUP_REQ *req);
-static void AUDIO_Req_SetCurrent(void *pdev, USB_SETUP_REQ *req);
-static uint8_t *USBD_audio_GetCfgDesc (uint8_t speed, uint16_t *length);
-/**
- * @}
- */
-
-/** @defgroup usbd_audio_Private_Variables
- * @{
- */
-/* Main Buffer for Audio Data Out transfers and its relative pointers */
-uint8_t IsocOutBuff [TOTAL_OUT_BUF_SIZE * 2];
-uint8_t* IsocOutWrPtr = IsocOutBuff;
-uint8_t* IsocOutRdPtr = IsocOutBuff;
-
-/* Main Buffer for Audio Control Rrequests transfers and its relative variables */
-uint8_t AudioCtl[64];
-uint8_t AudioCtlCmd = 0;
-uint32_t AudioCtlLen = 0;
-uint8_t AudioCtlUnit = 0;
-
-static uint32_t PlayFlag = 0;
-
-static __IO uint32_t usbd_audio_AltSet = 0;
-static uint8_t usbd_audio_CfgDesc[AUDIO_CONFIG_DESC_SIZE];
-
-/* AUDIO interface class callbacks structure */
-USBD_Class_cb_TypeDef AUDIO_cb =
-{
- usbd_audio_Init,
- usbd_audio_DeInit,
- usbd_audio_Setup,
- NULL, /* EP0_TxSent */
- usbd_audio_EP0_RxReady,
- usbd_audio_DataIn,
- usbd_audio_DataOut,
- usbd_audio_SOF,
- NULL,
- usbd_audio_OUT_Incplt,
- USBD_audio_GetCfgDesc,
-#ifdef USB_OTG_HS_CORE
- USBD_audio_GetCfgDesc, /* use same config as per FS */
-#endif
-};
-
-/* USB AUDIO device Configuration Descriptor */
-static uint8_t usbd_audio_CfgDesc[AUDIO_CONFIG_DESC_SIZE] =
-{
- /* Configuration 1 */
- 0x09, /* bLength */
- USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */
- LOBYTE(AUDIO_CONFIG_DESC_SIZE), /* wTotalLength 109 bytes*/
- HIBYTE(AUDIO_CONFIG_DESC_SIZE),
- 0x02, /* bNumInterfaces */
- 0x01, /* bConfigurationValue */
- 0x00, /* iConfiguration */
- 0xC0, /* bmAttributes BUS Powred*/
- 0x32, /* bMaxPower = 100 mA*/
- /* 09 byte*/
-
- /* USB Speaker Standard interface descriptor */
- AUDIO_INTERFACE_DESC_SIZE, /* bLength */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- 0x00, /* bInterfaceNumber */
- 0x00, /* bAlternateSetting */
- 0x00, /* bNumEndpoints */
- USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */
- AUDIO_SUBCLASS_AUDIOCONTROL, /* bInterfaceSubClass */
- AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */
- 0x00, /* iInterface */
- /* 09 byte*/
-
- /* USB Speaker Class-specific AC Interface Descriptor */
- AUDIO_INTERFACE_DESC_SIZE, /* bLength */
- AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_CONTROL_HEADER, /* bDescriptorSubtype */
- 0x00, /* 1.00 */ /* bcdADC */
- 0x01,
- 0x27, /* wTotalLength = 39*/
- 0x00,
- 0x01, /* bInCollection */
- 0x01, /* baInterfaceNr */
- /* 09 byte*/
-
- /* USB Speaker Input Terminal Descriptor */
- AUDIO_INPUT_TERMINAL_DESC_SIZE, /* bLength */
- AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_CONTROL_INPUT_TERMINAL, /* bDescriptorSubtype */
- 0x01, /* bTerminalID */
- 0x01, /* wTerminalType AUDIO_TERMINAL_USB_STREAMING 0x0101 */
- 0x01,
- 0x00, /* bAssocTerminal */
- 0x01, /* bNrChannels */
- 0x00, /* wChannelConfig 0x0000 Mono */
- 0x00,
- 0x00, /* iChannelNames */
- 0x00, /* iTerminal */
- /* 12 byte*/
-
- /* USB Speaker Audio Feature Unit Descriptor */
- 0x09, /* bLength */
- AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_CONTROL_FEATURE_UNIT, /* bDescriptorSubtype */
- AUDIO_OUT_STREAMING_CTRL, /* bUnitID */
- 0x01, /* bSourceID */
- 0x01, /* bControlSize */
- AUDIO_CONTROL_MUTE, /* bmaControls(0) */
- 0x00, /* bmaControls(1) */
- 0x00, /* iTerminal */
- /* 09 byte*/
-
- /*USB Speaker Output Terminal Descriptor */
- 0x09, /* bLength */
- AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_CONTROL_OUTPUT_TERMINAL, /* bDescriptorSubtype */
- 0x03, /* bTerminalID */
- 0x01, /* wTerminalType 0x0301*/
- 0x03,
- 0x00, /* bAssocTerminal */
- 0x02, /* bSourceID */
- 0x00, /* iTerminal */
- /* 09 byte*/
-
- /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Zero Bandwith */
- /* Interface 1, Alternate Setting 0 */
- AUDIO_INTERFACE_DESC_SIZE, /* bLength */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- 0x01, /* bInterfaceNumber */
- 0x00, /* bAlternateSetting */
- 0x00, /* bNumEndpoints */
- USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */
- AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */
- AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */
- 0x00, /* iInterface */
- /* 09 byte*/
-
- /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Operational */
- /* Interface 1, Alternate Setting 1 */
- AUDIO_INTERFACE_DESC_SIZE, /* bLength */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- 0x01, /* bInterfaceNumber */
- 0x01, /* bAlternateSetting */
- 0x01, /* bNumEndpoints */
- USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */
- AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */
- AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */
- 0x00, /* iInterface */
- /* 09 byte*/
-
- /* USB Speaker Audio Streaming Interface Descriptor */
- AUDIO_STREAMING_INTERFACE_DESC_SIZE, /* bLength */
- AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */
- 0x01, /* bTerminalLink */
- 0x01, /* bDelay */
- 0x01, /* wFormatTag AUDIO_FORMAT_PCM 0x0001*/
- 0x00,
- /* 07 byte*/
-
- /* USB Speaker Audio Type III Format Interface Descriptor */
- 0x0B, /* bLength */
- AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */
- AUDIO_FORMAT_TYPE_III, /* bFormatType */
- 0x02, /* bNrChannels */
- 0x02, /* bSubFrameSize : 2 Bytes per frame (16bits) */
- 16, /* bBitResolution (16-bits per sample) */
- 0x01, /* bSamFreqType only one frequency supported */
- SAMPLE_FREQ(USBD_AUDIO_FREQ), /* Audio sampling frequency coded on 3 bytes */
- /* 11 byte*/
-
- /* Endpoint 1 - Standard Descriptor */
- AUDIO_STANDARD_ENDPOINT_DESC_SIZE, /* bLength */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_OUT_EP, /* bEndpointAddress 1 out endpoint*/
- USB_ENDPOINT_TYPE_ISOCHRONOUS, /* bmAttributes */
- AUDIO_PACKET_SZE(USBD_AUDIO_FREQ), /* wMaxPacketSize in Bytes (Freq(Samples)*2(Stereo)*2(HalfWord)) */
- 0x01, /* bInterval */
- 0x00, /* bRefresh */
- 0x00, /* bSynchAddress */
- /* 09 byte*/
-
- /* Endpoint - Audio Streaming Descriptor*/
- AUDIO_STREAMING_ENDPOINT_DESC_SIZE, /* bLength */
- AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_ENDPOINT_GENERAL, /* bDescriptor */
- 0x00, /* bmAttributes */
- 0x00, /* bLockDelayUnits */
- 0x00, /* wLockDelay */
- 0x00,
- /* 07 byte*/
-} ;
-
-/**
- * @}
- */
-
-/** @defgroup usbd_audio_Private_Functions
- * @{
- */
-
-/**
-* @brief usbd_audio_Init
-* Initilaizes the AUDIO interface.
-* @param pdev: device instance
-* @param cfgidx: Configuration index
-* @retval status
-*/
-static uint8_t usbd_audio_Init (void *pdev,
- uint8_t cfgidx)
-{
- /* Open EP OUT */
- DCD_EP_Open(pdev,
- AUDIO_OUT_EP,
- AUDIO_OUT_PACKET,
- USB_OTG_EP_ISOC);
-
- /* Initialize the Audio output Hardware layer */
- if (AUDIO_OUT_fops.Init(USBD_AUDIO_FREQ, DEFAULT_VOLUME, 0) != USBD_OK)
- {
- return USBD_FAIL;
- }
-
- /* Prepare Out endpoint to receive audio data */
- DCD_EP_PrepareRx(pdev,
- AUDIO_OUT_EP,
- (uint8_t*)IsocOutBuff,
- AUDIO_OUT_PACKET);
-
- return USBD_OK;
-}
-
-/**
-* @brief usbd_audio_Init
-* DeInitializes the AUDIO layer.
-* @param pdev: device instance
-* @param cfgidx: Configuration index
-* @retval status
-*/
-static uint8_t usbd_audio_DeInit (void *pdev,
- uint8_t cfgidx)
-{
- DCD_EP_Close (pdev , AUDIO_OUT_EP);
-
- /* DeInitialize the Audio output Hardware layer */
- if (AUDIO_OUT_fops.DeInit(0) != USBD_OK)
- {
- return USBD_FAIL;
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_audio_Setup
- * Handles the Audio control request parsing.
- * @param pdev: instance
- * @param req: usb requests
- * @retval status
- */
-static uint8_t usbd_audio_Setup (void *pdev,
- USB_SETUP_REQ *req)
-{
- uint16_t len;
- uint8_t *pbuf;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
- /* AUDIO Class Requests -------------------------------*/
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest)
- {
- case AUDIO_REQ_GET_CUR:
- AUDIO_Req_GetCurrent(pdev, req);
- break;
-
- case AUDIO_REQ_SET_CUR:
- AUDIO_Req_SetCurrent(pdev, req);
- break;
-
- default:
- USBD_CtlError (pdev, req);
- return USBD_FAIL;
- }
- break;
-
- /* Standard Requests -------------------------------*/
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_DESCRIPTOR:
- if( (req->wValue >> 8) == AUDIO_DESCRIPTOR_TYPE)
- {
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- pbuf = usbd_audio_Desc;
-#else
- pbuf = usbd_audio_CfgDesc + 18;
-#endif
- len = MIN(USB_AUDIO_DESC_SIZ , req->wLength);
- }
-
- USBD_CtlSendData (pdev,
- pbuf,
- len);
- break;
-
- case USB_REQ_GET_INTERFACE :
- USBD_CtlSendData (pdev,
- (uint8_t *)&usbd_audio_AltSet,
- 1);
- break;
-
- case USB_REQ_SET_INTERFACE :
- if ((uint8_t)(req->wValue) < AUDIO_TOTAL_IF_NUM)
- {
- usbd_audio_AltSet = (uint8_t)(req->wValue);
- }
- else
- {
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- break;
- }
- }
- return USBD_OK;
-}
-
-/**
- * @brief usbd_audio_EP0_RxReady
- * Handles audio control requests data.
- * @param pdev: device device instance
- * @retval status
- */
-static uint8_t usbd_audio_EP0_RxReady (void *pdev)
-{
- /* Check if an AudioControl request has been issued */
- if (AudioCtlCmd == AUDIO_REQ_SET_CUR)
- {/* In this driver, to simplify code, only SET_CUR request is managed */
- /* Check for which addressed unit the AudioControl request has been issued */
- if (AudioCtlUnit == AUDIO_OUT_STREAMING_CTRL)
- {/* In this driver, to simplify code, only one unit is manage */
- /* Call the audio interface mute function */
- AUDIO_OUT_fops.MuteCtl(AudioCtl[0]);
-
- /* Reset the AudioCtlCmd variable to prevent re-entering this function */
- AudioCtlCmd = 0;
- AudioCtlLen = 0;
- }
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_audio_DataIn
- * Handles the audio IN data stage.
- * @param pdev: instance
- * @param epnum: endpoint number
- * @retval status
- */
-static uint8_t usbd_audio_DataIn (void *pdev, uint8_t epnum)
-{
- return USBD_OK;
-}
-
-/**
- * @brief usbd_audio_DataOut
- * Handles the Audio Out data stage.
- * @param pdev: instance
- * @param epnum: endpoint number
- * @retval status
- */
-static uint8_t usbd_audio_DataOut (void *pdev, uint8_t epnum)
-{
- if (epnum == AUDIO_OUT_EP)
- {
- /* Increment the Buffer pointer or roll it back when all buffers are full */
- if (IsocOutWrPtr >= (IsocOutBuff + (AUDIO_OUT_PACKET * OUT_PACKET_NUM)))
- {/* All buffers are full: roll back */
- IsocOutWrPtr = IsocOutBuff;
- }
- else
- {/* Increment the buffer pointer */
- IsocOutWrPtr += AUDIO_OUT_PACKET;
- }
-
- /* Toggle the frame index */
- ((USB_OTG_CORE_HANDLE*)pdev)->dev.out_ep[epnum].even_odd_frame =
- (((USB_OTG_CORE_HANDLE*)pdev)->dev.out_ep[epnum].even_odd_frame)? 0:1;
-
- /* Prepare Out endpoint to receive next audio packet */
- DCD_EP_PrepareRx(pdev,
- AUDIO_OUT_EP,
- (uint8_t*)(IsocOutWrPtr),
- AUDIO_OUT_PACKET);
-
- /* Trigger the start of streaming only when half buffer is full */
- if ((PlayFlag == 0) && (IsocOutWrPtr >= (IsocOutBuff + ((AUDIO_OUT_PACKET * OUT_PACKET_NUM) / 2))))
- {
- /* Enable start of Streaming */
- PlayFlag = 1;
- }
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_audio_SOF
- * Handles the SOF event (data buffer update and synchronization).
- * @param pdev: instance
- * @param epnum: endpoint number
- * @retval status
- */
-static uint8_t usbd_audio_SOF (void *pdev)
-{
- /* Check if there are available data in stream buffer.
- In this function, a single variable (PlayFlag) is used to avoid software delays.
- The play operation must be executed as soon as possible after the SOF detection. */
- if (PlayFlag)
- {
- /* Start playing received packet */
- AUDIO_OUT_fops.AudioCmd((uint8_t*)(IsocOutRdPtr), /* Samples buffer pointer */
- AUDIO_OUT_PACKET, /* Number of samples in Bytes */
- AUDIO_CMD_PLAY); /* Command to be processed */
-
- /* Increment the Buffer pointer or roll it back when all buffers all full */
- if (IsocOutRdPtr >= (IsocOutBuff + (AUDIO_OUT_PACKET * OUT_PACKET_NUM)))
- {/* Roll back to the start of buffer */
- IsocOutRdPtr = IsocOutBuff;
- }
- else
- {/* Increment to the next sub-buffer */
- IsocOutRdPtr += AUDIO_OUT_PACKET;
- }
-
- /* If all available buffers have been consumed, stop playing */
- if (IsocOutRdPtr == IsocOutWrPtr)
- {
- /* Pause the audio stream */
- AUDIO_OUT_fops.AudioCmd((uint8_t*)(IsocOutBuff), /* Samples buffer pointer */
- AUDIO_OUT_PACKET, /* Number of samples in Bytes */
- AUDIO_CMD_PAUSE); /* Command to be processed */
-
- /* Stop entering play loop */
- PlayFlag = 0;
-
- /* Reset buffer pointers */
- IsocOutRdPtr = IsocOutBuff;
- IsocOutWrPtr = IsocOutBuff;
- }
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_audio_OUT_Incplt
- * Handles the iso out incomplete event.
- * @param pdev: instance
- * @retval status
- */
-static uint8_t usbd_audio_OUT_Incplt (void *pdev)
-{
- return USBD_OK;
-}
-
-/******************************************************************************
- AUDIO Class requests management
-******************************************************************************/
-/**
- * @brief AUDIO_Req_GetCurrent
- * Handles the GET_CUR Audio control request.
- * @param pdev: instance
- * @param req: setup class request
- * @retval status
- */
-static void AUDIO_Req_GetCurrent(void *pdev, USB_SETUP_REQ *req)
-{
- /* Send the current mute state */
- USBD_CtlSendData (pdev,
- AudioCtl,
- req->wLength);
-}
-
-/**
- * @brief AUDIO_Req_SetCurrent
- * Handles the SET_CUR Audio control request.
- * @param pdev: instance
- * @param req: setup class request
- * @retval status
- */
-static void AUDIO_Req_SetCurrent(void *pdev, USB_SETUP_REQ *req)
-{
- if (req->wLength)
- {
- /* Prepare the reception of the buffer over EP0 */
- USBD_CtlPrepareRx (pdev,
- AudioCtl,
- req->wLength);
-
- /* Set the global variables indicating current request and its length
- to the function usbd_audio_EP0_RxReady() which will process the request */
- AudioCtlCmd = AUDIO_REQ_SET_CUR; /* Set the request value */
- AudioCtlLen = req->wLength; /* Set the request data length */
- AudioCtlUnit = HIBYTE(req->wIndex); /* Set the request target unit */
- }
-}
-
-/**
- * @brief USBD_audio_GetCfgDesc
- * Returns configuration descriptor.
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_audio_GetCfgDesc (uint8_t speed, uint16_t *length)
-{
- *length = sizeof (usbd_audio_CfgDesc);
- return usbd_audio_CfgDesc;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_audio_out_if.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief This file provides the Audio Out (palyback) interface API.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_audio_core.h"
-#include "usbd_audio_out_if.h"
-
-
-
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup usbd_audio_out_if
- * @brief usbd out interface module
- * @{
- */
-
-/** @defgroup usbd_audio_out_if_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup usbd_audio_out_if_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup usbd_audio_out_if_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup usbd_audio_out_if_Private_FunctionPrototypes
- * @{
- */
-static uint8_t Init (uint32_t AudioFreq, uint32_t Volume, uint32_t options);
-static uint8_t DeInit (uint32_t options);
-static uint8_t AudioCmd (uint8_t* pbuf, uint32_t size, uint8_t cmd);
-static uint8_t VolumeCtl (uint8_t vol);
-static uint8_t MuteCtl (uint8_t cmd);
-static uint8_t PeriodicTC (uint8_t cmd);
-static uint8_t GetState (void);
-
-/**
- * @}
- */
-
-/** @defgroup usbd_audio_out_if_Private_Variables
- * @{
- */
-AUDIO_FOPS_TypeDef AUDIO_OUT_fops =
-{
- Init,
- DeInit,
- AudioCmd,
- VolumeCtl,
- MuteCtl,
- PeriodicTC,
- GetState
-};
-
-static uint8_t AudioState = AUDIO_STATE_INACTIVE;
-
-/**
- * @}
- */
-
-/** @defgroup usbd_audio_out_if_Private_Functions
- * @{
- */
-
-/**
- * @brief Init
- * Initialize and configures all required resources for audio play function.
- * @param AudioFreq: Statrtup audio frequency.
- * @param Volume: Startup volume to be set.
- * @param options: specific options passed to low layer function.
- * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else.
- */
-static uint8_t Init (uint32_t AudioFreq,
- uint32_t Volume,
- uint32_t options)
-{
- static uint32_t Initialized = 0;
-
- /* Check if the low layer has already been initialized */
- if (Initialized == 0)
- {
- /* Call low layer function */
- if (EVAL_AUDIO_Init(OUTPUT_DEVICE_AUTO, Volume, AudioFreq) != 0)
- {
- AudioState = AUDIO_STATE_ERROR;
- return AUDIO_FAIL;
- }
-
- /* Set the Initialization flag to prevent reinitializing the interface again */
- Initialized = 1;
- }
-
- /* Update the Audio state machine */
- AudioState = AUDIO_STATE_ACTIVE;
-
- return AUDIO_OK;
-}
-
-/**
- * @brief DeInit
- * Free all resources used by low layer and stops audio-play function.
- * @param options: options passed to low layer function.
- * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else.
- */
-static uint8_t DeInit (uint32_t options)
-{
- /* Update the Audio state machine */
- AudioState = AUDIO_STATE_INACTIVE;
-
- return AUDIO_OK;
-}
-
-/**
- * @brief AudioCmd
- * Play, Stop, Pause or Resume current file.
- * @param pbuf: address from which file shoud be played.
- * @param size: size of the current buffer/file.
- * @param cmd: command to be executed, can be AUDIO_CMD_PLAY , AUDIO_CMD_PAUSE,
- * AUDIO_CMD_RESUME or AUDIO_CMD_STOP.
- * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else.
- */
-static uint8_t AudioCmd(uint8_t* pbuf,
- uint32_t size,
- uint8_t cmd)
-{
- /* Check the current state */
- if ((AudioState == AUDIO_STATE_INACTIVE) || (AudioState == AUDIO_STATE_ERROR))
- {
- AudioState = AUDIO_STATE_ERROR;
- return AUDIO_FAIL;
- }
-
- switch (cmd)
- {
- /* Process the PLAY command ----------------------------*/
- case AUDIO_CMD_PLAY:
- /* If current state is Active or Stopped */
- if ((AudioState == AUDIO_STATE_ACTIVE) || \
- (AudioState == AUDIO_STATE_STOPPED) || \
- (AudioState == AUDIO_STATE_PLAYING))
- {
- Audio_MAL_Play((uint32_t)pbuf, (size/2));
- AudioState = AUDIO_STATE_PLAYING;
- return AUDIO_OK;
- }
- /* If current state is Paused */
- else if (AudioState == AUDIO_STATE_PAUSED)
- {
- if (EVAL_AUDIO_PauseResume(AUDIO_RESUME, (uint32_t)pbuf, (size/2)) != 0)
- {
- AudioState = AUDIO_STATE_ERROR;
- return AUDIO_FAIL;
- }
- else
- {
- AudioState = AUDIO_STATE_PLAYING;
- return AUDIO_OK;
- }
- }
- else /* Not allowed command */
- {
- return AUDIO_FAIL;
- }
-
- /* Process the STOP command ----------------------------*/
- case AUDIO_CMD_STOP:
- if (AudioState != AUDIO_STATE_PLAYING)
- {
- /* Unsupported command */
- return AUDIO_FAIL;
- }
- else if (EVAL_AUDIO_Stop(CODEC_PDWN_SW) != 0)
- {
- AudioState = AUDIO_STATE_ERROR;
- return AUDIO_FAIL;
- }
- else
- {
- AudioState = AUDIO_STATE_STOPPED;
- return AUDIO_OK;
- }
-
- /* Process the PAUSE command ---------------------------*/
- case AUDIO_CMD_PAUSE:
- if (AudioState != AUDIO_STATE_PLAYING)
- {
- /* Unsupported command */
- return AUDIO_FAIL;
- }
- else if (EVAL_AUDIO_PauseResume(AUDIO_PAUSE, (uint32_t)pbuf, (size/2)) != 0)
- {
- AudioState = AUDIO_STATE_ERROR;
- return AUDIO_FAIL;
- }
- else
- {
- AudioState = AUDIO_STATE_PAUSED;
- return AUDIO_OK;
- }
-
- /* Unsupported command ---------------------------------*/
- default:
- return AUDIO_FAIL;
- }
-}
-
-/**
- * @brief VolumeCtl
- * Set the volume level in %
- * @param vol: volume level to be set in % (from 0% to 100%)
- * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else.
- */
-static uint8_t VolumeCtl (uint8_t vol)
-{
- /* Call low layer volume setting function */
- if (EVAL_AUDIO_VolumeCtl(vol) != 0)
- {
- AudioState = AUDIO_STATE_ERROR;
- return AUDIO_FAIL;
- }
-
- return AUDIO_OK;
-}
-
-/**
- * @brief MuteCtl
- * Mute or Unmute the audio current output
- * @param cmd: can be 0 to unmute, or 1 to mute.
- * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else.
- */
-static uint8_t MuteCtl (uint8_t cmd)
-{
- /* Call low layer mute setting function */
- if (EVAL_AUDIO_Mute(cmd) != 0)
- {
- AudioState = AUDIO_STATE_ERROR;
- return AUDIO_FAIL;
- }
-
- return AUDIO_OK;
-}
-
-/**
- * @brief
- *
- * @param
- * @param
- * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else.
- */
-static uint8_t PeriodicTC (uint8_t cmd)
-{
-
-
- return AUDIO_OK;
-}
-
-
-/**
- * @brief GetState
- * Return the current state of the audio machine
- * @param None
- * @retval Current State.
- */
-static uint8_t GetState (void)
-{
- return AudioState;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_cdc_core.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief header file for the usbd_cdc_core.c file.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-
-#ifndef __USB_CDC_CORE_H_
-#define __USB_CDC_CORE_H_
-
-#include "usbd_ioreq.h"
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup usbd_cdc
- * @brief This file is the Header file for USBD_cdc.c
- * @{
- */
-
-
-/** @defgroup usbd_cdc_Exported_Defines
- * @{
- */
-#define USB_CDC_CONFIG_DESC_SIZ (67)
-#define USB_CDC_DESC_SIZ (67-9)
-
-#define CDC_DESCRIPTOR_TYPE 0x21
-
-#define DEVICE_CLASS_CDC 0x02
-#define DEVICE_SUBCLASS_CDC 0x00
-
-
-#define USB_DEVICE_DESCRIPTOR_TYPE 0x01
-#define USB_CONFIGURATION_DESCRIPTOR_TYPE 0x02
-#define USB_STRING_DESCRIPTOR_TYPE 0x03
-#define USB_INTERFACE_DESCRIPTOR_TYPE 0x04
-#define USB_ENDPOINT_DESCRIPTOR_TYPE 0x05
-
-#define STANDARD_ENDPOINT_DESC_SIZE 0x09
-
-#define CDC_DATA_IN_PACKET_SIZE *(uint16_t *)(((USB_OTG_CORE_HANDLE *)pdev)->dev.pConfig_descriptor + 57)
-
-#define CDC_DATA_OUT_PACKET_SIZE *(uint16_t *)(((USB_OTG_CORE_HANDLE *)pdev)->dev.pConfig_descriptor + 64)
-
-/*---------------------------------------------------------------------*/
-/* CDC definitions */
-/*---------------------------------------------------------------------*/
-
-/**************************************************/
-/* CDC Requests */
-/**************************************************/
-#define SEND_ENCAPSULATED_COMMAND 0x00
-#define GET_ENCAPSULATED_RESPONSE 0x01
-#define SET_COMM_FEATURE 0x02
-#define GET_COMM_FEATURE 0x03
-#define CLEAR_COMM_FEATURE 0x04
-#define SET_LINE_CODING 0x20
-#define GET_LINE_CODING 0x21
-#define SET_CONTROL_LINE_STATE 0x22
-#define SEND_BREAK 0x23
-#define NO_CMD 0xFF
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CORE_Exported_TypesDefinitions
- * @{
- */
-typedef struct _CDC_IF_PROP
-{
- uint16_t (*pIf_Init) (void);
- uint16_t (*pIf_DeInit) (void);
- uint16_t (*pIf_Ctrl) (uint32_t Cmd, uint8_t* Buf, uint32_t Len);
- uint16_t (*pIf_DataTx) (uint8_t* Buf, uint32_t Len);
- uint16_t (*pIf_DataRx) (uint8_t* Buf, uint32_t Len);
-}
-CDC_IF_Prop_TypeDef;
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_CORE_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_CORE_Exported_Variables
- * @{
- */
-
-extern USBD_Class_cb_TypeDef USBD_CDC_cb;
-/**
- * @}
- */
-
-/** @defgroup USB_CORE_Exported_Functions
- * @{
- */
-/**
- * @}
- */
-
-#endif // __USB_CDC_CORE_H_
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_cdc_if_template.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief Header for dfu_mal.c file.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_CDC_IF_TEMPLATE_H
-#define __USBD_CDC_IF_TEMPLATE_H
-
-/* Includes ------------------------------------------------------------------*/
-#ifdef STM32F2XX
- #include "stm32f2xx.h"
-#elif defined(STM32F10X_CL)
- #include "stm32f10x.h"
-#endif /* STM32F2XX */
-
-#include "usbd_conf.h"
-#include "usbd_cdc_core.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-extern CDC_IF_Prop_TypeDef TEMPLATE_fops;
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-#endif /* __USBD_CDC_IF_TEMPLATE_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_cdc_core.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief This file provides the high layer firmware functions to manage the
- * following functionalities of the USB CDC Class:
- * - Initialization and Configuration of high and low layer
- * - Enumeration as CDC Device (and enumeration for each implemented memory interface)
- * - OUT/IN data transfer
- * - Command IN transfer (class requests management)
- * - Error management
- *
- * @verbatim
- *
- * ===================================================================
- * CDC Class Driver Description
- * ===================================================================
- * This driver manages the "Universal Serial Bus Class Definitions for Communications Devices
- * Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus
- * Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007"
- * This driver implements the following aspects of the specification:
- * - Device descriptor management
- * - Configuration descriptor management
- * - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN)
- * - Requests management (as described in section 6.2 in specification)
- * - Abstract Control Model compliant
- * - Union Functional collection (using 1 IN endpoint for control)
- * - Data interface class
-
- * @note
- * For the Abstract Control Model, this core allows only transmitting the requests to
- * lower layer dispatcher (ie. usbd_cdc_vcp.c/.h) which should manage each request and
- * perform relative actions.
- *
- * These aspects may be enriched or modified for a specific user application.
- *
- * This driver doesn't implement the following aspects of the specification
- * (but it is possible to manage these features with some modifications on this driver):
- * - Any class-specific aspect relative to communication classes should be managed by user application.
- * - All communication classes other than PSTN are not managed
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_cdc_core.h"
-#include "usbd_desc.h"
-#include "usbd_req.h"
-
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup usbd_cdc
- * @brief usbd core module
- * @{
- */
-
-/** @defgroup usbd_cdc_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup usbd_cdc_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup usbd_cdc_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup usbd_cdc_Private_FunctionPrototypes
- * @{
- */
-
-/*********************************************
- CDC Device library callbacks
- *********************************************/
-static uint8_t usbd_cdc_Init (void *pdev, uint8_t cfgidx);
-static uint8_t usbd_cdc_DeInit (void *pdev, uint8_t cfgidx);
-static uint8_t usbd_cdc_Setup (void *pdev, USB_SETUP_REQ *req);
-static uint8_t usbd_cdc_EP0_RxReady (void *pdev);
-static uint8_t usbd_cdc_DataIn (void *pdev, uint8_t epnum);
-static uint8_t usbd_cdc_DataOut (void *pdev, uint8_t epnum);
-static uint8_t usbd_cdc_SOF (void *pdev);
-
-/*********************************************
- CDC specific management functions
- *********************************************/
-static void Handle_USBAsynchXfer (void *pdev);
-static uint8_t *USBD_cdc_GetCfgDesc (uint8_t speed, uint16_t *length);
-#ifdef USE_USB_OTG_HS
-static uint8_t *USBD_cdc_GetOtherCfgDesc (uint8_t speed, uint16_t *length);
-#endif
-/**
- * @}
- */
-
-/** @defgroup usbd_cdc_Private_Variables
- * @{
- */
-extern CDC_IF_Prop_TypeDef APP_FOPS;
-extern uint8_t USBD_DeviceDesc [USB_SIZ_DEVICE_DESC];
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN uint8_t usbd_cdc_CfgDesc [USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END ;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN uint8_t usbd_cdc_OtherCfgDesc [USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END ;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN static __IO uint32_t usbd_cdc_AltSet __ALIGN_END = 0;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN uint8_t USB_Rx_Buffer [CDC_DATA_MAX_PACKET_SIZE] __ALIGN_END ;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN uint8_t APP_Rx_Buffer [APP_RX_DATA_SIZE] __ALIGN_END ;
-
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN uint8_t CmdBuff[CDC_CMD_PACKET_SZE] __ALIGN_END ;
-
-uint32_t APP_Rx_ptr_in = 0;
-uint32_t APP_Rx_ptr_out = 0;
-uint32_t APP_Rx_length = 0;
-
-uint8_t USB_Tx_State = 0;
-
-static uint32_t cdcCmd = 0xFF;
-static uint32_t cdcLen = 0;
-
-/* CDC interface class callbacks structure */
-USBD_Class_cb_TypeDef USBD_CDC_cb =
-{
- usbd_cdc_Init,
- usbd_cdc_DeInit,
- usbd_cdc_Setup,
- NULL, /* EP0_TxSent, */
- usbd_cdc_EP0_RxReady,
- usbd_cdc_DataIn,
- usbd_cdc_DataOut,
- usbd_cdc_SOF,
- NULL,
- NULL,
- USBD_cdc_GetCfgDesc,
-#ifdef USE_USB_OTG_HS
- USBD_cdc_GetOtherCfgDesc, /* use same cobfig as per FS */
-#endif /* USE_USB_OTG_HS */
-};
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-/* USB CDC device Configuration Descriptor */
-__ALIGN_BEGIN uint8_t usbd_cdc_CfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END =
-{
- /*Configuration Descriptor*/
- 0x09, /* bLength: Configuration Descriptor size */
- USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
- USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */
- 0x00,
- 0x02, /* bNumInterfaces: 2 interface */
- 0x01, /* bConfigurationValue: Configuration value */
- 0x00, /* iConfiguration: Index of string descriptor describing the configuration */
- 0xC0, /* bmAttributes: self powered */
- 0x32, /* MaxPower 0 mA */
-
- /*---------------------------------------------------------------------------*/
-
- /*Interface Descriptor */
- 0x09, /* bLength: Interface Descriptor size */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */
- /* Interface descriptor type */
- 0x00, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x01, /* bNumEndpoints: One endpoints used */
- 0x02, /* bInterfaceClass: Communication Interface Class */
- 0x02, /* bInterfaceSubClass: Abstract Control Model */
- 0x01, /* bInterfaceProtocol: Common AT commands */
- 0x00, /* iInterface: */
-
- /*Header Functional Descriptor*/
- 0x05, /* bLength: Endpoint Descriptor size */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x00, /* bDescriptorSubtype: Header Func Desc */
- 0x10, /* bcdCDC: spec release number */
- 0x01,
-
- /*Call Management Functional Descriptor*/
- 0x05, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x01, /* bDescriptorSubtype: Call Management Func Desc */
- 0x00, /* bmCapabilities: D0+D1 */
- 0x01, /* bDataInterface: 1 */
-
- /*ACM Functional Descriptor*/
- 0x04, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x02, /* bDescriptorSubtype: Abstract Control Management desc */
- 0x02, /* bmCapabilities */
-
- /*Union Functional Descriptor*/
- 0x05, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x06, /* bDescriptorSubtype: Union func desc */
- 0x00, /* bMasterInterface: Communication class interface */
- 0x01, /* bSlaveInterface0: Data Class Interface */
-
- /*Endpoint 2 Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
- CDC_CMD_EP, /* bEndpointAddress */
- 0x03, /* bmAttributes: Interrupt */
- LOBYTE(CDC_CMD_PACKET_SZE), /* wMaxPacketSize: */
- HIBYTE(CDC_CMD_PACKET_SZE),
-#ifdef USE_USB_OTG_HS
- 0x10, /* bInterval: */
-#else
- 0xFF, /* bInterval: */
-#endif /* USE_USB_OTG_HS */
-
- /*---------------------------------------------------------------------------*/
-
- /*Data class interface descriptor*/
- 0x09, /* bLength: Endpoint Descriptor size */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */
- 0x01, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints: Two endpoints used */
- 0x0A, /* bInterfaceClass: CDC */
- 0x00, /* bInterfaceSubClass: */
- 0x00, /* bInterfaceProtocol: */
- 0x00, /* iInterface: */
-
- /*Endpoint OUT Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
- CDC_OUT_EP, /* bEndpointAddress */
- 0x02, /* bmAttributes: Bulk */
- LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */
- HIBYTE(CDC_DATA_MAX_PACKET_SIZE),
- 0x00, /* bInterval: ignore for Bulk transfer */
-
- /*Endpoint IN Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
- CDC_IN_EP, /* bEndpointAddress */
- 0x02, /* bmAttributes: Bulk */
- LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */
- HIBYTE(CDC_DATA_MAX_PACKET_SIZE),
- 0x00 /* bInterval: ignore for Bulk transfer */
-} ;
-
-#ifdef USE_USB_OTG_HS
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN uint8_t usbd_cdc_OtherCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END =
-{
- 0x09, /* bLength: Configuation Descriptor size */
- USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION,
- USB_CDC_CONFIG_DESC_SIZ,
- 0x00,
- 0x02, /* bNumInterfaces: 2 interfaces */
- 0x01, /* bConfigurationValue: */
- 0x04, /* iConfiguration: */
- 0xC0, /* bmAttributes: */
- 0x32, /* MaxPower 100 mA */
-
- /*Interface Descriptor */
- 0x09, /* bLength: Interface Descriptor size */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */
- /* Interface descriptor type */
- 0x00, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x01, /* bNumEndpoints: One endpoints used */
- 0x02, /* bInterfaceClass: Communication Interface Class */
- 0x02, /* bInterfaceSubClass: Abstract Control Model */
- 0x01, /* bInterfaceProtocol: Common AT commands */
- 0x00, /* iInterface: */
-
- /*Header Functional Descriptor*/
- 0x05, /* bLength: Endpoint Descriptor size */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x00, /* bDescriptorSubtype: Header Func Desc */
- 0x10, /* bcdCDC: spec release number */
- 0x01,
-
- /*Call Management Functional Descriptor*/
- 0x05, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x01, /* bDescriptorSubtype: Call Management Func Desc */
- 0x00, /* bmCapabilities: D0+D1 */
- 0x01, /* bDataInterface: 1 */
-
- /*ACM Functional Descriptor*/
- 0x04, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x02, /* bDescriptorSubtype: Abstract Control Management desc */
- 0x02, /* bmCapabilities */
-
- /*Union Functional Descriptor*/
- 0x05, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x06, /* bDescriptorSubtype: Union func desc */
- 0x00, /* bMasterInterface: Communication class interface */
- 0x01, /* bSlaveInterface0: Data Class Interface */
-
- /*Endpoint 2 Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
- CDC_CMD_EP, /* bEndpointAddress */
- 0x03, /* bmAttributes: Interrupt */
- LOBYTE(CDC_CMD_PACKET_SZE), /* wMaxPacketSize: */
- HIBYTE(CDC_CMD_PACKET_SZE),
- 0xFF, /* bInterval: */
-
- /*---------------------------------------------------------------------------*/
-
- /*Data class interface descriptor*/
- 0x09, /* bLength: Endpoint Descriptor size */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */
- 0x01, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints: Two endpoints used */
- 0x0A, /* bInterfaceClass: CDC */
- 0x00, /* bInterfaceSubClass: */
- 0x00, /* bInterfaceProtocol: */
- 0x00, /* iInterface: */
-
- /*Endpoint OUT Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
- CDC_OUT_EP, /* bEndpointAddress */
- 0x02, /* bmAttributes: Bulk */
- 0x40, /* wMaxPacketSize: */
- 0x00,
- 0x00, /* bInterval: ignore for Bulk transfer */
-
- /*Endpoint IN Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
- CDC_IN_EP, /* bEndpointAddress */
- 0x02, /* bmAttributes: Bulk */
- 0x40, /* wMaxPacketSize: */
- 0x00,
- 0x00 /* bInterval */
-};
-#endif /* USE_USB_OTG_HS */
-
-/**
- * @}
- */
-
-/** @defgroup usbd_cdc_Private_Functions
- * @{
- */
-
-/**
- * @brief usbd_cdc_Init
- * Initilaize the CDC interface
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t usbd_cdc_Init (void *pdev,
- uint8_t cfgidx)
-{
- uint8_t *pbuf;
-
- /* Open EP IN */
- DCD_EP_Open(pdev,
- CDC_IN_EP,
- CDC_DATA_IN_PACKET_SIZE,
- USB_OTG_EP_BULK);
-
- /* Open EP OUT */
- DCD_EP_Open(pdev,
- CDC_OUT_EP,
- CDC_DATA_OUT_PACKET_SIZE,
- USB_OTG_EP_BULK);
-
- /* Open Command IN EP */
- DCD_EP_Open(pdev,
- CDC_CMD_EP,
- CDC_CMD_PACKET_SZE,
- USB_OTG_EP_INT);
-
- pbuf = (uint8_t *)USBD_DeviceDesc;
- pbuf[4] = DEVICE_CLASS_CDC;
- pbuf[5] = DEVICE_SUBCLASS_CDC;
-
- /* Initialize the Interface physical components */
- APP_FOPS.pIf_Init();
-
- /* Prepare Out endpoint to receive next packet */
- DCD_EP_PrepareRx(pdev,
- CDC_OUT_EP,
- (uint8_t*)(USB_Rx_Buffer),
- CDC_DATA_OUT_PACKET_SIZE);
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_cdc_Init
- * DeInitialize the CDC layer
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t usbd_cdc_DeInit (void *pdev,
- uint8_t cfgidx)
-{
- /* Open EP IN */
- DCD_EP_Close(pdev,
- CDC_IN_EP);
-
- /* Open EP OUT */
- DCD_EP_Close(pdev,
- CDC_OUT_EP);
-
- /* Open Command IN EP */
- DCD_EP_Close(pdev,
- CDC_CMD_EP);
-
- /* Restore default state of the Interface physical components */
- APP_FOPS.pIf_DeInit();
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_cdc_Setup
- * Handle the CDC specific requests
- * @param pdev: instance
- * @param req: usb requests
- * @retval status
- */
-static uint8_t usbd_cdc_Setup (void *pdev,
- USB_SETUP_REQ *req)
-{
- uint16_t len;
- uint8_t *pbuf;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
- /* CDC Class Requests -------------------------------*/
- case USB_REQ_TYPE_CLASS :
- /* Check if the request is a data setup packet */
- if (req->wLength)
- {
- /* Check if the request is Device-to-Host */
- if (req->bmRequest & 0x80)
- {
- /* Get the data to be sent to Host from interface layer */
- APP_FOPS.pIf_Ctrl(req->bRequest, CmdBuff, req->wLength);
-
- /* Send the data to the host */
- USBD_CtlSendData (pdev,
- CmdBuff,
- req->wLength);
- }
- else /* Host-to-Device requeset */
- {
- /* Set the value of the current command to be processed */
- cdcCmd = req->bRequest;
- cdcLen = req->wLength;
-
- /* Prepare the reception of the buffer over EP0
- Next step: the received data will be managed in usbd_cdc_EP0_TxSent()
- function. */
- USBD_CtlPrepareRx (pdev,
- CmdBuff,
- req->wLength);
- }
- }
- else /* No Data request */
- {
- /* Transfer the command to the interface layer */
- APP_FOPS.pIf_Ctrl(req->bRequest, NULL, 0);
- }
-
- return USBD_OK;
-
- default:
- USBD_CtlError (pdev, req);
- return USBD_FAIL;
-
-
-
- /* Standard Requests -------------------------------*/
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_DESCRIPTOR:
- if( (req->wValue >> 8) == CDC_DESCRIPTOR_TYPE)
- {
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- pbuf = usbd_cdc_Desc;
-#else
- pbuf = usbd_cdc_CfgDesc + 9 + (9 * USBD_ITF_MAX_NUM);
-#endif
- len = MIN(USB_CDC_DESC_SIZ , req->wLength);
- }
-
- USBD_CtlSendData (pdev,
- pbuf,
- len);
- break;
-
- case USB_REQ_GET_INTERFACE :
- USBD_CtlSendData (pdev,
- (uint8_t *)&usbd_cdc_AltSet,
- 1);
- break;
-
- case USB_REQ_SET_INTERFACE :
- if ((uint8_t)(req->wValue) < USBD_ITF_MAX_NUM)
- {
- usbd_cdc_AltSet = (uint8_t)(req->wValue);
- }
- else
- {
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- break;
- }
- }
- return USBD_OK;
-}
-
-/**
- * @brief usbd_cdc_EP0_RxReady
- * Data received on control endpoint
- * @param pdev: device device instance
- * @retval status
- */
-static uint8_t usbd_cdc_EP0_RxReady (void *pdev)
-{
- if (cdcCmd != NO_CMD)
- {
- /* Process the data */
- APP_FOPS.pIf_Ctrl(cdcCmd, CmdBuff, cdcLen);
-
- /* Reset the command variable to default value */
- cdcCmd = NO_CMD;
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_audio_DataIn
- * Data sent on non-control IN endpoint
- * @param pdev: device instance
- * @param epnum: endpoint number
- * @retval status
- */
-static uint8_t usbd_cdc_DataIn (void *pdev, uint8_t epnum)
-{
- uint16_t USB_Tx_ptr;
- uint16_t USB_Tx_length;
-
- if (USB_Tx_State == 1)
- {
- if (APP_Rx_length == 0)
- {
- USB_Tx_State = 0;
- }
- else
- {
- if (APP_Rx_length > CDC_DATA_IN_PACKET_SIZE){
- USB_Tx_ptr = APP_Rx_ptr_out;
- USB_Tx_length = CDC_DATA_IN_PACKET_SIZE;
-
- APP_Rx_ptr_out += CDC_DATA_IN_PACKET_SIZE;
- APP_Rx_length -= CDC_DATA_IN_PACKET_SIZE;
- }
- else
- {
- USB_Tx_ptr = APP_Rx_ptr_out;
- USB_Tx_length = APP_Rx_length;
-
- APP_Rx_ptr_out += APP_Rx_length;
- APP_Rx_length = 0;
- }
-
- /* Prepare the available data buffer to be sent on IN endpoint */
- DCD_EP_Tx (pdev,
- CDC_IN_EP,
- (uint8_t*)&APP_Rx_Buffer[USB_Tx_ptr],
- USB_Tx_length);
- }
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_audio_DataOut
- * Data received on non-control Out endpoint
- * @param pdev: device instance
- * @param epnum: endpoint number
- * @retval status
- */
-static uint8_t usbd_cdc_DataOut (void *pdev, uint8_t epnum)
-{
- uint16_t USB_Rx_Cnt;
-
- /* Get the received data buffer and update the counter */
- USB_Rx_Cnt = ((USB_OTG_CORE_HANDLE*)pdev)->dev.out_ep[epnum].xfer_count;
-
- /* USB data will be immediately processed, this allow next USB traffic being
- NAKed till the end of the application Xfer */
- APP_FOPS.pIf_DataRx(USB_Rx_Buffer, USB_Rx_Cnt);
-
- /* Prepare Out endpoint to receive next packet */
- DCD_EP_PrepareRx(pdev,
- CDC_OUT_EP,
- (uint8_t*)(USB_Rx_Buffer),
- CDC_DATA_OUT_PACKET_SIZE);
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_audio_SOF
- * Start Of Frame event management
- * @param pdev: instance
- * @param epnum: endpoint number
- * @retval status
- */
-static uint8_t usbd_cdc_SOF (void *pdev)
-{
- static uint32_t FrameCount = 0;
-
- if (FrameCount++ == CDC_IN_FRAME_INTERVAL)
- {
- /* Reset the frame counter */
- FrameCount = 0;
-
- /* Check the data to be sent through IN pipe */
- Handle_USBAsynchXfer(pdev);
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief Handle_USBAsynchXfer
- * Send data to USB
- * @param pdev: instance
- * @retval None
- */
-static void Handle_USBAsynchXfer (void *pdev)
-{
- uint16_t USB_Tx_ptr;
- uint16_t USB_Tx_length;
-
- if(USB_Tx_State != 1)
- {
- if (APP_Rx_ptr_out == APP_RX_DATA_SIZE)
- {
- APP_Rx_ptr_out = 0;
- }
-
- if(APP_Rx_ptr_out == APP_Rx_ptr_in)
- {
- USB_Tx_State = 0;
- return;
- }
-
- if(APP_Rx_ptr_out > APP_Rx_ptr_in) /* rollback */
- {
- APP_Rx_length = APP_RX_DATA_SIZE - APP_Rx_ptr_out;
-
- }
- else
- {
- APP_Rx_length = APP_Rx_ptr_in - APP_Rx_ptr_out;
-
- }
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- APP_Rx_length &= ~0x03;
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-
- if (APP_Rx_length > CDC_DATA_IN_PACKET_SIZE)
- {
- USB_Tx_ptr = APP_Rx_ptr_out;
- USB_Tx_length = CDC_DATA_IN_PACKET_SIZE;
-
- APP_Rx_ptr_out += CDC_DATA_IN_PACKET_SIZE;
- APP_Rx_length -= CDC_DATA_IN_PACKET_SIZE;
- }
- else
- {
- USB_Tx_ptr = APP_Rx_ptr_out;
- USB_Tx_length = APP_Rx_length;
-
- APP_Rx_ptr_out += APP_Rx_length;
- APP_Rx_length = 0;
- }
- USB_Tx_State = 1;
-
- DCD_EP_Tx (pdev,
- CDC_IN_EP,
- (uint8_t*)&APP_Rx_Buffer[USB_Tx_ptr],
- USB_Tx_length);
- }
-
-}
-
-/**
- * @brief USBD_cdc_GetCfgDesc
- * Return configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_cdc_GetCfgDesc (uint8_t speed, uint16_t *length)
-{
- *length = sizeof (usbd_cdc_CfgDesc);
- return usbd_cdc_CfgDesc;
-}
-
-/**
- * @brief USBD_cdc_GetCfgDesc
- * Return configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-#ifdef USE_USB_OTG_HS
-static uint8_t *USBD_cdc_GetOtherCfgDesc (uint8_t speed, uint16_t *length)
-{
- *length = sizeof (usbd_cdc_OtherCfgDesc);
- return usbd_cdc_OtherCfgDesc;
-}
-#endif
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_cdc_if_template.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief Generic media access Layer.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
-#pragma data_alignment = 4
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_cdc_if_template.h"
-#include "stm32_eval.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* These are external variables imported from CDC core to be used for IN
- transfer management. */
-extern uint8_t APP_Rx_Buffer []; /* Write CDC received data in this buffer.
- These data will be sent over USB IN endpoint
- in the CDC core functions. */
-extern uint32_t APP_Rx_ptr_in; /* Increment this pointer or roll it back to
- start address when writing received data
- in the buffer APP_Rx_Buffer. */
-
-/* Private function prototypes -----------------------------------------------*/
-static uint16_t TEMPLATE_Init (void);
-static uint16_t TEMPLATE_DeInit (void);
-static uint16_t TEMPLATE_Ctrl (uint32_t Cmd, uint8_t* Buf, uint32_t Len);
-static uint16_t TEMPLATE_DataTx (uint8_t* Buf, uint32_t Len);
-static uint16_t TEMPLATE_DataRx (uint8_t* Buf, uint32_t Len);
-
-CDC_IF_Prop_TypeDef TEMPLATE_fops =
-{
- TEMPLATE_Init,
- TEMPLATE_DeInit,
- TEMPLATE_Ctrl,
- TEMPLATE_DataTx,
- TEMPLATE_DataRx
-};
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief TEMPLATE_Init
- * Initializes the CDC media low layer
- * @param None
- * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL
- */
-static uint16_t TEMPLATE_Init(void)
-{
- /*
- Add your initialization code here
- */
- return USBD_OK;
-}
-
-/**
- * @brief TEMPLATE_DeInit
- * DeInitializes the CDC media low layer
- * @param None
- * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL
- */
-static uint16_t TEMPLATE_DeInit(void)
-{
- /*
- Add your deinitialization code here
- */
- return USBD_OK;
-}
-
-
-/**
- * @brief TEMPLATE_Ctrl
- * Manage the CDC class requests
- * @param Cmd: Command code
- * @param Buf: Buffer containing command data (request parameters)
- * @param Len: Number of data to be sent (in bytes)
- * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL
- */
-static uint16_t TEMPLATE_Ctrl (uint32_t Cmd, uint8_t* Buf, uint32_t Len)
-{
- switch (Cmd)
- {
- case SEND_ENCAPSULATED_COMMAND:
- /* Add your code here */
- break;
-
- case GET_ENCAPSULATED_RESPONSE:
- /* Add your code here */
- break;
-
- case SET_COMM_FEATURE:
- /* Add your code here */
- break;
-
- case GET_COMM_FEATURE:
- /* Add your code here */
- break;
-
- case CLEAR_COMM_FEATURE:
- /* Add your code here */
- break;
-
- case SET_LINE_CODING:
- /* Add your code here */
- break;
-
- case GET_LINE_CODING:
- /* Add your code here */
- break;
-
- case SET_CONTROL_LINE_STATE:
- /* Add your code here */
- break;
-
- case SEND_BREAK:
- /* Add your code here */
- break;
-
- default:
- break;
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief TEMPLATE_DataTx
- * CDC received data to be send over USB IN endpoint are managed in
- * this function.
- * @param Buf: Buffer of data to be sent
- * @param Len: Number of data to be sent (in bytes)
- * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL
- */
-static uint16_t TEMPLATE_DataTx (uint8_t* Buf, uint32_t Len)
-{
-
- /* Get the data to be sent */
- for (i = 0; i < Len; i++)
- {
- /* APP_Rx_Buffer[APP_Rx_ptr_in] = XXX_ReceiveData(XXX); */
- }
-
- /* Increment the in pointer */
- APP_Rx_ptr_in++;
-
- /* To avoid buffer overflow */
- if(APP_Rx_ptr_in == APP_RX_DATA_SIZE)
- {
- APP_Rx_ptr_in = 0;
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief TEMPLATE_DataRx
- * Data received over USB OUT endpoint are sent over CDC interface
- * through this function.
- *
- * @note
- * This function will block any OUT packet reception on USB endpoint
- * untill exiting this function. If you exit this function before transfer
- * is complete on CDC interface (ie. using DMA controller) it will result
- * in receiving more data while previous ones are still not sent.
- *
- * @param Buf: Buffer of data to be received
- * @param Len: Number of data received (in bytes)
- * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL
- */
-static uint16_t TEMPLATE_DataRx (uint8_t* Buf, uint32_t Len)
-{
- uint32_t i;
-
- /* Send the received buffer */
- for (i = 0; i < Len; i++)
- {
- /* XXXX_SendData(XXXX, *(Buf + i) ); */
- }
-
- return USBD_OK;
-}
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_dfu_core.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief header file for the usbd_dfu_core.c file.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-
-#ifndef __USB_DFU_CORE_H_
-#define __USB_DFU_CORE_H_
-
-#include "usbd_ioreq.h"
-#include "usbd_dfu_mal.h"
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup usbd_dfu
- * @brief This file is the Header file for USBD_dfu.c
- * @{
- */
-
-
-/** @defgroup usbd_dfu_Exported_Defines
- * @{
- */
-#define USB_DFU_CONFIG_DESC_SIZ (18 + (9 * USBD_ITF_MAX_NUM))
-#define USB_DFU_DESC_SIZ 9
-
-#define DFU_DESCRIPTOR_TYPE 0x21
-
-
-/*---------------------------------------------------------------------*/
-/* DFU definitions */
-/*---------------------------------------------------------------------*/
-
-
-
-/**************************************************/
-/* DFU Requests DFU states */
-/**************************************************/
-
-
-#define STATE_appIDLE 0
-#define STATE_appDETACH 1
-#define STATE_dfuIDLE 2
-#define STATE_dfuDNLOAD_SYNC 3
-#define STATE_dfuDNBUSY 4
-#define STATE_dfuDNLOAD_IDLE 5
-#define STATE_dfuMANIFEST_SYNC 6
-#define STATE_dfuMANIFEST 7
-#define STATE_dfuMANIFEST_WAIT_RESET 8
-#define STATE_dfuUPLOAD_IDLE 9
-#define STATE_dfuERROR 10
-
-/**************************************************/
-/* DFU Requests DFU status */
-/**************************************************/
-
-#define STATUS_OK 0x00
-#define STATUS_ERRTARGET 0x01
-#define STATUS_ERRFILE 0x02
-#define STATUS_ERRWRITE 0x03
-#define STATUS_ERRERASE 0x04
-#define STATUS_ERRCHECK_ERASED 0x05
-#define STATUS_ERRPROG 0x06
-#define STATUS_ERRVERIFY 0x07
-#define STATUS_ERRADDRESS 0x08
-#define STATUS_ERRNOTDONE 0x09
-#define STATUS_ERRFIRMWARE 0x0A
-#define STATUS_ERRVENDOR 0x0B
-#define STATUS_ERRUSBR 0x0C
-#define STATUS_ERRPOR 0x0D
-#define STATUS_ERRUNKNOWN 0x0E
-#define STATUS_ERRSTALLEDPKT 0x0F
-
-/**************************************************/
-/* DFU Requests DFU states Manifestation State */
-/**************************************************/
-
-#define Manifest_complete 0x00
-#define Manifest_In_Progress 0x01
-
-
-/**************************************************/
-/* Special Commands with Download Request */
-/**************************************************/
-
-#define CMD_GETCOMMANDS 0x00
-#define CMD_SETADDRESSPOINTER 0x21
-#define CMD_ERASE 0x41
-
-/**************************************************/
-/* Other defines */
-/**************************************************/
-/* Bit Detach capable = bit 3 in bmAttributes field */
-#define DFU_DETACH_MASK (uint8_t)(1 << 4)
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CORE_Exported_TypesDefinitions
- * @{
- */
-/**************************************************/
-/* DFU Requests */
-/**************************************************/
-
-typedef enum _DFU_REQUESTS {
- DFU_DETACH = 0,
- DFU_DNLOAD = 1,
- DFU_UPLOAD,
- DFU_GETSTATUS,
- DFU_CLRSTATUS,
- DFU_GETSTATE,
- DFU_ABORT
-} DFU_REQUESTS;
-
-typedef void (*pFunction)(void);
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_CORE_Exported_Macros
- * @{
- */
-/********** Descriptor of DFU interface 0 Alternate setting n ****************/
-#define USBD_DFU_IF_DESC(n) 0x09, /* bLength: Interface Descriptor size */ \
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \
- 0x00, /* bInterfaceNumber: Number of Interface */ \
- (n), /* bAlternateSetting: Alternate setting */ \
- 0x00, /* bNumEndpoints*/ \
- 0xFE, /* bInterfaceClass: Application Specific Class Code */ \
- 0x01, /* bInterfaceSubClass : Device Firmware Upgrade Code */ \
- 0x02, /* nInterfaceProtocol: DFU mode protocol */ \
- USBD_IDX_INTERFACE_STR + (n) + 1 /* iInterface: Index of string descriptor */ \
- /* 18 */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_CORE_Exported_Variables
- * @{
- */
-
-extern USBD_Class_cb_TypeDef DFU_cb;
-/**
- * @}
- */
-
-/** @defgroup USB_CORE_Exported_Functions
- * @{
- */
-/**
- * @}
- */
-
-#endif // __USB_DFU_CORE_H_
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_dfu_mal.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief Header for usbd_dfu_mal.c file.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __DFU_MAL_H
-#define __DFU_MAL_H
-
-/* Includes ------------------------------------------------------------------*/
-#ifdef STM32F2XX
- #include "stm32f2xx.h"
-#elif defined(STM32F10X_CL)
- #include "stm32f10x.h"
-#endif /* STM32F2XX */
-
-#include "usbd_conf.h"
-#include "usbd_dfu_core.h"
-
-/* Exported types ------------------------------------------------------------*/
-typedef struct _DFU_MAL_PROP
-{
- const uint8_t* pStrDesc;
- uint16_t (*pMAL_Init) (void);
- uint16_t (*pMAL_DeInit) (void);
- uint16_t (*pMAL_Erase) (uint32_t Add);
- uint16_t (*pMAL_Write) (uint32_t Add, uint32_t Len);
- uint8_t *(*pMAL_Read) (uint32_t Add, uint32_t Len);
- uint16_t (*pMAL_CheckAdd) (uint32_t Add);
- const uint32_t EraseTiming;
- const uint32_t WriteTiming;
-}
-DFU_MAL_Prop_TypeDef;
-
-
-/* Exported constants --------------------------------------------------------*/
-#define MAL_OK 0
-#define MAL_FAIL 1
-
-/* utils macro ---------------------------------------------------------------*/
-#define _1st_BYTE(x) (uint8_t)((x)&0xFF) /* 1st addressing cycle */
-#define _2nd_BYTE(x) (uint8_t)(((x)&0xFF00)>>8) /* 2nd addressing cycle */
-#define _3rd_BYTE(x) (uint8_t)(((x)&0xFF0000)>>16) /* 3rd addressing cycle */
-#define _4th_BYTE(x) (uint8_t)(((x)&0xFF000000)>>24) /* 4th addressing cycle */
-
-/* Exported macro ------------------------------------------------------------*/
-#define SET_POLLING_TIMING(x) buffer[1] = _1st_BYTE(x);\
- buffer[2] = _2nd_BYTE(x);\
- buffer[3] = _3rd_BYTE(x);
-
-/* Exported functions ------------------------------------------------------- */
-
-uint16_t MAL_Init (void);
-uint16_t MAL_DeInit (void);
-uint16_t MAL_Erase (uint32_t SectorAddress);
-uint16_t MAL_Write (uint32_t SectorAddress, uint32_t DataLength);
-uint8_t *MAL_Read (uint32_t SectorAddress, uint32_t DataLength);
-uint16_t MAL_GetStatus(uint32_t SectorAddress ,uint8_t Cmd, uint8_t *buffer);
-
-extern uint8_t MAL_Buffer[XFERSIZE]; /* RAM Buffer for Downloaded Data */
-#endif /* __DFU_MAL_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_flash_if.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 18-March-2011
- * @brief Header for usbd_flash_if.c file.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __FLASH_IF_MAL_H
-#define __FLASH_IF_MAL_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_dfu_mal.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-#define FLASH_START_ADD 0x08000000
-
-#ifdef STM32F2XX
- #define FLASH_END_ADD 0x08100000
- #define FLASH_IF_STRING "@Internal Flash /0x08000000/03*016Ka,01*016Kg,01*064Kg,07*128Kg"
-#elif defined(STM32F10X_CL)
- #define FLASH_END_ADD 0x08040000
- #define FLASH_IF_STRING "@Internal Flash /0x08000000/06*002Ka,122*002Kg"
-#endif /* STM32F2XX */
-
-
-extern DFU_MAL_Prop_TypeDef DFU_Flash_cb;
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __FLASH_IF_MAL_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_mem_if_template.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief Header for usbd_mem_if_template.c file.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MEM_IF_MAL_H
-#define __MEM_IF_MAL_H
-
-/* Includes ------------------------------------------------------------------*/
-#ifdef STM32F2XX
- #include "stm32f2xx.h"
-#endif /* STM32F2XX */
-#include "usbd_dfu_mal.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-#define MEM_START_ADD 0x00000000 /* Dummy start address */
-#define MEM_END_ADD (uint32_t)(MEM_START_ADD + (5 * 1024)) /* Dummy Size = 5KB */
-
-#define MEM_IF_STRING "@Dummy Memory /0x00000000/01*002Kg,03*001Kg"
-
-extern DFU_MAL_Prop_TypeDef DFU_Mem_cb;
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __MEM_IF_MAL_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_otp_if.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief Header for usbd_otp_if.c file.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __OTP_IF_MAL_H
-#define __OTP_IF_MAL_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_dfu_mal.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-#define OTP_START_ADD 0x1FFF7800
-#define OTP_END_ADD (uint32_t)(OTP_START_ADD + 528)
-
-#define OTP_IF_STRING "@OTP Area /0x1FFF7800/01*512 g,01*016 g"
-
-extern DFU_MAL_Prop_TypeDef DFU_Otp_cb;
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __OTP_IF_MAL_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_dfu_core.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief This file provides the high layer firmware functions to manage the
- * following functionalities of the USB DFU Class:
- * - Initialization and Configuration of high and low layer
- * - Enumeration as DFU Device (and enumeration for each implemented memory interface)
- * - Transfers to/from memory interfaces
- * - Easy-to-customize "plug-in-like" modules for adding/removing memory interfaces.
- * - Error management
- *
- * @verbatim
- *
- * ===================================================================
- * DFU Class Driver Description
- * ===================================================================
- * This driver manages the DFU class V1.1 following the "Device Class Specification for
- * Device Firmware Upgrade Version 1.1 Aug 5, 2004".
- * This driver implements the following aspects of the specification:
- * - Device descriptor management
- * - Configuration descriptor management
- * - Enumeration as DFU device (in DFU mode only)
- * - Requests management (supporting ST DFU sub-protocol)
- * - Memory operations management (Download/Upload/Erase/Detach/GetState/GetStatus)
- * - DFU state machine implementation.
- *
- * @note
- * ST DFU sub-protocol is compliant with DFU protocol and use sub-requests to manage
- * memory addressing, commands processing, specific memories operations (ie. Erase) ...
- * As required by the DFU specification, only endpoint 0 is used in this application.
- * Other endpoints and functions may be added to the application (ie. DFU ...)
- *
- * These aspects may be enriched or modified for a specific user application.
- *
- * This driver doesn't implement the following aspects of the specification
- * (but it is possible to manage these features with some modifications on this driver):
- * - Manifestation Tolerant mode
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_dfu_core.h"
-#include "usbd_desc.h"
-#include "usbd_req.h"
-#include "usb_bsp.h"
-
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup usbd_dfu
- * @brief usbd core module
- * @{
- */
-
-/** @defgroup usbd_dfu_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup usbd_dfu_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup usbd_dfu_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup usbd_dfu_Private_FunctionPrototypes
- * @{
- */
-
-/*********************************************
- DFU Device library callbacks
- *********************************************/
-static uint8_t usbd_dfu_Init (void *pdev,
- uint8_t cfgidx);
-
-static uint8_t usbd_dfu_DeInit (void *pdev,
- uint8_t cfgidx);
-
-static uint8_t usbd_dfu_Setup (void *pdev,
- USB_SETUP_REQ *req);
-
-static uint8_t EP0_TxSent (void *pdev);
-
-static uint8_t EP0_RxReady (void *pdev);
-
-
-static uint8_t *USBD_DFU_GetCfgDesc (uint8_t speed,
- uint16_t *length);
-
-
-#ifdef USB_OTG_HS_CORE
-static uint8_t *USBD_DFU_GetOtherCfgDesc (uint8_t speed,
- uint16_t *length);
-#endif
-
-static uint8_t* USBD_DFU_GetUsrStringDesc (uint8_t speed,
- uint8_t index ,
- uint16_t *length);
-
-/*********************************************
- DFU Requests management functions
- *********************************************/
-static void DFU_Req_DETACH (void *pdev,
- USB_SETUP_REQ *req);
-
-static void DFU_Req_DNLOAD (void *pdev,
- USB_SETUP_REQ *req);
-
-static void DFU_Req_UPLOAD (void *pdev,
- USB_SETUP_REQ *req);
-
-static void DFU_Req_GETSTATUS (void *pdev);
-
-static void DFU_Req_CLRSTATUS (void *pdev);
-
-static void DFU_Req_GETSTATE (void *pdev);
-
-static void DFU_Req_ABORT (void *pdev);
-
-static void DFU_LeaveDFUMode (void *pdev);
-
-/**
- * @}
- */
-
-/** @defgroup usbd_dfu_Private_Variables
- * @{
- */
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN uint8_t usbd_dfu_CfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END ;
-
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN uint8_t usbd_dfu_OtherCfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END ;
-
-/* The list of Interface String descriptor pointers is defined in usbd_dfu_mal.c
- file. This list can be updated whenever a memory has to be added or removed */
-extern const uint8_t* usbd_dfu_StringDesc[];
-
-/* State Machine variables */
-uint8_t DeviceState;
-uint8_t DeviceStatus[6];
-uint32_t Manifest_State = Manifest_complete;
-/* Data Management variables */
-static uint32_t wBlockNum = 0, wlength = 0;
-static uint32_t Pointer = APP_DEFAULT_ADD; /* Base Address to Erase, Program or Read */
-static __IO uint32_t usbd_dfu_AltSet = 0;
-
-extern uint8_t MAL_Buffer[];
-
-/* DFU interface class callbacks structure */
-USBD_Class_cb_TypeDef DFU_cb =
-{
- usbd_dfu_Init,
- usbd_dfu_DeInit,
- usbd_dfu_Setup,
- EP0_TxSent,
- EP0_RxReady,
- NULL, /* DataIn, */
- NULL, /* DataOut, */
- NULL, /*SOF */
- NULL,
- NULL,
- USBD_DFU_GetCfgDesc,
-#ifdef USB_OTG_HS_CORE
- USBD_DFU_GetOtherCfgDesc, /* use same cobfig as per FS */
-#endif
- USBD_DFU_GetUsrStringDesc,
-};
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-/* USB DFU device Configuration Descriptor */
-__ALIGN_BEGIN uint8_t usbd_dfu_CfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END =
-{
- 0x09, /* bLength: Configuation Descriptor size */
- USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
- USB_DFU_CONFIG_DESC_SIZ,
- /* wTotalLength: Bytes returned */
- 0x00,
- 0x01, /*bNumInterfaces: 1 interface*/
- 0x01, /*bConfigurationValue: Configuration value*/
- 0x02, /*iConfiguration: Index of string descriptor describing the configuration*/
- 0xC0, /*bmAttributes: bus powered and Supprts Remote Wakeup */
- 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/
- /* 09 */
-
- /********** Descriptor of DFU interface 0 Alternate setting 0 **************/
- USBD_DFU_IF_DESC(0), /* This interface is mandatory for all devices */
-
-#if (USBD_ITF_MAX_NUM > 1)
- /********** Descriptor of DFU interface 0 Alternate setting 1 **************/
- USBD_DFU_IF_DESC(1),
-#endif /* (USBD_ITF_MAX_NUM > 1) */
-
-#if (USBD_ITF_MAX_NUM > 2)
- /********** Descriptor of DFU interface 0 Alternate setting 2 **************/
- USBD_DFU_IF_DESC(2),
-#endif /* (USBD_ITF_MAX_NUM > 2) */
-
-#if (USBD_ITF_MAX_NUM > 3)
- /********** Descriptor of DFU interface 0 Alternate setting 3 **************/
- USBD_DFU_IF_DESC(3),
-#endif /* (USBD_ITF_MAX_NUM > 3) */
-
-#if (USBD_ITF_MAX_NUM > 4)
- /********** Descriptor of DFU interface 0 Alternate setting 4 **************/
- USBD_DFU_IF_DESC(4),
-#endif /* (USBD_ITF_MAX_NUM > 4) */
-
-#if (USBD_ITF_MAX_NUM > 5)
- /********** Descriptor of DFU interface 0 Alternate setting 5 **************/
- USBD_DFU_IF_DESC(5),
-#endif /* (USBD_ITF_MAX_NUM > 5) */
-
-#if (USBD_ITF_MAX_NUM > 6)
-#error "ERROR: usbd_dfu_core.c: Modify the file to support more descriptors!"
-#endif /* (USBD_ITF_MAX_NUM > 6) */
-
- /******************** DFU Functional Descriptor********************/
- 0x09, /*blength = 9 Bytes*/
- DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor*/
- 0x0B, /*bmAttribute
- bitCanDnload = 1 (bit 0)
- bitCanUpload = 1 (bit 1)
- bitManifestationTolerant = 0 (bit 2)
- bitWillDetach = 1 (bit 3)
- Reserved (bit4-6)
- bitAcceleratedST = 0 (bit 7)*/
- 0xFF, /*DetachTimeOut= 255 ms*/
- 0x00,
- /*WARNING: In DMA mode the multiple MPS packets feature is still not supported
- ==> In this case, when using DMA XFERSIZE should be set to 64 in usbd_conf.h */
- TRANSFER_SIZE_BYTES(XFERSIZE), /* TransferSize = 1024 Byte*/
- 0x1A, /* bcdDFUVersion*/
- 0x01
- /***********************************************************/
- /* 9*/
-} ;
-
-#ifdef USE_USB_OTG_HS
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-
-__ALIGN_BEGIN uint8_t usbd_dfu_OtherCfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END =
-{
- 0x09, /* bLength: Configuation Descriptor size */
- USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, /* bDescriptorType: Configuration */
- USB_DFU_CONFIG_DESC_SIZ,
- /* wTotalLength: Bytes returned */
- 0x00,
- 0x01, /*bNumInterfaces: 1 interface*/
- 0x01, /*bConfigurationValue: Configuration value*/
- 0x02, /*iConfiguration: Index of string descriptor describing the configuration*/
- 0xC0, /*bmAttributes: bus powered and Supprts Remote Wakeup */
- 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/
- /* 09 */
-
- /********** Descriptor of DFU interface 0 Alternate setting 0 **************/
- USBD_DFU_IF_DESC(0), /* This interface is mandatory for all devices */
-
-#if (USBD_ITF_MAX_NUM > 1)
- /********** Descriptor of DFU interface 0 Alternate setting 1 **************/
- USBD_DFU_IF_DESC(1),
-#endif /* (USBD_ITF_MAX_NUM > 1) */
-
-#if (USBD_ITF_MAX_NUM > 2)
- /********** Descriptor of DFU interface 0 Alternate setting 2 **************/
- USBD_DFU_IF_DESC(2),
-#endif /* (USBD_ITF_MAX_NUM > 2) */
-
-#if (USBD_ITF_MAX_NUM > 3)
- /********** Descriptor of DFU interface 0 Alternate setting 3 **************/
- USBD_DFU_IF_DESC(3),
-#endif /* (USBD_ITF_MAX_NUM > 3) */
-
-#if (USBD_ITF_MAX_NUM > 4)
- /********** Descriptor of DFU interface 0 Alternate setting 4 **************/
- USBD_DFU_IF_DESC(4),
-#endif /* (USBD_ITF_MAX_NUM > 4) */
-
-#if (USBD_ITF_MAX_NUM > 5)
- /********** Descriptor of DFU interface 0 Alternate setting 5 **************/
- USBD_DFU_IF_DESC(5),
-#endif /* (USBD_ITF_MAX_NUM > 5) */
-
-#if (USBD_ITF_MAX_NUM > 6)
-#error "ERROR: usbd_dfu_core.c: Modify the file to support more descriptors!"
-#endif /* (USBD_ITF_MAX_NUM > 6) */
-
- /******************** DFU Functional Descriptor********************/
- 0x09, /*blength = 9 Bytes*/
- DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor*/
- 0x0B, /*bmAttribute
- bitCanDnload = 1 (bit 0)
- bitCanUpload = 1 (bit 1)
- bitManifestationTolerant = 0 (bit 2)
- bitWillDetach = 1 (bit 3)
- Reserved (bit4-6)
- bitAcceleratedST = 0 (bit 7)*/
- 0xFF, /*DetachTimeOut= 255 ms*/
- 0x00,
- /*WARNING: In DMA mode the multiple MPS packets feature is still not supported
- ==> In this case, when using DMA XFERSIZE should be set to 64 in usbd_conf.h */
- TRANSFER_SIZE_BYTES(XFERSIZE), /* TransferSize = 1024 Byte*/
- 0x1A, /* bcdDFUVersion*/
- 0x01
- /***********************************************************/
- /* 9*/
-};
-#endif /* USE_USB_OTG_HS */
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-
-__ALIGN_BEGIN static uint8_t usbd_dfu_Desc[USB_DFU_DESC_SIZ] __ALIGN_END =
-{
- 0x09, /*blength = 9 Bytes*/
- DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor*/
- 0x0B, /*bmAttribute
- bitCanDnload = 1 (bit 0)
- bitCanUpload = 1 (bit 1)
- bitManifestationTolerant = 0 (bit 2)
- bitWillDetach = 1 (bit 3)
- Reserved (bit4-6)
- bitAcceleratedST = 0 (bit 7)*/
- 0xFF, /*DetachTimeOut= 255 ms*/
- 0x00,
- /*WARNING: In DMA mode the multiple MPS packets feature is still not supported
- ==> In this case, when using DMA XFERSIZE should be set to 64 in usbd_conf.h */
- TRANSFER_SIZE_BYTES(XFERSIZE), /* TransferSize = 1024 Byte*/
- 0x1A, /* bcdDFUVersion*/
- 0x01
-};
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-
-/**
- * @}
- */
-
-/** @defgroup usbd_dfu_Private_Functions
- * @{
- */
-
-/**
- * @brief usbd_dfu_Init
- * Initializes the DFU interface.
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t usbd_dfu_Init (void *pdev,
- uint8_t cfgidx)
-{
- /* Initilialize the MAL(Media Access Layer) */
- MAL_Init();
-
- /* Initialize the state of the DFU interface */
- DeviceState = STATE_dfuIDLE;
- DeviceStatus[0] = STATUS_OK;
- DeviceStatus[4] = DeviceState;
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_dfu_Init
- * De-initializes the DFU layer.
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t usbd_dfu_DeInit (void *pdev,
- uint8_t cfgidx)
-{
- /* Restore default state */
- DeviceState = STATE_dfuIDLE;
- DeviceStatus[0] = STATUS_OK;
- DeviceStatus[4] = DeviceState;
- wBlockNum = 0;
- wlength = 0;
-
- /* DeInitilialize the MAL(Media Access Layer) */
- MAL_DeInit();
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_dfu_Setup
- * Handles the DFU request parsing.
- * @param pdev: instance
- * @param req: usb requests
- * @retval status
- */
-static uint8_t usbd_dfu_Setup (void *pdev,
- USB_SETUP_REQ *req)
-{
- uint16_t len = 0;
- uint8_t *pbuf = NULL;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
- /* DFU Class Requests -------------------------------*/
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest)
- {
- case DFU_DNLOAD:
- DFU_Req_DNLOAD(pdev, req);
- break;
-
- case DFU_UPLOAD:
- DFU_Req_UPLOAD(pdev, req);
- break;
-
- case DFU_GETSTATUS:
- DFU_Req_GETSTATUS(pdev);
- break;
-
- case DFU_CLRSTATUS:
- DFU_Req_CLRSTATUS(pdev);
- break;
-
- case DFU_GETSTATE:
- DFU_Req_GETSTATE(pdev);
- break;
-
- case DFU_ABORT:
- DFU_Req_ABORT(pdev);
- break;
-
- case DFU_DETACH:
- DFU_Req_DETACH(pdev, req);
- break;
-
- default:
- USBD_CtlError (pdev, req);
- return USBD_FAIL;
- }
- break;
-
- /* Standard Requests -------------------------------*/
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_DESCRIPTOR:
- if( (req->wValue >> 8) == DFU_DESCRIPTOR_TYPE)
- {
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- pbuf = usbd_dfu_Desc;
-#else
- pbuf = usbd_dfu_CfgDesc + 9 + (9 * USBD_ITF_MAX_NUM);
-#endif
- len = MIN(USB_DFU_DESC_SIZ , req->wLength);
- }
-
- USBD_CtlSendData (pdev,
- pbuf,
- len);
- break;
-
- case USB_REQ_GET_INTERFACE :
- USBD_CtlSendData (pdev,
- (uint8_t *)&usbd_dfu_AltSet,
- 1);
- break;
-
- case USB_REQ_SET_INTERFACE :
- if ((uint8_t)(req->wValue) < USBD_ITF_MAX_NUM)
- {
- usbd_dfu_AltSet = (uint8_t)(req->wValue);
- }
- else
- {
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- break;
- }
- }
- return USBD_OK;
-}
-
-/**
- * @brief EP0_TxSent
- * Handles the DFU control endpoint data IN stage.
- * @param pdev: device instance
- * @retval status
- */
-static uint8_t EP0_TxSent (void *pdev)
-{
- uint32_t Addr;
- USB_SETUP_REQ req;
-
- if (DeviceState == STATE_dfuDNBUSY)
- {
- /* Decode the Special Command*/
- if (wBlockNum == 0)
- {
- if ((MAL_Buffer[0] == CMD_GETCOMMANDS) && (wlength == 1))
- {}
- else if (( MAL_Buffer[0] == CMD_SETADDRESSPOINTER ) && (wlength == 5))
- {
- Pointer = MAL_Buffer[1];
- Pointer += MAL_Buffer[2] << 8;
- Pointer += MAL_Buffer[3] << 16;
- Pointer += MAL_Buffer[4] << 24;
- }
- else if (( MAL_Buffer[0] == CMD_ERASE ) && (wlength == 5))
- {
- Pointer = MAL_Buffer[1];
- Pointer += MAL_Buffer[2] << 8;
- Pointer += MAL_Buffer[3] << 16;
- Pointer += MAL_Buffer[4] << 24;
- MAL_Erase(Pointer);
- }
- else
- {
- /* Reset the global length and block number */
- wlength = 0;
- wBlockNum = 0;
- /* Call the error management function (command will be nacked) */
- req.bmRequest = 0;
- req.wLength = 1;
- USBD_CtlError (pdev, &req);
- }
- }
- /* Regular Download Command */
- else if (wBlockNum > 1)
- {
- /* Decode the required address */
- Addr = ((wBlockNum - 2) * XFERSIZE) + Pointer;
-
- /* Preform the write operation */
- MAL_Write(Addr, wlength);
- }
- /* Reset the global lenght and block number */
- wlength = 0;
- wBlockNum = 0;
-
- /* Update the state machine */
- DeviceState = STATE_dfuDNLOAD_SYNC;
- DeviceStatus[4] = DeviceState;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
- return USBD_OK;
- }
- else if (DeviceState == STATE_dfuMANIFEST)/* Manifestation in progress*/
- {
- /* Start leaving DFU mode */
- DFU_LeaveDFUMode(pdev);
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief EP0_RxReady
- * Handles the DFU control endpoint data OUT stage.
- * @param pdev: device instance
- * @retval status
- */
-static uint8_t EP0_RxReady (void *pdev)
-{
- return USBD_OK;
-}
-
-
-/******************************************************************************
- DFU Class requests management
-******************************************************************************/
-/**
- * @brief DFU_Req_DETACH
- * Handles the DFU DETACH request.
- * @param pdev: device instance
- * @param req: pointer to the request structure.
- * @retval None.
- */
-static void DFU_Req_DETACH(void *pdev, USB_SETUP_REQ *req)
-{
- if (DeviceState == STATE_dfuIDLE || DeviceState == STATE_dfuDNLOAD_SYNC
- || DeviceState == STATE_dfuDNLOAD_IDLE || DeviceState == STATE_dfuMANIFEST_SYNC
- || DeviceState == STATE_dfuUPLOAD_IDLE )
- {
- /* Update the state machine */
- DeviceState = STATE_dfuIDLE;
- DeviceStatus[0] = STATUS_OK;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/
- DeviceStatus[4] = DeviceState;
- DeviceStatus[5] = 0; /*iString*/
- wBlockNum = 0;
- wlength = 0;
- }
-
- /* Check the detach capability in the DFU functional descriptor */
- if ((usbd_dfu_CfgDesc[12 + (9 * USBD_ITF_MAX_NUM)]) & DFU_DETACH_MASK)
- {
- /* Perform an Attach-Detach operation on USB bus */
- DCD_DevDisconnect (pdev);
- DCD_DevConnect (pdev);
- }
- else
- {
- /* Wait for the period of time specified in Detach request */
- USB_OTG_BSP_mDelay (req->wValue);
- }
-}
-
-/**
- * @brief DFU_Req_DNLOAD
- * Handles the DFU DNLOAD request.
- * @param pdev: device instance
- * @param req: pointer to the request structure
- * @retval None
- */
-static void DFU_Req_DNLOAD(void *pdev, USB_SETUP_REQ *req)
-{
- /* Data setup request */
- if (req->wLength > 0)
- {
- if ((DeviceState == STATE_dfuIDLE) || (DeviceState == STATE_dfuDNLOAD_IDLE))
- {
- /* Update the global length and block number */
- wBlockNum = req->wValue;
- wlength = req->wLength;
-
- /* Update the state machine */
- DeviceState = STATE_dfuDNLOAD_SYNC;
- DeviceStatus[4] = DeviceState;
-
- /* Prepare the reception of the buffer over EP0 */
- USBD_CtlPrepareRx (pdev,
- (uint8_t*)MAL_Buffer,
- wlength);
- }
- /* Unsupported state */
- else
- {
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- }
- /* 0 Data DNLOAD request */
- else
- {
- /* End of DNLOAD operation*/
- if (DeviceState == STATE_dfuDNLOAD_IDLE || DeviceState == STATE_dfuIDLE )
- {
- Manifest_State = Manifest_In_Progress;
- DeviceState = STATE_dfuMANIFEST_SYNC;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
- DeviceStatus[4] = DeviceState;
- }
- else
- {
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- }
-}
-
-/**
- * @brief DFU_Req_UPLOAD
- * Handles the DFU UPLOAD request.
- * @param pdev: instance
- * @param req: pointer to the request structure
- * @retval status
- */
-static void DFU_Req_UPLOAD(void *pdev, USB_SETUP_REQ *req)
-{
- uint8_t *Phy_Addr = NULL;
- uint32_t Addr = 0;
-
- /* Data setup request */
- if (req->wLength > 0)
- {
- if ((DeviceState == STATE_dfuIDLE) || (DeviceState == STATE_dfuUPLOAD_IDLE))
- {
- /* Update the global langth and block number */
- wBlockNum = req->wValue;
- wlength = req->wLength;
-
- /* DFU Get Command */
- if (wBlockNum == 0)
- {
- /* Update the state machine */
- DeviceState = (wlength > 3)? STATE_dfuIDLE:STATE_dfuUPLOAD_IDLE;
- DeviceStatus[4] = DeviceState;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
-
- /* Store the values of all supported commands */
- MAL_Buffer[0] = CMD_GETCOMMANDS;
- MAL_Buffer[1] = CMD_SETADDRESSPOINTER;
- MAL_Buffer[2] = CMD_ERASE;
-
- /* Send the status data over EP0 */
- USBD_CtlSendData (pdev,
- (uint8_t *)(&(MAL_Buffer[0])),
- 3);
- }
- else if (wBlockNum > 1)
- {
- DeviceState = STATE_dfuUPLOAD_IDLE ;
- DeviceStatus[4] = DeviceState;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
- Addr = ((wBlockNum - 2) * XFERSIZE) + Pointer; /* Change is Accelerated*/
-
- /* Return the physical address where data are stored */
- Phy_Addr = MAL_Read(Addr, wlength);
-
- /* Send the status data over EP0 */
- USBD_CtlSendData (pdev,
- Phy_Addr,
- wlength);
- }
- else /* unsupported wBlockNum */
- {
- DeviceState = STATUS_ERRSTALLEDPKT;
- DeviceStatus[4] = DeviceState;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
-
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- }
- /* Unsupported state */
- else
- {
- wlength = 0;
- wBlockNum = 0;
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- }
- /* No Data setup request */
- else
- {
- DeviceState = STATE_dfuIDLE;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
- DeviceStatus[4] = DeviceState;
- }
-}
-
-/**
- * @brief DFU_Req_GETSTATUS
- * Handles the DFU GETSTATUS request.
- * @param pdev: instance
- * @retval status
- */
-static void DFU_Req_GETSTATUS(void *pdev)
-{
- switch (DeviceState)
- {
- case STATE_dfuDNLOAD_SYNC:
- if (wlength != 0)
- {
- DeviceState = STATE_dfuDNBUSY;
- DeviceStatus[4] = DeviceState;
- if ((wBlockNum == 0) && (MAL_Buffer[0] == CMD_ERASE))
- {
- MAL_GetStatus(Pointer, 0, DeviceStatus);
- }
- else
- {
- MAL_GetStatus(Pointer, 1, DeviceStatus);
- }
- }
- else /* (wlength==0)*/
- {
- DeviceState = STATE_dfuDNLOAD_IDLE;
- DeviceStatus[4] = DeviceState;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
- }
- break;
-
- case STATE_dfuMANIFEST_SYNC :
- if (Manifest_State == Manifest_In_Progress)
- {
- DeviceState = STATE_dfuMANIFEST;
- DeviceStatus[4] = DeviceState;
- DeviceStatus[1] = 1; /*bwPollTimeout = 1ms*/
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
- //break;
- }
- else if ((Manifest_State == Manifest_complete) && \
- ((usbd_dfu_CfgDesc[(11 + (9 * USBD_ITF_MAX_NUM))]) & 0x04))
- {
- DeviceState = STATE_dfuIDLE;
- DeviceStatus[4] = DeviceState;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
- //break;
- }
- break;
-
- default :
- break;
- }
-
- /* Send the status data over EP0 */
- USBD_CtlSendData (pdev,
- (uint8_t *)(&(DeviceStatus[0])),
- 6);
-}
-
-/**
- * @brief DFU_Req_CLRSTATUS
- * Handles the DFU CLRSTATUS request.
- * @param pdev: device instance
- * @retval status
- */
-static void DFU_Req_CLRSTATUS(void *pdev)
-{
- if (DeviceState == STATE_dfuERROR)
- {
- DeviceState = STATE_dfuIDLE;
- DeviceStatus[0] = STATUS_OK;/*bStatus*/
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/
- DeviceStatus[4] = DeviceState;/*bState*/
- DeviceStatus[5] = 0;/*iString*/
- }
- else
- { /*State Error*/
- DeviceState = STATE_dfuERROR;
- DeviceStatus[0] = STATUS_ERRUNKNOWN;/*bStatus*/
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/
- DeviceStatus[4] = DeviceState;/*bState*/
- DeviceStatus[5] = 0;/*iString*/
- }
-}
-
-/**
- * @brief DFU_Req_GETSTATE
- * Handles the DFU GETSTATE request.
- * @param pdev: device instance
- * @retval None
- */
-static void DFU_Req_GETSTATE(void *pdev)
-{
- /* Return the current state of the DFU interface */
- USBD_CtlSendData (pdev,
- &DeviceState,
- 1);
-}
-
-/**
- * @brief DFU_Req_ABORT
- * Handles the DFU ABORT request.
- * @param pdev: device instance
- * @retval None
- */
-static void DFU_Req_ABORT(void *pdev)
-{
- if (DeviceState == STATE_dfuIDLE || DeviceState == STATE_dfuDNLOAD_SYNC
- || DeviceState == STATE_dfuDNLOAD_IDLE || DeviceState == STATE_dfuMANIFEST_SYNC
- || DeviceState == STATE_dfuUPLOAD_IDLE )
- {
- DeviceState = STATE_dfuIDLE;
- DeviceStatus[0] = STATUS_OK;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/
- DeviceStatus[4] = DeviceState;
- DeviceStatus[5] = 0; /*iString*/
- wBlockNum = 0;
- wlength = 0;
- }
-}
-
-/**
- * @brief DFU_LeaveDFUMode
- * Handles the sub-protocol DFU leave DFU mode request (leaves DFU mode
- * and resets device to jump to user loaded code).
- * @param pdev: device instance
- * @retval None
- */
-void DFU_LeaveDFUMode(void *pdev)
-{
- Manifest_State = Manifest_complete;
-
- if ((usbd_dfu_CfgDesc[(11 + (9 * USBD_ITF_MAX_NUM))]) & 0x04)
- {
- DeviceState = STATE_dfuMANIFEST_SYNC;
- DeviceStatus[4] = DeviceState;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
- return;
- }
- else
- {
- DeviceState = STATE_dfuMANIFEST_WAIT_RESET;
- DeviceStatus[4] = DeviceState;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
-
- /* Disconnect the USB device */
- DCD_DevDisconnect (pdev);
-
- /* DeInitilialize the MAL(Media Access Layer) */
- MAL_DeInit();
-
- /* Generate system reset to allow jumping to the user code */
- NVIC_SystemReset();
-
- /* This instruction will not be reached (system reset) */
- return;
- }
-}
-
-/**
- * @brief USBD_DFU_GetCfgDesc
- * Returns configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_DFU_GetCfgDesc (uint8_t speed, uint16_t *length)
-{
- *length = sizeof (usbd_dfu_CfgDesc);
- return usbd_dfu_CfgDesc;
-}
-
-#ifdef USB_OTG_HS_CORE
-/**
- * @brief USBD_DFU_GetOtherCfgDesc
- * Returns other speed configuration descriptor.
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_DFU_GetOtherCfgDesc (uint8_t speed, uint16_t *length)
-{
- *length = sizeof (usbd_dfu_OtherCfgDesc);
- return usbd_dfu_OtherCfgDesc;
-}
-#endif
-
-/**
- * @brief USBD_DFU_GetUsrStringDesc
- * Manages the transfer of memory interfaces string descriptors.
- * @param speed : current device speed
- * @param index: desciptor index
- * @param length : pointer data length
- * @retval pointer to the descriptor table or NULL if the descriptor is not supported.
- */
-static uint8_t* USBD_DFU_GetUsrStringDesc (uint8_t speed, uint8_t index , uint16_t *length)
-{
- /* Check if the requested string interface is supported */
- if (index <= (USBD_IDX_INTERFACE_STR + USBD_ITF_MAX_NUM))
- {
-
-
- USBD_GetString ((uint8_t *)usbd_dfu_StringDesc[index - USBD_IDX_INTERFACE_STR - 1], USBD_StrDesc, length);
- return USBD_StrDesc;
- }
- /* Not supported Interface Descriptor index */
- else
- {
- return NULL;
- }
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_dfu_mal.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief Generic media access Layer.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_dfu_mal.h"
-
-#include "usbd_flash_if.h"
-
-#ifdef DFU_MAL_SUPPORT_OTP
- #include "usbd_otp_if.h"
-#endif
-
-#ifdef DFU_MAL_SUPPORT_MEM
- #include "usbd_mem_if_template.h"
-#endif
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Global Memories callback and string descriptors reference tables.
- To add a new memory, modify the value of MAX_USED_MEDIA in usbd_dfu_mal.h
- and add the pointer to the callback structure in this table.
- Then add the pointer to the memory string descriptor in usbd_dfu_StringDesc table.
- No other operation is required. */
-DFU_MAL_Prop_TypeDef* tMALTab[MAX_USED_MEDIA] = {
- &DFU_Flash_cb
-#ifdef DFU_MAL_SUPPORT_OTP
- , &DFU_Otp_cb
-#endif
-#ifdef DFU_MAL_SUPPORT_MEM
- , &DFU_Mem_cb
-#endif
-};
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-
-__ALIGN_BEGIN const uint8_t* usbd_dfu_StringDesc[MAX_USED_MEDIA] __ALIGN_END = {
- FLASH_IF_STRING
-#ifdef DFU_MAL_SUPPORT_OTP
- , OTP_IF_STRING
-#endif
-#ifdef DFU_MAL_SUPPORT_MEM
- , MEM_IF_STRING
-#endif
-};
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-/* RAM Buffer for Downloaded Data */
-__ALIGN_BEGIN uint8_t MAL_Buffer[XFERSIZE] __ALIGN_END ;
-
-/* Private function prototypes -----------------------------------------------*/
-static uint8_t MAL_CheckAdd (uint32_t Add);
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief MAL_Init
- * Initializes the Media on the STM32
- * @param None
- * @retval Result of the opeartion (MAL_OK in all cases)
- */
-uint16_t MAL_Init(void)
-{
- uint32_t memIdx = 0;
-
- /* Init all supported memories */
- for(memIdx = 0; memIdx < MAX_USED_MEDIA; memIdx++)
- {
- /* If the check addres is positive, exit with the memory index */
- if (tMALTab[memIdx]->pMAL_Init != NULL)
- {
- tMALTab[memIdx]->pMAL_Init();
- }
- }
-
- return MAL_OK;
-}
-
-/**
- * @brief MAL_DeInit
- * DeInitializes the Media on the STM32
- * @param None
- * @retval Result of the opeartion (MAL_OK in all cases)
- */
-uint16_t MAL_DeInit(void)
-{
- uint32_t memIdx = 0;
-
- /* Init all supported memories */
- for(memIdx = 0; memIdx < MAX_USED_MEDIA; memIdx++)
- {
- /* Check if the command is supported */
- if (tMALTab[memIdx]->pMAL_DeInit != NULL)
- {
- tMALTab[memIdx]->pMAL_DeInit();
- }
- }
-
- return MAL_OK;
-}
-
-/**
- * @brief MAL_Erase
- * Erase a sector of memory.
- * @param Add: Sector address/code
- * @retval Result of the opeartion: MAL_OK if all operations are OK else MAL_FAIL
- */
-uint16_t MAL_Erase(uint32_t Add)
-{
- uint32_t memIdx = MAL_CheckAdd(Add);
-
- /* Check if the area is protected */
- if (DFU_MAL_IS_PROTECTED_AREA(Add))
- {
- return MAL_FAIL;
- }
-
- if (memIdx < MAX_USED_MEDIA)
- {
- /* Check if the command is supported */
- if (tMALTab[memIdx]->pMAL_Erase != NULL)
- {
- return tMALTab[memIdx]->pMAL_Erase(Add);
- }
- else
- {
- return MAL_FAIL;
- }
- }
- else
- {
- return MAL_FAIL;
- }
-}
-
-/**
- * @brief MAL_Write
- * Write sectors of memory.
- * @param Add: Sector address/code
- * @param Len: Number of data to be written (in bytes)
- * @retval Result of the opeartion: MAL_OK if all operations are OK else MAL_FAIL
- */
-uint16_t MAL_Write (uint32_t Add, uint32_t Len)
-{
- uint32_t memIdx = MAL_CheckAdd(Add);
-
- /* Check if the area is protected */
- if (DFU_MAL_IS_PROTECTED_AREA(Add))
- {
- return MAL_FAIL;
- }
-
- if (memIdx < MAX_USED_MEDIA)
- {
- /* Check if the command is supported */
- if (tMALTab[memIdx]->pMAL_Write != NULL)
- {
- return tMALTab[memIdx]->pMAL_Write(Add, Len);
- }
- else
- {
- return MAL_FAIL;
- }
- }
- else
- {
- return MAL_FAIL;
- }
-}
-
-/**
- * @brief MAL_Read
- * Read sectors of memory.
- * @param Add: Sector address/code
- * @param Len: Number of data to be written (in bytes)
- * @retval Buffer pointer
- */
-uint8_t *MAL_Read (uint32_t Add, uint32_t Len)
-{
- uint32_t memIdx = MAL_CheckAdd(Add);
-
- if (memIdx < MAX_USED_MEDIA)
- {
- /* Check if the command is supported */
- if (tMALTab[memIdx]->pMAL_Read != NULL)
- {
- return tMALTab[memIdx]->pMAL_Read(Add, Len);
- }
- else
- {
- return MAL_Buffer;
- }
- }
- else
- {
- return MAL_Buffer;
- }
-}
-
-/**
- * @brief MAL_GetStatus
- * Get the status of a given memory.
- * @param Add: Sector address/code (allow to determine which memory will be addressed)
- * @param Cmd: 0 for erase and 1 for write
- * @param buffer: pointer to the buffer where the status data will be stored.
- * @retval Buffer pointer
- */
-uint16_t MAL_GetStatus(uint32_t Add , uint8_t Cmd, uint8_t *buffer)
-{
- uint32_t memIdx = MAL_CheckAdd(Add);
-
- if (memIdx < MAX_USED_MEDIA)
- {
- if (Cmd & 0x01)
- {
- SET_POLLING_TIMING(tMALTab[memIdx]->EraseTiming);
- }
- else
- {
- SET_POLLING_TIMING(tMALTab[memIdx]->WriteTiming);
- }
-
- return MAL_OK;
- }
- else
- {
- return MAL_FAIL;
- }
-}
-
-/**
- * @brief MAL_CheckAdd
- * Determine which memory should be managed.
- * @param Add: Sector address/code (allow to determine which memory will be addressed)
- * @retval Index of the addressed memory.
- */
-static uint8_t MAL_CheckAdd(uint32_t Add)
-{
- uint32_t memIdx = 0;
-
- /* Check with all supported memories */
- for(memIdx = 0; memIdx < MAX_USED_MEDIA; memIdx++)
- {
- /* If the check addres is positive, exit with the memory index */
- if (tMALTab[memIdx]->pMAL_CheckAdd(Add) == MAL_OK)
- {
- return memIdx;
- }
- }
- /* If no memory found, return MAX_USED_MEDIA */
- return (MAX_USED_MEDIA);
-}
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_flash_if.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief Specific media access Layer for internal flash.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_flash_if.h"
-#include "usbd_dfu_mal.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-
-/* Private function prototypes -----------------------------------------------*/
-uint16_t FLASH_If_Init(void);
-uint16_t FLASH_If_Erase (uint32_t Add);
-uint16_t FLASH_If_Write (uint32_t Add, uint32_t Len);
-uint8_t *FLASH_If_Read (uint32_t Add, uint32_t Len);
-uint16_t FLASH_If_DeInit(void);
-uint16_t FLASH_If_CheckAdd(uint32_t Add);
-
-
-/* Private variables ---------------------------------------------------------*/
-DFU_MAL_Prop_TypeDef DFU_Flash_cb =
- {
- FLASH_IF_STRING,
- FLASH_If_Init,
- FLASH_If_DeInit,
- FLASH_If_Erase,
- FLASH_If_Write,
- FLASH_If_Read,
- FLASH_If_CheckAdd,
- 50, /* Erase Time in ms */
- 50 /* Programming Time in ms */
- };
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief FLASH_If_Init
- * Memory initialization routine.
- * @param None
- * @retval MAL_OK if operation is successeful, MAL_FAIL else.
- */
-uint16_t FLASH_If_Init(void)
-{
- /* Unlock the internal flash */
- FLASH_Unlock();
-
- return MAL_OK;
-}
-
-/**
- * @brief FLASH_If_DeInit
- * Memory deinitialization routine.
- * @param None
- * @retval MAL_OK if operation is successeful, MAL_FAIL else.
- */
-uint16_t FLASH_If_DeInit(void)
-{
- /* Lock the internal flash */
- FLASH_Lock();
-
- return MAL_OK;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_If_Erase
-* Description : Erase sector
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-uint16_t FLASH_If_Erase(uint32_t Add)
-{
-#ifdef STM32F2XX
- /* Check which sector has to be erased */
- if (Add < 0x08004000)
- {
- FLASH_EraseSector(FLASH_Sector_0, VoltageRange_3);
- }
- else if (Add < 0x08008000)
- {
- FLASH_EraseSector(FLASH_Sector_1, VoltageRange_3);
- }
- else if (Add < 0x0800C000)
- {
- FLASH_EraseSector(FLASH_Sector_2, VoltageRange_3);
- }
- else if (Add < 0x08010000)
- {
- FLASH_EraseSector(FLASH_Sector_3, VoltageRange_3);
- }
- else if (Add < 0x08020000)
- {
- FLASH_EraseSector(FLASH_Sector_4, VoltageRange_3);
- }
- else if (Add < 0x08040000)
- {
- FLASH_EraseSector(FLASH_Sector_5, VoltageRange_3);
- }
- else if (Add < 0x08060000)
- {
- FLASH_EraseSector(FLASH_Sector_6, VoltageRange_3);
- }
- else if (Add < 0x08080000)
- {
- FLASH_EraseSector(FLASH_Sector_7, VoltageRange_3);
- }
- else if (Add < 0x080A0000)
- {
- FLASH_EraseSector(FLASH_Sector_8, VoltageRange_3);
- }
- else if (Add < 0x080C0000)
- {
- FLASH_EraseSector(FLASH_Sector_9, VoltageRange_3);
- }
- else if (Add < 0x080E0000)
- {
- FLASH_EraseSector(FLASH_Sector_10, VoltageRange_3);
- }
- else if (Add < 0x08100000)
- {
- FLASH_EraseSector(FLASH_Sector_11, VoltageRange_3);
- }
- else
- {
- return MAL_FAIL;
- }
-#elif defined(STM32F10X_CL)
- /* Call the standard Flash erase function */
- FLASH_ErasePage(Add);
-#endif /* STM32F2XX */
-
- return MAL_OK;
-}
-
-/**
- * @brief FLASH_If_Write
- * Memory write routine.
- * @param Add: Address to be written to.
- * @param Len: Number of data to be written (in bytes).
- * @retval MAL_OK if operation is successeful, MAL_FAIL else.
- */
-uint16_t FLASH_If_Write(uint32_t Add, uint32_t Len)
-{
- uint32_t idx = 0;
-
- if (Len & 0x3) /* Not an aligned data */
- {
- for (idx = Len; idx < ((Len & 0xFFFC) + 4); idx++)
- {
- MAL_Buffer[idx] = 0xFF;
- }
- }
-
- /* Data received are Word multiple */
- for (idx = 0; idx < Len; idx = idx + 4)
- {
- FLASH_ProgramWord(Add, *(uint32_t *)(MAL_Buffer + idx));
- Add += 4;
- }
- return MAL_OK;
-}
-
-/**
- * @brief FLASH_If_Read
- * Memory read routine.
- * @param Add: Address to be read from.
- * @param Len: Number of data to be read (in bytes).
- * @retval Pointer to the phyisical address where data should be read.
- */
-uint8_t *FLASH_If_Read (uint32_t Add, uint32_t Len)
-{
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- uint32_t idx = 0;
- for (idx = 0; idx < Len; idx += 4)
- {
- *(uint32_t*)(MAL_Buffer + idx) = *(uint32_t *)(Add + idx);
- }
- return (uint8_t*)(MAL_Buffer);
-#else
- return (uint8_t *)(Add);
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-}
-
-/**
- * @brief FLASH_If_CheckAdd
- * Check if the address is an allowed address for this memory.
- * @param Add: Address to be checked.
- * @param Len: Number of data to be read (in bytes).
- * @retval MAL_OK if the address is allowed, MAL_FAIL else.
- */
-uint16_t FLASH_If_CheckAdd(uint32_t Add)
-{
- if ((Add >= FLASH_START_ADD) && (Add < FLASH_END_ADD))
- {
- return MAL_OK;
- }
- else
- {
- return MAL_FAIL;
- }
-}
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_mem_if_template.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief Specific media access Layer for a template memory. This file is
- provided as template example showing how to implement a new memory
- interface based on pre-defined API.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_mem_if_template.h"
-#include "usbd_dfu_mal.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-
-/* Private function prototypes -----------------------------------------------*/
-uint16_t MEM_If_Init(void);
-uint16_t MEM_If_Erase (uint32_t Add);
-uint16_t MEM_If_Write (uint32_t Add, uint32_t Len);
-uint8_t *MEM_If_Read (uint32_t Add, uint32_t Len);
-uint16_t MEM_If_DeInit(void);
-uint16_t MEM_If_CheckAdd(uint32_t Add);
-
-
-/* Private variables ---------------------------------------------------------*/
-DFU_MAL_Prop_TypeDef DFU_Mem_cb =
- {
- MEM_IF_STRING,
- MEM_If_Init,
- MEM_If_DeInit,
- MEM_If_Erase,
- MEM_If_Write,
- MEM_If_Read,
- MEM_If_CheckAdd,
- 10, /* Erase Time in ms */
- 10 /* Programming Time in ms */
- };
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief MEM_If_Init
- * Memory initialization routine.
- * @param None
- * @retval MAL_OK if operation is successeful, MAL_FAIL else.
- */
-uint16_t MEM_If_Init(void)
-{
- return MAL_OK;
-}
-
-/**
- * @brief MEM_If_DeInit
- * Memory deinitialization routine.
- * @param None
- * @retval MAL_OK if operation is successeful, MAL_FAIL else.
- */
-uint16_t MEM_If_DeInit(void)
-{
- return MAL_OK;
-}
-
-/**
- * @brief MEM_If_Erase
- * Erase sector.
- * @param Add: Address of sector to be erased.
- * @retval MAL_OK if operation is successeful, MAL_FAIL else.
- */
-uint16_t MEM_If_Erase(uint32_t Add)
-{
- return MAL_OK;
-}
-
-/**
- * @brief MEM_If_Write
- * Memory write routine.
- * @param Add: Address to be written to.
- * @param Len: Number of data to be written (in bytes).
- * @retval MAL_OK if operation is successeful, MAL_FAIL else.
- */
-uint16_t MEM_If_Write(uint32_t Add, uint32_t Len)
-{
- return MAL_OK;
-}
-
-/**
- * @brief MEM_If_Read
- * Memory read routine.
- * @param Add: Address to be read from.
- * @param Len: Number of data to be read (in bytes).
- * @retval Pointer to the phyisical address where data should be read.
- */
-uint8_t *MEM_If_Read (uint32_t Add, uint32_t Len)
-{
- /* Return a valid address to avoid HardFault */
- return (uint8_t*)(MAL_Buffer);
-}
-
-/**
- * @brief MEM_If_CheckAdd
- * Check if the address is an allowed address for this memory.
- * @param Add: Address to be checked.
- * @param Len: Number of data to be read (in bytes).
- * @retval MAL_OK if the address is allowed, MAL_FAIL else.
- */
-uint16_t MEM_If_CheckAdd(uint32_t Add)
-{
- if ((Add >= MEM_START_ADD) && (Add < MEM_END_ADD))
- {
- return MAL_OK;
- }
- else
- {
- return MAL_FAIL;
- }
-}
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_otp_if.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief Specific media access Layer for OTP (One Time Programming) memory.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_otp_if.h"
-#include "usbd_dfu_mal.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-
-/* Private function prototypes -----------------------------------------------*/
-uint16_t OTP_If_Write (uint32_t Add, uint32_t Len);
-uint8_t *OTP_If_Read (uint32_t Add, uint32_t Len);
-uint16_t OTP_If_DeInit(void);
-uint16_t OTP_If_CheckAdd(uint32_t Add);
-
-
-/* Private variables ---------------------------------------------------------*/
-DFU_MAL_Prop_TypeDef DFU_Otp_cb =
- {
- OTP_IF_STRING,
- NULL, /* Init not supported*/
- NULL, /* DeInit not supported */
- NULL, /* Erase not supported */
- OTP_If_Write,
- OTP_If_Read,
- OTP_If_CheckAdd,
- 1, /* Erase Time in ms */
- 10 /* Programming Time in ms */
- };
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief OTP_If_Write
- * Memory write routine.
- * @param Add: Address to be written to.
- * @param Len: Number of data to be written (in bytes).
- * @retval MAL_OK if operation is successeful, MAL_FAIL else.
- */
-uint16_t OTP_If_Write(uint32_t Add, uint32_t Len)
-{
- uint32_t idx = 0;
-
- if (Len & 0x3) /* Not an aligned data */
- {
- for (idx = Len; idx < ((Len & 0xFFFC) + 4); idx++)
- {
- MAL_Buffer[idx] = 0xFF;
- }
- }
-
- /* Data received are Word multiple */
- for (idx = 0; idx < Len; idx = idx + 4)
- {
- FLASH_ProgramWord(Add, *(uint32_t *)(MAL_Buffer + idx));
- Add += 4;
- }
- return MAL_OK;
-}
-
-/**
- * @brief OTP_If_Read
- * Memory read routine.
- * @param Add: Address to be read from.
- * @param Len: Number of data to be read (in bytes).
- * @retval Pointer to the phyisical address where data should be read.
- */
-uint8_t *OTP_If_Read (uint32_t Add, uint32_t Len)
-{
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- uint32_t idx = 0;
- for (idx = 0; idx < Len; idx += 4)
- {
- *(uint32_t*)(MAL_Buffer + idx) = *(uint32_t *)(Add + idx);
- }
- return (uint8_t*)(MAL_Buffer);
-#else
- return (uint8_t*)(Add);
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-}
-
-/**
- * @brief OTP_If_CheckAdd
- * Check if the address is an allowed address for this memory.
- * @param Add: Address to be checked.
- * @param Len: Number of data to be read (in bytes).
- * @retval MAL_OK if the address is allowed, MAL_FAIL else.
- */
-uint16_t OTP_If_CheckAdd(uint32_t Add)
-{
- if ((Add >= OTP_START_ADD) && (Add < OTP_END_ADD))
- {
- return MAL_OK;
- }
- else
- {
- return MAL_FAIL;
- }
-}
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_hid_core.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief header file for the usbd_hid_core.c file.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-
-#ifndef __USB_HID_CORE_H_
-#define __USB_HID_CORE_H_
-
-#include "usbd_ioreq.h"
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USBD_HID
- * @brief This file is the Header file for USBD_msc.c
- * @{
- */
-
-
-/** @defgroup USBD_HID_Exported_Defines
- * @{
- */
-#define USB_HID_CONFIG_DESC_SIZ 34
-#define USB_HID_DESC_SIZ 9
-#define HID_MOUSE_REPORT_DESC_SIZE 74
-
-#define HID_DESCRIPTOR_TYPE 0x21
-#define HID_REPORT_DESC 0x22
-
-
-#define HID_REQ_SET_PROTOCOL 0x0B
-#define HID_REQ_GET_PROTOCOL 0x03
-
-#define HID_REQ_SET_IDLE 0x0A
-#define HID_REQ_GET_IDLE 0x02
-
-#define HID_REQ_SET_REPORT 0x09
-#define HID_REQ_GET_REPORT 0x01
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CORE_Exported_TypesDefinitions
- * @{
- */
-
-
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_CORE_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_CORE_Exported_Variables
- * @{
- */
-
-extern USBD_Class_cb_TypeDef USBD_HID_cb;
-/**
- * @}
- */
-
-/** @defgroup USB_CORE_Exported_Functions
- * @{
- */
-uint8_t USBD_HID_SendReport (USB_OTG_CORE_HANDLE *pdev,
- uint8_t *report,
- uint16_t len);
-/**
- * @}
- */
-
-#endif // __USB_HID_CORE_H_
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_hid_core.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief This file provides the HID core functions.
- *
- * @verbatim
- *
- * ===================================================================
- * HID Class Description
- * ===================================================================
- * This module manages the HID class V1.11 following the "Device Class Definition
- * for Human Interface Devices (HID) Version 1.11 Jun 27, 2001".
- * This driver implements the following aspects of the specification:
- * - The Boot Interface Subclass
- * - The Mouse protocol
- * - Usage Page : Generic Desktop
- * - Usage : Joystick)
- * - Collection : Application
- *
- * @note In HS mode and when the DMA is used, all variables and data structures
- * dealing with the DMA during the transaction process should be 32-bit aligned.
- *
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_hid_core.h"
-#include "usbd_desc.h"
-#include "usbd_req.h"
-
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup USBD_HID
- * @brief usbd core module
- * @{
- */
-
-/** @defgroup USBD_HID_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_HID_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_HID_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-
-
-/** @defgroup USBD_HID_Private_FunctionPrototypes
- * @{
- */
-
-
-static uint8_t USBD_HID_Init (void *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_HID_DeInit (void *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_HID_Setup (void *pdev,
- USB_SETUP_REQ *req);
-
-static uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length);
-
-static uint8_t USBD_HID_DataIn (void *pdev, uint8_t epnum);
-/**
- * @}
- */
-
-/** @defgroup USBD_HID_Private_Variables
- * @{
- */
-
-USBD_Class_cb_TypeDef USBD_HID_cb =
-{
- USBD_HID_Init,
- USBD_HID_DeInit,
- USBD_HID_Setup,
- NULL, /*EP0_TxSent*/
- NULL, /*EP0_RxReady*/
- USBD_HID_DataIn, /*DataIn*/
- NULL, /*DataOut*/
- NULL, /*SOF */
- NULL,
- NULL,
- USBD_HID_GetCfgDesc,
-#ifdef USB_OTG_HS_CORE
- USBD_HID_GetCfgDesc, /* use same config as per FS */
-#endif
-};
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN static uint32_t USBD_HID_AltSet __ALIGN_END = 0;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN static uint32_t USBD_HID_Protocol __ALIGN_END = 0;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN static uint32_t USBD_HID_IdleState __ALIGN_END = 0;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-/* USB HID device Configuration Descriptor */
-__ALIGN_BEGIN static uint8_t USBD_HID_CfgDesc[USB_HID_CONFIG_DESC_SIZ] __ALIGN_END =
-{
- 0x09, /* bLength: Configuration Descriptor size */
- USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
- USB_HID_CONFIG_DESC_SIZ,
- /* wTotalLength: Bytes returned */
- 0x00,
- 0x01, /*bNumInterfaces: 1 interface*/
- 0x01, /*bConfigurationValue: Configuration value*/
- 0x00, /*iConfiguration: Index of string descriptor describing
- the configuration*/
- 0xE0, /*bmAttributes: bus powered and Support Remote Wake-up */
- 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/
-
- /************** Descriptor of Joystick Mouse interface ****************/
- /* 09 */
- 0x09, /*bLength: Interface Descriptor size*/
- USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/
- 0x00, /*bInterfaceNumber: Number of Interface*/
- 0x00, /*bAlternateSetting: Alternate setting*/
- 0x01, /*bNumEndpoints*/
- 0x03, /*bInterfaceClass: HID*/
- 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/
- 0x02, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/
- 0, /*iInterface: Index of string descriptor*/
- /******************** Descriptor of Joystick Mouse HID ********************/
- /* 18 */
- 0x09, /*bLength: HID Descriptor size*/
- HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/
- 0x11, /*bcdHID: HID Class Spec release number*/
- 0x01,
- 0x00, /*bCountryCode: Hardware target country*/
- 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/
- 0x22, /*bDescriptorType*/
- HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/
- 0x00,
- /******************** Descriptor of Mouse endpoint ********************/
- /* 27 */
- 0x07, /*bLength: Endpoint Descriptor size*/
- USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/
-
- HID_IN_EP, /*bEndpointAddress: Endpoint Address (IN)*/
- 0x03, /*bmAttributes: Interrupt endpoint*/
- HID_IN_PACKET, /*wMaxPacketSize: 4 Byte max */
- 0x00,
- 0x0A, /*bInterval: Polling Interval (10 ms)*/
- /* 34 */
-} ;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[HID_MOUSE_REPORT_DESC_SIZE] __ALIGN_END =
-{
- 0x05, 0x01,
- 0x09, 0x02,
- 0xA1, 0x01,
- 0x09, 0x01,
-
- 0xA1, 0x00,
- 0x05, 0x09,
- 0x19, 0x01,
- 0x29, 0x03,
-
- 0x15, 0x00,
- 0x25, 0x01,
- 0x95, 0x03,
- 0x75, 0x01,
-
- 0x81, 0x02,
- 0x95, 0x01,
- 0x75, 0x05,
- 0x81, 0x01,
-
- 0x05, 0x01,
- 0x09, 0x30,
- 0x09, 0x31,
- 0x09, 0x38,
-
- 0x15, 0x81,
- 0x25, 0x7F,
- 0x75, 0x08,
- 0x95, 0x03,
-
- 0x81, 0x06,
- 0xC0, 0x09,
- 0x3c, 0x05,
- 0xff, 0x09,
-
- 0x01, 0x15,
- 0x00, 0x25,
- 0x01, 0x75,
- 0x01, 0x95,
-
- 0x02, 0xb1,
- 0x22, 0x75,
- 0x06, 0x95,
- 0x01, 0xb1,
-
- 0x01, 0xc0
-};
-
-/**
- * @}
- */
-
-/** @defgroup USBD_HID_Private_Functions
- * @{
- */
-
-/**
- * @brief USBD_HID_Init
- * Initialize the HID interface
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_HID_Init (void *pdev,
- uint8_t cfgidx)
-{
-
- /* Open EP IN */
- DCD_EP_Open(pdev,
- HID_IN_EP,
- HID_IN_PACKET,
- USB_OTG_EP_INT);
-
- /* Open EP OUT */
- DCD_EP_Open(pdev,
- HID_OUT_EP,
- HID_OUT_PACKET,
- USB_OTG_EP_INT);
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_Init
- * DeInitialize the HID layer
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_HID_DeInit (void *pdev,
- uint8_t cfgidx)
-{
- /* Close HID EPs */
- DCD_EP_Close (pdev , HID_IN_EP);
- DCD_EP_Close (pdev , HID_OUT_EP);
-
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_Setup
- * Handle the HID specific requests
- * @param pdev: instance
- * @param req: usb requests
- * @retval status
- */
-static uint8_t USBD_HID_Setup (void *pdev,
- USB_SETUP_REQ *req)
-{
- uint16_t len = 0;
- uint8_t *pbuf = NULL;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest)
- {
-
-
- case HID_REQ_SET_PROTOCOL:
- USBD_HID_Protocol = (uint8_t)(req->wValue);
- break;
-
- case HID_REQ_GET_PROTOCOL:
- USBD_CtlSendData (pdev,
- (uint8_t *)&USBD_HID_Protocol,
- 1);
- break;
-
- case HID_REQ_SET_IDLE:
- USBD_HID_IdleState = (uint8_t)(req->wValue >> 8);
- break;
-
- case HID_REQ_GET_IDLE:
- USBD_CtlSendData (pdev,
- (uint8_t *)&USBD_HID_IdleState,
- 1);
- break;
-
- default:
- USBD_CtlError (pdev, req);
- return USBD_FAIL;
- }
- break;
-
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_DESCRIPTOR:
- if( req->wValue >> 8 == HID_REPORT_DESC)
- {
- len = MIN(HID_MOUSE_REPORT_DESC_SIZE , req->wLength);
- pbuf = HID_MOUSE_ReportDesc;
- }
- else if( req->wValue >> 8 == HID_DESCRIPTOR_TYPE)
- {
-
-//#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
-// pbuf = USBD_HID_Desc;
-//#else
- pbuf = USBD_HID_CfgDesc + 0x12;
-//#endif
- len = MIN(USB_HID_DESC_SIZ , req->wLength);
- }
-
- USBD_CtlSendData (pdev,
- pbuf,
- len);
-
- break;
-
- case USB_REQ_GET_INTERFACE :
- USBD_CtlSendData (pdev,
- (uint8_t *)&USBD_HID_AltSet,
- 1);
- break;
-
- case USB_REQ_SET_INTERFACE :
- USBD_HID_AltSet = (uint8_t)(req->wValue);
- break;
- }
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_SendReport
- * Send HID Report
- * @param pdev: device instance
- * @param buff: pointer to report
- * @retval status
- */
-uint8_t USBD_HID_SendReport (USB_OTG_CORE_HANDLE *pdev,
- uint8_t *report,
- uint16_t len)
-{
- if (pdev->dev.device_status == USB_OTG_CONFIGURED )
- {
- DCD_EP_Tx (pdev, HID_IN_EP, report, len);
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_GetCfgDesc
- * return configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length)
-{
- *length = sizeof (USBD_HID_CfgDesc);
- return USBD_HID_CfgDesc;
-}
-
-/**
- * @brief USBD_HID_DataIn
- * handle data IN Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_HID_DataIn (void *pdev,
- uint8_t epnum)
-{
-
- /* Ensure that the FIFO is empty before a new transfer, this condition could
- be caused by a new transfer before the end of the previous transfer */
- DCD_EP_Flush(pdev, HID_IN_EP);
- return USBD_OK;
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_msc_bot.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief header for the usbd_msc_bot.c file
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-
-#include "usbd_core.h"
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_MSC_BOT_H
-#define __USBD_MSC_BOT_H
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup MSC_BOT
- * @brief This file is the Header file for usbd_bot.c
- * @{
- */
-
-
-/** @defgroup USBD_CORE_Exported_Defines
- * @{
- */
-#define BOT_IDLE 0 /* Idle state */
-#define BOT_DATA_OUT 1 /* Data Out state */
-#define BOT_DATA_IN 2 /* Data In state */
-#define BOT_LAST_DATA_IN 3 /* Last Data In Last */
-#define BOT_SEND_DATA 4 /* Send Immediate data */
-
-#define BOT_CBW_SIGNATURE 0x43425355
-#define BOT_CSW_SIGNATURE 0x53425355
-#define BOT_CBW_LENGTH 31
-#define BOT_CSW_LENGTH 13
-
-/* CSW Status Definitions */
-#define CSW_CMD_PASSED 0x00
-#define CSW_CMD_FAILED 0x01
-#define CSW_PHASE_ERROR 0x02
-
-/* BOT Status */
-#define BOT_STATE_NORMAL 0
-#define BOT_STATE_RECOVERY 1
-#define BOT_STATE_ERROR 2
-
-
-#define DIR_IN 0
-#define DIR_OUT 1
-#define BOTH_DIR 2
-
-/**
- * @}
- */
-
-/** @defgroup MSC_CORE_Private_TypesDefinitions
- * @{
- */
-
-typedef struct _MSC_BOT_CBW
-{
- uint32_t dSignature;
- uint32_t dTag;
- uint32_t dDataLength;
- uint8_t bmFlags;
- uint8_t bLUN;
- uint8_t bCBLength;
- uint8_t CB[16];
-}
-MSC_BOT_CBW_TypeDef;
-
-
-typedef struct _MSC_BOT_CSW
-{
- uint32_t dSignature;
- uint32_t dTag;
- uint32_t dDataResidue;
- uint8_t bStatus;
-}
-MSC_BOT_CSW_TypeDef;
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CORE_Exported_Types
- * @{
- */
-
-extern uint8_t MSC_BOT_Data[];
-extern uint16_t MSC_BOT_DataLen;
-extern uint8_t MSC_BOT_State;
-extern uint8_t MSC_BOT_BurstMode;
-extern MSC_BOT_CBW_TypeDef MSC_BOT_cbw;
-extern MSC_BOT_CSW_TypeDef MSC_BOT_csw;
-/**
- * @}
- */
-/** @defgroup USBD_CORE_Exported_FunctionsPrototypes
- * @{
- */
-void MSC_BOT_Init (USB_OTG_CORE_HANDLE *pdev);
-void MSC_BOT_Reset (USB_OTG_CORE_HANDLE *pdev);
-void MSC_BOT_DeInit (USB_OTG_CORE_HANDLE *pdev);
-void MSC_BOT_DataIn (USB_OTG_CORE_HANDLE *pdev,
- uint8_t epnum);
-
-void MSC_BOT_DataOut (USB_OTG_CORE_HANDLE *pdev,
- uint8_t epnum);
-
-void MSC_BOT_SendCSW (USB_OTG_CORE_HANDLE *pdev,
- uint8_t CSW_Status);
-
-void MSC_BOT_CplClrFeature (USB_OTG_CORE_HANDLE *pdev,
- uint8_t epnum);
-/**
- * @}
- */
-
-#endif /* __USBD_MSC_BOT_H */
-/**
- * @}
- */
-
-/**
-* @}
-*/
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_msc_core.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief header for the usbd_msc_core.c file
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef _USB_MSC_CORE_H_
-#define _USB_MSC_CORE_H_
-
-#include "usbd_ioreq.h"
-
-/** @addtogroup USBD_MSC_BOT
- * @{
- */
-
-/** @defgroup USBD_MSC
- * @brief This file is the Header file for USBD_msc.c
- * @{
- */
-
-
-/** @defgroup USBD_BOT_Exported_Defines
- * @{
- */
-
-
-#define BOT_GET_MAX_LUN 0xFE
-#define BOT_RESET 0xFF
-#define USB_MSC_CONFIG_DESC_SIZ 32
-
-#define MSC_EPIN_SIZE *(uint16_t *)(((USB_OTG_CORE_HANDLE *)pdev)->dev.pConfig_descriptor + 22)
-
-#define MSC_EPOUT_SIZE *(uint16_t *)(((USB_OTG_CORE_HANDLE *)pdev)->dev.pConfig_descriptor + 29)
-
-/**
- * @}
- */
-
-/** @defgroup USB_CORE_Exported_Types
- * @{
- */
-
-extern USBD_Class_cb_TypeDef USBD_MSC_cb;
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif // _USB_MSC_CORE_H_
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_msc_data.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief header for the usbd_msc_data.c file
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-
-#ifndef _USBD_MSC_DATA_H_
-#define _USBD_MSC_DATA_H_
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_conf.h"
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USB_INFO
- * @brief general defines for the usb device library file
- * @{
- */
-
-/** @defgroup USB_INFO_Exported_Defines
- * @{
- */
-#define MODE_SENSE6_LEN 8
-#define MODE_SENSE10_LEN 8
-#define LENGTH_INQUIRY_PAGE00 7
-#define LENGTH_FORMAT_CAPACITIES 20
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_INFO_Exported_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_INFO_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_INFO_Exported_Variables
- * @{
- */
-extern const uint8_t MSC_Page00_Inquiry_Data[];
-extern const uint8_t MSC_Mode_Sense6_data[];
-extern const uint8_t MSC_Mode_Sense10_data[] ;
-
-/**
- * @}
- */
-
-/** @defgroup USBD_INFO_Exported_FunctionsPrototype
- * @{
- */
-
-/**
- * @}
- */
-
-#endif /* _USBD_MSC_DATA_H_ */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_msc_mem.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief header for the STORAGE DISK file file
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-
-#ifndef __USBD_MEM_H
-#define __USBD_MEM_H
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_def.h"
-
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USBD_MEM
- * @brief header file for the storage disk file
- * @{
- */
-
-/** @defgroup USBD_MEM_Exported_Defines
- * @{
- */
-#define USBD_STD_INQUIRY_LENGTH 36
-/**
- * @}
- */
-
-
-/** @defgroup USBD_MEM_Exported_TypesDefinitions
- * @{
- */
-
-typedef struct _USBD_STORAGE
-{
- int8_t (* Init) (uint8_t lun);
- int8_t (* GetCapacity) (uint8_t lun, uint32_t *block_num, uint32_t *block_size);
- int8_t (* IsReady) (uint8_t lun);
- int8_t (* IsWriteProtected) (uint8_t lun);
- int8_t (* Read) (uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
- int8_t (* Write)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
- int8_t (* GetMaxLun)(void);
- int8_t *pInquiry;
-
-}USBD_STORAGE_cb_TypeDef;
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_MEM_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_MEM_Exported_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_MEM_Exported_FunctionsPrototype
- * @{
- */
-extern USBD_STORAGE_cb_TypeDef *USBD_STORAGE_fops;
-/**
- * @}
- */
-
-#endif /* __USBD_MEM_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_msc_scsi.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief header for the usbd_msc_scsi.c file
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_MSC_SCSI_H
-#define __USBD_MSC_SCSI_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_def.h"
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USBD_SCSI
- * @brief header file for the storage disk file
- * @{
- */
-
-/** @defgroup USBD_SCSI_Exported_Defines
- * @{
- */
-
-#define SENSE_LIST_DEEPTH 4
-
-/* SCSI Commands */
-#define SCSI_FORMAT_UNIT 0x04
-#define SCSI_INQUIRY 0x12
-#define SCSI_MODE_SELECT6 0x15
-#define SCSI_MODE_SELECT10 0x55
-#define SCSI_MODE_SENSE6 0x1A
-#define SCSI_MODE_SENSE10 0x5A
-#define SCSI_ALLOW_MEDIUM_REMOVAL 0x1E
-#define SCSI_READ6 0x08
-#define SCSI_READ10 0x28
-#define SCSI_READ12 0xA8
-#define SCSI_READ16 0x88
-
-#define SCSI_READ_CAPACITY10 0x25
-#define SCSI_READ_CAPACITY16 0x9E
-
-#define SCSI_REQUEST_SENSE 0x03
-#define SCSI_START_STOP_UNIT 0x1B
-#define SCSI_TEST_UNIT_READY 0x00
-#define SCSI_WRITE6 0x0A
-#define SCSI_WRITE10 0x2A
-#define SCSI_WRITE12 0xAA
-#define SCSI_WRITE16 0x8A
-
-#define SCSI_VERIFY10 0x2F
-#define SCSI_VERIFY12 0xAF
-#define SCSI_VERIFY16 0x8F
-
-#define SCSI_SEND_DIAGNOSTIC 0x1D
-#define SCSI_READ_FORMAT_CAPACITIES 0x23
-
-#define NO_SENSE 0
-#define RECOVERED_ERROR 1
-#define NOT_READY 2
-#define MEDIUM_ERROR 3
-#define HARDWARE_ERROR 4
-#define ILLEGAL_REQUEST 5
-#define UNIT_ATTENTION 6
-#define DATA_PROTECT 7
-#define BLANK_CHECK 8
-#define VENDOR_SPECIFIC 9
-#define COPY_ABORTED 10
-#define ABORTED_COMMAND 11
-#define VOLUME_OVERFLOW 13
-#define MISCOMPARE 14
-
-
-#define INVALID_CDB 0x20
-#define INVALID_FIELED_IN_COMMAND 0x24
-#define PARAMETER_LIST_LENGTH_ERROR 0x1A
-#define INVALID_FIELD_IN_PARAMETER_LIST 0x26
-#define ADDRESS_OUT_OF_RANGE 0x21
-#define MEDIUM_NOT_PRESENT 0x3A
-#define MEDIUM_HAVE_CHANGED 0x28
-#define WRITE_PROTECTED 0x27
-#define UNRECOVERED_READ_ERROR 0x11
-#define WRITE_FAULT 0x03
-
-#define READ_FORMAT_CAPACITY_DATA_LEN 0x0C
-#define READ_CAPACITY10_DATA_LEN 0x08
-#define MODE_SENSE10_DATA_LEN 0x08
-#define MODE_SENSE6_DATA_LEN 0x04
-#define REQUEST_SENSE_DATA_LEN 0x12
-#define STANDARD_INQUIRY_DATA_LEN 0x24
-#define BLKVFY 0x04
-
-extern uint8_t Page00_Inquiry_Data[];
-extern uint8_t Standard_Inquiry_Data[];
-extern uint8_t Standard_Inquiry_Data2[];
-extern uint8_t Mode_Sense6_data[];
-extern uint8_t Mode_Sense10_data[];
-extern uint8_t Scsi_Sense_Data[];
-extern uint8_t ReadCapacity10_Data[];
-extern uint8_t ReadFormatCapacity_Data [];
-/**
- * @}
- */
-
-
-/** @defgroup USBD_SCSI_Exported_TypesDefinitions
- * @{
- */
-
-typedef struct _SENSE_ITEM {
- char Skey;
- union {
- struct _ASCs {
- char ASC;
- char ASCQ;
- }b;
- unsigned int ASC;
- char *pData;
- } w;
-} SCSI_Sense_TypeDef;
-/**
- * @}
- */
-
-/** @defgroup USBD_SCSI_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_SCSI_Exported_Variables
- * @{
- */
-extern SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH];
-extern uint8_t SCSI_Sense_Head;
-extern uint8_t SCSI_Sense_Tail;
-
-/**
- * @}
- */
-/** @defgroup USBD_SCSI_Exported_FunctionsPrototype
- * @{
- */
-int8_t SCSI_ProcessCmd(USB_OTG_CORE_HANDLE *pdev,
- uint8_t lun,
- uint8_t *cmd);
-
-void SCSI_SenseCode(uint8_t lun,
- uint8_t sKey,
- uint8_t ASC);
-
-/**
- * @}
- */
-
-#endif /* __USBD_MSC_SCSI_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_msc_bot.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief This file provides all the BOT protocol core functions.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc_bot.h"
-#include "usbd_msc_scsi.h"
-#include "usbd_ioreq.h"
-#include "usbd_msc_mem.h"
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup MSC_BOT
- * @brief BOT protocol module
- * @{
- */
-
-/** @defgroup MSC_BOT_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_BOT_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup MSC_BOT_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_BOT_Private_Variables
- * @{
- */
-uint16_t MSC_BOT_DataLen;
-uint8_t MSC_BOT_State;
-uint8_t MSC_BOT_Status;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN uint8_t MSC_BOT_Data[MSC_MEDIA_PACKET] __ALIGN_END ;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN MSC_BOT_CBW_TypeDef MSC_BOT_cbw __ALIGN_END ;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN MSC_BOT_CSW_TypeDef MSC_BOT_csw __ALIGN_END ;
-/**
- * @}
- */
-
-
-/** @defgroup MSC_BOT_Private_FunctionPrototypes
- * @{
- */
-static void MSC_BOT_CBW_Decode (USB_OTG_CORE_HANDLE *pdev);
-
-static void MSC_BOT_SendData (USB_OTG_CORE_HANDLE *pdev,
- uint8_t* pbuf,
- uint16_t len);
-
-static void MSC_BOT_Abort(USB_OTG_CORE_HANDLE *pdev);
-/**
- * @}
- */
-
-
-/** @defgroup MSC_BOT_Private_Functions
- * @{
- */
-
-
-
-/**
-* @brief MSC_BOT_Init
-* Initialize the BOT Process
-* @param pdev: device instance
-* @retval None
-*/
-void MSC_BOT_Init (USB_OTG_CORE_HANDLE *pdev)
-{
- MSC_BOT_State = BOT_IDLE;
- MSC_BOT_Status = BOT_STATE_NORMAL;
- USBD_STORAGE_fops->Init(0);
-
- DCD_EP_Flush(pdev, MSC_OUT_EP);
- DCD_EP_Flush(pdev, MSC_IN_EP);
- /* Prapare EP to Receive First BOT Cmd */
- DCD_EP_PrepareRx (pdev,
- MSC_OUT_EP,
- (uint8_t *)&MSC_BOT_cbw,
- BOT_CBW_LENGTH);
-}
-
-/**
-* @brief MSC_BOT_Reset
-* Reset the BOT Machine
-* @param pdev: device instance
-* @retval None
-*/
-void MSC_BOT_Reset (USB_OTG_CORE_HANDLE *pdev)
-{
- MSC_BOT_State = BOT_IDLE;
- MSC_BOT_Status = BOT_STATE_RECOVERY;
- /* Prapare EP to Receive First BOT Cmd */
- DCD_EP_PrepareRx (pdev,
- MSC_OUT_EP,
- (uint8_t *)&MSC_BOT_cbw,
- BOT_CBW_LENGTH);
-}
-
-/**
-* @brief MSC_BOT_DeInit
-* Uninitialize the BOT Machine
-* @param pdev: device instance
-* @retval None
-*/
-void MSC_BOT_DeInit (USB_OTG_CORE_HANDLE *pdev)
-{
- MSC_BOT_State = BOT_IDLE;
-}
-
-/**
-* @brief MSC_BOT_DataIn
-* Handle BOT IN data stage
-* @param pdev: device instance
-* @param epnum: endpoint index
-* @retval None
-*/
-void MSC_BOT_DataIn (USB_OTG_CORE_HANDLE *pdev,
- uint8_t epnum)
-{
-
- switch (MSC_BOT_State)
- {
- case BOT_DATA_IN:
- if(SCSI_ProcessCmd(pdev,
- MSC_BOT_cbw.bLUN,
- &MSC_BOT_cbw.CB[0]) < 0)
- {
- MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED);
- }
- break;
-
- case BOT_SEND_DATA:
- case BOT_LAST_DATA_IN:
- MSC_BOT_SendCSW (pdev, CSW_CMD_PASSED);
-
- break;
-
- default:
- break;
- }
-}
-/**
-* @brief MSC_BOT_DataOut
-* Proccess MSC OUT data
-* @param pdev: device instance
-* @param epnum: endpoint index
-* @retval None
-*/
-void MSC_BOT_DataOut (USB_OTG_CORE_HANDLE *pdev,
- uint8_t epnum)
-{
- switch (MSC_BOT_State)
- {
- case BOT_IDLE:
- MSC_BOT_CBW_Decode(pdev);
- break;
-
- case BOT_DATA_OUT:
-
- if(SCSI_ProcessCmd(pdev,
- MSC_BOT_cbw.bLUN,
- &MSC_BOT_cbw.CB[0]) < 0)
- {
- MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED);
- }
-
- break;
-
- default:
- break;
- }
-
-}
-
-/**
-* @brief MSC_BOT_CBW_Decode
-* Decode the CBW command and set the BOT state machine accordingtly
-* @param pdev: device instance
-* @retval None
-*/
-static void MSC_BOT_CBW_Decode (USB_OTG_CORE_HANDLE *pdev)
-{
-
- MSC_BOT_csw.dTag = MSC_BOT_cbw.dTag;
- MSC_BOT_csw.dDataResidue = MSC_BOT_cbw.dDataLength;
-
- if ((USBD_GetRxCount (pdev ,MSC_OUT_EP) != BOT_CBW_LENGTH) ||
- (MSC_BOT_cbw.dSignature != BOT_CBW_SIGNATURE)||
- (MSC_BOT_cbw.bLUN > 1) ||
- (MSC_BOT_cbw.bCBLength < 1) ||
- (MSC_BOT_cbw.bCBLength > 16))
- {
-
- SCSI_SenseCode(MSC_BOT_cbw.bLUN,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- MSC_BOT_Status = BOT_STATE_ERROR;
- MSC_BOT_Abort(pdev);
-
- }
- else
- {
- if(SCSI_ProcessCmd(pdev,
- MSC_BOT_cbw.bLUN,
- &MSC_BOT_cbw.CB[0]) < 0)
- {
- MSC_BOT_Abort(pdev);
- }
- /*Burst xfer handled internally*/
- else if ((MSC_BOT_State != BOT_DATA_IN) &&
- (MSC_BOT_State != BOT_DATA_OUT) &&
- (MSC_BOT_State != BOT_LAST_DATA_IN))
- {
- if (MSC_BOT_DataLen > 0)
- {
- MSC_BOT_SendData(pdev,
- MSC_BOT_Data,
- MSC_BOT_DataLen);
- }
- else if (MSC_BOT_DataLen == 0)
- {
- MSC_BOT_SendCSW (pdev,
- CSW_CMD_PASSED);
- }
- }
- }
-}
-
-/**
-* @brief MSC_BOT_SendData
-* Send the requested data
-* @param pdev: device instance
-* @param buf: pointer to data buffer
-* @param len: Data Length
-* @retval None
-*/
-static void MSC_BOT_SendData(USB_OTG_CORE_HANDLE *pdev,
- uint8_t* buf,
- uint16_t len)
-{
-
- len = MIN (MSC_BOT_cbw.dDataLength, len);
- MSC_BOT_csw.dDataResidue -= len;
- MSC_BOT_csw.bStatus = CSW_CMD_PASSED;
- MSC_BOT_State = BOT_SEND_DATA;
-
- DCD_EP_Tx (pdev, MSC_IN_EP, buf, len);
-}
-
-/**
-* @brief MSC_BOT_SendCSW
-* Send the Command Status Wrapper
-* @param pdev: device instance
-* @param status : CSW status
-* @retval None
-*/
-void MSC_BOT_SendCSW (USB_OTG_CORE_HANDLE *pdev,
- uint8_t CSW_Status)
-{
- MSC_BOT_csw.dSignature = BOT_CSW_SIGNATURE;
- MSC_BOT_csw.bStatus = CSW_Status;
- MSC_BOT_State = BOT_IDLE;
-
- DCD_EP_Tx (pdev,
- MSC_IN_EP,
- (uint8_t *)&MSC_BOT_csw,
- BOT_CSW_LENGTH);
-
- /* Prapare EP to Receive next Cmd */
- DCD_EP_PrepareRx (pdev,
- MSC_OUT_EP,
- (uint8_t *)&MSC_BOT_cbw,
- BOT_CBW_LENGTH);
-
-}
-
-/**
-* @brief MSC_BOT_Abort
-* Abort the current transfer
-* @param pdev: device instance
-* @retval status
-*/
-
-static void MSC_BOT_Abort (USB_OTG_CORE_HANDLE *pdev)
-{
-
- if ((MSC_BOT_cbw.bmFlags == 0) &&
- (MSC_BOT_cbw.dDataLength != 0) &&
- (MSC_BOT_Status == BOT_STATE_NORMAL) )
- {
- DCD_EP_Stall(pdev, MSC_OUT_EP );
- }
- DCD_EP_Stall(pdev, MSC_IN_EP);
-
- if(MSC_BOT_Status == BOT_STATE_ERROR)
- {
- DCD_EP_PrepareRx (pdev,
- MSC_OUT_EP,
- (uint8_t *)&MSC_BOT_cbw,
- BOT_CBW_LENGTH);
- }
-}
-
-/**
-* @brief MSC_BOT_CplClrFeature
-* Complete the clear feature request
-* @param pdev: device instance
-* @param epnum: endpoint index
-* @retval None
-*/
-
-void MSC_BOT_CplClrFeature (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
-{
- if(MSC_BOT_Status == BOT_STATE_ERROR )/* Bad CBW Signature */
- {
- DCD_EP_Stall(pdev, MSC_IN_EP);
- MSC_BOT_Status = BOT_STATE_NORMAL;
- }
- else if(((epnum & 0x80) == 0x80) && ( MSC_BOT_Status != BOT_STATE_RECOVERY))
- {
- MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED);
- }
-
-}
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_msc_core.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief This file provides all the MSC core functions.
- *
- * @verbatim
- *
- * ===================================================================
- * MSC Class Description
- * ===================================================================
- * This module manages the MSC class V1.0 following the "Universal
- * Serial Bus Mass Storage Class (MSC) Bulk-Only Transport (BOT) Version 1.0
- * Sep. 31, 1999".
- * This driver implements the following aspects of the specification:
- * - Bulk-Only Transport protocol
- * - Subclass : SCSI transparent command set (ref. SCSI Primary Commands - 3 (SPC-3))
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc_mem.h"
-#include "usbd_msc_core.h"
-#include "usbd_msc_bot.h"
-#include "usbd_req.h"
-
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup MSC_CORE
- * @brief Mass storage core module
- * @{
- */
-
-/** @defgroup MSC_CORE_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_CORE_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup MSC_CORE_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_CORE_Private_FunctionPrototypes
- * @{
- */
-uint8_t USBD_MSC_Init (void *pdev,
- uint8_t cfgidx);
-
-uint8_t USBD_MSC_DeInit (void *pdev,
- uint8_t cfgidx);
-
-uint8_t USBD_MSC_Setup (void *pdev,
- USB_SETUP_REQ *req);
-
-uint8_t USBD_MSC_DataIn (void *pdev,
- uint8_t epnum);
-
-
-uint8_t USBD_MSC_DataOut (void *pdev,
- uint8_t epnum);
-
-uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed,
- uint16_t *length);
-
-#ifdef USB_OTG_HS_CORE
-uint8_t *USBD_MSC_GetOtherCfgDesc (uint8_t speed,
- uint16_t *length);
-#endif
-
-
-uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ];
-
-
-
-
-/**
- * @}
- */
-
-
-/** @defgroup MSC_CORE_Private_Variables
- * @{
- */
-
-
-USBD_Class_cb_TypeDef USBD_MSC_cb =
-{
- USBD_MSC_Init,
- USBD_MSC_DeInit,
- USBD_MSC_Setup,
- NULL, /*EP0_TxSent*/
- NULL, /*EP0_RxReady*/
- USBD_MSC_DataIn,
- USBD_MSC_DataOut,
- NULL, /*SOF */
- NULL,
- NULL,
- USBD_MSC_GetCfgDesc,
-#ifdef USB_OTG_HS_CORE
- USBD_MSC_GetOtherCfgDesc,
-#endif
-};
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-/* USB Mass storage device Configuration Descriptor */
-/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
-__ALIGN_BEGIN uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END =
-{
-
- 0x09, /* bLength: Configuation Descriptor size */
- USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
- USB_MSC_CONFIG_DESC_SIZ,
-
- 0x00,
- 0x01, /* bNumInterfaces: 1 interface */
- 0x01, /* bConfigurationValue: */
- 0x04, /* iConfiguration: */
- 0xC0, /* bmAttributes: */
- 0x32, /* MaxPower 100 mA */
-
- /******************** Mass Storage interface ********************/
- 0x09, /* bLength: Interface Descriptor size */
- 0x04, /* bDescriptorType: */
- 0x00, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints*/
- 0x08, /* bInterfaceClass: MSC Class */
- 0x06, /* bInterfaceSubClass : SCSI transparent*/
- 0x50, /* nInterfaceProtocol */
- 0x05, /* iInterface: */
- /******************** Mass Storage Endpoints ********************/
- 0x07, /*Endpoint descriptor length = 7*/
- 0x05, /*Endpoint descriptor type */
- MSC_IN_EP, /*Endpoint address (IN, address 1) */
- 0x02, /*Bulk endpoint type */
- LOBYTE(MSC_MAX_PACKET),
- HIBYTE(MSC_MAX_PACKET),
- 0x00, /*Polling interval in milliseconds */
-
- 0x07, /*Endpoint descriptor length = 7 */
- 0x05, /*Endpoint descriptor type */
- MSC_OUT_EP, /*Endpoint address (OUT, address 1) */
- 0x02, /*Bulk endpoint type */
- LOBYTE(MSC_MAX_PACKET),
- HIBYTE(MSC_MAX_PACKET),
- 0x00 /*Polling interval in milliseconds*/
-};
-#ifdef USB_OTG_HS_CORE
- #ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
- #endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN uint8_t USBD_MSC_OtherCfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END =
-{
-
- 0x09, /* bLength: Configuation Descriptor size */
- USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION,
- USB_MSC_CONFIG_DESC_SIZ,
-
- 0x00,
- 0x01, /* bNumInterfaces: 1 interface */
- 0x01, /* bConfigurationValue: */
- 0x04, /* iConfiguration: */
- 0xC0, /* bmAttributes: */
- 0x32, /* MaxPower 100 mA */
-
- /******************** Mass Storage interface ********************/
- 0x09, /* bLength: Interface Descriptor size */
- 0x04, /* bDescriptorType: */
- 0x00, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints*/
- 0x08, /* bInterfaceClass: MSC Class */
- 0x06, /* bInterfaceSubClass : SCSI transparent command set*/
- 0x50, /* nInterfaceProtocol */
- 0x05, /* iInterface: */
- /******************** Mass Storage Endpoints ********************/
- 0x07, /*Endpoint descriptor length = 7*/
- 0x05, /*Endpoint descriptor type */
- MSC_IN_EP, /*Endpoint address (IN, address 1) */
- 0x02, /*Bulk endpoint type */
- 0x40,
- 0x00,
- 0x00, /*Polling interval in milliseconds */
-
- 0x07, /*Endpoint descriptor length = 7 */
- 0x05, /*Endpoint descriptor type */
- MSC_OUT_EP, /*Endpoint address (OUT, address 1) */
- 0x02, /*Bulk endpoint type */
- 0x40,
- 0x00,
- 0x00 /*Polling interval in milliseconds*/
-};
-#endif
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN static uint8_t USBD_MSC_MaxLun __ALIGN_END = 0;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN static uint8_t USBD_MSC_AltSet __ALIGN_END = 0;
-
-/**
- * @}
- */
-
-
-/** @defgroup MSC_CORE_Private_Functions
- * @{
- */
-
-/**
-* @brief USBD_MSC_Init
-* Initialize the mass storage configuration
-* @param pdev: device instance
-* @param cfgidx: configuration index
-* @retval status
-*/
-uint8_t USBD_MSC_Init (void *pdev,
- uint8_t cfgidx)
-{
- USBD_MSC_DeInit(pdev , cfgidx );
-
- /* Open EP IN */
- DCD_EP_Open(pdev,
- MSC_IN_EP,
- MSC_EPIN_SIZE,
- USB_OTG_EP_BULK);
-
- /* Open EP OUT */
- DCD_EP_Open(pdev,
- MSC_OUT_EP,
- MSC_EPOUT_SIZE,
- USB_OTG_EP_BULK);
-
- /* Init the BOT layer */
- MSC_BOT_Init(pdev);
-
- return USBD_OK;
-}
-
-/**
-* @brief USBD_MSC_DeInit
-* DeInitilaize the mass storage configuration
-* @param pdev: device instance
-* @param cfgidx: configuration index
-* @retval status
-*/
-uint8_t USBD_MSC_DeInit (void *pdev,
- uint8_t cfgidx)
-{
- /* Close MSC EPs */
- DCD_EP_Close (pdev , MSC_IN_EP);
- DCD_EP_Close (pdev , MSC_OUT_EP);
-
- /* Un Init the BOT layer */
- MSC_BOT_DeInit(pdev);
- return USBD_OK;
-}
-/**
-* @brief USBD_MSC_Setup
-* Handle the MSC specific requests
-* @param pdev: device instance
-* @param req: USB request
-* @retval status
-*/
-uint8_t USBD_MSC_Setup (void *pdev, USB_SETUP_REQ *req)
-{
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
-
- /* Class request */
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest)
- {
- case BOT_GET_MAX_LUN :
-
- if((req->wValue == 0) &&
- (req->wLength == 1) &&
- ((req->bmRequest & 0x80) == 0x80))
- {
- USBD_MSC_MaxLun = USBD_STORAGE_fops->GetMaxLun();
- if(USBD_MSC_MaxLun > 0)
- {
- USBD_CtlSendData (pdev,
- &USBD_MSC_MaxLun,
- 1);
- }
- else
- {
- USBD_CtlError(pdev , req);
- return USBD_FAIL;
-
- }
- }
- else
- {
- USBD_CtlError(pdev , req);
- return USBD_FAIL;
- }
- break;
-
- case BOT_RESET :
- if((req->wValue == 0) &&
- (req->wLength == 0) &&
- ((req->bmRequest & 0x80) != 0x80))
- {
- MSC_BOT_Reset(pdev);
- }
- else
- {
- USBD_CtlError(pdev , req);
- return USBD_FAIL;
- }
- break;
-
- default:
- USBD_CtlError(pdev , req);
- return USBD_FAIL;
- }
- break;
- /* Interface & Endpoint request */
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_INTERFACE :
- USBD_CtlSendData (pdev,
- &USBD_MSC_AltSet,
- 1);
- break;
-
- case USB_REQ_SET_INTERFACE :
- USBD_MSC_AltSet = (uint8_t)(req->wValue);
- break;
-
- case USB_REQ_CLEAR_FEATURE:
-
- /* Flush the FIFO and Clear the stall status */
- DCD_EP_Flush(pdev, (uint8_t)req->wIndex);
-
- /* Re-activate the EP */
- DCD_EP_Close (pdev , (uint8_t)req->wIndex);
- if((((uint8_t)req->wIndex) & 0x80) == 0x80)
- {
- DCD_EP_Open(pdev,
- ((uint8_t)req->wIndex),
- MSC_EPIN_SIZE,
- USB_OTG_EP_BULK);
- }
- else
- {
- DCD_EP_Open(pdev,
- ((uint8_t)req->wIndex),
- MSC_EPOUT_SIZE,
- USB_OTG_EP_BULK);
- }
-
- /* Handle BOT error */
- MSC_BOT_CplClrFeature(pdev, (uint8_t)req->wIndex);
- break;
-
- }
- break;
-
- default:
- break;
- }
- return USBD_OK;
-}
-
-/**
-* @brief USBD_MSC_DataIn
-* handle data IN Stage
-* @param pdev: device instance
-* @param epnum: endpoint index
-* @retval status
-*/
-uint8_t USBD_MSC_DataIn (void *pdev,
- uint8_t epnum)
-{
- MSC_BOT_DataIn(pdev , epnum);
- return USBD_OK;
-}
-
-/**
-* @brief USBD_MSC_DataOut
-* handle data OUT Stage
-* @param pdev: device instance
-* @param epnum: endpoint index
-* @retval status
-*/
-uint8_t USBD_MSC_DataOut (void *pdev,
- uint8_t epnum)
-{
- MSC_BOT_DataOut(pdev , epnum);
- return USBD_OK;
-}
-
-/**
-* @brief USBD_MSC_GetCfgDesc
-* return configuration descriptor
-* @param speed : current device speed
-* @param length : pointer data length
-* @retval pointer to descriptor buffer
-*/
-uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, uint16_t *length)
-{
- *length = sizeof (USBD_MSC_CfgDesc);
- return USBD_MSC_CfgDesc;
-}
-
-/**
-* @brief USBD_MSC_GetOtherCfgDesc
-* return other speed configuration descriptor
-* @param speed : current device speed
-* @param length : pointer data length
-* @retval pointer to descriptor buffer
-*/
-#ifdef USB_OTG_HS_CORE
-uint8_t *USBD_MSC_GetOtherCfgDesc (uint8_t speed,
- uint16_t *length)
-{
- *length = sizeof (USBD_MSC_OtherCfgDesc);
- return USBD_MSC_OtherCfgDesc;
-}
-#endif
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_msc_data.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief This file provides all the vital inquiry pages and sense data.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc_data.h"
-
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup MSC_DATA
- * @brief Mass storage info/data module
- * @{
- */
-
-/** @defgroup MSC_DATA_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_DATA_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_DATA_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_DATA_Private_Variables
- * @{
- */
-
-
-/* USB Mass storage Page 0 Inquiry Data */
-const uint8_t MSC_Page00_Inquiry_Data[] = {//7
- 0x00,
- 0x00,
- 0x00,
- (LENGTH_INQUIRY_PAGE00 - 4),
- 0x00,
- 0x80,
- 0x83
-};
-/* USB Mass storage sense 6 Data */
-const uint8_t MSC_Mode_Sense6_data[] = {
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
-};
-/* USB Mass storage sense 10 Data */
-const uint8_t MSC_Mode_Sense10_data[] = {
- 0x00,
- 0x06,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
-};
-/**
- * @}
- */
-
-
-/** @defgroup MSC_DATA_Private_FunctionPrototypes
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_DATA_Private_Functions
- * @{
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_msc_scsi.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief This file provides all the USBD SCSI layer functions.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc_bot.h"
-#include "usbd_msc_scsi.h"
-#include "usbd_msc_mem.h"
-#include "usbd_msc_data.h"
-
-
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup MSC_SCSI
- * @brief Mass storage SCSI layer module
- * @{
- */
-
-/** @defgroup MSC_SCSI_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_SCSI_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup MSC_SCSI_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_SCSI_Private_Variables
- * @{
- */
-
-SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH];
-uint8_t SCSI_Sense_Head;
-uint8_t SCSI_Sense_Tail;
-
-uint32_t SCSI_blk_size;
-uint32_t SCSI_blk_nbr;
-
-uint32_t SCSI_blk_addr;
-uint32_t SCSI_blk_len;
-
-USB_OTG_CORE_HANDLE *cdev;
-/**
- * @}
- */
-
-
-/** @defgroup MSC_SCSI_Private_FunctionPrototypes
- * @{
- */
-static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params);
-static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params);
-static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params);
-static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params);
-static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params);
-static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params);
-static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params);
-static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params);
-static int8_t SCSI_Write10(uint8_t lun , uint8_t *params);
-static int8_t SCSI_Read10(uint8_t lun , uint8_t *params);
-static int8_t SCSI_Verify10(uint8_t lun, uint8_t *params);
-static int8_t SCSI_CheckAddressRange (uint8_t lun ,
- uint32_t blk_offset ,
- uint16_t blk_nbr);
-static int8_t SCSI_ProcessRead (uint8_t lun);
-
-static int8_t SCSI_ProcessWrite (uint8_t lun);
-/**
- * @}
- */
-
-
-/** @defgroup MSC_SCSI_Private_Functions
- * @{
- */
-
-
-/**
-* @brief SCSI_ProcessCmd
-* Process SCSI commands
-* @param pdev: device instance
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-int8_t SCSI_ProcessCmd(USB_OTG_CORE_HANDLE *pdev,
- uint8_t lun,
- uint8_t *params)
-{
- cdev = pdev;
-
- switch (params[0])
- {
- case SCSI_TEST_UNIT_READY:
- return SCSI_TestUnitReady(lun, params);
-
- case SCSI_REQUEST_SENSE:
- return SCSI_RequestSense (lun, params);
- case SCSI_INQUIRY:
- return SCSI_Inquiry(lun, params);
-
- case SCSI_START_STOP_UNIT:
- return SCSI_StartStopUnit(lun, params);
-
- case SCSI_ALLOW_MEDIUM_REMOVAL:
- return SCSI_StartStopUnit(lun, params);
-
- case SCSI_MODE_SENSE6:
- return SCSI_ModeSense6 (lun, params);
-
- case SCSI_MODE_SENSE10:
- return SCSI_ModeSense10 (lun, params);
-
- case SCSI_READ_FORMAT_CAPACITIES:
- return SCSI_ReadFormatCapacity(lun, params);
-
- case SCSI_READ_CAPACITY10:
- return SCSI_ReadCapacity10(lun, params);
-
- case SCSI_READ10:
- return SCSI_Read10(lun, params);
-
- case SCSI_WRITE10:
- return SCSI_Write10(lun, params);
-
- case SCSI_VERIFY10:
- return SCSI_Verify10(lun, params);
-
- default:
- SCSI_SenseCode(lun,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- return -1;
- }
-}
-
-
-/**
-* @brief SCSI_TestUnitReady
-* Process SCSI Test Unit Ready Command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params)
-{
-
- /* case 9 : Hi > D0 */
- if (MSC_BOT_cbw.dDataLength != 0)
- {
- SCSI_SenseCode(MSC_BOT_cbw.bLUN,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- return -1;
- }
-
- if(USBD_STORAGE_fops->IsReady(lun) !=0 )
- {
- SCSI_SenseCode(lun,
- NOT_READY,
- MEDIUM_NOT_PRESENT);
- return -1;
- }
- MSC_BOT_DataLen = 0;
- return 0;
-}
-
-/**
-* @brief SCSI_Inquiry
-* Process Inquiry command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params)
-{
- uint8_t* pPage;
- uint16_t len;
-
- if (params[1] & 0x01)/*Evpd is set*/
- {
- pPage = (uint8_t *)MSC_Page00_Inquiry_Data;
- len = LENGTH_INQUIRY_PAGE00;
- }
- else
- {
-
- pPage = (uint8_t *)&USBD_STORAGE_fops->pInquiry[lun * USBD_STD_INQUIRY_LENGTH];
- len = pPage[4] + 5;
-
- if (params[4] <= len)
- {
- len = params[4];
- }
- }
- MSC_BOT_DataLen = len;
-
- while (len)
- {
- len--;
- MSC_BOT_Data[len] = pPage[len];
- }
- return 0;
-}
-
-/**
-* @brief SCSI_ReadCapacity10
-* Process Read Capacity 10 command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params)
-{
-
- if(USBD_STORAGE_fops->GetCapacity(lun, &SCSI_blk_nbr, &SCSI_blk_size) != 0)
- {
- SCSI_SenseCode(lun,
- NOT_READY,
- MEDIUM_NOT_PRESENT);
- return -1;
- }
- else
- {
-
- MSC_BOT_Data[0] = (uint8_t)(SCSI_blk_nbr - 1 >> 24);
- MSC_BOT_Data[1] = (uint8_t)(SCSI_blk_nbr - 1 >> 16);
- MSC_BOT_Data[2] = (uint8_t)(SCSI_blk_nbr - 1 >> 8);
- MSC_BOT_Data[3] = (uint8_t)(SCSI_blk_nbr - 1);
-
- MSC_BOT_Data[4] = (uint8_t)(SCSI_blk_size >> 24);
- MSC_BOT_Data[5] = (uint8_t)(SCSI_blk_size >> 16);
- MSC_BOT_Data[6] = (uint8_t)(SCSI_blk_size >> 8);
- MSC_BOT_Data[7] = (uint8_t)(SCSI_blk_size);
-
- MSC_BOT_DataLen = 8;
- return 0;
- }
-}
-/**
-* @brief SCSI_ReadFormatCapacity
-* Process Read Format Capacity command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params)
-{
-
- uint32_t blk_size;
- uint32_t blk_nbr;
- uint16_t i;
-
- for(i=0 ; i < 12 ; i++)
- {
- MSC_BOT_Data[i] = 0;
- }
-
- if(USBD_STORAGE_fops->GetCapacity(lun, &blk_nbr, &blk_size) != 0)
- {
- SCSI_SenseCode(lun,
- NOT_READY,
- MEDIUM_NOT_PRESENT);
- return -1;
- }
- else
- {
- MSC_BOT_Data[3] = 0x08;
- MSC_BOT_Data[4] = (uint8_t)(blk_nbr - 1 >> 24);
- MSC_BOT_Data[5] = (uint8_t)(blk_nbr - 1 >> 16);
- MSC_BOT_Data[6] = (uint8_t)(blk_nbr - 1 >> 8);
- MSC_BOT_Data[7] = (uint8_t)(blk_nbr - 1);
-
- MSC_BOT_Data[8] = 0x02;
- MSC_BOT_Data[9] = (uint8_t)(blk_size >> 16);
- MSC_BOT_Data[10] = (uint8_t)(blk_size >> 8);
- MSC_BOT_Data[11] = (uint8_t)(blk_size);
-
- MSC_BOT_DataLen = 12;
- return 0;
- }
-}
-/**
-* @brief SCSI_ModeSense6
-* Process Mode Sense6 command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params)
-{
-
- uint16_t len = 8 ;
- MSC_BOT_DataLen = len;
-
- while (len)
- {
- len--;
- MSC_BOT_Data[len] = MSC_Mode_Sense6_data[len];
- }
- return 0;
-}
-
-/**
-* @brief SCSI_ModeSense10
-* Process Mode Sense10 command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params)
-{
- uint16_t len = 8;
-
- MSC_BOT_DataLen = len;
-
- while (len)
- {
- len--;
- MSC_BOT_Data[len] = MSC_Mode_Sense10_data[len];
- }
- return 0;
-}
-
-/**
-* @brief SCSI_RequestSense
-* Process Request Sense command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-
-static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params)
-{
- uint8_t i;
-
- for(i=0 ; i < REQUEST_SENSE_DATA_LEN ; i++)
- {
- MSC_BOT_Data[i] = 0;
- }
-
- MSC_BOT_Data[0] = 0x70;
- MSC_BOT_Data[7] = REQUEST_SENSE_DATA_LEN - 6;
-
- if((SCSI_Sense_Head != SCSI_Sense_Tail)) {
-
- MSC_BOT_Data[2] = SCSI_Sense[SCSI_Sense_Head].Skey;
- MSC_BOT_Data[12] = SCSI_Sense[SCSI_Sense_Head].w.b.ASCQ;
- MSC_BOT_Data[13] = SCSI_Sense[SCSI_Sense_Head].w.b.ASC;
- SCSI_Sense_Head++;
-
- if (SCSI_Sense_Head == SENSE_LIST_DEEPTH)
- {
- SCSI_Sense_Head = 0;
- }
- }
- MSC_BOT_DataLen = REQUEST_SENSE_DATA_LEN;
-
- if (params[4] <= REQUEST_SENSE_DATA_LEN)
- {
- MSC_BOT_DataLen = params[4];
- }
- return 0;
-}
-
-/**
-* @brief SCSI_SenseCode
-* Load the last error code in the error list
-* @param lun: Logical unit number
-* @param sKey: Sense Key
-* @param ASC: Additional Sense Key
-* @retval none
-
-*/
-void SCSI_SenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC)
-{
- SCSI_Sense[SCSI_Sense_Tail].Skey = sKey;
- SCSI_Sense[SCSI_Sense_Tail].w.ASC = ASC << 8;
- SCSI_Sense_Tail++;
- if (SCSI_Sense_Tail == SENSE_LIST_DEEPTH)
- {
- SCSI_Sense_Tail = 0;
- }
-}
-/**
-* @brief SCSI_StartStopUnit
-* Process Start Stop Unit command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params)
-{
- MSC_BOT_DataLen = 0;
- return 0;
-}
-
-/**
-* @brief SCSI_Read10
-* Process Read10 command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-static int8_t SCSI_Read10(uint8_t lun , uint8_t *params)
-{
- if(MSC_BOT_State == BOT_IDLE) /* Idle */
- {
-
- /* case 10 : Ho <> Di */
-
- if ((MSC_BOT_cbw.bmFlags & 0x80) != 0x80)
- {
- SCSI_SenseCode(MSC_BOT_cbw.bLUN,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- return -1;
- }
-
- if(USBD_STORAGE_fops->IsReady(lun) !=0 )
- {
- SCSI_SenseCode(lun,
- NOT_READY,
- MEDIUM_NOT_PRESENT);
- return -1;
- }
-
- SCSI_blk_addr = (params[2] << 24) | \
- (params[3] << 16) | \
- (params[4] << 8) | \
- params[5];
-
- SCSI_blk_len = (params[7] << 8) | \
- params[8];
-
-
-
- if( SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0)
- {
- return -1; /* error */
- }
-
- MSC_BOT_State = BOT_DATA_IN;
- SCSI_blk_addr *= SCSI_blk_size;
- SCSI_blk_len *= SCSI_blk_size;
-
- /* cases 4,5 : Hi <> Dn */
- if (MSC_BOT_cbw.dDataLength != SCSI_blk_len)
- {
- SCSI_SenseCode(MSC_BOT_cbw.bLUN,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- return -1;
- }
- }
- MSC_BOT_DataLen = MSC_MEDIA_PACKET;
-
- return SCSI_ProcessRead(lun);
-}
-
-/**
-* @brief SCSI_Write10
-* Process Write10 command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-
-static int8_t SCSI_Write10 (uint8_t lun , uint8_t *params)
-{
- if (MSC_BOT_State == BOT_IDLE) /* Idle */
- {
-
- /* case 8 : Hi <> Do */
-
- if ((MSC_BOT_cbw.bmFlags & 0x80) == 0x80)
- {
- SCSI_SenseCode(MSC_BOT_cbw.bLUN,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- return -1;
- }
-
- /* Check whether Media is ready */
- if(USBD_STORAGE_fops->IsReady(lun) !=0 )
- {
- SCSI_SenseCode(lun,
- NOT_READY,
- MEDIUM_NOT_PRESENT);
- return -1;
- }
-
- /* Check If media is write-protected */
- if(USBD_STORAGE_fops->IsWriteProtected(lun) !=0 )
- {
- SCSI_SenseCode(lun,
- NOT_READY,
- WRITE_PROTECTED);
- return -1;
- }
-
-
- SCSI_blk_addr = (params[2] << 24) | \
- (params[3] << 16) | \
- (params[4] << 8) | \
- params[5];
- SCSI_blk_len = (params[7] << 8) | \
- params[8];
-
- /* check if LBA address is in the right range */
- if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0)
- {
- return -1; /* error */
- }
-
- SCSI_blk_addr *= SCSI_blk_size;
- SCSI_blk_len *= SCSI_blk_size;
-
- /* cases 3,11,13 : Hn,Ho <> D0 */
- if (MSC_BOT_cbw.dDataLength != SCSI_blk_len)
- {
- SCSI_SenseCode(MSC_BOT_cbw.bLUN,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- return -1;
- }
-
- /* Prepare EP to receive first data packet */
- MSC_BOT_State = BOT_DATA_OUT;
- DCD_EP_PrepareRx (cdev,
- MSC_OUT_EP,
- MSC_BOT_Data,
- MIN (SCSI_blk_len, MSC_MEDIA_PACKET));
- }
- else /* Write Process ongoing */
- {
- return SCSI_ProcessWrite(lun);
- }
- return 0;
-}
-
-
-/**
-* @brief SCSI_Verify10
-* Process Verify10 command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-
-static int8_t SCSI_Verify10(uint8_t lun , uint8_t *params){
- if ((params[1]& 0x02) == 0x02)
- {
- SCSI_SenseCode (lun, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND);
- return -1; /* Error, Verify Mode Not supported*/
- }
-
- if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0)
- {
- return -1; /* error */
- }
- MSC_BOT_DataLen = 0;
- return 0;
-}
-
-/**
-* @brief SCSI_CheckAddressRange
-* Check address range
-* @param lun: Logical unit number
-* @param blk_offset: first block address
-* @param blk_nbr: number of block to be processed
-* @retval status
-*/
-static int8_t SCSI_CheckAddressRange (uint8_t lun , uint32_t blk_offset , uint16_t blk_nbr)
-{
-
- if ((blk_offset + blk_nbr) > SCSI_blk_nbr )
- {
- SCSI_SenseCode(lun, ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE);
- return -1;
- }
- return 0;
-}
-
-/**
-* @brief SCSI_ProcessRead
-* Handle Read Process
-* @param lun: Logical unit number
-* @retval status
-*/
-static int8_t SCSI_ProcessRead (uint8_t lun)
-{
- uint32_t len;
-
- len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET);
-
- if( USBD_STORAGE_fops->Read(lun ,
- MSC_BOT_Data,
- SCSI_blk_addr / SCSI_blk_size,
- len / SCSI_blk_size) < 0)
- {
-
- SCSI_SenseCode(lun, HARDWARE_ERROR, UNRECOVERED_READ_ERROR);
- return -1;
- }
-
-
- DCD_EP_Tx (cdev,
- MSC_IN_EP,
- MSC_BOT_Data,
- len);
-
-
- SCSI_blk_addr += len;
- SCSI_blk_len -= len;
-
- /* case 6 : Hi = Di */
- MSC_BOT_csw.dDataResidue -= len;
-
- if (SCSI_blk_len == 0)
- {
- MSC_BOT_State = BOT_LAST_DATA_IN;
- }
- return 0;
-}
-
-/**
-* @brief SCSI_ProcessWrite
-* Handle Write Process
-* @param lun: Logical unit number
-* @retval status
-*/
-
-static int8_t SCSI_ProcessWrite (uint8_t lun)
-{
- uint32_t len;
-
- len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET);
-
- if(USBD_STORAGE_fops->Write(lun ,
- MSC_BOT_Data,
- SCSI_blk_addr / SCSI_blk_size,
- len / SCSI_blk_size) < 0)
- {
- SCSI_SenseCode(lun, HARDWARE_ERROR, WRITE_FAULT);
- return -1;
- }
-
-
- SCSI_blk_addr += len;
- SCSI_blk_len -= len;
-
- /* case 12 : Ho = Do */
- MSC_BOT_csw.dDataResidue -= len;
-
- if (SCSI_blk_len == 0)
- {
- MSC_BOT_SendCSW (cdev, CSW_CMD_PASSED);
- }
- else
- {
- /* Prapare EP to Receive next packet */
- DCD_EP_PrepareRx (cdev,
- MSC_OUT_EP,
- MSC_BOT_Data,
- MIN (SCSI_blk_len, MSC_MEDIA_PACKET));
- }
-
- return 0;
-}
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_storage_template.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief Memory management layer
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc_mem.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Extern function prototypes ------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-#define STORAGE_LUN_NBR 1
-
-int8_t STORAGE_Init (uint8_t lun);
-
-int8_t STORAGE_GetCapacity (uint8_t lun,
- uint32_t *block_num,
- uint16_t *block_size);
-
-int8_t STORAGE_IsReady (uint8_t lun);
-
-int8_t STORAGE_IsWriteProtected (uint8_t lun);
-
-int8_t STORAGE_Read (uint8_t lun,
- uint8_t *buf,
- uint32_t blk_addr,
- uint16_t blk_len);
-
-int8_t STORAGE_Write (uint8_t lun,
- uint8_t *buf,
- uint32_t blk_addr,
- uint16_t blk_len);
-
-int8_t STORAGE_GetMaxLun (void);
-
-/* USB Mass storage Standard Inquiry Data */
-const int8_t STORAGE_Inquirydata[] = {//36
-
- /* LUN 0 */
- 0x00,
- 0x80,
- 0x02,
- 0x02,
- (USBD_STD_INQUIRY_LENGTH - 5),
- 0x00,
- 0x00,
- 0x00,
- 'S', 'T', 'M', ' ', ' ', ' ', ' ', ' ', /* Manufacturer : 8 bytes */
- 'P', 'r', 'o', 'd', 'u', 't', ' ', ' ', /* Product : 16 Bytes */
- ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ',
- '0', '.', '0' ,'1', /* Version : 4 Bytes */
-};
-
-USBD_STORAGE_cb_TypeDef USBD_MICRO_SDIO_fops =
-{
- STORAGE_Init,
- STORAGE_GetCapacity,
- STORAGE_IsReady,
- STORAGE_IsWriteProtected,
- STORAGE_Read,
- STORAGE_Write,
- STORAGE_GetMaxLun,
- STORAGE_Inquirydata,
-
-};
-
-USBD_STORAGE_cb_TypeDef *USBD_STORAGE_fops = &USBD_MICRO_SDIO_fops;
-/*******************************************************************************
-* Function Name : Read_Memory
-* Description : Handle the Read operation from the microSD card.
-* Input : None.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-int8_t STORAGE_Init (uint8_t lun)
-{
- return (0);
-}
-
-/*******************************************************************************
-* Function Name : Read_Memory
-* Description : Handle the Read operation from the STORAGE card.
-* Input : None.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-int8_t STORAGE_GetCapacity (uint8_t lun, uint32_t *block_num, uint16_t *block_size)
-{
- return (0);
-}
-
-/*******************************************************************************
-* Function Name : Read_Memory
-* Description : Handle the Read operation from the STORAGE card.
-* Input : None.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-int8_t STORAGE_IsReady (uint8_t lun)
-{
- return (0);
-}
-
-/*******************************************************************************
-* Function Name : Read_Memory
-* Description : Handle the Read operation from the STORAGE card.
-* Input : None.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-int8_t STORAGE_IsWriteProtected (uint8_t lun)
-{
- return 0;
-}
-
-/*******************************************************************************
-* Function Name : Read_Memory
-* Description : Handle the Read operation from the STORAGE card.
-* Input : None.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-int8_t STORAGE_Read (uint8_t lun,
- uint8_t *buf,
- uint32_t blk_addr,
- uint16_t blk_len)
-{
- return 0;
-}
-/*******************************************************************************
-* Function Name : Write_Memory
-* Description : Handle the Write operation to the STORAGE card.
-* Input : None.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-int8_t STORAGE_Write (uint8_t lun,
- uint8_t *buf,
- uint32_t blk_addr,
- uint16_t blk_len)
-{
- return (0);
-}
-/*******************************************************************************
-* Function Name : Write_Memory
-* Description : Handle the Write operation to the STORAGE card.
-* Input : None.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-int8_t STORAGE_GetMaxLun (void)
-{
- return (STORAGE_LUN_NBR - 1);
-}
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_conf_template.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief usb device configuration template file
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_CONF__H__
-#define __USBD_CONF__H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-
-
-/** @defgroup USB_CONF_Exported_Defines
- * @{
- */
-#define USE_USB_OTG_HS
-
-#define USBD_CFG_MAX_NUM 1
-#define USB_MAX_STR_DESC_SIZ 64
-#define USBD_EP0_MAX_PACKET_SIZE 64
-
-/**
- * @}
- */
-
-
-/** @defgroup USB_CONF_Exported_Types
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_CONF_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_CONF_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_CONF_Exported_FunctionsPrototype
- * @{
- */
-/**
- * @}
- */
-
-
-#endif //__USBD_CONF__H__
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_core.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief Header file for usbd_core.c
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_CORE_H
-#define __USBD_CORE_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_dcd.h"
-#include "usbd_def.h"
-#include "usbd_conf.h"
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USBD_CORE
- * @brief This file is the Header file for usbd_core.c file
- * @{
- */
-
-
-/** @defgroup USBD_CORE_Exported_Defines
- * @{
- */
-
-typedef enum {
- USBD_OK = 0,
- USBD_BUSY,
- USBD_FAIL,
-}USBD_Status;
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CORE_Exported_TypesDefinitions
- * @{
- */
-
-
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_CORE_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_CORE_Exported_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_CORE_Exported_FunctionsPrototype
- * @{
- */
-void USBD_Init(USB_OTG_CORE_HANDLE *pdev,
- USB_OTG_CORE_ID_TypeDef coreID,
- USBD_DEVICE *pDevice,
- USBD_Class_cb_TypeDef *class_cb,
- USBD_Usr_cb_TypeDef *usr_cb);
-
-USBD_Status USBD_DeInit(USB_OTG_CORE_HANDLE *pdev);
-
-USBD_Status USBD_ClrCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx);
-
-USBD_Status USBD_SetCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx);
-
-/**
- * @}
- */
-
-#endif /* __USBD_CORE_H */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
-
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_def.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief general defines for the usb device library
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-
-#ifndef __USBD_DEF_H
-#define __USBD_DEF_H
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_conf.h"
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USB_DEF
- * @brief general defines for the usb device library file
- * @{
- */
-
-/** @defgroup USB_DEF_Exported_Defines
- * @{
- */
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-#define USB_LEN_DEV_QUALIFIER_DESC 0x0A
-#define USB_LEN_DEV_DESC 0x12
-#define USB_LEN_CFG_DESC 0x09
-#define USB_LEN_IF_DESC 0x09
-#define USB_LEN_EP_DESC 0x07
-#define USB_LEN_OTG_DESC 0x03
-
-#define USBD_IDX_LANGID_STR 0x00
-#define USBD_IDX_MFC_STR 0x01
-#define USBD_IDX_PRODUCT_STR 0x02
-#define USBD_IDX_SERIAL_STR 0x03
-#define USBD_IDX_CONFIG_STR 0x04
-#define USBD_IDX_INTERFACE_STR 0x05
-
-#define USB_REQ_TYPE_STANDARD 0x00
-#define USB_REQ_TYPE_CLASS 0x20
-#define USB_REQ_TYPE_VENDOR 0x40
-#define USB_REQ_TYPE_MASK 0x60
-
-#define USB_REQ_RECIPIENT_DEVICE 0x00
-#define USB_REQ_RECIPIENT_INTERFACE 0x01
-#define USB_REQ_RECIPIENT_ENDPOINT 0x02
-#define USB_REQ_RECIPIENT_MASK 0x03
-
-#define USB_REQ_GET_STATUS 0x00
-#define USB_REQ_CLEAR_FEATURE 0x01
-#define USB_REQ_SET_FEATURE 0x03
-#define USB_REQ_SET_ADDRESS 0x05
-#define USB_REQ_GET_DESCRIPTOR 0x06
-#define USB_REQ_SET_DESCRIPTOR 0x07
-#define USB_REQ_GET_CONFIGURATION 0x08
-#define USB_REQ_SET_CONFIGURATION 0x09
-#define USB_REQ_GET_INTERFACE 0x0A
-#define USB_REQ_SET_INTERFACE 0x0B
-#define USB_REQ_SYNCH_FRAME 0x0C
-
-#define USB_DESC_TYPE_DEVICE 1
-#define USB_DESC_TYPE_CONFIGURATION 2
-#define USB_DESC_TYPE_STRING 3
-#define USB_DESC_TYPE_INTERFACE 4
-#define USB_DESC_TYPE_ENDPOINT 5
-#define USB_DESC_TYPE_DEVICE_QUALIFIER 6
-#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7
-
-
-#define USB_CONFIG_REMOTE_WAKEUP 2
-#define USB_CONFIG_SELF_POWERED 1
-
-#define USB_FEATURE_EP_HALT 0
-#define USB_FEATURE_REMOTE_WAKEUP 1
-#define USB_FEATURE_TEST_MODE 2
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_DEF_Exported_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_DEF_Exported_Macros
- * @{
- */
-#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \
- (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8))
-
-#define LOBYTE(x) ((uint8_t)(x & 0x00FF))
-#define HIBYTE(x) ((uint8_t)((x & 0xFF00) >>8))
-/**
- * @}
- */
-
-/** @defgroup USBD_DEF_Exported_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_DEF_Exported_FunctionsPrototype
- * @{
- */
-
-/**
- * @}
- */
-
-#endif /* __USBD_DEF_H */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_ioreq.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief header file for the usbd_ioreq.c file
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-
-#ifndef __USBD_IOREQ_H_
-#define __USBD_IOREQ_H_
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_def.h"
-#include "usbd_core.h"
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USBD_IOREQ
- * @brief header file for the usbd_ioreq.c file
- * @{
- */
-
-/** @defgroup USBD_IOREQ_Exported_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_IOREQ_Exported_Types
- * @{
- */
-
-
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_IOREQ_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_IOREQ_Exported_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype
- * @{
- */
-
-USBD_Status USBD_CtlSendData (USB_OTG_CORE_HANDLE *pdev,
- uint8_t *buf,
- uint16_t len);
-
-USBD_Status USBD_CtlContinueSendData (USB_OTG_CORE_HANDLE *pdev,
- uint8_t *pbuf,
- uint16_t len);
-
-USBD_Status USBD_CtlPrepareRx (USB_OTG_CORE_HANDLE *pdev,
- uint8_t *pbuf,
- uint16_t len);
-
-USBD_Status USBD_CtlContinueRx (USB_OTG_CORE_HANDLE *pdev,
- uint8_t *pbuf,
- uint16_t len);
-
-USBD_Status USBD_CtlSendStatus (USB_OTG_CORE_HANDLE *pdev);
-
-USBD_Status USBD_CtlReceiveStatus (USB_OTG_CORE_HANDLE *pdev);
-
-uint16_t USBD_GetRxCount (USB_OTG_CORE_HANDLE *pdev ,
- uint8_t epnum);
-
-/**
- * @}
- */
-
-#endif /* __USBD_IOREQ_H_ */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_req.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief header file for the usbd_req.c file
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-
-#ifndef __USB_REQUEST_H_
-#define __USB_REQUEST_H_
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_def.h"
-#include "usbd_core.h"
-#include "usbd_conf.h"
-
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USBD_REQ
- * @brief header file for the usbd_ioreq.c file
- * @{
- */
-
-/** @defgroup USBD_REQ_Exported_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_REQ_Exported_Types
- * @{
- */
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_REQ_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBD_REQ_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBD_REQ_Exported_FunctionsPrototype
- * @{
- */
-
-USBD_Status USBD_StdDevReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req);
-USBD_Status USBD_StdItfReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req);
-USBD_Status USBD_StdEPReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req);
-void USBD_ParseSetupRequest( USB_OTG_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req);
-
-void USBD_CtlError( USB_OTG_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req);
-
-void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len);
-/**
- * @}
- */
-
-#endif /* __USB_REQUEST_H_ */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_usr.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief Header file for usbd_usr.c
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_USR_H__
-#define __USBD_USR_H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_core.h"
-
-
-/** @addtogroup USBD_USER
- * @{
- */
-
-/** @addtogroup USBD_MSC_DEMO_USER_CALLBACKS
- * @{
- */
-
-/** @defgroup USBD_USR
- * @brief This file is the Header file for usbd_usr.c
- * @{
- */
-
-
-/** @defgroup USBD_USR_Exported_Types
- * @{
- */
-
-extern USBD_Usr_cb_TypeDef USR_cb;
-extern USBD_Usr_cb_TypeDef USR_FS_cb;
-extern USBD_Usr_cb_TypeDef USR_HS_cb;
-
-
-
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_USR_Exported_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_USR_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBD_USR_Exported_Variables
- * @{
- */
-
-void USBD_USR_Init(void);
-void USBD_USR_DeviceReset (uint8_t speed);
-void USBD_USR_DeviceConfigured (void);
-void USBD_USR_DeviceSuspended(void);
-void USBD_USR_DeviceResumed(void);
-
-void USBD_USR_DeviceConnected(void);
-void USBD_USR_DeviceDisconnected(void);
-
-void USBD_USR_FS_Init(void);
-void USBD_USR_FS_DeviceReset (uint8_t speed);
-void USBD_USR_FS_DeviceConfigured (void);
-void USBD_USR_FS_DeviceSuspended(void);
-void USBD_USR_FS_DeviceResumed(void);
-
-void USBD_USR_FS_DeviceConnected(void);
-void USBD_USR_FS_DeviceDisconnected(void);
-
-void USBD_USR_HS_Init(void);
-void USBD_USR_HS_DeviceReset (uint8_t speed);
-void USBD_USR_HS_DeviceConfigured (void);
-void USBD_USR_HS_DeviceSuspended(void);
-void USBD_USR_HS_DeviceResumed(void);
-
-void USBD_USR_HS_DeviceConnected(void);
-void USBD_USR_HS_DeviceDisconnected(void);
-
-/**
- * @}
- */
-
-/** @defgroup USBD_USR_Exported_FunctionsPrototype
- * @{
- */
-/**
- * @}
- */
-
-#endif /*__USBD_USR_H__*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
-
-
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_core.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief This file provides all the USBD core functions.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_core.h"
-#include "usbd_req.h"
-#include "usbd_ioreq.h"
-#include "usb_dcd_int.h"
-#include "usb_bsp.h"
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
-* @{
-*/
-
-
-/** @defgroup USBD_CORE
-* @brief usbd core module
-* @{
-*/
-
-/** @defgroup USBD_CORE_Private_TypesDefinitions
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USBD_CORE_Private_Defines
-* @{
-*/
-
-/**
-* @}
-*/
-
-
-/** @defgroup USBD_CORE_Private_Macros
-* @{
-*/
-/**
-* @}
-*/
-
-
-
-
-/** @defgroup USBD_CORE_Private_FunctionPrototypes
-* @{
-*/
-static uint8_t USBD_SetupStage(USB_OTG_CORE_HANDLE *pdev);
-static uint8_t USBD_DataOutStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum);
-static uint8_t USBD_DataInStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum);
-static uint8_t USBD_SOF(USB_OTG_CORE_HANDLE *pdev);
-static uint8_t USBD_Reset(USB_OTG_CORE_HANDLE *pdev);
-static uint8_t USBD_Suspend(USB_OTG_CORE_HANDLE *pdev);
-static uint8_t USBD_Resume(USB_OTG_CORE_HANDLE *pdev);
-#ifdef VBUS_SENSING_ENABLED
-static uint8_t USBD_DevConnected(USB_OTG_CORE_HANDLE *pdev);
-static uint8_t USBD_DevDisconnected(USB_OTG_CORE_HANDLE *pdev);
-#endif
-static uint8_t USBD_IsoINIncomplete(USB_OTG_CORE_HANDLE *pdev);
-static uint8_t USBD_IsoOUTIncomplete(USB_OTG_CORE_HANDLE *pdev);
-/**
-* @}
-*/
-
-/** @defgroup USBD_CORE_Private_Variables
-* @{
-*/
-
-
-
-USBD_DCD_INT_cb_TypeDef USBD_DCD_INT_cb =
-{
- USBD_DataOutStage,
- USBD_DataInStage,
- USBD_SetupStage,
- USBD_SOF,
- USBD_Reset,
- USBD_Suspend,
- USBD_Resume,
- USBD_IsoINIncomplete,
- USBD_IsoOUTIncomplete,
-#ifdef VBUS_SENSING_ENABLED
-USBD_DevConnected,
-USBD_DevDisconnected,
-#endif
-};
-
-USBD_DCD_INT_cb_TypeDef *USBD_DCD_INT_fops = &USBD_DCD_INT_cb;
-/**
-* @}
-*/
-
-/** @defgroup USBD_CORE_Private_Functions
-* @{
-*/
-
-/**
-* @brief USBD_Init
-* Initailizes the device stack and load the class driver
-* @param pdev: device instance
-* @param core_address: USB OTG core ID
-* @param class_cb: Class callback structure address
-* @param usr_cb: User callback structure address
-* @retval None
-*/
-void USBD_Init(USB_OTG_CORE_HANDLE *pdev,
- USB_OTG_CORE_ID_TypeDef coreID,
- USBD_DEVICE *pDevice,
- USBD_Class_cb_TypeDef *class_cb,
- USBD_Usr_cb_TypeDef *usr_cb)
-{
- /* Hardware Init */
- USB_OTG_BSP_Init(pdev);
-
- USBD_DeInit(pdev);
-
- /*Register class and user callbacks */
- pdev->dev.class_cb = class_cb;
- pdev->dev.usr_cb = usr_cb;
- pdev->dev.usr_device = pDevice;
-
- /* set USB OTG core params */
- DCD_Init(pdev , coreID);
-
- /* Upon Init call usr callback */
- pdev->dev.usr_cb->Init();
-
- /* Enable Interrupts */
- USB_OTG_BSP_EnableInterrupt(pdev);
-}
-
-/**
-* @brief USBD_DeInit
-* Re-Initialize th deviuce library
-* @param pdev: device instance
-* @retval status: status
-*/
-USBD_Status USBD_DeInit(USB_OTG_CORE_HANDLE *pdev)
-{
- /* Software Init */
-
- return USBD_OK;
-}
-
-/**
-* @brief USBD_SetupStage
-* Handle the setup stage
-* @param pdev: device instance
-* @retval status
-*/
-static uint8_t USBD_SetupStage(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_SETUP_REQ req;
-
- USBD_ParseSetupRequest(pdev , &req);
-
- switch (req.bmRequest & 0x1F)
- {
- case USB_REQ_RECIPIENT_DEVICE:
- USBD_StdDevReq (pdev, &req);
- break;
-
- case USB_REQ_RECIPIENT_INTERFACE:
- USBD_StdItfReq(pdev, &req);
- break;
-
- case USB_REQ_RECIPIENT_ENDPOINT:
- USBD_StdEPReq(pdev, &req);
- break;
-
- default:
- DCD_EP_Stall(pdev , req.bmRequest & 0x80);
- break;
- }
- return USBD_OK;
-}
-
-/**
-* @brief USBD_DataOutStage
-* Handle data out stage
-* @param pdev: device instance
-* @param epnum: endpoint index
-* @retval status
-*/
-static uint8_t USBD_DataOutStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum)
-{
- USB_OTG_EP *ep;
-
- if(epnum == 0)
- {
- ep = &pdev->dev.out_ep[0];
- if ( pdev->dev.device_state == USB_OTG_EP0_DATA_OUT)
- {
- if(ep->rem_data_len > ep->maxpacket)
- {
- ep->rem_data_len -= ep->maxpacket;
-
- if(pdev->cfg.dma_enable == 1)
- {
- /* in slave mode this, is handled by the RxSTSQLvl ISR */
- ep->xfer_buff += ep->maxpacket;
- }
- USBD_CtlContinueRx (pdev,
- ep->xfer_buff,
- MIN(ep->rem_data_len ,ep->maxpacket));
- }
- else
- {
- if((pdev->dev.class_cb->EP0_RxReady != NULL)&&
- (pdev->dev.device_status == USB_OTG_CONFIGURED))
- {
- pdev->dev.class_cb->EP0_RxReady(pdev);
- }
- USBD_CtlSendStatus(pdev);
- }
- }
- }
- else if((pdev->dev.class_cb->DataOut != NULL)&&
- (pdev->dev.device_status == USB_OTG_CONFIGURED))
- {
- pdev->dev.class_cb->DataOut(pdev, epnum);
- }
- return USBD_OK;
-}
-
-/**
-* @brief USBD_DataInStage
-* Handle data in stage
-* @param pdev: device instance
-* @param epnum: endpoint index
-* @retval status
-*/
-static uint8_t USBD_DataInStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum)
-{
- USB_OTG_EP *ep;
-
- if(epnum == 0)
- {
- ep = &pdev->dev.in_ep[0];
- if ( pdev->dev.device_state == USB_OTG_EP0_DATA_IN)
- {
- if(ep->rem_data_len > ep->maxpacket)
- {
- ep->rem_data_len -= ep->maxpacket;
- if(pdev->cfg.dma_enable == 1)
- {
- /* in slave mode this, is handled by the TxFifoEmpty ISR */
- ep->xfer_buff += ep->maxpacket;
- }
- USBD_CtlContinueSendData (pdev,
- ep->xfer_buff,
- ep->rem_data_len);
- }
- else
- { /* last packet is MPS multiple, so send ZLP packet */
- if((ep->total_data_len % ep->maxpacket == 0) &&
- (ep->total_data_len >= ep->maxpacket) &&
- (ep->total_data_len < ep->ctl_data_len ))
- {
-
- USBD_CtlContinueSendData(pdev , NULL, 0);
- ep->ctl_data_len = 0;
- }
- else
- {
- if((pdev->dev.class_cb->EP0_TxSent != NULL)&&
- (pdev->dev.device_status == USB_OTG_CONFIGURED))
- {
- pdev->dev.class_cb->EP0_TxSent(pdev);
- }
- USBD_CtlReceiveStatus(pdev);
- }
- }
- }
- }
- else if((pdev->dev.class_cb->DataIn != NULL)&&
- (pdev->dev.device_status == USB_OTG_CONFIGURED))
- {
- pdev->dev.class_cb->DataIn(pdev, epnum);
- }
- return USBD_OK;
-}
-
-/**
-* @brief USBD_Reset
-* Handle Reset event
-* @param pdev: device instance
-* @retval status
-*/
-
-static uint8_t USBD_Reset(USB_OTG_CORE_HANDLE *pdev)
-{
- /* Open EP0 OUT */
- DCD_EP_Open(pdev,
- 0x00,
- USB_OTG_MAX_EP0_SIZE,
- EP_TYPE_CTRL);
-
- /* Open EP0 IN */
- DCD_EP_Open(pdev,
- 0x80,
- USB_OTG_MAX_EP0_SIZE,
- EP_TYPE_CTRL);
-
- /* Upon Reset call usr call back */
- pdev->dev.device_status = USB_OTG_DEFAULT;
- pdev->dev.usr_cb->DeviceReset(pdev->cfg.speed);
-
- return USBD_OK;
-}
-
-/**
-* @brief USBD_Resume
-* Handle Resume event
-* @param pdev: device instance
-* @retval status
-*/
-
-static uint8_t USBD_Resume(USB_OTG_CORE_HANDLE *pdev)
-{
- /* Upon Resume call usr call back */
- pdev->dev.usr_cb->DeviceResumed();
- pdev->dev.device_status = USB_OTG_CONFIGURED;
- return USBD_OK;
-}
-
-
-/**
-* @brief USBD_Suspend
-* Handle Suspend event
-* @param pdev: device instance
-* @retval status
-*/
-
-static uint8_t USBD_Suspend(USB_OTG_CORE_HANDLE *pdev)
-{
-
- pdev->dev.device_status = USB_OTG_SUSPENDED;
- /* Upon Resume call usr call back */
- pdev->dev.usr_cb->DeviceSuspended();
- return USBD_OK;
-}
-
-
-/**
-* @brief USBD_SOF
-* Handle SOF event
-* @param pdev: device instance
-* @retval status
-*/
-
-static uint8_t USBD_SOF(USB_OTG_CORE_HANDLE *pdev)
-{
- if(pdev->dev.class_cb->SOF)
- {
- pdev->dev.class_cb->SOF(pdev);
- }
- return USBD_OK;
-}
-/**
-* @brief USBD_SetCfg
-* Configure device and start the interface
-* @param pdev: device instance
-* @param cfgidx: configuration index
-* @retval status
-*/
-
-USBD_Status USBD_SetCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx)
-{
- pdev->dev.class_cb->Init(pdev, cfgidx);
-
- /* Upon set config call usr call back */
- pdev->dev.usr_cb->DeviceConfigured();
- return USBD_OK;
-}
-
-/**
-* @brief USBD_ClrCfg
-* Clear current configuration
-* @param pdev: device instance
-* @param cfgidx: configuration index
-* @retval status: USBD_Status
-*/
-USBD_Status USBD_ClrCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx)
-{
- pdev->dev.class_cb->DeInit(pdev, cfgidx);
- return USBD_OK;
-}
-
-/**
-* @brief USBD_IsoINIncomplete
-* Handle iso in incomplete event
-* @param pdev: device instance
-* @retval status
-*/
-static uint8_t USBD_IsoINIncomplete(USB_OTG_CORE_HANDLE *pdev)
-{
- pdev->dev.class_cb->IsoINIncomplete(pdev);
- return USBD_OK;
-}
-
-/**
-* @brief USBD_IsoOUTIncomplete
-* Handle iso out incomplete event
-* @param pdev: device instance
-* @retval status
-*/
-static uint8_t USBD_IsoOUTIncomplete(USB_OTG_CORE_HANDLE *pdev)
-{
- pdev->dev.class_cb->IsoOUTIncomplete(pdev);
- return USBD_OK;
-}
-
-#ifdef VBUS_SENSING_ENABLED
-/**
-* @brief USBD_DevConnected
-* Handle device connection event
-* @param pdev: device instance
-* @retval status
-*/
-static uint8_t USBD_DevConnected(USB_OTG_CORE_HANDLE *pdev)
-{
- pdev->dev.usr_cb->DeviceConnected();
- return USBD_OK;
-}
-
-/**
-* @brief USBD_DevDisconnected
-* Handle device disconnection event
-* @param pdev: device instance
-* @retval status
-*/
-static uint8_t USBD_DevDisconnected(USB_OTG_CORE_HANDLE *pdev)
-{
- pdev->dev.usr_cb->DeviceDisconnected();
- pdev->dev.class_cb->DeInit(pdev, 0);
- return USBD_OK;
-}
-#endif
-/**
-* @}
-*/
-
-
-/**
-* @}
-*/
-
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_ioreq.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief This file provides the IO requests APIs for control endpoints.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_ioreq.h"
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup USBD_IOREQ
- * @brief control I/O requests module
- * @{
- */
-
-/** @defgroup USBD_IOREQ_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_IOREQ_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_IOREQ_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_IOREQ_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_IOREQ_Private_FunctionPrototypes
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_IOREQ_Private_Functions
- * @{
- */
-
-/**
-* @brief USBD_CtlSendData
-* send data on the ctl pipe
-* @param pdev: device instance
-* @param buff: pointer to data buffer
-* @param len: length of data to be sent
-* @retval status
-*/
-USBD_Status USBD_CtlSendData (USB_OTG_CORE_HANDLE *pdev,
- uint8_t *pbuf,
- uint16_t len)
-{
- USBD_Status ret = USBD_OK;
-
- pdev->dev.in_ep[0].total_data_len = len;
- pdev->dev.in_ep[0].rem_data_len = len;
- pdev->dev.device_state = USB_OTG_EP0_DATA_IN;
-
- DCD_EP_Tx (pdev, 0, pbuf, len);
-
- return ret;
-}
-
-/**
-* @brief USBD_CtlContinueSendData
-* continue sending data on the ctl pipe
-* @param pdev: device instance
-* @param buff: pointer to data buffer
-* @param len: length of data to be sent
-* @retval status
-*/
-USBD_Status USBD_CtlContinueSendData (USB_OTG_CORE_HANDLE *pdev,
- uint8_t *pbuf,
- uint16_t len)
-{
- USBD_Status ret = USBD_OK;
-
- DCD_EP_Tx (pdev, 0, pbuf, len);
-
-
- return ret;
-}
-
-/**
-* @brief USBD_CtlPrepareRx
-* receive data on the ctl pipe
-* @param pdev: USB OTG device instance
-* @param buff: pointer to data buffer
-* @param len: length of data to be received
-* @retval status
-*/
-USBD_Status USBD_CtlPrepareRx (USB_OTG_CORE_HANDLE *pdev,
- uint8_t *pbuf,
- uint16_t len)
-{
- USBD_Status ret = USBD_OK;
-
- pdev->dev.out_ep[0].total_data_len = len;
- pdev->dev.out_ep[0].rem_data_len = len;
- pdev->dev.device_state = USB_OTG_EP0_DATA_OUT;
-
- DCD_EP_PrepareRx (pdev,
- 0,
- pbuf,
- len);
-
-
- return ret;
-}
-
-/**
-* @brief USBD_CtlContinueRx
-* continue receive data on the ctl pipe
-* @param pdev: USB OTG device instance
-* @param buff: pointer to data buffer
-* @param len: length of data to be received
-* @retval status
-*/
-USBD_Status USBD_CtlContinueRx (USB_OTG_CORE_HANDLE *pdev,
- uint8_t *pbuf,
- uint16_t len)
-{
- USBD_Status ret = USBD_OK;
-
- DCD_EP_PrepareRx (pdev,
- 0,
- pbuf,
- len);
- return ret;
-}
-/**
-* @brief USBD_CtlSendStatus
-* send zero lzngth packet on the ctl pipe
-* @param pdev: USB OTG device instance
-* @retval status
-*/
-USBD_Status USBD_CtlSendStatus (USB_OTG_CORE_HANDLE *pdev)
-{
- USBD_Status ret = USBD_OK;
- pdev->dev.device_state = USB_OTG_EP0_STATUS_IN;
- DCD_EP_Tx (pdev,
- 0,
- NULL,
- 0);
-
- USB_OTG_EP0_OutStart(pdev);
-
- return ret;
-}
-
-/**
-* @brief USBD_CtlReceiveStatus
-* receive zero lzngth packet on the ctl pipe
-* @param pdev: USB OTG device instance
-* @retval status
-*/
-USBD_Status USBD_CtlReceiveStatus (USB_OTG_CORE_HANDLE *pdev)
-{
- USBD_Status ret = USBD_OK;
- pdev->dev.device_state = USB_OTG_EP0_STATUS_OUT;
- DCD_EP_PrepareRx ( pdev,
- 0,
- NULL,
- 0);
-
- USB_OTG_EP0_OutStart(pdev);
-
- return ret;
-}
-
-
-/**
-* @brief USBD_GetRxCount
-* returns the received data length
-* @param pdev: USB OTG device instance
-* epnum: endpoint index
-* @retval Rx Data blength
-*/
-uint16_t USBD_GetRxCount (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum)
-{
- return pdev->dev.out_ep[epnum].xfer_count;
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbd_req.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 22-July-2011
- * @brief This file provides the standard USB requests following chapter 9.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_req.h"
-#include "usbd_ioreq.h"
-#include "usbd_desc.h"
-
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup USBD_REQ
- * @brief USB standard requests module
- * @{
- */
-
-/** @defgroup USBD_REQ_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_REQ_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_REQ_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_REQ_Private_Variables
- * @{
- */
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN uint32_t USBD_ep_status __ALIGN_END = 0;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN uint32_t USBD_default_cfg __ALIGN_END = 0;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN uint32_t USBD_cfg_status __ALIGN_END = 0;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ] __ALIGN_END ;
-/**
- * @}
- */
-
-
-/** @defgroup USBD_REQ_Private_FunctionPrototypes
- * @{
- */
-static void USBD_GetDescriptor(USB_OTG_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req);
-
-static void USBD_SetAddress(USB_OTG_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req);
-
-static void USBD_SetConfig(USB_OTG_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req);
-
-static void USBD_GetConfig(USB_OTG_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req);
-
-static void USBD_GetStatus(USB_OTG_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req);
-
-static void USBD_SetFeature(USB_OTG_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req);
-
-static void USBD_ClrFeature(USB_OTG_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req);
-
-static uint8_t USBD_GetLen(uint8_t *buf);
-/**
- * @}
- */
-
-
-/** @defgroup USBD_REQ_Private_Functions
- * @{
- */
-
-
-/**
-* @brief USBD_StdDevReq
-* Handle standard usb device requests
-* @param pdev: device instance
-* @param req: usb request
-* @retval status
-*/
-USBD_Status USBD_StdDevReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req)
-{
- USBD_Status ret = USBD_OK;
-
- switch (req->bRequest)
- {
- case USB_REQ_GET_DESCRIPTOR:
-
- USBD_GetDescriptor (pdev, req) ;
- break;
-
- case USB_REQ_SET_ADDRESS:
- USBD_SetAddress(pdev, req);
- break;
-
- case USB_REQ_SET_CONFIGURATION:
- USBD_SetConfig (pdev , req);
- break;
-
- case USB_REQ_GET_CONFIGURATION:
- USBD_GetConfig (pdev , req);
- break;
-
- case USB_REQ_GET_STATUS:
- USBD_GetStatus (pdev , req);
- break;
-
-
- case USB_REQ_SET_FEATURE:
- USBD_SetFeature (pdev , req);
- break;
-
- case USB_REQ_CLEAR_FEATURE:
- USBD_ClrFeature (pdev , req);
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
-
- return ret;
-}
-
-/**
-* @brief USBD_StdItfReq
-* Handle standard usb interface requests
-* @param pdev: USB OTG device instance
-* @param req: usb request
-* @retval status
-*/
-USBD_Status USBD_StdItfReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req)
-{
- USBD_Status ret = USBD_OK;
-
- switch (pdev->dev.device_status)
- {
- case USB_OTG_CONFIGURED:
-
- if (LOBYTE(req->wIndex) <= USBD_ITF_MAX_NUM)
- {
- pdev->dev.class_cb->Setup (pdev, req);
-
- if((req->wLength == 0)&& (ret == USBD_OK))
- {
- USBD_CtlSendStatus(pdev);
- }
- }
- else
- {
- USBD_CtlError(pdev , req);
- }
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
- return ret;
-}
-
-/**
-* @brief USBD_StdEPReq
-* Handle standard usb endpoint requests
-* @param pdev: USB OTG device instance
-* @param req: usb request
-* @retval status
-*/
-USBD_Status USBD_StdEPReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req)
-{
-
- uint8_t ep_addr;
- USBD_Status ret = USBD_OK;
-
- ep_addr = LOBYTE(req->wIndex);
-
- switch (req->bRequest)
- {
-
- case USB_REQ_SET_FEATURE :
-
- switch (pdev->dev.device_status)
- {
- case USB_OTG_ADDRESSED:
- if ((ep_addr != 0x00) && (ep_addr != 0x80))
- {
- DCD_EP_Stall(pdev , ep_addr);
- }
- break;
-
- case USB_OTG_CONFIGURED:
- if (req->wValue == USB_FEATURE_EP_HALT)
- {
- if ((ep_addr != 0x00) && (ep_addr != 0x80))
- {
- DCD_EP_Stall(pdev , ep_addr);
-
- }
- }
- pdev->dev.class_cb->Setup (pdev, req);
- USBD_CtlSendStatus(pdev);
-
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
- break;
-
- case USB_REQ_CLEAR_FEATURE :
-
- switch (pdev->dev.device_status)
- {
- case USB_OTG_ADDRESSED:
- if ((ep_addr != 0x00) && (ep_addr != 0x80))
- {
- DCD_EP_Stall(pdev , ep_addr);
- }
- break;
-
- case USB_OTG_CONFIGURED:
- if (req->wValue == USB_FEATURE_EP_HALT)
- {
- if ((ep_addr != 0x00) && (ep_addr != 0x80))
- {
- DCD_EP_ClrStall(pdev , ep_addr);
- pdev->dev.class_cb->Setup (pdev, req);
- }
- USBD_CtlSendStatus(pdev);
- }
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
- break;
-
- case USB_REQ_GET_STATUS:
- switch (pdev->dev.device_status)
- {
- case USB_OTG_ADDRESSED:
- if ((ep_addr != 0x00) && (ep_addr != 0x80))
- {
- DCD_EP_Stall(pdev , ep_addr);
- }
- break;
-
- case USB_OTG_CONFIGURED:
-
-
- if ((ep_addr & 0x80)== 0x80)
- {
- if(pdev->dev.in_ep[ep_addr & 0x7F].is_stall)
- {
- USBD_ep_status = 0x0001;
- }
- else
- {
- USBD_ep_status = 0x0000;
- }
- }
- else if ((ep_addr & 0x80)== 0x00)
- {
- if(pdev->dev.out_ep[ep_addr].is_stall)
- {
- USBD_ep_status = 0x0001;
- }
-
- else
- {
- USBD_ep_status = 0x0000;
- }
- }
- USBD_CtlSendData (pdev,
- (uint8_t *)&USBD_ep_status,
- 2);
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
- break;
-
- default:
- break;
- }
- return ret;
-}
-/**
-* @brief USBD_GetDescriptor
-* Handle Get Descriptor requests
-* @param pdev: device instance
-* @param req: usb request
-* @retval status
-*/
-static void USBD_GetDescriptor(USB_OTG_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req)
-{
- uint16_t len;
- uint8_t *pbuf;
-
- switch (req->wValue >> 8)
- {
- case USB_DESC_TYPE_DEVICE:
- pbuf = pdev->dev.usr_device->GetDeviceDescriptor(pdev->cfg.speed, &len);
- if ((req->wLength == 64) ||( pdev->dev.device_status == USB_OTG_DEFAULT))
- {
- len = 8;
- }
- break;
-
- case USB_DESC_TYPE_CONFIGURATION:
- pbuf = (uint8_t *)pdev->dev.class_cb->GetConfigDescriptor(pdev->cfg.speed, &len);
-#ifdef USB_OTG_HS_CORE
- if((pdev->cfg.speed == USB_OTG_SPEED_FULL )&&
- (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY))
- {
- pbuf = (uint8_t *)pdev->dev.class_cb->GetOtherConfigDescriptor(pdev->cfg.speed, &len);
- }
-#endif
- pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
- pdev->dev.pConfig_descriptor = pbuf;
- break;
-
- case USB_DESC_TYPE_STRING:
- switch ((uint8_t)(req->wValue))
- {
- case USBD_IDX_LANGID_STR:
- pbuf = pdev->dev.usr_device->GetLangIDStrDescriptor(pdev->cfg.speed, &len);
- break;
-
- case USBD_IDX_MFC_STR:
- pbuf = pdev->dev.usr_device->GetManufacturerStrDescriptor(pdev->cfg.speed, &len);
- break;
-
- case USBD_IDX_PRODUCT_STR:
- pbuf = pdev->dev.usr_device->GetProductStrDescriptor(pdev->cfg.speed, &len);
- break;
-
- case USBD_IDX_SERIAL_STR:
- pbuf = pdev->dev.usr_device->GetSerialStrDescriptor(pdev->cfg.speed, &len);
- break;
-
- case USBD_IDX_CONFIG_STR:
- pbuf = pdev->dev.usr_device->GetConfigurationStrDescriptor(pdev->cfg.speed, &len);
- break;
-
- case USBD_IDX_INTERFACE_STR:
- pbuf = pdev->dev.usr_device->GetInterfaceStrDescriptor(pdev->cfg.speed, &len);
- break;
-
- default:
-#ifdef USB_SUPPORT_USER_STRING_DESC
- pbuf = pdev->dev.class_cb->GetUsrStrDescriptor(pdev->cfg.speed, (req->wValue) , &len);
- break;
-#else
- USBD_CtlError(pdev , req);
- return;
-#endif /* USBD_CtlError(pdev , req); */
- }
- break;
- case USB_DESC_TYPE_DEVICE_QUALIFIER:
-#ifdef USB_OTG_HS_CORE
- if(pdev->cfg.speed == USB_OTG_SPEED_HIGH )
- {
-
- pbuf = (uint8_t *)pdev->dev.class_cb->GetConfigDescriptor(pdev->cfg.speed, &len);
-
- USBD_DeviceQualifierDesc[4]= pbuf[14];
- USBD_DeviceQualifierDesc[5]= pbuf[15];
- USBD_DeviceQualifierDesc[6]= pbuf[16];
-
- pbuf = USBD_DeviceQualifierDesc;
- len = USB_LEN_DEV_QUALIFIER_DESC;
- break;
- }
- else
- {
- USBD_CtlError(pdev , req);
- return;
- }
-#else
- USBD_CtlError(pdev , req);
- return;
-#endif
-
- case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
-#ifdef USB_OTG_HS_CORE
-
- if(pdev->cfg.speed == USB_OTG_SPEED_HIGH )
- {
- pbuf = (uint8_t *)pdev->dev.class_cb->GetOtherConfigDescriptor(pdev->cfg.speed, &len);
- pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
- break;
- }
- else
- {
- USBD_CtlError(pdev , req);
- return;
- }
-#else
- USBD_CtlError(pdev , req);
- return;
-#endif
-
-
- default:
- USBD_CtlError(pdev , req);
- return;
- }
-
- if((len != 0)&& (req->wLength != 0))
- {
-
- len = MIN(len , req->wLength);
-
- USBD_CtlSendData (pdev,
- pbuf,
- len);
- }
-
-}
-
-/**
-* @brief USBD_SetAddress
-* Set device address
-* @param pdev: device instance
-* @param req: usb request
-* @retval status
-*/
-static void USBD_SetAddress(USB_OTG_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req)
-{
- uint8_t dev_addr;
-
- if ((req->wIndex == 0) && (req->wLength == 0))
- {
- dev_addr = (uint8_t)(req->wValue) & 0x7F;
-
- if (pdev->dev.device_status == USB_OTG_CONFIGURED)
- {
- USBD_CtlError(pdev , req);
- }
- else
- {
- pdev->dev.device_address = dev_addr;
- DCD_EP_SetAddress(pdev, dev_addr);
- USBD_CtlSendStatus(pdev);
-
- if (dev_addr != 0)
- {
- pdev->dev.device_status = USB_OTG_ADDRESSED;
- }
- else
- {
- pdev->dev.device_status = USB_OTG_DEFAULT;
- }
- }
- }
- else
- {
- USBD_CtlError(pdev , req);
- }
-}
-
-/**
-* @brief USBD_SetConfig
-* Handle Set device configuration request
-* @param pdev: device instance
-* @param req: usb request
-* @retval status
-*/
-static void USBD_SetConfig(USB_OTG_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req)
-{
-
- static uint8_t cfgidx;
-
- cfgidx = (uint8_t)(req->wValue);
-
- if (cfgidx > USBD_CFG_MAX_NUM )
- {
- USBD_CtlError(pdev , req);
- }
- else
- {
- switch (pdev->dev.device_status)
- {
- case USB_OTG_ADDRESSED:
- if (cfgidx)
- {
- pdev->dev.device_config = cfgidx;
- pdev->dev.device_status = USB_OTG_CONFIGURED;
- USBD_SetCfg(pdev , cfgidx);
- USBD_CtlSendStatus(pdev);
- }
- else
- {
- USBD_CtlSendStatus(pdev);
- }
- break;
-
- case USB_OTG_CONFIGURED:
- if (cfgidx == 0)
- {
- pdev->dev.device_status = USB_OTG_ADDRESSED;
- pdev->dev.device_config = cfgidx;
- USBD_ClrCfg(pdev , cfgidx);
- USBD_CtlSendStatus(pdev);
-
- }
- else if (cfgidx != pdev->dev.device_config)
- {
- /* Clear old configuration */
- USBD_ClrCfg(pdev , pdev->dev.device_config);
-
- /* set new configuration */
- pdev->dev.device_config = cfgidx;
- USBD_SetCfg(pdev , cfgidx);
- USBD_CtlSendStatus(pdev);
- }
- else
- {
- USBD_CtlSendStatus(pdev);
- }
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
- }
-}
-
-/**
-* @brief USBD_GetConfig
-* Handle Get device configuration request
-* @param pdev: device instance
-* @param req: usb request
-* @retval status
-*/
-static void USBD_GetConfig(USB_OTG_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req)
-{
-
- if (req->wLength != 1)
- {
- USBD_CtlError(pdev , req);
- }
- else
- {
- switch (pdev->dev.device_status )
- {
- case USB_OTG_ADDRESSED:
-
- USBD_CtlSendData (pdev,
- (uint8_t *)&USBD_default_cfg,
- 1);
- break;
-
- case USB_OTG_CONFIGURED:
-
- USBD_CtlSendData (pdev,
- &pdev->dev.device_config,
- 1);
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
- }
-}
-
-/**
-* @brief USBD_GetStatus
-* Handle Get Status request
-* @param pdev: device instance
-* @param req: usb request
-* @retval status
-*/
-static void USBD_GetStatus(USB_OTG_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req)
-{
-
- switch (pdev->dev.device_status)
- {
- case USB_OTG_ADDRESSED:
- case USB_OTG_CONFIGURED:
-
- if (pdev->dev.DevRemoteWakeup)
- {
- USBD_cfg_status = USB_CONFIG_SELF_POWERED | USB_CONFIG_REMOTE_WAKEUP;
- }
- else
- {
- USBD_cfg_status = USB_CONFIG_SELF_POWERED;
- }
-
- USBD_CtlSendData (pdev,
- (uint8_t *)&USBD_cfg_status,
- 1);
- break;
-
- default :
- USBD_CtlError(pdev , req);
- break;
- }
-}
-
-
-/**
-* @brief USBD_SetFeature
-* Handle Set device feature request
-* @param pdev: device instance
-* @param req: usb request
-* @retval status
-*/
-static void USBD_SetFeature(USB_OTG_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req)
-{
-
- USB_OTG_DCTL_TypeDef dctl;
- uint8_t test_mode = 0;
-
- if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
- {
- pdev->dev.DevRemoteWakeup = 1;
- pdev->dev.class_cb->Setup (pdev, req);
- USBD_CtlSendStatus(pdev);
- }
-
- else if ((req->wValue == USB_FEATURE_TEST_MODE) &&
- ((req->wIndex & 0xFF) == 0))
- {
- dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL);
-
- test_mode = req->wIndex >> 8;
- switch (test_mode)
- {
- case 1: // TEST_J
- dctl.b.tstctl = 1;
- break;
-
- case 2: // TEST_K
- dctl.b.tstctl = 2;
- break;
-
- case 3: // TEST_SE0_NAK
- dctl.b.tstctl = 3;
- break;
-
- case 4: // TEST_PACKET
- dctl.b.tstctl = 4;
- break;
-
- case 5: // TEST_FORCE_ENABLE
- dctl.b.tstctl = 5;
- break;
- }
- USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32);
- USBD_CtlSendStatus(pdev);
- }
-
-}
-
-
-/**
-* @brief USBD_ClrFeature
-* Handle clear device feature request
-* @param pdev: device instance
-* @param req: usb request
-* @retval status
-*/
-static void USBD_ClrFeature(USB_OTG_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req)
-{
- switch (pdev->dev.device_status)
- {
- case USB_OTG_ADDRESSED:
- case USB_OTG_CONFIGURED:
- if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
- {
- pdev->dev.DevRemoteWakeup = 0;
- pdev->dev.class_cb->Setup (pdev, req);
- USBD_CtlSendStatus(pdev);
- }
- break;
-
- default :
- USBD_CtlError(pdev , req);
- break;
- }
-}
-
-/**
-* @brief USBD_ParseSetupRequest
-* Copy buffer into setup structure
-* @param pdev: device instance
-* @param req: usb request
-* @retval None
-*/
-
-void USBD_ParseSetupRequest( USB_OTG_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req)
-{
- req->bmRequest = *(uint8_t *) (pdev->dev.setup_packet);
- req->bRequest = *(uint8_t *) (pdev->dev.setup_packet + 1);
- req->wValue = SWAPBYTE (pdev->dev.setup_packet + 2);
- req->wIndex = SWAPBYTE (pdev->dev.setup_packet + 4);
- req->wLength = SWAPBYTE (pdev->dev.setup_packet + 6);
-
- pdev->dev.in_ep[0].ctl_data_len = req->wLength ;
- pdev->dev.device_state = USB_OTG_EP0_SETUP;
-}
-
-/**
-* @brief USBD_CtlError
-* Handle USB low level Error
-* @param pdev: device instance
-* @param req: usb request
-* @retval None
-*/
-
-void USBD_CtlError( USB_OTG_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req)
-{
- if((req->bmRequest & 0x80) == 0x80)
- {
- DCD_EP_Stall(pdev , 0x80);
- }
- else
- {
- if(req->wLength == 0)
- {
- DCD_EP_Stall(pdev , 0x80);
- }
- else
- {
- DCD_EP_Stall(pdev , 0);
- }
- }
- USB_OTG_EP0_OutStart(pdev);
-}
-
-
-/**
- * @brief USBD_GetString
- * Convert Ascii string into unicode one
- * @param desc : descriptor buffer
- * @param unicode : Formatted string buffer (unicode)
- * @param len : descriptor length
- * @retval None
- */
-void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
-{
- uint8_t idx = 0;
-
- if (desc != NULL)
- {
- *len = USBD_GetLen(desc) * 2 + 2;
- unicode[idx++] = *len;
- unicode[idx++] = USB_DESC_TYPE_STRING;
-
- while (*desc != NULL)
- {
- unicode[idx++] = *desc++;
- unicode[idx++] = 0x00;
- }
- }
-}
-
-/**
- * @brief USBD_GetLen
- * return the string length
- * @param buf : pointer to the ascii string buffer
- * @retval string length
- */
-static uint8_t USBD_GetLen(uint8_t *buf)
-{
- uint8_t len = 0;
-
- while (*buf != NULL)
- {
- len++;
- buf++;
- }
-
- return len;
-}
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_hid_core.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief This file contains all the prototypes for the usbh_hid_core.c
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive ----------------------------------------------*/
-#ifndef __USBH_HID_CORE_H
-#define __USBH_HID_CORE_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_core.h"
-#include "usbh_stdreq.h"
-#include "usb_bsp.h"
-#include "usbh_ioreq.h"
-#include "usbh_hcs.h"
-
-/** @addtogroup USBH_LIB
- * @{
- */
-
-/** @addtogroup USBH_CLASS
- * @{
- */
-
-/** @addtogroup USBH_HID_CLASS
- * @{
- */
-
-/** @defgroup USBH_HID_CORE
- * @brief This file is the Header file for USBH_HID_CORE.c
- * @{
- */
-
-
-/** @defgroup USBH_HID_CORE_Exported_Types
- * @{
- */
-
-
-/* States for HID State Machine */
-typedef enum
-{
- HID_IDLE= 0,
- HID_SEND_DATA,
- HID_BUSY,
- HID_GET_DATA,
- HID_POLL,
- HID_ERROR,
-}
-HID_State;
-
-typedef enum
-{
- HID_REQ_IDLE = 0,
- HID_REQ_GET_REPORT_DESC,
- HID_REQ_GET_HID_DESC,
- HID_REQ_SET_IDLE,
- HID_REQ_SET_PROTOCOL,
- HID_REQ_SET_REPORT,
-
-}
-HID_CtlState;
-
-typedef struct HID_cb
-{
- void (*Init) (void);
- void (*Decode) (uint8_t *data);
-
-} HID_cb_TypeDef;
-
-typedef struct _HID_Report
-{
- uint8_t ReportID;
- uint8_t ReportType;
- uint16_t UsagePage;
- uint32_t Usage[2];
- uint32_t NbrUsage;
- uint32_t UsageMin;
- uint32_t UsageMax;
- int32_t LogMin;
- int32_t LogMax;
- int32_t PhyMin;
- int32_t PhyMax;
- int32_t UnitExp;
- uint32_t Unit;
- uint32_t ReportSize;
- uint32_t ReportCnt;
- uint32_t Flag;
- uint32_t PhyUsage;
- uint32_t AppUsage;
- uint32_t LogUsage;
-}
-HID_Report_TypeDef;
-
-/* Structure for HID process */
-typedef struct _HID_Process
-{
- uint8_t buff[64];
- uint8_t hc_num_in;
- uint8_t hc_num_out;
- HID_State state;
- uint8_t HIDIntOutEp;
- uint8_t HIDIntInEp;
- HID_CtlState ctl_state;
- uint16_t length;
- uint8_t ep_addr;
- uint16_t poll;
- __IO uint16_t timer;
- HID_cb_TypeDef *cb;
-}
-HID_Machine_TypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup USBH_HID_CORE_Exported_Defines
- * @{
- */
-
-#define USB_HID_REQ_GET_REPORT 0x01
-#define USB_HID_GET_IDLE 0x02
-#define USB_HID_GET_PROTOCOL 0x03
-#define USB_HID_SET_REPORT 0x09
-#define USB_HID_SET_IDLE 0x0A
-#define USB_HID_SET_PROTOCOL 0x0B
-/**
- * @}
- */
-
-/** @defgroup USBH_HID_CORE_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_HID_CORE_Exported_Variables
- * @{
- */
-extern USBH_Class_cb_TypeDef HID_cb;
-/**
- * @}
- */
-
-/** @defgroup USBH_HID_CORE_Exported_FunctionsPrototype
- * @{
- */
-
-USBH_Status USBH_Set_Report (USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t reportType,
- uint8_t reportId,
- uint8_t reportLen,
- uint8_t* reportBuff);
-/**
- * @}
- */
-
-
-#endif /* __USBH_HID_CORE_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_hid_keybd.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief This file contains all the prototypes for the usbh_hid_keybd.c
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive -----------------------------------------------*/
-#ifndef __USBH_HID_KEYBD_H
-#define __USBH_HID_KEYBD_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_conf.h"
-#include "usbh_hid_core.h"
-
-/** @addtogroup USBH_LIB
- * @{
- */
-
-/** @addtogroup USBH_CLASS
- * @{
- */
-
-/** @addtogroup USBH_HID_CLASS
- * @{
- */
-
-/** @defgroup USBH_HID_KEYBD
- * @brief This file is the Header file for USBH_HID_KEYBD.c
- * @{
- */
-
-
-/** @defgroup USBH_HID_KEYBD_Exported_Types
- * @{
- */
-
-
-/**
- * @}
- */
-
-/** @defgroup USBH_HID_KEYBD_Exported_Defines
- * @{
- */
-//#define QWERTY_KEYBOARD
-#define AZERTY_KEYBOARD
-
-#define KBD_LEFT_CTRL 0x01
-#define KBD_LEFT_SHIFT 0x02
-#define KBD_LEFT_ALT 0x04
-#define KBD_LEFT_GUI 0x08
-#define KBD_RIGHT_CTRL 0x10
-#define KBD_RIGHT_SHIFT 0x20
-#define KBD_RIGHT_ALT 0x40
-#define KBD_RIGHT_GUI 0x80
-
-#define KBR_MAX_NBR_PRESSED 6
-
-/**
- * @}
- */
-
-/** @defgroup USBH_HID_KEYBD_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_HID_KEYBD_Exported_Variables
- * @{
- */
-
-extern HID_cb_TypeDef HID_KEYBRD_cb;
-/**
- * @}
- */
-
-/** @defgroup USBH_HID_KEYBD_Exported_FunctionsPrototype
- * @{
- */
-void USR_KEYBRD_Init (void);
-void USR_KEYBRD_ProcessData (uint8_t pbuf);
-/**
- * @}
- */
-
-#endif /* __USBH_HID_KEYBD_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_hid_mouse.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief This file contains all the prototypes for the usbh_hid_mouse.c
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-
-/* Define to prevent recursive ----------------------------------------------*/
-#ifndef __USBH_HID_MOUSE_H
-#define __USBH_HID_MOUSE_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_hid_core.h"
-
-/** @addtogroup USBH_LIB
- * @{
- */
-
-/** @addtogroup USBH_CLASS
- * @{
- */
-
-/** @addtogroup USBH_HID_CLASS
- * @{
- */
-
-/** @defgroup USBH_HID_MOUSE
- * @brief This file is the Header file for USBH_HID_MOUSE.c
- * @{
- */
-
-
-/** @defgroup USBH_HID_MOUSE_Exported_Types
- * @{
- */
-typedef struct _HID_MOUSE_Data
-{
- uint8_t x;
- uint8_t y;
- uint8_t z; /* Not Supported */
- uint8_t button;
-}
-HID_MOUSE_Data_TypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup USBH_HID_MOUSE_Exported_Defines
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_HID_MOUSE_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_HID_MOUSE_Exported_Variables
- * @{
- */
-
-extern HID_cb_TypeDef HID_MOUSE_cb;
-extern HID_MOUSE_Data_TypeDef HID_MOUSE_Data;
-/**
- * @}
- */
-
-/** @defgroup USBH_HID_MOUSE_Exported_FunctionsPrototype
- * @{
- */
-void USR_MOUSE_Init (void);
-void USR_MOUSE_ProcessData (HID_MOUSE_Data_TypeDef *data);
-/**
- * @}
- */
-
-#endif /* __USBH_HID_MOUSE_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_hid_core.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief This file is the HID Layer Handlers for USB Host HID class.
- *
- * @verbatim
- *
- * ===================================================================
- * HID Class Description
- * ===================================================================
- * This module manages the MSC class V1.11 following the "Device Class Definition
- * for Human Interface Devices (HID) Version 1.11 Jun 27, 2001".
- * This driver implements the following aspects of the specification:
- * - The Boot Interface Subclass
- * - The Mouse and Keyboard protocols
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_hid_core.h"
-#include "usbh_hid_mouse.h"
-#include "usbh_hid_keybd.h"
-
-/** @addtogroup USBH_LIB
-* @{
-*/
-
-/** @addtogroup USBH_CLASS
-* @{
-*/
-
-/** @addtogroup USBH_HID_CLASS
-* @{
-*/
-
-/** @defgroup USBH_HID_CORE
-* @brief This file includes HID Layer Handlers for USB Host HID class.
-* @{
-*/
-
-/** @defgroup USBH_HID_CORE_Private_TypesDefinitions
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USBH_HID_CORE_Private_Defines
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USBH_HID_CORE_Private_Macros
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USBH_HID_CORE_Private_Variables
-* @{
-*/
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN HID_Machine_TypeDef HID_Machine __ALIGN_END ;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN HID_Report_TypeDef HID_Report __ALIGN_END ;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN USB_Setup_TypeDef HID_Setup __ALIGN_END ;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN USBH_HIDDesc_TypeDef HID_Desc __ALIGN_END ;
-
-__IO uint8_t flag = 0;
-/**
-* @}
-*/
-
-
-/** @defgroup USBH_HID_CORE_Private_FunctionPrototypes
-* @{
-*/
-
-static USBH_Status USBH_HID_InterfaceInit (USB_OTG_CORE_HANDLE *pdev ,
- void *phost);
-
-static void USBH_ParseHIDDesc (USBH_HIDDesc_TypeDef *desc, uint8_t *buf);
-
-static void USBH_HID_InterfaceDeInit (USB_OTG_CORE_HANDLE *pdev ,
- void *phost);
-
-static USBH_Status USBH_HID_Handle(USB_OTG_CORE_HANDLE *pdev ,
- void *phost);
-
-static USBH_Status USBH_HID_ClassRequest(USB_OTG_CORE_HANDLE *pdev ,
- void *phost);
-
-static USBH_Status USBH_Get_HID_ReportDescriptor (USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint16_t length);
-
-static USBH_Status USBH_Get_HID_Descriptor (USB_OTG_CORE_HANDLE *pdev,\
- USBH_HOST *phost,
- uint16_t length);
-
-static USBH_Status USBH_Set_Idle (USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t duration,
- uint8_t reportId);
-
-static USBH_Status USBH_Set_Protocol (USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t protocol);
-
-
-USBH_Class_cb_TypeDef HID_cb =
-{
- USBH_HID_InterfaceInit,
- USBH_HID_InterfaceDeInit,
- USBH_HID_ClassRequest,
- USBH_HID_Handle
-};
-/**
-* @}
-*/
-
-
-/** @defgroup USBH_HID_CORE_Private_Functions
-* @{
-*/
-
-/**
-* @brief USBH_HID_InterfaceInit
-* The function init the HID class.
-* @param pdev: Selected device
-* @param hdev: Selected device property
-* @retval USBH_Status :Response for USB HID driver intialization
-*/
-static USBH_Status USBH_HID_InterfaceInit ( USB_OTG_CORE_HANDLE *pdev,
- void *phost)
-{
- uint8_t maxEP;
- USBH_HOST *pphost = phost;
-
- uint8_t num =0;
- USBH_Status status = USBH_BUSY ;
- HID_Machine.state = HID_ERROR;
-
-
- if(pphost->device_prop.Itf_Desc[0].bInterfaceSubClass == HID_BOOT_CODE)
- {
- /*Decode Bootclass Protocl: Mouse or Keyboard*/
- if(pphost->device_prop.Itf_Desc[0].bInterfaceProtocol == HID_KEYBRD_BOOT_CODE)
- {
- HID_Machine.cb = &HID_KEYBRD_cb;
- }
- else if(pphost->device_prop.Itf_Desc[0].bInterfaceProtocol == HID_MOUSE_BOOT_CODE)
- {
- HID_Machine.cb = &HID_MOUSE_cb;
- }
-
- HID_Machine.state = HID_IDLE;
- HID_Machine.ctl_state = HID_REQ_IDLE;
- HID_Machine.ep_addr = pphost->device_prop.Ep_Desc[0][0].bEndpointAddress;
- HID_Machine.length = pphost->device_prop.Ep_Desc[0][0].wMaxPacketSize;
- HID_Machine.poll = pphost->device_prop.Ep_Desc[0][0].bInterval ;
-
- /* Check fo available number of endpoints */
- /* Find the number of EPs in the Interface Descriptor */
- /* Choose the lower number in order not to overrun the buffer allocated */
- maxEP = ( (pphost->device_prop.Itf_Desc[0].bNumEndpoints <= USBH_MAX_NUM_ENDPOINTS) ?
- pphost->device_prop.Itf_Desc[0].bNumEndpoints :
- USBH_MAX_NUM_ENDPOINTS);
-
-
- /* Decode endpoint IN and OUT address from interface descriptor */
- for (num=0; num < maxEP; num++)
- {
- if(pphost->device_prop.Ep_Desc[0][num].bEndpointAddress & 0x80)
- {
- HID_Machine.HIDIntInEp = (pphost->device_prop.Ep_Desc[0][num].bEndpointAddress);
- HID_Machine.hc_num_in =\
- USBH_Alloc_Channel(pdev,
- pphost->device_prop.Ep_Desc[0][num].bEndpointAddress);
-
- /* Open channel for IN endpoint */
- USBH_Open_Channel (pdev,
- HID_Machine.hc_num_in,
- pphost->device_prop.address,
- pphost->device_prop.speed,
- EP_TYPE_INTR,
- HID_Machine.length);
- }
- else
- {
- HID_Machine.HIDIntOutEp = (pphost->device_prop.Ep_Desc[0][num].bEndpointAddress);
- HID_Machine.hc_num_out =\
- USBH_Alloc_Channel(pdev,
- pphost->device_prop.Ep_Desc[0][num].bEndpointAddress);
-
- /* Open channel for OUT endpoint */
- USBH_Open_Channel (pdev,
- HID_Machine.hc_num_out,
- pphost->device_prop.address,
- pphost->device_prop.speed,
- EP_TYPE_INTR,
- HID_Machine.length);
- }
-
- }
-
- flag =0;
- status = USBH_OK;
- }
- else
- {
- pphost->usr_cb->USBH_USR_DeviceNotSupported();
- }
-
- return status;
-
-}
-
-
-
-/**
-* @brief USBH_HID_InterfaceDeInit
-* The function DeInit the Host Channels used for the HID class.
-* @param pdev: Selected device
-* @param hdev: Selected device property
-* @retval None
-*/
-void USBH_HID_InterfaceDeInit ( USB_OTG_CORE_HANDLE *pdev,
- void *phost)
-{
- //USBH_HOST *pphost = phost;
-
- if(HID_Machine.hc_num_in != 0x00)
- {
- USB_OTG_HC_Halt(pdev, HID_Machine.hc_num_in);
- USBH_Free_Channel (pdev, HID_Machine.hc_num_in);
- HID_Machine.hc_num_in = 0; /* Reset the Channel as Free */
- }
-
- if(HID_Machine.hc_num_out != 0x00)
- {
- USB_OTG_HC_Halt(pdev, HID_Machine.hc_num_out);
- USBH_Free_Channel (pdev, HID_Machine.hc_num_out);
- HID_Machine.hc_num_out = 0; /* Reset the Channel as Free */
- }
-
- flag = 0;
-}
-
-/**
-* @brief USBH_HID_ClassRequest
-* The function is responsible for handling HID Class requests
-* for HID class.
-* @param pdev: Selected device
-* @param hdev: Selected device property
-* @retval USBH_Status :Response for USB Set Protocol request
-*/
-static USBH_Status USBH_HID_ClassRequest(USB_OTG_CORE_HANDLE *pdev ,
- void *phost)
-{
- USBH_HOST *pphost = phost;
-
- USBH_Status status = USBH_BUSY;
- USBH_Status classReqStatus = USBH_BUSY;
-
-
- /* Switch HID state machine */
- switch (HID_Machine.ctl_state)
- {
- case HID_IDLE:
- case HID_REQ_GET_HID_DESC:
-
- /* Get HID Desc */
- if (USBH_Get_HID_Descriptor (pdev, pphost, USB_HID_DESC_SIZE)== USBH_OK)
- {
-
- USBH_ParseHIDDesc(&HID_Desc, pdev->host.Rx_Buffer);
- HID_Machine.ctl_state = HID_REQ_GET_REPORT_DESC;
- }
-
- break;
- case HID_REQ_GET_REPORT_DESC:
-
-
- /* Get Report Desc */
- if (USBH_Get_HID_ReportDescriptor(pdev , pphost, HID_Desc.wItemLength) == USBH_OK)
- {
- HID_Machine.ctl_state = HID_REQ_SET_IDLE;
- }
-
- break;
-
- case HID_REQ_SET_IDLE:
-
- classReqStatus = USBH_Set_Idle (pdev, pphost, 0, 0);
-
- /* set Idle */
- if (classReqStatus == USBH_OK)
- {
- HID_Machine.ctl_state = HID_REQ_SET_PROTOCOL;
- }
- else if(classReqStatus == USBH_NOT_SUPPORTED)
- {
- HID_Machine.ctl_state = HID_REQ_SET_PROTOCOL;
- }
- break;
-
- case HID_REQ_SET_PROTOCOL:
- /* set protocol */
- if (USBH_Set_Protocol (pdev ,pphost, 0) == USBH_OK)
- {
- HID_Machine.ctl_state = HID_REQ_IDLE;
-
- /* all requests performed*/
- status = USBH_OK;
- }
- break;
-
- default:
- break;
- }
-
- return status;
-}
-
-
-/**
-* @brief USBH_HID_Handle
-* The function is for managing state machine for HID data transfers
-* @param pdev: Selected device
-* @param hdev: Selected device property
-* @retval USBH_Status
-*/
-static USBH_Status USBH_HID_Handle(USB_OTG_CORE_HANDLE *pdev ,
- void *phost)
-{
- USBH_HOST *pphost = phost;
- USBH_Status status = USBH_OK;
-
- switch (HID_Machine.state)
- {
-
- case HID_IDLE:
- HID_Machine.cb->Init();
- HID_Machine.state = HID_GET_DATA;
- break;
-
- case HID_GET_DATA:
-
- /* Sync with start of Even Frame */
- while(USB_OTG_IsEvenFrame(pdev) == FALSE);
-
- USBH_InterruptReceiveData(pdev,
- HID_Machine.buff,
- HID_Machine.length,
- HID_Machine.hc_num_in);
- flag = 1;
-
- HID_Machine.state = HID_POLL;
- HID_Machine.timer = HCD_GetCurrentFrame(pdev);
- break;
-
- case HID_POLL:
- if(( HCD_GetCurrentFrame(pdev) - HID_Machine.timer) >= HID_Machine.poll)
- {
- HID_Machine.state = HID_GET_DATA;
- }
- else if(HCD_GetURB_State(pdev , HID_Machine.hc_num_in) == URB_DONE)
- {
- if(flag == 1) /* handle data once */
- {
- flag = 0;
- HID_Machine.cb->Decode(HID_Machine.buff);
- }
- }
- else if(HCD_GetURB_State(pdev, HID_Machine.hc_num_in) == URB_STALL) /* IN Endpoint Stalled */
- {
-
- /* Issue Clear Feature on interrupt IN endpoint */
- if( (USBH_ClrFeature(pdev,
- pphost,
- HID_Machine.ep_addr,
- HID_Machine.hc_num_in)) == USBH_OK)
- {
- /* Change state to issue next IN token */
- HID_Machine.state = HID_GET_DATA;
-
- }
-
- }
- break;
-
- default:
- break;
- }
- return status;
-}
-
-
-/**
-* @brief USBH_Get_HID_ReportDescriptor
-* Issue report Descriptor command to the device. Once the response
-* received, parse the report descriptor and update the status.
-* @param pdev : Selected device
-* @param Length : HID Report Descriptor Length
-* @retval USBH_Status : Response for USB HID Get Report Descriptor Request
-*/
-static USBH_Status USBH_Get_HID_ReportDescriptor (USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint16_t length)
-{
-
- USBH_Status status;
-
- status = USBH_GetDescriptor(pdev,
- phost,
- USB_REQ_RECIPIENT_INTERFACE
- | USB_REQ_TYPE_STANDARD,
- USB_DESC_HID_REPORT,
- pdev->host.Rx_Buffer,
- length);
-
- /* HID report descriptor is available in pdev->host.Rx_Buffer.
- In case of USB Boot Mode devices for In report handling ,
- HID report descriptor parsing is not required.
- In case, for supporting Non-Boot Protocol devices and output reports,
- user may parse the report descriptor*/
-
-
- return status;
-}
-
-/**
-* @brief USBH_Get_HID_Descriptor
-* Issue HID Descriptor command to the device. Once the response
-* received, parse the report descriptor and update the status.
-* @param pdev : Selected device
-* @param Length : HID Descriptor Length
-* @retval USBH_Status : Response for USB HID Get Report Descriptor Request
-*/
-static USBH_Status USBH_Get_HID_Descriptor (USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint16_t length)
-{
-
- USBH_Status status;
-
- status = USBH_GetDescriptor(pdev,
- phost,
- USB_REQ_RECIPIENT_INTERFACE
- | USB_REQ_TYPE_STANDARD,
- USB_DESC_HID,
- pdev->host.Rx_Buffer,
- length);
-
- return status;
-}
-
-/**
-* @brief USBH_Set_Idle
-* Set Idle State.
-* @param pdev: Selected device
-* @param duration: Duration for HID Idle request
-* @param reportID : Targetted report ID for Set Idle request
-* @retval USBH_Status : Response for USB Set Idle request
-*/
-static USBH_Status USBH_Set_Idle (USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t duration,
- uint8_t reportId)
-{
-
- phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE |\
- USB_REQ_TYPE_CLASS;
-
-
- phost->Control.setup.b.bRequest = USB_HID_SET_IDLE;
- phost->Control.setup.b.wValue.w = (duration << 8 ) | reportId;
-
- phost->Control.setup.b.wIndex.w = 0;
- phost->Control.setup.b.wLength.w = 0;
-
- return USBH_CtlReq(pdev, phost, 0 , 0 );
-}
-
-
-/**
-* @brief USBH_Set_Report
-* Issues Set Report
-* @param pdev: Selected device
-* @param reportType : Report type to be sent
-* @param reportID : Targetted report ID for Set Report request
-* @param reportLen : Length of data report to be send
-* @param reportBuff : Report Buffer
-* @retval USBH_Status : Response for USB Set Idle request
-*/
-USBH_Status USBH_Set_Report (USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t reportType,
- uint8_t reportId,
- uint8_t reportLen,
- uint8_t* reportBuff)
-{
-
- phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE |\
- USB_REQ_TYPE_CLASS;
-
-
- phost->Control.setup.b.bRequest = USB_HID_SET_REPORT;
- phost->Control.setup.b.wValue.w = (reportType << 8 ) | reportId;
-
- phost->Control.setup.b.wIndex.w = 0;
- phost->Control.setup.b.wLength.w = reportLen;
-
- return USBH_CtlReq(pdev, phost, reportBuff , reportLen );
-}
-
-
-/**
-* @brief USBH_Set_Protocol
-* Set protocol State.
-* @param pdev: Selected device
-* @param protocol : Set Protocol for HID : boot/report protocol
-* @retval USBH_Status : Response for USB Set Protocol request
-*/
-static USBH_Status USBH_Set_Protocol(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t protocol)
-{
-
-
- phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE |\
- USB_REQ_TYPE_CLASS;
-
-
- phost->Control.setup.b.bRequest = USB_HID_SET_PROTOCOL;
-
- if(protocol != 0)
- {
- /* Boot Protocol */
- phost->Control.setup.b.wValue.w = 0;
- }
- else
- {
- /*Report Protocol*/
- phost->Control.setup.b.wValue.w = 1;
- }
-
- phost->Control.setup.b.wIndex.w = 0;
- phost->Control.setup.b.wLength.w = 0;
-
- return USBH_CtlReq(pdev, phost, 0 , 0 );
-
-}
-
-/**
-* @brief USBH_ParseHIDDesc
-* This function Parse the HID descriptor
-* @param buf: Buffer where the source descriptor is available
-* @retval None
-*/
-static void USBH_ParseHIDDesc (USBH_HIDDesc_TypeDef *desc, uint8_t *buf)
-{
-
- desc->bLength = *(uint8_t *) (buf + 0);
- desc->bDescriptorType = *(uint8_t *) (buf + 1);
- desc->bcdHID = LE16 (buf + 2);
- desc->bCountryCode = *(uint8_t *) (buf + 4);
- desc->bNumDescriptors = *(uint8_t *) (buf + 5);
- desc->bReportDescriptorType = *(uint8_t *) (buf + 6);
- desc->wItemLength = LE16 (buf + 7);
-
-}
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-
-/**
-* @}
-*/
-
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_hid_keybd.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief This file is the application layer for USB Host HID Keyboard handling
- * QWERTY and AZERTY Keyboard are supported as per the selection in
- * usbh_hid_keybd.h
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_hid_keybd.h"
-
-/** @addtogroup USBH_LIB
-* @{
-*/
-
-/** @addtogroup USBH_CLASS
-* @{
-*/
-
-/** @addtogroup USBH_HID_CLASS
-* @{
-*/
-
-/** @defgroup USBH_HID_KEYBD
-* @brief This file includes HID Layer Handlers for USB Host HID class.
-* @{
-*/
-
-/** @defgroup USBH_HID_KEYBD_Private_TypesDefinitions
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USBH_HID_KEYBD_Private_Defines
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USBH_HID_KEYBD_Private_Macros
-* @{
-*/
-/**
-* @}
-*/
-
-/** @defgroup USBH_HID_KEYBD_Private_FunctionPrototypes
-* @{
-*/
-static void KEYBRD_Init (void);
-static void KEYBRD_Decode(uint8_t *data);
-
-/**
-* @}
-*/
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined (__CC_ARM) /*!< ARM Compiler */
- __align(4)
- #elif defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #elif defined (__GNUC__) /*!< GNU Compiler */
- #pragma pack(4)
- #elif defined (__TASKING__) /*!< TASKING Compiler */
- __align(4)
- #endif /* __CC_ARM */
-#endif
-
-/** @defgroup USBH_HID_KEYBD_Private_Variables
-* @{
-*/
-HID_cb_TypeDef HID_KEYBRD_cb=
-{
- KEYBRD_Init,
- KEYBRD_Decode
-};
-
-/*
-*******************************************************************************
-* LOCAL CONSTANTS
-*******************************************************************************
-*/
-
-static const uint8_t HID_KEYBRD_Codes[] = {
- 0, 0, 0, 0, 31, 50, 48, 33,
- 19, 34, 35, 36, 24, 37, 38, 39, /* 0x00 - 0x0F */
- 52, 51, 25, 26, 17, 20, 32, 21,
- 23, 49, 18, 47, 22, 46, 2, 3, /* 0x10 - 0x1F */
- 4, 5, 6, 7, 8, 9, 10, 11,
- 43, 110, 15, 16, 61, 12, 13, 27, /* 0x20 - 0x2F */
- 28, 29, 42, 40, 41, 1, 53, 54,
- 55, 30, 112, 113, 114, 115, 116, 117, /* 0x30 - 0x3F */
- 118, 119, 120, 121, 122, 123, 124, 125,
- 126, 75, 80, 85, 76, 81, 86, 89, /* 0x40 - 0x4F */
- 79, 84, 83, 90, 95, 100, 105, 106,
- 108, 93, 98, 103, 92, 97, 102, 91, /* 0x50 - 0x5F */
- 96, 101, 99, 104, 45, 129, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, /* 0x60 - 0x6F */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, /* 0x70 - 0x7F */
- 0, 0, 0, 0, 0, 107, 0, 56,
- 0, 0, 0, 0, 0, 0, 0, 0, /* 0x80 - 0x8F */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, /* 0x90 - 0x9F */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, /* 0xA0 - 0xAF */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, /* 0xB0 - 0xBF */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, /* 0xC0 - 0xCF */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, /* 0xD0 - 0xDF */
- 58, 44, 60, 127, 64, 57, 62, 128 /* 0xE0 - 0xE7 */
-};
-
-#ifdef QWERTY_KEYBOARD
-static const int8_t HID_KEYBRD_Key[] = {
- '\0', '`', '1', '2', '3', '4', '5', '6',
- '7', '8', '9', '0', '-', '=', '\0', '\r',
- '\t', 'q', 'w', 'e', 'r', 't', 'y', 'u',
- 'i', 'o', 'p', '[', ']', '\\',
- '\0', 'a', 's', 'd', 'f', 'g', 'h', 'j',
- 'k', 'l', ';', '\'', '\0', '\n',
- '\0', '\0', 'z', 'x', 'c', 'v', 'b', 'n',
- 'm', ',', '.', '/', '\0', '\0',
- '\0', '\0', '\0', ' ', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '7', '4', '1',
- '\0', '/', '8', '5', '2',
- '0', '*', '9', '6', '3',
- '.', '-', '+', '\0', '\n', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0'
-};
-
-static const int8_t HID_KEYBRD_ShiftKey[] = {
- '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')',
- '_', '+', '\0', '\0', '\0', 'Q', 'W', 'E', 'R', 'T', 'Y', 'U',
- 'I', 'O', 'P', '{', '}', '|', '\0', 'A', 'S', 'D', 'F', 'G',
- 'H', 'J', 'K', 'L', ':', '"', '\0', '\n', '\0', '\0', 'Z', 'X',
- 'C', 'V', 'B', 'N', 'M', '<', '>', '?', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0'
-};
-
-#else
-
-static const int8_t HID_KEYBRD_Key[] = {
- '\0', '`', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0',
- '-', '=', '\0', '\r', '\t', 'a', 'z', 'e', 'r', 't', 'y', 'u',
- 'i', 'o', 'p', '[', ']', '\\', '\0', 'q', 's', 'd', 'f', 'g',
- 'h', 'j', 'k', 'l', 'm', '\0', '\0', '\n', '\0', '\0', 'w', 'x',
- 'c', 'v', 'b', 'n', ',', ';', ':', '!', '\0', '\0', '\0', '\0',
- '\0', ' ', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '7', '4', '1','\0', '/',
- '8', '5', '2', '0', '*', '9', '6', '3', '.', '-', '+', '\0',
- '\n', '\0', '\0', '\0', '\0', '\0', '\0','\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0'
-};
-
-static const int8_t HID_KEYBRD_ShiftKey[] = {
- '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_',
- '+', '\0', '\0', '\0', 'A', 'Z', 'E', 'R', 'T', 'Y', 'U', 'I', 'O',
- 'P', '{', '}', '*', '\0', 'Q', 'S', 'D', 'F', 'G', 'H', 'J', 'K',
- 'L', 'M', '%', '\0', '\n', '\0', '\0', 'W', 'X', 'C', 'V', 'B', 'N',
- '?', '.', '/', '\0', '\0', '\0','\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0'
-};
-#endif
-
-/**
-* @}
-*/
-
-
-/** @defgroup USBH_HID_KEYBD_Private_Functions
-* @{
-*/
-
-
-/**
-* @brief KEYBRD_Init.
-* Initialize the keyboard function.
-* @param None
-* @retval None
-*/
-static void KEYBRD_Init (void)
-{
- /* Call User Init*/
- USR_KEYBRD_Init();
-}
-
-/**
-* @brief KEYBRD_ProcessData.
-* The function is to decode the pressed keys.
-* @param pbuf : Pointer to the HID IN report data buffer
-* @retval None
-*/
-
-static void KEYBRD_Decode(uint8_t *pbuf)
-{
- static uint8_t shift;
- static uint8_t keys[KBR_MAX_NBR_PRESSED];
- static uint8_t keys_new[KBR_MAX_NBR_PRESSED];
- static uint8_t keys_last[KBR_MAX_NBR_PRESSED];
- static uint8_t key_newest;
- static uint8_t nbr_keys;
- static uint8_t nbr_keys_new;
- static uint8_t nbr_keys_last;
- uint8_t ix;
- uint8_t jx;
- uint8_t error;
- uint8_t output;
-
- nbr_keys = 0;
- nbr_keys_new = 0;
- nbr_keys_last = 0;
- key_newest = 0x00;
-
-
- /* Check if Shift key is pressed */
- if ((pbuf[0] == KBD_LEFT_SHIFT) || (pbuf[0] == KBD_RIGHT_SHIFT)) {
- shift = TRUE;
- } else {
- shift = FALSE;
- }
-
- error = FALSE;
-
- /* Check for the value of pressed key */
- for (ix = 2; ix < 2 + KBR_MAX_NBR_PRESSED; ix++) {
- if ((pbuf[ix] == 0x01) ||
- (pbuf[ix] == 0x02) ||
- (pbuf[ix] == 0x03)) {
- error = TRUE;
- }
- }
-
- if (error == TRUE) {
- return;
- }
-
- nbr_keys = 0;
- nbr_keys_new = 0;
- for (ix = 2; ix < 2 + KBR_MAX_NBR_PRESSED; ix++) {
- if (pbuf[ix] != 0) {
- keys[nbr_keys] = pbuf[ix];
- nbr_keys++;
- for (jx = 0; jx < nbr_keys_last; jx++) {
- if (pbuf[ix] == keys_last[jx]) {
- break;
- }
- }
-
- if (jx == nbr_keys_last) {
- keys_new[nbr_keys_new] = pbuf[ix];
- nbr_keys_new++;
- }
- }
- }
-
- if (nbr_keys_new == 1) {
- key_newest = keys_new[0];
-
- if (shift == TRUE) {
- output = HID_KEYBRD_ShiftKey[HID_KEYBRD_Codes[key_newest]];
- } else {
- output = HID_KEYBRD_Key[HID_KEYBRD_Codes[key_newest]];
- }
-
- /* call user process handle */
- USR_KEYBRD_ProcessData(output);
- } else {
- key_newest = 0x00;
- }
-
-
- nbr_keys_last = nbr_keys;
- for (ix = 0; ix < KBR_MAX_NBR_PRESSED; ix++) {
- keys_last[ix] = keys[ix];
- }
-}
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_hid_mouse.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief This file is the application layer for USB Host HID Mouse Handling.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_hid_mouse.h"
-
-
-/** @addtogroup USBH_LIB
- * @{
- */
-
-/** @addtogroup USBH_CLASS
- * @{
- */
-
-/** @addtogroup USBH_HID_CLASS
- * @{
- */
-
-/** @defgroup USBH_HID_MOUSE
- * @brief This file includes HID Layer Handlers for USB Host HID class.
- * @{
- */
-
-/** @defgroup USBH_HID_MOUSE_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBH_HID_MOUSE_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBH_HID_MOUSE_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_HID_MOUSE_Private_FunctionPrototypes
- * @{
- */
-static void MOUSE_Init (void);
-static void MOUSE_Decode(uint8_t *data);
-/**
- * @}
- */
-
-
-/** @defgroup USBH_HID_MOUSE_Private_Variables
- * @{
- */
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined (__CC_ARM) /*!< ARM Compiler */
- __align(4)
- #elif defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #elif defined (__GNUC__) /*!< GNU Compiler */
- #pragma pack(4)
- #elif defined (__TASKING__) /*!< TASKING Compiler */
- __align(4)
- #endif /* __CC_ARM */
-#endif
-
-
-HID_MOUSE_Data_TypeDef HID_MOUSE_Data;
-HID_cb_TypeDef HID_MOUSE_cb =
-{
- MOUSE_Init,
- MOUSE_Decode,
-};
-/**
- * @}
- */
-
-
-/** @defgroup USBH_HID_MOUSE_Private_Functions
- * @{
- */
-
-/**
-* @brief MOUSE_Init
-* Init Mouse State.
-* @param None
-* @retval None
-*/
-static void MOUSE_Init ( void)
-{
- /* Call User Init*/
- USR_MOUSE_Init();
-}
-
-/**
-* @brief MOUSE_Decode
-* Decode Mouse data
-* @param data : Pointer to Mouse HID data buffer
-* @retval None
-*/
-static void MOUSE_Decode(uint8_t *data)
-{
- HID_MOUSE_Data.button = data[0];
-
- HID_MOUSE_Data.x = data[1];
- HID_MOUSE_Data.y = data[2];
-
- USR_MOUSE_ProcessData(&HID_MOUSE_Data);
-
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_msc_bot.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Header file for usbh_msc_bot.c
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive ----------------------------------------------*/
-#ifndef __USBH_MSC_BOT_H__
-#define __USBH_MSC_BOT_H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_stdreq.h"
-
-
-/** @addtogroup USBH_LIB
- * @{
- */
-
-/** @addtogroup USBH_CLASS
- * @{
- */
-
-/** @addtogroup USBH_MSC_CLASS
- * @{
- */
-
-/** @defgroup USBH_MSC_BOT
- * @brief This file is the Header file for usbh_msc_core.c
- * @{
- */
-
-
-/** @defgroup USBH_MSC_BOT_Exported_Types
- * @{
- */
-
-typedef union _USBH_CBW_Block
-{
- struct __CBW
- {
- uint32_t CBWSignature;
- uint32_t CBWTag;
- uint32_t CBWTransferLength;
- uint8_t CBWFlags;
- uint8_t CBWLUN;
- uint8_t CBWLength;
- uint8_t CBWCB[16];
-}field;
- uint8_t CBWArray[31];
-}HostCBWPkt_TypeDef;
-
-typedef enum
-{
- USBH_MSC_BOT_INIT_STATE = 0,
- USBH_MSC_BOT_RESET,
- USBH_MSC_GET_MAX_LUN,
- USBH_MSC_TEST_UNIT_READY,
- USBH_MSC_READ_CAPACITY10,
- USBH_MSC_MODE_SENSE6,
- USBH_MSC_REQUEST_SENSE,
- USBH_MSC_BOT_USB_TRANSFERS,
- USBH_MSC_DEFAULT_APPLI_STATE,
- USBH_MSC_CTRL_ERROR_STATE,
- USBH_MSC_UNRECOVERED_STATE
-}
-MSCState;
-
-
-typedef struct _BOTXfer
-{
-uint8_t MSCState;
-uint8_t MSCStateBkp;
-uint8_t MSCStateCurrent;
-uint8_t CmdStateMachine;
-uint8_t BOTState;
-uint8_t BOTStateBkp;
-uint8_t* pRxTxBuff;
-uint16_t DataLength;
-uint8_t BOTXferErrorCount;
-uint8_t BOTXferStatus;
-} USBH_BOTXfer_TypeDef;
-
-
-typedef union _USBH_CSW_Block
-{
- struct __CSW
- {
- uint32_t CSWSignature;
- uint32_t CSWTag;
- uint32_t CSWDataResidue;
- uint8_t CSWStatus;
- }field;
- uint8_t CSWArray[13];
-}HostCSWPkt_TypeDef;
-
-/**
- * @}
- */
-
-
-
-/** @defgroup USBH_MSC_BOT_Exported_Defines
- * @{
- */
-#define USBH_MSC_SEND_CBW 1
-#define USBH_MSC_SENT_CBW 2
-#define USBH_MSC_BOT_DATAIN_STATE 3
-#define USBH_MSC_BOT_DATAOUT_STATE 4
-#define USBH_MSC_RECEIVE_CSW_STATE 5
-#define USBH_MSC_DECODE_CSW 6
-#define USBH_MSC_BOT_ERROR_IN 7
-#define USBH_MSC_BOT_ERROR_OUT 8
-
-
-#define USBH_MSC_BOT_CBW_SIGNATURE 0x43425355
-#define USBH_MSC_BOT_CBW_TAG 0x20304050
-#define USBH_MSC_BOT_CSW_SIGNATURE 0x53425355
-#define USBH_MSC_CSW_DATA_LENGTH 0x000D
-#define USBH_MSC_BOT_CBW_PACKET_LENGTH 31
-#define USBH_MSC_CSW_LENGTH 13
-#define USBH_MSC_CSW_MAX_LENGTH 63
-
-/* CSW Status Definitions */
-#define USBH_MSC_CSW_CMD_PASSED 0x00
-#define USBH_MSC_CSW_CMD_FAILED 0x01
-#define USBH_MSC_CSW_PHASE_ERROR 0x02
-
-#define USBH_MSC_SEND_CSW_DISABLE 0
-#define USBH_MSC_SEND_CSW_ENABLE 1
-
-#define USBH_MSC_DIR_IN 0
-#define USBH_MSC_DIR_OUT 1
-#define USBH_MSC_BOTH_DIR 2
-
-//#define USBH_MSC_PAGE_LENGTH 0x40
-#define USBH_MSC_PAGE_LENGTH 512
-
-
-#define CBW_CB_LENGTH 16
-#define CBW_LENGTH 10
-#define CBW_LENGTH_TEST_UNIT_READY 6
-
-#define USB_REQ_BOT_RESET 0xFF
-#define USB_REQ_GET_MAX_LUN 0xFE
-
-#define MAX_BULK_STALL_COUNT_LIMIT 0x04 /* If STALL is seen on Bulk
- Endpoint continously, this means
- that device and Host has phase error
- Hence a Reset is needed */
-
-/**
- * @}
- */
-
-/** @defgroup USBH_MSC_BOT_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_MSC_BOT_Exported_Variables
- * @{
- */
-extern USBH_BOTXfer_TypeDef USBH_MSC_BOTXferParam;
-extern HostCBWPkt_TypeDef USBH_MSC_CBWData;
-extern HostCSWPkt_TypeDef USBH_MSC_CSWData;
-/**
- * @}
- */
-
-/** @defgroup USBH_MSC_BOT_Exported_FunctionsPrototype
- * @{
- */
-void USBH_MSC_HandleBOTXfer(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost);
-uint8_t USBH_MSC_DecodeCSW(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost);
-void USBH_MSC_Init(USB_OTG_CORE_HANDLE *pdev);
-USBH_Status USBH_MSC_BOT_Abort(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t direction);
-/**
- * @}
- */
-
-#endif //__USBH_MSC_BOT_H__
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_msc_core.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief This file contains all the prototypes for the usbh_msc_core.c
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive ----------------------------------------------*/
-#ifndef __USBH_MSC_CORE_H
-#define __USBH_MSC_CORE_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_core.h"
-#include "usbh_stdreq.h"
-#include "usb_bsp.h"
-#include "usbh_ioreq.h"
-#include "usbh_hcs.h"
-#include "usbh_msc_core.h"
-#include "usbh_msc_scsi.h"
-#include "usbh_msc_bot.h"
-
-/** @addtogroup USBH_LIB
- * @{
- */
-
-/** @addtogroup USBH_CLASS
- * @{
- */
-
-/** @addtogroup USBH_MSC_CLASS
- * @{
- */
-
-/** @defgroup USBH_MSC_CORE
- * @brief This file is the Header file for usbh_msc_core.c
- * @{
- */
-
-
-/** @defgroup USBH_MSC_CORE_Exported_Types
- * @{
- */
-
-
-/* Structure for MSC process */
-typedef struct _MSC_Process
-{
- uint8_t hc_num_in;
- uint8_t hc_num_out;
- uint8_t MSBulkOutEp;
- uint8_t MSBulkInEp;
- uint16_t MSBulkInEpSize;
- uint16_t MSBulkOutEpSize;
- uint8_t buff[USBH_MSC_MPS_SIZE];
- uint8_t maxLun;
-}
-MSC_Machine_TypeDef;
-
-
-/**
- * @}
- */
-
-
-
-/** @defgroup USBH_MSC_CORE_Exported_Defines
- * @{
- */
-
-#define USB_REQ_BOT_RESET 0xFF
-#define USB_REQ_GET_MAX_LUN 0xFE
-
-
-/**
- * @}
- */
-
-/** @defgroup USBH_MSC_CORE_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_MSC_CORE_Exported_Variables
- * @{
- */
-extern USBH_Class_cb_TypeDef USBH_MSC_cb;
-extern MSC_Machine_TypeDef MSC_Machine;
-extern uint8_t MSCErrorCount;
-
-/**
- * @}
- */
-
-/** @defgroup USBH_MSC_CORE_Exported_FunctionsPrototype
- * @{
- */
-
-
-
-/**
- * @}
- */
-
-#endif /* __USBH_MSC_CORE_H */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
-
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_msc_scsi.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Header file for usbh_msc_scsi.c
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive ----------------------------------------------*/
-#ifndef __USBH_MSC_SCSI_H__
-#define __USBH_MSC_SCSI_H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_stdreq.h"
-
-
-/** @addtogroup USBH_LIB
- * @{
- */
-
-/** @addtogroup USBH_CLASS
- * @{
- */
-
-/** @addtogroup USBH_MSC_CLASS
- * @{
- */
-
-/** @defgroup USBH_MSC_SCSI
- * @brief This file is the Header file for usbh_msc_scsi.c
- * @{
- */
-
-
-/** @defgroup USBH_MSC_SCSI_Exported_Types
- * @{
- */
-typedef enum {
- USBH_MSC_OK = 0,
- USBH_MSC_FAIL = 1,
- USBH_MSC_PHASE_ERROR = 2,
- USBH_MSC_BUSY = 3
-}USBH_MSC_Status_TypeDef;
-
-typedef enum {
- CMD_UNINITIALIZED_STATE =0,
- CMD_SEND_STATE,
- CMD_WAIT_STATUS
-} CMD_STATES_TypeDef;
-
-
-
-typedef struct __MassStorageParameter
-{
- uint32_t MSCapacity;
- uint32_t MSSenseKey;
- uint16_t MSPageLength;
- uint8_t MSBulkOutEp;
- uint8_t MSBulkInEp;
- uint8_t MSWriteProtect;
-} MassStorageParameter_TypeDef;
-/**
- * @}
- */
-
-
-
-/** @defgroup USBH_MSC_SCSI_Exported_Defines
- * @{
- */
-
-
-
-#define OPCODE_TEST_UNIT_READY 0X00
-#define OPCODE_READ_CAPACITY10 0x25
-#define OPCODE_MODE_SENSE6 0x1A
-#define OPCODE_READ10 0x28
-#define OPCODE_WRITE10 0x2A
-#define OPCODE_REQUEST_SENSE 0x03
-
-#define DESC_REQUEST_SENSE 0X00
-#define ALLOCATION_LENGTH_REQUEST_SENSE 63
-#define XFER_LEN_READ_CAPACITY10 8
-#define XFER_LEN_MODE_SENSE6 63
-
-#define MASK_MODE_SENSE_WRITE_PROTECT 0x80
-#define MODE_SENSE_PAGE_CONTROL_FIELD 0x00
-#define MODE_SENSE_PAGE_CODE 0x3F
-#define DISK_WRITE_PROTECTED 0x01
-/**
- * @}
- */
-
-/** @defgroup USBH_MSC_SCSI_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup _Exported_Variables
- * @{
- */
-extern MassStorageParameter_TypeDef USBH_MSC_Param;
-/**
- * @}
- */
-
-/** @defgroup USBH_MSC_SCSI_Exported_FunctionsPrototype
- * @{
- */
-uint8_t USBH_MSC_TestUnitReady(USB_OTG_CORE_HANDLE *pdev);
-uint8_t USBH_MSC_ReadCapacity10(USB_OTG_CORE_HANDLE *pdev);
-uint8_t USBH_MSC_ModeSense6(USB_OTG_CORE_HANDLE *pdev);
-uint8_t USBH_MSC_RequestSense(USB_OTG_CORE_HANDLE *pdev);
-uint8_t USBH_MSC_Write10(USB_OTG_CORE_HANDLE *pdev,
- uint8_t *,
- uint32_t ,
- uint32_t );
-uint8_t USBH_MSC_Read10(USB_OTG_CORE_HANDLE *pdev,
- uint8_t *,
- uint32_t ,
- uint32_t );
-void USBH_MSC_StateMachine(USB_OTG_CORE_HANDLE *pdev);
-
-/**
- * @}
- */
-
-#endif //__USBH_MSC_SCSI_H__
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_msc_bot.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief This file includes the mass storage related functions
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_msc_core.h"
-#include "usbh_msc_scsi.h"
-#include "usbh_msc_bot.h"
-#include "usbh_ioreq.h"
-#include "usbh_def.h"
-#include "usb_hcd_int.h"
-
-
-/** @addtogroup USBH_LIB
-* @{
-*/
-
-/** @addtogroup USBH_CLASS
-* @{
-*/
-
-/** @addtogroup USBH_MSC_CLASS
-* @{
-*/
-
-/** @defgroup USBH_MSC_BOT
-* @brief This file includes the mass storage related functions
-* @{
-*/
-
-
-/** @defgroup USBH_MSC_BOT_Private_TypesDefinitions
-* @{
-*/
-/**
-* @}
-*/
-
-/** @defgroup USBH_MSC_BOT_Private_Defines
-* @{
-*/
-/**
-* @}
-*/
-
-/** @defgroup USBH_MSC_BOT_Private_Macros
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USBH_MSC_BOT_Private_Variables
-* @{
-*/
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN HostCBWPkt_TypeDef USBH_MSC_CBWData __ALIGN_END ;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN HostCSWPkt_TypeDef USBH_MSC_CSWData __ALIGN_END ;
-
-
-static uint32_t BOTStallErrorCount; /* Keeps count of STALL Error Cases*/
-
-/**
-* @}
-*/
-
-
-/** @defgroup USBH_MSC_BOT_Private_FunctionPrototypes
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USBH_MSC_BOT_Exported_Variables
-* @{
-*/
-USBH_BOTXfer_TypeDef USBH_MSC_BOTXferParam;
-/**
-* @}
-*/
-
-
-/** @defgroup USBH_MSC_BOT_Private_Functions
-* @{
-*/
-
-
-/**
-* @brief USBH_MSC_Init
-* Initializes the mass storage parameters
-* @param None
-* @retval None
-*/
-void USBH_MSC_Init(USB_OTG_CORE_HANDLE *pdev )
-{
- if(HCD_IsDeviceConnected(pdev))
- {
- USBH_MSC_CBWData.field.CBWSignature = USBH_MSC_BOT_CBW_SIGNATURE;
- USBH_MSC_CBWData.field.CBWTag = USBH_MSC_BOT_CBW_TAG;
- USBH_MSC_CBWData.field.CBWLUN = 0; /*Only one LUN is supported*/
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- }
-
- BOTStallErrorCount = 0;
- MSCErrorCount = 0;
-}
-
-/**
-* @brief USBH_MSC_HandleBOTXfer
-* This function manages the different states of BOT transfer and
-* updates the status to upper layer.
-* @param None
-* @retval None
-*
-*/
-void USBH_MSC_HandleBOTXfer (USB_OTG_CORE_HANDLE *pdev ,USBH_HOST *phost)
-{
- uint8_t xferDirection, index;
- static uint32_t remainingDataLength;
- static uint8_t *datapointer;
- static uint8_t error_direction;
- USBH_Status status;
-
- URB_STATE URB_Status = URB_IDLE;
-
- if(HCD_IsDeviceConnected(pdev))
- {
-
- switch (USBH_MSC_BOTXferParam.BOTState)
- {
- case USBH_MSC_SEND_CBW:
- /* send CBW */
- USBH_BulkSendData (pdev,
- &USBH_MSC_CBWData.CBWArray[0],
- USBH_MSC_BOT_CBW_PACKET_LENGTH ,
- MSC_Machine.hc_num_out);
-
- USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_SEND_CBW;
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SENT_CBW;
-
- break;
-
- case USBH_MSC_SENT_CBW:
- URB_Status = HCD_GetURB_State(pdev , MSC_Machine.hc_num_out);
-
- if(URB_Status == URB_DONE)
- {
- BOTStallErrorCount = 0;
- USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_SENT_CBW;
-
- /* If the CBW Pkt is sent successful, then change the state */
- xferDirection = (USBH_MSC_CBWData.field.CBWFlags & USB_REQ_DIR_MASK);
-
- if ( USBH_MSC_CBWData.field.CBWTransferLength != 0 )
- {
- remainingDataLength = USBH_MSC_CBWData.field.CBWTransferLength ;
- datapointer = USBH_MSC_BOTXferParam.pRxTxBuff;
-
- /* If there is Data Transfer Stage */
- if (xferDirection == USB_D2H)
- {
- /* Data Direction is IN */
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_DATAIN_STATE;
- }
- else
- {
- /* Data Direction is OUT */
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_DATAOUT_STATE;
- }
- }
-
- else
- {/* If there is NO Data Transfer Stage */
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_RECEIVE_CSW_STATE;
- }
-
- }
- else if(URB_Status == URB_NOTREADY)
- {
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp;
- }
- else if(URB_Status == URB_STALL)
- {
- error_direction = USBH_MSC_DIR_OUT;
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_ERROR_OUT;
- }
- break;
-
- case USBH_MSC_BOT_DATAIN_STATE:
-
- URB_Status = HCD_GetURB_State(pdev , MSC_Machine.hc_num_in);
- /* BOT DATA IN stage */
- if((URB_Status == URB_DONE) ||(USBH_MSC_BOTXferParam.BOTStateBkp != USBH_MSC_BOT_DATAIN_STATE))
- {
- BOTStallErrorCount = 0;
- USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_BOT_DATAIN_STATE;
-
- if(remainingDataLength > USBH_MSC_MPS_SIZE)
- {
- USBH_BulkReceiveData (pdev,
- datapointer,
- USBH_MSC_MPS_SIZE ,
- MSC_Machine.hc_num_in);
-
- remainingDataLength -= USBH_MSC_MPS_SIZE;
- datapointer = datapointer + USBH_MSC_MPS_SIZE;
- }
- else if ( remainingDataLength == 0)
- {
- /* If value was 0, and successful transfer, then change the state */
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_RECEIVE_CSW_STATE;
- }
- else
- {
- USBH_BulkReceiveData (pdev,
- datapointer,
- remainingDataLength ,
- MSC_Machine.hc_num_in);
-
- remainingDataLength = 0; /* Reset this value and keep in same state */
- }
- }
- else if(URB_Status == URB_STALL)
- {
- /* This is Data Stage STALL Condition */
-
- error_direction = USBH_MSC_DIR_IN;
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_ERROR_IN;
-
- /* Refer to USB Mass-Storage Class : BOT (www.usb.org)
- 6.7.2 Host expects to receive data from the device
- 3. On a STALL condition receiving data, then:
- The host shall accept the data received.
- The host shall clear the Bulk-In pipe.
- 4. The host shall attempt to receive a CSW.
-
- USBH_MSC_BOTXferParam.BOTStateBkp is used to switch to the Original
- state after the ClearFeature Command is issued.
- */
- USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_RECEIVE_CSW_STATE;
-
- }
- break;
-
-
- case USBH_MSC_BOT_DATAOUT_STATE:
- /* BOT DATA OUT stage */
- URB_Status = HCD_GetURB_State(pdev , MSC_Machine.hc_num_out);
- if(URB_Status == URB_DONE)
- {
- BOTStallErrorCount = 0;
- USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_BOT_DATAOUT_STATE;
- if(remainingDataLength > USBH_MSC_MPS_SIZE)
- {
- USBH_BulkSendData (pdev,
- datapointer,
- USBH_MSC_MPS_SIZE ,
- MSC_Machine.hc_num_out);
- datapointer = datapointer + USBH_MSC_MPS_SIZE;
- remainingDataLength = remainingDataLength - USBH_MSC_MPS_SIZE;
- }
- else if ( remainingDataLength == 0)
- {
- /* If value was 0, and successful transfer, then change the state */
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_RECEIVE_CSW_STATE;
- }
- else
- {
- USBH_BulkSendData (pdev,
- datapointer,
- remainingDataLength ,
- MSC_Machine.hc_num_out);
-
- remainingDataLength = 0; /* Reset this value and keep in same state */
- }
- }
-
- else if(URB_Status == URB_NOTREADY)
- {
- USBH_BulkSendData (pdev,
- (datapointer - USBH_MSC_MPS_SIZE),
- USBH_MSC_MPS_SIZE ,
- MSC_Machine.hc_num_out);
- }
-
- else if(URB_Status == URB_STALL)
- {
- error_direction = USBH_MSC_DIR_OUT;
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_ERROR_OUT;
-
- /* Refer to USB Mass-Storage Class : BOT (www.usb.org)
- 6.7.3 Ho - Host expects to send data to the device
- 3. On a STALL condition sending data, then:
- " The host shall clear the Bulk-Out pipe.
- 4. The host shall attempt to receive a CSW.
-
- The Above statement will do the clear the Bulk-Out pipe.
- The Below statement will help in Getting the CSW.
-
- USBH_MSC_BOTXferParam.BOTStateBkp is used to switch to the Original
- state after the ClearFeature Command is issued.
- */
-
- USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_RECEIVE_CSW_STATE;
-
- }
- break;
-
- case USBH_MSC_RECEIVE_CSW_STATE:
- /* BOT CSW stage */
- /* NOTE: We cannot reset the BOTStallErrorCount here as it may come from
- the clearFeature from previous command */
-
- USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_RECEIVE_CSW_STATE;
-
- USBH_MSC_BOTXferParam.pRxTxBuff = USBH_MSC_CSWData.CSWArray;
- USBH_MSC_BOTXferParam.DataLength = USBH_MSC_CSW_MAX_LENGTH;
-
- for(index = USBH_MSC_CSW_LENGTH; index != 0; index--)
- {
- USBH_MSC_CSWData.CSWArray[index] = 0;
- }
-
- USBH_MSC_CSWData.CSWArray[0] = 0;
-
- USBH_BulkReceiveData (pdev,
- USBH_MSC_BOTXferParam.pRxTxBuff,
- USBH_MSC_CSW_MAX_LENGTH ,
- MSC_Machine.hc_num_in);
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_DECODE_CSW;
-
- break;
-
- case USBH_MSC_DECODE_CSW:
- URB_Status = HCD_GetURB_State(pdev , MSC_Machine.hc_num_in);
- /* Decode CSW */
- if(URB_Status == URB_DONE)
- {
- BOTStallErrorCount = 0;
- USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_RECEIVE_CSW_STATE;
-
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOTXferParam.MSCStateCurrent ;
-
- USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_DecodeCSW(pdev , phost);
- }
- else if(URB_Status == URB_STALL)
- {
- error_direction = USBH_MSC_DIR_IN;
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_ERROR_IN;
- }
- break;
-
- case USBH_MSC_BOT_ERROR_IN:
- status = USBH_MSC_BOT_Abort(pdev, phost, USBH_MSC_DIR_IN);
- if (status == USBH_OK)
- {
- /* Check if the error was due in Both the directions */
- if (error_direction == USBH_MSC_BOTH_DIR)
- {/* If Both directions are Needed, Switch to OUT Direction */
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_ERROR_OUT;
- }
- else
- {
- /* Switch Back to the Original State, In many cases this will be
- USBH_MSC_RECEIVE_CSW_STATE state */
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp;
- }
- }
- else if (status == USBH_UNRECOVERED_ERROR)
- {
- /* This means that there is a STALL Error limit, Do Reset Recovery */
- USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_PHASE_ERROR;
- }
- break;
-
- case USBH_MSC_BOT_ERROR_OUT:
- status = USBH_MSC_BOT_Abort(pdev, phost, USBH_MSC_DIR_OUT);
- if ( status == USBH_OK)
- { /* Switch Back to the Original State */
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp;
- }
- else if (status == USBH_UNRECOVERED_ERROR)
- {
- /* This means that there is a STALL Error limit, Do Reset Recovery */
- USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_PHASE_ERROR;
- }
- break;
-
- default:
- break;
- }
- }
-}
-
-/**
-* @brief USBH_MSC_BOT_Abort
-* This function manages the different Error handling for STALL
-* @param direction : IN / OUT
-* @retval None
-*/
-USBH_Status USBH_MSC_BOT_Abort(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t direction)
-{
- USBH_Status status;
-
- status = USBH_BUSY;
-
- switch (direction)
- {
- case USBH_MSC_DIR_IN :
- /* send ClrFeture on Bulk IN endpoint */
- status = USBH_ClrFeature(pdev,
- phost,
- MSC_Machine.MSBulkInEp,
- MSC_Machine.hc_num_in);
-
- break;
-
- case USBH_MSC_DIR_OUT :
- /*send ClrFeature on Bulk OUT endpoint */
- status = USBH_ClrFeature(pdev,
- phost,
- MSC_Machine.MSBulkOutEp,
- MSC_Machine.hc_num_out);
- break;
-
- default:
- break;
- }
-
- BOTStallErrorCount++; /* Check Continous Number of times, STALL has Occured */
- if (BOTStallErrorCount > MAX_BULK_STALL_COUNT_LIMIT )
- {
- status = USBH_UNRECOVERED_ERROR;
- }
-
- return status;
-}
-
-/**
-* @brief USBH_MSC_DecodeCSW
-* This function decodes the CSW received by the device and updates the
-* same to upper layer.
-* @param None
-* @retval On success USBH_MSC_OK, on failure USBH_MSC_FAIL
-* @notes
-* Refer to USB Mass-Storage Class : BOT (www.usb.org)
-* 6.3.1 Valid CSW Conditions :
-* The host shall consider the CSW valid when:
-* 1. dCSWSignature is equal to 53425355h
-* 2. the CSW is 13 (Dh) bytes in length,
-* 3. dCSWTag matches the dCBWTag from the corresponding CBW.
-*/
-
-uint8_t USBH_MSC_DecodeCSW(USB_OTG_CORE_HANDLE *pdev , USBH_HOST *phost)
-{
- uint8_t status;
- uint32_t dataXferCount = 0;
- status = USBH_MSC_FAIL;
-
- if(HCD_IsDeviceConnected(pdev))
- {
- /*Checking if the transfer length is diffrent than 13*/
- dataXferCount = HCD_GetXferCnt(pdev, MSC_Machine.hc_num_in);
-
- if(dataXferCount != USBH_MSC_CSW_LENGTH)
- {
- /*(4) Hi > Dn (Host expects to receive data from the device,
- Device intends to transfer no data)
- (5) Hi > Di (Host expects to receive data from the device,
- Device intends to send data to the host)
- (9) Ho > Dn (Host expects to send data to the device,
- Device intends to transfer no data)
- (11) Ho > Do (Host expects to send data to the device,
- Device intends to receive data from the host)*/
-
-
- status = USBH_MSC_PHASE_ERROR;
- }
- else
- { /* CSW length is Correct */
-
- /* Check validity of the CSW Signature and CSWStatus */
- if(USBH_MSC_CSWData.field.CSWSignature == USBH_MSC_BOT_CSW_SIGNATURE)
- {/* Check Condition 1. dCSWSignature is equal to 53425355h */
-
- if(USBH_MSC_CSWData.field.CSWTag == USBH_MSC_CBWData.field.CBWTag)
- {
- /* Check Condition 3. dCSWTag matches the dCBWTag from the
- corresponding CBW */
-
- if(USBH_MSC_CSWData.field.CSWStatus == USBH_MSC_OK)
- {
- /* Refer to USB Mass-Storage Class : BOT (www.usb.org)
-
- Hn Host expects no data transfers
- Hi Host expects to receive data from the device
- Ho Host expects to send data to the device
-
- Dn Device intends to transfer no data
- Di Device intends to send data to the host
- Do Device intends to receive data from the host
-
- Section 6.7
- (1) Hn = Dn (Host expects no data transfers,
- Device intends to transfer no data)
- (6) Hi = Di (Host expects to receive data from the device,
- Device intends to send data to the host)
- (12) Ho = Do (Host expects to send data to the device,
- Device intends to receive data from the host)
-
- */
-
- status = USBH_MSC_OK;
- }
- else if(USBH_MSC_CSWData.field.CSWStatus == USBH_MSC_FAIL)
- {
- status = USBH_MSC_FAIL;
- }
-
- else if(USBH_MSC_CSWData.field.CSWStatus == USBH_MSC_PHASE_ERROR)
- {
- /* Refer to USB Mass-Storage Class : BOT (www.usb.org)
- Section 6.7
- (2) Hn < Di ( Host expects no data transfers,
- Device intends to send data to the host)
- (3) Hn < Do ( Host expects no data transfers,
- Device intends to receive data from the host)
- (7) Hi < Di ( Host expects to receive data from the device,
- Device intends to send data to the host)
- (8) Hi <> Do ( Host expects to receive data from the device,
- Device intends to receive data from the host)
- (10) Ho <> Di (Host expects to send data to the device,
- Di Device intends to send data to the host)
- (13) Ho < Do (Host expects to send data to the device,
- Device intends to receive data from the host)
- */
-
- status = USBH_MSC_PHASE_ERROR;
- }
- } /* CSW Tag Matching is Checked */
- } /* CSW Signature Correct Checking */
- else
- {
- /* If the CSW Signature is not valid, We sall return the Phase Error to
- Upper Layers for Reset Recovery */
-
- status = USBH_MSC_PHASE_ERROR;
- }
- } /* CSW Length Check*/
- }
-
- USBH_MSC_BOTXferParam.BOTXferStatus = status;
- return status;
-}
-
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
-
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_msc_core.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief This file implements the MSC class driver functions
- * ===================================================================
- * MSC Class Description
- * ===================================================================
- * This module manages the MSC class V1.0 following the "Universal
- * Serial Bus Mass Storage Class (MSC) Bulk-Only Transport (BOT) Version 1.0
- * Sep. 31, 1999".
- * This driver implements the following aspects of the specification:
- * - Bulk-Only Transport protocol
- * - Subclass : SCSI transparent command set (ref. SCSI Primary Commands - 3 (SPC-3))
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
-*/
-
-/* Includes ------------------------------------------------------------------*/
-
-#include "usbh_msc_core.h"
-#include "usbh_msc_scsi.h"
-#include "usbh_msc_bot.h"
-#include "usbh_core.h"
-
-
-/** @addtogroup USBH_LIB
- * @{
- */
-
-/** @addtogroup USBH_CLASS
- * @{
- */
-
-/** @addtogroup USBH_MSC_CLASS
- * @{
- */
-
-/** @defgroup USBH_MSC_CORE
- * @brief This file includes the mass storage related functions
- * @{
- */
-
-
-/** @defgroup USBH_MSC_CORE_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_MSC_CORE_Private_Defines
- * @{
- */
-#define USBH_MSC_ERROR_RETRY_LIMIT 10
-/**
- * @}
- */
-
-/** @defgroup USBH_MSC_CORE_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBH_MSC_CORE_Private_Variables
- * @{
- */
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN MSC_Machine_TypeDef MSC_Machine __ALIGN_END ;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN USB_Setup_TypeDef MSC_Setup __ALIGN_END ;
-uint8_t MSCErrorCount = 0;
-
-
-/**
- * @}
- */
-
-
-/** @defgroup USBH_MSC_CORE_Private_FunctionPrototypes
- * @{
- */
-
-static USBH_Status USBH_MSC_InterfaceInit (USB_OTG_CORE_HANDLE *pdev ,
- void *phost);
-
-static void USBH_MSC_InterfaceDeInit (USB_OTG_CORE_HANDLE *pdev ,
- void *phost);
-
-static USBH_Status USBH_MSC_Handle(USB_OTG_CORE_HANDLE *pdev ,
- void *phost);
-
-static USBH_Status USBH_MSC_ClassRequest(USB_OTG_CORE_HANDLE *pdev ,
- void *phost);
-
-static USBH_Status USBH_MSC_BOTReset(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost);
-static USBH_Status USBH_MSC_GETMaxLUN(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost);
-
-
-USBH_Class_cb_TypeDef USBH_MSC_cb =
-{
- USBH_MSC_InterfaceInit,
- USBH_MSC_InterfaceDeInit,
- USBH_MSC_ClassRequest,
- USBH_MSC_Handle,
-};
-
-void USBH_MSC_ErrorHandle(uint8_t status);
-
-/**
- * @}
- */
-
-
-/** @defgroup USBH_MSC_CORE_Exported_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBH_MSC_CORE_Private_Functions
- * @{
- */
-
-
-/**
- * @brief USBH_MSC_InterfaceInit
- * Interface initialization for MSC class.
- * @param pdev: Selected device
- * @param hdev: Selected device property
- * @retval USBH_Status : Status of class request handled.
- */
-static USBH_Status USBH_MSC_InterfaceInit ( USB_OTG_CORE_HANDLE *pdev,
- void *phost)
-{
- USBH_HOST *pphost = phost;
-
- if((pphost->device_prop.Itf_Desc[0].bInterfaceClass == MSC_CLASS) && \
- (pphost->device_prop.Itf_Desc[0].bInterfaceProtocol == MSC_PROTOCOL))
- {
- if(pphost->device_prop.Ep_Desc[0][0].bEndpointAddress & 0x80)
- {
- MSC_Machine.MSBulkInEp = (pphost->device_prop.Ep_Desc[0][0].bEndpointAddress);
- MSC_Machine.MSBulkInEpSize = pphost->device_prop.Ep_Desc[0][0].wMaxPacketSize;
- }
- else
- {
- MSC_Machine.MSBulkOutEp = (pphost->device_prop.Ep_Desc[0][0].bEndpointAddress);
- MSC_Machine.MSBulkOutEpSize = pphost->device_prop.Ep_Desc[0] [0].wMaxPacketSize;
- }
-
- if(pphost->device_prop.Ep_Desc[0][1].bEndpointAddress & 0x80)
- {
- MSC_Machine.MSBulkInEp = (pphost->device_prop.Ep_Desc[0][1].bEndpointAddress);
- MSC_Machine.MSBulkInEpSize = pphost->device_prop.Ep_Desc[0][1].wMaxPacketSize;
- }
- else
- {
- MSC_Machine.MSBulkOutEp = (pphost->device_prop.Ep_Desc[0][1].bEndpointAddress);
- MSC_Machine.MSBulkOutEpSize = pphost->device_prop.Ep_Desc[0][1].wMaxPacketSize;
- }
-
- MSC_Machine.hc_num_out = USBH_Alloc_Channel(pdev,
- MSC_Machine.MSBulkOutEp);
- MSC_Machine.hc_num_in = USBH_Alloc_Channel(pdev,
- MSC_Machine.MSBulkInEp);
-
- /* Open the new channels */
- USBH_Open_Channel (pdev,
- MSC_Machine.hc_num_out,
- pphost->device_prop.address,
- pphost->device_prop.speed,
- EP_TYPE_BULK,
- MSC_Machine.MSBulkOutEpSize);
-
- USBH_Open_Channel (pdev,
- MSC_Machine.hc_num_in,
- pphost->device_prop.address,
- pphost->device_prop.speed,
- EP_TYPE_BULK,
- MSC_Machine.MSBulkInEpSize);
-
- }
-
- else
- {
- pphost->usr_cb->USBH_USR_DeviceNotSupported();
- }
-
- return USBH_OK ;
-
-}
-
-
-/**
- * @brief USBH_MSC_InterfaceDeInit
- * De-Initialize interface by freeing host channels allocated to interface
- * @param pdev: Selected device
- * @param hdev: Selected device property
- * @retval None
- */
-void USBH_MSC_InterfaceDeInit ( USB_OTG_CORE_HANDLE *pdev,
- void *phost)
-{
- if ( MSC_Machine.hc_num_out)
- {
- USB_OTG_HC_Halt(pdev, MSC_Machine.hc_num_out);
- USBH_Free_Channel (pdev, MSC_Machine.hc_num_out);
- MSC_Machine.hc_num_out = 0; /* Reset the Channel as Free */
- }
-
- if ( MSC_Machine.hc_num_in)
- {
- USB_OTG_HC_Halt(pdev, MSC_Machine.hc_num_in);
- USBH_Free_Channel (pdev, MSC_Machine.hc_num_in);
- MSC_Machine.hc_num_in = 0; /* Reset the Channel as Free */
- }
-}
-
-/**
- * @brief USBH_MSC_ClassRequest
- * This function will only initialize the MSC state machine
- * @param pdev: Selected device
- * @param hdev: Selected device property
- * @retval USBH_Status : Status of class request handled.
- */
-
-static USBH_Status USBH_MSC_ClassRequest(USB_OTG_CORE_HANDLE *pdev ,
- void *phost)
-{
-
- USBH_Status status = USBH_OK ;
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_INIT_STATE;
-
- return status;
-}
-
-
-/**
- * @brief USBH_MSC_Handle
- * MSC state machine handler
- * @param pdev: Selected device
- * @param hdev: Selected device property
- * @retval USBH_Status
- */
-
-static USBH_Status USBH_MSC_Handle(USB_OTG_CORE_HANDLE *pdev ,
- void *phost)
-{
- USBH_HOST *pphost = phost;
-
- USBH_Status status = USBH_BUSY;
- uint8_t mscStatus = USBH_MSC_BUSY;
- uint8_t appliStatus = 0;
-
- static uint8_t maxLunExceed = FALSE;
-
-
- if(HCD_IsDeviceConnected(pdev))
- {
- switch(USBH_MSC_BOTXferParam.MSCState)
- {
- case USBH_MSC_BOT_INIT_STATE:
- USBH_MSC_Init(pdev);
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_RESET;
- break;
-
- case USBH_MSC_BOT_RESET:
- /* Issue BOT RESET request */
- status = USBH_MSC_BOTReset(pdev, phost);
- if(status == USBH_OK )
- {
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_GET_MAX_LUN;
- }
-
- if(status == USBH_NOT_SUPPORTED )
- {
- /* If the Command has failed, then we need to move to Next State, after
- STALL condition is cleared by Control-Transfer */
- USBH_MSC_BOTXferParam.MSCStateBkp = USBH_MSC_GET_MAX_LUN;
-
- /* a Clear Feature should be issued here */
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_CTRL_ERROR_STATE;
- }
- break;
-
- case USBH_MSC_GET_MAX_LUN:
- /* Issue GetMaxLUN request */
- status = USBH_MSC_GETMaxLUN(pdev, phost);
-
- if(status == USBH_OK )
- {
- MSC_Machine.maxLun = *(MSC_Machine.buff) ;
-
- /* If device has more that one logical unit then it is not supported */
- if((MSC_Machine.maxLun > 0) && (maxLunExceed == FALSE))
- {
- maxLunExceed = TRUE;
- pphost->usr_cb->USBH_USR_DeviceNotSupported();
-
- break;
- }
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_TEST_UNIT_READY;
- }
-
- if(status == USBH_NOT_SUPPORTED )
- {
- /* If the Command has failed, then we need to move to Next State, after
- STALL condition is cleared by Control-Transfer */
- USBH_MSC_BOTXferParam.MSCStateBkp = USBH_MSC_TEST_UNIT_READY;
-
- /* a Clear Feature should be issued here */
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_CTRL_ERROR_STATE;
- }
- break;
-
- case USBH_MSC_CTRL_ERROR_STATE:
- /* Issue Clearfeature request */
- status = USBH_ClrFeature(pdev,
- phost,
- 0x00,
- pphost->Control.hc_num_out);
- if(status == USBH_OK )
- {
- /* If GetMaxLun Request not support, assume Single LUN configuration */
- MSC_Machine.maxLun = 0;
-
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOTXferParam.MSCStateBkp;
- }
- break;
-
- case USBH_MSC_TEST_UNIT_READY:
- /* Issue SCSI command TestUnitReady */
- mscStatus = USBH_MSC_TestUnitReady(pdev);
-
- if(mscStatus == USBH_MSC_OK )
- {
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_READ_CAPACITY10;
- MSCErrorCount = 0;
- status = USBH_OK;
- }
- else
- {
- USBH_MSC_ErrorHandle(mscStatus);
- }
- break;
-
- case USBH_MSC_READ_CAPACITY10:
- /* Issue READ_CAPACITY10 SCSI command */
- mscStatus = USBH_MSC_ReadCapacity10(pdev);
- if(mscStatus == USBH_MSC_OK )
- {
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_MODE_SENSE6;
- MSCErrorCount = 0;
- status = USBH_OK;
- }
- else
- {
- USBH_MSC_ErrorHandle(mscStatus);
- }
- break;
-
- case USBH_MSC_MODE_SENSE6:
- /* Issue ModeSense6 SCSI command for detecting if device is write-protected */
- mscStatus = USBH_MSC_ModeSense6(pdev);
- if(mscStatus == USBH_MSC_OK )
- {
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_DEFAULT_APPLI_STATE;
- MSCErrorCount = 0;
- status = USBH_OK;
- }
- else
- {
- USBH_MSC_ErrorHandle(mscStatus);
- }
- break;
-
- case USBH_MSC_REQUEST_SENSE:
- /* Issue RequestSense SCSI command for retreiving error code */
- mscStatus = USBH_MSC_RequestSense(pdev);
- if(mscStatus == USBH_MSC_OK )
- {
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOTXferParam.MSCStateBkp;
- status = USBH_OK;
- }
- else
- {
- USBH_MSC_ErrorHandle(mscStatus);
- }
- break;
-
- case USBH_MSC_BOT_USB_TRANSFERS:
- /* Process the BOT state machine */
- USBH_MSC_HandleBOTXfer(pdev , phost);
- break;
-
- case USBH_MSC_DEFAULT_APPLI_STATE:
- /* Process Application callback for MSC */
- appliStatus = pphost->usr_cb->USBH_USR_MSC_Application();
- if(appliStatus == 0)
- {
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_DEFAULT_APPLI_STATE;
- }
- else if (appliStatus == 1)
- {
- /* De-init requested from application layer */
- status = USBH_APPLY_DEINIT;
- }
- break;
-
- case USBH_MSC_UNRECOVERED_STATE:
-
- status = USBH_UNRECOVERED_ERROR;
-
- break;
-
- default:
- break;
-
- }
- }
- return status;
-}
-
-
-
-/**
- * @brief USBH_MSC_BOTReset
- * This request is used to reset the mass storage device and its
- * associated interface. This class-specific request shall ready the
- * device for the next CBW from the host.
- * @param pdev: Selected device
- * @retval USBH_Status : Status of class request handled.
- */
-static USBH_Status USBH_MSC_BOTReset(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost)
-{
-
- phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_TYPE_CLASS | \
- USB_REQ_RECIPIENT_INTERFACE;
-
- phost->Control.setup.b.bRequest = USB_REQ_BOT_RESET;
- phost->Control.setup.b.wValue.w = 0;
- phost->Control.setup.b.wIndex.w = 0;
- phost->Control.setup.b.wLength.w = 0;
-
- return USBH_CtlReq(pdev, phost, 0 , 0 );
-}
-
-
-/**
- * @brief USBH_MSC_GETMaxLUN
- * This request is used to reset the mass storage device and its
- * associated interface. This class-specific request shall ready the
- * device for the next CBW from the host.
- * @param pdev: Selected device
- * @retval USBH_Status : USB ctl xfer status
- */
-static USBH_Status USBH_MSC_GETMaxLUN(USB_OTG_CORE_HANDLE *pdev , USBH_HOST *phost)
-{
- phost->Control.setup.b.bmRequestType = USB_D2H | USB_REQ_TYPE_CLASS | \
- USB_REQ_RECIPIENT_INTERFACE;
-
- phost->Control.setup.b.bRequest = USB_REQ_GET_MAX_LUN;
- phost->Control.setup.b.wValue.w = 0;
- phost->Control.setup.b.wIndex.w = 0;
- phost->Control.setup.b.wLength.w = 1;
-
- return USBH_CtlReq(pdev, phost, MSC_Machine.buff , 1 );
-}
-
-/**
- * @brief USBH_MSC_ErrorHandle
- * The function is for handling errors occuring during the MSC
- * state machine
- * @param status
- * @retval None
- */
-
-void USBH_MSC_ErrorHandle(uint8_t status)
-{
- if(status == USBH_MSC_FAIL)
- {
- MSCErrorCount++;
- if(MSCErrorCount < USBH_MSC_ERROR_RETRY_LIMIT)
- { /* Try MSC level error recovery, Issue the request Sense to get
- Drive error reason */
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_REQUEST_SENSE;
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- }
- else
- {
- /* Error trials exceeded the limit, go to unrecovered state */
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_UNRECOVERED_STATE;
- }
- }
- else if(status == USBH_MSC_PHASE_ERROR)
- {
- /* Phase error, Go to Unrecoovered state */
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_UNRECOVERED_STATE;
- }
- else if(status == USBH_MSC_BUSY)
- {
- /*No change in state*/
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-
-#include "usb_conf.h"
-#include "diskio.h"
-#include "usbh_msc_core.h"
-/*--------------------------------------------------------------------------
-
-Module Private Functions and Variables
-
----------------------------------------------------------------------------*/
-
-static volatile DSTATUS Stat = STA_NOINIT; /* Disk status */
-
-extern USB_OTG_CORE_HANDLE USB_OTG_Core;
-extern USBH_HOST USB_Host;
-
-/*-----------------------------------------------------------------------*/
-/* Initialize Disk Drive */
-/*-----------------------------------------------------------------------*/
-
-DSTATUS disk_initialize (
- BYTE drv /* Physical drive number (0) */
- )
-{
-
- if(HCD_IsDeviceConnected(&USB_OTG_Core))
- {
- Stat &= ~STA_NOINIT;
- }
-
- return Stat;
-
-
-}
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Get Disk Status */
-/*-----------------------------------------------------------------------*/
-
-DSTATUS disk_status (
- BYTE drv /* Physical drive number (0) */
- )
-{
- if (drv) return STA_NOINIT; /* Supports only single drive */
- return Stat;
-}
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Read Sector(s) */
-/*-----------------------------------------------------------------------*/
-
-DRESULT disk_read (
- BYTE drv, /* Physical drive number (0) */
- BYTE *buff, /* Pointer to the data buffer to store read data */
- DWORD sector, /* Start sector number (LBA) */
- BYTE count /* Sector count (1..255) */
- )
-{
- BYTE status = USBH_MSC_OK;
-
- if (drv || !count) return RES_PARERR;
- if (Stat & STA_NOINIT) return RES_NOTRDY;
-
-
- if(HCD_IsDeviceConnected(&USB_OTG_Core))
- {
-
- do
- {
- status = USBH_MSC_Read10(&USB_OTG_Core, buff,sector,512);
- USBH_MSC_HandleBOTXfer(&USB_OTG_Core ,&USB_Host);
-
- if(!HCD_IsDeviceConnected(&USB_OTG_Core))
- {
- return RES_ERROR;
- }
- }
- while(status == USBH_MSC_BUSY );
- }
-
- if(status == USBH_MSC_OK)
- return RES_OK;
- return RES_ERROR;
-
-}
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Write Sector(s) */
-/*-----------------------------------------------------------------------*/
-
-#if _READONLY == 0
-DRESULT disk_write (
- BYTE drv, /* Physical drive number (0) */
- const BYTE *buff, /* Pointer to the data to be written */
- DWORD sector, /* Start sector number (LBA) */
- BYTE count /* Sector count (1..255) */
- )
-{
- BYTE status = USBH_MSC_OK;
- if (drv || !count) return RES_PARERR;
- if (Stat & STA_NOINIT) return RES_NOTRDY;
- if (Stat & STA_PROTECT) return RES_WRPRT;
-
-
- if(HCD_IsDeviceConnected(&USB_OTG_Core))
- {
- do
- {
- status = USBH_MSC_Write10(&USB_OTG_Core,(BYTE*)buff,sector,512);
- USBH_MSC_HandleBOTXfer(&USB_OTG_Core, &USB_Host);
-
- if(!HCD_IsDeviceConnected(&USB_OTG_Core))
- {
- return RES_ERROR;
- }
- }
-
- while(status == USBH_MSC_BUSY );
-
- }
-
- if(status == USBH_MSC_OK)
- return RES_OK;
- return RES_ERROR;
-}
-#endif /* _READONLY == 0 */
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Miscellaneous Functions */
-/*-----------------------------------------------------------------------*/
-
-#if _USE_IOCTL != 0
-DRESULT disk_ioctl (
- BYTE drv, /* Physical drive number (0) */
- BYTE ctrl, /* Control code */
- void *buff /* Buffer to send/receive control data */
- )
-{
- DRESULT res = RES_OK;
-
- if (drv) return RES_PARERR;
-
- res = RES_ERROR;
-
- if (Stat & STA_NOINIT) return RES_NOTRDY;
-
- switch (ctrl) {
- case CTRL_SYNC : /* Make sure that no pending write process */
-
- res = RES_OK;
- break;
-
- case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */
-
- *(DWORD*)buff = (DWORD) USBH_MSC_Param.MSCapacity;
- res = RES_OK;
- break;
-
- case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */
- *(WORD*)buff = 512;
- res = RES_OK;
- break;
-
- case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */
-
- *(DWORD*)buff = 512;
-
- break;
-
-
- default:
- res = RES_PARERR;
- }
-
-
-
- return res;
-}
-#endif /* _USE_IOCTL != 0 */
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_msc_scsi.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief This file implements the SCSI commands
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_msc_core.h"
-#include "usbh_msc_scsi.h"
-#include "usbh_msc_bot.h"
-#include "usbh_ioreq.h"
-#include "usbh_def.h"
-
-
-/** @addtogroup USBH_LIB
- * @{
- */
-
-/** @addtogroup USBH_CLASS
- * @{
- */
-
-/** @addtogroup USBH_MSC_CLASS
- * @{
- */
-
-/** @defgroup USBH_MSC_SCSI
- * @brief This file includes the mass storage related functions
- * @{
- */
-
-
-/** @defgroup USBH_MSC_SCSI_Private_TypesDefinitions
- * @{
- */
-
-MassStorageParameter_TypeDef USBH_MSC_Param;
-/**
- * @}
- */
-
-/** @defgroup USBH_MSC_SCSI_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_MSC_SCSI_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBH_MSC_SCSI_Private_Variables
- * @{
- */
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN uint8_t USBH_DataInBuffer[512] __ALIGN_END ;
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
- #endif
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-__ALIGN_BEGIN uint8_t USBH_DataOutBuffer[512] __ALIGN_END ;
-/**
- * @}
- */
-
-
-/** @defgroup USBH_MSC_SCSI_Private_FunctionPrototypes
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBH_MSC_SCSI_Exported_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBH_MSC_SCSI_Private_Functions
- * @{
- */
-
-
-
-
-/**
- * @brief USBH_MSC_TestUnitReady
- * Issues 'Test unit ready' command to the device. Once the response
- * received, it updates the status to upper layer.
- * @param None
- * @retval Status
- */
-uint8_t USBH_MSC_TestUnitReady (USB_OTG_CORE_HANDLE *pdev)
-{
- uint8_t index;
- USBH_MSC_Status_TypeDef status = USBH_MSC_BUSY;
-
- if(HCD_IsDeviceConnected(pdev))
- {
- switch(USBH_MSC_BOTXferParam.CmdStateMachine)
- {
- case CMD_SEND_STATE:
- /*Prepare the CBW and relevent field*/
- USBH_MSC_CBWData.field.CBWTransferLength = 0; /* No Data Transfer */
- USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_OUT;
- USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH_TEST_UNIT_READY;
- USBH_MSC_BOTXferParam.pRxTxBuff = USBH_MSC_CSWData.CSWArray;
- USBH_MSC_BOTXferParam.DataLength = USBH_MSC_CSW_MAX_LENGTH;
- USBH_MSC_BOTXferParam.MSCStateCurrent = USBH_MSC_TEST_UNIT_READY;
-
- for(index = CBW_CB_LENGTH; index != 0; index--)
- {
- USBH_MSC_CBWData.field.CBWCB[index] = 0x00;
- }
-
- USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_TEST_UNIT_READY;
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SEND_CBW;
- /* Start the transfer, then let the state
- machine magage the other transactions */
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_USB_TRANSFERS;
- USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_BUSY;
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_WAIT_STATUS;
-
- status = USBH_MSC_BUSY;
- break;
-
- case CMD_WAIT_STATUS:
- if(USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_OK)
- {
- /* Commands successfully sent and Response Received */
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
-
- status = USBH_MSC_OK;
- }
- else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_FAIL )
- {
- /* Failure Mode */
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- status = USBH_MSC_FAIL;
- }
-
- else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_PHASE_ERROR )
- {
- /* Failure Mode */
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- status = USBH_MSC_PHASE_ERROR;
- }
- break;
-
- default:
- break;
- }
- }
- return status;
-}
-
-
-/**
- * @brief USBH_MSC_ReadCapacity10
- * Issue the read capacity command to the device. Once the response
- * received, it updates the status to upper layer
- * @param None
- * @retval Status
- */
-uint8_t USBH_MSC_ReadCapacity10(USB_OTG_CORE_HANDLE *pdev)
-{
- uint8_t index;
- USBH_MSC_Status_TypeDef status = USBH_MSC_BUSY;
-
- if(HCD_IsDeviceConnected(pdev))
- {
- switch(USBH_MSC_BOTXferParam.CmdStateMachine)
- {
- case CMD_SEND_STATE:
- /*Prepare the CBW and relevent field*/
- USBH_MSC_CBWData.field.CBWTransferLength = XFER_LEN_READ_CAPACITY10;
- USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN;
- USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH;
-
- USBH_MSC_BOTXferParam.pRxTxBuff = USBH_DataInBuffer;
- USBH_MSC_BOTXferParam.MSCStateCurrent = USBH_MSC_READ_CAPACITY10;
-
- for(index = CBW_CB_LENGTH; index != 0; index--)
- {
- USBH_MSC_CBWData.field.CBWCB[index] = 0x00;
- }
-
- USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_READ_CAPACITY10;
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SEND_CBW;
-
- /* Start the transfer, then let the state machine manage the other
- transactions */
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_USB_TRANSFERS;
- USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_BUSY;
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_WAIT_STATUS;
-
- status = USBH_MSC_BUSY;
- break;
-
- case CMD_WAIT_STATUS:
- if(USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_OK)
- {
- /*assign the capacity*/
- (((uint8_t*)&USBH_MSC_Param.MSCapacity )[3]) = USBH_DataInBuffer[0];
- (((uint8_t*)&USBH_MSC_Param.MSCapacity )[2]) = USBH_DataInBuffer[1];
- (((uint8_t*)&USBH_MSC_Param.MSCapacity )[1]) = USBH_DataInBuffer[2];
- (((uint8_t*)&USBH_MSC_Param.MSCapacity )[0]) = USBH_DataInBuffer[3];
-
- /*assign the page length*/
- (((uint8_t*)&USBH_MSC_Param.MSPageLength )[1]) = USBH_DataInBuffer[6];
- (((uint8_t*)&USBH_MSC_Param.MSPageLength )[0]) = USBH_DataInBuffer[7];
-
- /* Commands successfully sent and Response Received */
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- status = USBH_MSC_OK;
- }
- else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_FAIL )
- {
- /* Failure Mode */
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- status = USBH_MSC_FAIL;
- }
- else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_PHASE_ERROR )
- {
- /* Failure Mode */
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- status = USBH_MSC_PHASE_ERROR;
- }
- else
- {
- /* Wait for the Commands to get Completed */
- /* NO Change in state Machine */
- }
- break;
-
- default:
- break;
- }
- }
- return status;
-}
-
-
-/**
- * @brief USBH_MSC_ModeSense6
- * Issue the Mode Sense6 Command to the device. This function is used
- * for reading the WriteProtect Status of the Mass-Storage device.
- * @param None
- * @retval Status
- */
-uint8_t USBH_MSC_ModeSense6(USB_OTG_CORE_HANDLE *pdev)
-{
- uint8_t index;
- USBH_MSC_Status_TypeDef status = USBH_MSC_BUSY;
-
- if(HCD_IsDeviceConnected(pdev))
- {
- switch(USBH_MSC_BOTXferParam.CmdStateMachine)
- {
- case CMD_SEND_STATE:
- /*Prepare the CBW and relevent field*/
- USBH_MSC_CBWData.field.CBWTransferLength = XFER_LEN_MODE_SENSE6;
- USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN;
- USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH;
-
- USBH_MSC_BOTXferParam.pRxTxBuff = USBH_DataInBuffer;
- USBH_MSC_BOTXferParam.MSCStateCurrent = USBH_MSC_MODE_SENSE6;
-
- for(index = CBW_CB_LENGTH; index != 0; index--)
- {
- USBH_MSC_CBWData.field.CBWCB[index] = 0x00;
- }
-
- USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_MODE_SENSE6;
- USBH_MSC_CBWData.field.CBWCB[2] = MODE_SENSE_PAGE_CONTROL_FIELD | \
- MODE_SENSE_PAGE_CODE;
-
- USBH_MSC_CBWData.field.CBWCB[4] = XFER_LEN_MODE_SENSE6;
-
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SEND_CBW;
-
- /* Start the transfer, then let the state machine manage the other
- transactions */
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_USB_TRANSFERS;
- USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_BUSY;
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_WAIT_STATUS;
-
- status = USBH_MSC_BUSY;
- break;
-
- case CMD_WAIT_STATUS:
- if(USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_OK)
- {
- /* Assign the Write Protect status */
- /* If WriteProtect = 0, Writing is allowed
- If WriteProtect != 0, Disk is Write Protected */
- if ( USBH_DataInBuffer[2] & MASK_MODE_SENSE_WRITE_PROTECT)
- {
- USBH_MSC_Param.MSWriteProtect = DISK_WRITE_PROTECTED;
- }
- else
- {
- USBH_MSC_Param.MSWriteProtect = 0;
- }
-
- /* Commands successfully sent and Response Received */
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- status = USBH_MSC_OK;
- }
- else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_FAIL )
- {
- /* Failure Mode */
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- status = USBH_MSC_FAIL;
- }
- else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_PHASE_ERROR )
- {
- /* Failure Mode */
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- status = USBH_MSC_PHASE_ERROR;
- }
- else
- {
- /* Wait for the Commands to get Completed */
- /* NO Change in state Machine */
- }
- break;
-
- default:
- break;
- }
- }
- return status;
-}
-
-/**
- * @brief USBH_MSC_RequestSense
- * Issues the Request Sense command to the device. Once the response
- * received, it updates the status to upper layer
- * @param None
- * @retval Status
- */
-uint8_t USBH_MSC_RequestSense(USB_OTG_CORE_HANDLE *pdev)
-{
- USBH_MSC_Status_TypeDef status = USBH_MSC_BUSY;
-
- uint8_t index;
-
-
- if(HCD_IsDeviceConnected(pdev))
- {
- switch(USBH_MSC_BOTXferParam.CmdStateMachine)
- {
- case CMD_SEND_STATE:
-
- /*Prepare the CBW and relevent field*/
- USBH_MSC_CBWData.field.CBWTransferLength = \
- ALLOCATION_LENGTH_REQUEST_SENSE;
- USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN;
- USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH;
-
- USBH_MSC_BOTXferParam.pRxTxBuff = USBH_DataInBuffer;
- USBH_MSC_BOTXferParam.MSCStateBkp = USBH_MSC_BOTXferParam.MSCStateCurrent;
- USBH_MSC_BOTXferParam.MSCStateCurrent = USBH_MSC_REQUEST_SENSE;
-
-
- for(index = CBW_CB_LENGTH; index != 0; index--)
- {
- USBH_MSC_CBWData.field.CBWCB[index] = 0x00;
- }
-
- USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_REQUEST_SENSE;
- USBH_MSC_CBWData.field.CBWCB[1] = DESC_REQUEST_SENSE;
- USBH_MSC_CBWData.field.CBWCB[4] = ALLOCATION_LENGTH_REQUEST_SENSE;
-
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SEND_CBW;
- /* Start the transfer, then let the state machine magage
- the other transactions */
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_USB_TRANSFERS;
- USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_BUSY;
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_WAIT_STATUS;
-
- status = USBH_MSC_BUSY;
-
- break;
-
- case CMD_WAIT_STATUS:
-
- if(USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_OK)
- {
- /* Get Sense data*/
- (((uint8_t*)&USBH_MSC_Param.MSSenseKey )[3]) = USBH_DataInBuffer[0];
- (((uint8_t*)&USBH_MSC_Param.MSSenseKey )[2]) = USBH_DataInBuffer[1];
- (((uint8_t*)&USBH_MSC_Param.MSSenseKey )[1]) = USBH_DataInBuffer[2];
- (((uint8_t*)&USBH_MSC_Param.MSSenseKey )[0]) = USBH_DataInBuffer[3];
-
- /* Commands successfully sent and Response Received */
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- status = USBH_MSC_OK;
- }
- else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_FAIL )
- {
- /* Failure Mode */
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- status = USBH_MSC_FAIL;
- }
-
- else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_PHASE_ERROR )
- {
- /* Failure Mode */
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- status = USBH_MSC_PHASE_ERROR;
- }
-
- else
- {
- /* Wait for the Commands to get Completed */
- /* NO Change in state Machine */
- }
- break;
-
- default:
- break;
- }
- }
- return status;
-}
-
-
-/**
- * @brief USBH_MSC_Write10
- * Issue the write command to the device. Once the response received,
- * it updates the status to upper layer
- * @param dataBuffer : DataBuffer contains the data to write
- * @param address : Address to which the data will be written
- * @param nbOfbytes : NbOfbytes to be written
- * @retval Status
- */
-uint8_t USBH_MSC_Write10(USB_OTG_CORE_HANDLE *pdev,
- uint8_t *dataBuffer,
- uint32_t address,
- uint32_t nbOfbytes)
-{
- uint8_t index;
- USBH_MSC_Status_TypeDef status = USBH_MSC_BUSY;
- uint16_t nbOfPages;
-
- if(HCD_IsDeviceConnected(pdev))
- {
- switch(USBH_MSC_BOTXferParam.CmdStateMachine)
- {
- case CMD_SEND_STATE:
- USBH_MSC_CBWData.field.CBWTransferLength = nbOfbytes;
- USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_OUT;
- USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH;
- USBH_MSC_BOTXferParam.pRxTxBuff = dataBuffer;
-
-
- for(index = CBW_CB_LENGTH; index != 0; index--)
- {
- USBH_MSC_CBWData.field.CBWCB[index] = 0x00;
- }
-
- USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_WRITE10;
-
- /*logical block address*/
- USBH_MSC_CBWData.field.CBWCB[2] = (((uint8_t*)&address)[3]) ;
- USBH_MSC_CBWData.field.CBWCB[3] = (((uint8_t*)&address)[2]);
- USBH_MSC_CBWData.field.CBWCB[4] = (((uint8_t*)&address)[1]);
- USBH_MSC_CBWData.field.CBWCB[5] = (((uint8_t*)&address)[0]);
-
- /*USBH_MSC_PAGE_LENGTH = 512*/
- nbOfPages = nbOfbytes/ USBH_MSC_PAGE_LENGTH;
-
- /*Tranfer length */
- USBH_MSC_CBWData.field.CBWCB[7] = (((uint8_t *)&nbOfPages)[1]) ;
- USBH_MSC_CBWData.field.CBWCB[8] = (((uint8_t *)&nbOfPages)[0]) ;
-
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SEND_CBW;
- /* Start the transfer, then let the state machine
- magage the other transactions */
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_USB_TRANSFERS;
- USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_BUSY;
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_WAIT_STATUS;
-
- status = USBH_MSC_BUSY;
-
- break;
-
- case CMD_WAIT_STATUS:
- if(USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_OK)
- {
- /* Commands successfully sent and Response Received */
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- status = USBH_MSC_OK;
- }
- else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_FAIL )
- {
- /* Failure Mode */
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- }
-
- else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_PHASE_ERROR )
- {
- /* Failure Mode */
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- status = USBH_MSC_PHASE_ERROR;
- }
- break;
-
- default:
- break;
- }
- }
- return status;
-}
-
-/**
- * @brief USBH_MSC_Read10
- * Issue the read command to the device. Once the response received,
- * it updates the status to upper layer
- * @param dataBuffer : DataBuffer will contain the data to be read
- * @param address : Address from which the data will be read
- * @param nbOfbytes : NbOfbytes to be read
- * @retval Status
- */
-uint8_t USBH_MSC_Read10(USB_OTG_CORE_HANDLE *pdev,
- uint8_t *dataBuffer,
- uint32_t address,
- uint32_t nbOfbytes)
-{
- uint8_t index;
- static USBH_MSC_Status_TypeDef status = USBH_MSC_BUSY;
- uint16_t nbOfPages;
- status = USBH_MSC_BUSY;
-
- if(HCD_IsDeviceConnected(pdev))
- {
- switch(USBH_MSC_BOTXferParam.CmdStateMachine)
- {
- case CMD_SEND_STATE:
- /*Prepare the CBW and relevent field*/
- USBH_MSC_CBWData.field.CBWTransferLength = nbOfbytes;
- USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN;
- USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH;
-
- USBH_MSC_BOTXferParam.pRxTxBuff = dataBuffer;
-
- for(index = CBW_CB_LENGTH; index != 0; index--)
- {
- USBH_MSC_CBWData.field.CBWCB[index] = 0x00;
- }
-
- USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_READ10;
-
- /*logical block address*/
-
- USBH_MSC_CBWData.field.CBWCB[2] = (((uint8_t*)&address)[3]);
- USBH_MSC_CBWData.field.CBWCB[3] = (((uint8_t*)&address)[2]);
- USBH_MSC_CBWData.field.CBWCB[4] = (((uint8_t*)&address)[1]);
- USBH_MSC_CBWData.field.CBWCB[5] = (((uint8_t*)&address)[0]);
-
- /*USBH_MSC_PAGE_LENGTH = 512*/
- nbOfPages = nbOfbytes/ USBH_MSC_PAGE_LENGTH;
-
- /*Tranfer length */
- USBH_MSC_CBWData.field.CBWCB[7] = (((uint8_t *)&nbOfPages)[1]) ;
- USBH_MSC_CBWData.field.CBWCB[8] = (((uint8_t *)&nbOfPages)[0]) ;
-
-
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SEND_CBW;
- /* Start the transfer, then let the state machine
- magage the other transactions */
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_USB_TRANSFERS;
- USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_BUSY;
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_WAIT_STATUS;
-
- status = USBH_MSC_BUSY;
-
- break;
-
- case CMD_WAIT_STATUS:
-
- if((USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_OK) && \
- (HCD_IsDeviceConnected(pdev)))
- {
- /* Commands successfully sent and Response Received */
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- status = USBH_MSC_OK;
- }
- else if (( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_FAIL ) && \
- (HCD_IsDeviceConnected(pdev)))
- {
- /* Failure Mode */
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- }
-
- else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_PHASE_ERROR )
- {
- /* Failure Mode */
- USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE;
- status = USBH_MSC_PHASE_ERROR;
- }
- else
- {
- /* Wait for the Commands to get Completed */
- /* NO Change in state Machine */
- }
- break;
-
- default:
- break;
- }
- }
- return status;
-}
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
-
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_conf_template
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief General USB Host library configuration
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBH_CONF__H__
-#define __USBH_CONF__H__
-
-/* Includes ------------------------------------------------------------------*/
-/** @addtogroup USBH_OTG_DRIVER
- * @{
- */
-
-/** @defgroup USBH_CONF
- * @brief usb otg low level driver configuration file
- * @{
- */
-
-/** @defgroup USBH_CONF_Exported_Defines
- * @{
- */
-
-#define USBH_MAX_NUM_ENDPOINTS 2
-#define USBH_MAX_NUM_INTERFACES 2
-#ifdef USE_USB_OTG_FS
-#define USBH_MSC_MPS_SIZE 0x40
-#else
-#define USBH_MSC_MPS_SIZE 0x200
-#endif
-
-/**
- * @}
- */
-
-
-/** @defgroup USBH_CONF_Exported_Types
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBH_CONF_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_CONF_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_CONF_Exported_FunctionsPrototype
- * @{
- */
-/**
- * @}
- */
-
-
-#endif //__USBH_CONF__H__
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_core.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Header file for usbh_core.c
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive ----------------------------------------------*/
-#ifndef __USBH_CORE_H
-#define __USBH_CORE_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_hcd.h"
-#include "usbh_def.h"
-#include "usbh_conf.h"
-
-/** @addtogroup USBH_LIB
- * @{
- */
-
-/** @addtogroup USBH_LIB_CORE
-* @{
-*/
-
-/** @defgroup USBH_CORE
- * @brief This file is the Header file for usbh_core.c
- * @{
- */
-
-
-/** @defgroup USBH_CORE_Exported_Defines
- * @{
- */
-
-#define MSC_CLASS 0x08
-#define HID_CLASS 0x03
-#define MSC_PROTOCOL 0x50
-#define CBI_PROTOCOL 0x01
-
-
-#define USBH_MAX_ERROR_COUNT 2
-#define USBH_DEVICE_ADDRESS_DEFAULT 0
-#define USBH_DEVICE_ADDRESS 1
-
-
-/**
- * @}
- */
-
-
-/** @defgroup USBH_CORE_Exported_Types
- * @{
- */
-
-typedef enum {
- USBH_OK = 0,
- USBH_BUSY,
- USBH_FAIL,
- USBH_NOT_SUPPORTED,
- USBH_UNRECOVERED_ERROR,
- USBH_ERROR_SPEED_UNKNOWN,
- USBH_APPLY_DEINIT
-}USBH_Status;
-
-/* Following states are used for gState */
-typedef enum {
- HOST_IDLE =0,
- HOST_ISSUE_CORE_RESET,
- HOST_DEV_ATTACHED,
- HOST_DEV_DISCONNECTED,
- HOST_ISSUE_RESET,
- HOST_DETECT_DEVICE_SPEED,
- HOST_ENUMERATION,
- HOST_CLASS_REQUEST,
- HOST_CLASS,
- HOST_CTRL_XFER,
- HOST_USR_INPUT,
- HOST_SUSPENDED,
- HOST_ERROR_STATE
-}HOST_State;
-
-/* Following states are used for EnumerationState */
-typedef enum {
- ENUM_IDLE = 0,
- ENUM_GET_FULL_DEV_DESC,
- ENUM_SET_ADDR,
- ENUM_GET_CFG_DESC,
- ENUM_GET_FULL_CFG_DESC,
- ENUM_GET_MFC_STRING_DESC,
- ENUM_GET_PRODUCT_STRING_DESC,
- ENUM_GET_SERIALNUM_STRING_DESC,
- ENUM_SET_CONFIGURATION,
- ENUM_DEV_CONFIGURED
-} ENUM_State;
-
-
-
-/* Following states are used for CtrlXferStateMachine */
-typedef enum {
- CTRL_IDLE =0,
- CTRL_SETUP,
- CTRL_SETUP_WAIT,
- CTRL_DATA_IN,
- CTRL_DATA_IN_WAIT,
- CTRL_DATA_OUT,
- CTRL_DATA_OUT_WAIT,
- CTRL_STATUS_IN,
- CTRL_STATUS_IN_WAIT,
- CTRL_STATUS_OUT,
- CTRL_STATUS_OUT_WAIT,
- CTRL_ERROR
-}
-CTRL_State;
-
-typedef enum {
- USBH_USR_NO_RESP = 0,
- USBH_USR_RESP_OK = 1,
-}
-USBH_USR_Status;
-
-/* Following states are used for RequestState */
-typedef enum {
- CMD_IDLE =0,
- CMD_SEND,
- CMD_WAIT
-} CMD_State;
-
-
-
-typedef struct _Ctrl
-{
- uint8_t hc_num_in;
- uint8_t hc_num_out;
- uint8_t ep0size;
- uint8_t *buff;
- uint16_t length;
- uint8_t errorcount;
- uint16_t timer;
- CTRL_STATUS status;
- USB_Setup_TypeDef setup;
- CTRL_State state;
-
-} USBH_Ctrl_TypeDef;
-
-
-
-typedef struct _DeviceProp
-{
-
- uint8_t address;
- uint8_t speed;
- USBH_DevDesc_TypeDef Dev_Desc;
- USBH_CfgDesc_TypeDef Cfg_Desc;
- USBH_InterfaceDesc_TypeDef Itf_Desc[USBH_MAX_NUM_INTERFACES];
- USBH_EpDesc_TypeDef Ep_Desc[USBH_MAX_NUM_INTERFACES][USBH_MAX_NUM_ENDPOINTS];
- USBH_HIDDesc_TypeDef HID_Desc;
-
-}USBH_Device_TypeDef;
-
-typedef struct _USBH_Class_cb
-{
- USBH_Status (*Init)\
- (USB_OTG_CORE_HANDLE *pdev , void *phost);
- void (*DeInit)\
- (USB_OTG_CORE_HANDLE *pdev , void *phost);
- USBH_Status (*Requests)\
- (USB_OTG_CORE_HANDLE *pdev , void *phost);
- USBH_Status (*Machine)\
- (USB_OTG_CORE_HANDLE *pdev , void *phost);
-
-} USBH_Class_cb_TypeDef;
-
-
-typedef struct _USBH_USR_PROP
-{
- void (*Init)(void); /* HostLibInitialized */
- void (*DeInit)(void); /* HostLibInitialized */
- void (*DeviceAttached)(void); /* DeviceAttached */
- void (*ResetDevice)(void);
- void (*DeviceDisconnected)(void);
- void (*OverCurrentDetected)(void);
- void (*DeviceSpeedDetected)(uint8_t DeviceSpeed); /* DeviceSpeed */
- void (*DeviceDescAvailable)(void *); /* DeviceDescriptor is available */
- void (*DeviceAddressAssigned)(void); /* Address is assigned to USB Device */
- void (*ConfigurationDescAvailable)(USBH_CfgDesc_TypeDef *,
- USBH_InterfaceDesc_TypeDef *,
- USBH_EpDesc_TypeDef *);
- /* Configuration Descriptor available */
- void (*ManufacturerString)(void *); /* ManufacturerString*/
- void (*ProductString)(void *); /* ProductString*/
- void (*SerialNumString)(void *); /* SerialNubString*/
- void (*EnumerationDone)(void); /* Enumeration finished */
- USBH_USR_Status (*UserInput)(void);
- int (*USBH_USR_MSC_Application) (void);
- void (*USBH_USR_DeviceNotSupported)(void); /* Device is not supported*/
- void (*UnrecoveredError)(void);
-
-}
-USBH_Usr_cb_TypeDef;
-
-typedef struct _Host_TypeDef
-{
- HOST_State gState; /* Host State Machine Value */
- HOST_State gStateBkp; /* backup of previous State machine value */
- ENUM_State EnumState; /* Enumeration state Machine */
- CMD_State RequestState;
- USBH_Ctrl_TypeDef Control;
-
- USBH_Device_TypeDef device_prop;
-
- USBH_Class_cb_TypeDef *class_cb;
- USBH_Usr_cb_TypeDef *usr_cb;
-
-
-} USBH_HOST, *pUSBH_HOST;
-
-/**
- * @}
- */
-
-
-
-/** @defgroup USBH_CORE_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBH_CORE_Exported_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBH_CORE_Exported_FunctionsPrototype
- * @{
- */
-void USBH_Init(USB_OTG_CORE_HANDLE *pdev,
- USB_OTG_CORE_ID_TypeDef coreID,
- USBH_HOST *phost,
- USBH_Class_cb_TypeDef *class_cb,
- USBH_Usr_cb_TypeDef *usr_cb);
-
-USBH_Status USBH_DeInit(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost);
-void USBH_Process(USB_OTG_CORE_HANDLE *pdev ,
- USBH_HOST *phost);
-void USBH_ErrorHandle(USBH_HOST *phost,
- USBH_Status errType);
-
-/**
- * @}
- */
-
-#endif /* __USBH_CORE_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
-
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_def.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Definitions used in the USB host library
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-/** @addtogroup USBH_LIB
- * @{
- */
-
-/** @addtogroup USBH_LIB_CORE
-* @{
-*/
-
-/** @defgroup USBH_DEF
- * @brief This file is includes USB descriptors
- * @{
- */
-
-#ifndef USBH_DEF_H
-#define USBH_DEF_H
-
-#ifndef USBH_NULL
-#define USBH_NULL ((void *)0)
-#endif
-
-#ifndef FALSE
-#define FALSE 0
-#endif
-
-#ifndef TRUE
-#define TRUE 1
-#endif
-
-
-#define ValBit(VAR,POS) (VAR & (1 << POS))
-#define SetBit(VAR,POS) (VAR |= (1 << POS))
-#define ClrBit(VAR,POS) (VAR &= ((1 << POS)^255))
-
-#define LE16(addr) (((u16)(*((u8 *)(addr))))\
- + (((u16)(*(((u8 *)(addr)) + 1))) << 8))
-
-#define USB_LEN_DESC_HDR 0x02
-#define USB_LEN_DEV_DESC 0x12
-#define USB_LEN_CFG_DESC 0x09
-#define USB_LEN_IF_DESC 0x09
-#define USB_LEN_EP_DESC 0x07
-#define USB_LEN_OTG_DESC 0x03
-#define USB_LEN_SETUP_PKT 0x08
-
-/* bmRequestType :D7 Data Phase Transfer Direction */
-#define USB_REQ_DIR_MASK 0x80
-#define USB_H2D 0x00
-#define USB_D2H 0x80
-
-/* bmRequestType D6..5 Type */
-#define USB_REQ_TYPE_STANDARD 0x00
-#define USB_REQ_TYPE_CLASS 0x20
-#define USB_REQ_TYPE_VENDOR 0x40
-#define USB_REQ_TYPE_RESERVED 0x60
-
-/* bmRequestType D4..0 Recipient */
-#define USB_REQ_RECIPIENT_DEVICE 0x00
-#define USB_REQ_RECIPIENT_INTERFACE 0x01
-#define USB_REQ_RECIPIENT_ENDPOINT 0x02
-#define USB_REQ_RECIPIENT_OTHER 0x03
-
-/* Table 9-4. Standard Request Codes */
-/* bRequest , Value */
-#define USB_REQ_GET_STATUS 0x00
-#define USB_REQ_CLEAR_FEATURE 0x01
-#define USB_REQ_SET_FEATURE 0x03
-#define USB_REQ_SET_ADDRESS 0x05
-#define USB_REQ_GET_DESCRIPTOR 0x06
-#define USB_REQ_SET_DESCRIPTOR 0x07
-#define USB_REQ_GET_CONFIGURATION 0x08
-#define USB_REQ_SET_CONFIGURATION 0x09
-#define USB_REQ_GET_INTERFACE 0x0A
-#define USB_REQ_SET_INTERFACE 0x0B
-#define USB_REQ_SYNCH_FRAME 0x0C
-
-/* Table 9-5. Descriptor Types of USB Specifications */
-#define USB_DESC_TYPE_DEVICE 1
-#define USB_DESC_TYPE_CONFIGURATION 2
-#define USB_DESC_TYPE_STRING 3
-#define USB_DESC_TYPE_INTERFACE 4
-#define USB_DESC_TYPE_ENDPOINT 5
-#define USB_DESC_TYPE_DEVICE_QUALIFIER 6
-#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7
-#define USB_DESC_TYPE_INTERFACE_POWER 8
-#define USB_DESC_TYPE_HID 0x21
-#define USB_DESC_TYPE_HID_REPORT 0x22
-
-
-#define USB_DEVICE_DESC_SIZE 18
-#define USB_CONFIGURATION_DESC_SIZE 9
-#define USB_HID_DESC_SIZE 9
-#define USB_INTERFACE_DESC_SIZE 9
-#define USB_ENDPOINT_DESC_SIZE 7
-
-/* Descriptor Type and Descriptor Index */
-/* Use the following values when calling the function USBH_GetDescriptor */
-#define USB_DESC_DEVICE ((USB_DESC_TYPE_DEVICE << 8) & 0xFF00)
-#define USB_DESC_CONFIGURATION ((USB_DESC_TYPE_CONFIGURATION << 8) & 0xFF00)
-#define USB_DESC_STRING ((USB_DESC_TYPE_STRING << 8) & 0xFF00)
-#define USB_DESC_INTERFACE ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00)
-#define USB_DESC_ENDPOINT ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00)
-#define USB_DESC_DEVICE_QUALIFIER ((USB_DESC_TYPE_DEVICE_QUALIFIER << 8) & 0xFF00)
-#define USB_DESC_OTHER_SPEED_CONFIGURATION ((USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION << 8) & 0xFF00)
-#define USB_DESC_INTERFACE_POWER ((USB_DESC_TYPE_INTERFACE_POWER << 8) & 0xFF00)
-#define USB_DESC_HID_REPORT ((USB_DESC_TYPE_HID_REPORT << 8) & 0xFF00)
-#define USB_DESC_HID ((USB_DESC_TYPE_HID << 8) & 0xFF00)
-
-
-#define USB_EP_TYPE_CTRL 0x00
-#define USB_EP_TYPE_ISOC 0x01
-#define USB_EP_TYPE_BULK 0x02
-#define USB_EP_TYPE_INTR 0x03
-
-#define USB_EP_DIR_OUT 0x00
-#define USB_EP_DIR_IN 0x80
-#define USB_EP_DIR_MSK 0x80
-
-/* supported classes */
-#define USB_MSC_CLASS 0x08
-#define USB_HID_CLASS 0x03
-
-/* Interface Descriptor field values for HID Boot Protocol */
-#define HID_BOOT_CODE 0x01
-#define HID_KEYBRD_BOOT_CODE 0x01
-#define HID_MOUSE_BOOT_CODE 0x02
-
-/* As per USB specs 9.2.6.4 :Standard request with data request timeout: 5sec
- Standard request with no data stage timeout : 50ms */
-#define DATA_STAGE_TIMEOUT 5000
-#define NODATA_STAGE_TIMEOUT 50
-
-/**
- * @}
- */
-
-
-#define USBH_CONFIGURATION_DESCRIPTOR_SIZE (USB_CONFIGURATION_DESC_SIZE \
- + USB_INTERFACE_DESC_SIZE\
- + (USBH_MAX_NUM_ENDPOINTS * USB_ENDPOINT_DESC_SIZE))
-
-
-#define CONFIG_DESC_wTOTAL_LENGTH (ConfigurationDescriptorData.ConfigDescfield.\
- ConfigurationDescriptor.wTotalLength)
-
-
-/* This Union is copied from usb_core.h */
-typedef union
-{
- uint16_t w;
- struct BW
- {
- uint8_t msb;
- uint8_t lsb;
- }
- bw;
-}
-uint16_t_uint8_t;
-
-
-typedef union _USB_Setup
-{
- uint8_t d8[8];
-
- struct _SetupPkt_Struc
- {
- uint8_t bmRequestType;
- uint8_t bRequest;
- uint16_t_uint8_t wValue;
- uint16_t_uint8_t wIndex;
- uint16_t_uint8_t wLength;
- } b;
-}
-USB_Setup_TypeDef;
-
-typedef struct _DescHeader
-{
- uint8_t bLength;
- uint8_t bDescriptorType;
-}
-USBH_DescHeader_t;
-
-typedef struct _DeviceDescriptor
-{
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint16_t bcdUSB; /* USB Specification Number which device complies too */
- uint8_t bDeviceClass;
- uint8_t bDeviceSubClass;
- uint8_t bDeviceProtocol;
- /* If equal to Zero, each interface specifies its own class
- code if equal to 0xFF, the class code is vendor specified.
- Otherwise field is valid Class Code.*/
- uint8_t bMaxPacketSize;
- uint16_t idVendor; /* Vendor ID (Assigned by USB Org) */
- uint16_t idProduct; /* Product ID (Assigned by Manufacturer) */
- uint16_t bcdDevice; /* Device Release Number */
- uint8_t iManufacturer; /* Index of Manufacturer String Descriptor */
- uint8_t iProduct; /* Index of Product String Descriptor */
- uint8_t iSerialNumber; /* Index of Serial Number String Descriptor */
- uint8_t bNumConfigurations; /* Number of Possible Configurations */
-}
-USBH_DevDesc_TypeDef;
-
-
-typedef struct _ConfigurationDescriptor
-{
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint16_t wTotalLength; /* Total Length of Data Returned */
- uint8_t bNumInterfaces; /* Number of Interfaces */
- uint8_t bConfigurationValue; /* Value to use as an argument to select this configuration*/
- uint8_t iConfiguration; /*Index of String Descriptor Describing this configuration */
- uint8_t bmAttributes; /* D7 Bus Powered , D6 Self Powered, D5 Remote Wakeup , D4..0 Reserved (0)*/
- uint8_t bMaxPower; /*Maximum Power Consumption */
-}
-USBH_CfgDesc_TypeDef;
-
-
-typedef struct _HIDDescriptor
-{
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint16_t bcdHID; /* indicates what endpoint this descriptor is describing */
- uint8_t bCountryCode; /* specifies the transfer type. */
- uint8_t bNumDescriptors; /* specifies the transfer type. */
- uint8_t bReportDescriptorType; /* Maximum Packet Size this endpoint is capable of sending or receiving */
- uint16_t wItemLength; /* is used to specify the polling interval of certain transfers. */
-}
-USBH_HIDDesc_TypeDef;
-
-
-typedef struct _InterfaceDescriptor
-{
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint8_t bInterfaceNumber;
- uint8_t bAlternateSetting; /* Value used to select alternative setting */
- uint8_t bNumEndpoints; /* Number of Endpoints used for this interface */
- uint8_t bInterfaceClass; /* Class Code (Assigned by USB Org) */
- uint8_t bInterfaceSubClass; /* Subclass Code (Assigned by USB Org) */
- uint8_t bInterfaceProtocol; /* Protocol Code */
- uint8_t iInterface; /* Index of String Descriptor Describing this interface */
-
-}
-USBH_InterfaceDesc_TypeDef;
-
-
-typedef struct _EndpointDescriptor
-{
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint8_t bEndpointAddress; /* indicates what endpoint this descriptor is describing */
- uint8_t bmAttributes; /* specifies the transfer type. */
- uint16_t wMaxPacketSize; /* Maximum Packet Size this endpoint is capable of sending or receiving */
- uint8_t bInterval; /* is used to specify the polling interval of certain transfers. */
-}
-USBH_EpDesc_TypeDef;
-#endif
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_hcs.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Header file for usbh_hcs.c
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive ----------------------------------------------*/
-#ifndef __USBH_HCS_H
-#define __USBH_HCS_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_core.h"
-
-
-
-/** @addtogroup USBH_LIB
- * @{
- */
-
-/** @addtogroup USBH_LIB_CORE
-* @{
-*/
-
-/** @defgroup USBH_HCS
- * @brief This file is the header file for usbh_hcs.c
- * @{
- */
-
-/** @defgroup USBH_HCS_Exported_Defines
- * @{
- */
-#define HC_MAX 8
-
-#define HC_OK 0x0000
-#define HC_USED 0x8000
-#define HC_ERROR 0xFFFF
-#define HC_USED_MASK 0x7FFF
-/**
- * @}
- */
-
-/** @defgroup USBH_HCS_Exported_Types
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBH_HCS_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_HCS_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_HCS_Exported_FunctionsPrototype
- * @{
- */
-
-uint8_t USBH_Alloc_Channel(USB_OTG_CORE_HANDLE *pdev, uint8_t ep_addr);
-
-uint8_t USBH_Free_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t idx);
-
-uint8_t USBH_DeAllocate_AllChannel (USB_OTG_CORE_HANDLE *pdev);
-
-uint8_t USBH_Open_Channel (USB_OTG_CORE_HANDLE *pdev,
- uint8_t ch_num,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
-
-uint8_t USBH_Modify_Channel (USB_OTG_CORE_HANDLE *pdev,
- uint8_t hc_num,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
-/**
- * @}
- */
-
-
-
-#endif /* __USBH_HCS_H */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_ioreq.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Header file for usbh_ioreq.c
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive ----------------------------------------------*/
-#ifndef __USBH_IOREQ_H
-#define __USBH_IOREQ_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_conf.h"
-#include "usbh_core.h"
-#include "usbh_def.h"
-
-
-/** @addtogroup USBH_LIB
- * @{
- */
-
-/** @addtogroup USBH_LIB_CORE
-* @{
-*/
-
-/** @defgroup USBH_IOREQ
- * @brief This file is the header file for usbh_ioreq.c
- * @{
- */
-
-
-/** @defgroup USBH_IOREQ_Exported_Defines
- * @{
- */
-#define USBH_SETUP_PKT_SIZE 8
-#define USBH_EP0_EP_NUM 0
-#define USBH_MAX_PACKET_SIZE 0x40
-/**
- * @}
- */
-
-
-/** @defgroup USBH_IOREQ_Exported_Types
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBH_IOREQ_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_IOREQ_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_IOREQ_Exported_FunctionsPrototype
- * @{
- */
-USBH_Status USBH_CtlSendSetup ( USB_OTG_CORE_HANDLE *pdev,
- uint8_t *buff,
- uint8_t hc_num);
-
-USBH_Status USBH_CtlSendData ( USB_OTG_CORE_HANDLE *pdev,
- uint8_t *buff,
- uint8_t length,
- uint8_t hc_num);
-
-USBH_Status USBH_CtlReceiveData( USB_OTG_CORE_HANDLE *pdev,
- uint8_t *buff,
- uint8_t length,
- uint8_t hc_num);
-
-USBH_Status USBH_BulkReceiveData( USB_OTG_CORE_HANDLE *pdev,
- uint8_t *buff,
- uint16_t length,
- uint8_t hc_num);
-
-USBH_Status USBH_BulkSendData ( USB_OTG_CORE_HANDLE *pdev,
- uint8_t *buff,
- uint16_t length,
- uint8_t hc_num);
-
-USBH_Status USBH_InterruptReceiveData( USB_OTG_CORE_HANDLE *pdev,
- uint8_t *buff,
- uint8_t length,
- uint8_t hc_num);
-
-USBH_Status USBH_InterruptSendData( USB_OTG_CORE_HANDLE *pdev,
- uint8_t *buff,
- uint8_t length,
- uint8_t hc_num);
-
-USBH_Status USBH_CtlReq (USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t *buff,
- uint16_t length);
-/**
- * @}
- */
-
-#endif /* __USBH_IOREQ_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_stdreq.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Header file for usbh_stdreq.c
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive ----------------------------------------------*/
-#ifndef __USBH_STDREQ_H
-#define __USBH_STDREQ_H
-
-/* Includes ------------------------------------------------------------------*/
-
-#include "usb_conf.h"
-#include "usb_hcd.h"
-#include "usbh_core.h"
-#include "usbh_def.h"
-
-/** @addtogroup USBH_LIB
- * @{
- */
-
-/** @addtogroup USBH_LIB_CORE
-* @{
-*/
-
-/** @defgroup USBH_STDREQ
- * @brief This file is the
- * @{
- */
-
-
-/** @defgroup USBH_STDREQ_Exported_Defines
- * @{
- */
-/*Standard Feature Selector for clear feature command*/
-#define FEATURE_SELECTOR_ENDPOINT 0X00
-#define FEATURE_SELECTOR_DEVICE 0X01
-
-
-#define INTERFACE_DESC_TYPE 0x04
-#define ENDPOINT_DESC_TYPE 0x05
-#define INTERFACE_DESC_SIZE 0x09
-
-
-#define USBH_HID_CLASS 0x03
-
-/**
- * @}
- */
-
-
-/** @defgroup USBH_STDREQ_Exported_Types
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBH_STDREQ_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_STDREQ_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_STDREQ_Exported_FunctionsPrototype
- * @{
- */
-USBH_Status USBH_GetDescriptor(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t req_type,
- uint16_t value_idx,
- uint8_t* buff,
- uint16_t length );
-
-USBH_Status USBH_Get_DevDesc(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t length);
-
-USBH_Status USBH_Get_StringDesc(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t string_index,
- uint8_t *buff,
- uint16_t length);
-
-USBH_Status USBH_SetCfg(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint16_t configuration_value);
-
-USBH_Status USBH_Get_CfgDesc(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint16_t length);
-
-USBH_Status USBH_SetAddress(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t DeviceAddress);
-
-USBH_Status USBH_ClrFeature(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t ep_num, uint8_t hc_num);
-
-USBH_Status USBH_Issue_ClrFeature(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t ep_num);
-/**
- * @}
- */
-
-#endif /* __USBH_STDREQ_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_core.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief This file implements the functions for the core state machine process
- * the enumeration and the control transfer process
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-/* Includes ------------------------------------------------------------------*/
-
-#include "usbh_ioreq.h"
-#include "usb_bsp.h"
-#include "usbh_hcs.h"
-#include "usbh_stdreq.h"
-#include "usbh_core.h"
-
-
-/** @addtogroup USBH_LIB
- * @{
- */
-
-/** @addtogroup USBH_LIB_CORE
-* @{
-*/
-
-/** @defgroup USBH_CORE
- * @brief TThis file handles the basic enumaration when a device is connected
- * to the host.
- * @{
- */
-
-/** @defgroup USBH_CORE_Private_TypesDefinitions
- * @{
- */
-void USBH_Disconnect (void *pdev);
-void USBH_Connect (void *pdev);
-
-USB_OTG_hPort_TypeDef USBH_DeviceConnStatus_cb =
-{
- USBH_Disconnect,
- USBH_Connect,
- 0,
- 0,
- 0,
- 0
-};
-/**
- * @}
- */
-
-
-/** @defgroup USBH_CORE_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBH_CORE_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBH_CORE_Private_Variables
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBH_CORE_Private_FunctionPrototypes
- * @{
- */
-static USBH_Status USBH_HandleEnum(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost);
-USBH_Status USBH_HandleControl (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost);
-
-/**
- * @}
- */
-
-
-/** @defgroup USBH_CORE_Private_Functions
- * @{
- */
-
-
-/**
- * @brief USBH_Connect
- * USB Connect callback function from the Interrupt.
- * @param selected device
- * @retval none
- */
-void USBH_Connect (void *pdev)
-{
- USB_OTG_CORE_HANDLE *ppdev = pdev;
- ppdev->host.port_cb->ConnStatus = 1;
- ppdev->host.port_cb->ConnHandled = 0;
-}
-
-/**
- * @brief USBH_Disconnect
- * USB Disconnect callback function from the Interrupt.
- * @param selected device
- * @retval none
- */
-
-void USBH_Disconnect (void *pdev)
-{
-
- USB_OTG_CORE_HANDLE *ppdev = pdev;
-
- /* Make device Not connected flag true */
- ppdev->host.port_cb->DisconnStatus = 1;
- ppdev->host.port_cb->DisconnHandled = 0;
-}
-
-/**
- * @brief USBH_Init
- * Host hardware and stack initializations
- * @param class_cb: Class callback structure address
- * @param usr_cb: User callback structure address
- * @retval None
- */
-void USBH_Init(USB_OTG_CORE_HANDLE *pdev,
- USB_OTG_CORE_ID_TypeDef coreID,
- USBH_HOST *phost,
- USBH_Class_cb_TypeDef *class_cb,
- USBH_Usr_cb_TypeDef *usr_cb)
-{
-
- /* Hardware Init */
- USB_OTG_BSP_Init(pdev);
-
- /* configure GPIO pin used for switching VBUS power */
- USB_OTG_BSP_ConfigVBUS(0);
-
-
- /* Host de-initializations */
- USBH_DeInit(pdev, phost);
-
- /*Register class and user callbacks */
- phost->class_cb = class_cb;
- phost->usr_cb = usr_cb;
- pdev->host.port_cb = &USBH_DeviceConnStatus_cb;
-
- pdev->host.port_cb->ConnStatus = 0;
- pdev->host.port_cb->DisconnStatus = 0;
-
-
- /* Start the USB OTG core */
- HCD_Init(pdev , coreID);
-
- /* Upon Init call usr call back */
- phost->usr_cb->Init();
-
- /* Enable Interrupts */
- USB_OTG_BSP_EnableInterrupt(pdev);
-}
-
-/**
- * @brief USBH_DeInit
- * Re-Initialize Host
- * @param None
- * @retval status: USBH_Status
- */
-USBH_Status USBH_DeInit(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
-{
- /* Software Init */
-
- phost->gState = HOST_IDLE;
- phost->gStateBkp = HOST_IDLE;
- phost->EnumState = ENUM_IDLE;
- phost->RequestState = CMD_SEND;
-
- phost->Control.state = CTRL_SETUP;
- phost->Control.ep0size = USB_OTG_MAX_EP0_SIZE;
-
- phost->device_prop.address = USBH_DEVICE_ADDRESS_DEFAULT;
- phost->device_prop.speed = HPRT0_PRTSPD_FULL_SPEED;
-
- USBH_Free_Channel (pdev, phost->Control.hc_num_in);
- USBH_Free_Channel (pdev, phost->Control.hc_num_out);
- return USBH_OK;
-}
-
-/**
-* @brief USBH_Process
-* USB Host core main state machine process
-* @param None
-* @retval None
-*/
-void USBH_Process(USB_OTG_CORE_HANDLE *pdev , USBH_HOST *phost)
-{
- volatile USBH_Status status = USBH_FAIL;
-
- switch (phost->gState)
- {
- case HOST_ISSUE_CORE_RESET :
-
- if ( HCD_ResetPort(pdev) == 0)
- {
- phost->gState = HOST_IDLE;
- }
- break;
-
- case HOST_IDLE :
-
- if (HCD_IsDeviceConnected(pdev))
- {
- /* Wait for USB Connect Interrupt void USBH_ISR_Connected(void) */
- USBH_DeAllocate_AllChannel(pdev);
- phost->gState = HOST_DEV_ATTACHED;
- }
- break;
-
- case HOST_DEV_ATTACHED :
-
- phost->usr_cb->DeviceAttached();
- pdev->host.port_cb->DisconnStatus = 0;
- pdev->host.port_cb->ConnHandled = 1;
-
- phost->Control.hc_num_out = USBH_Alloc_Channel(pdev, 0x00);
- phost->Control.hc_num_in = USBH_Alloc_Channel(pdev, 0x80);
-
- /* Reset USB Device */
- if ( HCD_ResetPort(pdev) == 0)
- {
- phost->usr_cb->ResetDevice();
- /* Wait for USB USBH_ISR_PrtEnDisableChange()
- Host is Now ready to start the Enumeration
- */
-
- phost->device_prop.speed = HCD_GetCurrentSpeed(pdev);
-
- phost->gState = HOST_ENUMERATION;
- phost->usr_cb->DeviceSpeedDetected(phost->device_prop.speed);
-
- /* Open Control pipes */
- USBH_Open_Channel (pdev,
- phost->Control.hc_num_in,
- phost->device_prop.address,
- phost->device_prop.speed,
- EP_TYPE_CTRL,
- phost->Control.ep0size);
-
- /* Open Control pipes */
- USBH_Open_Channel (pdev,
- phost->Control.hc_num_out,
- phost->device_prop.address,
- phost->device_prop.speed,
- EP_TYPE_CTRL,
- phost->Control.ep0size);
- }
- break;
-
- case HOST_ENUMERATION:
- /* Check for enumeration status */
- if ( USBH_HandleEnum(pdev , phost) == USBH_OK)
- {
- /* The function shall return USBH_OK when full enumeration is complete */
-
- /* user callback for end of device basic enumeration */
- phost->usr_cb->EnumerationDone();
-
- phost->gState = HOST_USR_INPUT;
- }
- break;
-
- case HOST_USR_INPUT:
- /*The function should return user response true to move to class state */
- if ( phost->usr_cb->UserInput() == USBH_USR_RESP_OK)
- {
- if((phost->class_cb->Init(pdev, phost))\
- == USBH_OK)
- {
- phost->gState = HOST_CLASS_REQUEST;
- }
- }
- break;
-
- case HOST_CLASS_REQUEST:
- /* process class standard contol requests state machine */
- status = phost->class_cb->Requests(pdev, phost);
-
- if(status == USBH_OK)
- {
- phost->gState = HOST_CLASS;
- }
-
- else
- {
- USBH_ErrorHandle(phost, status);
- }
-
-
- break;
- case HOST_CLASS:
- /* process class state machine */
- status = phost->class_cb->Machine(pdev, phost);
- USBH_ErrorHandle(phost, status);
- break;
-
- case HOST_CTRL_XFER:
- /* process control transfer state machine */
- USBH_HandleControl(pdev, phost);
- break;
-
- case HOST_SUSPENDED:
- break;
-
- case HOST_ERROR_STATE:
- /* Re-Initilaize Host for new Enumeration */
- USBH_DeInit(pdev, phost);
- phost->usr_cb->DeInit();
- phost->class_cb->DeInit(pdev, &phost->device_prop);
- break;
-
- default :
- break;
- }
-
- /* check device disconnection event */
- if (!(HCD_IsDeviceConnected(pdev)) &&
- (pdev->host.port_cb->DisconnHandled == 0))
- {
- /* Manage User disconnect operations*/
- phost->usr_cb->DeviceDisconnected();
-
- pdev->host.port_cb->DisconnHandled = 1; /* Handle to avoid the Re-entry*/
-
- /* Re-Initilaize Host for new Enumeration */
- USBH_DeInit(pdev, phost);
- phost->usr_cb->DeInit();
- phost->class_cb->DeInit(pdev, &phost->device_prop);
- }
-}
-
-
-/**
- * @brief USBH_ErrorHandle
- * This function handles the Error on Host side.
- * @param errType : Type of Error or Busy/OK state
- * @retval None
- */
-void USBH_ErrorHandle(USBH_HOST *phost, USBH_Status errType)
-{
- /* Error unrecovered or not supported device speed */
- if ( (errType == USBH_ERROR_SPEED_UNKNOWN) ||
- (errType == USBH_UNRECOVERED_ERROR) )
- {
- phost->usr_cb->UnrecoveredError();
- phost->gState = HOST_ERROR_STATE;
- }
- /* USB host restart requested from application layer */
- else if(errType == USBH_APPLY_DEINIT)
- {
- phost->gState = HOST_ERROR_STATE;
- /* user callback for initalization */
- phost->usr_cb->Init();
- }
-}
-
-
-/**
- * @brief USBH_HandleEnum
- * This function includes the complete enumeration process
- * @param pdev: Selected device
- * @retval USBH_Status
- */
-static USBH_Status USBH_HandleEnum(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
-{
- USBH_Status Status = USBH_BUSY;
- uint8_t Local_Buffer[64];
-
- switch (phost->EnumState)
- {
- case ENUM_IDLE:
- /* Get Device Desc for only 1st 8 bytes : To get EP0 MaxPacketSize */
- if ( USBH_Get_DevDesc(pdev , phost, 8) == USBH_OK)
- {
- phost->Control.ep0size = phost->device_prop.Dev_Desc.bMaxPacketSize;
-
- /* Issue Reset */
- HCD_ResetPort(pdev);
- phost->EnumState = ENUM_GET_FULL_DEV_DESC;
-
- /* modify control channels configuration for MaxPacket size */
- USBH_Modify_Channel (pdev,
- phost->Control.hc_num_out,
- 0,
- 0,
- 0,
- phost->Control.ep0size);
-
- USBH_Modify_Channel (pdev,
- phost->Control.hc_num_in,
- 0,
- 0,
- 0,
- phost->Control.ep0size);
- }
- break;
-
- case ENUM_GET_FULL_DEV_DESC:
- /* Get FULL Device Desc */
- if ( USBH_Get_DevDesc(pdev, phost, USB_DEVICE_DESC_SIZE)\
- == USBH_OK)
- {
- /* user callback for device descriptor available */
- phost->usr_cb->DeviceDescAvailable(&phost->device_prop.Dev_Desc);
- phost->EnumState = ENUM_SET_ADDR;
- }
- break;
-
- case ENUM_SET_ADDR:
- /* set address */
- if ( USBH_SetAddress(pdev, phost, USBH_DEVICE_ADDRESS) == USBH_OK)
- {
- phost->device_prop.address = USBH_DEVICE_ADDRESS;
-
- /* user callback for device address assigned */
- phost->usr_cb->DeviceAddressAssigned();
- phost->EnumState = ENUM_GET_CFG_DESC;
-
- /* modify control channels to update device address */
- USBH_Modify_Channel (pdev,
- phost->Control.hc_num_in,
- phost->device_prop.address,
- 0,
- 0,
- 0);
-
- USBH_Modify_Channel (pdev,
- phost->Control.hc_num_out,
- phost->device_prop.address,
- 0,
- 0,
- 0);
- }
- break;
-
- case ENUM_GET_CFG_DESC:
- /* get standard configuration descriptor */
- if ( USBH_Get_CfgDesc(pdev,
- phost,
- USB_CONFIGURATION_DESC_SIZE) == USBH_OK)
- {
- phost->EnumState = ENUM_GET_FULL_CFG_DESC;
- }
- break;
-
- case ENUM_GET_FULL_CFG_DESC:
- /* get FULL config descriptor (config, interface, endpoints) */
- if (USBH_Get_CfgDesc(pdev,
- phost,
- phost->device_prop.Cfg_Desc.wTotalLength) == USBH_OK)
- {
- /* User callback for configuration descriptors available */
- phost->usr_cb->ConfigurationDescAvailable(&phost->device_prop.Cfg_Desc,
- phost->device_prop.Itf_Desc,
- phost->device_prop.Ep_Desc[0]);
-
- phost->EnumState = ENUM_GET_MFC_STRING_DESC;
- }
- break;
-
- case ENUM_GET_MFC_STRING_DESC:
- if (phost->device_prop.Dev_Desc.iManufacturer != 0)
- { /* Check that Manufacturer String is available */
-
- if ( USBH_Get_StringDesc(pdev,
- phost,
- phost->device_prop.Dev_Desc.iManufacturer,
- Local_Buffer ,
- 0xff) == USBH_OK)
- {
- /* User callback for Manufacturing string */
- phost->usr_cb->ManufacturerString(Local_Buffer);
- phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC;
- }
- }
- else
- {
- phost->usr_cb->ManufacturerString("N/A");
- phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC;
- }
- break;
-
- case ENUM_GET_PRODUCT_STRING_DESC:
- if (phost->device_prop.Dev_Desc.iProduct != 0)
- { /* Check that Product string is available */
- if ( USBH_Get_StringDesc(pdev,
- phost,
- phost->device_prop.Dev_Desc.iProduct,
- Local_Buffer,
- 0xff) == USBH_OK)
- {
- /* User callback for Product string */
- phost->usr_cb->ProductString(Local_Buffer);
- phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC;
- }
- }
- else
- {
- phost->usr_cb->ProductString("N/A");
- phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC;
- }
- break;
-
- case ENUM_GET_SERIALNUM_STRING_DESC:
- if (phost->device_prop.Dev_Desc.iSerialNumber != 0)
- { /* Check that Serial number string is available */
- if ( USBH_Get_StringDesc(pdev,
- phost,
- phost->device_prop.Dev_Desc.iSerialNumber,
- Local_Buffer,
- 0xff) == USBH_OK)
- {
- /* User callback for Serial number string */
- phost->usr_cb->SerialNumString(Local_Buffer);
- phost->EnumState = ENUM_SET_CONFIGURATION;
- }
- }
- else
- {
- phost->usr_cb->SerialNumString("N/A");
- phost->EnumState = ENUM_SET_CONFIGURATION;
- }
- break;
-
- case ENUM_SET_CONFIGURATION:
- /* set configuration (default config) */
- if (USBH_SetCfg(pdev,
- phost,
- phost->device_prop.Cfg_Desc.bConfigurationValue) == USBH_OK)
- {
- phost->EnumState = ENUM_DEV_CONFIGURED;
- }
- break;
-
-
- case ENUM_DEV_CONFIGURED:
- /* user callback for enumeration done */
- Status = USBH_OK;
- break;
-
- default:
- break;
- }
- return Status;
-}
-
-
-/**
- * @brief USBH_HandleControl
- * Handles the USB control transfer state machine
- * @param pdev: Selected device
- * @retval Status
- */
-USBH_Status USBH_HandleControl (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
-{
- uint8_t direction;
- static uint16_t timeout = 0;
- USBH_Status status = USBH_OK;
- URB_STATE URB_Status = URB_IDLE;
-
- phost->Control.status = CTRL_START;
-
-
- switch (phost->Control.state)
- {
- case CTRL_SETUP:
- /* send a SETUP packet */
- USBH_CtlSendSetup (pdev,
- phost->Control.setup.d8 ,
- phost->Control.hc_num_out);
- phost->Control.state = CTRL_SETUP_WAIT;
- break;
-
- case CTRL_SETUP_WAIT:
-
- URB_Status = HCD_GetURB_State(pdev , phost->Control.hc_num_out);
- /* case SETUP packet sent successfully */
- if(URB_Status == URB_DONE)
- {
- direction = (phost->Control.setup.b.bmRequestType & USB_REQ_DIR_MASK);
-
- /* check if there is a data stage */
- if (phost->Control.setup.b.wLength.w != 0 )
- {
- timeout = DATA_STAGE_TIMEOUT;
- if (direction == USB_D2H)
- {
- /* Data Direction is IN */
- phost->Control.state = CTRL_DATA_IN;
- }
- else
- {
- /* Data Direction is OUT */
- phost->Control.state = CTRL_DATA_OUT;
- }
- }
- /* No DATA stage */
- else
- {
- timeout = NODATA_STAGE_TIMEOUT;
-
- /* If there is No Data Transfer Stage */
- if (direction == USB_D2H)
- {
- /* Data Direction is IN */
- phost->Control.state = CTRL_STATUS_OUT;
- }
- else
- {
- /* Data Direction is OUT */
- phost->Control.state = CTRL_STATUS_IN;
- }
- }
- /* Set the delay timer to enable timeout for data stage completion */
- phost->Control.timer = HCD_GetCurrentFrame(pdev);
- }
- else if(URB_Status == URB_ERROR)
- {
- phost->Control.state = CTRL_ERROR;
- phost->Control.status = CTRL_XACTERR;
- }
- break;
-
- case CTRL_DATA_IN:
- /* Issue an IN token */
- USBH_CtlReceiveData(pdev,
- phost->Control.buff,
- phost->Control.length,
- phost->Control.hc_num_in);
-
- phost->Control.state = CTRL_DATA_IN_WAIT;
- break;
-
- case CTRL_DATA_IN_WAIT:
-
- URB_Status = HCD_GetURB_State(pdev , phost->Control.hc_num_in);
-
- /* check is DATA packet transfered successfully */
- if (URB_Status == URB_DONE)
- {
- phost->Control.state = CTRL_STATUS_OUT;
- }
-
- /* manage error cases*/
- if (URB_Status == URB_STALL)
- {
- /* In stall case, return to previous machine state*/
- phost->gState = phost->gStateBkp;
- }
- else if (URB_Status == URB_ERROR)
- {
- /* Device error */
- phost->Control.state = CTRL_ERROR;
- }
- else if ((HCD_GetCurrentFrame(pdev)- phost->Control.timer) > timeout)
- {
- /* timeout for IN transfer */
- phost->Control.state = CTRL_ERROR;
- }
- break;
-
- case CTRL_DATA_OUT:
- /* Start DATA out transfer (only one DATA packet)*/
-
- pdev->host.hc[phost->Control.hc_num_out].toggle_out ^= 1;
-
- USBH_CtlSendData (pdev,
- phost->Control.buff,
- phost->Control.length ,
- phost->Control.hc_num_out);
-
- phost->Control.state = CTRL_DATA_OUT_WAIT;
- break;
-
- case CTRL_DATA_OUT_WAIT:
-
- URB_Status = HCD_GetURB_State(pdev , phost->Control.hc_num_out);
- if (URB_Status == URB_DONE)
- { /* If the Setup Pkt is sent successful, then change the state */
- phost->Control.state = CTRL_STATUS_IN;
- }
-
- /* handle error cases */
- else if (URB_Status == URB_STALL)
- {
- /* In stall case, return to previous machine state*/
- phost->gState = phost->gStateBkp;
- }
- else if (URB_Status == URB_NOTREADY)
- {
- /* Nack received from device */
- phost->Control.state = CTRL_DATA_OUT;
- }
- else if (URB_Status == URB_ERROR)
- {
- /* device error */
- phost->Control.state = CTRL_ERROR;
- }
- break;
-
-
- case CTRL_STATUS_IN:
- /* Send 0 bytes out packet */
- USBH_CtlReceiveData (pdev,
- 0,
- 0,
- phost->Control.hc_num_in);
-
- phost->Control.state = CTRL_STATUS_IN_WAIT;
-
- break;
-
- case CTRL_STATUS_IN_WAIT:
-
- URB_Status = HCD_GetURB_State(pdev , phost->Control.hc_num_in);
-
- if ( URB_Status == URB_DONE)
- { /* Control transfers completed, Exit the State Machine */
- phost->gState = phost->gStateBkp;
- }
-
- else if (URB_Status == URB_ERROR)
- {
- phost->Control.state = CTRL_ERROR;
- }
-
- else if((HCD_GetCurrentFrame(pdev)\
- - phost->Control.timer) > timeout)
- {
- phost->Control.state = CTRL_ERROR;
- }
- else if(URB_Status == URB_STALL)
- {
- /* Control transfers completed, Exit the State Machine */
- phost->gState = phost->gStateBkp;
- phost->Control.status = CTRL_STALL;
- status = USBH_NOT_SUPPORTED;
- }
- break;
-
- case CTRL_STATUS_OUT:
- pdev->host.hc[phost->Control.hc_num_out].toggle_out ^= 1;
- USBH_CtlSendData (pdev,
- 0,
- 0,
- phost->Control.hc_num_out);
-
- phost->Control.state = CTRL_STATUS_OUT_WAIT;
- break;
-
- case CTRL_STATUS_OUT_WAIT:
-
- URB_Status = HCD_GetURB_State(pdev , phost->Control.hc_num_out);
- if (URB_Status == URB_DONE)
- {
- phost->gState = phost->gStateBkp;
- }
- else if (URB_Status == URB_NOTREADY)
- {
- phost->Control.state = CTRL_STATUS_OUT;
- }
- else if (URB_Status == URB_ERROR)
- {
- phost->Control.state = CTRL_ERROR;
- }
- break;
-
- case CTRL_ERROR:
- /*
- After a halt condition is encountered or an error is detected by the
- host, a control endpoint is allowed to recover by accepting the next Setup
- PID; i.e., recovery actions via some other pipe are not required for control
- endpoints. For the Default Control Pipe, a device reset will ultimately be
- required to clear the halt or error condition if the next Setup PID is not
- accepted.
- */
- if (++ phost->Control.errorcount <= USBH_MAX_ERROR_COUNT)
- {
- /* Do the transmission again, starting from SETUP Packet */
- phost->Control.state = CTRL_SETUP;
- }
- else
- {
- phost->Control.status = CTRL_FAIL;
- phost->gState = phost->gStateBkp;
-
- status = USBH_FAIL;
- }
- break;
-
- default:
- break;
- }
- return status;
-}
-
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
-
-
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_hcs.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief This file implements functions for opening and closing host channels
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_hcs.h"
-
-/** @addtogroup USBH_LIB
- * @{
- */
-
-/** @addtogroup USBH_LIB_CORE
-* @{
-*/
-
-/** @defgroup USBH_HCS
- * @brief This file includes opening and closing host channels
- * @{
- */
-
-/** @defgroup USBH_HCS_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_HCS_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBH_HCS_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBH_HCS_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBH_HCS_Private_FunctionPrototypes
- * @{
- */
-static uint16_t USBH_GetFreeChannel (USB_OTG_CORE_HANDLE *pdev);
-/**
- * @}
- */
-
-
-/** @defgroup USBH_HCS_Private_Functions
- * @{
- */
-
-
-
-/**
- * @brief USBH_Open_Channel
- * Open a pipe
- * @param pdev : Selected device
- * @param hc_num: Host channel Number
- * @param dev_address: USB Device address allocated to attached device
- * @param speed : USB device speed (Full/Low)
- * @param ep_type: end point type (Bulk/int/ctl)
- * @param mps: max pkt size
- * @retval Status
- */
-uint8_t USBH_Open_Channel (USB_OTG_CORE_HANDLE *pdev,
- uint8_t hc_num,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps)
-{
-
- pdev->host.hc[hc_num].ep_num = pdev->host.channel[hc_num]& 0x7F;
- pdev->host.hc[hc_num].ep_is_in = (pdev->host.channel[hc_num] & 0x80 ) == 0x80;
- pdev->host.hc[hc_num].dev_addr = dev_address;
- pdev->host.hc[hc_num].ep_type = ep_type;
- pdev->host.hc[hc_num].max_packet = mps;
- pdev->host.hc[hc_num].speed = speed;
- pdev->host.hc[hc_num].toggle_in = 0;
- pdev->host.hc[hc_num].toggle_out = 0;
- if(speed == HPRT0_PRTSPD_HIGH_SPEED)
- {
- pdev->host.hc[hc_num].do_ping = 1;
- }
-
- USB_OTG_HC_Init(pdev, hc_num) ;
-
- return HC_OK;
-
-}
-
-/**
- * @brief USBH_Modify_Channel
- * Modify a pipe
- * @param pdev : Selected device
- * @param hc_num: Host channel Number
- * @param dev_address: USB Device address allocated to attached device
- * @param speed : USB device speed (Full/Low)
- * @param ep_type: end point type (Bulk/int/ctl)
- * @param mps: max pkt size
- * @retval Status
- */
-uint8_t USBH_Modify_Channel (USB_OTG_CORE_HANDLE *pdev,
- uint8_t hc_num,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps)
-{
-
- if(dev_address != 0)
- {
- pdev->host.hc[hc_num].dev_addr = dev_address;
- }
-
- if((pdev->host.hc[hc_num].max_packet != mps) && (mps != 0))
- {
- pdev->host.hc[hc_num].max_packet = mps;
- }
-
- if((pdev->host.hc[hc_num].speed != speed ) && (speed != 0 ))
- {
- pdev->host.hc[hc_num].speed = speed;
- }
-
- USB_OTG_HC_Init(pdev, hc_num);
- return HC_OK;
-
-}
-
-/**
- * @brief USBH_Alloc_Channel
- * Allocate a new channel for the pipe
- * @param ep_addr: End point for which the channel to be allocated
- * @retval hc_num: Host channel number
- */
-uint8_t USBH_Alloc_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t ep_addr)
-{
- uint16_t hc_num;
-
- hc_num = USBH_GetFreeChannel(pdev);
-
- if (hc_num != HC_ERROR)
- {
- pdev->host.channel[hc_num] = HC_USED | ep_addr;
- }
- return hc_num;
-}
-
-/**
- * @brief USBH_Free_Pipe
- * Free the USB host channel
- * @param idx: Channel number to be freed
- * @retval Status
- */
-uint8_t USBH_Free_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t idx)
-{
- if(idx < HC_MAX)
- {
- pdev->host.channel[idx] &= HC_USED_MASK;
- }
- return USBH_OK;
-}
-
-
-/**
- * @brief USBH_DeAllocate_AllChannel
- * Free all USB host channel
-* @param pdev : core instance
- * @retval Status
- */
-uint8_t USBH_DeAllocate_AllChannel (USB_OTG_CORE_HANDLE *pdev)
-{
- uint8_t idx;
-
- for (idx = 2; idx < HC_MAX ; idx ++)
- {
- pdev->host.channel[idx] = 0;
- }
- return USBH_OK;
-}
-
-/**
- * @brief USBH_GetFreeChannel
- * Get a free channel number for allocation to a device endpoint
- * @param None
- * @retval idx: Free Channel number
- */
-static uint16_t USBH_GetFreeChannel (USB_OTG_CORE_HANDLE *pdev)
-{
- uint8_t idx = 0;
-
- for (idx = 0 ; idx < HC_MAX ; idx++)
- {
- if ((pdev->host.channel[idx] & HC_USED) == 0)
- {
- return idx;
- }
- }
- return HC_ERROR;
-}
-
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_ioreq.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief This file handles the issuing of the USB transactions
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-/* Includes ------------------------------------------------------------------*/
-
-#include "usbh_ioreq.h"
-
-/** @addtogroup USBH_LIB
- * @{
- */
-
-/** @addtogroup USBH_LIB_CORE
-* @{
-*/
-
-/** @defgroup USBH_IOREQ
- * @brief This file handles the standard protocol processing (USB v2.0)
- * @{
- */
-
-
-/** @defgroup USBH_IOREQ_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBH_IOREQ_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-
-/** @defgroup USBH_IOREQ_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBH_IOREQ_Private_Variables
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBH_IOREQ_Private_FunctionPrototypes
- * @{
- */
-static USBH_Status USBH_SubmitSetupRequest(USBH_HOST *phost,
- uint8_t* buff,
- uint16_t length);
-
-/**
- * @}
- */
-
-
-/** @defgroup USBH_IOREQ_Private_Functions
- * @{
- */
-
-
-/**
- * @brief USBH_CtlReq
- * USBH_CtlReq sends a control request and provide the status after
- * completion of the request
- * @param pdev: Selected device
- * @param req: Setup Request Structure
- * @param buff: data buffer address to store the response
- * @param length: length of the response
- * @retval Status
- */
-USBH_Status USBH_CtlReq (USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t *buff,
- uint16_t length)
-{
- USBH_Status status;
- URB_STATE URB_Status = URB_IDLE;
-
- URB_Status = HCD_GetURB_State(pdev, phost->Control.hc_num_out);
-
- status = USBH_BUSY;
-
- switch (phost->RequestState)
- {
- case CMD_SEND:
- /* Start a SETUP transfer */
- USBH_SubmitSetupRequest(phost, buff, length);
- phost->RequestState = CMD_WAIT;
- status = USBH_BUSY;
- break;
-
- case CMD_WAIT:
- if (URB_Status == URB_DONE)
- {
- /* Commands successfully sent and Response Received */
- phost->RequestState = CMD_SEND;
- status = USBH_OK;
- }
- else if (URB_Status == URB_ERROR)
- {
- /* Failure Mode */
- phost->RequestState = CMD_SEND;
- status = USBH_FAIL;
- }
- else if (URB_Status == URB_STALL)
- {
- /* Commands successfully sent and Response Received */
- phost->RequestState = CMD_SEND;
- status = USBH_NOT_SUPPORTED;
- }
- break;
-
- default:
- break;
- }
- return status;
-}
-
-/**
- * @brief USBH_CtlSendSetup
- * Sends the Setup Packet to the Device
- * @param pdev: Selected device
- * @param buff: Buffer pointer from which the Data will be send to Device
- * @param hc_num: Host channel Number
- * @retval Status
- */
-USBH_Status USBH_CtlSendSetup ( USB_OTG_CORE_HANDLE *pdev,
- uint8_t *buff,
- uint8_t hc_num){
- pdev->host.hc[hc_num].ep_is_in = 0;
- pdev->host.hc[hc_num].data_pid = HC_PID_SETUP;
- pdev->host.hc[hc_num].xfer_buff = buff;
- pdev->host.hc[hc_num].xfer_len = USBH_SETUP_PKT_SIZE;
-
- return (USBH_Status)HCD_SubmitRequest (pdev , hc_num);
-}
-
-
-/**
- * @brief USBH_CtlSendData
- * Sends a data Packet to the Device
- * @param pdev: Selected device
- * @param buff: Buffer pointer from which the Data will be sent to Device
- * @param length: Length of the data to be sent
- * @param hc_num: Host channel Number
- * @retval Status
- */
-USBH_Status USBH_CtlSendData ( USB_OTG_CORE_HANDLE *pdev,
- uint8_t *buff,
- uint8_t length,
- uint8_t hc_num)
-{
- pdev->host.hc[hc_num].ep_is_in = 0;
- pdev->host.hc[hc_num].xfer_buff = buff;
- pdev->host.hc[hc_num].xfer_len = length;
-
- if ( length == 0 )
- { /* For Status OUT stage, Length==0, Status Out PID = 1 */
- pdev->host.hc[hc_num].toggle_out = 1;
- }
-
- /* Set the Data Toggle bit as per the Flag */
- if ( pdev->host.hc[hc_num].toggle_out == 0)
- { /* Put the PID 0 */
- pdev->host.hc[hc_num].data_pid = HC_PID_DATA0;
- }
- else
- { /* Put the PID 1 */
- pdev->host.hc[hc_num].data_pid = HC_PID_DATA1 ;
- }
-
- HCD_SubmitRequest (pdev , hc_num);
-
- return USBH_OK;
-}
-
-
-/**
- * @brief USBH_CtlReceiveData
- * Receives the Device Response to the Setup Packet
- * @param pdev: Selected device
- * @param buff: Buffer pointer in which the response needs to be copied
- * @param length: Length of the data to be received
- * @param hc_num: Host channel Number
- * @retval Status.
- */
-USBH_Status USBH_CtlReceiveData(USB_OTG_CORE_HANDLE *pdev,
- uint8_t* buff,
- uint8_t length,
- uint8_t hc_num)
-{
-
- pdev->host.hc[hc_num].ep_is_in = 1;
- pdev->host.hc[hc_num].data_pid = HC_PID_DATA1;
- pdev->host.hc[hc_num].xfer_buff = buff;
- pdev->host.hc[hc_num].xfer_len = length;
-
- HCD_SubmitRequest (pdev , hc_num);
-
- return USBH_OK;
-
-}
-
-
-/**
- * @brief USBH_BulkSendData
- * Sends the Bulk Packet to the device
- * @param pdev: Selected device
- * @param buff: Buffer pointer from which the Data will be sent to Device
- * @param length: Length of the data to be sent
- * @param hc_num: Host channel Number
- * @retval Status
- */
-USBH_Status USBH_BulkSendData ( USB_OTG_CORE_HANDLE *pdev,
- uint8_t *buff,
- uint16_t length,
- uint8_t hc_num)
-{
- pdev->host.hc[hc_num].ep_is_in = 0;
- pdev->host.hc[hc_num].xfer_buff = buff;
- pdev->host.hc[hc_num].xfer_len = length;
-
- /* Set the Data Toggle bit as per the Flag */
- if ( pdev->host.hc[hc_num].toggle_out == 0)
- { /* Put the PID 0 */
- pdev->host.hc[hc_num].data_pid = HC_PID_DATA0;
- }
- else
- { /* Put the PID 1 */
- pdev->host.hc[hc_num].data_pid = HC_PID_DATA1 ;
- }
-
- HCD_SubmitRequest (pdev , hc_num);
- return USBH_OK;
-}
-
-
-/**
- * @brief USBH_BulkReceiveData
- * Receives IN bulk packet from device
- * @param pdev: Selected device
- * @param buff: Buffer pointer in which the received data packet to be copied
- * @param length: Length of the data to be received
- * @param hc_num: Host channel Number
- * @retval Status.
- */
-USBH_Status USBH_BulkReceiveData( USB_OTG_CORE_HANDLE *pdev,
- uint8_t *buff,
- uint16_t length,
- uint8_t hc_num)
-{
- pdev->host.hc[hc_num].ep_is_in = 1;
- pdev->host.hc[hc_num].xfer_buff = buff;
- pdev->host.hc[hc_num].xfer_len = length;
-
-
- if( pdev->host.hc[hc_num].toggle_in == 0)
- {
- pdev->host.hc[hc_num].data_pid = HC_PID_DATA0;
- }
- else
- {
- pdev->host.hc[hc_num].data_pid = HC_PID_DATA1;
- }
-
- HCD_SubmitRequest (pdev , hc_num);
- return USBH_OK;
-}
-
-
-/**
- * @brief USBH_InterruptReceiveData
- * Receives the Device Response to the Interrupt IN token
- * @param pdev: Selected device
- * @param buff: Buffer pointer in which the response needs to be copied
- * @param length: Length of the data to be received
- * @param hc_num: Host channel Number
- * @retval Status.
- */
-USBH_Status USBH_InterruptReceiveData( USB_OTG_CORE_HANDLE *pdev,
- uint8_t *buff,
- uint8_t length,
- uint8_t hc_num)
-{
-
- pdev->host.hc[hc_num].ep_is_in = 1;
- pdev->host.hc[hc_num].xfer_buff = buff;
- pdev->host.hc[hc_num].xfer_len = length;
-
-
-
- if(pdev->host.hc[hc_num].toggle_in == 0)
- {
- pdev->host.hc[hc_num].data_pid = HC_PID_DATA0;
- }
- else
- {
- pdev->host.hc[hc_num].data_pid = HC_PID_DATA1;
- }
-
- /* toggle DATA PID */
- pdev->host.hc[hc_num].toggle_in ^= 1;
-
- HCD_SubmitRequest (pdev , hc_num);
-
- return USBH_OK;
-}
-
-/**
- * @brief USBH_InterruptSendData
- * Sends the data on Interrupt OUT Endpoint
- * @param pdev: Selected device
- * @param buff: Buffer pointer from where the data needs to be copied
- * @param length: Length of the data to be sent
- * @param hc_num: Host channel Number
- * @retval Status.
- */
-USBH_Status USBH_InterruptSendData( USB_OTG_CORE_HANDLE *pdev,
- uint8_t *buff,
- uint8_t length,
- uint8_t hc_num)
-{
-
- pdev->host.hc[hc_num].ep_is_in = 0;
- pdev->host.hc[hc_num].xfer_buff = buff;
- pdev->host.hc[hc_num].xfer_len = length;
-
- if(pdev->host.hc[hc_num].toggle_in == 0)
- {
- pdev->host.hc[hc_num].data_pid = HC_PID_DATA0;
- }
- else
- {
- pdev->host.hc[hc_num].data_pid = HC_PID_DATA1;
- }
-
- pdev->host.hc[hc_num].toggle_in ^= 1;
-
- HCD_SubmitRequest (pdev , hc_num);
-
- return USBH_OK;
-}
-
-
-/**
- * @brief USBH_SubmitSetupRequest
- * Start a setup transfer by changing the state-machine and
- * initializing the required variables needed for the Control Transfer
- * @param pdev: Selected device
- * @param setup: Setup Request Structure
- * @param buff: Buffer used for setup request
- * @param length: Length of the data
- * @retval Status.
-*/
-static USBH_Status USBH_SubmitSetupRequest(USBH_HOST *phost,
- uint8_t* buff,
- uint16_t length)
-{
-
- /* Save Global State */
- phost->gStateBkp = phost->gState;
-
- /* Prepare the Transactions */
- phost->gState = HOST_CTRL_XFER;
- phost->Control.buff = buff;
- phost->Control.length = length;
- phost->Control.state = CTRL_SETUP;
-
- return USBH_OK;
-}
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
-
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usbh_stdreq.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief This file implements the standard requests for device enumeration
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-/* Includes ------------------------------------------------------------------*/
-
-#include "usbh_ioreq.h"
-#include "usbh_stdreq.h"
-
-/** @addtogroup USBH_LIB
-* @{
-*/
-
-/** @addtogroup USBH_LIB_CORE
-* @{
-*/
-
-/** @defgroup USBH_STDREQ
-* @brief This file implements the standard requests for device enumeration
-* @{
-*/
-
-
-/** @defgroup USBH_STDREQ_Private_Defines
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USBH_STDREQ_Private_TypesDefinitions
-* @{
-*/
-/**
-* @}
-*/
-
-
-
-/** @defgroup USBH_STDREQ_Private_Macros
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USBH_STDREQ_Private_Variables
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USBH_STDREQ_Private_FunctionPrototypes
-* @{
-*/
-static void USBH_ParseDevDesc (USBH_DevDesc_TypeDef* , uint8_t *buf, uint16_t length);
-
-static void USBH_ParseCfgDesc (USBH_CfgDesc_TypeDef* cfg_desc,
- USBH_InterfaceDesc_TypeDef* itf_desc,
- USBH_EpDesc_TypeDef* ep_desc,
- uint8_t *buf,
- uint16_t length);
-static USBH_DescHeader_t *USBH_GetNextDesc (uint8_t *pbuf,
- uint16_t *ptr);
-
-static void USBH_ParseInterfaceDesc (USBH_InterfaceDesc_TypeDef *if_descriptor, uint8_t *buf);
-static void USBH_ParseEPDesc (USBH_EpDesc_TypeDef *ep_descriptor, uint8_t *buf);
-
-static void USBH_ParseStringDesc (uint8_t* psrc, uint8_t* pdest, uint16_t length);
-/**
-* @}
-*/
-
-
-/** @defgroup USBH_STDREQ_Private_Functions
-* @{
-*/
-
-
-/**
-* @brief USBH_Get_DevDesc
-* Issue Get Device Descriptor command to the device. Once the response
-* received, it parses the device descriptor and updates the status.
-* @param pdev: Selected device
-* @param dev_desc: Device Descriptor buffer address
-* @param pdev->host.Rx_Buffer: Receive Buffer address
-* @param length: Length of the descriptor
-* @retval Status
-*/
-USBH_Status USBH_Get_DevDesc(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t length)
-{
-
- USBH_Status status;
-
- if((status = USBH_GetDescriptor(pdev,
- phost,
- USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD,
- USB_DESC_DEVICE,
- pdev->host.Rx_Buffer,
- length)) == USBH_OK)
- {
- /* Commands successfully sent and Response Received */
- USBH_ParseDevDesc(&phost->device_prop.Dev_Desc, pdev->host.Rx_Buffer, length);
- }
- return status;
-}
-
-/**
-* @brief USBH_Get_CfgDesc
-* Issues Configuration Descriptor to the device. Once the response
-* received, it parses the configuartion descriptor and updates the
-* status.
-* @param pdev: Selected device
-* @param cfg_desc: Configuration Descriptor address
-* @param itf_desc: Interface Descriptor address
-* @param ep_desc: Endpoint Descriptor address
-* @param length: Length of the descriptor
-* @retval Status
-*/
-USBH_Status USBH_Get_CfgDesc(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint16_t length)
-
-{
- USBH_Status status;
-
- if((status = USBH_GetDescriptor(pdev,
- phost,
- USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD,
- USB_DESC_CONFIGURATION,
- pdev->host.Rx_Buffer,
- length)) == USBH_OK)
- {
- /* Commands successfully sent and Response Received */
- USBH_ParseCfgDesc (&phost->device_prop.Cfg_Desc,
- phost->device_prop.Itf_Desc,
- phost->device_prop.Ep_Desc[0],
- pdev->host.Rx_Buffer,
- length);
-
- }
- return status;
-}
-
-
-/**
-* @brief USBH_Get_StringDesc
-* Issues string Descriptor command to the device. Once the response
-* received, it parses the string descriptor and updates the status.
-* @param pdev: Selected device
-* @param string_index: String index for the descriptor
-* @param buff: Buffer address for the descriptor
-* @param length: Length of the descriptor
-* @retval Status
-*/
-USBH_Status USBH_Get_StringDesc(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t string_index,
- uint8_t *buff,
- uint16_t length)
-{
- USBH_Status status;
-
- if((status = USBH_GetDescriptor(pdev,
- phost,
- USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD,
- USB_DESC_STRING | string_index,
- pdev->host.Rx_Buffer,
- length)) == USBH_OK)
- {
- /* Commands successfully sent and Response Received */
- USBH_ParseStringDesc(pdev->host.Rx_Buffer,buff, length);
- }
- return status;
-}
-
-/**
-* @brief USBH_GetDescriptor
-* Issues Descriptor command to the device. Once the response received,
-* it parses the descriptor and updates the status.
-* @param pdev: Selected device
-* @param req_type: Descriptor type
-* @param value_idx: wValue for the GetDescriptr request
-* @param buff: Buffer to store the descriptor
-* @param length: Length of the descriptor
-* @retval Status
-*/
-USBH_Status USBH_GetDescriptor(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t req_type,
- uint16_t value_idx,
- uint8_t* buff,
- uint16_t length )
-{
- phost->Control.setup.b.bmRequestType = USB_D2H | req_type;
- phost->Control.setup.b.bRequest = USB_REQ_GET_DESCRIPTOR;
- phost->Control.setup.b.wValue.w = value_idx;
-
- if ((value_idx & 0xff00) == USB_DESC_STRING)
- {
- phost->Control.setup.b.wIndex.w = 0x0409;
- }
- else
- {
- phost->Control.setup.b.wIndex.w = 0;
- }
- phost->Control.setup.b.wLength.w = length;
- return USBH_CtlReq(pdev, phost, buff , length );
-}
-
-/**
-* @brief USBH_SetAddress
-* This command sets the address to the connected device
-* @param pdev: Selected device
-* @param DeviceAddress: Device address to assign
-* @retval Status
-*/
-USBH_Status USBH_SetAddress(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t DeviceAddress)
-{
- phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE | \
- USB_REQ_TYPE_STANDARD;
-
- phost->Control.setup.b.bRequest = USB_REQ_SET_ADDRESS;
-
- phost->Control.setup.b.wValue.w = (uint16_t)DeviceAddress;
- phost->Control.setup.b.wIndex.w = 0;
- phost->Control.setup.b.wLength.w = 0;
-
- return USBH_CtlReq(pdev, phost, 0 , 0 );
-}
-
-/**
-* @brief USBH_SetCfg
-* The command sets the configuration value to the connected device
-* @param pdev: Selected device
-* @param cfg_idx: Configuration value
-* @retval Status
-*/
-USBH_Status USBH_SetCfg(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint16_t cfg_idx)
-{
-
- phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE |\
- USB_REQ_TYPE_STANDARD;
- phost->Control.setup.b.bRequest = USB_REQ_SET_CONFIGURATION;
- phost->Control.setup.b.wValue.w = cfg_idx;
- phost->Control.setup.b.wIndex.w = 0;
- phost->Control.setup.b.wLength.w = 0;
-
- return USBH_CtlReq(pdev, phost, 0 , 0 );
-}
-
-/**
-* @brief USBH_ClrFeature
-* This request is used to clear or disable a specific feature.
-
-* @param pdev: Selected device
-* @param ep_num: endpoint number
-* @param hc_num: Host channel number
-* @retval Status
-*/
-USBH_Status USBH_ClrFeature(USB_OTG_CORE_HANDLE *pdev,
- USBH_HOST *phost,
- uint8_t ep_num,
- uint8_t hc_num)
-{
-
- phost->Control.setup.b.bmRequestType = USB_H2D |
- USB_REQ_RECIPIENT_ENDPOINT |
- USB_REQ_TYPE_STANDARD;
-
- phost->Control.setup.b.bRequest = USB_REQ_CLEAR_FEATURE;
- phost->Control.setup.b.wValue.w = FEATURE_SELECTOR_ENDPOINT;
- phost->Control.setup.b.wIndex.w = ep_num;
- phost->Control.setup.b.wLength.w = 0;
-
- if ((ep_num & USB_REQ_DIR_MASK ) == USB_D2H)
- { /* EP Type is IN */
- pdev->host.hc[hc_num].toggle_in = 0;
- }
- else
- {/* EP Type is OUT */
- pdev->host.hc[hc_num].toggle_out = 0;
- }
-
- return USBH_CtlReq(pdev, phost, 0 , 0 );
-}
-
-/**
-* @brief USBH_ParseDevDesc
-* This function Parses the device descriptor
-* @param dev_desc: device_descriptor destinaton address
-* @param buf: Buffer where the source descriptor is available
-* @param length: Length of the descriptor
-* @retval None
-*/
-static void USBH_ParseDevDesc (USBH_DevDesc_TypeDef* dev_desc,
- uint8_t *buf,
- uint16_t length)
-{
- dev_desc->bLength = *(uint8_t *) (buf + 0);
- dev_desc->bDescriptorType = *(uint8_t *) (buf + 1);
- dev_desc->bcdUSB = LE16 (buf + 2);
- dev_desc->bDeviceClass = *(uint8_t *) (buf + 4);
- dev_desc->bDeviceSubClass = *(uint8_t *) (buf + 5);
- dev_desc->bDeviceProtocol = *(uint8_t *) (buf + 6);
- dev_desc->bMaxPacketSize = *(uint8_t *) (buf + 7);
-
- if (length > 8)
- { /* For 1st time after device connection, Host may issue only 8 bytes for
- Device Descriptor Length */
- dev_desc->idVendor = LE16 (buf + 8);
- dev_desc->idProduct = LE16 (buf + 10);
- dev_desc->bcdDevice = LE16 (buf + 12);
- dev_desc->iManufacturer = *(uint8_t *) (buf + 14);
- dev_desc->iProduct = *(uint8_t *) (buf + 15);
- dev_desc->iSerialNumber = *(uint8_t *) (buf + 16);
- dev_desc->bNumConfigurations = *(uint8_t *) (buf + 17);
- }
-}
-
-/**
-* @brief USBH_ParseCfgDesc
-* This function Parses the configuration descriptor
-* @param cfg_desc: Configuration Descriptor address
-* @param itf_desc: Interface Descriptor address
-* @param ep_desc: Endpoint Descriptor address
-* @param buf: Buffer where the source descriptor is available
-* @param length: Length of the descriptor
-* @retval None
-*/
-static void USBH_ParseCfgDesc (USBH_CfgDesc_TypeDef* cfg_desc,
- USBH_InterfaceDesc_TypeDef* itf_desc,
- USBH_EpDesc_TypeDef* ep_desc,
- uint8_t *buf,
- uint16_t length)
-{
- USBH_InterfaceDesc_TypeDef *pif ;
- USBH_EpDesc_TypeDef *pep;
- USBH_DescHeader_t *pdesc = (USBH_DescHeader_t *)buf;
- uint16_t ptr;
- int8_t if_ix;
- int8_t ep_ix;
-
- pdesc = (USBH_DescHeader_t *)buf;
-
- /* Parse configuration descriptor */
- cfg_desc->bLength = *(uint8_t *) (buf + 0);
- cfg_desc->bDescriptorType = *(uint8_t *) (buf + 1);
- cfg_desc->wTotalLength = LE16 (buf + 2);
- cfg_desc->bNumInterfaces = *(uint8_t *) (buf + 4);
- cfg_desc->bConfigurationValue = *(uint8_t *) (buf + 5);
- cfg_desc->iConfiguration = *(uint8_t *) (buf + 6);
- cfg_desc->bmAttributes = *(uint8_t *) (buf + 7);
- cfg_desc->bMaxPower = *(uint8_t *) (buf + 8);
-
-
- if (length > USB_CONFIGURATION_DESC_SIZE)
- {
- ptr = USB_LEN_CFG_DESC;
-
- if ( cfg_desc->bNumInterfaces <= USBH_MAX_NUM_INTERFACES)
- {
- if_ix = 0;
- pif = (USBH_InterfaceDesc_TypeDef *)0;
-
- /* Parse Interface descriptor relative to the current configuration */
- if(cfg_desc->bNumInterfaces <= USBH_MAX_NUM_INTERFACES)
- {
- while (if_ix < cfg_desc->bNumInterfaces)
- {
- pdesc = USBH_GetNextDesc((uint8_t *)pdesc, &ptr);
- if (pdesc->bDescriptorType == USB_DESC_TYPE_INTERFACE)
- {
- pif = &itf_desc[if_ix];
- USBH_ParseInterfaceDesc (pif, (uint8_t *)pdesc);
- ep_ix = 0;
-
- /* Parse Ep descriptors relative to the current interface */
- if(pif->bNumEndpoints <= USBH_MAX_NUM_ENDPOINTS)
- {
- while (ep_ix < pif->bNumEndpoints)
- {
- pdesc = USBH_GetNextDesc((void* )pdesc, &ptr);
- if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT)
- {
- pep = &ep_desc[ep_ix];
- USBH_ParseEPDesc (pep, (uint8_t *)pdesc);
- ep_ix++;
- }
- else
- {
- ptr += pdesc->bLength;
- }
- }
- }
- if_ix++;
- }
- else
- {
- ptr += pdesc->bLength;
- }
- }
- }
- }
- }
-}
-
-
-/**
-* @brief USBH_ParseInterfaceDesc
-* This function Parses the interface descriptor
-* @param if_descriptor : Interface descriptor destination
-* @param buf: Buffer where the descriptor data is available
-* @retval None
-*/
-static void USBH_ParseInterfaceDesc (USBH_InterfaceDesc_TypeDef *if_descriptor,
- uint8_t *buf)
-{
- if_descriptor->bLength = *(uint8_t *) (buf + 0);
- if_descriptor->bDescriptorType = *(uint8_t *) (buf + 1);
- if_descriptor->bInterfaceNumber = *(uint8_t *) (buf + 2);
- if_descriptor->bAlternateSetting = *(uint8_t *) (buf + 3);
- if_descriptor->bNumEndpoints = *(uint8_t *) (buf + 4);
- if_descriptor->bInterfaceClass = *(uint8_t *) (buf + 5);
- if_descriptor->bInterfaceSubClass = *(uint8_t *) (buf + 6);
- if_descriptor->bInterfaceProtocol = *(uint8_t *) (buf + 7);
- if_descriptor->iInterface = *(uint8_t *) (buf + 8);
-}
-
-/**
-* @brief USBH_ParseEPDesc
-* This function Parses the endpoint descriptor
-* @param ep_descriptor: Endpoint descriptor destination address
-* @param buf: Buffer where the parsed descriptor stored
-* @retval None
-*/
-static void USBH_ParseEPDesc (USBH_EpDesc_TypeDef *ep_descriptor,
- uint8_t *buf)
-{
-
- ep_descriptor->bLength = *(uint8_t *) (buf + 0);
- ep_descriptor->bDescriptorType = *(uint8_t *) (buf + 1);
- ep_descriptor->bEndpointAddress = *(uint8_t *) (buf + 2);
- ep_descriptor->bmAttributes = *(uint8_t *) (buf + 3);
- ep_descriptor->wMaxPacketSize = LE16 (buf + 4);
- ep_descriptor->bInterval = *(uint8_t *) (buf + 6);
-}
-
-/**
-* @brief USBH_ParseStringDesc
-* This function Parses the string descriptor
-* @param psrc: Source pointer containing the descriptor data
-* @param pdest: Destination address pointer
-* @param length: Length of the descriptor
-* @retval None
-*/
-static void USBH_ParseStringDesc (uint8_t* psrc,
- uint8_t* pdest,
- uint16_t length)
-{
- uint16_t strlength;
- uint16_t idx;
-
- /* The UNICODE string descriptor is not NULL-terminated. The string length is
- computed by substracting two from the value of the first byte of the descriptor.
- */
-
- /* Check which is lower size, the Size of string or the length of bytes read
- from the device */
-
- if ( psrc[1] == USB_DESC_TYPE_STRING)
- { /* Make sure the Descriptor is String Type */
-
- /* psrc[0] contains Size of Descriptor, subtract 2 to get the length of string */
- strlength = ( ( (psrc[0]-2) <= length) ? (psrc[0]-2) :length);
- psrc += 2; /* Adjust the offset ignoring the String Len and Descriptor type */
-
- for (idx = 0; idx < strlength; idx+=2 )
- {/* Copy Only the string and ignore the UNICODE ID, hence add the src */
- *pdest = psrc[idx];
- pdest++;
- }
- *pdest = 0; /* mark end of string */
- }
-}
-
-/**
-* @brief USBH_GetNextDesc
-* This function return the next descriptor header
-* @param buf: Buffer where the cfg descriptor is available
-* @param ptr: data popinter inside the cfg descriptor
-* @retval next header
-*/
-static USBH_DescHeader_t *USBH_GetNextDesc (uint8_t *pbuf, uint16_t *ptr)
-{
- USBH_DescHeader_t *pnext;
-
- *ptr += ((USBH_DescHeader_t *)pbuf)->bLength;
- pnext = (USBH_DescHeader_t *)((uint8_t *)pbuf + \
- ((USBH_DescHeader_t *)pbuf)->bLength);
-
- return(pnext);
-}
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
-
-
-
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- <p class="MsoNormal"><span style="font-size: 8pt; font-family: "Arial","sans-serif"; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
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- <td style="padding: 1.5pt;">
- <h1 style="margin-bottom: 0.25in; text-align: center;" align="center"><span style="font-size: 20pt; font-family: "Verdana","sans-serif"; color: rgb(51, 102, 255);">Release Notes for STM32F105/7xx and STM32F2xx USB OTG Driver</span><span style="font-size: 20pt; font-family: "Verdana","sans-serif";"><o:p></o:p></span></h1>
- <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Arial","sans-serif"; color: black;">Copyright
- 2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
- <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Arial","sans-serif"; color: black;"><img id="_x0000_i1026" src="../../_htmresc/logo.bmp" border="0" height="65" width="86"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
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- <td style="padding: 0in;" valign="top">
- <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
- <ol style="margin-top: 0in;" start="1" type="1">
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><a href="#History">STM32F105/7xx and STM32F2xx USB OTG Driver update History</a><o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><a href="#License">License</a><o:p></o:p></span></li>
- </ol>
- <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F105/7xx and STM32F2xx USB OTG Driver update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 171px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.0 / 22-July-2011 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Second official version supporting <span style="font-weight: bold; font-style: italic;">STM32F105/7</span> and <span style="font-weight: bold; font-style: italic;">STM32F2xx</span> devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename the Library from "<span style="font-style: italic;">STM32_USB_HOST_Driver</span>" to "<span style="font-style: italic;">STM32_USB_OTG_Driver</span>"</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold; font-style: italic;">STM32F2xx</span> devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support for Device and OTG modes</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change HCD layer to support High speed core</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change the Low level driver to support multi core support for Host mode</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add Stop mechanism for Host and Device modes</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change VBUS enabling method, to use the external or the internal VBUS when using the ULPI</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><br></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 171px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 - 11/29/2010<o:p></o:p></span></h3>
-<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Created </span></li></ul><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
- <p class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana; color: black;">The use of this STM32 software is governed by the terms and conditions of the License Agreement </span><span style="font-size: 10pt; font-family: Verdana; color: black;"><span style="font-weight: bold; font-style: italic;">"MCD-ST Liberty SW License Agreement 20Jul2011 v0.1.pdf"</span> </span><span style="font-size: 10pt; font-family: Verdana; color: black;">available in the root of this package.</span><span style="color: black;"><o:p> </o:p></span></p>
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- <hr align="center" size="2" width="100%">
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- complete documentation on </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32(<span style="color: black;">CORTEX M3) 32-Bit
- Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
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\ No newline at end of file
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_bsp.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Specific api's relative to the used hardware platform
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_BSP__H__
-#define __USB_BSP__H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_core.h"
-#include "stm32f4_discovery.h"
-
-/** @addtogroup USB_OTG_DRIVER
- * @{
- */
-
-/** @defgroup USB_BSP
- * @brief This file is the
- * @{
- */
-
-
-/** @defgroup USB_BSP_Exported_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_BSP_Exported_Types
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_BSP_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_BSP_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_BSP_Exported_FunctionsPrototype
- * @{
- */
-void BSP_Init(void);
-
-void USB_OTG_BSP_Init (USB_OTG_CORE_HANDLE *pdev);
-void USB_OTG_BSP_uDelay (const uint32_t usec);
-void USB_OTG_BSP_mDelay (const uint32_t msec);
-void USB_OTG_BSP_EnableInterrupt (USB_OTG_CORE_HANDLE *pdev);
-#ifdef USE_HOST_MODE
-void USB_OTG_BSP_ConfigVBUS(USB_OTG_CORE_HANDLE *pdev);
-void USB_OTG_BSP_DriveVBUS(USB_OTG_CORE_HANDLE *pdev,uint8_t state);
-#endif
-/**
- * @}
- */
-
-#endif //__USB_BSP__H__
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_conf.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief general low level driver configuration
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_CONF__H__
-#define __USB_CONF__H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-
-/** @addtogroup USB_OTG_DRIVER
- * @{
- */
-
-/** @defgroup USB_CONF
- * @brief USB low level driver configuration file
- * @{
- */
-
-/** @defgroup USB_CONF_Exported_Defines
- * @{
- */
-
-/* USB Core and PHY interface configuration.
- Tip: To avoid modifying these defines each time you need to change the USB
- configuration, you can declare the needed define in your toolchain
- compiler preprocessor.
- */
-#ifndef USE_USB_OTG_FS
- //#define USE_USB_OTG_FS
-#endif /* USE_USB_OTG_FS */
-
-#ifndef USE_USB_OTG_HS
- //#define USE_USB_OTG_HS
-#endif /* USE_USB_OTG_HS */
-
-#ifndef USE_ULPI_PHY
- //#define USE_ULPI_PHY
-#endif /* USE_ULPI_PHY */
-
-#ifndef USE_EMBEDDED_PHY
- //#define USE_EMBEDDED_PHY
-#endif /* USE_EMBEDDED_PHY */
-
-#ifndef USE_I2C_PHY
- //#define USE_I2C_PHY
-#endif /* USE_I2C_PHY */
-
-
-#ifdef USE_USB_OTG_FS
- #define USB_OTG_FS_CORE
-#endif
-
-#ifdef USE_USB_OTG_HS
- #define USB_OTG_HS_CORE
-#endif
-
-/*******************************************************************************
-* FIFO Size Configuration in Device mode
-*
-* (i) Receive data FIFO size = RAM for setup packets +
-* OUT endpoint control information +
-* data OUT packets + miscellaneous
-* Space = ONE 32-bits words
-* --> RAM for setup packets = 10 spaces
-* (n is the nbr of CTRL EPs the device core supports)
-* --> OUT EP CTRL info = 1 space
-* (one space for status information written to the FIFO along with each
-* received packet)
-* --> data OUT packets = (Largest Packet Size / 4) + 1 spaces
-* (MINIMUM to receive packets)
-* --> OR data OUT packets = at least 2*(Largest Packet Size / 4) + 1 spaces
-* (if high-bandwidth EP is enabled or multiple isochronous EPs)
-* --> miscellaneous = 1 space per OUT EP
-* (one space for transfer complete status information also pushed to the
-* FIFO with each endpoint's last packet)
-*
-* (ii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for
-* that particular IN EP. More space allocated in the IN EP Tx FIFO results
-* in a better performance on the USB and can hide latencies on the AHB.
-*
-* (iii) TXn min size = 16 words. (n : Transmit FIFO index)
-* (iv) When a TxFIFO is not used, the Configuration should be as follows:
-* case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
-* --> Txm can use the space allocated for Txn.
-* case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
-* --> Txn should be configured with the minimum space of 16 words
-* (v) The FIFO is used optimally when used TxFIFOs are allocated in the top
-* of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
-*******************************************************************************/
-
-/*******************************************************************************
-* FIFO Size Configuration in Host mode
-*
-* (i) Receive data FIFO size = (Largest Packet Size / 4) + 1 or
-* 2x (Largest Packet Size / 4) + 1, If a
-* high-bandwidth channel or multiple isochronous
-* channels are enabled
-*
-* (ii) For the host nonperiodic Transmit FIFO is the largest maximum packet size
-* for all supported nonperiodic OUT channels. Typically, a space
-* corresponding to two Largest Packet Size is recommended.
-*
-* (iii) The minimum amount of RAM required for Host periodic Transmit FIFO is
-* the largest maximum packet size for all supported periodic OUT channels.
-* If there is at least one High Bandwidth Isochronous OUT endpoint,
-* then the space must be at least two times the maximum packet size for
-* that channel.
-*******************************************************************************/
-
-/****************** USB OTG HS CONFIGURATION **********************************/
-#ifdef USB_OTG_HS_CORE
- #define RX_FIFO_HS_SIZE 512
- #define TX0_FIFO_HS_SIZE 512
- #define TX1_FIFO_HS_SIZE 512
- #define TX2_FIFO_HS_SIZE 0
- #define TX3_FIFO_HS_SIZE 0
- #define TX4_FIFO_HS_SIZE 0
- #define TX5_FIFO_HS_SIZE 0
- #define TXH_NP_HS_FIFOSIZ 96
- #define TXH_P_HS_FIFOSIZ 96
-
- //#define USB_OTG_HS_LOW_PWR_MGMT_SUPPORT
- //#define USB_OTG_HS_SOF_OUTPUT_ENABLED
-
- //#define USB_OTG_INTERNAL_VBUS_ENABLED
- #define USB_OTG_EXTERNAL_VBUS_ENABLED
-
- #ifdef USE_ULPI_PHY
- #define USB_OTG_ULPI_PHY_ENABLED
- #endif
- #ifdef USE_EMBEDDED_PHY
- #define USB_OTG_EMBEDDED_PHY_ENABLED
- #endif
- #ifdef USE_I2C_PHY
- #define USB_OTG_I2C_PHY_ENABLED
- #endif
- #define USB_OTG_HS_INTERNAL_DMA_ENABLED
- #define USB_OTG_HS_DEDICATED_EP1_ENABLED
-#endif
-
-/****************** USB OTG FS CONFIGURATION **********************************/
-#ifdef USB_OTG_FS_CORE
- #define RX_FIFO_FS_SIZE 128
- #define TX0_FIFO_FS_SIZE 64
- #define TX1_FIFO_FS_SIZE 128
- #define TX2_FIFO_FS_SIZE 0
- #define TX3_FIFO_FS_SIZE 0
- #define TXH_NP_HS_FIFOSIZ 96
- #define TXH_P_HS_FIFOSIZ 96
-
- //#define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
- //#define USB_OTG_FS_SOF_OUTPUT_ENABLED
-#endif
-
-/****************** USB OTG MODE CONFIGURATION ********************************/
-//#define USE_HOST_MODE
-#define USE_DEVICE_MODE
-//#define USE_OTG_MODE
-
-
-#ifndef USB_OTG_FS_CORE
- #ifndef USB_OTG_HS_CORE
- #error "USB_OTG_HS_CORE or USB_OTG_FS_CORE should be defined"
- #endif
-#endif
-
-
-#ifndef USE_DEVICE_MODE
- #ifndef USE_HOST_MODE
- #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
- #endif
-#endif
-
-#ifndef USE_USB_OTG_HS
- #ifndef USE_USB_OTG_FS
- #error "USE_USB_OTG_HS or USE_USB_OTG_FS should be defined"
- #endif
-#else //USE_USB_OTG_HS
- #ifndef USE_ULPI_PHY
- #ifndef USE_EMBEDDED_PHY
- #ifndef USE_I2C_PHY
- #error "USE_ULPI_PHY or USE_EMBEDDED_PHY or USE_I2C_PHY should be defined"
- #endif
- #endif
- #endif
-#endif
-
-/****************** C Compilers dependant keywords ****************************/
-/* In HS mode and when the DMA is used, all variables and data structures dealing
- with the DMA during the transaction process should be 4-bytes aligned */
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined (__GNUC__) /* GNU Compiler */
- #define __ALIGN_END __attribute__ ((aligned (4)))
- #define __ALIGN_BEGIN
- #else
- #define __ALIGN_END
- #if defined (__CC_ARM) /* ARM Compiler */
- #define __ALIGN_BEGIN __align(4)
- #elif defined (__ICCARM__) /* IAR Compiler */
- #define __ALIGN_BEGIN
- #elif defined (__TASKING__) /* TASKING Compiler */
- #define __ALIGN_BEGIN __align(4)
- #endif /* __CC_ARM */
- #endif /* __GNUC__ */
-#else
- #define __ALIGN_BEGIN
- #define __ALIGN_END
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-
-/* __packed keyword used to decrease the data type alignment to 1-byte */
-#if defined (__CC_ARM) /* ARM Compiler */
- #define __packed __packed
-#elif defined (__ICCARM__) /* IAR Compiler */
- #define __packed __packed
-#elif defined ( __GNUC__ ) /* GNU Compiler */
- #define __packed __attribute__ ((__packed__))
-#elif defined (__TASKING__) /* TASKING Compiler */
- #define __packed __unaligned
-#endif /* __CC_ARM */
-
-/**
- * @}
- */
-
-
-/** @defgroup USB_CONF_Exported_Types
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_CONF_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_CONF_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_CONF_Exported_FunctionsPrototype
- * @{
- */
-/**
- * @}
- */
-
-
-#endif //__USB_CONF__H__
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_core.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Header of the Core Layer
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_CORE_H__
-#define __USB_CORE_H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_conf.h"
-#include "usb_regs.h"
-#include "usb_defines.h"
-
-
-/** @addtogroup USB_OTG_DRIVER
- * @{
- */
-
-/** @defgroup USB_CORE
- * @brief usb otg driver core layer
- * @{
- */
-
-
-/** @defgroup USB_CORE_Exported_Defines
- * @{
- */
-
-#define USB_OTG_EP0_IDLE 0
-#define USB_OTG_EP0_SETUP 1
-#define USB_OTG_EP0_DATA_IN 2
-#define USB_OTG_EP0_DATA_OUT 3
-#define USB_OTG_EP0_STATUS_IN 4
-#define USB_OTG_EP0_STATUS_OUT 5
-#define USB_OTG_EP0_STALL 6
-
-#define USB_OTG_EP_TX_DIS 0x0000
-#define USB_OTG_EP_TX_STALL 0x0010
-#define USB_OTG_EP_TX_NAK 0x0020
-#define USB_OTG_EP_TX_VALID 0x0030
-
-#define USB_OTG_EP_RX_DIS 0x0000
-#define USB_OTG_EP_RX_STALL 0x1000
-#define USB_OTG_EP_RX_NAK 0x2000
-#define USB_OTG_EP_RX_VALID 0x3000
-/**
- * @}
- */
-#define MAX_DATA_LENGTH 0xFF
-
-/** @defgroup USB_CORE_Exported_Types
- * @{
- */
-
-
-typedef enum {
- USB_OTG_OK = 0,
- USB_OTG_FAIL
-}USB_OTG_STS;
-
-typedef enum {
- HC_IDLE = 0,
- HC_XFRC,
- HC_HALTED,
- HC_NAK,
- HC_NYET,
- HC_STALL,
- HC_XACTERR,
- HC_BBLERR,
- HC_DATATGLERR,
-}HC_STATUS;
-
-typedef enum {
- URB_IDLE = 0,
- URB_DONE,
- URB_NOTREADY,
- URB_ERROR,
- URB_STALL
-}URB_STATE;
-
-typedef enum {
- CTRL_START = 0,
- CTRL_XFRC,
- CTRL_HALTED,
- CTRL_NAK,
- CTRL_STALL,
- CTRL_XACTERR,
- CTRL_BBLERR,
- CTRL_DATATGLERR,
- CTRL_FAIL
-}CTRL_STATUS;
-
-
-typedef struct USB_OTG_hc
-{
- uint8_t dev_addr ;
- uint8_t ep_num;
- uint8_t ep_is_in;
- uint8_t speed;
- uint8_t do_ping;
- uint8_t ep_type;
- uint16_t max_packet;
- uint8_t data_pid;
- uint8_t *xfer_buff;
- uint32_t xfer_len;
- uint32_t xfer_count;
- uint8_t toggle_in;
- uint8_t toggle_out;
- uint32_t dma_addr;
-}
-USB_OTG_HC , *PUSB_OTG_HC;
-
-typedef struct USB_OTG_ep
-{
- uint8_t num;
- uint8_t is_in;
- uint8_t is_stall;
- uint8_t type;
- uint8_t data_pid_start;
- uint8_t even_odd_frame;
- uint16_t tx_fifo_num;
- uint32_t maxpacket;
- /* transaction level variables*/
- uint8_t *xfer_buff;
- uint32_t dma_addr;
- uint32_t xfer_len;
- uint32_t xfer_count;
- /* Transfer level variables*/
- uint32_t rem_data_len;
- uint32_t total_data_len;
- uint32_t ctl_data_len;
-
-}
-
-USB_OTG_EP , *PUSB_OTG_EP;
-
-
-
-typedef struct USB_OTG_core_cfg
-{
- uint8_t host_channels;
- uint8_t dev_endpoints;
- uint8_t speed;
- uint8_t dma_enable;
- uint16_t mps;
- uint16_t TotalFifoSize;
- uint8_t phy_itface;
- uint8_t Sof_output;
- uint8_t low_power;
- uint8_t coreID;
-
-}
-USB_OTG_CORE_CFGS, *PUSB_OTG_CORE_CFGS;
-
-
-
-typedef struct usb_setup_req {
-
- uint8_t bmRequest;
- uint8_t bRequest;
- uint16_t wValue;
- uint16_t wIndex;
- uint16_t wLength;
-} USB_SETUP_REQ;
-
-typedef struct _Device_TypeDef
-{
- uint8_t *(*GetDeviceDescriptor)( uint8_t speed , uint16_t *length);
- uint8_t *(*GetLangIDStrDescriptor)( uint8_t speed , uint16_t *length);
- uint8_t *(*GetManufacturerStrDescriptor)( uint8_t speed , uint16_t *length);
- uint8_t *(*GetProductStrDescriptor)( uint8_t speed , uint16_t *length);
- uint8_t *(*GetSerialStrDescriptor)( uint8_t speed , uint16_t *length);
- uint8_t *(*GetConfigurationStrDescriptor)( uint8_t speed , uint16_t *length);
- uint8_t *(*GetInterfaceStrDescriptor)( uint8_t speed , uint16_t *length);
-} USBD_DEVICE, *pUSBD_DEVICE;
-
-typedef struct USB_OTG_hPort
-{
- void (*Disconnect) (void *phost);
- void (*Connect) (void *phost);
- uint8_t ConnStatus;
- uint8_t DisconnStatus;
- uint8_t ConnHandled;
- uint8_t DisconnHandled;
-} USB_OTG_hPort_TypeDef;
-
-typedef struct _Device_cb
-{
- uint8_t (*Init) (void *pdev , uint8_t cfgidx);
- uint8_t (*DeInit) (void *pdev , uint8_t cfgidx);
- /* Control Endpoints*/
- uint8_t (*Setup) (void *pdev , USB_SETUP_REQ *req);
- uint8_t (*EP0_TxSent) (void *pdev );
- uint8_t (*EP0_RxReady) (void *pdev );
- /* Class Specific Endpoints*/
- uint8_t (*DataIn) (void *pdev , uint8_t epnum);
- uint8_t (*DataOut) (void *pdev , uint8_t epnum);
- uint8_t (*SOF) (void *pdev);
- uint8_t (*IsoINIncomplete) (void *pdev);
- uint8_t (*IsoOUTIncomplete) (void *pdev);
-
- uint8_t *(*GetConfigDescriptor)( uint8_t speed , uint16_t *length);
-#ifdef USB_OTG_HS_CORE
- uint8_t *(*GetOtherConfigDescriptor)( uint8_t speed , uint16_t *length);
-#endif
-
-#ifdef USB_SUPPORT_USER_STRING_DESC
- uint8_t *(*GetUsrStrDescriptor)( uint8_t speed ,uint8_t index, uint16_t *length);
-#endif
-
-} USBD_Class_cb_TypeDef;
-
-
-
-typedef struct _USBD_USR_PROP
-{
- void (*Init)(void);
- void (*DeviceReset)(uint8_t speed);
- void (*DeviceConfigured)(void);
- void (*DeviceSuspended)(void);
- void (*DeviceResumed)(void);
-
- void (*DeviceConnected)(void);
- void (*DeviceDisconnected)(void);
-
-}
-USBD_Usr_cb_TypeDef;
-
-typedef struct _DCD
-{
- uint8_t device_config;
- uint8_t device_state;
- uint8_t device_status;
- uint8_t device_address;
- uint32_t DevRemoteWakeup;
- USB_OTG_EP in_ep [USB_OTG_MAX_TX_FIFOS];
- USB_OTG_EP out_ep [USB_OTG_MAX_TX_FIFOS];
- uint8_t setup_packet [8*3];
- USBD_Class_cb_TypeDef *class_cb;
- USBD_Usr_cb_TypeDef *usr_cb;
- USBD_DEVICE *usr_device;
- uint8_t *pConfig_descriptor;
- }
-DCD_DEV , *DCD_PDEV;
-
-
-typedef struct _HCD
-{
- uint8_t Rx_Buffer [MAX_DATA_LENGTH];
- __IO uint32_t ConnSts;
- __IO uint32_t ErrCnt[USB_OTG_MAX_TX_FIFOS];
- __IO uint32_t XferCnt[USB_OTG_MAX_TX_FIFOS];
- __IO HC_STATUS HC_Status[USB_OTG_MAX_TX_FIFOS];
- __IO URB_STATE URB_State[USB_OTG_MAX_TX_FIFOS];
- USB_OTG_HC hc [USB_OTG_MAX_TX_FIFOS];
- uint16_t channel [USB_OTG_MAX_TX_FIFOS];
- USB_OTG_hPort_TypeDef *port_cb;
-}
-HCD_DEV , *USB_OTG_USBH_PDEV;
-
-
-typedef struct _OTG
-{
- uint8_t OTG_State;
- uint8_t OTG_PrevState;
- uint8_t OTG_Mode;
-}
-OTG_DEV , *USB_OTG_USBO_PDEV;
-
-typedef struct USB_OTG_handle
-{
- USB_OTG_CORE_CFGS cfg;
- USB_OTG_CORE_REGS regs;
-#ifdef USE_DEVICE_MODE
- DCD_DEV dev;
-#endif
-#ifdef USE_HOST_MODE
- HCD_DEV host;
-#endif
-#ifdef USE_OTG_MODE
- OTG_DEV otg;
-#endif
-}
-USB_OTG_CORE_HANDLE , *PUSB_OTG_CORE_HANDLE;
-
-/**
- * @}
- */
-
-
-/** @defgroup USB_CORE_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USB_CORE_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_CORE_Exported_FunctionsPrototype
- * @{
- */
-
-
-USB_OTG_STS USB_OTG_CoreInit (USB_OTG_CORE_HANDLE *pdev);
-USB_OTG_STS USB_OTG_SelectCore (USB_OTG_CORE_HANDLE *pdev,
- USB_OTG_CORE_ID_TypeDef coreID);
-USB_OTG_STS USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE *pdev);
-USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev);
-void* USB_OTG_ReadPacket (USB_OTG_CORE_HANDLE *pdev ,
- uint8_t *dest,
- uint16_t len);
-USB_OTG_STS USB_OTG_WritePacket (USB_OTG_CORE_HANDLE *pdev ,
- uint8_t *src,
- uint8_t ch_ep_num,
- uint16_t len);
-USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num);
-USB_OTG_STS USB_OTG_FlushRxFifo (USB_OTG_CORE_HANDLE *pdev);
-
-uint32_t USB_OTG_ReadCoreItr (USB_OTG_CORE_HANDLE *pdev);
-uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev);
-uint8_t USB_OTG_IsHostMode (USB_OTG_CORE_HANDLE *pdev);
-uint8_t USB_OTG_IsDeviceMode (USB_OTG_CORE_HANDLE *pdev);
-uint32_t USB_OTG_GetMode (USB_OTG_CORE_HANDLE *pdev);
-USB_OTG_STS USB_OTG_PhyInit (USB_OTG_CORE_HANDLE *pdev);
-USB_OTG_STS USB_OTG_SetCurrentMode (USB_OTG_CORE_HANDLE *pdev,
- uint8_t mode);
-
-/*********************** HOST APIs ********************************************/
-#ifdef USE_HOST_MODE
-USB_OTG_STS USB_OTG_CoreInitHost (USB_OTG_CORE_HANDLE *pdev);
-USB_OTG_STS USB_OTG_EnableHostInt (USB_OTG_CORE_HANDLE *pdev);
-USB_OTG_STS USB_OTG_HC_Init (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num);
-USB_OTG_STS USB_OTG_HC_Halt (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num);
-USB_OTG_STS USB_OTG_HC_StartXfer (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num);
-USB_OTG_STS USB_OTG_HC_DoPing (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num);
-uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev);
-uint32_t USB_OTG_ResetPort (USB_OTG_CORE_HANDLE *pdev);
-uint32_t USB_OTG_ReadHPRT0 (USB_OTG_CORE_HANDLE *pdev);
-void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state);
-void USB_OTG_InitFSLSPClkSel (USB_OTG_CORE_HANDLE *pdev ,uint8_t freq);
-uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) ;
-void USB_OTG_StopHost (USB_OTG_CORE_HANDLE *pdev);
-#endif
-/********************* DEVICE APIs ********************************************/
-#ifdef USE_DEVICE_MODE
-USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev);
-USB_OTG_STS USB_OTG_EnableDevInt (USB_OTG_CORE_HANDLE *pdev);
-uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev);
-enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev);
-USB_OTG_STS USB_OTG_EP0Activate (USB_OTG_CORE_HANDLE *pdev);
-USB_OTG_STS USB_OTG_EPActivate (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
-USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
-USB_OTG_STS USB_OTG_EPStartXfer (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
-USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
-USB_OTG_STS USB_OTG_EPSetStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
-USB_OTG_STS USB_OTG_EPClearStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
-uint32_t USB_OTG_ReadDevAllOutEp_itr (USB_OTG_CORE_HANDLE *pdev);
-uint32_t USB_OTG_ReadDevOutEP_itr (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum);
-uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev);
-void USB_OTG_InitDevSpeed (USB_OTG_CORE_HANDLE *pdev , uint8_t speed);
-uint8_t USBH_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev);
-void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev);
-void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev);
-void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev);
-void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev);
-void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status);
-uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep);
-#endif
-/**
- * @}
- */
-
-#endif /* __USB_CORE_H__ */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_dcd.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Peripheral Driver Header file
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __DCD_H__
-#define __DCD_H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_core.h"
-
-
-/** @addtogroup USB_OTG_DRIVER
-* @{
-*/
-
-/** @defgroup USB_DCD
-* @brief This file is the
-* @{
-*/
-
-
-/** @defgroup USB_DCD_Exported_Defines
-* @{
-*/
-#define USB_OTG_EP_CONTROL 0
-#define USB_OTG_EP_ISOC 1
-#define USB_OTG_EP_BULK 2
-#define USB_OTG_EP_INT 3
-#define USB_OTG_EP_MASK 3
-
-/* Device Status */
-#define USB_OTG_DEFAULT 1
-#define USB_OTG_ADDRESSED 2
-#define USB_OTG_CONFIGURED 3
-#define USB_OTG_SUSPENDED 4
-
-/**
-* @}
-*/
-
-
-/** @defgroup USB_DCD_Exported_Types
-* @{
-*/
-/********************************************************************************
-Data structure type
-********************************************************************************/
-typedef struct
-{
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint8_t bEndpointAddress;
- uint8_t bmAttributes;
- uint16_t wMaxPacketSize;
- uint8_t bInterval;
-}
-EP_DESCRIPTOR , *PEP_DESCRIPTOR;
-
-/**
-* @}
-*/
-
-
-/** @defgroup USB_DCD_Exported_Macros
-* @{
-*/
-/**
-* @}
-*/
-
-/** @defgroup USB_DCD_Exported_Variables
-* @{
-*/
-/**
-* @}
-*/
-
-/** @defgroup USB_DCD_Exported_FunctionsPrototype
-* @{
-*/
-/********************************************************************************
-EXPORTED FUNCTION FROM THE USB-OTG LAYER
-********************************************************************************/
-void DCD_Init(USB_OTG_CORE_HANDLE *pdev ,
- USB_OTG_CORE_ID_TypeDef coreID);
-
-void DCD_DevConnect (USB_OTG_CORE_HANDLE *pdev);
-void DCD_DevDisconnect (USB_OTG_CORE_HANDLE *pdev);
-void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev,
- uint8_t address);
-uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev ,
- uint8_t ep_addr,
- uint16_t ep_mps,
- uint8_t ep_type);
-
-uint32_t DCD_EP_Close (USB_OTG_CORE_HANDLE *pdev,
- uint8_t ep_addr);
-
-
-uint32_t DCD_EP_PrepareRx ( USB_OTG_CORE_HANDLE *pdev,
- uint8_t ep_addr,
- uint8_t *pbuf,
- uint16_t buf_len);
-
-uint32_t DCD_EP_Tx (USB_OTG_CORE_HANDLE *pdev,
- uint8_t ep_addr,
- uint8_t *pbuf,
- uint32_t buf_len);
-uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev,
- uint8_t epnum);
-uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev,
- uint8_t epnum);
-uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev,
- uint8_t epnum);
-uint32_t DCD_Handle_ISR(USB_OTG_CORE_HANDLE *pdev);
-
-uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,
- uint8_t epnum);
-
-void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev ,
- uint8_t epnum ,
- uint32_t Status);
-
-/**
-* @}
-*/
-
-
-#endif //__DCD_H__
-
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_dcd_int.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Peripheral Device Interface Layer
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef USB_DCD_INT_H__
-#define USB_DCD_INT_H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_dcd.h"
-
-
-
-/** @addtogroup USB_OTG_DRIVER
- * @{
- */
-
-/** @defgroup USB_DCD_INT
- * @brief This file is the
- * @{
- */
-
-
-/** @defgroup USB_DCD_INT_Exported_Defines
- * @{
- */
-
-typedef struct _USBD_DCD_INT
-{
- uint8_t (* DataOutStage) (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum);
- uint8_t (* DataInStage) (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum);
- uint8_t (* SetupStage) (USB_OTG_CORE_HANDLE *pdev);
- uint8_t (* SOF) (USB_OTG_CORE_HANDLE *pdev);
- uint8_t (* Reset) (USB_OTG_CORE_HANDLE *pdev);
- uint8_t (* Suspend) (USB_OTG_CORE_HANDLE *pdev);
- uint8_t (* Resume) (USB_OTG_CORE_HANDLE *pdev);
- uint8_t (* IsoINIncomplete) (USB_OTG_CORE_HANDLE *pdev);
- uint8_t (* IsoOUTIncomplete) (USB_OTG_CORE_HANDLE *pdev);
-
- uint8_t (* DevConnected) (USB_OTG_CORE_HANDLE *pdev);
- uint8_t (* DevDisconnected) (USB_OTG_CORE_HANDLE *pdev);
-
-}USBD_DCD_INT_cb_TypeDef;
-
-extern USBD_DCD_INT_cb_TypeDef *USBD_DCD_INT_fops;
-/**
- * @}
- */
-
-
-/** @defgroup USB_DCD_INT_Exported_Types
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_DCD_INT_Exported_Macros
- * @{
- */
-
-#define CLEAR_IN_EP_INTR(epnum,intr) \
- diepint.d32=0; \
- diepint.b.intr = 1; \
- USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT,diepint.d32);
-
-#define CLEAR_OUT_EP_INTR(epnum,intr) \
- doepint.d32=0; \
- doepint.b.intr = 1; \
- USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT,doepint.d32);
-
-/**
- * @}
- */
-
-/** @defgroup USB_DCD_INT_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_DCD_INT_Exported_FunctionsPrototype
- * @{
- */
-
-uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev);
-
-/**
- * @}
- */
-
-
-#endif // USB_DCD_INT_H__
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_defines.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Header of the Core Layer
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_DEF_H__
-#define __USB_DEF_H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_conf.h"
-
-/** @addtogroup USB_OTG_DRIVER
- * @{
- */
-
-/** @defgroup USB_DEFINES
- * @brief This file is the
- * @{
- */
-
-
-/** @defgroup USB_DEFINES_Exported_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup _CORE_DEFINES_
- * @{
- */
-
-#define USB_OTG_SPEED_PARAM_HIGH 0
-#define USB_OTG_SPEED_PARAM_HIGH_IN_FULL 1
-#define USB_OTG_SPEED_PARAM_FULL 3
-
-#define USB_OTG_SPEED_HIGH 0
-#define USB_OTG_SPEED_FULL 1
-
-#define USB_OTG_ULPI_PHY 1
-#define USB_OTG_EMBEDDED_PHY 2
-#define USB_OTG_I2C_PHY 3
-
-/**
- * @}
- */
-
-
-/** @defgroup _GLOBAL_DEFINES_
- * @{
- */
-#define GAHBCFG_TXFEMPTYLVL_EMPTY 1
-#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
-#define GAHBCFG_GLBINT_ENABLE 1
-#define GAHBCFG_INT_DMA_BURST_SINGLE 0
-#define GAHBCFG_INT_DMA_BURST_INCR 1
-#define GAHBCFG_INT_DMA_BURST_INCR4 3
-#define GAHBCFG_INT_DMA_BURST_INCR8 5
-#define GAHBCFG_INT_DMA_BURST_INCR16 7
-#define GAHBCFG_DMAENABLE 1
-#define GAHBCFG_TXFEMPTYLVL_EMPTY 1
-#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
-#define GRXSTS_PKTSTS_IN 2
-#define GRXSTS_PKTSTS_IN_XFER_COMP 3
-#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5
-#define GRXSTS_PKTSTS_CH_HALTED 7
-/**
- * @}
- */
-
-
-/** @defgroup _OnTheGo_DEFINES_
- * @{
- */
-#define MODE_HNP_SRP_CAPABLE 0
-#define MODE_SRP_ONLY_CAPABLE 1
-#define MODE_NO_HNP_SRP_CAPABLE 2
-#define MODE_SRP_CAPABLE_DEVICE 3
-#define MODE_NO_SRP_CAPABLE_DEVICE 4
-#define MODE_SRP_CAPABLE_HOST 5
-#define MODE_NO_SRP_CAPABLE_HOST 6
-#define A_HOST 1
-#define A_SUSPEND 2
-#define A_PERIPHERAL 3
-#define B_PERIPHERAL 4
-#define B_HOST 5
-#define DEVICE_MODE 0
-#define HOST_MODE 1
-#define OTG_MODE 2
-/**
- * @}
- */
-
-
-/** @defgroup __DEVICE_DEFINES_
- * @{
- */
-#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
-#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
-#define DSTS_ENUMSPD_LS_PHY_6MHZ 2
-#define DSTS_ENUMSPD_FS_PHY_48MHZ 3
-
-#define DCFG_FRAME_INTERVAL_80 0
-#define DCFG_FRAME_INTERVAL_85 1
-#define DCFG_FRAME_INTERVAL_90 2
-#define DCFG_FRAME_INTERVAL_95 3
-
-#define DEP0CTL_MPS_64 0
-#define DEP0CTL_MPS_32 1
-#define DEP0CTL_MPS_16 2
-#define DEP0CTL_MPS_8 3
-
-#define EP_SPEED_LOW 0
-#define EP_SPEED_FULL 1
-#define EP_SPEED_HIGH 2
-
-#define EP_TYPE_CTRL 0
-#define EP_TYPE_ISOC 1
-#define EP_TYPE_BULK 2
-#define EP_TYPE_INTR 3
-#define EP_TYPE_MSK 3
-
-#define STS_GOUT_NAK 1
-#define STS_DATA_UPDT 2
-#define STS_XFER_COMP 3
-#define STS_SETUP_COMP 4
-#define STS_SETUP_UPDT 6
-/**
- * @}
- */
-
-
-/** @defgroup __HOST_DEFINES_
- * @{
- */
-#define HC_PID_DATA0 0
-#define HC_PID_DATA2 1
-#define HC_PID_DATA1 2
-#define HC_PID_SETUP 3
-
-#define HPRT0_PRTSPD_HIGH_SPEED 0
-#define HPRT0_PRTSPD_FULL_SPEED 1
-#define HPRT0_PRTSPD_LOW_SPEED 2
-
-#define HCFG_30_60_MHZ 0
-#define HCFG_48_MHZ 1
-#define HCFG_6_MHZ 2
-
-#define HCCHAR_CTRL 0
-#define HCCHAR_ISOC 1
-#define HCCHAR_BULK 2
-#define HCCHAR_INTR 3
-
-#define MIN(a, b) (((a) < (b)) ? (a) : (b))
-
-/**
- * @}
- */
-
-
-/** @defgroup USB_DEFINES_Exported_Types
- * @{
- */
-
-typedef enum
-{
- USB_OTG_HS_CORE_ID = 0,
- USB_OTG_FS_CORE_ID = 1
-}USB_OTG_CORE_ID_TypeDef;
-/**
- * @}
- */
-
-
-/** @defgroup USB_DEFINES_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_DEFINES_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_DEFINES_Exported_FunctionsPrototype
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup Internal_Macro's
- * @{
- */
-#define USB_OTG_READ_REG32(reg) (*(__IO uint32_t *)reg)
-#define USB_OTG_WRITE_REG32(reg,value) (*(__IO uint32_t *)reg = value)
-#define USB_OTG_MODIFY_REG32(reg,clear_mask,set_mask) \
- USB_OTG_WRITE_REG32(reg, (((USB_OTG_READ_REG32(reg)) & ~clear_mask) | set_mask ) )
-
-/********************************************************************************
- ENUMERATION TYPE
-********************************************************************************/
-enum USB_OTG_SPEED {
- USB_SPEED_UNKNOWN = 0,
- USB_SPEED_LOW,
- USB_SPEED_FULL,
- USB_SPEED_HIGH
-};
-
-#endif //__USB_DEFINES__H__
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_hcd.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Host layer Header file
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_HCD_H__
-#define __USB_HCD_H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_regs.h"
-#include "usb_core.h"
-
-
-/** @addtogroup USB_OTG_DRIVER
- * @{
- */
-
-/** @defgroup USB_HCD
- * @brief This file is the
- * @{
- */
-
-
-/** @defgroup USB_HCD_Exported_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_HCD_Exported_Types
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_HCD_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_HCD_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_HCD_Exported_FunctionsPrototype
- * @{
- */
-uint32_t HCD_Init (USB_OTG_CORE_HANDLE *pdev ,
- USB_OTG_CORE_ID_TypeDef coreID);
-uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev ,
- uint8_t hc_num);
-uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev ,
- uint8_t hc_num) ;
-uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev);
-uint32_t HCD_ResetPort (USB_OTG_CORE_HANDLE *pdev);
-uint32_t HCD_IsDeviceConnected (USB_OTG_CORE_HANDLE *pdev);
-uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev) ;
-URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num);
-uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num);
-HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num) ;
-/**
- * @}
- */
-
-#endif //__USB_HCD_H__
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_hcd_int.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Peripheral Device Interface Layer
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __HCD_INT_H__
-#define __HCD_INT_H__
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_hcd.h"
-
-
-/** @addtogroup USB_OTG_DRIVER
- * @{
- */
-
-/** @defgroup USB_HCD_INT
- * @brief This file is the
- * @{
- */
-
-
-/** @defgroup USB_HCD_INT_Exported_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_HCD_INT_Exported_Types
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_HCD_INT_Exported_Macros
- * @{
- */
-
-#define CLEAR_HC_INT(HC_REGS, intr) \
- {\
- USB_OTG_HCINTn_TypeDef hcint_clear; \
- hcint_clear.d32 = 0; \
- hcint_clear.b.intr = 1; \
- USB_OTG_WRITE_REG32(&((HC_REGS)->HCINT), hcint_clear.d32);\
- }\
-
-#define MASK_HOST_INT_CHH(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
- GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
- GINTMSK.b.chhltd = 0; \
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
-
-#define UNMASK_HOST_INT_CHH(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
- GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
- GINTMSK.b.chhltd = 1; \
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
-
-#define MASK_HOST_INT_ACK(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
- GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
- GINTMSK.b.ack = 0; \
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
-
-#define UNMASK_HOST_INT_ACK(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
- GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
- GINTMSK.b.ack = 1; \
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
-
-/**
- * @}
- */
-
-/** @defgroup USB_HCD_INT_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_HCD_INT_Exported_FunctionsPrototype
- * @{
- */
-/* Callbacks handler */
-void ConnectCallback_Handler(USB_OTG_CORE_HANDLE *pdev);
-void Disconnect_Callback_Handler(USB_OTG_CORE_HANDLE *pdev);
-void Overcurrent_Callback_Handler(USB_OTG_CORE_HANDLE *pdev);
-uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev);
-
-/**
- * @}
- */
-
-
-
-#endif //__HCD_INT_H__
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_otg.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief OTG Core Header
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_OTG__
-#define __USB_OTG__
-
-
-/** @addtogroup USB_OTG_DRIVER
- * @{
- */
-
-/** @defgroup USB_OTG
- * @brief This file is the
- * @{
- */
-
-
-/** @defgroup USB_OTG_Exported_Defines
- * @{
- */
-
-
-void USB_OTG_InitiateSRP(void);
-void USB_OTG_InitiateHNP(uint8_t state , uint8_t mode);
-void USB_OTG_Switchback (USB_OTG_CORE_HANDLE *pdev);
-uint32_t USB_OTG_GetCurrentState (USB_OTG_CORE_HANDLE *pdev);
-
-uint32_t STM32_USBO_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev);
-/**
- * @}
- */
-
-
-/** @defgroup USB_OTG_Exported_Types
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_OTG_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_OTG_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_OTG_Exported_FunctionsPrototype
- * @{
- */
-/**
- * @}
- */
-
-
-#endif //__USB_OTG__
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_regs.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief hardware registers
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_OTG_REGS_H__
-#define __USB_OTG_REGS_H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_conf.h"
-
-
-/** @addtogroup USB_OTG_DRIVER
- * @{
- */
-
-/** @defgroup USB_REGS
- * @brief This file is the
- * @{
- */
-
-
-/** @defgroup USB_REGS_Exported_Defines
- * @{
- */
-
-#define USB_OTG_HS_BASE_ADDR 0x40040000
-#define USB_OTG_FS_BASE_ADDR 0x50000000
-
-#define USB_OTG_CORE_GLOBAL_REGS_OFFSET 0x000
-#define USB_OTG_DEV_GLOBAL_REG_OFFSET 0x800
-#define USB_OTG_DEV_IN_EP_REG_OFFSET 0x900
-#define USB_OTG_EP_REG_OFFSET 0x20
-#define USB_OTG_DEV_OUT_EP_REG_OFFSET 0xB00
-#define USB_OTG_HOST_GLOBAL_REG_OFFSET 0x400
-#define USB_OTG_HOST_PORT_REGS_OFFSET 0x440
-#define USB_OTG_HOST_CHAN_REGS_OFFSET 0x500
-#define USB_OTG_CHAN_REGS_OFFSET 0x20
-#define USB_OTG_PCGCCTL_OFFSET 0xE00
-#define USB_OTG_DATA_FIFO_OFFSET 0x1000
-#define USB_OTG_DATA_FIFO_SIZE 0x1000
-
-
-#define USB_OTG_MAX_TX_FIFOS 15
-
-#define USB_OTG_HS_MAX_PACKET_SIZE 512
-#define USB_OTG_FS_MAX_PACKET_SIZE 64
-#define USB_OTG_MAX_EP0_SIZE 64
-/**
- * @}
- */
-
-/** @defgroup USB_REGS_Exported_Types
- * @{
- */
-
-/** @defgroup __USB_OTG_Core_register
- * @{
- */
-typedef struct _USB_OTG_GREGS //000h
-{
- __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
- __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
- __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
- __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
- __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
- __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
- __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
- __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
- __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
- __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
- __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
- __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
- __IO uint32_t GI2CCTL; /* I2C Access Register 030h*/
- uint32_t Reserved34; /* PHY Vendor Control Register 034h*/
- __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
- __IO uint32_t CID; /* User ID Register 03Ch*/
- uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
- __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
- __IO uint32_t DIEPTXF[USB_OTG_MAX_TX_FIFOS];/* dev Periodic Transmit FIFO */
-}
-USB_OTG_GREGS;
-/**
- * @}
- */
-
-
-/** @defgroup __device_Registers
- * @{
- */
-typedef struct _USB_OTG_DREGS // 800h
-{
- __IO uint32_t DCFG; /* dev Configuration Register 800h*/
- __IO uint32_t DCTL; /* dev Control Register 804h*/
- __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
- uint32_t Reserved0C; /* Reserved 80Ch*/
- __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
- __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
- __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
- __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
- uint32_t Reserved20; /* Reserved 820h*/
- uint32_t Reserved9; /* Reserved 824h*/
- __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
- __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
- __IO uint32_t DTHRCTL; /* dev thr 830h*/
- __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
- __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
- __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
- uint32_t Reserved40; /* dedicated EP mask 840h*/
- __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
- uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
- __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
-}
-USB_OTG_DREGS;
-/**
- * @}
- */
-
-
-/** @defgroup __IN_Endpoint-Specific_Register
- * @{
- */
-typedef struct _USB_OTG_INEPREGS
-{
- __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
- uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
- __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
- uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
- __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
- __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
- __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
- uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_INEPREGS;
-/**
- * @}
- */
-
-
-/** @defgroup __OUT_Endpoint-Specific_Registers
- * @{
- */
-typedef struct _USB_OTG_OUTEPREGS
-{
- __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
- __IO uint32_t DOUTEPFRM; /* dev OUT Endpoint Frame number B00h + (ep_num * 20h) + 04h*/
- __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
- uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
- __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
- __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
- uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_OUTEPREGS;
-/**
- * @}
- */
-
-
-/** @defgroup __Host_Mode_Register_Structures
- * @{
- */
-typedef struct _USB_OTG_HREGS
-{
- __IO uint32_t HCFG; /* Host Configuration Register 400h*/
- __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
- __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
- uint32_t Reserved40C; /* Reserved 40Ch*/
- __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
- __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
- __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
-}
-USB_OTG_HREGS;
-/**
- * @}
- */
-
-
-/** @defgroup __Host_Channel_Specific_Registers
- * @{
- */
-typedef struct _USB_OTG_HC_REGS
-{
- __IO uint32_t HCCHAR;
- __IO uint32_t HCSPLT;
- __IO uint32_t HCINT;
- __IO uint32_t HCGINTMSK;
- __IO uint32_t HCTSIZ;
- __IO uint32_t HCDMA;
- uint32_t Reserved[2];
-}
-USB_OTG_HC_REGS;
-/**
- * @}
- */
-
-
-/** @defgroup __otg_Core_registers
- * @{
- */
-typedef struct USB_OTG_core_regs //000h
-{
- USB_OTG_GREGS *GREGS;
- USB_OTG_DREGS *DREGS;
- USB_OTG_HREGS *HREGS;
- USB_OTG_INEPREGS *INEP_REGS[USB_OTG_MAX_TX_FIFOS];
- USB_OTG_OUTEPREGS *OUTEP_REGS[USB_OTG_MAX_TX_FIFOS];
- USB_OTG_HC_REGS *HC_REGS[USB_OTG_MAX_TX_FIFOS];
- __IO uint32_t *HPRT0;
- __IO uint32_t *DFIFO[USB_OTG_MAX_TX_FIFOS];
- __IO uint32_t *PCGCCTL;
-}
-USB_OTG_CORE_REGS , *PUSB_OTG_CORE_REGS;
-typedef union _USB_OTG_OTGCTL_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t sesreqscs :
- 1;
-uint32_t sesreq :
- 1;
-uint32_t Reserved2_7 :
- 6;
-uint32_t hstnegscs :
- 1;
-uint32_t hnpreq :
- 1;
-uint32_t hstsethnpen :
- 1;
-uint32_t devhnpen :
- 1;
-uint32_t Reserved12_15 :
- 4;
-uint32_t conidsts :
- 1;
-uint32_t Reserved17 :
- 1;
-uint32_t asesvld :
- 1;
-uint32_t bsesvld :
- 1;
-uint32_t currmod :
- 1;
-uint32_t Reserved21_31 :
- 11;
- }
- b;
-} USB_OTG_OTGCTL_TypeDef ;
-typedef union _USB_OTG_GOTGINT_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t Reserved0_1 :
- 2;
-uint32_t sesenddet :
- 1;
-uint32_t Reserved3_7 :
- 5;
-uint32_t sesreqsucstschng :
- 1;
-uint32_t hstnegsucstschng :
- 1;
-uint32_t reserver10_16 :
- 7;
-uint32_t hstnegdet :
- 1;
-uint32_t adevtoutchng :
- 1;
-uint32_t debdone :
- 1;
-uint32_t Reserved31_20 :
- 12;
- }
- b;
-} USB_OTG_GOTGINT_TypeDef ;
-typedef union _USB_OTG_GAHBCFG_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t glblintrmsk :
- 1;
-uint32_t hburstlen :
- 4;
-uint32_t dmaenable :
- 1;
-uint32_t Reserved :
- 1;
-uint32_t nptxfemplvl_txfemplvl :
- 1;
-uint32_t ptxfemplvl :
- 1;
-uint32_t Reserved9_31 :
- 23;
- }
- b;
-} USB_OTG_GAHBCFG_TypeDef ;
-typedef union _USB_OTG_GUSBCFG_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t toutcal :
- 3;
-uint32_t phyif :
- 1;
-uint32_t ulpi_utmi_sel :
- 1;
-uint32_t fsintf :
- 1;
-uint32_t physel :
- 1;
-uint32_t ddrsel :
- 1;
-uint32_t srpcap :
- 1;
-uint32_t hnpcap :
- 1;
-uint32_t usbtrdtim :
- 4;
-uint32_t nptxfrwnden :
- 1;
-uint32_t phylpwrclksel :
- 1;
-uint32_t otgutmifssel :
- 1;
-uint32_t ulpi_fsls :
- 1;
-uint32_t ulpi_auto_res :
- 1;
-uint32_t ulpi_clk_sus_m :
- 1;
-uint32_t ulpi_ext_vbus_drv :
- 1;
-uint32_t ulpi_int_vbus_indicator :
- 1;
-uint32_t term_sel_dl_pulse :
- 1;
-uint32_t Reserved :
- 6;
-uint32_t force_host :
- 1;
-uint32_t force_dev :
- 1;
-uint32_t corrupt_tx :
- 1;
- }
- b;
-} USB_OTG_GUSBCFG_TypeDef ;
-typedef union _USB_OTG_GRSTCTL_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t csftrst :
- 1;
-uint32_t hsftrst :
- 1;
-uint32_t hstfrm :
- 1;
-uint32_t intknqflsh :
- 1;
-uint32_t rxfflsh :
- 1;
-uint32_t txfflsh :
- 1;
-uint32_t txfnum :
- 5;
-uint32_t Reserved11_29 :
- 19;
-uint32_t dmareq :
- 1;
-uint32_t ahbidle :
- 1;
- }
- b;
-} USB_OTG_GRSTCTL_TypeDef ;
-typedef union _USB_OTG_GINTMSK_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t Reserved0 :
- 1;
-uint32_t modemismatch :
- 1;
-uint32_t otgintr :
- 1;
-uint32_t sofintr :
- 1;
-uint32_t rxstsqlvl :
- 1;
-uint32_t nptxfempty :
- 1;
-uint32_t ginnakeff :
- 1;
-uint32_t goutnakeff :
- 1;
-uint32_t Reserved8 :
- 1;
-uint32_t i2cintr :
- 1;
-uint32_t erlysuspend :
- 1;
-uint32_t usbsuspend :
- 1;
-uint32_t usbreset :
- 1;
-uint32_t enumdone :
- 1;
-uint32_t isooutdrop :
- 1;
-uint32_t eopframe :
- 1;
-uint32_t Reserved16 :
- 1;
-uint32_t epmismatch :
- 1;
-uint32_t inepintr :
- 1;
-uint32_t outepintr :
- 1;
-uint32_t incomplisoin :
- 1;
-uint32_t incomplisoout :
- 1;
-uint32_t Reserved22_23 :
- 2;
-uint32_t portintr :
- 1;
-uint32_t hcintr :
- 1;
-uint32_t ptxfempty :
- 1;
-uint32_t Reserved27 :
- 1;
-uint32_t conidstschng :
- 1;
-uint32_t disconnect :
- 1;
-uint32_t sessreqintr :
- 1;
-uint32_t wkupintr :
- 1;
- }
- b;
-} USB_OTG_GINTMSK_TypeDef ;
-typedef union _USB_OTG_GINTSTS_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t curmode :
- 1;
-uint32_t modemismatch :
- 1;
-uint32_t otgintr :
- 1;
-uint32_t sofintr :
- 1;
-uint32_t rxstsqlvl :
- 1;
-uint32_t nptxfempty :
- 1;
-uint32_t ginnakeff :
- 1;
-uint32_t goutnakeff :
- 1;
-uint32_t Reserved8 :
- 1;
-uint32_t i2cintr :
- 1;
-uint32_t erlysuspend :
- 1;
-uint32_t usbsuspend :
- 1;
-uint32_t usbreset :
- 1;
-uint32_t enumdone :
- 1;
-uint32_t isooutdrop :
- 1;
-uint32_t eopframe :
- 1;
-uint32_t intimerrx :
- 1;
-uint32_t epmismatch :
- 1;
-uint32_t inepint:
- 1;
-uint32_t outepintr :
- 1;
-uint32_t incomplisoin :
- 1;
-uint32_t incomplisoout :
- 1;
-uint32_t Reserved22_23 :
- 2;
-uint32_t portintr :
- 1;
-uint32_t hcintr :
- 1;
-uint32_t ptxfempty :
- 1;
-uint32_t Reserved27 :
- 1;
-uint32_t conidstschng :
- 1;
-uint32_t disconnect :
- 1;
-uint32_t sessreqintr :
- 1;
-uint32_t wkupintr :
- 1;
- }
- b;
-} USB_OTG_GINTSTS_TypeDef ;
-typedef union _USB_OTG_DRXSTS_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t epnum :
- 4;
-uint32_t bcnt :
- 11;
-uint32_t dpid :
- 2;
-uint32_t pktsts :
- 4;
-uint32_t fn :
- 4;
-uint32_t Reserved :
- 7;
- }
- b;
-} USB_OTG_DRXSTS_TypeDef ;
-typedef union _USB_OTG_GRXSTS_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t chnum :
- 4;
-uint32_t bcnt :
- 11;
-uint32_t dpid :
- 2;
-uint32_t pktsts :
- 4;
-uint32_t Reserved :
- 11;
- }
- b;
-} USB_OTG_GRXFSTS_TypeDef ;
-typedef union _USB_OTG_FSIZ_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t startaddr :
- 16;
-uint32_t depth :
- 16;
- }
- b;
-} USB_OTG_FSIZ_TypeDef ;
-typedef union _USB_OTG_HNPTXSTS_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t nptxfspcavail :
- 16;
-uint32_t nptxqspcavail :
- 8;
-uint32_t nptxqtop_terminate :
- 1;
-uint32_t nptxqtop_timer :
- 2;
-uint32_t nptxqtop :
- 2;
-uint32_t chnum :
- 2;
-uint32_t Reserved :
- 1;
- }
- b;
-} USB_OTG_HNPTXSTS_TypeDef ;
-typedef union _USB_OTG_DTXFSTSn_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t txfspcavail :
- 16;
-uint32_t Reserved :
- 16;
- }
- b;
-} USB_OTG_DTXFSTSn_TypeDef ;
-typedef union _USB_OTG_GI2CCTL_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t rwdata :
- 8;
-uint32_t regaddr :
- 8;
-uint32_t addr :
- 7;
-uint32_t i2cen :
- 1;
-uint32_t ack :
- 1;
-uint32_t i2csuspctl :
- 1;
-uint32_t i2cdevaddr :
- 2;
-uint32_t dat_se0:
- 1;
-uint32_t Reserved :
- 1;
-uint32_t rw :
- 1;
-uint32_t bsydne :
- 1;
- }
- b;
-} USB_OTG_GI2CCTL_TypeDef ;
-typedef union _USB_OTG_GCCFG_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t Reserved_in :
- 16;
-uint32_t pwdn :
- 1;
-uint32_t i2cifen :
- 1;
-uint32_t vbussensingA :
- 1;
-uint32_t vbussensingB :
- 1;
-uint32_t sofouten :
- 1;
-uint32_t disablevbussensing :
- 1;
-uint32_t Reserved_out :
- 10;
- }
- b;
-} USB_OTG_GCCFG_TypeDef ;
-
-typedef union _USB_OTG_DCFG_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t devspd :
- 2;
-uint32_t nzstsouthshk :
- 1;
-uint32_t Reserved3 :
- 1;
-uint32_t devaddr :
- 7;
-uint32_t perfrint :
- 2;
-uint32_t Reserved13_17 :
- 5;
-uint32_t epmscnt :
- 4;
- }
- b;
-} USB_OTG_DCFG_TypeDef ;
-typedef union _USB_OTG_DCTL_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t rmtwkupsig :
- 1;
-uint32_t sftdiscon :
- 1;
-uint32_t gnpinnaksts :
- 1;
-uint32_t goutnaksts :
- 1;
-uint32_t tstctl :
- 3;
-uint32_t sgnpinnak :
- 1;
-uint32_t cgnpinnak :
- 1;
-uint32_t sgoutnak :
- 1;
-uint32_t cgoutnak :
- 1;
-uint32_t Reserved :
- 21;
- }
- b;
-} USB_OTG_DCTL_TypeDef ;
-typedef union _USB_OTG_DSTS_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t suspsts :
- 1;
-uint32_t enumspd :
- 2;
-uint32_t errticerr :
- 1;
-uint32_t Reserved4_7:
- 4;
-uint32_t soffn :
- 14;
-uint32_t Reserved22_31 :
- 10;
- }
- b;
-} USB_OTG_DSTS_TypeDef ;
-typedef union _USB_OTG_DIEPINTn_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t xfercompl :
- 1;
-uint32_t epdisabled :
- 1;
-uint32_t ahberr :
- 1;
-uint32_t timeout :
- 1;
-uint32_t intktxfemp :
- 1;
-uint32_t intknepmis :
- 1;
-uint32_t inepnakeff :
- 1;
-uint32_t emptyintr :
- 1;
-uint32_t txfifoundrn :
- 1;
-uint32_t Reserved08_31 :
- 23;
- }
- b;
-} USB_OTG_DIEPINTn_TypeDef ;
-typedef union _USB_OTG_DIEPINTn_TypeDef USB_OTG_DIEPMSK_TypeDef ;
-typedef union _USB_OTG_DOEPINTn_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t xfercompl :
- 1;
-uint32_t epdisabled :
- 1;
-uint32_t ahberr :
- 1;
-uint32_t setup :
- 1;
-uint32_t Reserved04_31 :
- 28;
- }
- b;
-} USB_OTG_DOEPINTn_TypeDef ;
-typedef union _USB_OTG_DOEPINTn_TypeDef USB_OTG_DOEPMSK_TypeDef ;
-
-typedef union _USB_OTG_DAINT_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t in :
- 16;
-uint32_t out :
- 16;
- }
- ep;
-} USB_OTG_DAINT_TypeDef ;
-
-typedef union _USB_OTG_DTHRCTL_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t non_iso_thr_en :
- 1;
-uint32_t iso_thr_en :
- 1;
-uint32_t tx_thr_len :
- 9;
-uint32_t Reserved11_15 :
- 5;
-uint32_t rx_thr_en :
- 1;
-uint32_t rx_thr_len :
- 9;
-uint32_t Reserved26_31 :
- 6;
- }
- b;
-} USB_OTG_DTHRCTL_TypeDef ;
-typedef union _USB_OTG_DEPCTL_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t mps :
- 11;
-uint32_t reserved :
- 4;
-uint32_t usbactep :
- 1;
-uint32_t dpid :
- 1;
-uint32_t naksts :
- 1;
-uint32_t eptype :
- 2;
-uint32_t snp :
- 1;
-uint32_t stall :
- 1;
-uint32_t txfnum :
- 4;
-uint32_t cnak :
- 1;
-uint32_t snak :
- 1;
-uint32_t setd0pid :
- 1;
-uint32_t setd1pid :
- 1;
-uint32_t epdis :
- 1;
-uint32_t epena :
- 1;
- }
- b;
-} USB_OTG_DEPCTL_TypeDef ;
-typedef union _USB_OTG_DEPXFRSIZ_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t xfersize :
- 19;
-uint32_t pktcnt :
- 10;
-uint32_t mc :
- 2;
-uint32_t Reserved :
- 1;
- }
- b;
-} USB_OTG_DEPXFRSIZ_TypeDef ;
-typedef union _USB_OTG_DEP0XFRSIZ_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t xfersize :
- 7;
-uint32_t Reserved7_18 :
- 12;
-uint32_t pktcnt :
- 2;
-uint32_t Reserved20_28 :
- 9;
-uint32_t supcnt :
- 2;
- uint32_t Reserved31;
- }
- b;
-} USB_OTG_DEP0XFRSIZ_TypeDef ;
-typedef union _USB_OTG_HCFG_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t fslspclksel :
- 2;
-uint32_t fslssupp :
- 1;
- }
- b;
-} USB_OTG_HCFG_TypeDef ;
-typedef union _USB_OTG_HFRMINTRVL_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t frint :
- 16;
-uint32_t Reserved :
- 16;
- }
- b;
-} USB_OTG_HFRMINTRVL_TypeDef ;
-
-typedef union _USB_OTG_HFNUM_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t frnum :
- 16;
-uint32_t frrem :
- 16;
- }
- b;
-} USB_OTG_HFNUM_TypeDef ;
-typedef union _USB_OTG_HPTXSTS_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t ptxfspcavail :
- 16;
-uint32_t ptxqspcavail :
- 8;
-uint32_t ptxqtop_terminate :
- 1;
-uint32_t ptxqtop_timer :
- 2;
-uint32_t ptxqtop :
- 2;
-uint32_t chnum :
- 2;
-uint32_t ptxqtop_odd :
- 1;
- }
- b;
-} USB_OTG_HPTXSTS_TypeDef ;
-typedef union _USB_OTG_HPRT0_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t prtconnsts :
- 1;
-uint32_t prtconndet :
- 1;
-uint32_t prtena :
- 1;
-uint32_t prtenchng :
- 1;
-uint32_t prtovrcurract :
- 1;
-uint32_t prtovrcurrchng :
- 1;
-uint32_t prtres :
- 1;
-uint32_t prtsusp :
- 1;
-uint32_t prtrst :
- 1;
-uint32_t Reserved9 :
- 1;
-uint32_t prtlnsts :
- 2;
-uint32_t prtpwr :
- 1;
-uint32_t prttstctl :
- 4;
-uint32_t prtspd :
- 2;
-uint32_t Reserved19_31 :
- 13;
- }
- b;
-} USB_OTG_HPRT0_TypeDef ;
-typedef union _USB_OTG_HAINT_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t chint :
- 16;
-uint32_t Reserved :
- 16;
- }
- b;
-} USB_OTG_HAINT_TypeDef ;
-typedef union _USB_OTG_HAINTMSK_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t chint :
- 16;
-uint32_t Reserved :
- 16;
- }
- b;
-} USB_OTG_HAINTMSK_TypeDef ;
-typedef union _USB_OTG_HCCHAR_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t mps :
- 11;
-uint32_t epnum :
- 4;
-uint32_t epdir :
- 1;
-uint32_t Reserved :
- 1;
-uint32_t lspddev :
- 1;
-uint32_t eptype :
- 2;
-uint32_t multicnt :
- 2;
-uint32_t devaddr :
- 7;
-uint32_t oddfrm :
- 1;
-uint32_t chdis :
- 1;
-uint32_t chen :
- 1;
- }
- b;
-} USB_OTG_HCCHAR_TypeDef ;
-typedef union _USB_OTG_HCSPLT_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t prtaddr :
- 7;
-uint32_t hubaddr :
- 7;
-uint32_t xactpos :
- 2;
-uint32_t compsplt :
- 1;
-uint32_t Reserved :
- 14;
-uint32_t spltena :
- 1;
- }
- b;
-} USB_OTG_HCSPLT_TypeDef ;
-typedef union _USB_OTG_HCINTn_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t xfercompl :
- 1;
-uint32_t chhltd :
- 1;
-uint32_t ahberr :
- 1;
-uint32_t stall :
- 1;
-uint32_t nak :
- 1;
-uint32_t ack :
- 1;
-uint32_t nyet :
- 1;
-uint32_t xacterr :
- 1;
-uint32_t bblerr :
- 1;
-uint32_t frmovrun :
- 1;
-uint32_t datatglerr :
- 1;
-uint32_t Reserved :
- 21;
- }
- b;
-} USB_OTG_HCINTn_TypeDef ;
-typedef union _USB_OTG_HCTSIZn_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t xfersize :
- 19;
-uint32_t pktcnt :
- 10;
-uint32_t pid :
- 2;
-uint32_t dopng :
- 1;
- }
- b;
-} USB_OTG_HCTSIZn_TypeDef ;
-typedef union _USB_OTG_HCGINTMSK_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t xfercompl :
- 1;
-uint32_t chhltd :
- 1;
-uint32_t ahberr :
- 1;
-uint32_t stall :
- 1;
-uint32_t nak :
- 1;
-uint32_t ack :
- 1;
-uint32_t nyet :
- 1;
-uint32_t xacterr :
- 1;
-uint32_t bblerr :
- 1;
-uint32_t frmovrun :
- 1;
-uint32_t datatglerr :
- 1;
-uint32_t Reserved :
- 21;
- }
- b;
-} USB_OTG_HCGINTMSK_TypeDef ;
-typedef union _USB_OTG_PCGCCTL_TypeDef
-{
- uint32_t d32;
- struct
- {
-uint32_t stoppclk :
- 1;
-uint32_t gatehclk :
- 1;
-uint32_t Reserved :
- 30;
- }
- b;
-} USB_OTG_PCGCCTL_TypeDef ;
-
-/**
- * @}
- */
-
-
-/** @defgroup USB_REGS_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_REGS_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_REGS_Exported_FunctionsPrototype
- * @{
- */
-/**
- * @}
- */
-
-
-#endif //__USB_OTG_REGS_H__
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_bsp.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief This file is responsible to offer board support package and is
- * configurable by user.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_bsp.h"
-
-/** @addtogroup USB_OTG_DRIVER
-* @{
-*/
-
-/** @defgroup USB_BSP
- * @brief This file is responsible to offer board support package
- * @{
- */
-
-/** @defgroup USB_BSP_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_BSP_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-
-
-
-/** @defgroup USB_BSP_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBH_BSP_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBH_BSP_Private_FunctionPrototypes
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_BSP_Private_Functions
- * @{
- */
-
-
-/**
- * @brief USB_OTG_BSP_Init
- * Initilizes BSP configurations
- * @param None
- * @retval None
- */
-
-void USB_OTG_BSP_Init(void)
-{
-
-}
-/**
- * @brief USB_OTG_BSP_EnableInterrupt
- * Enabele USB Global interrupt
- * @param None
- * @retval None
- */
-void USB_OTG_BSP_EnableInterrupt(void)
-{
-
-}
-
-/**
- * @brief BSP_Drive_VBUS
- * Drives the Vbus signal through IO
- * @param speed : Full, Low
- * @param state : VBUS states
- * @retval None
- */
-
-void USB_OTG_BSP_DriveVBUS(uint32_t speed, uint8_t state)
-{
-
-}
-
-/**
- * @brief USB_OTG_BSP_ConfigVBUS
- * Configures the IO for the Vbus and OverCurrent
- * @param Speed : Full, Low
- * @retval None
- */
-
-void USB_OTG_BSP_ConfigVBUS(uint32_t speed)
-{
-
-}
-
-/**
- * @brief USB_OTG_BSP_TimeInit
- * Initialises delay unit Systick timer /Timer2
- * @param None
- * @retval None
- */
-void USB_OTG_BSP_TimeInit ( void )
-{
-
-}
-
-/**
- * @brief USB_OTG_BSP_uDelay
- * This function provides delay time in micro sec
- * @param usec : Value of delay required in micro sec
- * @retval None
- */
-void USB_OTG_BSP_uDelay (const uint32_t usec)
-{
-
- uint32_t count = 0;
- const uint32_t utime = (120 * usec / 7);
- do
- {
- if ( ++count > utime )
- {
- return ;
- }
- }
- while (1);
-
-}
-
-
-/**
- * @brief USB_OTG_BSP_mDelay
- * This function provides delay time in milli sec
- * @param msec : Value of delay required in milli sec
- * @retval None
- */
-void USB_OTG_BSP_mDelay (const uint32_t msec)
-{
-
- USB_OTG_BSP_uDelay(msec * 1000);
-
-}
-
-
-/**
- * @brief USB_OTG_BSP_TimerIRQ
- * Time base IRQ
- * @param None
- * @retval None
- */
-
-void USB_OTG_BSP_TimerIRQ (void)
-{
-
-}
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_core.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief USB-OTG Core Layer
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_core.h"
-#include "usb_bsp.h"
-
-
-/** @addtogroup USB_OTG_DRIVER
-* @{
-*/
-
-/** @defgroup USB_CORE
-* @brief This file includes the USB-OTG Core Layer
-* @{
-*/
-
-
-/** @defgroup USB_CORE_Private_Defines
-* @{
-*/
-
-/**
-* @}
-*/
-
-
-/** @defgroup USB_CORE_Private_TypesDefinitions
-* @{
-*/
-/**
-* @}
-*/
-
-
-
-/** @defgroup USB_CORE_Private_Macros
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USB_CORE_Private_Variables
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USB_CORE_Private_FunctionPrototypes
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USB_CORE_Private_Functions
-* @{
-*/
-
-/**
-* @brief USB_OTG_EnableCommonInt
-* Initializes the commmon interrupts, used in both device and modes
-* @param pdev : Selected device
-* @retval None
-*/
-static void USB_OTG_EnableCommonInt(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_GINTMSK_TypeDef int_mask;
-
- int_mask.d32 = 0;
- /* Clear any pending USB_OTG Interrupts */
-#ifndef USE_OTG_MODE
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GOTGINT, 0xFFFFFFFF);
-#endif
- /* Clear any pending interrupts */
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF);
- /* Enable the interrupts in the INTMSK */
- int_mask.b.wkupintr = 1;
- int_mask.b.usbsuspend = 1;
-
-#ifdef USE_OTG_MODE
- int_mask.b.otgintr = 1;
- int_mask.b.sessreqintr = 1;
- int_mask.b.conidstschng = 1;
-#endif
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32);
-}
-
-/**
-* @brief USB_OTG_CoreReset : Soft reset of the core
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-static USB_OTG_STS USB_OTG_CoreReset(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_STS status = USB_OTG_OK;
- __IO USB_OTG_GRSTCTL_TypeDef greset;
- uint32_t count = 0;
-
- greset.d32 = 0;
- /* Wait for AHB master IDLE state. */
- do
- {
- USB_OTG_BSP_uDelay(3);
- greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL);
- if (++count > 200000)
- {
- return USB_OTG_OK;
- }
- }
- while (greset.b.ahbidle == 0);
- /* Core Soft Reset */
- count = 0;
- greset.b.csftrst = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRSTCTL, greset.d32 );
- do
- {
- greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL);
- if (++count > 200000)
- {
- break;
- }
- }
- while (greset.b.csftrst == 1);
- /* Wait for 3 PHY Clocks*/
- USB_OTG_BSP_uDelay(3);
- return status;
-}
-
-/**
-* @brief USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated
-* with the EP
-* @param pdev : Selected device
-* @param src : source pointer
-* @param ch_ep_num : end point number
-* @param bytes : No. of bytes
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev,
- uint8_t *src,
- uint8_t ch_ep_num,
- uint16_t len)
-{
- USB_OTG_STS status = USB_OTG_OK;
- if (pdev->cfg.dma_enable == 0)
- {
- uint32_t count32b= 0 , i= 0;
- __IO uint32_t *fifo;
-
- count32b = (len + 3) / 4;
- fifo = pdev->regs.DFIFO[ch_ep_num];
- for (i = 0; i < count32b; i++, src+=4)
- {
- USB_OTG_WRITE_REG32( fifo, *((__packed uint32_t *)src) );
- }
- }
- return status;
-}
-
-
-/**
-* @brief USB_OTG_ReadPacket : Reads a packet from the Rx FIFO
-* @param pdev : Selected device
-* @param dest : Destination Pointer
-* @param bytes : No. of bytes
-* @retval None
-*/
-void *USB_OTG_ReadPacket(USB_OTG_CORE_HANDLE *pdev,
- uint8_t *dest,
- uint16_t len)
-{
- uint32_t i=0;
- uint32_t count32b = (len + 3) / 4;
-
- __IO uint32_t *fifo = pdev->regs.DFIFO[0];
-
- for ( i = 0; i < count32b; i++, dest += 4 )
- {
- *(__packed uint32_t *)dest = USB_OTG_READ_REG32(fifo);
-
- }
- return ((void *)dest);
-}
-
-/**
-* @brief USB_OTG_SelectCore
-* Initialize core registers address.
-* @param pdev : Selected device
-* @param coreID : USB OTG Core ID
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev,
- USB_OTG_CORE_ID_TypeDef coreID)
-{
- uint32_t i , baseAddress = 0;
- USB_OTG_STS status = USB_OTG_OK;
-
- pdev->cfg.dma_enable = 0;
-
- /* at startup the core is in FS mode */
- pdev->cfg.speed = USB_OTG_SPEED_FULL;
- pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ;
-
- /* initialize device cfg following its address */
- if (coreID == USB_OTG_FS_CORE_ID)
- {
- baseAddress = USB_OTG_FS_BASE_ADDR;
- pdev->cfg.coreID = USB_OTG_FS_CORE_ID;
- pdev->cfg.host_channels = 8 ;
- pdev->cfg.dev_endpoints = 4 ;
- pdev->cfg.TotalFifoSize = 320; /* in 32-bits */
- pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY;
-
-#ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED
- pdev->cfg.Sof_output = 1;
-#endif
-
-#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
- pdev->cfg.low_power = 1;
-#endif
- }
- else if (coreID == USB_OTG_HS_CORE_ID)
- {
- baseAddress = USB_OTG_HS_BASE_ADDR;
- pdev->cfg.coreID = USB_OTG_HS_CORE_ID;
- pdev->cfg.host_channels = 12 ;
- pdev->cfg.dev_endpoints = 6 ;
- pdev->cfg.TotalFifoSize = 1280;/* in 32-bits */
-
-#ifdef USB_OTG_ULPI_PHY_ENABLED
- pdev->cfg.phy_itface = USB_OTG_ULPI_PHY;
-#else
- #ifdef USB_OTG_EMBEDDED_PHY_ENABLED
- pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY;
- #else
- #ifdef USB_OTG_I2C_PHY_ENABLED
- pdev->cfg.phy_itface = USB_OTG_I2C_PHY;
- #endif
- #endif
-#endif
-
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- pdev->cfg.dma_enable = 1;
-#endif
-
-#ifdef USB_OTG_HS_SOF_OUTPUT_ENABLED
- pdev->cfg.Sof_output = 1;
-#endif
-
-#ifdef USB_OTG_HS_LOW_PWR_MGMT_SUPPORT
- pdev->cfg.low_power = 1;
-#endif
-
- }
-
- pdev->regs.GREGS = (USB_OTG_GREGS *)(baseAddress + \
- USB_OTG_CORE_GLOBAL_REGS_OFFSET);
- pdev->regs.DREGS = (USB_OTG_DREGS *) (baseAddress + \
- USB_OTG_DEV_GLOBAL_REG_OFFSET);
-
- for (i = 0; i < pdev->cfg.dev_endpoints; i++)
- {
- pdev->regs.INEP_REGS[i] = (USB_OTG_INEPREGS *) \
- (baseAddress + USB_OTG_DEV_IN_EP_REG_OFFSET + \
- (i * USB_OTG_EP_REG_OFFSET));
- pdev->regs.OUTEP_REGS[i] = (USB_OTG_OUTEPREGS *) \
- (baseAddress + USB_OTG_DEV_OUT_EP_REG_OFFSET + \
- (i * USB_OTG_EP_REG_OFFSET));
- }
- pdev->regs.HREGS = (USB_OTG_HREGS *)(baseAddress + \
- USB_OTG_HOST_GLOBAL_REG_OFFSET);
- pdev->regs.HPRT0 = (uint32_t *)(baseAddress + USB_OTG_HOST_PORT_REGS_OFFSET);
-
- for (i = 0; i < pdev->cfg.host_channels; i++)
- {
- pdev->regs.HC_REGS[i] = (USB_OTG_HC_REGS *)(baseAddress + \
- USB_OTG_HOST_CHAN_REGS_OFFSET + \
- (i * USB_OTG_CHAN_REGS_OFFSET));
- }
- for (i = 0; i < pdev->cfg.host_channels; i++)
- {
- pdev->regs.DFIFO[i] = (uint32_t *)(baseAddress + USB_OTG_DATA_FIFO_OFFSET +\
- (i * USB_OTG_DATA_FIFO_SIZE));
- }
- pdev->regs.PCGCCTL = (uint32_t *)(baseAddress + USB_OTG_PCGCCTL_OFFSET);
-
- return status;
-}
-
-
-/**
-* @brief USB_OTG_CoreInit
-* Initializes the USB_OTG controller registers and prepares the core
-* device mode or host mode operation.
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_GUSBCFG_TypeDef usbcfg;
- USB_OTG_GCCFG_TypeDef gccfg;
- USB_OTG_GI2CCTL_TypeDef i2cctl;
- USB_OTG_GAHBCFG_TypeDef ahbcfg;
-
- usbcfg.d32 = 0;
- gccfg.d32 = 0;
- ahbcfg.d32 = 0;
-
-
-
- if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY)
- {
- gccfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GCCFG);
- gccfg.b.pwdn = 0;
-
- if (pdev->cfg.Sof_output)
- {
- gccfg.b.sofouten = 1;
- }
- USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32);
-
- /* Init The ULPI Interface */
- usbcfg.d32 = 0;
- usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
-
- usbcfg.b.physel = 0; /* HS Interface */
-#ifdef USB_OTG_INTERNAL_VBUS_ENABLED
- usbcfg.b.ulpi_ext_vbus_drv = 0; /* Use internal VBUS */
-#else
- #ifdef USB_OTG_EXTERNAL_VBUS_ENABLED
- usbcfg.b.ulpi_ext_vbus_drv = 1; /* Use external VBUS */
- #endif
-#endif
- usbcfg.b.term_sel_dl_pulse = 0; /* Data line pulsing using utmi_txvalid */
- usbcfg.b.ulpi_utmi_sel = 1; /* ULPI seleInterfacect */
-
- usbcfg.b.phyif = 0; /* 8 bits */
- usbcfg.b.ddrsel = 0; /* single data rate */
-
- usbcfg.b.ulpi_fsls = 0;
- usbcfg.b.ulpi_clk_sus_m = 0;
- USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
-
- /* Reset after a PHY select */
- USB_OTG_CoreReset(pdev);
-
- if(pdev->cfg.dma_enable == 1)
- {
-
- ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/
- ahbcfg.b.dmaenable = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32);
-
- }
- }
- else /* FS interface (embedded Phy or I2C Phy) */
- {
-
- usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);;
- usbcfg.b.physel = 1; /* FS Interface */
- USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
- /* Reset after a PHY select and set Host mode */
- USB_OTG_CoreReset(pdev);
- /* Enable the I2C interface and deactivate the power down*/
- gccfg.d32 = 0;
- gccfg.b.pwdn = 1;
-
- if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY)
- {
- gccfg.b.i2cifen = 1;
- }
- gccfg.b.vbussensingA = 1 ;
- gccfg.b.vbussensingB = 1 ;
-#ifndef VBUS_SENSING_ENABLED
- gccfg.b.disablevbussensing = 1;
-#endif
-
- if(pdev->cfg.Sof_output)
- {
- gccfg.b.sofouten = 1;
- }
-
- USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32);
- USB_OTG_BSP_mDelay(20);
- /* Program GUSBCFG.OtgUtmifsSel to I2C*/
- usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
-
- if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY)
- {
- usbcfg.b.otgutmifssel = 1;
- }
-
- USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
-
- if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY)
- {
- /*Program GI2CCTL.I2CEn*/
- i2cctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GI2CCTL);
- i2cctl.b.i2cdevaddr = 1;
- i2cctl.b.i2cen = 0;
- i2cctl.b.dat_se0 = 1;
- i2cctl.b.addr = 0x2D;
- USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GI2CCTL, i2cctl.d32);
-
- USB_OTG_BSP_mDelay(200);
-
- i2cctl.b.i2cen = 1;
- USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GI2CCTL, i2cctl.d32);
- USB_OTG_BSP_mDelay(200);
- }
- }
- /* case the HS core is working in FS mode */
- if(pdev->cfg.dma_enable == 1)
- {
-
- ahbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GAHBCFG);
- ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/
- ahbcfg.b.dmaenable = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32);
-
- }
- /* initialize OTG features */
-#ifdef USE_OTG_MODE
- usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
- usbcfg.b.hnpcap = 1;
- usbcfg.b.srpcap = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
- USB_OTG_EnableCommonInt(pdev);
-#endif
- return status;
-}
-/**
-* @brief USB_OTG_EnableGlobalInt
-* Enables the controller's Global Int in the AHB Config reg
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EnableGlobalInt(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_GAHBCFG_TypeDef ahbcfg;
-
- ahbcfg.d32 = 0;
- ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
- USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, 0, ahbcfg.d32);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_DisableGlobalInt
-* Enables the controller's Global Int in the AHB Config reg
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_GAHBCFG_TypeDef ahbcfg;
- ahbcfg.d32 = 0;
- ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
- USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32, 0);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
-* @param pdev : Selected device
-* @param num : FO num
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num )
-{
- USB_OTG_STS status = USB_OTG_OK;
- __IO USB_OTG_GRSTCTL_TypeDef greset;
-
- uint32_t count = 0;
- greset.d32 = 0;
- greset.b.txfflsh = 1;
- greset.b.txfnum = num;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 );
- do
- {
- greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL);
- if (++count > 200000)
- {
- break;
- }
- }
- while (greset.b.txfflsh == 1);
- /* Wait for 3 PHY Clocks*/
- USB_OTG_BSP_uDelay(3);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_FlushRxFifo : Flush a Rx FIFO
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_FlushRxFifo( USB_OTG_CORE_HANDLE *pdev )
-{
- USB_OTG_STS status = USB_OTG_OK;
- __IO USB_OTG_GRSTCTL_TypeDef greset;
- uint32_t count = 0;
-
- greset.d32 = 0;
- greset.b.rxfflsh = 1;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 );
- do
- {
- greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL);
- if (++count > 200000)
- {
- break;
- }
- }
- while (greset.b.rxfflsh == 1);
- /* Wait for 3 PHY Clocks*/
- USB_OTG_BSP_uDelay(3);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_SetCurrentMode : Set ID line
-* @param pdev : Selected device
-* @param mode : (Host/device)
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE *pdev , uint8_t mode)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_GUSBCFG_TypeDef usbcfg;
-
- usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
-
- usbcfg.b.force_host = 0;
- usbcfg.b.force_dev = 0;
-
- if ( mode == HOST_MODE)
- {
- usbcfg.b.force_host = 1;
- }
- else if ( mode == DEVICE_MODE)
- {
- usbcfg.b.force_dev = 1;
- }
-
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
- USB_OTG_BSP_mDelay(50);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_GetMode : Get current mode
-* @param pdev : Selected device
-* @retval current mode
-*/
-uint32_t USB_OTG_GetMode(USB_OTG_CORE_HANDLE *pdev)
-{
- return (USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS ) & 0x1);
-}
-
-
-/**
-* @brief USB_OTG_IsDeviceMode : Check if it is device mode
-* @param pdev : Selected device
-* @retval num_in_ep
-*/
-uint8_t USB_OTG_IsDeviceMode(USB_OTG_CORE_HANDLE *pdev)
-{
- return (USB_OTG_GetMode(pdev) != HOST_MODE);
-}
-
-
-/**
-* @brief USB_OTG_IsHostMode : Check if it is host mode
-* @param pdev : Selected device
-* @retval num_in_ep
-*/
-uint8_t USB_OTG_IsHostMode(USB_OTG_CORE_HANDLE *pdev)
-{
- return (USB_OTG_GetMode(pdev) == HOST_MODE);
-}
-
-
-/**
-* @brief USB_OTG_ReadCoreItr : returns the Core Interrupt register
-* @param pdev : Selected device
-* @retval Status
-*/
-uint32_t USB_OTG_ReadCoreItr(USB_OTG_CORE_HANDLE *pdev)
-{
- uint32_t v = 0;
- v = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS);
- v &= USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK);
- return v;
-}
-
-
-/**
-* @brief USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register
-* @param pdev : Selected device
-* @retval Status
-*/
-uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev)
-{
- return (USB_OTG_READ_REG32 (&pdev->regs.GREGS->GOTGINT));
-}
-
-#ifdef USE_HOST_MODE
-/**
-* @brief USB_OTG_CoreInitHost : Initializes USB_OTG controller for host mode
-* @param pdev : Selected device
-* @retval status
-*/
-USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_FSIZ_TypeDef nptxfifosize;
- USB_OTG_FSIZ_TypeDef ptxfifosize;
- USB_OTG_HCFG_TypeDef hcfg;
-
-#ifdef USE_OTG_MODE
- USB_OTG_OTGCTL_TypeDef gotgctl;
-#endif
-
- uint32_t i = 0;
-
- nptxfifosize.d32 = 0;
- ptxfifosize.d32 = 0;
-#ifdef USE_OTG_MODE
- gotgctl.d32 = 0;
-#endif
- hcfg.d32 = 0;
-
-
- /* configure charge pump IO */
- USB_OTG_BSP_ConfigVBUS(pdev);
-
- /* Restart the Phy Clock */
- USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0);
-
- /* Initialize Host Configuration Register */
- USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ); /* in init phase */
-
- hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG);
- hcfg.b.fslssupp = 0;
- USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32);
-
- /* Configure data FIFO sizes */
- /* Rx FIFO */
-#ifdef USB_OTG_FS_CORE
- if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID)
- {
- /* set Rx FIFO size */
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE);
- nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE;
- nptxfifosize.b.depth = TXH_NP_FS_FIFOSIZ;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32);
-
- ptxfifosize.b.startaddr = RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ;
- ptxfifosize.b.depth = TXH_P_FS_FIFOSIZ;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32);
- }
-#endif
-#ifdef USB_OTG_HS_CORE
- if (pdev->cfg.coreID == USB_OTG_HS_CORE_ID)
- {
- /* set Rx FIFO size */
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE);
- nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE;
- nptxfifosize.b.depth = TXH_NP_HS_FIFOSIZ;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32);
-
- ptxfifosize.b.startaddr = RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ;
- ptxfifosize.b.depth = TXH_P_HS_FIFOSIZ;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32);
- }
-#endif
-
-#ifdef USE_OTG_MODE
- /* Clear Host Set HNP Enable in the USB_OTG Control Register */
- gotgctl.b.hstsethnpen = 1;
- USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0);
-#endif
-
- /* Make sure the FIFOs are flushed. */
- USB_OTG_FlushTxFifo(pdev, 0x10 ); /* all Tx FIFOs */
- USB_OTG_FlushRxFifo(pdev);
-
-
- /* Clear all pending HC Interrupts */
- for (i = 0; i < pdev->cfg.host_channels; i++)
- {
- USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINT, 0xFFFFFFFF );
- USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCGINTMSK, 0 );
- }
-#ifndef USE_OTG_MODE
- USB_OTG_DriveVbus(pdev, 1);
-#endif
-
- USB_OTG_EnableHostInt(pdev);
- return status;
-}
-
-/**
-* @brief USB_OTG_IsEvenFrame
-* This function returns the frame number for sof packet
-* @param pdev : Selected device
-* @retval Frame number
-*/
-uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev)
-{
- return !(USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0x1);
-}
-
-/**
-* @brief USB_OTG_DriveVbus : set/reset vbus
-* @param pdev : Selected device
-* @param state : VBUS state
-* @retval None
-*/
-void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state)
-{
- USB_OTG_HPRT0_TypeDef hprt0;
-
- hprt0.d32 = 0;
-
- /* enable disable the external charge pump */
- USB_OTG_BSP_DriveVBUS(pdev, state);
-
- /* Turn on the Host port power. */
- hprt0.d32 = USB_OTG_ReadHPRT0(pdev);
- if ((hprt0.b.prtpwr == 0 ) && (state == 1 ))
- {
- hprt0.b.prtpwr = 1;
- USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
- }
- if ((hprt0.b.prtpwr == 1 ) && (state == 0 ))
- {
- hprt0.b.prtpwr = 0;
- USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
- }
-
- USB_OTG_BSP_mDelay(200);
-}
-/**
-* @brief USB_OTG_EnableHostInt: Enables the Host mode interrupts
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EnableHostInt(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_GINTMSK_TypeDef intmsk;
- intmsk.d32 = 0;
- /* Disable all interrupts. */
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTMSK, 0);
-
- /* Clear any pending interrupts. */
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF);
-
- /* Enable the common interrupts */
- USB_OTG_EnableCommonInt(pdev);
-
- if (pdev->cfg.dma_enable == 0)
- {
- intmsk.b.rxstsqlvl = 1;
- }
- intmsk.b.portintr = 1;
- intmsk.b.hcintr = 1;
- intmsk.b.disconnect = 1;
- intmsk.b.sofintr = 1;
- intmsk.b.incomplisoout = 1;
- USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32);
- return status;
-}
-
-/**
-* @brief USB_OTG_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
-* HCFG register on the PHY type
-* @param pdev : Selected device
-* @param freq : clock frequency
-* @retval None
-*/
-void USB_OTG_InitFSLSPClkSel(USB_OTG_CORE_HANDLE *pdev , uint8_t freq)
-{
- USB_OTG_HCFG_TypeDef hcfg;
-
- hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG);
- hcfg.b.fslspclksel = freq;
- USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32);
-}
-
-
-/**
-* @brief USB_OTG_ReadHPRT0 : Reads HPRT0 to modify later
-* @param pdev : Selected device
-* @retval HPRT0 value
-*/
-uint32_t USB_OTG_ReadHPRT0(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_HPRT0_TypeDef hprt0;
-
- hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
- hprt0.b.prtena = 0;
- hprt0.b.prtconndet = 0;
- hprt0.b.prtenchng = 0;
- hprt0.b.prtovrcurrchng = 0;
- return hprt0.d32;
-}
-
-
-/**
-* @brief USB_OTG_ReadHostAllChannels_intr : Register PCD Callbacks
-* @param pdev : Selected device
-* @retval Status
-*/
-uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev)
-{
- return (USB_OTG_READ_REG32 (&pdev->regs.HREGS->HAINT));
-}
-
-
-/**
-* @brief USB_OTG_ResetPort : Reset Host Port
-* @param pdev : Selected device
-* @retval status
-* @note : (1)The application must wait at least 10 ms (+ 10 ms security)
-* before clearing the reset bit.
-*/
-uint32_t USB_OTG_ResetPort(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_HPRT0_TypeDef hprt0;
-
- hprt0.d32 = USB_OTG_ReadHPRT0(pdev);
- hprt0.b.prtrst = 1;
- USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
- USB_OTG_BSP_mDelay (10); /* See Note #1 */
- hprt0.b.prtrst = 0;
- USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
- USB_OTG_BSP_mDelay (20);
- return 1;
-}
-
-
-/**
-* @brief USB_OTG_HC_Init : Prepares a host channel for transferring packets
-* @param pdev : Selected device
-* @param hc_num : channel number
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_HC_Init(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
-{
- USB_OTG_STS status = USB_OTG_OK;
- uint32_t intr_enable = 0;
- USB_OTG_HCGINTMSK_TypeDef hcintmsk;
- USB_OTG_GINTMSK_TypeDef gintmsk;
- USB_OTG_HCCHAR_TypeDef hcchar;
- USB_OTG_HCINTn_TypeDef hcint;
-
-
- gintmsk.d32 = 0;
- hcintmsk.d32 = 0;
- hcchar.d32 = 0;
-
- /* Clear old interrupt conditions for this host channel. */
- hcint.d32 = 0xFFFFFFFF;
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINT, hcint.d32);
-
- /* Enable channel interrupts required for this transfer. */
- hcintmsk.d32 = 0;
-
- if (pdev->cfg.dma_enable == 1)
- {
- hcintmsk.b.ahberr = 1;
- }
-
- switch (pdev->host.hc[hc_num].ep_type)
- {
- case EP_TYPE_CTRL:
- case EP_TYPE_BULK:
- hcintmsk.b.xfercompl = 1;
- hcintmsk.b.stall = 1;
- hcintmsk.b.xacterr = 1;
- hcintmsk.b.datatglerr = 1;
- hcintmsk.b.nak = 1;
- if (pdev->host.hc[hc_num].ep_is_in)
- {
- hcintmsk.b.bblerr = 1;
- }
- else
- {
- hcintmsk.b.nyet = 1;
- if (pdev->host.hc[hc_num].do_ping)
- {
- hcintmsk.b.ack = 1;
- }
- }
- break;
- case EP_TYPE_INTR:
- hcintmsk.b.xfercompl = 1;
- hcintmsk.b.nak = 1;
- hcintmsk.b.stall = 1;
- hcintmsk.b.xacterr = 1;
- hcintmsk.b.datatglerr = 1;
- hcintmsk.b.frmovrun = 1;
-
- if (pdev->host.hc[hc_num].ep_is_in)
- {
- hcintmsk.b.bblerr = 1;
- }
-
- break;
- case EP_TYPE_ISOC:
- hcintmsk.b.xfercompl = 1;
- hcintmsk.b.frmovrun = 1;
- hcintmsk.b.ack = 1;
-
- if (pdev->host.hc[hc_num].ep_is_in)
- {
- hcintmsk.b.xacterr = 1;
- hcintmsk.b.bblerr = 1;
- }
- break;
- }
-
-
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, hcintmsk.d32);
-
-
- /* Enable the top level host channel interrupt. */
- intr_enable = (1 << hc_num);
- USB_OTG_MODIFY_REG32(&pdev->regs.HREGS->HAINTMSK, 0, intr_enable);
-
- /* Make sure host channel interrupts are enabled. */
- gintmsk.b.hcintr = 1;
- USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, gintmsk.d32);
-
- /* Program the HCCHAR register */
- hcchar.d32 = 0;
- hcchar.b.devaddr = pdev->host.hc[hc_num].dev_addr;
- hcchar.b.epnum = pdev->host.hc[hc_num].ep_num;
- hcchar.b.epdir = pdev->host.hc[hc_num].ep_is_in;
- hcchar.b.lspddev = (pdev->host.hc[hc_num].speed == HPRT0_PRTSPD_LOW_SPEED);
- hcchar.b.eptype = pdev->host.hc[hc_num].ep_type;
- hcchar.b.mps = pdev->host.hc[hc_num].max_packet;
- if (pdev->host.hc[hc_num].ep_type == HCCHAR_INTR)
- {
- hcchar.b.oddfrm = 1;
- }
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_HC_StartXfer : Start transfer
-* @param pdev : Selected device
-* @param hc_num : channel number
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_HC_StartXfer(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_HCCHAR_TypeDef hcchar;
- USB_OTG_HCTSIZn_TypeDef hctsiz;
- USB_OTG_HNPTXSTS_TypeDef hnptxsts;
- USB_OTG_HPTXSTS_TypeDef hptxsts;
- USB_OTG_GINTMSK_TypeDef intmsk;
- uint16_t len_words = 0;
-
- uint16_t num_packets;
- uint16_t max_hc_pkt_count;
-
- max_hc_pkt_count = 256;
- hctsiz.d32 = 0;
- hcchar.d32 = 0;
- intmsk.d32 = 0;
-
- /* Compute the expected number of packets associated to the transfer */
- if (pdev->host.hc[hc_num].xfer_len > 0)
- {
- num_packets = (pdev->host.hc[hc_num].xfer_len + \
- pdev->host.hc[hc_num].max_packet - 1) / pdev->host.hc[hc_num].max_packet;
-
- if (num_packets > max_hc_pkt_count)
- {
- num_packets = max_hc_pkt_count;
- pdev->host.hc[hc_num].xfer_len = num_packets * \
- pdev->host.hc[hc_num].max_packet;
- }
- }
- else
- {
- num_packets = 1;
- }
- if (pdev->host.hc[hc_num].ep_is_in)
- {
- pdev->host.hc[hc_num].xfer_len = num_packets * \
- pdev->host.hc[hc_num].max_packet;
- }
- /* Initialize the HCTSIZn register */
- hctsiz.b.xfersize = pdev->host.hc[hc_num].xfer_len;
- hctsiz.b.pktcnt = num_packets;
- hctsiz.b.pid = pdev->host.hc[hc_num].data_pid;
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32);
-
- if (pdev->cfg.dma_enable == 1)
- {
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCDMA, (unsigned int)pdev->host.hc[hc_num].xfer_buff);
- }
-
-
- hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR);
- hcchar.b.oddfrm = USB_OTG_IsEvenFrame(pdev);
-
- /* Set host channel enable */
- hcchar.b.chen = 1;
- hcchar.b.chdis = 0;
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
-
- if (pdev->cfg.dma_enable == 0) /* Slave mode */
- {
- if((pdev->host.hc[hc_num].ep_is_in == 0) &&
- (pdev->host.hc[hc_num].xfer_len > 0))
- {
- switch(pdev->host.hc[hc_num].ep_type)
- {
- /* Non periodic transfer */
- case EP_TYPE_CTRL:
- case EP_TYPE_BULK:
-
- hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
- len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4;
-
- /* check if there is enough space in FIFO space */
- if(len_words > hnptxsts.b.nptxfspcavail)
- {
- /* need to process data in nptxfempty interrupt */
- intmsk.b.nptxfempty = 1;
- USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32);
- }
-
- break;
- /* Periodic transfer */
- case EP_TYPE_INTR:
- case EP_TYPE_ISOC:
- hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
- len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4;
- /* check if there is enough space in FIFO space */
- if(len_words > hptxsts.b.ptxfspcavail) /* split the transfer */
- {
- /* need to process data in ptxfempty interrupt */
- intmsk.b.ptxfempty = 1;
- USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32);
- }
- break;
-
- default:
- break;
- }
-
- /* Write packet into the Tx FIFO. */
- USB_OTG_WritePacket(pdev,
- pdev->host.hc[hc_num].xfer_buff ,
- hc_num, pdev->host.hc[hc_num].xfer_len);
- }
- }
- return status;
-}
-
-
-/**
-* @brief USB_OTG_HC_Halt : Halt channel
-* @param pdev : Selected device
-* @param hc_num : channel number
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_HC_Halt(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_HNPTXSTS_TypeDef nptxsts;
- USB_OTG_HPTXSTS_TypeDef hptxsts;
- USB_OTG_HCCHAR_TypeDef hcchar;
-
- nptxsts.d32 = 0;
- hptxsts.d32 = 0;
- hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR);
- hcchar.b.chen = 1;
- hcchar.b.chdis = 1;
-
- /* Check for space in the request queue to issue the halt. */
- if (hcchar.b.eptype == HCCHAR_CTRL || hcchar.b.eptype == HCCHAR_BULK)
- {
- nptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
- if (nptxsts.b.nptxqspcavail == 0)
- {
- hcchar.b.chen = 0;
- }
- }
- else
- {
- hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
- if (hptxsts.b.ptxqspcavail == 0)
- {
- hcchar.b.chen = 0;
- }
- }
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
- return status;
-}
-
-/**
-* @brief Issue a ping token
-* @param None
-* @retval : None
-*/
-USB_OTG_STS USB_OTG_HC_DoPing(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_HCCHAR_TypeDef hcchar;
- USB_OTG_HCTSIZn_TypeDef hctsiz;
-
- hctsiz.d32 = 0;
- hctsiz.b.dopng = 1;
- hctsiz.b.pktcnt = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32);
-
- hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR);
- hcchar.b.chen = 1;
- hcchar.b.chdis = 0;
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
- return status;
-}
-
-/**
-* @brief Stop the device and clean up fifo's
-* @param None
-* @retval : None
-*/
-void USB_OTG_StopHost(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_HCCHAR_TypeDef hcchar;
- uint32_t i;
-
- USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINTMSK , 0);
- USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINT, 0xFFFFFFFF);
- /* Flush out any leftover queued requests. */
-
- for (i = 0; i < pdev->cfg.host_channels; i++)
- {
- hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR);
- hcchar.b.chen = 0;
- hcchar.b.chdis = 1;
- hcchar.b.epdir = 0;
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[i]->HCCHAR, hcchar.d32);
- }
-
- /* Flush the FIFO */
- USB_OTG_FlushRxFifo(pdev);
- USB_OTG_FlushTxFifo(pdev , 0x10 );
-}
-#endif
-#ifdef USE_DEVICE_MODE
-/* PCD Core Layer */
-
-/**
-* @brief USB_OTG_InitDevSpeed :Initializes the DevSpd field of DCFG register
-* depending the PHY type and the enumeration speed of the device.
-* @param pdev : Selected device
-* @retval : None
-*/
-void USB_OTG_InitDevSpeed(USB_OTG_CORE_HANDLE *pdev , uint8_t speed)
-{
- USB_OTG_DCFG_TypeDef dcfg;
-
- dcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCFG);
- dcfg.b.devspd = speed;
- USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCFG, dcfg.d32);
-}
-
-
-/**
-* @brief USB_OTG_CoreInitDev : Initializes the USB_OTG controller registers
-* for device mode
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_DEPCTL_TypeDef depctl;
- uint32_t i;
- USB_OTG_DCFG_TypeDef dcfg;
- USB_OTG_FSIZ_TypeDef nptxfifosize;
- USB_OTG_FSIZ_TypeDef txfifosize;
- USB_OTG_DIEPMSK_TypeDef msk;
- USB_OTG_DTHRCTL_TypeDef dthrctl;
-
- depctl.d32 = 0;
- dcfg.d32 = 0;
- nptxfifosize.d32 = 0;
- txfifosize.d32 = 0;
- msk.d32 = 0;
-
- /* Restart the Phy Clock */
- USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0);
- /* Device configuration register */
- dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG);
- dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80;
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32 );
-
-#ifdef USB_OTG_FS_CORE
- if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID )
- {
-
- /* Set Full speed phy */
- USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_FULL);
-
- /* set Rx FIFO size */
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE);
-
- /* EP0 TX*/
- nptxfifosize.b.depth = TX0_FIFO_FS_SIZE;
- nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 );
-
-
- /* EP1 TX*/
- txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
- txfifosize.b.depth = TX1_FIFO_FS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 );
-
-
- /* EP2 TX*/
- txfifosize.b.startaddr += txfifosize.b.depth;
- txfifosize.b.depth = TX2_FIFO_FS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 );
-
-
- /* EP3 TX*/
- txfifosize.b.startaddr += txfifosize.b.depth;
- txfifosize.b.depth = TX3_FIFO_FS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 );
- }
-#endif
-#ifdef USB_OTG_HS_CORE
- if(pdev->cfg.coreID == USB_OTG_HS_CORE_ID )
- {
-
- /* Set High speed phy */
-
- if(pdev->cfg.phy_itface == USB_OTG_ULPI_PHY)
- {
- USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH);
- }
- else /* set High speed phy in Full speed mode */
- {
- USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH_IN_FULL);
- }
-
- /* set Rx FIFO size */
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE);
-
- /* EP0 TX*/
- nptxfifosize.b.depth = TX0_FIFO_HS_SIZE;
- nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 );
-
-
- /* EP1 TX*/
- txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
- txfifosize.b.depth = TX1_FIFO_HS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 );
-
-
- /* EP2 TX*/
- txfifosize.b.startaddr += txfifosize.b.depth;
- txfifosize.b.depth = TX2_FIFO_HS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 );
-
-
- /* EP3 TX*/
- txfifosize.b.startaddr += txfifosize.b.depth;
- txfifosize.b.depth = TX3_FIFO_HS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 );
-
- /* EP4 TX*/
- txfifosize.b.startaddr += txfifosize.b.depth;
- txfifosize.b.depth = TX4_FIFO_HS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[3], txfifosize.d32 );
-
-
- /* EP5 TX*/
- txfifosize.b.startaddr += txfifosize.b.depth;
- txfifosize.b.depth = TX5_FIFO_HS_SIZE;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[4], txfifosize.d32 );
- }
-#endif
- /* Flush the FIFOs */
- USB_OTG_FlushTxFifo(pdev , 0x10); /* all Tx FIFOs */
- USB_OTG_FlushRxFifo(pdev);
- /* Clear all pending Device Interrupts */
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 );
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 );
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF );
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 );
-
- for (i = 0; i < pdev->cfg.dev_endpoints; i++)
- {
- depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[i]->DIEPCTL);
- if (depctl.b.epena)
- {
- depctl.d32 = 0;
- depctl.b.epdis = 1;
- depctl.b.snak = 1;
- }
- else
- {
- depctl.d32 = 0;
- }
- USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPCTL, depctl.d32);
- USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPTSIZ, 0);
- USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
- }
- for (i = 0; i < pdev->cfg.dev_endpoints; i++)
- {
- USB_OTG_DEPCTL_TypeDef depctl;
- depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[i]->DOEPCTL);
- if (depctl.b.epena)
- {
- depctl.d32 = 0;
- depctl.b.epdis = 1;
- depctl.b.snak = 1;
- }
- else
- {
- depctl.d32 = 0;
- }
- USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPCTL, depctl.d32);
- USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPTSIZ, 0);
- USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
- }
- msk.d32 = 0;
- msk.b.txfifoundrn = 1;
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPMSK, msk.d32, msk.d32);
-
- if (pdev->cfg.dma_enable == 1)
- {
- dthrctl.d32 = 0;
- dthrctl.b.non_iso_thr_en = 1;
- dthrctl.b.iso_thr_en = 1;
- dthrctl.b.tx_thr_len = 64;
- dthrctl.b.rx_thr_en = 1;
- dthrctl.b.rx_thr_len = 64;
- USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DTHRCTL, dthrctl.d32);
- }
- USB_OTG_EnableDevInt(pdev);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_EnableDevInt : Enables the Device mode interrupts
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EnableDevInt(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_GINTMSK_TypeDef intmsk;
-
- intmsk.d32 = 0;
-
- /* Disable all interrupts. */
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, 0);
- /* Clear any pending interrupts */
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF);
- /* Enable the common interrupts */
- USB_OTG_EnableCommonInt(pdev);
-
- if (pdev->cfg.dma_enable == 0)
- {
- intmsk.b.rxstsqlvl = 1;
- }
-
- /* Enable interrupts matching to the Device mode ONLY */
- intmsk.b.usbsuspend = 1;
- intmsk.b.usbreset = 1;
- intmsk.b.enumdone = 1;
- intmsk.b.inepintr = 1;
- intmsk.b.outepintr = 1;
- intmsk.b.sofintr = 1;
-
- intmsk.b.incomplisoin = 1;
- intmsk.b.incomplisoout = 1;
-#ifdef VBUS_SENSING_ENABLED
- intmsk.b.sessreqintr = 1;
- intmsk.b.otgintr = 1;
-#endif
- USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_GetDeviceSpeed
-* Get the device speed from the device status register
-* @param None
-* @retval status
-*/
-enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_DSTS_TypeDef dsts;
- enum USB_OTG_SPEED speed = USB_SPEED_UNKNOWN;
-
-
- dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
-
- switch (dsts.b.enumspd)
- {
- case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
- speed = USB_SPEED_HIGH;
- break;
- case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
- case DSTS_ENUMSPD_FS_PHY_48MHZ:
- speed = USB_SPEED_FULL;
- break;
-
- case DSTS_ENUMSPD_LS_PHY_6MHZ:
- speed = USB_SPEED_LOW;
- break;
- }
-
- return speed;
-}
-/**
-* @brief enables EP0 OUT to receive SETUP packets and configures EP0
-* for transmitting packets
-* @param None
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EP0Activate(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_DSTS_TypeDef dsts;
- USB_OTG_DEPCTL_TypeDef diepctl;
- USB_OTG_DCTL_TypeDef dctl;
-
- dctl.d32 = 0;
- /* Read the Device Status and Endpoint 0 Control registers */
- dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
- diepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL);
- /* Set the MPS of the IN EP based on the enumeration speed */
- switch (dsts.b.enumspd)
- {
- case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
- case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
- case DSTS_ENUMSPD_FS_PHY_48MHZ:
- diepctl.b.mps = DEP0CTL_MPS_64;
- break;
- case DSTS_ENUMSPD_LS_PHY_6MHZ:
- diepctl.b.mps = DEP0CTL_MPS_8;
- break;
- }
- USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL, diepctl.d32);
- dctl.b.cgnpinnak = 1;
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, dctl.d32);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_EPActivate : Activates an EP
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EPActivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_DEPCTL_TypeDef depctl;
- USB_OTG_DAINT_TypeDef daintmsk;
- __IO uint32_t *addr;
-
-
- depctl.d32 = 0;
- daintmsk.d32 = 0;
- /* Read DEPCTLn register */
- if (ep->is_in == 1)
- {
- addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL;
- daintmsk.ep.in = 1 << ep->num;
- }
- else
- {
- addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL;
- daintmsk.ep.out = 1 << ep->num;
- }
- /* If the EP is already active don't change the EP Control
- * register. */
- depctl.d32 = USB_OTG_READ_REG32(addr);
- if (!depctl.b.usbactep)
- {
- depctl.b.mps = ep->maxpacket;
- depctl.b.eptype = ep->type;
- depctl.b.txfnum = ep->tx_fifo_num;
- depctl.b.setd0pid = 1;
- depctl.b.usbactep = 1;
- USB_OTG_WRITE_REG32(addr, depctl.d32);
- }
- /* Enable the Interrupt for this EP */
-#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
- if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID))
- {
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, 0, daintmsk.d32);
- }
- else
-#endif
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, 0, daintmsk.d32);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_EPDeactivate : Deactivates an EP
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_DEPCTL_TypeDef depctl;
- USB_OTG_DAINT_TypeDef daintmsk;
- __IO uint32_t *addr;
-
- depctl.d32 = 0;
- daintmsk.d32 = 0;
- /* Read DEPCTLn register */
- if (ep->is_in == 1)
- {
- addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL;
- daintmsk.ep.in = 1 << ep->num;
- }
- else
- {
- addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL;
- daintmsk.ep.out = 1 << ep->num;
- }
- depctl.b.usbactep = 0;
- USB_OTG_WRITE_REG32(addr, depctl.d32);
- /* Disable the Interrupt for this EP */
-
-#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
- if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID))
- {
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, daintmsk.d32, 0);
- }
- else
-#endif
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, daintmsk.d32, 0);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_EPStartXfer : Handle the setup for data xfer for an EP and
-* starts the xfer
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_DEPCTL_TypeDef depctl;
- USB_OTG_DEPXFRSIZ_TypeDef deptsiz;
- USB_OTG_DSTS_TypeDef dsts;
- uint32_t fifoemptymsk = 0;
-
- depctl.d32 = 0;
- deptsiz.d32 = 0;
- /* IN endpoint */
- if (ep->is_in == 1)
- {
- depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPCTL));
- deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ));
- /* Zero Length Packet? */
- if (ep->xfer_len == 0)
- {
- deptsiz.b.xfersize = 0;
- deptsiz.b.pktcnt = 1;
- }
- else
- {
- /* Program the transfer size and packet count
- * as follows: xfersize = N * maxpacket +
- * short_packet pktcnt = N + (short_packet
- * exist ? 1 : 0)
- */
- deptsiz.b.xfersize = ep->xfer_len;
- deptsiz.b.pktcnt = (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
-
- if (ep->type == EP_TYPE_ISOC)
- {
- deptsiz.b.mc = 1;
- }
- }
- USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ, deptsiz.d32);
-
- if (pdev->cfg.dma_enable == 1)
- {
- USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr);
- }
- else
- {
- if (ep->type != EP_TYPE_ISOC)
- {
- /* Enable the Tx FIFO Empty Interrupt for this EP */
- if (ep->xfer_len > 0)
- {
- fifoemptymsk = 1 << ep->num;
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk);
- }
- }
- }
-
-
- if (ep->type == EP_TYPE_ISOC)
- {
- dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
-
- if (((dsts.b.soffn)&0x1) == 0)
- {
- depctl.b.setd1pid = 1;
- }
- else
- {
- depctl.b.setd0pid = 1;
- }
- }
-
- /* EP enable, IN data in FIFO */
- depctl.b.cnak = 1;
- depctl.b.epena = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPCTL, depctl.d32);
-
- if (ep->type == EP_TYPE_ISOC)
- {
- USB_OTG_WritePacket(pdev, ep->xfer_buff, ep->num, ep->xfer_len);
- }
- }
- else
- {
- /* OUT endpoint */
- depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL));
- deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ));
- /* Program the transfer size and packet count as follows:
- * pktcnt = N
- * xfersize = N * maxpacket
- */
- if (ep->xfer_len == 0)
- {
- deptsiz.b.xfersize = ep->maxpacket;
- deptsiz.b.pktcnt = 1;
- }
- else
- {
- deptsiz.b.pktcnt = (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
- deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
- }
- USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32);
-
- if (pdev->cfg.dma_enable == 1)
- {
- USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr);
- }
-
- if (ep->type == EP_TYPE_ISOC)
- {
- if (ep->even_odd_frame)
- {
- depctl.b.setd1pid = 1;
- }
- else
- {
- depctl.b.setd0pid = 1;
- }
- }
- /* EP enable */
- depctl.b.cnak = 1;
- depctl.b.epena = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL, depctl.d32);
- }
- return status;
-}
-
-
-/**
-* @brief USB_OTG_EP0StartXfer : Handle the setup for a data xfer for EP0 and
-* starts the xfer
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_DEPCTL_TypeDef depctl;
- USB_OTG_DEP0XFRSIZ_TypeDef deptsiz;
- USB_OTG_INEPREGS *in_regs;
- uint32_t fifoemptymsk = 0;
-
- depctl.d32 = 0;
- deptsiz.d32 = 0;
- /* IN endpoint */
- if (ep->is_in == 1)
- {
- in_regs = pdev->regs.INEP_REGS[0];
- depctl.d32 = USB_OTG_READ_REG32(&in_regs->DIEPCTL);
- deptsiz.d32 = USB_OTG_READ_REG32(&in_regs->DIEPTSIZ);
- /* Zero Length Packet? */
- if (ep->xfer_len == 0)
- {
- deptsiz.b.xfersize = 0;
- deptsiz.b.pktcnt = 1;
-
- }
- else
- {
- if (ep->xfer_len > ep->maxpacket)
- {
- ep->xfer_len = ep->maxpacket;
- deptsiz.b.xfersize = ep->maxpacket;
- }
- else
- {
- deptsiz.b.xfersize = ep->xfer_len;
- }
- deptsiz.b.pktcnt = 1;
- }
- USB_OTG_WRITE_REG32(&in_regs->DIEPTSIZ, deptsiz.d32);
-
- if (pdev->cfg.dma_enable == 1)
- {
- USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr);
- }
-
- /* EP enable, IN data in FIFO */
- depctl.b.cnak = 1;
- depctl.b.epena = 1;
- USB_OTG_WRITE_REG32(&in_regs->DIEPCTL, depctl.d32);
-
-
-
- if (pdev->cfg.dma_enable == 0)
- {
- /* Enable the Tx FIFO Empty Interrupt for this EP */
- if (ep->xfer_len > 0)
- {
- {
- fifoemptymsk |= 1 << ep->num;
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk);
- }
- }
- }
- }
- else
- {
- /* OUT endpoint */
- depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
- deptsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ);
- /* Program the transfer size and packet count as follows:
- * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
- * pktcnt = N */
- if (ep->xfer_len == 0)
- {
- deptsiz.b.xfersize = ep->maxpacket;
- deptsiz.b.pktcnt = 1;
- }
- else
- {
- ep->xfer_len = ep->maxpacket;
- deptsiz.b.xfersize = ep->maxpacket;
- deptsiz.b.pktcnt = 1;
- }
- USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32);
- if (pdev->cfg.dma_enable == 1)
- {
- USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr);
- }
- /* EP enable */
- depctl.b.cnak = 1;
- depctl.b.epena = 1;
- USB_OTG_WRITE_REG32 (&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL), depctl.d32);
-
- }
- return status;
-}
-
-
-/**
-* @brief USB_OTG_EPSetStall : Set the EP STALL
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EPSetStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_DEPCTL_TypeDef depctl;
- __IO uint32_t *depctl_addr;
-
- depctl.d32 = 0;
- if (ep->is_in == 1)
- {
- depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
- depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
- /* set the disable and stall bits */
- if (depctl.b.epena)
- {
- depctl.b.epdis = 1;
- }
- depctl.b.stall = 1;
- USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
- }
- else
- {
- depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
- depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
- /* set the stall bit */
- depctl.b.stall = 1;
- USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
- }
- return status;
-}
-
-
-/**
-* @brief Clear the EP STALL
-* @param pdev : Selected device
-* @retval USB_OTG_STS : status
-*/
-USB_OTG_STS USB_OTG_EPClearStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
-{
- USB_OTG_STS status = USB_OTG_OK;
- USB_OTG_DEPCTL_TypeDef depctl;
- __IO uint32_t *depctl_addr;
-
- depctl.d32 = 0;
-
- if (ep->is_in == 1)
- {
- depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
- }
- else
- {
- depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
- }
- depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
- /* clear the stall bits */
- depctl.b.stall = 0;
- if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
- {
- depctl.b.setd0pid = 1; /* DATA0 */
- }
- USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
- return status;
-}
-
-
-/**
-* @brief USB_OTG_ReadDevAllOutEp_itr : returns OUT endpoint interrupt bits
-* @param pdev : Selected device
-* @retval OUT endpoint interrupt bits
-*/
-uint32_t USB_OTG_ReadDevAllOutEp_itr(USB_OTG_CORE_HANDLE *pdev)
-{
- uint32_t v;
- v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT);
- v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK);
- return ((v & 0xffff0000) >> 16);
-}
-
-
-/**
-* @brief USB_OTG_ReadDevOutEP_itr : returns Device OUT EP Interrupt register
-* @param pdev : Selected device
-* @param ep : end point number
-* @retval Device OUT EP Interrupt register
-*/
-uint32_t USB_OTG_ReadDevOutEP_itr(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum)
-{
- uint32_t v;
- v = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT);
- v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOEPMSK);
- return v;
-}
-
-
-/**
-* @brief USB_OTG_ReadDevAllInEPItr : Get int status register
-* @param pdev : Selected device
-* @retval int status register
-*/
-uint32_t USB_OTG_ReadDevAllInEPItr(USB_OTG_CORE_HANDLE *pdev)
-{
- uint32_t v;
- v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT);
- v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK);
- return (v & 0xffff);
-}
-
-/**
-* @brief configures EPO to receive SETUP packets
-* @param None
-* @retval : None
-*/
-void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_DEP0XFRSIZ_TypeDef doeptsize0;
- doeptsize0.d32 = 0;
- doeptsize0.b.supcnt = 3;
- doeptsize0.b.pktcnt = 1;
- doeptsize0.b.xfersize = 8 * 3;
- USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPTSIZ, doeptsize0.d32 );
-
- if (pdev->cfg.dma_enable == 1)
- {
- USB_OTG_DEPCTL_TypeDef doepctl;
- doepctl.d32 = 0;
- USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPDMA,
- (uint32_t)&pdev->dev.setup_packet);
-
- /* EP enable */
- doepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[0]->DOEPCTL);
- doepctl.b.epena = 1;
- doepctl.d32 = 0x80008000;
- USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPCTL, doepctl.d32);
- }
-}
-
-/**
-* @brief USB_OTG_RemoteWakeup : active remote wakeup signalling
-* @param None
-* @retval : None
-*/
-void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev)
-{
-
- USB_OTG_DCTL_TypeDef dctl;
- USB_OTG_DSTS_TypeDef dsts;
- USB_OTG_PCGCCTL_TypeDef power;
-
- if (pdev->dev.DevRemoteWakeup)
- {
- dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
- if(dsts.b.suspsts == 1)
- {
- if(pdev->cfg.low_power)
- {
- /* un-gate USB Core clock */
- power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL);
- power.b.gatehclk = 0;
- power.b.stoppclk = 0;
- USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
- }
- /* active Remote wakeup signaling */
- dctl.d32 = 0;
- dctl.b.rmtwkupsig = 1;
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, 0, dctl.d32);
- USB_OTG_BSP_mDelay(5);
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 );
- }
- }
-}
-
-
-/**
-* @brief USB_OTG_UngateClock : active USB Core clock
-* @param None
-* @retval : None
-*/
-void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev)
-{
- if(pdev->cfg.low_power)
- {
-
- USB_OTG_DSTS_TypeDef dsts;
- USB_OTG_PCGCCTL_TypeDef power;
-
- dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
-
- if(dsts.b.suspsts == 1)
- {
- /* un-gate USB Core clock */
- power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL);
- power.b.gatehclk = 0;
- power.b.stoppclk = 0;
- USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
-
- }
- }
-}
-
-/**
-* @brief Stop the device and clean up fifo's
-* @param None
-* @retval : None
-*/
-void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev)
-{
- uint32_t i;
-
- pdev->dev.device_status = 1;
-
- for (i = 0; i < pdev->cfg.dev_endpoints ; i++)
- {
- USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
- USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
- }
-
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 );
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 );
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 );
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF );
-
- /* Flush the FIFO */
- USB_OTG_FlushRxFifo(pdev);
- USB_OTG_FlushTxFifo(pdev , 0x10 );
-}
-
-/**
-* @brief returns the EP Status
-* @param pdev : Selected device
-* ep : endpoint structure
-* @retval : EP status
-*/
-
-uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep)
-{
- USB_OTG_DEPCTL_TypeDef depctl;
- __IO uint32_t *depctl_addr;
- uint32_t Status = 0;
-
- depctl.d32 = 0;
- if (ep->is_in == 1)
- {
- depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
- depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
-
- if (depctl.b.stall == 1)
- Status = USB_OTG_EP_TX_STALL;
- else if (depctl.b.naksts == 1)
- Status = USB_OTG_EP_TX_NAK;
- else
- Status = USB_OTG_EP_TX_VALID;
-
- }
- else
- {
- depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
- depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
- if (depctl.b.stall == 1)
- Status = USB_OTG_EP_RX_STALL;
- else if (depctl.b.naksts == 1)
- Status = USB_OTG_EP_RX_NAK;
- else
- Status = USB_OTG_EP_RX_VALID;
- }
-
- /* Return the current status */
- return Status;
-}
-
-/**
-* @brief Set the EP Status
-* @param pdev : Selected device
-* Status : new Status
-* ep : EP structure
-* @retval : None
-*/
-void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status)
-{
- USB_OTG_DEPCTL_TypeDef depctl;
- __IO uint32_t *depctl_addr;
-
- depctl.d32 = 0;
-
- /* Process for IN endpoint */
- if (ep->is_in == 1)
- {
- depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
- depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
-
- if (Status == USB_OTG_EP_TX_STALL)
- {
- USB_OTG_EPSetStall(pdev, ep); return;
- }
- else if (Status == USB_OTG_EP_TX_NAK)
- depctl.b.snak = 1;
- else if (Status == USB_OTG_EP_TX_VALID)
- {
- if (depctl.b.stall == 1)
- {
- ep->even_odd_frame = 0;
- USB_OTG_EPClearStall(pdev, ep);
- return;
- }
- depctl.b.cnak = 1;
- depctl.b.usbactep = 1;
- depctl.b.epena = 1;
- }
- else if (Status == USB_OTG_EP_TX_DIS)
- depctl.b.usbactep = 0;
- }
- else /* Process for OUT endpoint */
- {
- depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
- depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
-
- if (Status == USB_OTG_EP_RX_STALL) {
- depctl.b.stall = 1;
- }
- else if (Status == USB_OTG_EP_RX_NAK)
- depctl.b.snak = 1;
- else if (Status == USB_OTG_EP_RX_VALID)
- {
- if (depctl.b.stall == 1)
- {
- ep->even_odd_frame = 0;
- USB_OTG_EPClearStall(pdev, ep);
- return;
- }
- depctl.b.cnak = 1;
- depctl.b.usbactep = 1;
- depctl.b.epena = 1;
- }
- else if (Status == USB_OTG_EP_RX_DIS)
- {
- depctl.b.usbactep = 0;
- }
- }
-
- USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
-}
-
-#endif
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_dcd.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Peripheral Device Interface Layer
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_dcd.h"
-#include "usb_bsp.h"
-
-
-/** @addtogroup USB_OTG_DRIVER
-* @{
-*/
-
-/** @defgroup USB_DCD
-* @brief This file is the interface between EFSL ans Host mass-storage class
-* @{
-*/
-
-
-/** @defgroup USB_DCD_Private_Defines
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USB_DCD_Private_TypesDefinitions
-* @{
-*/
-/**
-* @}
-*/
-
-
-
-/** @defgroup USB_DCD_Private_Macros
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USB_DCD_Private_Variables
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USB_DCD_Private_FunctionPrototypes
-* @{
-*/
-
-/**
-* @}
-*/
-
-
-/** @defgroup USB_DCD_Private_Functions
-* @{
-*/
-
-
-
-void DCD_Init(USB_OTG_CORE_HANDLE *pdev ,
- USB_OTG_CORE_ID_TypeDef coreID)
-{
- uint32_t i;
- USB_OTG_EP *ep;
-
- USB_OTG_SelectCore (pdev , coreID);
-
- pdev->dev.device_status = USB_OTG_DEFAULT;
- pdev->dev.device_address = 0;
-
- /* Init ep structure */
- for (i = 0; i < pdev->cfg.dev_endpoints ; i++)
- {
- ep = &pdev->dev.in_ep[i];
- /* Init ep structure */
- ep->is_in = 1;
- ep->num = i;
- ep->tx_fifo_num = i;
- /* Control until ep is actvated */
- ep->type = EP_TYPE_CTRL;
- ep->maxpacket = USB_OTG_MAX_EP0_SIZE;
- ep->xfer_buff = 0;
- ep->xfer_len = 0;
- }
-
- for (i = 0; i < pdev->cfg.dev_endpoints; i++)
- {
- ep = &pdev->dev.out_ep[i];
- /* Init ep structure */
- ep->is_in = 0;
- ep->num = i;
- ep->tx_fifo_num = i;
- /* Control until ep is activated */
- ep->type = EP_TYPE_CTRL;
- ep->maxpacket = USB_OTG_MAX_EP0_SIZE;
- ep->xfer_buff = 0;
- ep->xfer_len = 0;
- }
-
- USB_OTG_DisableGlobalInt(pdev);
-
- /*Init the Core (common init.) */
- USB_OTG_CoreInit(pdev);
-
-
- /* Force Device Mode*/
- USB_OTG_SetCurrentMode(pdev, DEVICE_MODE);
-
- /* Init Device */
- USB_OTG_CoreInitDev(pdev);
-
-
- /* Enable USB Global interrupt */
- USB_OTG_EnableGlobalInt(pdev);
-}
-
-
-/**
-* @brief Configure an EP
-* @param pdev : Device instance
-* @param epdesc : Endpoint Descriptor
-* @retval : status
-*/
-uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev ,
- uint8_t ep_addr,
- uint16_t ep_mps,
- uint8_t ep_type)
-{
- USB_OTG_EP *ep;
-
- if ((ep_addr & 0x80) == 0x80)
- {
- ep = &pdev->dev.in_ep[ep_addr & 0x7F];
- }
- else
- {
- ep = &pdev->dev.out_ep[ep_addr & 0x7F];
- }
- ep->num = ep_addr & 0x7F;
-
- ep->is_in = (0x80 & ep_addr) != 0;
- ep->maxpacket = ep_mps;
- ep->type = ep_type;
- if (ep->is_in)
- {
- /* Assign a Tx FIFO */
- ep->tx_fifo_num = ep->num;
- }
- /* Set initial data PID. */
- if (ep_type == USB_OTG_EP_BULK )
- {
- ep->data_pid_start = 0;
- }
- USB_OTG_EPActivate(pdev , ep );
- return 0;
-}
-/**
-* @brief called when an EP is disabled
-* @param pdev: device instance
-* @param ep_addr: endpoint address
-* @retval : status
-*/
-uint32_t DCD_EP_Close(USB_OTG_CORE_HANDLE *pdev , uint8_t ep_addr)
-{
- USB_OTG_EP *ep;
-
- if ((ep_addr&0x80) == 0x80)
- {
- ep = &pdev->dev.in_ep[ep_addr & 0x7F];
- }
- else
- {
- ep = &pdev->dev.out_ep[ep_addr & 0x7F];
- }
- ep->num = ep_addr & 0x7F;
- ep->is_in = (0x80 & ep_addr) != 0;
- USB_OTG_EPDeactivate(pdev , ep );
- return 0;
-}
-
-
-/**
-* @brief DCD_EP_PrepareRx
-* @param pdev: device instance
-* @param ep_addr: endpoint address
-* @param pbuf: pointer to Rx buffer
-* @param buf_len: data length
-* @retval : status
-*/
-uint32_t DCD_EP_PrepareRx( USB_OTG_CORE_HANDLE *pdev,
- uint8_t ep_addr,
- uint8_t *pbuf,
- uint16_t buf_len)
-{
- USB_OTG_EP *ep;
-
- ep = &pdev->dev.out_ep[ep_addr & 0x7F];
-
- /*setup and start the Xfer */
- ep->xfer_buff = pbuf;
- ep->xfer_len = buf_len;
- ep->xfer_count = 0;
- ep->is_in = 0;
- ep->num = ep_addr & 0x7F;
-
- if (pdev->cfg.dma_enable == 1)
- {
- ep->dma_addr = (uint32_t)pbuf;
- }
-
- if ( ep->num == 0 )
- {
- USB_OTG_EP0StartXfer(pdev , ep);
- }
- else
- {
- USB_OTG_EPStartXfer(pdev, ep );
- }
- return 0;
-}
-
-/**
-* @brief Transmit data over USB
-* @param pdev: device instance
-* @param ep_addr: endpoint address
-* @param pbuf: pointer to Tx buffer
-* @param buf_len: data length
-* @retval : status
-*/
-uint32_t DCD_EP_Tx ( USB_OTG_CORE_HANDLE *pdev,
- uint8_t ep_addr,
- uint8_t *pbuf,
- uint32_t buf_len)
-{
- USB_OTG_EP *ep;
-
- ep = &pdev->dev.in_ep[ep_addr & 0x7F];
-
- /* Setup and start the Transfer */
- ep->is_in = 1;
- ep->num = ep_addr & 0x7F;
- ep->xfer_buff = pbuf;
- ep->dma_addr = (uint32_t)pbuf;
- ep->xfer_count = 0;
- ep->xfer_len = buf_len;
-
- if ( ep->num == 0 )
- {
- USB_OTG_EP0StartXfer(pdev , ep);
- }
- else
- {
- USB_OTG_EPStartXfer(pdev, ep );
- }
- return 0;
-}
-
-
-/**
-* @brief Stall an endpoint.
-* @param pdev: device instance
-* @param epnum: endpoint address
-* @retval : status
-*/
-uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
-{
- USB_OTG_EP *ep;
- if ((0x80 & epnum) == 0x80)
- {
- ep = &pdev->dev.in_ep[epnum & 0x7F];
- }
- else
- {
- ep = &pdev->dev.out_ep[epnum];
- }
-
- ep->is_stall = 1;
- ep->num = epnum & 0x7F;
- ep->is_in = ((epnum & 0x80) == 0x80);
-
- USB_OTG_EPSetStall(pdev , ep);
- return (0);
-}
-
-
-/**
-* @brief Clear stall condition on endpoints.
-* @param pdev: device instance
-* @param epnum: endpoint address
-* @retval : status
-*/
-uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
-{
- USB_OTG_EP *ep;
- if ((0x80 & epnum) == 0x80)
- {
- ep = &pdev->dev.in_ep[epnum & 0x7F];
- }
- else
- {
- ep = &pdev->dev.out_ep[epnum];
- }
-
- ep->is_stall = 0;
- ep->num = epnum & 0x7F;
- ep->is_in = ((epnum & 0x80) == 0x80);
-
- USB_OTG_EPClearStall(pdev , ep);
- return (0);
-}
-
-
-/**
-* @brief This Function flushes the FIFOs.
-* @param pdev: device instance
-* @param epnum: endpoint address
-* @retval : status
-*/
-uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum)
-{
-
- if ((epnum & 0x80) == 0x80)
- {
- USB_OTG_FlushTxFifo(pdev, epnum & 0x7F);
- }
- else
- {
- USB_OTG_FlushRxFifo(pdev);
- }
-
- return (0);
-}
-
-
-/**
-* @brief This Function set USB device address
-* @param pdev: device instance
-* @param address: new device address
-* @retval : status
-*/
-void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev, uint8_t address)
-{
- USB_OTG_DCFG_TypeDef dcfg;
- dcfg.d32 = 0;
- dcfg.b.devaddr = address;
- USB_OTG_MODIFY_REG32( &pdev->regs.DREGS->DCFG, 0, dcfg.d32);
-}
-
-/**
-* @brief Connect device (enable internal pull-up)
-* @param pdev: device instance
-* @retval : None
-*/
-void DCD_DevConnect (USB_OTG_CORE_HANDLE *pdev)
-{
-#ifndef USE_OTG_MODE
- USB_OTG_DCTL_TypeDef dctl;
- dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL);
- /* Connect device */
- dctl.b.sftdiscon = 0;
- USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32);
- USB_OTG_BSP_mDelay(3);
-#endif
-}
-
-
-/**
-* @brief Disconnect device (disable internal pull-up)
-* @param pdev: device instance
-* @retval : None
-*/
-void DCD_DevDisconnect (USB_OTG_CORE_HANDLE *pdev)
-{
-#ifndef USE_OTG_MODE
- USB_OTG_DCTL_TypeDef dctl;
- dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL);
- /* Disconnect device for 3ms */
- dctl.b.sftdiscon = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32);
- USB_OTG_BSP_mDelay(3);
-#endif
-}
-
-
-/**
-* @brief returns the EP Status
-* @param pdev : Selected device
-* epnum : endpoint address
-* @retval : EP status
-*/
-
-uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,uint8_t epnum)
-{
- USB_OTG_EP *ep;
- uint32_t Status = 0;
-
- if ((0x80 & epnum) == 0x80)
- {
- ep = &pdev->dev.in_ep[epnum & 0x7F];
- }
- else
- {
- ep = &pdev->dev.out_ep[epnum];
- }
-
- Status = USB_OTG_GetEPStatus(pdev ,ep);
-
- /* Return the current status */
- return Status;
-}
-
-/**
-* @brief Set the EP Status
-* @param pdev : Selected device
-* Status : new Status
-* epnum : EP address
-* @retval : None
-*/
-void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum , uint32_t Status)
-{
- USB_OTG_EP *ep;
-
- if ((0x80 & epnum) == 0x80)
- {
- ep = &pdev->dev.in_ep[epnum & 0x7F];
- }
- else
- {
- ep = &pdev->dev.out_ep[epnum];
- }
-
- USB_OTG_SetEPStatus(pdev ,ep , Status);
-}
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_dcd_int.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Peripheral Device interrupt subroutines
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_dcd_int.h"
-/** @addtogroup USB_OTG_DRIVER
-* @{
-*/
-
-/** @defgroup USB_DCD_INT
-* @brief This file contains the interrupt subroutines for the Device mode.
-* @{
-*/
-
-
-/** @defgroup USB_DCD_INT_Private_Defines
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USB_DCD_INT_Private_TypesDefinitions
-* @{
-*/
-/**
-* @}
-*/
-
-
-
-/** @defgroup USB_DCD_INT_Private_Macros
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USB_DCD_INT_Private_Variables
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USB_DCD_INT_Private_FunctionPrototypes
-* @{
-*/
-/* static functions */
-static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum);
-
-/* Interrupt Handlers */
-static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev);
-static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev);
-static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev);
-
-static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev);
-static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev , uint32_t epnum);
-
-static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev);
-static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev);
-static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev);
-static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev);
-
-static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev);
-static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev);
-#ifdef VBUS_SENSING_ENABLED
-static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev);
-static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev);
-#endif
-
-/**
-* @}
-*/
-
-
-/** @defgroup USB_DCD_INT_Private_Functions
-* @{
-*/
-
-
-#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
-/**
-* @brief USBD_OTG_EP1OUT_ISR_Handler
-* handles all USB Interrupts
-* @param pdev: device instance
-* @retval status
-*/
-uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
-{
-
- USB_OTG_DOEPINTn_TypeDef doepint;
- USB_OTG_DEPXFRSIZ_TypeDef deptsiz;
-
- doepint.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[1]->DOEPINT);
- doepint.d32&= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOUTEP1MSK);
-
- /* Transfer complete */
- if ( doepint.b.xfercompl )
- {
- /* Clear the bit in DOEPINTn for this interrupt */
- CLEAR_OUT_EP_INTR(1, xfercompl);
- if (pdev->cfg.dma_enable == 1)
- {
- deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[1]->DOEPTSIZ));
- /*ToDo : handle more than one single MPS size packet */
- pdev->dev.out_ep[1].xfer_count = pdev->dev.out_ep[1].maxpacket - \
- deptsiz.b.xfersize;
- }
- /* Inform upper layer: data ready */
- /* RX COMPLETE */
- USBD_DCD_INT_fops->DataOutStage(pdev , 1);
-
- }
-
- /* Endpoint disable */
- if ( doepint.b.epdisabled )
- {
- /* Clear the bit in DOEPINTn for this interrupt */
- CLEAR_OUT_EP_INTR(1, epdisabled);
- }
- /* AHB Error */
- if ( doepint.b.ahberr )
- {
- CLEAR_OUT_EP_INTR(1, ahberr);
- }
- return 1;
-}
-
-/**
-* @brief USBD_OTG_EP1IN_ISR_Handler
-* handles all USB Interrupts
-* @param pdev: device instance
-* @retval status
-*/
-uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
-{
-
- USB_OTG_DIEPINTn_TypeDef diepint;
- uint32_t fifoemptymsk, msk, emp;
-
- msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DINEP1MSK);
- emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK);
- msk |= ((emp >> 1 ) & 0x1) << 7;
- diepint.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[1]->DIEPINT) & msk;
-
- if ( diepint.b.xfercompl )
- {
- fifoemptymsk = 0x1 << 1;
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0);
- CLEAR_IN_EP_INTR(1, xfercompl);
- /* TX COMPLETE */
- USBD_DCD_INT_fops->DataInStage(pdev , 1);
- }
- if ( diepint.b.ahberr )
- {
- CLEAR_IN_EP_INTR(1, ahberr);
- }
- if ( diepint.b.epdisabled )
- {
- CLEAR_IN_EP_INTR(1, epdisabled);
- }
- if ( diepint.b.timeout )
- {
- CLEAR_IN_EP_INTR(1, timeout);
- }
- if (diepint.b.intktxfemp)
- {
- CLEAR_IN_EP_INTR(1, intktxfemp);
- }
- if (diepint.b.intknepmis)
- {
- CLEAR_IN_EP_INTR(1, intknepmis);
- }
- if (diepint.b.inepnakeff)
- {
- CLEAR_IN_EP_INTR(1, inepnakeff);
- }
- if (diepint.b.emptyintr)
- {
- DCD_WriteEmptyTxFifo(pdev , 1);
- CLEAR_IN_EP_INTR(1, emptyintr);
- }
- return 1;
-}
-#endif
-
-/**
-* @brief STM32_USBF_OTG_ISR_Handler
-* handles all USB Interrupts
-* @param pdev: device instance
-* @retval status
-*/
-uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_GINTSTS_TypeDef gintr_status;
- uint32_t retval = 0;
-
- if (USB_OTG_IsDeviceMode(pdev)) /* ensure that we are in device mode */
- {
- gintr_status.d32 = USB_OTG_ReadCoreItr(pdev);
- if (!gintr_status.d32) /* avoid spurious interrupt */
- {
- return 0;
- }
-
- if (gintr_status.b.outepintr)
- {
- retval |= DCD_HandleOutEP_ISR(pdev);
- }
-
- if (gintr_status.b.inepint)
- {
- retval |= DCD_HandleInEP_ISR(pdev);
- }
-
- if (gintr_status.b.modemismatch)
- {
- USB_OTG_GINTSTS_TypeDef gintsts;
-
- /* Clear interrupt */
- gintsts.d32 = 0;
- gintsts.b.modemismatch = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
- }
-
- if (gintr_status.b.wkupintr)
- {
- retval |= DCD_HandleResume_ISR(pdev);
- }
-
- if (gintr_status.b.usbsuspend)
- {
- retval |= DCD_HandleUSBSuspend_ISR(pdev);
- }
- if (gintr_status.b.sofintr)
- {
- retval |= DCD_HandleSof_ISR(pdev);
-
- }
-
- if (gintr_status.b.rxstsqlvl)
- {
- retval |= DCD_HandleRxStatusQueueLevel_ISR(pdev);
-
- }
-
- if (gintr_status.b.usbreset)
- {
- retval |= DCD_HandleUsbReset_ISR(pdev);
-
- }
- if (gintr_status.b.enumdone)
- {
- retval |= DCD_HandleEnumDone_ISR(pdev);
- }
-
- if (gintr_status.b.incomplisoin)
- {
- retval |= DCD_IsoINIncomplete_ISR(pdev);
- }
-
- if (gintr_status.b.incomplisoout)
- {
- retval |= DCD_IsoOUTIncomplete_ISR(pdev);
- }
-#ifdef VBUS_SENSING_ENABLED
- if (gintr_status.b.sessreqintr)
- {
- retval |= DCD_SessionRequest_ISR(pdev);
- }
-
- if (gintr_status.b.otgintr)
- {
- retval |= DCD_OTG_ISR(pdev);
- }
-#endif
- }
- return retval;
-}
-
-#ifdef VBUS_SENSING_ENABLED
-/**
-* @brief DCD_SessionRequest_ISR
-* Indicates that the USB_OTG controller has detected a connection
-* @param pdev: device instance
-* @retval status
-*/
-static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_GINTSTS_TypeDef gintsts;
- USBD_DCD_INT_fops->DevConnected (pdev);
-
- /* Clear interrupt */
- gintsts.d32 = 0;
- gintsts.b.sessreqintr = 1;
- USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
- return 1;
-}
-
-/**
-* @brief DCD_OTG_ISR
-* Indicates that the USB_OTG controller has detected an OTG event:
-* used to detect the end of session i.e. disconnection
-* @param pdev: device instance
-* @retval status
-*/
-static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev)
-{
-
- USB_OTG_GOTGINT_TypeDef gotgint;
-
- gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT);
-
- if (gotgint.b.sesenddet)
- {
- USBD_DCD_INT_fops->DevDisconnected (pdev);
- }
- /* Clear OTG interrupt */
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32);
- return 1;
-}
-#endif
-/**
-* @brief DCD_HandleResume_ISR
-* Indicates that the USB_OTG controller has detected a resume or
-* remote Wake-up sequence
-* @param pdev: device instance
-* @retval status
-*/
-static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_GINTSTS_TypeDef gintsts;
- USB_OTG_DCTL_TypeDef devctl;
- USB_OTG_PCGCCTL_TypeDef power;
-
- if(pdev->cfg.low_power)
- {
- /* un-gate USB Core clock */
- power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL);
- power.b.gatehclk = 0;
- power.b.stoppclk = 0;
- USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
- }
-
- /* Clear the Remote Wake-up Signaling */
- devctl.d32 = 0;
- devctl.b.rmtwkupsig = 1;
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, devctl.d32, 0);
-
- /* Inform upper layer by the Resume Event */
- USBD_DCD_INT_fops->Resume (pdev);
-
- /* Clear interrupt */
- gintsts.d32 = 0;
- gintsts.b.wkupintr = 1;
- USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
- return 1;
-}
-
-/**
-* @brief USB_OTG_HandleUSBSuspend_ISR
-* Indicates that SUSPEND state has been detected on the USB
-* @param pdev: device instance
-* @retval status
-*/
-static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_GINTSTS_TypeDef gintsts;
- USB_OTG_PCGCCTL_TypeDef power;
- USB_OTG_DSTS_TypeDef dsts;
-
- USBD_DCD_INT_fops->Suspend (pdev);
-
- dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
-
- /* Clear interrupt */
- gintsts.d32 = 0;
- gintsts.b.usbsuspend = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
-
- if((pdev->cfg.low_power) && (dsts.b.suspsts == 1))
- {
- /* switch-off the clocks */
- power.d32 = 0;
- power.b.stoppclk = 1;
- USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32);
-
- power.b.gatehclk = 1;
- USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32);
-
- /* Request to enter Sleep mode after exit from current ISR */
- SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk);
- }
- return 1;
-}
-
-/**
-* @brief DCD_HandleInEP_ISR
-* Indicates that an IN EP has a pending Interrupt
-* @param pdev: device instance
-* @retval status
-*/
-static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_DIEPINTn_TypeDef diepint;
-
- uint32_t ep_intr;
- uint32_t epnum = 0;
- uint32_t fifoemptymsk;
- diepint.d32 = 0;
- ep_intr = USB_OTG_ReadDevAllInEPItr(pdev);
-
- while ( ep_intr )
- {
- if (ep_intr&0x1) /* In ITR */
- {
- diepint.d32 = DCD_ReadDevInEP(pdev , epnum); /* Get In ITR status */
- if ( diepint.b.xfercompl )
- {
- fifoemptymsk = 0x1 << epnum;
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0);
- CLEAR_IN_EP_INTR(epnum, xfercompl);
- /* TX COMPLETE */
- USBD_DCD_INT_fops->DataInStage(pdev , epnum);
-
- if (pdev->cfg.dma_enable == 1)
- {
- if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_IN))
- {
- /* prepare to rx more setup packets */
- USB_OTG_EP0_OutStart(pdev);
- }
- }
- }
- if ( diepint.b.ahberr )
- {
- CLEAR_IN_EP_INTR(epnum, ahberr);
- }
- if ( diepint.b.timeout )
- {
- CLEAR_IN_EP_INTR(epnum, timeout);
- }
- if (diepint.b.intktxfemp)
- {
- CLEAR_IN_EP_INTR(epnum, intktxfemp);
- }
- if (diepint.b.intknepmis)
- {
- CLEAR_IN_EP_INTR(epnum, intknepmis);
- }
- if (diepint.b.inepnakeff)
- {
- CLEAR_IN_EP_INTR(epnum, inepnakeff);
- }
- if ( diepint.b.epdisabled )
- {
- CLEAR_IN_EP_INTR(epnum, epdisabled);
- }
- if (diepint.b.emptyintr)
- {
-
- DCD_WriteEmptyTxFifo(pdev , epnum);
-
- CLEAR_IN_EP_INTR(epnum, emptyintr);
- }
- }
- epnum++;
- ep_intr >>= 1;
- }
-
- return 1;
-}
-
-/**
-* @brief DCD_HandleOutEP_ISR
-* Indicates that an OUT EP has a pending Interrupt
-* @param pdev: device instance
-* @retval status
-*/
-static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev)
-{
- uint32_t ep_intr;
- USB_OTG_DOEPINTn_TypeDef doepint;
- USB_OTG_DEPXFRSIZ_TypeDef deptsiz;
- uint32_t epnum = 0;
-
- doepint.d32 = 0;
-
- /* Read in the device interrupt bits */
- ep_intr = USB_OTG_ReadDevAllOutEp_itr(pdev);
-
- while ( ep_intr )
- {
- if (ep_intr&0x1)
- {
-
- doepint.d32 = USB_OTG_ReadDevOutEP_itr(pdev, epnum);
-
- /* Transfer complete */
- if ( doepint.b.xfercompl )
- {
- /* Clear the bit in DOEPINTn for this interrupt */
- CLEAR_OUT_EP_INTR(epnum, xfercompl);
- if (pdev->cfg.dma_enable == 1)
- {
- deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[epnum]->DOEPTSIZ));
- /*ToDo : handle more than one single MPS size packet */
- pdev->dev.out_ep[epnum].xfer_count = pdev->dev.out_ep[epnum].maxpacket - \
- deptsiz.b.xfersize;
- }
- /* Inform upper layer: data ready */
- /* RX COMPLETE */
- USBD_DCD_INT_fops->DataOutStage(pdev , epnum);
-
- if (pdev->cfg.dma_enable == 1)
- {
- if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_OUT))
- {
- /* prepare to rx more setup packets */
- USB_OTG_EP0_OutStart(pdev);
- }
- }
- }
- /* Endpoint disable */
- if ( doepint.b.epdisabled )
- {
- /* Clear the bit in DOEPINTn for this interrupt */
- CLEAR_OUT_EP_INTR(epnum, epdisabled);
- }
- /* AHB Error */
- if ( doepint.b.ahberr )
- {
- CLEAR_OUT_EP_INTR(epnum, ahberr);
- }
- /* Setup Phase Done (control EPs) */
- if ( doepint.b.setup )
- {
-
- /* inform the upper layer that a setup packet is available */
- /* SETUP COMPLETE */
- USBD_DCD_INT_fops->SetupStage(pdev);
- CLEAR_OUT_EP_INTR(epnum, setup);
- }
- }
- epnum++;
- ep_intr >>= 1;
- }
- return 1;
-}
-
-/**
-* @brief DCD_HandleSof_ISR
-* Handles the SOF Interrupts
-* @param pdev: device instance
-* @retval status
-*/
-static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_GINTSTS_TypeDef GINTSTS;
-
-
- USBD_DCD_INT_fops->SOF(pdev);
-
- /* Clear interrupt */
- GINTSTS.d32 = 0;
- GINTSTS.b.sofintr = 1;
- USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, GINTSTS.d32);
-
- return 1;
-}
-
-/**
-* @brief DCD_HandleRxStatusQueueLevel_ISR
-* Handles the Rx Status Queue Level Interrupt
-* @param pdev: device instance
-* @retval status
-*/
-static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_GINTMSK_TypeDef int_mask;
- USB_OTG_DRXSTS_TypeDef status;
- USB_OTG_EP *ep;
-
- /* Disable the Rx Status Queue Level interrupt */
- int_mask.d32 = 0;
- int_mask.b.rxstsqlvl = 1;
- USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32, 0);
-
- /* Get the Status from the top of the FIFO */
- status.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRXSTSP );
-
- ep = &pdev->dev.out_ep[status.b.epnum];
-
- switch (status.b.pktsts)
- {
- case STS_GOUT_NAK:
- break;
- case STS_DATA_UPDT:
- if (status.b.bcnt)
- {
- USB_OTG_ReadPacket(pdev,ep->xfer_buff, status.b.bcnt);
- ep->xfer_buff += status.b.bcnt;
- ep->xfer_count += status.b.bcnt;
- }
- break;
- case STS_XFER_COMP:
- break;
- case STS_SETUP_COMP:
- break;
- case STS_SETUP_UPDT:
- /* Copy the setup packet received in FIFO into the setup buffer in RAM */
- USB_OTG_ReadPacket(pdev , pdev->dev.setup_packet, 8);
- ep->xfer_count += status.b.bcnt;
- break;
- default:
- break;
- }
-
- /* Enable the Rx Status Queue Level interrupt */
- USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, int_mask.d32);
-
- return 1;
-}
-
-/**
-* @brief DCD_WriteEmptyTxFifo
-* check FIFO for the next packet to be loaded
-* @param pdev: device instance
-* @retval status
-*/
-static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t epnum)
-{
- USB_OTG_DTXFSTSn_TypeDef txstatus;
- USB_OTG_EP *ep;
- uint32_t len = 0;
- uint32_t len32b;
- txstatus.d32 = 0;
-
- ep = &pdev->dev.in_ep[epnum];
-
- len = ep->xfer_len - ep->xfer_count;
-
- if (len > ep->maxpacket)
- {
- len = ep->maxpacket;
- }
-
- len32b = (len + 3) / 4;
- txstatus.d32 = USB_OTG_READ_REG32( &pdev->regs.INEP_REGS[epnum]->DTXFSTS);
-
-
-
- while (txstatus.b.txfspcavail > len32b &&
- ep->xfer_count < ep->xfer_len &&
- ep->xfer_len != 0)
- {
- /* Write the FIFO */
- len = ep->xfer_len - ep->xfer_count;
-
- if (len > ep->maxpacket)
- {
- len = ep->maxpacket;
- }
- len32b = (len + 3) / 4;
-
- USB_OTG_WritePacket (pdev , ep->xfer_buff, epnum, len);
-
- ep->xfer_buff += len;
- ep->xfer_count += len;
-
- txstatus.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DTXFSTS);
- }
-
- return 1;
-}
-
-/**
-* @brief DCD_HandleUsbReset_ISR
-* This interrupt occurs when a USB Reset is detected
-* @param pdev: device instance
-* @retval status
-*/
-static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_DAINT_TypeDef daintmsk;
- USB_OTG_DOEPMSK_TypeDef doepmsk;
- USB_OTG_DIEPMSK_TypeDef diepmsk;
- USB_OTG_DCFG_TypeDef dcfg;
- USB_OTG_DCTL_TypeDef dctl;
- USB_OTG_GINTSTS_TypeDef gintsts;
- uint32_t i;
-
- dctl.d32 = 0;
- daintmsk.d32 = 0;
- doepmsk.d32 = 0;
- diepmsk.d32 = 0;
- dcfg.d32 = 0;
- gintsts.d32 = 0;
-
- /* Clear the Remote Wake-up Signaling */
- dctl.b.rmtwkupsig = 1;
- USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 );
-
- /* Flush the Tx FIFO */
- USB_OTG_FlushTxFifo(pdev , 0 );
-
- for (i = 0; i < pdev->cfg.dev_endpoints ; i++)
- {
- USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
- USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
- }
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF );
-
- daintmsk.ep.in = 1;
- daintmsk.ep.out = 1;
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, daintmsk.d32 );
-
- doepmsk.b.setup = 1;
- doepmsk.b.xfercompl = 1;
- doepmsk.b.ahberr = 1;
- doepmsk.b.epdisabled = 1;
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, doepmsk.d32 );
-#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOUTEP1MSK, doepmsk.d32 );
-#endif
- diepmsk.b.xfercompl = 1;
- diepmsk.b.timeout = 1;
- diepmsk.b.epdisabled = 1;
- diepmsk.b.ahberr = 1;
- diepmsk.b.intknepmis = 1;
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, diepmsk.d32 );
-#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DINEP1MSK, diepmsk.d32 );
-#endif
- /* Reset Device Address */
- dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG);
- dcfg.b.devaddr = 0;
- USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32);
-
-
- /* setup EP0 to receive SETUP packets */
- USB_OTG_EP0_OutStart(pdev);
-
- /* Clear interrupt */
- gintsts.d32 = 0;
- gintsts.b.usbreset = 1;
- USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
-
- /*Reset internal state machine */
- USBD_DCD_INT_fops->Reset(pdev);
- return 1;
-}
-
-/**
-* @brief DCD_HandleEnumDone_ISR
-* Read the device status register and set the device speed
-* @param pdev: device instance
-* @retval status
-*/
-static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_GINTSTS_TypeDef gintsts;
- USB_OTG_GUSBCFG_TypeDef gusbcfg;
-
- USB_OTG_EP0Activate(pdev);
-
- /* Set USB turn-around time based on device speed and PHY interface. */
- gusbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
-
- /* Full or High speed */
- if ( USB_OTG_GetDeviceSpeed(pdev) == USB_SPEED_HIGH)
- {
- pdev->cfg.speed = USB_OTG_SPEED_HIGH;
- pdev->cfg.mps = USB_OTG_HS_MAX_PACKET_SIZE ;
- gusbcfg.b.usbtrdtim = 9;
- }
- else
- {
- pdev->cfg.speed = USB_OTG_SPEED_FULL;
- pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ;
- gusbcfg.b.usbtrdtim = 5;
- }
-
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, gusbcfg.d32);
-
- /* Clear interrupt */
- gintsts.d32 = 0;
- gintsts.b.enumdone = 1;
- USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, gintsts.d32 );
- return 1;
-}
-
-
-/**
-* @brief DCD_IsoINIncomplete_ISR
-* handle the ISO IN incomplete interrupt
-* @param pdev: device instance
-* @retval status
-*/
-static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_GINTSTS_TypeDef gintsts;
-
- gintsts.d32 = 0;
-
- USBD_DCD_INT_fops->IsoINIncomplete (pdev);
-
- /* Clear interrupt */
- gintsts.b.incomplisoin = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
-
- return 1;
-}
-
-/**
-* @brief DCD_IsoOUTIncomplete_ISR
-* handle the ISO OUT incomplete interrupt
-* @param pdev: device instance
-* @retval status
-*/
-static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_GINTSTS_TypeDef gintsts;
-
- gintsts.d32 = 0;
-
- USBD_DCD_INT_fops->IsoOUTIncomplete (pdev);
-
- /* Clear interrupt */
- gintsts.b.incomplisoout = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
- return 1;
-}
-/**
-* @brief DCD_ReadDevInEP
-* Reads ep flags
-* @param pdev: device instance
-* @retval status
-*/
-static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
-{
- uint32_t v, msk, emp;
- msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPMSK);
- emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK);
- msk |= ((emp >> epnum) & 0x1) << 7;
- v = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT) & msk;
- return v;
-}
-
-
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_hcd.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Host Interface Layer
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_core.h"
-#include "usb_hcd.h"
-#include "usb_conf.h"
-#include "usb_bsp.h"
-
-
-/** @addtogroup USB_OTG_DRIVER
- * @{
- */
-
-/** @defgroup USB_HCD
- * @brief This file is the interface between EFSL ans Host mass-storage class
- * @{
- */
-
-
-/** @defgroup USB_HCD_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_HCD_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-
-/** @defgroup USB_HCD_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_HCD_Private_Variables
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_HCD_Private_FunctionPrototypes
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_HCD_Private_Functions
- * @{
- */
-
-/**
- * @brief HCD_Init
- * Initialize the HOST portion of the driver.
- * @param pdev: Selected device
- * @param base_address: OTG base address
- * @retval Status
- */
-uint32_t HCD_Init(USB_OTG_CORE_HANDLE *pdev ,
- USB_OTG_CORE_ID_TypeDef coreID)
-{
- uint8_t i = 0;
- pdev->host.ConnSts = 0;
-
- for (i= 0; i< USB_OTG_MAX_TX_FIFOS; i++)
- {
- pdev->host.ErrCnt[i] = 0;
- pdev->host.XferCnt[i] = 0;
- pdev->host.HC_Status[i] = HC_IDLE;
- }
- pdev->host.hc[0].max_packet = 8;
-
- USB_OTG_SelectCore(pdev, coreID);
-#ifndef DUAL_ROLE_MODE_ENABLED
- USB_OTG_DisableGlobalInt(pdev);
- USB_OTG_CoreInit(pdev);
-
- /* Force Host Mode*/
- USB_OTG_SetCurrentMode(pdev , HOST_MODE);
- USB_OTG_CoreInitHost(pdev);
- USB_OTG_EnableGlobalInt(pdev);
-#endif
-
- return 0;
-}
-
-
-/**
- * @brief HCD_GetCurrentSpeed
- * Get Current device Speed.
- * @param pdev : Selected device
- * @retval Status
- */
-
-uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_HPRT0_TypeDef HPRT0;
- HPRT0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
-
- return HPRT0.b.prtspd;
-}
-
-/**
- * @brief HCD_ResetPort
- * Issues the reset command to device
- * @param pdev : Selected device
- * @retval Status
- */
-uint32_t HCD_ResetPort(USB_OTG_CORE_HANDLE *pdev)
-{
- /*
- Before starting to drive a USB reset, the application waits for the OTG
- interrupt triggered by the debounce done bit (DBCDNE bit in OTG_FS_GOTGINT),
- which indicates that the bus is stable again after the electrical debounce
- caused by the attachment of a pull-up resistor on DP (FS) or DM (LS).
- */
-
- USB_OTG_ResetPort(pdev);
- return 0;
-}
-
-/**
- * @brief HCD_IsDeviceConnected
- * Check if the device is connected.
- * @param pdev : Selected device
- * @retval Device connection status. 1 -> connected and 0 -> disconnected
- *
- */
-uint32_t HCD_IsDeviceConnected(USB_OTG_CORE_HANDLE *pdev)
-{
- return (pdev->host.ConnSts);
-}
-
-/**
- * @brief HCD_GetCurrentFrame
- * This function returns the frame number for sof packet
- * @param pdev : Selected device
- * @retval Frame number
- *
- */
-uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev)
-{
- return (USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0xFFFF) ;
-}
-
-/**
- * @brief HCD_GetURB_State
- * This function returns the last URBstate
- * @param pdev: Selected device
- * @retval URB_STATE
- *
- */
-URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev , uint8_t ch_num)
-{
- return pdev->host.URB_State[ch_num] ;
-}
-
-/**
- * @brief HCD_GetXferCnt
- * This function returns the last URBstate
- * @param pdev: Selected device
- * @retval No. of data bytes transferred
- *
- */
-uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
-{
- return pdev->host.XferCnt[ch_num] ;
-}
-
-
-
-/**
- * @brief HCD_GetHCState
- * This function returns the HC Status
- * @param pdev: Selected device
- * @retval HC_STATUS
- *
- */
-HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev , uint8_t ch_num)
-{
- return pdev->host.HC_Status[ch_num] ;
-}
-
-/**
- * @brief HCD_HC_Init
- * This function prepare a HC and start a transfer
- * @param pdev: Selected device
- * @param hc_num: Channel number
- * @retval status
- */
-uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
-{
- return USB_OTG_HC_Init(pdev, hc_num);
-}
-
-/**
- * @brief HCD_SubmitRequest
- * This function prepare a HC and start a transfer
- * @param pdev: Selected device
- * @param hc_num: Channel number
- * @retval status
- */
-uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
-{
-
- pdev->host.URB_State[hc_num] = URB_IDLE;
- pdev->host.hc[hc_num].xfer_count = 0 ;
- return USB_OTG_HC_StartXfer(pdev, hc_num);
-}
-
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_hcd_int.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief Host driver interrupt subroutines
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_core.h"
-#include "usb_defines.h"
-#include "usb_hcd_int.h"
-
-#if defined (__CC_ARM) /*!< ARM Compiler */
- #pragma O0
-#elif defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma O0
-#elif defined (__GNUC__) /*!< GNU Compiler */
- #pragma GCC optimize ("O0")
-#elif defined (__TASKING__) /*!< TASKING Compiler */
- #pragma optimize=0
-
-#endif /* __CC_ARM */
-
-/** @addtogroup USB_OTG_DRIVER
- * @{
- */
-
-/** @defgroup USB_HCD_INT
- * @brief This file contains the interrupt subroutines for the Host mode.
- * @{
- */
-
-
-/** @defgroup USB_HCD_INT_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_HCD_INT_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-
-/** @defgroup USB_HCD_INT_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_HCD_INT_Private_Variables
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_HCD_INT_Private_FunctionPrototypes
- * @{
- */
-
-static uint32_t USB_OTG_USBH_handle_sof_ISR(USB_OTG_CORE_HANDLE *pdev);
-static uint32_t USB_OTG_USBH_handle_port_ISR(USB_OTG_CORE_HANDLE *pdev);
-static uint32_t USB_OTG_USBH_handle_hc_ISR (USB_OTG_CORE_HANDLE *pdev);
-static uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev ,
- uint32_t num);
-static uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev ,
- uint32_t num);
-static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev);
-static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev);
-static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev);
-static uint32_t USB_OTG_USBH_handle_Disconnect_ISR (USB_OTG_CORE_HANDLE *pdev);
-static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev);
-
-/**
- * @}
- */
-
-
-/** @defgroup USB_HCD_INT_Private_Functions
- * @{
- */
-
-/**
- * @brief HOST_Handle_ISR
- * This function handles all USB Host Interrupts
- * @param pdev: Selected device
- * @retval status
- */
-
-uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_GINTSTS_TypeDef gintsts;
- uint32_t retval = 0;
-
- gintsts.d32 = 0;
-
- /* Check if HOST Mode */
- if (USB_OTG_IsHostMode(pdev))
- {
- gintsts.d32 = USB_OTG_ReadCoreItr(pdev);
- if (!gintsts.d32)
- {
- return 0;
- }
-
- if (gintsts.b.sofintr)
- {
- retval |= USB_OTG_USBH_handle_sof_ISR (pdev);
- }
-
- if (gintsts.b.rxstsqlvl)
- {
- retval |= USB_OTG_USBH_handle_rx_qlvl_ISR (pdev);
- }
-
- if (gintsts.b.nptxfempty)
- {
- retval |= USB_OTG_USBH_handle_nptxfempty_ISR (pdev);
- }
-
- if (gintsts.b.ptxfempty)
- {
- retval |= USB_OTG_USBH_handle_ptxfempty_ISR (pdev);
- }
-
- if (gintsts.b.hcintr)
- {
- retval |= USB_OTG_USBH_handle_hc_ISR (pdev);
- }
-
- if (gintsts.b.portintr)
- {
- retval |= USB_OTG_USBH_handle_port_ISR (pdev);
- }
-
- if (gintsts.b.disconnect)
- {
- retval |= USB_OTG_USBH_handle_Disconnect_ISR (pdev);
-
- }
-
- if (gintsts.b.incomplisoout)
- {
- retval |= USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (pdev);
- }
-
-
- }
- return retval;
-}
-
-/**
- * @brief USB_OTG_USBH_handle_hc_ISR
- * This function indicates that one or more host channels has a pending
- * @param pdev: Selected device
- * @retval status
- */
-static uint32_t USB_OTG_USBH_handle_hc_ISR (USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_HAINT_TypeDef haint;
- USB_OTG_HCCHAR_TypeDef hcchar;
- uint32_t i = 0;
- uint32_t retval = 0;
-
- /* Clear appropriate bits in HCINTn to clear the interrupt bit in
- * GINTSTS */
-
- haint.d32 = USB_OTG_ReadHostAllChannels_intr(pdev);
-
- for (i = 0; i < pdev->cfg.host_channels ; i++)
- {
- if (haint.b.chint & (1 << i))
- {
- hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR);
-
- if (hcchar.b.epdir)
- {
- retval |= USB_OTG_USBH_handle_hc_n_In_ISR (pdev, i);
- }
- else
- {
- retval |= USB_OTG_USBH_handle_hc_n_Out_ISR (pdev, i);
- }
- }
- }
-
- return retval;
-}
-
-/**
- * @brief USB_OTG_otg_hcd_handle_sof_intr
- * Handles the start-of-frame interrupt in host mode.
- * @param pdev: Selected device
- * @retval status
- */
-static uint32_t USB_OTG_USBH_handle_sof_ISR (USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_GINTSTS_TypeDef gintsts;
-
-
- gintsts.d32 = 0;
- /* Clear interrupt */
- gintsts.b.sofintr = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
-
- return 1;
-}
-
-/**
- * @brief USB_OTG_USBH_handle_Disconnect_ISR
- * Handles disconnect event.
- * @param pdev: Selected device
- * @retval status
- */
-static uint32_t USB_OTG_USBH_handle_Disconnect_ISR (USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_GINTSTS_TypeDef gintsts;
-
- pdev->host.ConnSts = 0;
- gintsts.d32 = 0;
-
- pdev->host.port_cb->Disconnect(pdev);
-
- /* Clear interrupt */
- gintsts.b.disconnect = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
-
- return 1;
-}
-
-/**
- * @brief USB_OTG_USBH_handle_nptxfempty_ISR
- * Handles non periodic tx fifo empty.
- * @param pdev: Selected device
- * @retval status
- */
-static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_GINTMSK_TypeDef intmsk;
- USB_OTG_HNPTXSTS_TypeDef hnptxsts;
- uint16_t len_words , len;
-
- hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
-
- len_words = (pdev->host.hc[hnptxsts.b.chnum].xfer_len + 3) / 4;
-
- while ((hnptxsts.b.nptxfspcavail > len_words)&&
- (pdev->host.hc[hnptxsts.b.chnum].xfer_len != 0))
- {
-
- len = hnptxsts.b.nptxfspcavail * 4;
-
- if (len > pdev->host.hc[hnptxsts.b.chnum].xfer_len)
- {
- /* Last packet */
- len = pdev->host.hc[hnptxsts.b.chnum].xfer_len;
-
- intmsk.d32 = 0;
- intmsk.b.nptxfempty = 1;
- USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);
- }
-
- len_words = (pdev->host.hc[hnptxsts.b.chnum].xfer_len + 3) / 4;
-
- USB_OTG_WritePacket (pdev , pdev->host.hc[hnptxsts.b.chnum].xfer_buff, hnptxsts.b.chnum, len);
-
- pdev->host.hc[hnptxsts.b.chnum].xfer_buff += len;
- pdev->host.hc[hnptxsts.b.chnum].xfer_len -= len;
- pdev->host.hc[hnptxsts.b.chnum].xfer_count += len;
-
- hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
- }
-
- return 1;
-}
-
-/**
- * @brief USB_OTG_USBH_handle_ptxfempty_ISR
- * Handles periodic tx fifo empty
- * @param pdev: Selected device
- * @retval status
- */
-static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_GINTMSK_TypeDef intmsk;
- USB_OTG_HPTXSTS_TypeDef hptxsts;
- uint16_t len_words , len;
-
- hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
-
- len_words = (pdev->host.hc[hptxsts.b.chnum].xfer_len + 3) / 4;
-
- while ((hptxsts.b.ptxfspcavail > len_words)&&
- (pdev->host.hc[hptxsts.b.chnum].xfer_len != 0))
- {
-
- len = hptxsts.b.ptxfspcavail * 4;
-
- if (len > pdev->host.hc[hptxsts.b.chnum].xfer_len)
- {
- len = pdev->host.hc[hptxsts.b.chnum].xfer_len;
- /* Last packet */
- intmsk.d32 = 0;
- intmsk.b.ptxfempty = 1;
- USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);
- }
-
- len_words = (pdev->host.hc[hptxsts.b.chnum].xfer_len + 3) / 4;
-
- USB_OTG_WritePacket (pdev , pdev->host.hc[hptxsts.b.chnum].xfer_buff, hptxsts.b.chnum, len);
-
- pdev->host.hc[hptxsts.b.chnum].xfer_buff += len;
- pdev->host.hc[hptxsts.b.chnum].xfer_len -= len;
- pdev->host.hc[hptxsts.b.chnum].xfer_count += len;
-
- hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
- }
-
- return 1;
-}
-
-/**
- * @brief USB_OTG_USBH_handle_port_ISR
- * This function determines which interrupt conditions have occurred
- * @param pdev: Selected device
- * @retval status
- */
-static uint32_t USB_OTG_USBH_handle_port_ISR (USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_HPRT0_TypeDef hprt0;
- USB_OTG_HPRT0_TypeDef hprt0_dup;
- USB_OTG_HCFG_TypeDef hcfg;
- uint32_t do_reset = 0;
- uint32_t retval = 0;
-
- hcfg.d32 = 0;
- hprt0.d32 = 0;
- hprt0_dup.d32 = 0;
-
- hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
- hprt0_dup.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
-
- /* Clear the interrupt bits in GINTSTS */
-
- hprt0_dup.b.prtena = 0;
- hprt0_dup.b.prtconndet = 0;
- hprt0_dup.b.prtenchng = 0;
- hprt0_dup.b.prtovrcurrchng = 0;
-
- /* Port Connect Detected */
- if (hprt0.b.prtconndet)
- {
- pdev->host.port_cb->Connect(pdev);
- hprt0_dup.b.prtconndet = 1;
- do_reset = 1;
- retval |= 1;
- }
-
- /* Port Enable Changed */
- if (hprt0.b.prtenchng)
- {
- hprt0_dup.b.prtenchng = 1;
- if (hprt0.b.prtena == 1)
- {
- pdev->host.ConnSts = 1;
-
- if ((hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED) ||
- (hprt0.b.prtspd == HPRT0_PRTSPD_FULL_SPEED))
- {
-
- hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG);
-
- if (hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED)
- {
- USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 6000 );
- if (hcfg.b.fslspclksel != HCFG_6_MHZ)
- {
- if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID)
- {
- USB_OTG_InitFSLSPClkSel(pdev ,HCFG_6_MHZ );
- }
- do_reset = 1;
- }
- }
- else
- {
-
- USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 48000 );
- if (hcfg.b.fslspclksel != HCFG_48_MHZ)
- {
- USB_OTG_InitFSLSPClkSel(pdev ,HCFG_48_MHZ );
- do_reset = 1;
- }
- }
- }
- else
- {
- do_reset = 1;
- }
- }
- }
- /* Overcurrent Change Interrupt */
- if (hprt0.b.prtovrcurrchng)
- {
- hprt0_dup.b.prtovrcurrchng = 1;
- retval |= 1;
- }
- if (do_reset)
- {
- USB_OTG_ResetPort(pdev);
-
- }
- /* Clear Port Interrupts */
- USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0_dup.d32);
-
- return retval;
-}
-
-/**
- * @brief USB_OTG_USBH_handle_hc_n_Out_ISR
- * Handles interrupt for a specific Host Channel
- * @param pdev: Selected device
- * @param hc_num: Channel number
- * @retval status
- */
-uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t num)
-{
-
- USB_OTG_HCINTn_TypeDef hcint;
- USB_OTG_HCGINTMSK_TypeDef hcintmsk;
- USB_OTG_HC_REGS *hcreg;
- USB_OTG_HCCHAR_TypeDef hcchar;
-
- hcreg = pdev->regs.HC_REGS[num];
- hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT);
- hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCGINTMSK);
- hcint.d32 = hcint.d32 & hcintmsk.d32;
-
- hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR);
-
- if (hcint.b.ahberr)
- {
- CLEAR_HC_INT(hcreg ,ahberr);
- UNMASK_HOST_INT_CHH (num);
- }
- else if (hcint.b.ack)
- {
- CLEAR_HC_INT(hcreg , ack);
- }
-
- else if (hcint.b.xfercompl)
- {
- pdev->host.ErrCnt[num] = 0;
- UNMASK_HOST_INT_CHH (num);
- USB_OTG_HC_Halt(pdev, num);
- CLEAR_HC_INT(hcreg , xfercompl);
- pdev->host.HC_Status[num] = HC_XFRC;
- }
-
- else if (hcint.b.stall)
- {
- CLEAR_HC_INT(hcreg , stall);
- UNMASK_HOST_INT_CHH (num);
- USB_OTG_HC_Halt(pdev, num);
- pdev->host.HC_Status[num] = HC_STALL;
- }
-
- else if (hcint.b.nak)
- {
- pdev->host.ErrCnt[num] = 0;
- UNMASK_HOST_INT_CHH (num);
- USB_OTG_HC_Halt(pdev, num);
- CLEAR_HC_INT(hcreg , nak);
- pdev->host.HC_Status[num] = HC_NAK;
- }
-
- else if (hcint.b.xacterr)
- {
- UNMASK_HOST_INT_CHH (num);
- USB_OTG_HC_Halt(pdev, num);
- pdev->host.ErrCnt[num] ++;
- pdev->host.HC_Status[num] = HC_XACTERR;
- CLEAR_HC_INT(hcreg , xacterr);
- }
- else if (hcint.b.nyet)
- {
- pdev->host.ErrCnt[num] = 0;
- UNMASK_HOST_INT_CHH (num);
- USB_OTG_HC_Halt(pdev, num);
- CLEAR_HC_INT(hcreg , nyet);
- pdev->host.HC_Status[num] = HC_NYET;
- }
- else if (hcint.b.datatglerr)
- {
-
- UNMASK_HOST_INT_CHH (num);
- USB_OTG_HC_Halt(pdev, num);
- CLEAR_HC_INT(hcreg , nak);
- pdev->host.HC_Status[num] = HC_DATATGLERR;
-
- CLEAR_HC_INT(hcreg , datatglerr);
- }
- else if (hcint.b.chhltd)
- {
- MASK_HOST_INT_CHH (num);
-
- if(pdev->host.HC_Status[num] == HC_XFRC)
- {
- pdev->host.URB_State[num] = URB_DONE;
-
- if (hcchar.b.eptype == EP_TYPE_BULK)
- {
- pdev->host.hc[num].toggle_out ^= 1;
- }
- }
- else if(pdev->host.HC_Status[num] == HC_NAK)
- {
- pdev->host.URB_State[num] = URB_NOTREADY;
- }
- else if(pdev->host.HC_Status[num] == HC_NYET)
- {
- if(pdev->host.hc[num].do_ping == 1)
- {
- USB_OTG_HC_DoPing(pdev, num);
- }
- pdev->host.URB_State[num] = URB_NOTREADY;
- }
- else if(pdev->host.HC_Status[num] == HC_STALL)
- {
- pdev->host.URB_State[num] = URB_STALL;
- }
- else if(pdev->host.HC_Status[num] == HC_XACTERR)
- {
- if (pdev->host.ErrCnt[num] == 3)
- {
- pdev->host.URB_State[num] = URB_ERROR;
- pdev->host.ErrCnt[num] = 0;
- }
- }
- CLEAR_HC_INT(hcreg , chhltd);
- }
-
-
- return 1;
-}
-
-/**
- * @brief USB_OTG_USBH_handle_hc_n_In_ISR
- * Handles interrupt for a specific Host Channel
- * @param pdev: Selected device
- * @param hc_num: Channel number
- * @retval status
- */
-uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t num)
-{
- USB_OTG_HCINTn_TypeDef hcint;
- USB_OTG_HCGINTMSK_TypeDef hcintmsk;
- USB_OTG_HCCHAR_TypeDef hcchar;
- USB_OTG_HCTSIZn_TypeDef hctsiz;
- USB_OTG_HC_REGS *hcreg;
-
-
- hcreg = pdev->regs.HC_REGS[num];
- hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT);
- hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCGINTMSK);
- hcint.d32 = hcint.d32 & hcintmsk.d32;
- hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR);
- hcintmsk.d32 = 0;
-
-
- if (hcint.b.ahberr)
- {
- CLEAR_HC_INT(hcreg ,ahberr);
- UNMASK_HOST_INT_CHH (num);
- }
- else if (hcint.b.ack)
- {
- CLEAR_HC_INT(hcreg ,ack);
- }
-
- else if (hcint.b.stall)
- {
- UNMASK_HOST_INT_CHH (num);
- pdev->host.HC_Status[num] = HC_STALL;
- CLEAR_HC_INT(hcreg , nak); /* Clear the NAK Condition */
- CLEAR_HC_INT(hcreg , stall); /* Clear the STALL Condition */
- hcint.b.nak = 0; /* NOTE: When there is a 'stall', reset also nak,
- else, the pdev->host.HC_Status = HC_STALL
- will be overwritten by 'nak' in code below */
- USB_OTG_HC_Halt(pdev, num);
- }
- else if (hcint.b.datatglerr)
- {
-
- UNMASK_HOST_INT_CHH (num);
- USB_OTG_HC_Halt(pdev, num);
- CLEAR_HC_INT(hcreg , nak);
- pdev->host.HC_Status[num] = HC_DATATGLERR;
- CLEAR_HC_INT(hcreg , datatglerr);
- }
-
- if (hcint.b.frmovrun)
- {
- UNMASK_HOST_INT_CHH (num);
- USB_OTG_HC_Halt(pdev, num);
- CLEAR_HC_INT(hcreg ,frmovrun);
- }
-
- else if (hcint.b.xfercompl)
- {
-
- if (pdev->cfg.dma_enable == 1)
- {
- hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCTSIZ);
- pdev->host.XferCnt[num] = pdev->host.hc[num].xfer_len - hctsiz.b.xfersize;
- }
-
- pdev->host.HC_Status[num] = HC_XFRC;
- pdev->host.ErrCnt [num]= 0;
- CLEAR_HC_INT(hcreg , xfercompl);
-
- if ((hcchar.b.eptype == EP_TYPE_CTRL)||
- (hcchar.b.eptype == EP_TYPE_BULK))
- {
- UNMASK_HOST_INT_CHH (num);
- USB_OTG_HC_Halt(pdev, num);
- CLEAR_HC_INT(hcreg , nak);
- pdev->host.hc[num].toggle_in ^= 1;
-
- }
- else if(hcchar.b.eptype == EP_TYPE_INTR)
- {
- hcchar.b.oddfrm = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32);
- pdev->host.URB_State[num] = URB_DONE;
- }
-
- }
- else if (hcint.b.chhltd)
- {
- MASK_HOST_INT_CHH (num);
-
- if(pdev->host.HC_Status[num] == HC_XFRC)
- {
- pdev->host.URB_State[num] = URB_DONE;
- }
-
- else if (pdev->host.HC_Status[num] == HC_STALL)
- {
- pdev->host.URB_State[num] = URB_STALL;
- }
-
- else if((pdev->host.HC_Status[num] == HC_XACTERR) ||
- (pdev->host.HC_Status[num] == HC_DATATGLERR))
- {
- pdev->host.ErrCnt[num] = 0;
- pdev->host.URB_State[num] = URB_ERROR;
-
- }
- else if(hcchar.b.eptype == EP_TYPE_INTR)
- {
- pdev->host.hc[num].toggle_in ^= 1;
- }
-
- CLEAR_HC_INT(hcreg , chhltd);
-
- }
- else if (hcint.b.xacterr)
- {
- UNMASK_HOST_INT_CHH (num);
- pdev->host.ErrCnt[num] ++;
- pdev->host.HC_Status[num] = HC_XACTERR;
- USB_OTG_HC_Halt(pdev, num);
- CLEAR_HC_INT(hcreg , xacterr);
-
- }
- else if (hcint.b.nak)
- {
- if(hcchar.b.eptype == EP_TYPE_INTR)
- {
- UNMASK_HOST_INT_CHH (num);
- USB_OTG_HC_Halt(pdev, num);
- CLEAR_HC_INT(hcreg , nak);
- }
- else if ((hcchar.b.eptype == EP_TYPE_CTRL)||
- (hcchar.b.eptype == EP_TYPE_BULK))
- {
- /* re-activate the channel */
- hcchar.b.chen = 1;
- hcchar.b.chdis = 0;
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32);
- }
- pdev->host.HC_Status[num] = HC_NAK;
- }
-
-
- return 1;
-
-}
-
-/**
- * @brief USB_OTG_USBH_handle_rx_qlvl_ISR
- * Handles the Rx Status Queue Level Interrupt
- * @param pdev: Selected device
- * @retval status
- */
-
-static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_GRXFSTS_TypeDef grxsts;
- USB_OTG_GINTMSK_TypeDef intmsk;
- USB_OTG_HCTSIZn_TypeDef hctsiz;
- USB_OTG_HCCHAR_TypeDef hcchar;
- __IO uint8_t channelnum =0;
- uint32_t count;
-
- /* Disable the Rx Status Queue Level interrupt */
- intmsk.d32 = 0;
- intmsk.b.rxstsqlvl = 1;
- USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);
-
- grxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRXSTSP);
- channelnum = grxsts.b.chnum;
- hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR);
-
- switch (grxsts.b.pktsts)
- {
- case GRXSTS_PKTSTS_IN:
- /* Read the data into the host buffer. */
- if ((grxsts.b.bcnt > 0) && (pdev->host.hc[channelnum].xfer_buff != (void *)0))
- {
-
- USB_OTG_ReadPacket(pdev, pdev->host.hc[channelnum].xfer_buff, grxsts.b.bcnt);
- /*manage multiple Xfer */
- pdev->host.hc[grxsts.b.chnum].xfer_buff += grxsts.b.bcnt;
- pdev->host.hc[grxsts.b.chnum].xfer_count += grxsts.b.bcnt;
-
-
- count = pdev->host.hc[channelnum].xfer_count;
- pdev->host.XferCnt[channelnum] = count;
-
- hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCTSIZ);
- if(hctsiz.b.pktcnt > 0)
- {
- /* re-activate the channel when more packets are expected */
- hcchar.b.chen = 1;
- hcchar.b.chdis = 0;
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR, hcchar.d32);
- }
- }
- break;
-
- case GRXSTS_PKTSTS_IN_XFER_COMP:
-
- case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
- case GRXSTS_PKTSTS_CH_HALTED:
- default:
- break;
- }
-
- /* Enable the Rx Status Queue Level interrupt */
- intmsk.b.rxstsqlvl = 1;
- USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, intmsk.d32);
- return 1;
-}
-
-/**
- * @brief USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR
- * Handles the incomplete Periodic transfer Interrupt
- * @param pdev: Selected device
- * @retval status
- */
-static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev)
-{
-
- USB_OTG_GINTSTS_TypeDef gintsts;
- USB_OTG_HCCHAR_TypeDef hcchar;
-
-
-
-
- hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[0]->HCCHAR);
- hcchar.b.chen = 1;
- hcchar.b.chdis = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[0]->HCCHAR, hcchar.d32);
-
- gintsts.d32 = 0;
- /* Clear interrupt */
- gintsts.b.incomplisoout = 1;
- USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
-
- return 1;
-}
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+++ /dev/null
-/**
- ******************************************************************************
- * @file usb_otg.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 22-July-2011
- * @brief OTG Core Layer
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_defines.h"
-#include "usb_regs.h"
-#include "usb_core.h"
-#include "usb_otg.h"
-
-/** @addtogroup USB_OTG_DRIVER
- * @{
- */
-
-/** @defgroup USB_OTG
- * @brief This file is the interface between EFSL ans Host mass-storage class
- * @{
- */
-
-
-/** @defgroup USB_OTG_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_OTG_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-
-/** @defgroup USB_OTG_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_OTG_Private_Variables
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_OTG_Private_FunctionPrototypes
- * @{
- */
-
-static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev);
-
-/**
- * @}
- */
-
-
-/** @defgroup USB_OTG_Private_Functions
- * @{
- */
-
-
-/* OTG Interrupt Handler */
-
-
-/**
- * @brief STM32_USBO_OTG_ISR_Handler
- *
- * @param None
- * @retval : None
- */
-uint32_t STM32_USBO_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev)
-{
- uint32_t retval = 0;
- USB_OTG_GINTSTS_TypeDef gintsts ;
- gintsts.d32 = 0;
-
- gintsts.d32 = USB_OTG_Read_itr(pdev);
- if (gintsts.d32 == 0)
- {
- return 0;
- }
- if (gintsts.b.otgintr)
- {
- retval |= 1;//USB_OTG_HandleOTG_ISR(pdev);
- }
- if (gintsts.b.conidstschng)
- {
- retval |= 2;//USB_OTG_HandleConnectorIDStatusChange_ISR(pdev);
- }
- if (gintsts.b.sessreqintr)
- {
- retval |= 3;//USB_OTG_HandleSessionRequest_ISR(pdev);
- }
- return retval;
-}
-
-
-/**
- * @brief USB_OTG_Read_itr
- * returns the Core Interrupt register
- * @param None
- * @retval : status
- */
-static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev)
-{
- USB_OTG_GINTSTS_TypeDef gintsts;
- USB_OTG_GINTMSK_TypeDef gintmsk;
- USB_OTG_GINTMSK_TypeDef gintmsk_common;
-
-
- gintsts.d32 = 0;
- gintmsk.d32 = 0;
- gintmsk_common.d32 = 0;
-
- /* OTG interrupts */
- gintmsk_common.b.sessreqintr = 1;
- gintmsk_common.b.conidstschng = 1;
- gintmsk_common.b.otgintr = 1;
-
- gintsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS);
- gintmsk.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK);
- return ((gintsts.d32 & gintmsk.d32 ) & gintmsk_common.d32);
-}
-
-
-/**
- * @brief USB_OTG_GetCurrentState
- * Return current OTG State
- * @param None
- * @retval : None
- */
-uint32_t USB_OTG_GetCurrentState (USB_OTG_CORE_HANDLE *pdev)
-{
- return pdev->otg.OTG_State;
-}
-
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
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- <meta content="MCD Application Team" name="author"></head>
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- <tbody>
- <tr>
- <td style="vertical-align: top;">
- <p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
- </td>
- </tr>
- <tr style="">
- <td style="padding: 1.5pt;">
- <h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
-Notes for STM32F4-Discovery Board Drivers</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
- <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
-2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
- <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
- </td>
- </tr>
- </tbody>
- </table>
- <p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p>
- <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
- <tbody>
- <tr style="">
- <td style="padding: 0cm;" valign="top">
- <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
- <ol style="margin-top: 0cm;" start="1" type="1">
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F4-Discovery Board Drivers update History</a><o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
- </ol>
- <span style="font-family: "Times New Roman";">
- </span>
- <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F4-Discovery Board Drivers update History</span></h2><div style="margin-left: 40px;"><span style="font-size: 10pt; font-family: Verdana;">For more information on the STM32F4-Discovery board visit <a href="http://www.st.com/stm32f4-discovery" target="_blank">www.st.com/stm32f4-discovery</a>.</span></div><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 186px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 19-September-2011</span></h3>
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
- <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">First official version of the<span style="font-weight: bold; font-style: italic;"> STM32F4-Discovery Board Drivers</span></span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"></span></span><br><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
- <p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The
-enclosed firmware and all the related documentation are not covered by
-a License Agreement, if you need such License you can contact your
-local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>
-
- <b><span style="font-size: 10pt; font-family: Verdana; color: black;">THE
-PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
-SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
-ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
-CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
-CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
-THEIR PRODUCTS.</span></b>
-
- <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
- <hr align="center" size="2" width="100%"></span></div>
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
-complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STMicroelectronics<span style="color: black;"> Microcontrollers visit </span><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;">www.st.com</span></u></a></span><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"><a href="http://www.st.com/stm32l" target="_blank"></a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
- </td>
- </tr>
- </tbody>
- </table>
- <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
- </td>
- </tr>
- </tbody>
-</table>
-</div>
-<p class="MsoNormal"><o:p> </o:p></p>
-</div>
-
-</body></html>
\ No newline at end of file
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4_discovery.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief This file provides set of firmware functions to manage Leds and
- * push-button available on STM32F4-Discovery Kit from STMicroelectronics.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4_discovery.h"
-
-//ADDED BY ME!!!!!!!!!!!!!!!!!!!!
-#include "stm32f4xx_conf.h"
-
-
-/** @addtogroup Utilities
- * @{
- */
-
-/** @addtogroup STM32F4_DISCOVERY
- * @{
- */
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL
- * @brief This file provides set of firmware functions to manage Leds and push-button
- * available on STM32F4-Discovery Kit from STMicroelectronics.
- * @{
- */
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_Variables
- * @{
- */
-GPIO_TypeDef* GPIO_PORT[LEDn] = {LED4_GPIO_PORT, LED3_GPIO_PORT, LED5_GPIO_PORT,
- LED6_GPIO_PORT};
-const uint16_t GPIO_PIN[LEDn] = {LED4_PIN, LED3_PIN, LED5_PIN,
- LED6_PIN};
-const uint32_t GPIO_CLK[LEDn] = {LED4_GPIO_CLK, LED3_GPIO_CLK, LED5_GPIO_CLK,
- LED6_GPIO_CLK};
-
-GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {USER_BUTTON_GPIO_PORT };
-
-const uint16_t BUTTON_PIN[BUTTONn] = {USER_BUTTON_PIN };
-
-const uint32_t BUTTON_CLK[BUTTONn] = {USER_BUTTON_GPIO_CLK };
-
-const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {USER_BUTTON_EXTI_LINE };
-
-const uint8_t BUTTON_PORT_SOURCE[BUTTONn] = {USER_BUTTON_EXTI_PORT_SOURCE};
-
-const uint8_t BUTTON_PIN_SOURCE[BUTTONn] = {USER_BUTTON_EXTI_PIN_SOURCE };
-const uint8_t BUTTON_IRQn[BUTTONn] = {USER_BUTTON_EXTI_IRQn };
-
-NVIC_InitTypeDef NVIC_InitStructure;
-
-/**
- * @}
- */
-
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_Functions
- * @{
- */
-
-/**
- * @brief Configures LED GPIO.
- * @param Led: Specifies the Led to be configured.
- * This parameter can be one of following parameters:
- * @arg LED4
- * @arg LED3
- * @arg LED5
- * @arg LED6
- * @retval None
- */
-void STM_EVAL_LEDInit(Led_TypeDef Led)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
-
- /* Enable the GPIO_LED Clock */
- RCC_AHB1PeriphClockCmd(GPIO_CLK[Led], ENABLE);
-
- /* Configure the GPIO_LED pin */
- GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
-}
-
-/**
- * @brief Turns selected LED On.
- * @param Led: Specifies the Led to be set on.
- * This parameter can be one of following parameters:
- * @arg LED4
- * @arg LED3
- * @arg LED5
- * @arg LED6
- * @retval None
- */
-void STM_EVAL_LEDOn(Led_TypeDef Led)
-{
- GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led];
-}
-
-/**
- * @brief Turns selected LED Off.
- * @param Led: Specifies the Led to be set off.
- * This parameter can be one of following parameters:
- * @arg LED4
- * @arg LED3
- * @arg LED5
- * @arg LED6
- * @retval None
- */
-void STM_EVAL_LEDOff(Led_TypeDef Led)
-{
- GPIO_PORT[Led]->BSRRH = GPIO_PIN[Led];
-}
-
-/**
- * @brief Toggles the selected LED.
- * @param Led: Specifies the Led to be toggled.
- * This parameter can be one of following parameters:
- * @arg LED4
- * @arg LED3
- * @arg LED5
- * @arg LED6
- * @retval None
- */
-void STM_EVAL_LEDToggle(Led_TypeDef Led)
-{
- GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
-}
-
-/**
- * @brief Configures Button GPIO and EXTI Line.
- * @param Button: Specifies the Button to be configured.
- * This parameter should be: BUTTON_USER
- * @param Button_Mode: Specifies Button mode.
- * This parameter can be one of following parameters:
- * @arg BUTTON_MODE_GPIO: Button will be used as simple IO
- * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
- * generation capability
- * @retval None
- */
-void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
- EXTI_InitTypeDef EXTI_InitStructure;
- NVIC_InitTypeDef NVIC_InitStructure;
-
- /* Enable the BUTTON Clock */
- RCC_AHB1PeriphClockCmd(BUTTON_CLK[Button], ENABLE);
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-
- /* Configure Button pin as input */
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
- GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
-
- if (Button_Mode == BUTTON_MODE_EXTI)
- {
- /* Connect Button EXTI Line to Button GPIO Pin */
- SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
-
- /* Configure Button EXTI line */
- EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
- EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
- EXTI_InitStructure.EXTI_LineCmd = ENABLE;
- EXTI_Init(&EXTI_InitStructure);
-
- /* Enable and set Button EXTI Interrupt to the lowest priority */
- NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-
- NVIC_Init(&NVIC_InitStructure);
- }
-}
-
-/**
- * @brief Returns the selected Button state.
- * @param Button: Specifies the Button to be checked.
- * This parameter should be: BUTTON_USER
- * @retval The Button GPIO pin value.
- */
-uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
-{
- return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4_discovery.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief This file contains definitions for STM32F4-Discovery Kit's Leds and
- * push-button hardware resources.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4_DISCOVERY_H
-#define __STM32F4_DISCOVERY_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
- #include "stm32f4xx.h"
-
-/** @addtogroup Utilities
- * @{
- */
-
-/** @addtogroup STM32F4_DISCOVERY
- * @{
- */
-
-/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL
- * @{
- */
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Types
- * @{
- */
-typedef enum
-{
- LED4 = 0,
- LED3 = 1,
- LED5 = 2,
- LED6 = 3
-} Led_TypeDef;
-
-typedef enum
-{
- BUTTON_USER = 0,
-} Button_TypeDef;
-
-typedef enum
-{
- BUTTON_MODE_GPIO = 0,
- BUTTON_MODE_EXTI = 1
-} ButtonMode_TypeDef;
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Constants
- * @{
- */
-
-/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL_LED
- * @{
- */
-#define LEDn 4
-
-#define LED4_PIN GPIO_Pin_12
-#define LED4_GPIO_PORT GPIOD
-#define LED4_GPIO_CLK RCC_AHB1Periph_GPIOD
-
-#define LED3_PIN GPIO_Pin_13
-#define LED3_GPIO_PORT GPIOD
-#define LED3_GPIO_CLK RCC_AHB1Periph_GPIOD
-
-#define LED5_PIN GPIO_Pin_14
-#define LED5_GPIO_PORT GPIOD
-#define LED5_GPIO_CLK RCC_AHB1Periph_GPIOD
-
-#define LED6_PIN GPIO_Pin_15
-#define LED6_GPIO_PORT GPIOD
-#define LED6_GPIO_CLK RCC_AHB1Periph_GPIOD
-/**
- * @}
- */
-
-/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL_BUTTON
- * @{
- */
-#define BUTTONn 1
-
-/**
- * @brief Wakeup push-button
- */
-#define USER_BUTTON_PIN GPIO_Pin_0
-#define USER_BUTTON_GPIO_PORT GPIOA
-#define USER_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOA
-#define USER_BUTTON_EXTI_LINE EXTI_Line0
-#define USER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA
-#define USER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0
-#define USER_BUTTON_EXTI_IRQn EXTI0_IRQn
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Functions
- * @{
- */
-void STM_EVAL_LEDInit(Led_TypeDef Led);
-void STM_EVAL_LEDOn(Led_TypeDef Led);
-void STM_EVAL_LEDOff(Led_TypeDef Led);
-void STM_EVAL_LEDToggle(Led_TypeDef Led);
-void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
-uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4_DISCOVERY_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4_discovery_audio_codec.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief This file includes the low layer driver for CS43L22 Audio Codec
- * available on STM32F4-Discovery Kit.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/*==============================================================================================================================
- User NOTES
-1. How To use this driver:
---------------------------
- - This driver supports STM32F4xx devices on STM32F4-Discovery Kit.
-
- - Configure the options in file stm32f4_discovery_audio_codec.h in the section CONFIGURATION.
- Refer to the sections 2 and 3 to have more details on the possible configurations.
-
- - Call the function EVAL_AUDIO_Init(
- OutputDevice: physical output mode (OUTPUT_DEVICE_SPEAKER,
- OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_AUTO or
- OUTPUT_DEVICE_BOTH)
- Volume: initial volume to be set (0 is min (mute), 100 is max (100%)
- AudioFreq: Audio frequency in Hz (8000, 16000, 22500, 32000 ...)
- this parameter is relative to the audio file/stream type.
- )
- This function configures all the hardware required for the audio application (codec, I2C, I2S,
- GPIOs, DMA and interrupt if needed). This function returns 0 if configuration is OK.
- if the returned value is different from 0 or the function is stuck then the communication with
- the codec (try to un-plug the power or reset device in this case).
- + OUTPUT_DEVICE_SPEAKER: only speaker will be set as output for the audio stream.
- + OUTPUT_DEVICE_HEADPHONE: only headphones will be set as output for the audio stream.
- + OUTPUT_DEVICE_AUTO: Selection of output device is made through external switch (implemented
- into the audio jack on the evaluation board). When the Headphone is connected it is used
- as output. When the headphone is disconnected from the audio jack, the output is
- automatically switched to Speaker.
- + OUTPUT_DEVICE_BOTH: both Speaker and Headphone are used as outputs for the audio stream
- at the same time.
-
- - Call the function EVAL_AUDIO_Play(
- pBuffer: pointer to the audio data file address
- Size: size of the buffer to be sent in Bytes
- )
- to start playing (for the first time) from the audio file/stream.
-
- - Call the function EVAL_AUDIO_PauseResume(
- Cmd: AUDIO_PAUSE (or 0) to pause playing or AUDIO_RESUME (or
- any value different from 0) to resume playing.
- )
- Note. After calling EVAL_AUDIO_PauseResume() function for pause, only EVAL_AUDIO_PauseResume() should be called
- for resume (it is not allowed to call EVAL_AUDIO_Play() in this case).
- Note. This function should be called only when the audio file is played or paused (not stopped).
-
- - For each mode, you may need to implement the relative callback functions into your code.
- The Callback functions are named EVAL_AUDIO_XXX_CallBack() and only their prototypes are declared in
- the stm32f4_discovery_audio_codec.h file. (refer to the example for more details on the callbacks implementations)
-
- - To Stop playing, to modify the volume level or to mute, use the functions
- EVAL_AUDIO_Stop(), EVAL_AUDIO_VolumeCtl() and EVAL_AUDIO_Mute().
-
- - The driver API and the callback functions are at the end of the stm32f4_discovery_audio_codec.h file.
-
-
- Driver architecture:
- --------------------
- This driver is composed of three main layers:
- o High Audio Layer: consists of the function API exported in the stm32f4_discovery_audio_codec.h file
- (EVAL_AUDIO_Init(), EVAL_AUDIO_Play() ...)
- o Codec Control layer: consists of the functions API controlling the audio codec (CS43L22) and
- included as local functions in file stm32f4_discovery_audio_codec.c (Codec_Init(), Codec_Play() ...)
- o Media Access Layer (MAL): which consists of functions allowing to access the media containing/
- providing the audio file/stream. These functions are also included as local functions into
- the stm32f4_discovery_audio_codec.c file (Audio_MAL_Init(), Audio_MAL_Play() ...)
- Each set of functions (layer) may be implemented independently of the others and customized when
- needed.
-
-2. Modes description:
----------------------
- + AUDIO_MAL_MODE_NORMAL : is suitable when the audio file is in a memory location.
- + AUDIO_MAL_MODE_CIRCULAR: is suitable when the audio data are read either from a
- memory location or from a device at real time (double buffer could be used).
-
-3. DMA interrupts description:
-------------------------------
- + EVAL_AUDIO_IT_TC_ENABLE: Enable this define to use the DMA end of transfer interrupt.
- then, a callback should be implemented by user to perform specific actions
- when the DMA has finished the transfer.
- + EVAL_AUDIO_IT_HT_ENABLE: Enable this define to use the DMA end of half transfer interrupt.
- then, a callback should be implemented by user to perform specific actions
- when the DMA has reached the half of the buffer transfer (generally, it is useful
- to load the first half of buffer while DMA is loading from the second half).
- + EVAL_AUDIO_IT_ER_ENABLE: Enable this define to manage the cases of error on DMA transfer.
-
-4. Known Limitations:
----------------------
- 1- When using the Speaker, if the audio file quality is not high enough, the speaker output
- may produce high and uncomfortable noise level. To avoid this issue, to use speaker
- output properly, try to increase audio file sampling rate (typically higher than 48KHz).
- This operation will lead to larger file size.
- 2- Communication with the audio codec (through I2C) may be corrupted if it is interrupted by some
- user interrupt routines (in this case, interrupts could be disabled just before the start of
- communication then re-enabled when it is over). Note that this communication is only done at
- the configuration phase (EVAL_AUDIO_Init() or EVAL_AUDIO_Stop()) and when Volume control modification is
- performed (EVAL_AUDIO_VolumeCtl() or EVAL_AUDIO_Mute()). When the audio data is played, no communication is
- required with the audio codec.
- 3- Parsing of audio file is not implemented (in order to determine audio file properties: Mono/Stereo, Data size,
- File size, Audio Frequency, Audio Data header size ...). The configuration is fixed for the given audio file.
- 4- Mono audio streaming is not supported (in order to play mono audio streams, each data should be sent twice
- on the I2S or should be duplicated on the source buffer. Or convert the stream in stereo before playing).
- 5- Supports only 16-bit audio data size.
-===============================================================================================================================*/
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4_discovery_audio_codec.h"
-//ADDED BY ME!!!!!!!!!!!!!!!!!!!!
-#include "stm32f4xx_conf.h"
-
-/** @addtogroup Utilities
- * @{
- */
-
-/** @addtogroup STM32F4_DISCOVERY
- * @{
- */
-
-/** @addtogroup STM32F4_DISCOVERY_AUDIO_CODEC
- * @brief This file includes the low layer driver for CS43L22 Audio Codec
- * available on STM32F4-Discovery Kit.
- * @{
- */
-
-/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Private_Types
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Private_Defines
- * @{
- */
-
-/* Mask for the bit EN of the I2S CFGR register */
-#define I2S_ENABLE_MASK 0x0400
-
-/* Delay for the Codec to be correctly reset */
-#define CODEC_RESET_DELAY 0x4FFF
-
-/* Codec audio Standards */
-#ifdef I2S_STANDARD_PHILLIPS
- #define CODEC_STANDARD 0x04
- #define I2S_STANDARD I2S_Standard_Phillips
-#elif defined(I2S_STANDARD_MSB)
- #define CODEC_STANDARD 0x00
- #define I2S_STANDARD I2S_Standard_MSB
-#elif defined(I2S_STANDARD_LSB)
- #define CODEC_STANDARD 0x08
- #define I2S_STANDARD I2S_Standard_LSB
-#else
- #error "Error: No audio communication standard selected !"
-#endif /* I2S_STANDARD */
-
-/* The 7 bits Codec address (sent through I2C interface) */
-#define CODEC_ADDRESS 0x94 /* b00100111 */
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Private_Variables
- * @{
- */
-/* This structure is declared global because it is handled by two different functions */
-static DMA_InitTypeDef DMA_InitStructure;
-DMA_InitTypeDef AUDIO_MAL_DMA_InitStructure;
-
-uint32_t AudioTotalSize = 0xFFFF; /* This variable holds the total size of the audio file */
-uint32_t AudioRemSize = 0xFFFF; /* This variable holds the remaining data in audio file */
-uint16_t *CurrentPos; /* This variable holds the current position of audio pointer */
-
-__IO uint32_t CODECTimeout = CODEC_LONG_TIMEOUT;
-__IO uint8_t OutputDev = 0;
-
-
-__IO uint32_t CurrAudioInterface = AUDIO_INTERFACE_I2S; //AUDIO_INTERFACE_DAC
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Private_Function_Prototypes
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Private_Functions
- * @{
- */
-static void Audio_MAL_IRQHandler(void);
-/*-----------------------------------
- Audio Codec functions
- ------------------------------------------*/
-/* High Layer codec functions */
-static uint32_t Codec_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq);
-static uint32_t Codec_DeInit(void);
-static uint32_t Codec_Play(void);
-static uint32_t Codec_PauseResume(uint32_t Cmd);
-static uint32_t Codec_Stop(uint32_t Cmd);
-static uint32_t Codec_VolumeCtrl(uint8_t Volume);
-static uint32_t Codec_Mute(uint32_t Cmd);
-/* Low layer codec functions */
-static void Codec_CtrlInterface_Init(void);
-static void Codec_CtrlInterface_DeInit(void);
-static void Codec_AudioInterface_Init(uint32_t AudioFreq);
-static void Codec_AudioInterface_DeInit(void);
-static void Codec_Reset(void);
-static uint32_t Codec_WriteRegister(uint8_t RegisterAddr, uint8_t RegisterValue);
-static uint32_t Codec_ReadRegister(uint8_t RegisterAddr);
-static void Codec_GPIO_Init(void);
-static void Codec_GPIO_DeInit(void);
-static void Delay(__IO uint32_t nCount);
-/*----------------------------------------------------------------------------*/
-
-/*-----------------------------------
- MAL (Media Access Layer) functions
- ------------------------------------------*/
-/* Peripherals configuration functions */
-static void Audio_MAL_Init(void);
-static void Audio_MAL_DeInit(void);
-static void Audio_MAL_Play(uint32_t Addr, uint32_t Size);
-static void Audio_MAL_PauseResume(uint32_t Cmd, uint32_t Addr);
-static void Audio_MAL_Stop(void);
-/*----------------------------------------------------------------------------*/
-
- /* DMA Stream definitions */
- uint32_t AUDIO_MAL_DMA_CLOCK = AUDIO_I2S_DMA_CLOCK;
- DMA_Stream_TypeDef * AUDIO_MAL_DMA_STREAM = AUDIO_I2S_DMA_STREAM ;
- uint32_t AUDIO_MAL_DMA_DREG = AUDIO_I2S_DMA_DREG;
- uint32_t AUDIO_MAL_DMA_CHANNEL = AUDIO_I2S_DMA_CHANNEL;
- uint32_t AUDIO_MAL_DMA_IRQ = AUDIO_I2S_DMA_IRQ ;
- uint32_t AUDIO_MAL_DMA_FLAG_TC = AUDIO_I2S_DMA_FLAG_TC;
- uint32_t AUDIO_MAL_DMA_FLAG_HT = AUDIO_I2S_DMA_FLAG_HT;
- uint32_t AUDIO_MAL_DMA_FLAG_FE = AUDIO_I2S_DMA_FLAG_FE;
- uint32_t AUDIO_MAL_DMA_FLAG_TE = AUDIO_I2S_DMA_FLAG_TE;
- uint32_t AUDIO_MAL_DMA_FLAG_DME = AUDIO_I2S_DMA_FLAG_DME;
-
-/**
- * @brief Set the current audio interface (I2S or DAC).
- * @param Interface: AUDIO_INTERFACE_I2S or AUDIO_INTERFACE_DAC
- * @retval None
- */
-void EVAL_AUDIO_SetAudioInterface(uint32_t Interface)
-{
- CurrAudioInterface = Interface;
-
- if (CurrAudioInterface == AUDIO_INTERFACE_I2S)
- {
- /* DMA Stream definitions */
- AUDIO_MAL_DMA_CLOCK = AUDIO_I2S_DMA_CLOCK;
- AUDIO_MAL_DMA_STREAM = AUDIO_I2S_DMA_STREAM;
- AUDIO_MAL_DMA_DREG = AUDIO_I2S_DMA_DREG;
- AUDIO_MAL_DMA_CHANNEL = AUDIO_I2S_DMA_CHANNEL;
- AUDIO_MAL_DMA_IRQ = AUDIO_I2S_DMA_IRQ ;
- AUDIO_MAL_DMA_FLAG_TC = AUDIO_I2S_DMA_FLAG_TC;
- AUDIO_MAL_DMA_FLAG_HT = AUDIO_I2S_DMA_FLAG_HT;
- AUDIO_MAL_DMA_FLAG_FE = AUDIO_I2S_DMA_FLAG_FE;
- AUDIO_MAL_DMA_FLAG_TE = AUDIO_I2S_DMA_FLAG_TE;
- AUDIO_MAL_DMA_FLAG_DME = AUDIO_I2S_DMA_FLAG_DME;
- }
- else if (Interface == AUDIO_INTERFACE_DAC)
- {
- /* DMA Stream definitions */
- AUDIO_MAL_DMA_CLOCK = AUDIO_DAC_DMA_CLOCK;
- AUDIO_MAL_DMA_STREAM = AUDIO_DAC_DMA_STREAM;
- AUDIO_MAL_DMA_DREG = AUDIO_DAC_DMA_DREG;
- AUDIO_MAL_DMA_CHANNEL = AUDIO_DAC_DMA_CHANNEL;
- AUDIO_MAL_DMA_IRQ = AUDIO_DAC_DMA_IRQ ;
- AUDIO_MAL_DMA_FLAG_TC = AUDIO_DAC_DMA_FLAG_TC;
- AUDIO_MAL_DMA_FLAG_HT = AUDIO_DAC_DMA_FLAG_HT;
- AUDIO_MAL_DMA_FLAG_FE = AUDIO_DAC_DMA_FLAG_FE;
- AUDIO_MAL_DMA_FLAG_TE = AUDIO_DAC_DMA_FLAG_TE;
- AUDIO_MAL_DMA_FLAG_DME = AUDIO_DAC_DMA_FLAG_DME;
- }
-}
-
-/**
- * @brief Configure the audio peripherals.
- * @param OutputDevice: OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,
- * OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO .
- * @param Volume: Initial volume level (from 0 (Mute) to 100 (Max))
- * @param AudioFreq: Audio frequency used to play the audio stream.
- * @retval 0 if correct communication, else wrong communication
- */
-uint32_t EVAL_AUDIO_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq)
-{
- /* Perform low layer Codec initialization */
- if (Codec_Init(OutputDevice, VOLUME_CONVERT(Volume), AudioFreq) != 0)
- {
- return 1;
- }
- else
- {
- /* I2S data transfer preparation:
- Prepare the Media to be used for the audio transfer from memory to I2S peripheral */
- Audio_MAL_Init();
-
- /* Return 0 when all operations are OK */
- return 0;
- }
-}
-
-/**
- * @brief Deinitializes all the resources used by the codec (those initialized
- * by EVAL_AUDIO_Init() function).
- * @param None
- * @retval 0 if correct communication, else wrong communication
- */
-uint32_t EVAL_AUDIO_DeInit(void)
-{
- /* DeInitialize the Media layer */
- Audio_MAL_DeInit();
-
- /* DeInitialize Codec */
- Codec_DeInit();
-
- return 0;
-}
-
-/**
- * @brief Starts playing audio stream from a data buffer for a determined size.
- * @param pBuffer: Pointer to the buffer
- * @param Size: Number of audio data BYTES.
- * @retval 0 if correct communication, else wrong communication
- */
-uint32_t EVAL_AUDIO_Play(uint16_t* pBuffer, uint32_t Size)
-{
- /* Set the total number of data to be played (count in half-word) */
- AudioTotalSize = Size/2;
-
- /* Call the audio Codec Play function */
- Codec_Play();
-
- /* Update the Media layer and enable it for play */
- Audio_MAL_Play((uint32_t)pBuffer, (uint32_t)(DMA_MAX(AudioTotalSize / 2)));
-
- /* Update the remaining number of data to be played */
- AudioRemSize = (Size/2) - DMA_MAX(AudioTotalSize);
-
- /* Update the current audio pointer position */
- CurrentPos = pBuffer + DMA_MAX(AudioTotalSize);
-
- return 0;
-}
-
-/**
- * @brief This function Pauses or Resumes the audio file stream. In case
- * of using DMA, the DMA Pause feature is used. In all cases the I2S
- * peripheral is disabled.
- *
- * @WARNING When calling EVAL_AUDIO_PauseResume() function for pause, only
- * this function should be called for resume (use of EVAL_AUDIO_Play()
- * function for resume could lead to unexpected behavior).
- *
- * @param Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different
- * from 0) to resume.
- * @retval 0 if correct communication, else wrong communication
- */
-uint32_t EVAL_AUDIO_PauseResume(uint32_t Cmd)
-{
- /* Call the Audio Codec Pause/Resume function */
- if (Codec_PauseResume(Cmd) != 0)
- {
- return 1;
- }
- else
- {
- /* Call the Media layer pause/resume function */
- Audio_MAL_PauseResume(Cmd, 0);
-
- /* Return 0 if all operations are OK */
- return 0;
- }
-}
-
-/**
- * @brief Stops audio playing and Power down the Audio Codec.
- * @param Option: could be one of the following parameters
- * - CODEC_PDWN_SW: for software power off (by writing registers).
- * Then no need to reconfigure the Codec after power on.
- * - CODEC_PDWN_HW: completely shut down the codec (physically).
- * Then need to reconfigure the Codec after power on.
- * @retval 0 if correct communication, else wrong communication
- */
-uint32_t EVAL_AUDIO_Stop(uint32_t Option)
-{
- /* Call Audio Codec Stop function */
- if (Codec_Stop(Option) != 0)
- {
- return 1;
- }
- else
- {
- /* Call Media layer Stop function */
- Audio_MAL_Stop();
-
- /* Update the remaining data number */
- AudioRemSize = AudioTotalSize;
-
- /* Return 0 when all operations are correctly done */
- return 0;
- }
-}
-
-/**
- * @brief Controls the current audio volume level.
- * @param Volume: Volume level to be set in percentage from 0% to 100% (0 for
- * Mute and 100 for Max volume level).
- * @retval 0 if correct communication, else wrong communication
- */
-uint32_t EVAL_AUDIO_VolumeCtl(uint8_t Volume)
-{
- /* Call the codec volume control function with converted volume value */
- return (Codec_VolumeCtrl(VOLUME_CONVERT(Volume)));
-}
-
-/**
- * @brief Enables or disables the MUTE mode by software
- * @param Command: could be AUDIO_MUTE_ON to mute sound or AUDIO_MUTE_OFF to
- * unmute the codec and restore previous volume level.
- * @retval 0 if correct communication, else wrong communication
- */
-uint32_t EVAL_AUDIO_Mute(uint32_t Cmd)
-{
- /* Call the Codec Mute function */
- return (Codec_Mute(Cmd));
-}
-
-/**
- * @brief This function handles main Media layer interrupt.
- * @param None
- * @retval 0 if correct communication, else wrong communication
- */
-static void Audio_MAL_IRQHandler(void)
-{
-#ifndef AUDIO_MAL_MODE_NORMAL
- uint16_t *pAddr = (uint16_t *)CurrentPos;
- uint32_t Size = AudioRemSize;
-#endif /* AUDIO_MAL_MODE_NORMAL */
-
-#ifdef AUDIO_MAL_DMA_IT_TC_EN
- /* Transfer complete interrupt */
- if (DMA_GetFlagStatus(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TC) != RESET)
- {
- #ifdef AUDIO_MAL_MODE_NORMAL
- /* Check if the end of file has been reached */
- if (AudioRemSize > 0)
- {
- /* Wait the DMA Stream to be effectively disabled */
- while (DMA_GetCmdStatus(AUDIO_MAL_DMA_STREAM) != DISABLE)
- {}
-
- /* Clear the Interrupt flag */
- DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TC);
-
- /* Re-Configure the buffer address and size */
- DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t) CurrentPos;
- DMA_InitStructure.DMA_BufferSize = (uint32_t) (DMA_MAX(AudioRemSize));
-
- /* Configure the DMA Stream with the new parameters */
- DMA_Init(AUDIO_MAL_DMA_STREAM, &DMA_InitStructure);
-
- /* Enable the I2S DMA Stream*/
- DMA_Cmd(AUDIO_MAL_DMA_STREAM, ENABLE);
-
- /* Update the current pointer position */
- CurrentPos += DMA_MAX(AudioRemSize);
-
- /* Update the remaining number of data to be played */
- AudioRemSize -= DMA_MAX(AudioRemSize);
- }
- else
- {
- /* Disable the I2S DMA Stream*/
- DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE);
-
- /* Clear the Interrupt flag */
- DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TC);
-
- /* Manage the remaining file size and new address offset: This function
- should be coded by user (its prototype is already declared in stm32f4_discovery_audio_codec.h) */
- EVAL_AUDIO_TransferComplete_CallBack((uint32_t)CurrentPos, 0);
- }
-
- #elif defined(AUDIO_MAL_MODE_CIRCULAR)
- /* Manage the remaining file size and new address offset: This function
- should be coded by user (its prototype is already declared in stm32f4_discovery_audio_codec.h) */
- EVAL_AUDIO_TransferComplete_CallBack(pAddr, Size);
-
- /* Clear the Interrupt flag */
- DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TC);
- #endif /* AUDIO_MAL_MODE_NORMAL */
- }
-#endif /* AUDIO_MAL_DMA_IT_TC_EN */
-
-#ifdef AUDIO_MAL_DMA_IT_HT_EN
- /* Half Transfer complete interrupt */
- if (DMA_GetFlagStatus(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_HT) != RESET)
- {
- /* Manage the remaining file size and new address offset: This function
- should be coded by user (its prototype is already declared in stm32f4_discovery_audio_codec.h) */
- EVAL_AUDIO_HalfTransfer_CallBack((uint32_t)pAddr, Size);
-
- /* Clear the Interrupt flag */
- DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_HT);
- }
-#endif /* AUDIO_MAL_DMA_IT_HT_EN */
-
-#ifdef AUDIO_MAL_DMA_IT_TE_EN
- /* FIFO Error interrupt */
- if ((DMA_GetFlagStatus(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TE) != RESET) || \
- (DMA_GetFlagStatus(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_FE) != RESET) || \
- (DMA_GetFlagStatus(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_DME) != RESET))
-
- {
- /* Manage the error generated on DMA FIFO: This function
- should be coded by user (its prototype is already declared in stm32f4_discovery_audio_codec.h) */
- EVAL_AUDIO_Error_CallBack((uint32_t*)&pAddr);
-
- /* Clear the Interrupt flag */
- DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TE | AUDIO_MAL_DMA_FLAG_FE | \
- AUDIO_MAL_DMA_FLAG_DME);
- }
-#endif /* AUDIO_MAL_DMA_IT_TE_EN */
-}
-
-/**
- * @brief This function handles main I2S interrupt.
- * @param None
- * @retval 0 if correct communication, else wrong communication
- */
-void Audio_MAL_I2S_IRQHandler(void)
-{
- Audio_MAL_IRQHandler();
-}
-
-/**
- * @brief This function handles main DAC interrupt.
- * @param None
- * @retval 0 if correct communication, else wrong communication
- */
-void Audio_MAL_DAC_IRQHandler(void)
-{
- Audio_MAL_IRQHandler();
-}
-
-/**
- * @brief I2S interrupt management
- * @param None
- * @retval None
- */
-void Audio_I2S_IRQHandler(void)
-{
- /* Check on the I2S TXE flag */
- if (SPI_I2S_GetFlagStatus(SPI3, SPI_I2S_FLAG_TXE) != RESET)
- {
- if (CurrAudioInterface == AUDIO_INTERFACE_DAC)
- {
- /* Wirte data to the DAC interface */
- DAC_SetChannel1Data(DAC_Align_12b_L, EVAL_AUDIO_GetSampleCallBack());
- }
-
- /* Send dummy data on I2S to avoid the underrun condition */
- SPI_I2S_SendData(CODEC_I2S, EVAL_AUDIO_GetSampleCallBack());
- }
-}
-/*========================
-
- CS43L22 Audio Codec Control Functions
- ==============================*/
-/**
- * @brief Initializes the audio codec and all related interfaces (control
- * interface: I2C and audio interface: I2S)
- * @param OutputDevice: can be OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,
- * OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO .
- * @param Volume: Initial volume level (from 0 (Mute) to 100 (Max))
- * @param AudioFreq: Audio frequency used to play the audio stream.
- * @retval 0 if correct communication, else wrong communication
- */
-static uint32_t Codec_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq)
-{
- uint32_t counter = 0;
-
- /* Configure the Codec related IOs */
- Codec_GPIO_Init();
-
- /* Reset the Codec Registers */
- Codec_Reset();
-
- /* Initialize the Control interface of the Audio Codec */
- Codec_CtrlInterface_Init();
-
- /* Keep Codec powered OFF */
- counter += Codec_WriteRegister(0x02, 0x01);
-
- counter += Codec_WriteRegister(0x04, 0xAF); /* SPK always OFF & HP always ON */
- OutputDev = 0xAF;
-
- /* Clock configuration: Auto detection */
- counter += Codec_WriteRegister(0x05, 0x81);
-
- /* Set the Slave Mode and the audio Standard */
- counter += Codec_WriteRegister(0x06, CODEC_STANDARD);
-
- /* Set the Master volume */
- Codec_VolumeCtrl(Volume);
-
- if (CurrAudioInterface == AUDIO_INTERFACE_DAC)
- {
- /* Enable the PassThrough on AIN1A and AIN1B */
- counter += Codec_WriteRegister(0x08, 0x01);
- counter += Codec_WriteRegister(0x09, 0x01);
-
- /* Route the analog input to the HP line */
- counter += Codec_WriteRegister(0x0E, 0xC0);
-
- /* Set the Passthough volume */
- counter += Codec_WriteRegister(0x14, 0x00);
- counter += Codec_WriteRegister(0x15, 0x00);
- }
-
- /* Power on the Codec */
- counter += Codec_WriteRegister(0x02, 0x9E);
-
- /* Additional configuration for the CODEC. These configurations are done to reduce
- the time needed for the Codec to power off. If these configurations are removed,
- then a long delay should be added between powering off the Codec and switching
- off the I2S peripheral MCLK clock (which is the operating clock for Codec).
- If this delay is not inserted, then the codec will not shut down properly and
- it results in high noise after shut down. */
-
- /* Disable the analog soft ramp */
- counter += Codec_WriteRegister(0x0A, 0x00);
- if (CurrAudioInterface != AUDIO_INTERFACE_DAC)
- {
- /* Disable the digital soft ramp */
- counter += Codec_WriteRegister(0x0E, 0x04);
- }
- /* Disable the limiter attack level */
- counter += Codec_WriteRegister(0x27, 0x00);
- /* Adjust Bass and Treble levels */
- counter += Codec_WriteRegister(0x1F, 0x0F);
- /* Adjust PCM volume level */
- counter += Codec_WriteRegister(0x1A, 0x0A);
- counter += Codec_WriteRegister(0x1B, 0x0A);
-
- /* Configure the I2S peripheral */
- Codec_AudioInterface_Init(AudioFreq);
-
- /* Return communication control value */
- return counter;
-}
-
-/**
- * @brief Restore the audio codec state to default state and free all used
- * resources.
- * @param None
- * @retval 0 if correct communication, else wrong communication
- */
-static uint32_t Codec_DeInit(void)
-{
- uint32_t counter = 0;
-
- /* Reset the Codec Registers */
- Codec_Reset();
-
- /* Keep Codec powered OFF */
- counter += Codec_WriteRegister(0x02, 0x01);
-
- /* Deinitialize all use GPIOs */
- Codec_GPIO_DeInit();
-
- /* Disable the Codec control interface */
- Codec_CtrlInterface_DeInit();
-
- /* Deinitialize the Codec audio interface (I2S) */
- Codec_AudioInterface_DeInit();
-
- /* Return communication control value */
- return counter;
-}
-
-/**
- * @brief Start the audio Codec play feature.
- * @note For this codec no Play options are required.
- * @param None
- * @retval 0 if correct communication, else wrong communication
- */
-static uint32_t Codec_Play(void)
-{
- /*
- No actions required on Codec level for play command
- */
-
- /* Return communication control value */
- return 0;
-}
-
-/**
- * @brief Pauses and resumes playing on the audio codec.
- * @param Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different
- * from 0) to resume.
- * @retval 0 if correct communication, else wrong communication
- */
-static uint32_t Codec_PauseResume(uint32_t Cmd)
-{
- uint32_t counter = 0;
-
- /* Pause the audio file playing */
- if (Cmd == AUDIO_PAUSE)
- {
- /* Mute the output first */
- counter += Codec_Mute(AUDIO_MUTE_ON);
-
- /* Put the Codec in Power save mode */
- counter += Codec_WriteRegister(0x02, 0x01);
- }
- else /* AUDIO_RESUME */
- {
- /* Unmute the output first */
- counter += Codec_Mute(AUDIO_MUTE_OFF);
-
- counter += Codec_WriteRegister(0x04, OutputDev);
-
- /* Exit the Power save mode */
- counter += Codec_WriteRegister(0x02, 0x9E);
- }
-
- return counter;
-}
-
-/**
- * @brief Stops audio Codec playing. It powers down the codec.
- * @param CodecPdwnMode: selects the power down mode.
- * - CODEC_PDWN_SW: only mutes the audio codec. When resuming from this
- * mode the codec keeps the previous initialization
- * (no need to re-Initialize the codec registers).
- * - CODEC_PDWN_HW: Physically power down the codec. When resuming from this
- * mode, the codec is set to default configuration
- * (user should re-Initialize the codec in order to
- * play again the audio stream).
- * @retval 0 if correct communication, else wrong communication
- */
-static uint32_t Codec_Stop(uint32_t CodecPdwnMode)
-{
- uint32_t counter = 0;
-
- /* Mute the output first */
- Codec_Mute(AUDIO_MUTE_ON);
-
- if (CodecPdwnMode == CODEC_PDWN_SW)
- {
- /* Power down the DAC and the speaker (PMDAC and PMSPK bits)*/
- counter += Codec_WriteRegister(0x02, 0x9F);
- }
- else /* CODEC_PDWN_HW */
- {
- /* Power down the DAC components */
- counter += Codec_WriteRegister(0x02, 0x9F);
-
- /* Wait at least 100us */
- Delay(0xFFF);
-
- /* Reset The pin */
- GPIO_WriteBit(AUDIO_RESET_GPIO, AUDIO_RESET_PIN, Bit_RESET);
- }
-
- return counter;
-}
-
-/**
- * @brief Sets higher or lower the codec volume level.
- * @param Volume: a byte value from 0 to 255 (refer to codec registers
- * description for more details).
- * @retval 0 if correct communication, else wrong communication
- */
-static uint32_t Codec_VolumeCtrl(uint8_t Volume)
-{
- uint32_t counter = 0;
-
- if (Volume > 0xE6)
- {
- /* Set the Master volume */
- counter += Codec_WriteRegister(0x20, Volume - 0xE7);
- counter += Codec_WriteRegister(0x21, Volume - 0xE7);
- }
- else
- {
- /* Set the Master volume */
- counter += Codec_WriteRegister(0x20, Volume + 0x19);
- counter += Codec_WriteRegister(0x21, Volume + 0x19);
- }
-
- return counter;
-}
-
-/**
- * @brief Enables or disables the mute feature on the audio codec.
- * @param Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the
- * mute mode.
- * @retval 0 if correct communication, else wrong communication
- */
-static uint32_t Codec_Mute(uint32_t Cmd)
-{
- uint32_t counter = 0;
-
- /* Set the Mute mode */
- if (Cmd == AUDIO_MUTE_ON)
- {
- counter += Codec_WriteRegister(0x04, 0xFF);
- }
- else /* AUDIO_MUTE_OFF Disable the Mute */
- {
- counter += Codec_WriteRegister(0x04, OutputDev);
- }
-
- return counter;
-}
-
-/**
- * @brief Resets the audio codec. It restores the default configuration of the
- * codec (this function shall be called before initializing the codec).
- * @note This function calls an external driver function: The IO Expander driver.
- * @param None
- * @retval None
- */
-static void Codec_Reset(void)
-{
- /* Power Down the codec */
- GPIO_WriteBit(AUDIO_RESET_GPIO, AUDIO_RESET_PIN, Bit_RESET);
-
- /* wait for a delay to insure registers erasing */
- Delay(CODEC_RESET_DELAY);
-
- /* Power on the codec */
- GPIO_WriteBit(AUDIO_RESET_GPIO, AUDIO_RESET_PIN, Bit_SET);
-}
-
-/**
- * @brief Writes a Byte to a given register into the audio codec through the
- control interface (I2C)
- * @param RegisterAddr: The address (location) of the register to be written.
- * @param RegisterValue: the Byte value to be written into destination register.
- * @retval 0 if correct communication, else wrong communication
- */
-static uint32_t Codec_WriteRegister(uint8_t RegisterAddr, uint8_t RegisterValue)
-{
- uint32_t result = 0;
-
- /*!< While the bus is busy */
- CODECTimeout = CODEC_LONG_TIMEOUT;
- while(I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_BUSY))
- {
- if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
- }
-
- /* Start the config sequence */
- I2C_GenerateSTART(CODEC_I2C, ENABLE);
-
- /* Test on EV5 and clear it */
- CODECTimeout = CODEC_FLAG_TIMEOUT;
- while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_MODE_SELECT))
- {
- if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
- }
-
- /* Transmit the slave address and enable writing operation */
- I2C_Send7bitAddress(CODEC_I2C, CODEC_ADDRESS, I2C_Direction_Transmitter);
-
- /* Test on EV6 and clear it */
- CODECTimeout = CODEC_FLAG_TIMEOUT;
- while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
- {
- if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
- }
-
- /* Transmit the first address for write operation */
- I2C_SendData(CODEC_I2C, RegisterAddr);
-
- /* Test on EV8 and clear it */
- CODECTimeout = CODEC_FLAG_TIMEOUT;
- while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING))
- {
- if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
- }
-
- /* Prepare the register value to be sent */
- I2C_SendData(CODEC_I2C, RegisterValue);
-
- /*!< Wait till all data have been physically transferred on the bus */
- CODECTimeout = CODEC_LONG_TIMEOUT;
- while(!I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_BTF))
- {
- if((CODECTimeout--) == 0) Codec_TIMEOUT_UserCallback();
- }
-
- /* End the configuration sequence */
- I2C_GenerateSTOP(CODEC_I2C, ENABLE);
-
-#ifdef VERIFY_WRITTENDATA
- /* Verify that the data has been correctly written */
- result = (Codec_ReadRegister(RegisterAddr) == RegisterValue)? 0:1;
-#endif /* VERIFY_WRITTENDATA */
-
- /* Return the verifying value: 0 (Passed) or 1 (Failed) */
- return result;
-}
-
-/**
- * @brief Reads and returns the value of an audio codec register through the
- * control interface (I2C).
- * @param RegisterAddr: Address of the register to be read.
- * @retval Value of the register to be read or dummy value if the communication
- * fails.
- */
-static uint32_t Codec_ReadRegister(uint8_t RegisterAddr)
-{
- uint32_t result = 0;
-
- /*!< While the bus is busy */
- CODECTimeout = CODEC_LONG_TIMEOUT;
- while(I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_BUSY))
- {
- if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
- }
-
- /* Start the config sequence */
- I2C_GenerateSTART(CODEC_I2C, ENABLE);
-
- /* Test on EV5 and clear it */
- CODECTimeout = CODEC_FLAG_TIMEOUT;
- while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_MODE_SELECT))
- {
- if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
- }
-
- /* Transmit the slave address and enable writing operation */
- I2C_Send7bitAddress(CODEC_I2C, CODEC_ADDRESS, I2C_Direction_Transmitter);
-
- /* Test on EV6 and clear it */
- CODECTimeout = CODEC_FLAG_TIMEOUT;
- while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
- {
- if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
- }
-
- /* Transmit the register address to be read */
- I2C_SendData(CODEC_I2C, RegisterAddr);
-
- /* Test on EV8 and clear it */
- CODECTimeout = CODEC_FLAG_TIMEOUT;
- while (I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_BTF) == RESET)
- {
- if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
- }
-
- /*!< Send START condition a second time */
- I2C_GenerateSTART(CODEC_I2C, ENABLE);
-
- /*!< Test on EV5 and clear it (cleared by reading SR1 then writing to DR) */
- CODECTimeout = CODEC_FLAG_TIMEOUT;
- while(!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_MODE_SELECT))
- {
- if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
- }
-
- /*!< Send Codec address for read */
- I2C_Send7bitAddress(CODEC_I2C, CODEC_ADDRESS, I2C_Direction_Receiver);
-
- /* Wait on ADDR flag to be set (ADDR is still not cleared at this level */
- CODECTimeout = CODEC_FLAG_TIMEOUT;
- while(I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_ADDR) == RESET)
- {
- if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
- }
-
- /*!< Disable Acknowledgment */
- I2C_AcknowledgeConfig(CODEC_I2C, DISABLE);
-
- /* Clear ADDR register by reading SR1 then SR2 register (SR1 has already been read) */
- (void)CODEC_I2C->SR2;
-
- /*!< Send STOP Condition */
- I2C_GenerateSTOP(CODEC_I2C, ENABLE);
-
- /* Wait for the byte to be received */
- CODECTimeout = CODEC_FLAG_TIMEOUT;
- while(I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_RXNE) == RESET)
- {
- if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
- }
-
- /*!< Read the byte received from the Codec */
- result = I2C_ReceiveData(CODEC_I2C);
-
- /* Wait to make sure that STOP flag has been cleared */
- CODECTimeout = CODEC_FLAG_TIMEOUT;
- while(CODEC_I2C->CR1 & I2C_CR1_STOP)
- {
- if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
- }
-
- /*!< Re-Enable Acknowledgment to be ready for another reception */
- I2C_AcknowledgeConfig(CODEC_I2C, ENABLE);
-
- /* Clear AF flag for next communication */
- I2C_ClearFlag(CODEC_I2C, I2C_FLAG_AF);
-
- /* Return the byte read from Codec */
- return result;
-}
-
-/**
- * @brief Initializes the Audio Codec control interface (I2C).
- * @param None
- * @retval None
- */
-static void Codec_CtrlInterface_Init(void)
-{
- I2C_InitTypeDef I2C_InitStructure;
-
- /* Enable the CODEC_I2C peripheral clock */
- RCC_APB1PeriphClockCmd(CODEC_I2C_CLK, ENABLE);
-
- /* CODEC_I2C peripheral configuration */
- I2C_DeInit(CODEC_I2C);
- I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
- I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
- I2C_InitStructure.I2C_OwnAddress1 = 0x33;
- I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
- I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
- I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED;
- /* Enable the I2C peripheral */
- I2C_Cmd(CODEC_I2C, ENABLE);
- I2C_Init(CODEC_I2C, &I2C_InitStructure);
-}
-
-/**
- * @brief Restore the Audio Codec control interface to its default state.
- * This function doesn't de-initialize the I2C because the I2C peripheral
- * may be used by other modules.
- * @param None
- * @retval None
- */
-static void Codec_CtrlInterface_DeInit(void)
-{
- /* Disable the I2C peripheral */ /* This step is not done here because
- the I2C interface can be used by other modules */
- /* I2C_DeInit(CODEC_I2C); */
-}
-
-/**
- * @brief Initializes the Audio Codec audio interface (I2S)
- * @note This function assumes that the I2S input clock (through PLL_R in
- * Devices RevA/Z and through dedicated PLLI2S_R in Devices RevB/Y)
- * is already configured and ready to be used.
- * @param AudioFreq: Audio frequency to be configured for the I2S peripheral.
- * @retval None
- */
-static void Codec_AudioInterface_Init(uint32_t AudioFreq)
-{
- I2S_InitTypeDef I2S_InitStructure;
- DAC_InitTypeDef DAC_InitStructure;
-
- /* Enable the CODEC_I2S peripheral clock */
- RCC_APB1PeriphClockCmd(CODEC_I2S_CLK, ENABLE);
-
- /* CODEC_I2S peripheral configuration */
- SPI_I2S_DeInit(CODEC_I2S);
- I2S_InitStructure.I2S_AudioFreq = AudioFreq;
- I2S_InitStructure.I2S_Standard = I2S_STANDARD;
- I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
- I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
-#ifdef DAC_USE_I2S_DMA
- if (CurrAudioInterface == AUDIO_INTERFACE_DAC)
- {
- I2S_InitStructure.I2S_Mode = I2S_Mode_MasterRx;
- }
- else
- {
-#else
- I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
-#endif
-#ifdef DAC_USE_I2S_DMA
- }
-#endif /* DAC_USE_I2S_DMA */
-#ifdef CODEC_MCLK_ENABLED
- I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Enable;
-#elif defined(CODEC_MCLK_DISABLED)
- I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
-#else
-#error "No selection for the MCLK output has been defined !"
-#endif /* CODEC_MCLK_ENABLED */
-
- /* Initialize the I2S peripheral with the structure above */
- I2S_Init(CODEC_I2S, &I2S_InitStructure);
-
-
- /* Configure the DAC interface */
- if (CurrAudioInterface == AUDIO_INTERFACE_DAC)
- {
- /* DAC Periph clock enable */
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);
-
- /* DAC channel1 Configuration */
- DAC_InitStructure.DAC_Trigger = DAC_Trigger_None;
- DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;
- DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
- DAC_Init(AUDIO_DAC_CHANNEL, &DAC_InitStructure);
-
- /* Enable DAC Channel1 */
- DAC_Cmd(AUDIO_DAC_CHANNEL, ENABLE);
- }
-
- /* The I2S peripheral will be enabled only in the EVAL_AUDIO_Play() function
- or by user functions if DMA mode not enabled */
-}
-
-/**
- * @brief Restores the Audio Codec audio interface to its default state.
- * @param None
- * @retval None
- */
-static void Codec_AudioInterface_DeInit(void)
-{
- /* Disable the CODEC_I2S peripheral (in case it hasn't already been disabled) */
- I2S_Cmd(CODEC_I2S, DISABLE);
-
- /* Deinitialize the CODEC_I2S peripheral */
- SPI_I2S_DeInit(CODEC_I2S);
-
- /* Disable the CODEC_I2S peripheral clock */
- RCC_APB1PeriphClockCmd(CODEC_I2S_CLK, DISABLE);
-}
-
-/**
- * @brief Initializes IOs used by the Audio Codec (on the control and audio
- * interfaces).
- * @param None
- * @retval None
- */
-static void Codec_GPIO_Init(void)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
-
- /* Enable Reset GPIO Clock */
- RCC_AHB1PeriphClockCmd(AUDIO_RESET_GPIO_CLK,ENABLE);
-
- /* Audio reset pin configuration -------------------------------------------------*/
- GPIO_InitStructure.GPIO_Pin = AUDIO_RESET_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_Init(AUDIO_RESET_GPIO, &GPIO_InitStructure);
-
- /* Enable I2S and I2C GPIO clocks */
- RCC_AHB1PeriphClockCmd(CODEC_I2C_GPIO_CLOCK | CODEC_I2S_GPIO_CLOCK, ENABLE);
-
- /* CODEC_I2C SCL and SDA pins configuration -------------------------------------*/
- GPIO_InitStructure.GPIO_Pin = CODEC_I2C_SCL_PIN | CODEC_I2C_SDA_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_Init(CODEC_I2C_GPIO, &GPIO_InitStructure);
- /* Connect pins to I2C peripheral */
- GPIO_PinAFConfig(CODEC_I2C_GPIO, CODEC_I2S_SCL_PINSRC, CODEC_I2C_GPIO_AF);
- GPIO_PinAFConfig(CODEC_I2C_GPIO, CODEC_I2S_SDA_PINSRC, CODEC_I2C_GPIO_AF);
-
- /* CODEC_I2S pins configuration: WS, SCK and SD pins -----------------------------*/
- GPIO_InitStructure.GPIO_Pin = CODEC_I2S_SCK_PIN | CODEC_I2S_SD_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure);
-
- /* Connect pins to I2S peripheral */
- GPIO_PinAFConfig(CODEC_I2S_WS_GPIO, CODEC_I2S_WS_PINSRC, CODEC_I2S_GPIO_AF);
- GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SCK_PINSRC, CODEC_I2S_GPIO_AF);
-
- if (CurrAudioInterface != AUDIO_INTERFACE_DAC)
- {
- GPIO_InitStructure.GPIO_Pin = CODEC_I2S_WS_PIN ;
- GPIO_Init(CODEC_I2S_WS_GPIO, &GPIO_InitStructure);
- GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SD_PINSRC, CODEC_I2S_GPIO_AF);
- }
- else
- {
- /* GPIOA clock enable (to be used with DAC) */
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
-
- /* DAC channel 1 & 2 (DAC_OUT1 = PA.4) configuration */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
- }
-
-#ifdef CODEC_MCLK_ENABLED
- /* CODEC_I2S pins configuration: MCK pin */
- GPIO_InitStructure.GPIO_Pin = CODEC_I2S_MCK_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_Init(CODEC_I2S_MCK_GPIO, &GPIO_InitStructure);
- /* Connect pins to I2S peripheral */
- GPIO_PinAFConfig(CODEC_I2S_MCK_GPIO, CODEC_I2S_MCK_PINSRC, CODEC_I2S_GPIO_AF);
-#endif /* CODEC_MCLK_ENABLED */
-}
-
-/**
- * @brief Restores the IOs used by the Audio Codec interface to their default state.
- * @param None
- * @retval None
- */
-static void Codec_GPIO_DeInit(void)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
-
- /* Deinitialize all the GPIOs used by the driver */
- GPIO_InitStructure.GPIO_Pin = CODEC_I2S_SCK_PIN | CODEC_I2S_SD_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure);
-
- GPIO_InitStructure.GPIO_Pin = CODEC_I2S_WS_PIN ;
- GPIO_Init(CODEC_I2S_WS_GPIO, &GPIO_InitStructure);
-
- /* Disconnect pins from I2S peripheral */
- GPIO_PinAFConfig(CODEC_I2S_WS_GPIO, CODEC_I2S_WS_PINSRC, 0x00);
- GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SCK_PINSRC, 0x00);
- GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SD_PINSRC, 0x00);
-
-#ifdef CODEC_MCLK_ENABLED
- /* CODEC_I2S pins deinitialization: MCK pin */
- GPIO_InitStructure.GPIO_Pin = CODEC_I2S_MCK_PIN;
- GPIO_Init(CODEC_I2S_MCK_GPIO, &GPIO_InitStructure);
- /* Disconnect pins from I2S peripheral */
- GPIO_PinAFConfig(CODEC_I2S_MCK_GPIO, CODEC_I2S_MCK_PINSRC, CODEC_I2S_GPIO_AF);
-#endif /* CODEC_MCLK_ENABLED */
-}
-
-/**
- * @brief Inserts a delay time (not accurate timing).
- * @param nCount: specifies the delay time length.
- * @retval None
- */
-static void Delay( __IO uint32_t nCount)
-{
- for (; nCount != 0; nCount--);
-}
-
-#ifdef USE_DEFAULT_TIMEOUT_CALLBACK
-/**
- * @brief Basic management of the timeout situation.
- * @param None
- * @retval None
- */
-uint32_t Codec_TIMEOUT_UserCallback(void)
-{
- /* Block communication and all processes */
- while (1)
- {
- }
-}
-#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */
-/*========================
-
- Audio MAL Interface Control Functions
-
- ==============================*/
-
-/**
- * @brief Initializes and prepares the Media to perform audio data transfer
- * from Media to the I2S peripheral.
- * @param None
- * @retval None
- */
-static void Audio_MAL_Init(void)
-{
-
-#ifdef I2S_INTERRUPT
- NVIC_InitTypeDef NVIC_InitStructure;
-
- NVIC_InitStructure.NVIC_IRQChannel = SPI3_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority =0;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
-
- SPI_I2S_ITConfig(SPI3, SPI_I2S_IT_TXE, ENABLE);
-
- I2S_Cmd(SPI3, ENABLE);
-#else
-#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN)
- NVIC_InitTypeDef NVIC_InitStructure;
-#endif
-
- if (CurrAudioInterface == AUDIO_INTERFACE_I2S)
- {
- /* Enable the DMA clock */
- RCC_AHB1PeriphClockCmd(AUDIO_MAL_DMA_CLOCK, ENABLE);
-
- /* Configure the DMA Stream */
- DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE);
- DMA_DeInit(AUDIO_MAL_DMA_STREAM);
- /* Set the parameters to be configured */
- DMA_InitStructure.DMA_Channel = AUDIO_MAL_DMA_CHANNEL;
- DMA_InitStructure.DMA_PeripheralBaseAddr = AUDIO_MAL_DMA_DREG;
- DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)0; /* This field will be configured in play function */
- DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
- DMA_InitStructure.DMA_BufferSize = (uint32_t)0xFFFE; /* This field will be configured in play function */
- DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
- DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
- DMA_InitStructure.DMA_PeripheralDataSize = AUDIO_MAL_DMA_PERIPH_DATA_SIZE;
- DMA_InitStructure.DMA_MemoryDataSize = AUDIO_MAL_DMA_MEM_DATA_SIZE;
-#ifdef AUDIO_MAL_MODE_NORMAL
- DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-#elif defined(AUDIO_MAL_MODE_CIRCULAR)
- DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
-#else
-#error "AUDIO_MAL_MODE_NORMAL or AUDIO_MAL_MODE_CIRCULAR should be selected !!"
-#endif /* AUDIO_MAL_MODE_NORMAL */
- DMA_InitStructure.DMA_Priority = DMA_Priority_High;
- DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable;
- DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
- DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
- DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
- DMA_Init(AUDIO_MAL_DMA_STREAM, &DMA_InitStructure);
-
- /* Enable the selected DMA interrupts (selected in "stm32f4_discovery_eval_audio_codec.h" defines) */
-#ifdef AUDIO_MAL_DMA_IT_TC_EN
- DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_TC, ENABLE);
-#endif /* AUDIO_MAL_DMA_IT_TC_EN */
-#ifdef AUDIO_MAL_DMA_IT_HT_EN
- DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_HT, ENABLE);
-#endif /* AUDIO_MAL_DMA_IT_HT_EN */
-#ifdef AUDIO_MAL_DMA_IT_TE_EN
- DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_TE | DMA_IT_FE | DMA_IT_DME, ENABLE);
-#endif /* AUDIO_MAL_DMA_IT_TE_EN */
-
-#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN)
- /* I2S DMA IRQ Channel configuration */
- NVIC_InitStructure.NVIC_IRQChannel = AUDIO_MAL_DMA_IRQ;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = EVAL_AUDIO_IRQ_PREPRIO;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = EVAL_AUDIO_IRQ_SUBRIO;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
-#endif
- }
-
-#ifdef DAC_USE_I2S_DMA
- else
- {
- /* Enable the DMA clock */
- RCC_AHB1PeriphClockCmd(AUDIO_MAL_DMA_CLOCK, ENABLE);
-
- /* Configure the DMA Stream */
- DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE);
- DMA_DeInit(AUDIO_MAL_DMA_STREAM);
- /* Set the parameters to be configured */
- DMA_InitStructure.DMA_Channel = AUDIO_MAL_DMA_CHANNEL;
- DMA_InitStructure.DMA_PeripheralBaseAddr = AUDIO_MAL_DMA_DREG;
- DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)0; /* This field will be configured in play function */
- DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
- DMA_InitStructure.DMA_BufferSize = (uint32_t)0xFFFE; /* This field will be configured in play function */
- DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
- DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
- DMA_InitStructure.DMA_PeripheralDataSize = AUDIO_MAL_DMA_PERIPH_DATA_SIZE;
- DMA_InitStructure.DMA_MemoryDataSize = AUDIO_MAL_DMA_MEM_DATA_SIZE;
-#ifdef AUDIO_MAL_MODE_NORMAL
- DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-#elif defined(AUDIO_MAL_MODE_CIRCULAR)
- DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
-#else
-#error "AUDIO_MAL_MODE_NORMAL or AUDIO_MAL_MODE_CIRCULAR should be selected !!"
-#endif /* AUDIO_MAL_MODE_NORMAL */
- DMA_InitStructure.DMA_Priority = DMA_Priority_High;
- DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable;
- DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
- DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
- DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
- DMA_Init(AUDIO_MAL_DMA_STREAM, &DMA_InitStructure);
-
- /* Enable the selected DMA interrupts (selected in "stm32f4_discovery_eval_audio_codec.h" defines) */
-#ifdef AUDIO_MAL_DMA_IT_TC_EN
- DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_TC, ENABLE);
-#endif /* AUDIO_MAL_DMA_IT_TC_EN */
-#ifdef AUDIO_MAL_DMA_IT_HT_EN
- DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_HT, ENABLE);
-#endif /* AUDIO_MAL_DMA_IT_HT_EN */
-#ifdef AUDIO_MAL_DMA_IT_TE_EN
- DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_TE | DMA_IT_FE | DMA_IT_DME, ENABLE);
-#endif /* AUDIO_MAL_DMA_IT_TE_EN */
-
-#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN)
- /* I2S DMA IRQ Channel configuration */
- NVIC_InitStructure.NVIC_IRQChannel = AUDIO_MAL_DMA_IRQ;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = EVAL_AUDIO_IRQ_PREPRIO;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = EVAL_AUDIO_IRQ_SUBRIO;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
-#endif
- }
-#endif /* DAC_USE_I2S_DMA */
-
- if (CurrAudioInterface == AUDIO_INTERFACE_I2S)
- {
- /* Enable the I2S DMA request */
- SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, ENABLE);
- }
- else
- {
- /* Configure the STM32 DAC to geenrate audio analog signal */
- DAC_Config();
-
-#ifndef DAC_USE_I2S_DMA
- /* Enable the I2S interrupt used to write into the DAC register */
- SPI_I2S_ITConfig(SPI3, SPI_I2S_IT_TXE, ENABLE);
-
- /* I2S DMA IRQ Channel configuration */
- NVIC_InitStructure.NVIC_IRQChannel = CODEC_I2S_IRQ;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = EVAL_AUDIO_IRQ_PREPRIO;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = EVAL_AUDIO_IRQ_SUBRIO;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
-#else
- /* Enable the I2S DMA request */
- SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Rx, ENABLE);
-#endif /* DAC_USE_I2S_DMA */
- }
-#endif
-}
-
-/**
- * @brief Restore default state of the used Media.
- * @param None
- * @retval None
- */
-static void Audio_MAL_DeInit(void)
-{
-#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN)
- NVIC_InitTypeDef NVIC_InitStructure;
-
- /* Deinitialize the NVIC interrupt for the I2S DMA Stream */
- NVIC_InitStructure.NVIC_IRQChannel = AUDIO_MAL_DMA_IRQ;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = EVAL_AUDIO_IRQ_PREPRIO;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = EVAL_AUDIO_IRQ_SUBRIO;
- NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
- NVIC_Init(&NVIC_InitStructure);
-#endif
-
- /* Disable the DMA stream before the deinit */
- DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE);
-
- /* Dinitialize the DMA Stream */
- DMA_DeInit(AUDIO_MAL_DMA_STREAM);
-
- /*
- The DMA clock is not disabled, since it can be used by other streams
- */
-}
-
-/**
- * @brief Starts playing audio stream from the audio Media.
- * @param None
- * @retval None
- */
-static void Audio_MAL_Play(uint32_t Addr, uint32_t Size)
-{
- if (CurrAudioInterface == AUDIO_INTERFACE_I2S)
- {
- /* Configure the buffer address and size */
- DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)Addr;
- DMA_InitStructure.DMA_BufferSize = (uint32_t)Size;
-
- /* Configure the DMA Stream with the new parameters */
- DMA_Init(AUDIO_MAL_DMA_STREAM, &DMA_InitStructure);
-
- /* Enable the I2S DMA Stream*/
- DMA_Cmd(AUDIO_MAL_DMA_STREAM, ENABLE);
- }
-#ifndef DAC_USE_I2S_DMA
- else
- {
- /* Configure the buffer address and size */
- DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)Addr;
- DMA_InitStructure.DMA_BufferSize = (uint32_t)Size;
-
- /* Configure the DMA Stream with the new parameters */
- DMA_Init(AUDIO_MAL_DMA_STREAM, &DMA_InitStructure);
-
- /* Enable the I2S DMA Stream*/
- DMA_Cmd(AUDIO_MAL_DMA_STREAM, ENABLE);
- }
-#endif /* DAC_USE_I2S_DMA */
-
- /* If the I2S peripheral is still not enabled, enable it */
- if ((CODEC_I2S->I2SCFGR & I2S_ENABLE_MASK) == 0)
- {
- I2S_Cmd(CODEC_I2S, ENABLE);
- }
-}
-
-/**
- * @brief Pauses or Resumes the audio stream playing from the Media.
- * @param Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different
- * from 0) to resume.
- * @param Addr: Address from/at which the audio stream should resume/pause.
- * @retval None
- */
-static void Audio_MAL_PauseResume(uint32_t Cmd, uint32_t Addr)
-{
- /* Pause the audio file playing */
- if (Cmd == AUDIO_PAUSE)
- {
- /* Disable the I2S DMA request */
- SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, DISABLE);
-
- /* Pause the I2S DMA Stream
- Note. For the STM32F4xx devices, the DMA implements a pause feature,
- by disabling the stream, all configuration is preserved and data
- transfer is paused till the next enable of the stream.
- This feature is not available on STM32F4xx devices. */
- DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE);
- }
- else /* AUDIO_RESUME */
- {
- /* Enable the I2S DMA request */
- SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, ENABLE);
-
- /* Resume the I2S DMA Stream
- Note. For the STM32F4xx devices, the DMA implements a pause feature,
- by disabling the stream, all configuration is preserved and data
- transfer is paused till the next enable of the stream.
- This feature is not available on STM32F4xx devices. */
- DMA_Cmd(AUDIO_MAL_DMA_STREAM, ENABLE);
-
- /* If the I2S peripheral is still not enabled, enable it */
- if ((CODEC_I2S->I2SCFGR & I2S_ENABLE_MASK) == 0)
- {
- I2S_Cmd(CODEC_I2S, ENABLE);
- }
- }
-}
-
-/**
- * @brief Stops audio stream playing on the used Media.
- * @param None
- * @retval None
- */
-static void Audio_MAL_Stop(void)
-{
- /* Stop the Transfer on the I2S side: Stop and disable the DMA stream */
- DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE);
-
- /* Clear all the DMA flags for the next transfer */
- DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TC |AUDIO_MAL_DMA_FLAG_HT | \
- AUDIO_MAL_DMA_FLAG_FE | AUDIO_MAL_DMA_FLAG_TE);
-
- /*
- The I2S DMA requests are not disabled here.
- */
-
- /* In all modes, disable the I2S peripheral */
- I2S_Cmd(CODEC_I2S, DISABLE);
-}
-
-/**
- * @brief DAC Channel1 Configuration
- * @param None
- * @retval None
- */
-void DAC_Config(void)
-{
- DAC_InitTypeDef DAC_InitStructure;
- GPIO_InitTypeDef GPIO_InitStructure;
-
- /* DMA1 clock and GPIOA clock enable (to be used with DAC) */
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1 | RCC_AHB1Periph_GPIOA, ENABLE);
-
- /* DAC Periph clock enable */
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);
-
- /* DAC channel 1 & 2 (DAC_OUT1 = PA.4) configuration */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- /* DAC channel1 Configuration */
- DAC_InitStructure.DAC_Trigger = DAC_Trigger_None;
- DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;
- DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
- DAC_Init(AUDIO_DAC_CHANNEL, &DAC_InitStructure);
-
- /* Enable DAC Channel1 */
- DAC_Cmd(AUDIO_DAC_CHANNEL, ENABLE);
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4_discovery_audio_codec.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief This file contains all the functions prototypes for the
- * stm32f4_discovery_audio_codec.c driver.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4_DISCOVERY_AUDIOCODEC_H
-#define __STM32F4_DISCOVERY_AUDIOCODEC_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-#include "stm32f4xx_gpio.h"
-
-/** @addtogroup Utilities
- * @{
- */
-
-
-/** @addtogroup STM32F4_DISCOVERY
- * @{
- */
-
-/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC
- * @{
- */
-
-
-/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Exported_Types
- * @{
- */
-
-/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Exported_Constants
- * @{
- */
-
-/*------------------------------------
- CONFIGURATION: Audio Codec Driver Configuration parameters
- ----------------------------------------*/
-#define I2S_INTERRUPT
-/* Audio Transfer mode (DMA, Interrupt or Polling) */
-#define AUDIO_MAL_MODE_NORMAL /* Uncomment this line to enable the audio
- Transfer using DMA */
-/* #define AUDIO_MAL_MODE_CIRCULAR */ /* Uncomment this line to enable the audio
- Transfer using DMA */
-
-/* For the DMA modes select the interrupt that will be used */
-#define AUDIO_MAL_DMA_IT_TC_EN /* Uncomment this line to enable DMA Transfer Complete interrupt */
-/* #define AUDIO_MAL_DMA_IT_HT_EN */ /* Uncomment this line to enable DMA Half Transfer Complete interrupt */
-/* #define AUDIO_MAL_DMA_IT_TE_EN */ /* Uncomment this line to enable DMA Transfer Error interrupt */
-
-/* Select the interrupt preemption priority and subpriority for the DMA interrupt */
-#define EVAL_AUDIO_IRQ_PREPRIO 0 /* Select the preemption priority level(0 is the highest) */
-#define EVAL_AUDIO_IRQ_SUBRIO 0 /* Select the sub-priority level (0 is the highest) */
-
-/* Uncomment the following line to use the default Codec_TIMEOUT_UserCallback()
- function implemented in stm32f4_discovery_audio_codec.c file.
- Codec_TIMEOUT_UserCallback() function is called whenever a timeout condition
- occurs during communication (waiting on an event that doesn't occur, bus
- errors, busy devices ...). */
-/* #define USE_DEFAULT_TIMEOUT_CALLBACK */
-
-/* Enable this define to use the I2S DMA for writing into DAC register */
-//#define DAC_USE_I2S_DMA
-/*----------------------------------------------------------------------------*/
-
-/*------------------------------------
- OPTIONAL Configuration defines parameters
- ----------------------------------------*/
-/* I2C clock speed configuration (in Hz)
- WARNING:
- Make sure that this define is not already declared in other files (ie.
- stm322xg_eval.h file). It can be used in parallel by other modules. */
-#ifndef I2C_SPEED
- #define I2C_SPEED 100000
-#endif /* I2C_SPEED */
-
-/* Uncomment defines below to select standard for audio communication between
- Codec and I2S peripheral */
-#define I2S_STANDARD_PHILLIPS
-/* #define I2S_STANDARD_MSB */
-/* #define I2S_STANDARD_LSB */
-
-/* Uncomment the defines below to select if the Master clock mode should be
- enabled or not */
-#define CODEC_MCLK_ENABLED
-/* #deine CODEC_MCLK_DISABLED */
-
-/* Uncomment this line to enable verifying data sent to codec after each write
- operation */
-#define VERIFY_WRITTENDATA
-/*----------------------------------------------------------------------------*/
-
-/*-----------------------------------
- Hardware Configuration defines parameters
- -----------------------------------------*/
-/* Audio Reset Pin definition */
-#define AUDIO_RESET_GPIO_CLK RCC_AHB1Periph_GPIOD
-#define AUDIO_RESET_PIN GPIO_Pin_4
-#define AUDIO_RESET_GPIO GPIOD
-
-/* I2S peripheral configuration defines */
-#define CODEC_I2S SPI3
-#define CODEC_I2S_CLK RCC_APB1Periph_SPI3
-#define CODEC_I2S_ADDRESS 0x40003C0C
-#define CODEC_I2S_GPIO_AF GPIO_AF_SPI3
-#define CODEC_I2S_IRQ SPI3_IRQn
-#define CODEC_I2S_GPIO_CLOCK (RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOA)
-#define CODEC_I2S_WS_PIN GPIO_Pin_4
-#define CODEC_I2S_SCK_PIN GPIO_Pin_10
-#define CODEC_I2S_SD_PIN GPIO_Pin_12
-#define CODEC_I2S_MCK_PIN GPIO_Pin_7
-#define CODEC_I2S_WS_PINSRC GPIO_PinSource4
-#define CODEC_I2S_SCK_PINSRC GPIO_PinSource10
-#define CODEC_I2S_SD_PINSRC GPIO_PinSource12
-#define CODEC_I2S_MCK_PINSRC GPIO_PinSource7
-#define CODEC_I2S_GPIO GPIOC
-#define CODEC_I2S_WS_GPIO GPIOA
-#define CODEC_I2S_MCK_GPIO GPIOC
-#define Audio_I2S_IRQHandler SPI3_IRQHandler
-
-
- #define AUDIO_MAL_DMA_PERIPH_DATA_SIZE DMA_PeripheralDataSize_HalfWord
- #define AUDIO_MAL_DMA_MEM_DATA_SIZE DMA_MemoryDataSize_HalfWord
- #define DMA_MAX_SZE 0xFFFF
-
-
- #define DAC_DHR12L1_ADDRESS 0x4000740C
- #define DAC_DHR12R1_ADDRESS 0x40007408
- #define DAC_DHR8R1_ADDRESS 0x40007410
- #define AUDIO_DAC_CHANNEL DAC_Channel_1
-
- /* I2S DMA Stream definitions */
- #define AUDIO_I2S_DMA_CLOCK RCC_AHB1Periph_DMA1
- #define AUDIO_I2S_DMA_STREAM DMA1_Stream7
- #define AUDIO_I2S_DMA_DREG CODEC_I2S_ADDRESS
- #define AUDIO_I2S_DMA_CHANNEL DMA_Channel_0
- #define AUDIO_I2S_DMA_IRQ DMA1_Stream7_IRQn
- #define AUDIO_I2S_DMA_FLAG_TC DMA_FLAG_TCIF7
- #define AUDIO_I2S_DMA_FLAG_HT DMA_FLAG_HTIF7
- #define AUDIO_I2S_DMA_FLAG_FE DMA_FLAG_FEIF7
- #define AUDIO_I2S_DMA_FLAG_TE DMA_FLAG_TEIF7
- #define AUDIO_I2S_DMA_FLAG_DME DMA_FLAG_DMEIF7
-
- #define Audio_MAL_I2S_IRQHandler DMA1_Stream7_IRQHandler
-
-
- /* DAC DMA Stream definitions */
- #define AUDIO_DAC_DMA_CLOCK RCC_AHB1Periph_DMA1
- #define AUDIO_DAC_DMA_STREAM DMA1_Stream0
- #define AUDIO_DAC_DMA_DREG DAC_DHR12L1_ADDRESS
- #define AUDIO_DAC_DMA_CHANNEL DMA_Channel_0
- #define AUDIO_DAC_DMA_IRQ DMA1_Stream0_IRQn
- #define AUDIO_DAC_DMA_FLAG_TC DMA_FLAG_TCIF0
- #define AUDIO_DAC_DMA_FLAG_HT DMA_FLAG_HTIF0
- #define AUDIO_DAC_DMA_FLAG_FE DMA_FLAG_FEIF0
- #define AUDIO_DAC_DMA_FLAG_TE DMA_FLAG_TEIF0
- #define AUDIO_DAC_DMA_FLAG_DME DMA_FLAG_DMEIF0
-
- #define Audio_MAL_DAC_IRQHandler DMA1_Stream0_IRQHandler
-
-
-/* I2C peripheral configuration defines (control interface of the audio codec) */
-#define CODEC_I2C I2C1
-#define CODEC_I2C_CLK RCC_APB1Periph_I2C1
-#define CODEC_I2C_GPIO_CLOCK RCC_AHB1Periph_GPIOB
-#define CODEC_I2C_GPIO_AF GPIO_AF_I2C1
-#define CODEC_I2C_GPIO GPIOB
-#define CODEC_I2C_SCL_PIN GPIO_Pin_6
-#define CODEC_I2C_SDA_PIN GPIO_Pin_9
-#define CODEC_I2S_SCL_PINSRC GPIO_PinSource6
-#define CODEC_I2S_SDA_PINSRC GPIO_PinSource9
-
-/* Maximum Timeout values for flags and events waiting loops. These timeouts are
- not based on accurate values, they just guarantee that the application will
- not remain stuck if the I2C communication is corrupted.
- You may modify these timeout values depending on CPU frequency and application
- conditions (interrupts routines ...). */
-#define CODEC_FLAG_TIMEOUT ((uint32_t)0x1000)
-#define CODEC_LONG_TIMEOUT ((uint32_t)(300 * CODEC_FLAG_TIMEOUT))
-/*----------------------------------------------------------------------------*/
-
-/*-----------------------------------
- Audio Codec User defines
- -----------------------------------------*/
-/* Audio interface : I2S or DAC */
-#define AUDIO_INTERFACE_I2S 1
-#define AUDIO_INTERFACE_DAC 2
-
-/* Codec output DEVICE */
-#define OUTPUT_DEVICE_SPEAKER 1
-#define OUTPUT_DEVICE_HEADPHONE 2
-#define OUTPUT_DEVICE_BOTH 3
-#define OUTPUT_DEVICE_AUTO 4
-
-/* Volume Levels values */
-#define DEFAULT_VOLMIN 0x00
-#define DEFAULT_VOLMAX 0xFF
-#define DEFAULT_VOLSTEP 0x04
-
-#define AUDIO_PAUSE 0
-#define AUDIO_RESUME 1
-
-/* Codec POWER DOWN modes */
-#define CODEC_PDWN_HW 1
-#define CODEC_PDWN_SW 2
-
-/* MUTE commands */
-#define AUDIO_MUTE_ON 1
-#define AUDIO_MUTE_OFF 0
-/*----------------------------------------------------------------------------*/
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Exported_Macros
- * @{
- */
-#define VOLUME_CONVERT(x) ((Volume > 100)? 100:((uint8_t)((Volume * 255) / 100)))
-#define DMA_MAX(x) (((x) <= DMA_MAX_SZE)? (x):DMA_MAX_SZE)
-
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Exported_Functions
- * @{
- */
-void EVAL_AUDIO_SetAudioInterface(uint32_t Interface);
-uint32_t EVAL_AUDIO_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq);
-uint32_t EVAL_AUDIO_DeInit(void);
-uint32_t EVAL_AUDIO_Play(uint16_t* pBuffer, uint32_t Size);
-uint32_t EVAL_AUDIO_PauseResume(uint32_t Cmd);
-uint32_t EVAL_AUDIO_Stop(uint32_t CodecPowerDown_Mode);
-uint32_t EVAL_AUDIO_VolumeCtl(uint8_t Volume);
-uint32_t EVAL_AUDIO_Mute(uint32_t Command);
-void DAC_Config(void);
-
-/* User Callbacks: user has to implement these functions in his code if
- they are needed. -----------------------------------------------------------*/
-
-uint16_t EVAL_AUDIO_GetSampleCallBack(void);
-
-/* This function is called when the requested data has been completely transferred.
- In Normal mode (when the define AUDIO_MAL_MODE_NORMAL is enabled) this function
- is called at the end of the whole audio file.
- In circular mode (when the define AUDIO_MAL_MODE_CIRCULAR is enabled) this
- function is called at the end of the current buffer transmission. */
-void EVAL_AUDIO_TransferComplete_CallBack(uint32_t pBuffer, uint32_t Size);
-
-/* This function is called when half of the requested buffer has been transferred
- This callback is useful in Circular mode only (when AUDIO_MAL_MODE_CIRCULAR
- define is enabled)*/
-void EVAL_AUDIO_HalfTransfer_CallBack(uint32_t pBuffer, uint32_t Size);
-
-/* This function is called when an Interrupt due to transfer error on or peripheral
- error occurs. */
-void EVAL_AUDIO_Error_CallBack(void* pData);
-
-/* Codec_TIMEOUT_UserCallback() function is called whenever a timeout condition
- occurs during communication (waiting on an event that doesn't occur, bus
- errors, busy devices ...) on the Codec control interface (I2C).
- You can use the default timeout callback implementation by uncommenting the
- define USE_DEFAULT_TIMEOUT_CALLBACK in stm32f4_discovery_audio_codec.h file.
- Typically the user implementation of this callback should reset I2C peripheral
- and re-initialize communication or in worst case reset all the application. */
-uint32_t Codec_TIMEOUT_UserCallback(void);
-
-#endif /* __STM32F4_DISCOVERY_AUDIOCODEC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4_discovery_lis302dl.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief This file provides a set of functions needed to manage the LIS302DL
- * MEMS accelerometer available on STM32F4-Discovery Kit.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4_discovery_lis302dl.h"
-//ADDED BY ME!!!!!!!!!!!!!!!!!!!!
-#include "stm32f4xx_conf.h"
-
-/** @addtogroup Utilities
- * @{
- */
-
-/** @addtogroup STM32F4_DISCOVERY
- * @{
- */
-
-/** @addtogroup STM32F4_DISCOVERY_LIS302DL
- * @{
- */
-
-
-/** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_Defines
- * @{
- */
-__IO uint32_t LIS302DLTimeout = LIS302DL_FLAG_TIMEOUT;
-
-/* Read/Write command */
-#define READWRITE_CMD ((uint8_t)0x80)
-/* Multiple byte read/write command */
-#define MULTIPLEBYTE_CMD ((uint8_t)0x40)
-/* Dummy Byte Send by the SPI Master device in order to generate the Clock to the Slave device */
-#define DUMMY_BYTE ((uint8_t)0x00)
-
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_FunctionPrototypes
- * @{
- */
-static uint8_t LIS302DL_SendByte(uint8_t byte);
-static void LIS302DL_LowLevel_Init(void);
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_Functions
- * @{
- */
-
-
-/**
- * @brief Set LIS302DL Initialization.
- * @param LIS302DL_Config_Struct: pointer to a LIS302DL_Config_TypeDef structure
- * that contains the configuration setting for the LIS302DL.
- * @retval None
- */
-void LIS302DL_Init(LIS302DL_InitTypeDef *LIS302DL_InitStruct)
-{
- uint8_t ctrl = 0x00;
-
- /* Configure the low level interface ---------------------------------------*/
- LIS302DL_LowLevel_Init();
-
- /* Configure MEMS: data rate, power mode, full scale, self test and axes */
- ctrl = (uint8_t) (LIS302DL_InitStruct->Output_DataRate | LIS302DL_InitStruct->Power_Mode | \
- LIS302DL_InitStruct->Full_Scale | LIS302DL_InitStruct->Self_Test | \
- LIS302DL_InitStruct->Axes_Enable);
-
- /* Write value to MEMS CTRL_REG1 regsister */
- LIS302DL_Write(&ctrl, LIS302DL_CTRL_REG1_ADDR, 1);
-}
-
-/**
- * @brief Set LIS302DL Internal High Pass Filter configuration.
- * @param LIS302DL_Filter_ConfigTypeDef: pointer to a LIS302DL_FilterConfig_TypeDef
- * structure that contains the configuration setting for the LIS302DL Filter.
- * @retval None
- */
-void LIS302DL_FilterConfig(LIS302DL_FilterConfigTypeDef *LIS302DL_FilterConfigStruct)
-{
- uint8_t ctrl = 0x00;
-
- /* Read CTRL_REG2 register */
- LIS302DL_Read(&ctrl, LIS302DL_CTRL_REG2_ADDR, 1);
-
- /* Clear high pass filter cut-off level, interrupt and data selection bits*/
- ctrl &= (uint8_t)~(LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER | \
- LIS302DL_HIGHPASSFILTER_LEVEL_3 | \
- LIS302DL_HIGHPASSFILTERINTERRUPT_1_2);
- /* Configure MEMS high pass filter cut-off level, interrupt and data selection bits */
- ctrl |= (uint8_t)(LIS302DL_FilterConfigStruct->HighPassFilter_Data_Selection | \
- LIS302DL_FilterConfigStruct->HighPassFilter_CutOff_Frequency | \
- LIS302DL_FilterConfigStruct->HighPassFilter_Interrupt);
-
- /* Write value to MEMS CTRL_REG2 register */
- LIS302DL_Write(&ctrl, LIS302DL_CTRL_REG2_ADDR, 1);
-}
-
-/**
- * @brief Set LIS302DL Interrupt configuration
- * @param LIS302DL_InterruptConfig_TypeDef: pointer to a LIS302DL_InterruptConfig_TypeDef
- * structure that contains the configuration setting for the LIS302DL Interrupt.
- * @retval None
- */
-void LIS302DL_InterruptConfig(LIS302DL_InterruptConfigTypeDef *LIS302DL_IntConfigStruct)
-{
- uint8_t ctrl = 0x00;
-
- /* Read CLICK_CFG register */
- LIS302DL_Read(&ctrl, LIS302DL_CLICK_CFG_REG_ADDR, 1);
-
- /* Configure latch Interrupt request, click interrupts and double click interrupts */
- ctrl = (uint8_t)(LIS302DL_IntConfigStruct->Latch_Request| \
- LIS302DL_IntConfigStruct->SingleClick_Axes | \
- LIS302DL_IntConfigStruct->DoubleClick_Axes);
-
- /* Write value to MEMS CLICK_CFG register */
- LIS302DL_Write(&ctrl, LIS302DL_CLICK_CFG_REG_ADDR, 1);
-}
-
-/**
- * @brief Change the lowpower mode for LIS302DL
- * @param LowPowerMode: new state for the lowpower mode.
- * This parameter can be one of the following values:
- * @arg LIS302DL_LOWPOWERMODE_POWERDOWN: Power down mode
- * @arg LIS302DL_LOWPOWERMODE_ACTIVE: Active mode
- * @retval None
- */
-void LIS302DL_LowpowerCmd(uint8_t LowPowerMode)
-{
- uint8_t tmpreg;
-
- /* Read CTRL_REG1 register */
- LIS302DL_Read(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1);
-
- /* Set new low power mode configuration */
- tmpreg &= (uint8_t)~LIS302DL_LOWPOWERMODE_ACTIVE;
- tmpreg |= LowPowerMode;
-
- /* Write value to MEMS CTRL_REG1 regsister */
- LIS302DL_Write(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1);
-}
-
-/**
- * @brief Data Rate command
- * @param DataRateValue: Data rate value
- * This parameter can be one of the following values:
- * @arg LIS302DL_DATARATE_100: 100 Hz output data rate
- * @arg LIS302DL_DATARATE_400: 400 Hz output data rate
- * @retval None
- */
-void LIS302DL_DataRateCmd(uint8_t DataRateValue)
-{
- uint8_t tmpreg;
-
- /* Read CTRL_REG1 register */
- LIS302DL_Read(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1);
-
- /* Set new Data rate configuration */
- tmpreg &= (uint8_t)~LIS302DL_DATARATE_400;
- tmpreg |= DataRateValue;
-
- /* Write value to MEMS CTRL_REG1 regsister */
- LIS302DL_Write(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1);
-}
-
-/**
- * @brief Change the Full Scale of LIS302DL
- * @param FS_value: new full scale value.
- * This parameter can be one of the following values:
- * @arg LIS302DL_FULLSCALE_2_3: +-2.3g
- * @arg LIS302DL_FULLSCALE_9_2: +-9.2g
- * @retval None
- */
-void LIS302DL_FullScaleCmd(uint8_t FS_value)
-{
- uint8_t tmpreg;
-
- /* Read CTRL_REG1 register */
- LIS302DL_Read(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1);
-
- /* Set new full scale configuration */
- tmpreg &= (uint8_t)~LIS302DL_FULLSCALE_9_2;
- tmpreg |= FS_value;
-
- /* Write value to MEMS CTRL_REG1 regsister */
- LIS302DL_Write(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1);
-}
-
-/**
- * @brief Reboot memory content of LIS302DL
- * @param None
- * @retval None
- */
-void LIS302DL_RebootCmd(void)
-{
- uint8_t tmpreg;
- /* Read CTRL_REG2 register */
- LIS302DL_Read(&tmpreg, LIS302DL_CTRL_REG2_ADDR, 1);
-
- /* Enable or Disable the reboot memory */
- tmpreg |= LIS302DL_BOOT_REBOOTMEMORY;
-
- /* Write value to MEMS CTRL_REG2 regsister */
- LIS302DL_Write(&tmpreg, LIS302DL_CTRL_REG2_ADDR, 1);
-}
-
-/**
- * @brief Writes one byte to the LIS302DL.
- * @param pBuffer : pointer to the buffer containing the data to be written to the LIS302DL.
- * @param WriteAddr : LIS302DL's internal address to write to.
- * @param NumByteToWrite: Number of bytes to write.
- * @retval None
- */
-void LIS302DL_Write(uint8_t* pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite)
-{
- /* Configure the MS bit:
- - When 0, the address will remain unchanged in multiple read/write commands.
- - When 1, the address will be auto incremented in multiple read/write commands.
- */
- if(NumByteToWrite > 0x01)
- {
- WriteAddr |= (uint8_t)MULTIPLEBYTE_CMD;
- }
- /* Set chip select Low at the start of the transmission */
- LIS302DL_CS_LOW();
-
- /* Send the Address of the indexed register */
- LIS302DL_SendByte(WriteAddr);
- /* Send the data that will be written into the device (MSB First) */
- while(NumByteToWrite >= 0x01)
- {
- LIS302DL_SendByte(*pBuffer);
- NumByteToWrite--;
- pBuffer++;
- }
-
- /* Set chip select High at the end of the transmission */
- LIS302DL_CS_HIGH();
-}
-
-/**
- * @brief Reads a block of data from the LIS302DL.
- * @param pBuffer : pointer to the buffer that receives the data read from the LIS302DL.
- * @param ReadAddr : LIS302DL's internal address to read from.
- * @param NumByteToRead : number of bytes to read from the LIS302DL.
- * @retval None
- */
-void LIS302DL_Read(uint8_t* pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead)
-{
- if(NumByteToRead > 0x01)
- {
- ReadAddr |= (uint8_t)(READWRITE_CMD | MULTIPLEBYTE_CMD);
- }
- else
- {
- ReadAddr |= (uint8_t)READWRITE_CMD;
- }
- /* Set chip select Low at the start of the transmission */
- LIS302DL_CS_LOW();
-
- /* Send the Address of the indexed register */
- LIS302DL_SendByte(ReadAddr);
-
- /* Receive the data that will be read from the device (MSB First) */
- while(NumByteToRead > 0x00)
- {
- /* Send dummy byte (0x00) to generate the SPI clock to LIS302DL (Slave device) */
- *pBuffer = LIS302DL_SendByte(DUMMY_BYTE);
- NumByteToRead--;
- pBuffer++;
- }
-
- /* Set chip select High at the end of the transmission */
- LIS302DL_CS_HIGH();
-}
-
-/**
- * @brief Read LIS302DL output register, and calculate the acceleration
- * ACC[mg]=SENSITIVITY* (out_h*256+out_l)/16 (12 bit rappresentation)
- * @param s16 buffer to store data
- * @retval None
- */
-void LIS302DL_ReadACC(int32_t* out)
-{
- uint8_t buffer[6];
- uint8_t crtl, i = 0x00;
-
- LIS302DL_Read(&crtl, LIS302DL_CTRL_REG1_ADDR, 1);
- LIS302DL_Read(buffer, LIS302DL_OUT_X_ADDR, 6);
-
- switch(crtl & 0x20)
- {
- /* FS bit = 0 ==> Sensitivity typical value = 18milligals/digit*/
- case 0x00:
- for(i=0; i<0x03; i++)
- {
- *out =(int32_t)(LIS302DL_SENSITIVITY_2_3G * (int8_t)buffer[2*i]);
- out++;
- }
- break;
- /* FS bit = 1 ==> Sensitivity typical value = 72milligals/digit*/
- case 0x20:
- for(i=0; i<0x03; i++)
- {
- *out =(int32_t)(LIS302DL_SENSITIVITY_9_2G * (int8_t)buffer[2*i]);
- out++;
- }
- break;
- default:
- break;
- }
- }
-
-/**
- * @brief Initializes the low level interface used to drive the LIS302DL
- * @param None
- * @retval None
- */
-static void LIS302DL_LowLevel_Init(void)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
- SPI_InitTypeDef SPI_InitStructure;
-
- /* Enable the SPI periph */
- RCC_APB2PeriphClockCmd(LIS302DL_SPI_CLK, ENABLE);
-
- /* Enable SCK, MOSI and MISO GPIO clocks */
- RCC_AHB1PeriphClockCmd(LIS302DL_SPI_SCK_GPIO_CLK | LIS302DL_SPI_MISO_GPIO_CLK | LIS302DL_SPI_MOSI_GPIO_CLK, ENABLE);
-
- /* Enable CS GPIO clock */
- RCC_AHB1PeriphClockCmd(LIS302DL_SPI_CS_GPIO_CLK, ENABLE);
-
- /* Enable INT1 GPIO clock */
- RCC_AHB1PeriphClockCmd(LIS302DL_SPI_INT1_GPIO_CLK, ENABLE);
-
- /* Enable INT2 GPIO clock */
- RCC_AHB1PeriphClockCmd(LIS302DL_SPI_INT2_GPIO_CLK, ENABLE);
-
- GPIO_PinAFConfig(LIS302DL_SPI_SCK_GPIO_PORT, LIS302DL_SPI_SCK_SOURCE, LIS302DL_SPI_SCK_AF);
- GPIO_PinAFConfig(LIS302DL_SPI_MISO_GPIO_PORT, LIS302DL_SPI_MISO_SOURCE, LIS302DL_SPI_MISO_AF);
- GPIO_PinAFConfig(LIS302DL_SPI_MOSI_GPIO_PORT, LIS302DL_SPI_MOSI_SOURCE, LIS302DL_SPI_MOSI_AF);
-
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
- /* SPI SCK pin configuration */
- GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_SCK_PIN;
- GPIO_Init(LIS302DL_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
- /* SPI MOSI pin configuration */
- GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_MOSI_PIN;
- GPIO_Init(LIS302DL_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
- /* SPI MISO pin configuration */
- GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_MISO_PIN;
- GPIO_Init(LIS302DL_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-
- /* SPI configuration -------------------------------------------------------*/
- SPI_I2S_DeInit(LIS302DL_SPI);
- SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
- SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
- SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
- SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
- SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
- SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
- SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
- SPI_InitStructure.SPI_CRCPolynomial = 7;
- SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
- SPI_Init(LIS302DL_SPI, &SPI_InitStructure);
-
- /* Enable SPI1 */
- SPI_Cmd(LIS302DL_SPI, ENABLE);
-
- /* Configure GPIO PIN for Lis Chip select */
- GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_CS_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(LIS302DL_SPI_CS_GPIO_PORT, &GPIO_InitStructure);
-
- /* Deselect : Chip Select high */
- GPIO_SetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN);
-
- /* Configure GPIO PINs to detect Interrupts */
- GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_INT1_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_Init(LIS302DL_SPI_INT1_GPIO_PORT, &GPIO_InitStructure);
-
- GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_INT2_PIN;
- GPIO_Init(LIS302DL_SPI_INT2_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
- * @brief Sends a Byte through the SPI interface and return the Byte received
- * from the SPI bus.
- * @param Byte : Byte send.
- * @retval The received byte value
- */
-static uint8_t LIS302DL_SendByte(uint8_t byte)
-{
- /* Loop while DR register in not emplty */
- LIS302DLTimeout = LIS302DL_FLAG_TIMEOUT;
- while (SPI_I2S_GetFlagStatus(LIS302DL_SPI, SPI_I2S_FLAG_TXE) == RESET)
- {
- if((LIS302DLTimeout--) == 0) return LIS302DL_TIMEOUT_UserCallback();
- }
-
- /* Send a Byte through the SPI peripheral */
- SPI_I2S_SendData(LIS302DL_SPI, byte);
-
- /* Wait to receive a Byte */
- LIS302DLTimeout = LIS302DL_FLAG_TIMEOUT;
- while (SPI_I2S_GetFlagStatus(LIS302DL_SPI, SPI_I2S_FLAG_RXNE) == RESET)
- {
- if((LIS302DLTimeout--) == 0) return LIS302DL_TIMEOUT_UserCallback();
- }
-
- /* Return the Byte read from the SPI bus */
- return (uint8_t)SPI_I2S_ReceiveData(LIS302DL_SPI);
-}
-
-#ifdef USE_DEFAULT_TIMEOUT_CALLBACK
-/**
- * @brief Basic management of the timeout situation.
- * @param None.
- * @retval None.
- */
-uint32_t LIS302DL_TIMEOUT_UserCallback(void)
-{
- /* Block communication and all processes */
- while (1)
- {
- }
-}
-#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/**
- ******************************************************************************
- * @file stm32f4_discovery_lis302dl.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 19-September-2011
- * @brief This file contains all the functions prototypes for the stm32f4_discovery_lis302dl.c
- * firmware driver.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4_DISCOVERY_LIS302DL_H
-#define __STM32F4_DISCOVERY_LIS302DL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
- #include "stm32f4xx.h"
-
-/** @addtogroup Utilities
- * @{
- */
-
-/** @addtogroup STM32F4_DISCOVERY
- * @{
- */
-
-/** @addtogroup STM32F4_DISCOVERY_LIS302DL
- * @{
- */
-
-
-/** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Types
- * @{
- */
-
-/* LIS302DL struct */
-typedef struct
-{
- uint8_t Power_Mode; /* Power-down/Active Mode */
- uint8_t Output_DataRate; /* OUT data rate 100 Hz / 400 Hz */
- uint8_t Axes_Enable; /* Axes enable */
- uint8_t Full_Scale; /* Full scale */
- uint8_t Self_Test; /* Self test */
-}LIS302DL_InitTypeDef;
-
-/* LIS302DL High Pass Filter struct */
-typedef struct
-{
- uint8_t HighPassFilter_Data_Selection; /* Internal filter bypassed or data from internal filter send to output register*/
- uint8_t HighPassFilter_CutOff_Frequency; /* High pass filter cut-off frequency */
- uint8_t HighPassFilter_Interrupt; /* High pass filter enabled for Freefall/WakeUp #1 or #2 */
-}LIS302DL_FilterConfigTypeDef;
-
-/* LIS302DL Interrupt struct */
-typedef struct
-{
- uint8_t Latch_Request; /* Latch interrupt request into CLICK_SRC register*/
- uint8_t SingleClick_Axes; /* Single Click Axes Interrupts */
- uint8_t DoubleClick_Axes; /* Double Click Axes Interrupts */
-}LIS302DL_InterruptConfigTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Constants
- * @{
- */
-
-/* Uncomment the following line to use the default LIS302DL_TIMEOUT_UserCallback()
- function implemented in stm32f4_discovery_lis302dl.c file.
- LIS302DL_TIMEOUT_UserCallback() function is called whenever a timeout condition
- occure during communication (waiting transmit data register empty flag(TXE)
- or waiting receive data register is not empty flag (RXNE)). */
-/* #define USE_DEFAULT_TIMEOUT_CALLBACK */
-
-/* Maximum Timeout values for flags waiting loops. These timeouts are not based
- on accurate values, they just guarantee that the application will not remain
- stuck if the SPI communication is corrupted.
- You may modify these timeout values depending on CPU frequency and application
- conditions (interrupts routines ...). */
-#define LIS302DL_FLAG_TIMEOUT ((uint32_t)0x1000)
-
-/**
- * @brief LIS302DL SPI Interface pins
- */
-#define LIS302DL_SPI SPI1
-#define LIS302DL_SPI_CLK RCC_APB2Periph_SPI1
-
-#define LIS302DL_SPI_SCK_PIN GPIO_Pin_5 /* PA.05 */
-#define LIS302DL_SPI_SCK_GPIO_PORT GPIOA /* GPIOA */
-#define LIS302DL_SPI_SCK_GPIO_CLK RCC_AHB1Periph_GPIOA
-#define LIS302DL_SPI_SCK_SOURCE GPIO_PinSource5
-#define LIS302DL_SPI_SCK_AF GPIO_AF_SPI1
-
-#define LIS302DL_SPI_MISO_PIN GPIO_Pin_6 /* PA.6 */
-#define LIS302DL_SPI_MISO_GPIO_PORT GPIOA /* GPIOA */
-#define LIS302DL_SPI_MISO_GPIO_CLK RCC_AHB1Periph_GPIOA
-#define LIS302DL_SPI_MISO_SOURCE GPIO_PinSource6
-#define LIS302DL_SPI_MISO_AF GPIO_AF_SPI1
-
-#define LIS302DL_SPI_MOSI_PIN GPIO_Pin_7 /* PA.7 */
-#define LIS302DL_SPI_MOSI_GPIO_PORT GPIOA /* GPIOA */
-#define LIS302DL_SPI_MOSI_GPIO_CLK RCC_AHB1Periph_GPIOA
-#define LIS302DL_SPI_MOSI_SOURCE GPIO_PinSource7
-#define LIS302DL_SPI_MOSI_AF GPIO_AF_SPI1
-
-#define LIS302DL_SPI_CS_PIN GPIO_Pin_3 /* PE.03 */
-#define LIS302DL_SPI_CS_GPIO_PORT GPIOE /* GPIOE */
-#define LIS302DL_SPI_CS_GPIO_CLK RCC_AHB1Periph_GPIOE
-
-#define LIS302DL_SPI_INT1_PIN GPIO_Pin_0 /* PE.00 */
-#define LIS302DL_SPI_INT1_GPIO_PORT GPIOE /* GPIOE */
-#define LIS302DL_SPI_INT1_GPIO_CLK RCC_AHB1Periph_GPIOE
-#define LIS302DL_SPI_INT1_EXTI_LINE EXTI_Line0
-#define LIS302DL_SPI_INT1_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
-#define LIS302DL_SPI_INT1_EXTI_PIN_SOURCE EXTI_PinSource0
-#define LIS302DL_SPI_INT1_EXTI_IRQn EXTI0_IRQn
-
-#define LIS302DL_SPI_INT2_PIN GPIO_Pin_1 /* PE.01 */
-#define LIS302DL_SPI_INT2_GPIO_PORT GPIOE /* GPIOE */
-#define LIS302DL_SPI_INT2_GPIO_CLK RCC_AHB1Periph_GPIOE
-#define LIS302DL_SPI_INT2_EXTI_LINE EXTI_Line1
-#define LIS302DL_SPI_INT2_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
-#define LIS302DL_SPI_INT2_EXTI_PIN_SOURCE EXTI_PinSource1
-#define LIS302DL_SPI_INT2_EXTI_IRQn EXTI1_IRQn
-
-
-/******************************************************************************/
-/*************************** START REGISTER MAPPING **************************/
-/******************************************************************************/
-
-/*******************************************************************************
-* WHO_AM_I Register: Device Identification Register
-* Read only register
-* Default value: 0x3B
-*******************************************************************************/
-#define LIS302DL_WHO_AM_I_ADDR 0x0F
-
-/*******************************************************************************
-* CTRL_REG1 Register: Control Register 1
-* Read Write register
-* Default value: 0x07
-* 7 DR: Data Rate selection.
-* 0 - 100 Hz output data rate
-* 1 - 400 Hz output data rate
-* 6 PD: Power Down control.
-* 0 - power down mode
-* 1 - active mode
-* 5 FS: Full Scale selection.
-* 0 - Typical measurement range 2.3
-* 1 - Typical measurement range 9.2
-* 4:3 STP-STM Self Test Enable:
-* STP | STM | mode
-* ----------------------------
-* 0 | 0 | Normal mode
-* 0 | 1 | Self Test M
-* 1 | 0 | Self Test P
-* 2 Zen: Z axis enable.
-* 0 - Z axis disabled
-* 1- Z axis enabled
-* 1 Yen: Y axis enable.
-* 0 - Y axis disabled
-* 1- Y axis enabled
-* 0 Xen: X axis enable.
-* 0 - X axis disabled
-* 1- X axis enabled
-********************************************************************************/
-#define LIS302DL_CTRL_REG1_ADDR 0x20
-
-/*******************************************************************************
-* CTRL_REG2 Regsiter: Control Register 2
-* Read Write register
-* Default value: 0x00
-* 7 SIM: SPI Serial Interface Mode Selection.
-* 0 - 4 wire interface
-* 1 - 3 wire interface
-* 6 BOOT: Reboot memory content
-* 0 - normal mode
-* 1 - reboot memory content
-* 5 Reserved
-* 4 FDS: Filtered data selection.
-* 0 - internal filter bypassed
-* 1 - data from internal filter sent to output register
-* 3 HP FF_WU2: High pass filter enabled for FreeFall/WakeUp#2.
-* 0 - filter bypassed
-* 1 - filter enabled
-* 2 HP FF_WU1: High pass filter enabled for FreeFall/WakeUp#1.
-* 0 - filter bypassed
-* 1 - filter enabled
-* 1:0 HP coeff2-HP coeff1 High pass filter cut-off frequency (ft) configuration.
-* ft= ODR[hz]/6*HP coeff
-* HP coeff2 | HP coeff1 | HP coeff
-* -------------------------------------------
-* 0 | 0 | 8
-* 0 | 1 | 16
-* 1 | 0 | 32
-* 1 | 1 | 64
-* HP coeff | ft[hz] | ft[hz] |
-* |ODR 100Hz | ODR 400Hz |
-* --------------------------------------------
-* 00 | 2 | 8 |
-* 01 | 1 | 4 |
-* 10 | 0.5 | 2 |
-* 11 | 0.25 | 1 |
-*******************************************************************************/
-#define LIS302DL_CTRL_REG2_ADDR 0x21
-
-/*******************************************************************************
-* CTRL_REG3 Register: Interrupt Control Register
-* Read Write register
-* Default value: 0x00
-* 7 IHL active: Interrupt active high/low.
-* 0 - active high
-* 1 - active low
-* 6 PP_OD: push-pull/open-drain.
-* 0 - push-pull
-* 1 - open-drain
-* 5:3 I2_CFG2 - I2_CFG0 Data signal on INT2 pad control bits
-* 2:0 I1_CFG2 - I1_CFG0 Data signal on INT1 pad control bits
-* I1(2)_CFG2 | I1(2)_CFG1 | I1(2)_CFG0 | INT1(2) Pad
-* ----------------------------------------------------------
-* 0 | 0 | 0 | GND
-* 0 | 0 | 1 | FreeFall/WakeUp#1
-* 0 | 1 | 0 | FreeFall/WakeUp#2
-* 0 | 1 | 1 | FreeFall/WakeUp#1 or FreeFall/WakeUp#2
-* 1 | 0 | 0 | Data ready
-* 1 | 1 | 1 | Click interrupt
-*******************************************************************************/
-#define LIS302DL_CTRL_REG3_ADDR 0x22
-
-/*******************************************************************************
-* HP_FILTER_RESET Register: Dummy register. Reading at this address zeroes
-* instantaneously the content of the internal high pass filter. If the high pass
-* filter is enabled all three axes are instantaneously set to 0g.
-* This allows to overcome the settling time of the high pass filter.
-* Read only register
-* Default value: Dummy
-*******************************************************************************/
-#define LIS302DL_HP_FILTER_RESET_REG_ADDR 0x23
-
-/*******************************************************************************
-* STATUS_REG Register: Status Register
-* Default value: 0x00
-* 7 ZYXOR: X, Y and Z axis data overrun.
-* 0: no overrun has occurred
-* 1: new data has overwritten the previous one before it was read
-* 6 ZOR: Z axis data overrun.
-* 0: no overrun has occurred
-* 1: new data for Z-axis has overwritten the previous one before it was read
-* 5 yOR: y axis data overrun.
-* 0: no overrun has occurred
-* 1: new data for y-axis has overwritten the previous one before it was read
-* 4 XOR: X axis data overrun.
-* 0: no overrun has occurred
-* 1: new data for X-axis has overwritten the previous one before it was read
-* 3 ZYXDA: X, Y and Z axis new data available
-* 0: a new set of data is not yet available
-* 1: a new set of data is available
-* 2 ZDA: Z axis new data available.
-* 0: a new set of data is not yet available
-* 1: a new data for Z axis is available
-* 1 YDA: Y axis new data available
-* 0: a new set of data is not yet available
-* 1: a new data for Y axis is available
-* 0 XDA: X axis new data available
-* 0: a new set of data is not yet available
-* 1: a new data for X axis is available
-*******************************************************************************/
-#define LIS302DL_STATUS_REG_ADDR 0x27
-
-/*******************************************************************************
-* OUT_X Register: X-axis output Data
-* Read only register
-* Default value: output
-* 7:0 XD7-XD0: X-axis output Data
-*******************************************************************************/
-#define LIS302DL_OUT_X_ADDR 0x29
-
-/*******************************************************************************
-* OUT_Y Register: Y-axis output Data
-* Read only register
-* Default value: output
-* 7:0 YD7-YD0: Y-axis output Data
-*******************************************************************************/
-#define LIS302DL_OUT_Y_ADDR 0x2B
-
-/*******************************************************************************
-* OUT_Z Register: Z-axis output Data
-* Read only register
-* Default value: output
-* 7:0 ZD7-ZD0: Z-axis output Data
-*******************************************************************************/
-#define LIS302DL_OUT_Z_ADDR 0x2D
-
-/*******************************************************************************
-* FF_WW_CFG_1 Register: Configuration register for Interrupt 1 source.
-* Read write register
-* Default value: 0x00
-* 7 AOI: AND/OR combination of Interrupt events.
-* 0: OR combination of interrupt events
-* 1: AND combination of interrupt events
-* 6 LIR: Latch/not latch interrupt request
-* 0: interrupt request not latched
-* 1: interrupt request latched
-* 5 ZHIE: Enable interrupt generation on Z high event.
-* 0: disable interrupt request
-* 1: enable interrupt request on measured accel. value higher than preset threshold
-* 4 ZLIE: Enable interrupt generation on Z low event.
-* 0: disable interrupt request
-* 1: enable interrupt request on measured accel. value lower than preset threshold
-* 3 YHIE: Enable interrupt generation on Y high event.
-* 0: disable interrupt request
-* 1: enable interrupt request on measured accel. value higher than preset threshold
-* 2 YLIE: Enable interrupt generation on Y low event.
-* 0: disable interrupt request
-* 1: enable interrupt request on measured accel. value lower than preset threshold
-* 1 XHIE: Enable interrupt generation on X high event.
-* 0: disable interrupt request
-* 1: enable interrupt request on measured accel. value higher than preset threshold
-* 0 XLIE: Enable interrupt generation on X low event.
-* 0: disable interrupt request
-* 1: enable interrupt request on measured accel. value lower than preset threshold
-*******************************************************************************/
-#define LIS302DL_FF_WU_CFG1_REG_ADDR 0x30
-
-/*******************************************************************************
-* FF_WU_SRC_1 Register: Interrupt 1 source register.
-* Reading at this address clears FF_WU_SRC_1 register and the FF, WU 1 interrupt
-* and allow the refreshment of data in the FF_WU_SRC_1 register if the latched option
-* was chosen.
-* Read only register
-* Default value: 0x00
-* 7 Reserved
-* 6 IA: Interrupt active.
-* 0: no interrupt has been generated
-* 1: one or more interrupts have been generated
-* 5 ZH: Z high.
-* 0: no interrupt
-* 1: ZH event has occurred
-* 4 ZL: Z low.
-* 0: no interrupt
-* 1: ZL event has occurred
-* 3 YH: Y high.
-* 0: no interrupt
-* 1: YH event has occurred
-* 2 YL: Y low.
-* 0: no interrupt
-* 1: YL event has occurred
-* 1 YH: X high.
-* 0: no interrupt
-* 1: XH event has occurred
-* 0 YL: X low.
-* 0: no interrupt
-* 1: XL event has occurred
-*******************************************************************************/
-#define LIS302DL_FF_WU_SRC1_REG_ADDR 0x31
-
-/*******************************************************************************
-* FF_WU_THS_1 Register: Threshold register
-* Read Write register
-* Default value: 0x00
-* 7 DCRM: Reset mode selection.
-* 0 - counter resetted
-* 1 - counter decremented
-* 6 THS6-THS0: Free-fall/wake-up threshold value.
-*******************************************************************************/
-#define LIS302DL_FF_WU_THS1_REG_ADDR 0x32
-
-/*******************************************************************************
-* FF_WU_DURATION_1 Register: duration Register
-* Read Write register
-* Default value: 0x00
-* 7:0 D7-D0 Duration value. (Duration steps and maximum values depend on the ODR chosen)
- ******************************************************************************/
-#define LIS302DL_FF_WU_DURATION1_REG_ADDR 0x33
-
-/*******************************************************************************
-* FF_WW_CFG_2 Register: Configuration register for Interrupt 2 source.
-* Read write register
-* Default value: 0x00
-* 7 AOI: AND/OR combination of Interrupt events.
-* 0: OR combination of interrupt events
-* 1: AND combination of interrupt events
-* 6 LIR: Latch/not latch interrupt request
-* 0: interrupt request not latched
-* 1: interrupt request latched
-* 5 ZHIE: Enable interrupt generation on Z high event.
-* 0: disable interrupt request
-* 1: enable interrupt request on measured accel. value higher than preset threshold
-* 4 ZLIE: Enable interrupt generation on Z low event.
-* 0: disable interrupt request
-* 1: enable interrupt request on measured accel. value lower than preset threshold
-* 3 YHIE: Enable interrupt generation on Y high event.
-* 0: disable interrupt request
-* 1: enable interrupt request on measured accel. value higher than preset threshold
-* 2 YLIE: Enable interrupt generation on Y low event.
-* 0: disable interrupt request
-* 1: enable interrupt request on measured accel. value lower than preset threshold
-* 1 XHIE: Enable interrupt generation on X high event.
-* 0: disable interrupt request
-* 1: enable interrupt request on measured accel. value higher than preset threshold
-* 0 XLIE: Enable interrupt generation on X low event.
-* 0: disable interrupt request
-* 1: enable interrupt request on measured accel. value lower than preset threshold
-*******************************************************************************/
-#define LIS302DL_FF_WU_CFG2_REG_ADDR 0x34
-
-/*******************************************************************************
-* FF_WU_SRC_2 Register: Interrupt 2 source register.
-* Reading at this address clears FF_WU_SRC_2 register and the FF, WU 2 interrupt
-* and allow the refreshment of data in the FF_WU_SRC_2 register if the latched option
-* was chosen.
-* Read only register
-* Default value: 0x00
-* 7 Reserved
-* 6 IA: Interrupt active.
-* 0: no interrupt has been generated
-* 1: one or more interrupts have been generated
-* 5 ZH: Z high.
-* 0: no interrupt
-* 1: ZH event has occurred
-* 4 ZL: Z low.
-* 0: no interrupt
-* 1: ZL event has occurred
-* 3 YH: Y high.
-* 0: no interrupt
-* 1: YH event has occurred
-* 2 YL: Y low.
-* 0: no interrupt
-* 1: YL event has occurred
-* 1 YH: X high.
-* 0: no interrupt
-* 1: XH event has occurred
-* 0 YL: X low.
-* 0: no interrupt
-* 1: XL event has occurred
-*******************************************************************************/
-#define LIS302DL_FF_WU_SRC2_REG_ADDR 0x35
-
-/*******************************************************************************
-* FF_WU_THS_2 Register: Threshold register
-* Read Write register
-* Default value: 0x00
-* 7 DCRM: Reset mode selection.
-* 0 - counter resetted
-* 1 - counter decremented
-* 6 THS6-THS0: Free-fall/wake-up threshold value.
-*******************************************************************************/
-#define LIS302DL_FF_WU_THS2_REG_ADDR 0x36
-
-/*******************************************************************************
-* FF_WU_DURATION_2 Register: duration Register
-* Read Write register
-* Default value: 0x00
-* 7:0 D7-D0 Duration value. (Duration steps and maximum values depend on the ODR chosen)
- ******************************************************************************/
-#define LIS302DL_FF_WU_DURATION2_REG_ADDR 0x37
-
-/******************************************************************************
-* CLICK_CFG Register: click Register
-* Read Write register
-* Default value: 0x00
-* 7 Reserved
-* 6 LIR: Latch Interrupt request.
-* 0: interrupt request not latched
-* 1: interrupt request latched
-* 5 Double_Z: Enable interrupt generation on double click event on Z axis.
-* 0: disable interrupt request
-* 1: enable interrupt request
-* 4 Single_Z: Enable interrupt generation on single click event on Z axis.
-* 0: disable interrupt request
-* 1: enable interrupt request
-* 3 Double_Y: Enable interrupt generation on double click event on Y axis.
-* 0: disable interrupt request
-* 1: enable interrupt request
-* 2 Single_Y: Enable interrupt generation on single click event on Y axis.
-* 0: disable interrupt request
-* 1: enable interrupt request
-* 1 Double_X: Enable interrupt generation on double click event on X axis.
-* 0: disable interrupt request
-* 1: enable interrupt request
-* 0 Single_y: Enable interrupt generation on single click event on X axis.
-* 0: disable interrupt request
-* 1: enable interrupt request
- ******************************************************************************/
-#define LIS302DL_CLICK_CFG_REG_ADDR 0x38
-
-/******************************************************************************
-* CLICK_SRC Register: click status Register
-* Read only register
-* Default value: 0x00
-* 7 Reserved
-* 6 IA: Interrupt active.
-* 0: no interrupt has been generated
-* 1: one or more interrupts have been generated
-* 5 Double_Z: Double click on Z axis event.
-* 0: no interrupt
-* 1: Double Z event has occurred
-* 4 Single_Z: Z low.
-* 0: no interrupt
-* 1: Single Z event has occurred
-* 3 Double_Y: Y high.
-* 0: no interrupt
-* 1: Double Y event has occurred
-* 2 Single_Y: Y low.
-* 0: no interrupt
-* 1: Single Y event has occurred
-* 1 Double_X: X high.
-* 0: no interrupt
-* 1: Double X event has occurred
-* 0 Single_X: X low.
-* 0: no interrupt
-* 1: Single X event has occurred
-*******************************************************************************/
-#define LIS302DL_CLICK_SRC_REG_ADDR 0x39
-
-/*******************************************************************************
-* CLICK_THSY_X Register: Click threshold Y and X register
-* Read Write register
-* Default value: 0x00
-* 7:4 THSy3-THSy0: Click threshold on Y axis, step 0.5g
-* 3:0 THSx3-THSx0: Click threshold on X axis, step 0.5g
-*******************************************************************************/
-#define LIS302DL_CLICK_THSY_X_REG_ADDR 0x3B
-
-/*******************************************************************************
-* CLICK_THSZ Register: Click threshold Z register
-* Read Write register
-* Default value: 0x00
-* 7:4 Reserved
-* 3:0 THSz3-THSz0: Click threshold on Z axis, step 0.5g
-*******************************************************************************/
-#define LIS302DL_CLICK_THSZ_REG_ADDR 0x3C
-
-/*******************************************************************************
-* CLICK_TimeLimit Register: Time Limit register
-* Read Write register
-* Default value: 0x00
-* 7:0 Dur7-Dur0: Time Limit value, step 0.5g
-*******************************************************************************/
-#define LIS302DL_CLICK_TIMELIMIT_REG_ADDR 0x3D
-
-/*******************************************************************************
-* CLICK_Latency Register: Latency register
-* Read Write register
-* Default value: 0x00
-* 7:0 Lat7-Lat0: Latency value, step 1msec
-*******************************************************************************/
-#define LIS302DL_CLICK_LATENCY_REG_ADDR 0x3E
-
-/*******************************************************************************
-* CLICK_Window Register: Window register
-* Read Write register
-* Default value: 0x00
-* 7:0 Win7-Win0: Window value, step 1msec
-*******************************************************************************/
-#define LIS302DL_CLICK_WINDOW_REG_ADDR 0x3F
-
-/******************************************************************************/
-/**************************** END REGISTER MAPPING ***************************/
-/******************************************************************************/
-
-#define LIS302DL_SENSITIVITY_2_3G 18 /* 18 mg/digit*/
-#define LIS302DL_SENSITIVITY_9_2G 72 /* 72 mg/digit*/
-
-/** @defgroup Data_Rate_selection
- * @{
- */
-#define LIS302DL_DATARATE_100 ((uint8_t)0x00)
-#define LIS302DL_DATARATE_400 ((uint8_t)0x80)
-/**
- * @}
- */
-
-/** @defgroup Power_Mode_selection
- * @{
- */
-#define LIS302DL_LOWPOWERMODE_POWERDOWN ((uint8_t)0x00)
-#define LIS302DL_LOWPOWERMODE_ACTIVE ((uint8_t)0x40)
-/**
- * @}
- */
-
-/** @defgroup Full_Scale_selection
- * @{
- */
-#define LIS302DL_FULLSCALE_2_3 ((uint8_t)0x00)
-#define LIS302DL_FULLSCALE_9_2 ((uint8_t)0x20)
-/**
- * @}
- */
-
-/** @defgroup Self_Test_selection
- * @{
- */
-#define LIS302DL_SELFTEST_NORMAL ((uint8_t)0x00)
-#define LIS302DL_SELFTEST_P ((uint8_t)0x10)
-#define LIS302DL_SELFTEST_M ((uint8_t)0x08)
-/**
- * @}
- */
-
-/** @defgroup Direction_XYZ_selection
- * @{
- */
-#define LIS302DL_X_ENABLE ((uint8_t)0x01)
-#define LIS302DL_Y_ENABLE ((uint8_t)0x02)
-#define LIS302DL_Z_ENABLE ((uint8_t)0x04)
-#define LIS302DL_XYZ_ENABLE ((uint8_t)0x07)
-/**
- * @}
- */
-
- /** @defgroup SPI_Serial_Interface_Mode_selection
- * @{
- */
-#define LIS302DL_SERIALINTERFACE_4WIRE ((uint8_t)0x00)
-#define LIS302DL_SERIALINTERFACE_3WIRE ((uint8_t)0x80)
-/**
- * @}
- */
-
- /** @defgroup Boot_Mode_selection
- * @{
- */
-#define LIS302DL_BOOT_NORMALMODE ((uint8_t)0x00)
-#define LIS302DL_BOOT_REBOOTMEMORY ((uint8_t)0x40)
-/**
- * @}
- */
-
- /** @defgroup Filtered_Data_Selection_Mode_selection
- * @{
- */
-#define LIS302DL_FILTEREDDATASELECTION_BYPASSED ((uint8_t)0x00)
-#define LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER ((uint8_t)0x20)
-/**
- * @}
- */
-
- /** @defgroup High_Pass_Filter_Interrupt_selection
- * @{
- */
-#define LIS302DL_HIGHPASSFILTERINTERRUPT_OFF ((uint8_t)0x00)
-#define LIS302DL_HIGHPASSFILTERINTERRUPT_1 ((uint8_t)0x04)
-#define LIS302DL_HIGHPASSFILTERINTERRUPT_2 ((uint8_t)0x08)
-#define LIS302DL_HIGHPASSFILTERINTERRUPT_1_2 ((uint8_t)0x0C)
-/**
- * @}
- */
-
- /** @defgroup High_Pass_Filter_selection
- * @{
- */
-#define LIS302DL_HIGHPASSFILTER_LEVEL_0 ((uint8_t)0x00)
-#define LIS302DL_HIGHPASSFILTER_LEVEL_1 ((uint8_t)0x01)
-#define LIS302DL_HIGHPASSFILTER_LEVEL_2 ((uint8_t)0x02)
-#define LIS302DL_HIGHPASSFILTER_LEVEL_3 ((uint8_t)0x03)
-/**
- * @}
- */
-
-
-/** @defgroup latch_Interrupt_Request_selection
- * @{
- */
-#define LIS302DL_INTERRUPTREQUEST_NOTLATCHED ((uint8_t)0x00)
-#define LIS302DL_INTERRUPTREQUEST_LATCHED ((uint8_t)0x40)
-/**
- * @}
- */
-
-/** @defgroup Click_Interrupt_XYZ_selection
- * @{
- */
-#define LIS302DL_CLICKINTERRUPT_XYZ_DISABLE ((uint8_t)0x00)
-#define LIS302DL_CLICKINTERRUPT_X_ENABLE ((uint8_t)0x01)
-#define LIS302DL_CLICKINTERRUPT_Y_ENABLE ((uint8_t)0x04)
-#define LIS302DL_CLICKINTERRUPT_Z_ENABLE ((uint8_t)0x10)
-#define LIS302DL_CLICKINTERRUPT_XYZ_ENABLE ((uint8_t)0x15)
-/**
- * @}
- */
-
-/** @defgroup Double_Click_Interrupt_XYZ_selection
- * @{
- */
-#define LIS302DL_DOUBLECLICKINTERRUPT_XYZ_DISABLE ((uint8_t)0x00)
-#define LIS302DL_DOUBLECLICKINTERRUPT_X_ENABLE ((uint8_t)0x02)
-#define LIS302DL_DOUBLECLICKINTERRUPT_Y_ENABLE ((uint8_t)0x08)
-#define LIS302DL_DOUBLECLICKINTERRUPT_Z_ENABLE ((uint8_t)0x20)
-#define LIS302DL_DOUBLECLICKINTERRUPT_XYZ_ENABLE ((uint8_t)0x2A)
-/**
- * @}
- */
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Macros
- * @{
- */
-#define LIS302DL_CS_LOW() GPIO_ResetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN)
-#define LIS302DL_CS_HIGH() GPIO_SetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN)
-/**
- * @}
- */
-
-/** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Functions
- * @{
- */
-void LIS302DL_Init(LIS302DL_InitTypeDef *LIS302DL_InitStruct);
-void LIS302DL_InterruptConfig(LIS302DL_InterruptConfigTypeDef *LIS302DL_InterruptConfigStruct);
-void LIS302DL_FilterConfig(LIS302DL_FilterConfigTypeDef *LIS302DL_FilterConfigStruct);
-void LIS302DL_LowpowerCmd(uint8_t LowPowerMode);
-void LIS302DL_FullScaleCmd(uint8_t FS_value);
-void LIS302DL_DataRateCmd(uint8_t DataRateValue);
-void LIS302DL_RebootCmd(void);
-void LIS302DL_ReadACC(int32_t* out);
-void LIS302DL_Write(uint8_t* pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite);
-void LIS302DL_Read(uint8_t* pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead);
-
-/* USER Callbacks: This is function for which prototype only is declared in
- MEMS accelerometre driver and that should be implemented into user applicaiton. */
-/* LIS302DL_TIMEOUT_UserCallback() function is called whenever a timeout condition
- occure during communication (waiting transmit data register empty flag(TXE)
- or waiting receive data register is not empty flag (RXNE)).
- You can use the default timeout callback implementation by uncommenting the
- define USE_DEFAULT_TIMEOUT_CALLBACK in stm32f4_discovery_lis302dl.h file.
- Typically the user implementation of this callback should reset MEMS peripheral
- and re-initialize communication or in worst case reset all the application. */
-uint32_t LIS302DL_TIMEOUT_UserCallback(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4_DISCOVERY_LIS302DL_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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