--- /dev/null
+/*-------------------------------------------------------------------------
+ Register Declarations for the Cygnal C8051F000-C8051F017 Processor Range
+
+ Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------*/
+
+#ifndef C8051F000_H
+#define C8051F000_H
+
+
+/* BYTE Registers */
+sfr at 0x80 P0 ; /* PORT 0 */
+sfr at 0x81 SP ; /* STACK POINTER */
+sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
+sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
+sfr at 0x87 PCON ; /* POWER CONTROL */
+sfr at 0x88 TCON ; /* TIMER CONTROL */
+sfr at 0x89 TMOD ; /* TIMER MODE */
+sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
+sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
+sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
+sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
+sfr at 0x8E CKCON ; /* CLOCK CONTROL */
+sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
+sfr at 0x90 P1 ; /* PORT 1 */
+sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */
+sfr at 0x92 TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
+sfr at 0x93 TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
+sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */
+sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */
+sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */
+sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */
+sfr at 0x9A SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
+sfr at 0x9B SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
+sfr at 0x9D SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
+sfr at 0x9E CPT0CN ; /* COMPARATOR 0 CONTROL */
+sfr at 0x9F CPT1CN ; /* COMPARATOR 1 CONTROL */
+sfr at 0xA0 P2 ; /* PORT 2 */
+sfr at 0xA4 PRT0CF ; /* PORT 0 CONFIGURATION */
+sfr at 0xA5 PRT1CF ; /* PORT 1 CONFIGURATION */
+sfr at 0xA6 PRT2CF ; /* PORT 2 CONFIGURATION */
+sfr at 0xA7 PRT3CF ; /* PORT 3 CONFIGURATION */
+sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
+sfr at 0xAD PRT1IF ; /* PORT 1 EXTERNAL INTERRUPT FLAGS */
+sfr at 0xAF EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
+sfr at 0xB0 P3 ; /* PORT 3 */
+sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
+sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
+sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
+sfr at 0xB7 FLACL ; /* FLASH ACESS LIMIT */
+sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
+sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
+sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
+sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
+sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
+sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
+sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
+sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
+sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
+sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
+sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
+sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
+sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
+sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
+sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */
+sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
+sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
+sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
+sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
+sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
+sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
+sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
+sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
+sfr at 0xD5 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
+sfr at 0xD6 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
+sfr at 0xD7 DAC1CN ; /* DAC 1 CONTROL */
+sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
+sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
+sfr at 0xDA PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
+sfr at 0xDB PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
+sfr at 0xDC PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
+sfr at 0xDD PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
+sfr at 0xDE PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
+sfr at 0xE0 ACC ; /* ACCUMULATOR */
+sfr at 0xE1 XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
+sfr at 0xE2 XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
+sfr at 0xE3 XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
+sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
+sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
+sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
+sfr at 0xE9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
+sfr at 0xEA PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
+sfr at 0xEB PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
+sfr at 0xEC PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
+sfr at 0xED PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
+sfr at 0xEE PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
+sfr at 0xEF RSTSRC ; /* RESET SOURCE */
+sfr at 0xF0 B ; /* B REGISTER */
+sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
+sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
+sfr at 0xF8 SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
+sfr at 0xF9 PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
+sfr at 0xFA PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
+sfr at 0xFB PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
+sfr at 0xFC PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
+sfr at 0xFD PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
+sfr at 0xFE PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
+sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
+
+
+/* BIT Registers */
+
+/* P0 0x80 */
+sbit at 0x87 P0_7 ;
+sbit at 0x86 P0_6 ;
+sbit at 0x85 P0_5 ;
+sbit at 0x84 P0_4 ;
+sbit at 0x83 P0_3 ;
+sbit at 0x82 P0_2 ;
+sbit at 0x81 P0_1 ;
+sbit at 0x80 P0_0 ;
+
+/* TCON 0x88 */
+sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
+sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
+sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
+sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
+sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
+sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
+sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
+sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
+
+/* P1 0x90 */
+sbit at 0x97 P1_7 ;
+sbit at 0x96 P1_6 ;
+sbit at 0x95 P1_5 ;
+sbit at 0x94 P1_4 ;
+sbit at 0x93 P1_3 ;
+sbit at 0x92 P1_2 ;
+sbit at 0x91 P1_1 ;
+sbit at 0x90 P1_0 ;
+
+/* SCON 0x98 */
+sbit at 0x9F SM0 ; /* SERIAL MODE CONTROL BIT 0 */
+sbit at 0x9E SM1 ; /* SERIAL MODE CONTROL BIT 1 */
+sbit at 0x9D SM2 ; /* MULTIPROCESSOR COMMUNICATION ENABLE */
+sbit at 0x9C REN ; /* RECEIVE ENABLE */
+sbit at 0x9B TB8 ; /* TRANSMIT BIT 8 */
+sbit at 0x9A RB8 ; /* RECEIVE BIT 8 */
+sbit at 0x99 TI ; /* TRANSMIT INTERRUPT FLAG */
+sbit at 0x98 RI ; /* RECEIVE INTERRUPT FLAG */
+
+/* P2 0xA0 */
+sbit at 0xA7 P2_7 ;
+sbit at 0xA6 P2_6 ;
+sbit at 0xA5 P2_5 ;
+sbit at 0xA4 P2_4 ;
+sbit at 0xA3 P2_3 ;
+sbit at 0xA2 P2_2 ;
+sbit at 0xA1 P2_1 ;
+sbit at 0xA0 P2_0 ;
+
+/* IE 0xA8 */
+sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
+sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
+sbit at 0xAC ES ; /* SERIAL PORT INTERRUPT ENABLE */
+sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
+sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
+sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
+sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
+
+/* P3 0xB0 */
+sbit at 0xB7 P3_7 ;
+sbit at 0xB6 P3_6 ;
+sbit at 0xB5 P3_5 ;
+sbit at 0xB4 P3_4 ;
+sbit at 0xB3 P3_3 ;
+sbit at 0xB2 P3_2 ;
+sbit at 0xB1 P3_1 ;
+sbit at 0xB0 P3_0 ;
+
+/* IP 0xB8 */
+sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */
+sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */
+sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */
+sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
+sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
+sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
+
+/* SMB0CN 0xC0 */
+sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */
+sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
+sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */
+sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
+sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
+sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
+sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
+sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
+
+/* T2CON 0xC8 */
+sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
+sbit at 0xCE EXF2 ; /* EXTERNAL FLAG */
+sbit at 0xCD RCLK ; /* RECEIVE CLOCK FLAG */
+sbit at 0xCC TCLK ; /* TRANSMIT CLOCK FLAG */
+sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
+sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
+sbit at 0xC9 CT2 ; /* TIMER OR COUNTER SELECT */
+sbit at 0xC8 CPRL2 ; /* CAPTURE OR RELOAD SELECT */
+
+/* PSW 0xD0 */
+sbit at 0xD7 CY ; /* CARRY FLAG */
+sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
+sbit at 0xD5 F0 ; /* USER FLAG 0 */
+sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
+sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
+sbit at 0xD2 OV ; /* OVERFLOW FLAG */
+sbit at 0xD1 F1 ; /* USER FLAG 1 */
+sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
+
+/* PCA0CN 0xD8H */
+sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
+sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
+sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
+sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
+sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
+sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
+sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
+
+/* ADC0CN 0xE8H */
+sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */
+sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
+sbit at 0xED AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
+sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
+sbit at 0xEB ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
+sbit at 0xEA ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
+sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
+sbit at 0xE8 ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
+
+/* SPI0CN 0xF8H */
+sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
+sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
+sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
+sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
+sbit at 0xFB TXBSY ; /* SPI 0 TX BUSY FLAG */
+sbit at 0xFA SLVSEL ; /* SPI 0 SLAVE SELECT */
+sbit at 0xF9 MSTEN ; /* SPI 0 MASTER ENABLE */
+sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
+
+
+
+#define IDLE 0x01 /* PCON */
+#define STOP 0x02 /* PCON */
+#define TF3 0x80 /* TMR3CN */
+#define CPFIF 0x10 /* CPTnCN */
+#define CPRIF 0x20 /* CPTnCN */
+#define CPOUT 0x40 /* CPTnCN */
+#define ECCF 0x01 /* PCA0CPMn */
+#define PWM 0x02 /* PCA0CPMn */
+#define TOG 0x04 /* PCA0CPMn */
+#define MAT 0x08 /* PCA0CPMn */
+#define ECOM 0x40 /* PCA0CPMn */
+
+#endif
--- /dev/null
+/*-------------------------------------------------------------------------
+ Register Declarations for the Cygnal C8051F12x Processor Range
+
+ Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------*/
+
+#ifndef C8051F120_H
+#define C8051F120_H
+
+/* BYTE Registers */
+
+/* All Pages */
+sfr at 0x80 P0 ; /* PORT 0 */
+sfr at 0x81 SP ; /* STACK POINTER */
+sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
+sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
+sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */
+sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */
+sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */
+sfr at 0x87 PCON ; /* POWER CONTROL */
+sfr at 0x90 P1 ; /* PORT 1 */
+sfr at 0xA0 P2 ; /* PORT 2 */
+sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
+sfr at 0xB0 P3 ; /* PORT 3 */
+sfr at 0xB1 PSBANK ; /* FLASH BANK SELECT */
+sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
+sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
+sfr at 0xE0 ACC ; /* ACCUMULATOR */
+sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
+sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
+sfr at 0xF0 B ; /* B REGISTER */
+sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
+sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
+sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
+
+/* Page 0x00 */
+sfr at 0x88 TCON ; /* TIMER CONTROL */
+sfr at 0x89 TMOD ; /* TIMER MODE */
+sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
+sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
+sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
+sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
+sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */
+sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */
+sfr at 0x91 SSTA0 ; /* UART 0 STATUS */
+sfr at 0x98 SCON0 ; /* UART 0 CONTROL */
+sfr at 0x98 SCON ; /* UART 0 CONTROL */
+sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */
+sfr at 0x99 SBUF ; /* UART 0 BUFFER */
+sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */
+sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */
+sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */
+sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */
+sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */
+sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */
+sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */
+sfr at 0xB7 FLSCL ; /* FLASH SCALE */
+sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */
+sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
+sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
+sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
+sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
+sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
+sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
+sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
+sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
+sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
+sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
+sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
+sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
+sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
+sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
+sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */
+sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
+sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
+sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
+sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
+sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
+sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
+sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
+sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
+sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
+sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
+sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
+sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */
+sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */
+sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */
+sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */
+sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */
+sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */
+sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
+sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
+sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
+sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
+sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
+sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
+sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
+sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
+sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
+sfr at 0xEF RSTSRC ; /* RESET SOURCE */
+sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */
+sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
+sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
+sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
+sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
+sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
+sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
+
+/* Page 0x01 */
+sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */
+sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */
+sfr at 0x98 SCON1 ; /* UART 1 CONTROL */
+sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */
+sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */
+sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */
+sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
+sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
+sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */
+sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */
+sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
+sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
+sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */
+
+/* Page 0x02 */
+sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */
+sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */
+sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */
+sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */
+sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */
+sfr at 0xBE ADC2 ; /* ADC 2 DATA */
+sfr at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */
+sfr at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */
+sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */
+sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */
+sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
+sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
+sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */
+sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */
+
+/* Page 0x02 */
+sfr at 0x91 MAC0BL ; /* MAC0 B Register Low Byte */
+sfr at 0x92 MAC0BH ; /* MAC0 B Register High Byte */
+sfr at 0x93 MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */
+sfr at 0x94 MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */
+sfr at 0x95 MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */
+sfr at 0x96 MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */
+sfr at 0x97 MAC0OVR ; /* MAC0 Accumulator Overflow */
+sfr at 0xC0 MAC0STA ; /* MAC0 Status Register */
+sfr at 0xC1 MAC0AL ; /* MAC0 A Register Low Byte */
+sfr at 0xC2 MAC0AH ; /* MAC0 A Register High Byte */
+sfr at 0xC3 MAC0CF ; /* MAC0 Configuration */
+sfr at 0xCE MAC0RNDL ; /* MAC0 Rounding Register Low Byte */
+sfr at 0xCF MAC0RNDH ; /* MAC0 Rounding Register High Byte */
+
+/* Page 0x0F */
+sfr at 0x88 FLSTAT ; /* FLASH STATUS */
+sfr at 0x89 PLL0CN ; /* PLL 0 CONTROL */
+sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
+sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
+sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
+sfr at 0x8D PLL0DIV ; /* PLL 0 DIVIDER */
+sfr at 0x8E PLL0MUL ; /* PLL 0 MULTIPLIER */
+sfr at 0x8F PLL0FLT ; /* PLL 0 FILTER */
+sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */
+sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */
+sfr at 0x9A CCH0MA ; /* CACHE MISS ACCUMULATOR */
+sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */
+sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */
+sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */
+sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */
+sfr at 0xA1 CCH0CN ; /* CACHE CONTROL */
+sfr at 0xA2 CCH0TN ; /* CACHE TUNING REGISTER */
+sfr at 0xA3 CCH0LC ; /* CACHE LOCK */
+sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */
+sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */
+sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
+sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
+sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */
+sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */
+sfr at 0xC8 P4 ; /* PORT 4 */
+sfr at 0xD8 P5 ; /* PORT 5 */
+sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */
+sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */
+sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */
+sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */
+sfr at 0xE8 P6 ; /* PORT 6 */
+sfr at 0xF8 P7 ; /* PORT 7 */
+
+
+/* BIT Registers */
+
+/* P0 0x80 */
+sbit at 0x80 P0_0 ;
+sbit at 0x81 P0_1 ;
+sbit at 0x82 P0_2 ;
+sbit at 0x83 P0_3 ;
+sbit at 0x84 P0_4 ;
+sbit at 0x85 P0_5 ;
+sbit at 0x86 P0_6 ;
+sbit at 0x87 P0_7 ;
+
+/* TCON 0x88 */
+sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
+sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
+sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
+sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
+sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
+sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
+sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
+sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
+
+/* CPT0CN 0x88 */
+sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
+sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
+sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
+sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
+sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */
+sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */
+sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */
+sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */
+
+/* CPT1CN 0x88 */
+sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
+sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
+sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
+sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
+sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */
+sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */
+sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */
+sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */
+
+/* FLSTAT 0x88 */
+sbit at 0x88 FLHBUSY ; /* FLASH BUSY */
+
+/* SCON0 0x98 */
+sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */
+sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */
+sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */
+sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */
+sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */
+sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */
+sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */
+sbit at 0x9C REN ; /* UART 0 RX ENABLE */
+sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */
+sbit at 0x9E SM10 ; /* UART 0 MODE 1 */
+sbit at 0x9F SM00 ; /* UART 0 MODE 0 */
+
+/* SCON1 0x98 */
+sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */
+sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */
+sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */
+sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */
+sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */
+sbit at 0x9D MCE1 ; /* UART 1 MCE */
+sbit at 0x9F S1MODE ; /* UART 1 MODE */
+
+/* IE 0xA8 */
+sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
+sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
+sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
+sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
+sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */
+sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */
+sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
+sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
+
+/* IP 0xB8 */
+sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
+sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
+sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
+sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */
+sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */
+sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */
+
+/* SMB0CN 0xC0 */
+sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
+sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
+sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
+sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
+sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
+sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */
+sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
+sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */
+
+/* TMR2CN 0xC8 */
+sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */
+sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */
+sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
+sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
+sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */
+sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
+
+/* TMR3CN 0xC8 */
+sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */
+sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */
+sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */
+sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */
+sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */
+sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */
+
+/* TMR4CN 0xC8 */
+sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */
+sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */
+sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */
+sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */
+sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */
+sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */
+
+/* P4 0xC8 */
+sbit at 0xC8 P4_0 ;
+sbit at 0xC9 P4_1 ;
+sbit at 0xCA P4_2 ;
+sbit at 0xCB P4_3 ;
+sbit at 0xCC P4_4 ;
+sbit at 0xCD P4_5 ;
+sbit at 0xCE P4_6 ;
+sbit at 0xCF P4_7 ;
+
+/* PSW 0xD0 */
+sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
+sbit at 0xD1 F1 ; /* USER FLAG 1 */
+sbit at 0xD2 OV ; /* OVERFLOW FLAG */
+sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
+sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
+sbit at 0xD5 F0 ; /* USER FLAG 0 */
+sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
+sbit at 0xD7 CY ; /* CARRY FLAG */
+
+/* PCA0CN D8H */
+sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
+sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
+sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
+sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
+sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
+sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */
+sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
+sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
+
+/* P5 0xD8 */
+sbit at 0xD8 P5_0 ;
+sbit at 0xD9 P5_1 ;
+sbit at 0xDA P5_2 ;
+sbit at 0xDB P5_3 ;
+sbit at 0xDC P5_4 ;
+sbit at 0xDD P5_5 ;
+sbit at 0xDE P5_6 ;
+sbit at 0xDF P5_7 ;
+
+/* ADC0CN E8H */
+sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
+sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */
+sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */
+sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */
+sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
+sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */
+sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
+sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */
+
+/* ADC2CN E8H */
+sbit at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */
+sbit at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */
+sbit at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */
+sbit at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */
+sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */
+sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */
+sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */
+sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */
+
+/* P6 0xE8 */
+sbit at 0xE8 P6_0 ;
+sbit at 0xE9 P6_1 ;
+sbit at 0xEA P6_2 ;
+sbit at 0xEB P6_3 ;
+sbit at 0xEC P6_4 ;
+sbit at 0xED P6_5 ;
+sbit at 0xEE P6_6 ;
+sbit at 0xEF P6_7 ;
+
+/* SPI0CN F8H */
+sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
+sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */
+sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */
+sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */
+sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
+sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
+sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
+sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
+
+/* P7 0xF8 */
+sbit at 0xF8 P7_0 ;
+sbit at 0xF9 P7_1 ;
+sbit at 0xFA P7_2 ;
+sbit at 0xFB P7_3 ;
+sbit at 0xFC P7_4 ;
+sbit at 0xFD P7_5 ;
+sbit at 0xFE P7_6 ;
+sbit at 0xFF P7_7 ;
+
+
+/* Predefined SFR Bit Masks */
+
+#define IDLE 0x01 /* PCON */
+#define STOP 0x01 /* PCON */
+#define ECCF 0x01 /* PCA0CPMn */
+#define PWM 0x02 /* PCA0CPMn */
+#define TOG 0x04 /* PCA0CPMn */
+#define MAT 0x08 /* PCA0CPMn */
+#define ECOM 0x40 /* PCA0CPMn */
+#define PORSF 0x02 /* RSTSRC */
+#define SWRSF 0x10 /* RSTSRC */
+
+
+/* SFR PAGE DEFINITIONS */
+
+#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */
+#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */
+#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */
+#define CPT0_PAGE 0x01 /* COMPARATOR 0 */
+#define CPT1_PAGE 0x02 /* COMPARATOR 1 */
+#define UART0_PAGE 0x00 /* UART 0 */
+#define UART1_PAGE 0x01 /* UART 1 */
+#define SPI0_PAGE 0x00 /* SPI 0 */
+#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */
+#define ADC0_PAGE 0x00 /* ADC 0 */
+#define ADC2_PAGE 0x02 /* ADC 2 */
+#define SMB0_PAGE 0x00 /* SMBUS 0 */
+#define TMR2_PAGE 0x00 /* TIMER 2 */
+#define TMR3_PAGE 0x01 /* TIMER 3 */
+#define TMR4_PAGE 0x02 /* TIMER 4 */
+#define DAC0_PAGE 0x00 /* DAC 0 */
+#define DAC1_PAGE 0x01 /* DAC 1 */
+#define PCA0_PAGE 0x00 /* PCA 0 */
+#define PLL0_PAGE 0x0F /* PLL 0 */
+
+#endif
--- /dev/null
+/*-------------------------------------------------------------------------
+ Register Declarations for the Cygnal C8051F30x Processor Range
+
+ Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------*/
+
+#ifndef C8051F300_H
+#define C8051F300_H
+
+/* BYTE Registers */
+sfr at 0x80 P0 ; /* PORT 0 */
+sfr at 0x81 SP ; /* STACK POINTER */
+sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
+sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
+sfr at 0x87 PCON ; /* POWER CONTROL */
+sfr at 0x88 TCON ; /* TIMER CONTROL */
+sfr at 0x89 TMOD ; /* TIMER MODE */
+sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
+sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
+sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
+sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
+sfr at 0x8E CKCON ; /* CLOCK CONTROL */
+sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
+sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */
+sfr at 0x98 SCON0 ; /* SERIAL PORT CONTROL */
+sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */
+sfr at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */
+sfr at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
+sfr at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
+sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
+sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
+sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
+sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
+sfr at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
+sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
+sfr at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */
+sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
+sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
+sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
+sfr at 0xBE ADC0 ; /* ADC 0 DATA */
+sfr at 0xC0 SMB0CN ; /* SMBUS CONTROL */
+sfr at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */
+sfr at 0xC2 SMB0DAT ; /* SMBUS DATA */
+sfr at 0xC4 ADC0GT ; /* ADC 0 GREATER-THAN REGISTER */
+sfr at 0xC6 ADC0LT ; /* ADC 0 LESS-THAN REGISTER */
+sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */
+sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
+sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+sfr at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
+sfr at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
+sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
+sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
+sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
+sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
+sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
+sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
+sfr at 0xD8 PCA0CN ; /* PCA CONTROL */
+sfr at 0xD9 PCA0MD ; /* PCA MODE */
+sfr at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
+sfr at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
+sfr at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
+sfr at 0xE0 ACC ; /* ACCUMULATOR */
+sfr at 0xE1 PRT0MX ; /* PORT MUX CONFIGURATION REGISTER 0 */
+sfr at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
+sfr at 0xE2 PRT1MX ; /* PORT MUX CONFIGURATION REGISTER 1 */
+sfr at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
+sfr at 0xE3 PRT2MX ; /* PORT MUX CONFIGURATION REGISTER 2 */
+sfr at 0xE3 XBR2 ; /* PORT MUX CONFIGURATION REGISTER 2 */
+sfr at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
+sfr at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
+sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
+sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
+sfr at 0xE9 PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
+sfr at 0xEA PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
+sfr at 0xEB PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
+sfr at 0xEC PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
+sfr at 0xEF RSTSRC ; /* RESET SOURCE */
+sfr at 0xF0 B ; /* B REGISTER */
+sfr at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
+sfr at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
+sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
+sfr at 0xF8 CPT0CN ; /* COMPARATOR 0 CONTROL */
+sfr at 0xF9 PCA0L ; /* PCA COUNTER LOW */
+sfr at 0xFA PCA0H ; /* PCA COUNTER HIGH */
+sfr at 0xFB PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
+sfr at 0xFC PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
+
+
+/* BIT Registers */
+
+/* P0 0x80 */
+sbit at 0x80 P0_0 ;
+sbit at 0x81 P0_1 ;
+sbit at 0x82 P0_2 ;
+sbit at 0x83 P0_3 ;
+sbit at 0x84 P0_4 ;
+sbit at 0x85 P0_5 ;
+sbit at 0x86 P0_6 ;
+sbit at 0x87 P0_7 ;
+
+/* TCON 0x88 */
+sbit at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
+sbit at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
+sbit at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
+sbit at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
+sbit at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
+sbit at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
+sbit at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
+sbit at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
+
+/* SCON 0x98 */
+sbit at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
+sbit at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
+sbit at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
+sbit at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
+sbit at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */
+sbit at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */
+sbit at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
+sbit at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
+sbit at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */
+sbit at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */
+sbit at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
+sbit at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
+sbit at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
+sbit at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
+
+/* IE 0xA8 */
+sbit at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
+sbit at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
+sbit at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
+sbit at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
+sbit at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
+sbit at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
+sbit at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
+sbit at 0xAE IEGF0 ; /* IE.6 - GENERAL PURPOSE FLAG 0 */
+sbit at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
+
+/* IP 0xB8 */
+sbit at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
+sbit at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */
+sbit at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
+sbit at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */
+sbit at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */
+sbit at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
+sbit at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */
+
+/* SMB0CN 0xC0 */
+sbit at 0xC0 SMBTOE ; /* SMB0CN.0 - SMBUS 0 TIMEOUT ENABLE */
+sbit at 0xC1 SMBFTE ; /* SMB0CN.1 - SMBUS 0 FREE TIMER ENABLE */
+sbit at 0xC2 AA ; /* SMB0CN.2 - SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
+sbit at 0xC3 SI ; /* SMB0CN.3 - SMBUS 0 INTERRUPT PENDING FLAG */
+sbit at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
+sbit at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
+sbit at 0xC6 ENSMB ; /* SMB0CN.6 - SMBUS 0 ENABLE */
+sbit at 0xC7 BUSY ; /* SMB0CN.7 - SMBUS 0 BUSY */
+
+/* TMR2CN 0xC8 */
+sbit at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
+sbit at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
+sbit at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
+sbit at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
+sbit at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
+sbit at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
+sbit at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
+
+/* PSW 0xD0 */
+sbit at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
+sbit at 0xD1 F1 ; /* PSW.1 - FLAG 1 */
+sbit at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */
+sbit at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
+sbit at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
+sbit at 0xD5 F0 ; /* PSW.5 - FLAG 0 */
+sbit at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
+sbit at 0xD7 CY ; /* PSW.7 - CARRY FLAG */
+
+/* PCA0CN 0xD8 */
+sbit at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
+sbit at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
+sbit at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
+sbit at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
+sbit at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
+
+/* ADC0CN 0xE8 */
+sbit at 0xE8 AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
+sbit at 0xE9 AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
+sbit at 0xEA AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
+sbit at 0xEB AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
+sbit at 0xEC AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
+sbit at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
+sbit at 0xEE AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
+sbit at 0xEF AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
+
+/* CPT0CN 0xF8 */
+sbit at 0xF8 CP0HYN0 ; /* CPT0CN.0 - Comp.0 Neg. Hysteresis Control Bit0*/
+sbit at 0xF9 CP0HYN1 ; /* CPT0CN.1 - Comp.0 Neg. Hysteresis Control Bit1*/
+sbit at 0xFA CP0HYP0 ; /* CPT0CN.2 - Comp.0 Pos. Hysteresis Control Bit0*/
+sbit at 0xFB CP0HYP1 ; /* CPT0CN.3 - Comp.0 Pos. Hysteresis Control Bit1*/
+sbit at 0xFC CP0FIF ; /* CPT0CN.4 - Comparator0 Falling-Edge Int. Flag */
+sbit at 0xFD CP0RIF ; /* CPT0CN.5 - Comparator0 Rising-Edge Int. Flag */
+sbit at 0xFE CP0OUT ; /* CPT0CN.6 - Comparator0 Output State Flag */
+sbit at 0xFF CP0EN ; /* CPT0CN.7 - Comparator0 Enable Bit */
+
+
+/* Predefined SFR Bit Masks */
+
+#define IDLE 0x01 /* PCON */
+#define STOP 0x01 /* PCON */
+#define T1M 0x10 /* CKCON */
+#define PSWE 0x01 /* PSCTL */
+#define PSEE 0x02 /* PSCTL */
+#define ECP0F 0x10 /* EIE1 */
+#define ECP0R 0x20 /* EIE1 */
+#define PORSF 0x02 /* RSTSRC */
+#define SWRSF 0x10 /* RSTSRC */
+#define ECCF 0x01 /* PCA0CPMn */
+#define PWM 0x02 /* PCA0CPMn */
+#define TOG 0x04 /* PCA0CPMn */
+#define MAT 0x08 /* PCA0CPMn */
+#define ECOM 0x40 /* PCA0CPMn */
+#define CP0AOEN 0x20 /* XBR1 */
+
+#endif
projects / fw / sdcc / commitdiff