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(from parent 1:
c88f64a
)
Enable pps interrupts. Not sure why they were disabled in the first place.
author
Matt Ettus
<matt@ettus.com>
Wed, 30 Sep 2009 05:35:38 +0000
(22:35 -0700)
committer
Matt Ettus
<matt@ettus.com>
Wed, 30 Sep 2009 05:35:38 +0000
(22:35 -0700)
usrp2/fpga/timing/time_sync.v
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diff --git
a/usrp2/fpga/timing/time_sync.v
b/usrp2/fpga/timing/time_sync.v
index a4c021f58ca0a34df8143892c6e7a215f3400b6b..c0c8e195fc7543d561f70526121992a10e7c49f2 100644
(file)
--- a/
usrp2/fpga/timing/time_sync.v
+++ b/
usrp2/fpga/timing/time_sync.v
@@
-133,12
+133,11
@@
module time_sync
always @(posedge wb_clk_i)
if(rst_i)
int_o <= 0;
-/*
- else if(tick_int_enable & (internal_tick | internal_tick_d1))
+ else if(tick_int_enable & (internal_tick | internal_tick_d1))
int_o <= 1;
else
int_o <= 0;
-*/
+
always @(posedge sys_clk_i)
if(rst_i)
epoch_o <= 0;