device/include/mcs51/P89LPC925.h: Added

git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@4640 4a8a32a2-be11-0410-ad9d-d568d2c75423

diff --git a/ChangeLog b/ChangeLog
index ad2a84fce7852b0a098eb9455c67e834a465eb51..56728ae47caa6a79abf5e20468688e59cd6f8388 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,7 @@
+2007-02-22 Jesus Calvino-Fraga <jesusc at ece.ubc.ca>
+
+       * device/include/mcs51/P89LPC925.h: Added.
+
 2007-02-18 Raphael Neider <rneider AT web.de>
 
        * src/pic/glue.c (emitInitVal): fixed #1659894 (SIGSEGV on arrays)

diff --git a/device/include/mcs51/P89LPC925.h b/device/include/mcs51/P89LPC925.h
index 00e634937835b05fb3a5747bbf37d6faac218f30..7eddeac97682d9e3f701b6655c43773569d04c96 100644 (file)
--- a/device/include/mcs51/P89LPC925.h
+++ b/device/include/mcs51/P89LPC925.h
@@ -26,9 +26,9 @@
 #ifndef REG_P89LPC925_H\r
 #define REG_P89LPC925_H\r
 \r
-#include <compiler_h>\r
+#include <compiler.h>\r
 \r
-SFR(ACC*, 0xE0); // Accumulator\r
+SFR(ACC, 0xE0); // Accumulator\r
    SBIT(ACC_7, 0xE0, 7);\r
    SBIT(ACC_6, 0xE0, 6);\r
    SBIT(ACC_5, 0xE0, 5);\r
@@ -87,7 +87,7 @@ SFR(AUXR1, 0xA2); // Auxiliary function register
    #define SRST  0x08\r
    #define DPS   0x01\r
 \r
-SFR(B*, 0xF0); // B register\r
+SFR(B, 0xF0); // B register\r
    SBIT(B_7, 0xF0, 7);\r
    SBIT(B_6, 0xF0, 6);\r
    SBIT(B_5, 0xF0, 5);\r
@@ -160,7 +160,7 @@ SFR(I2ADR, 0xDB); // I2C slave address register
    #define I2ADR_0 0x02\r
    #define GC      0x01\r
 \r
-SFR(I2CON*, 0xD8); // I2C control register\r
+SFR(I2CON, 0xD8); // I2C control register\r
    SBIT(I2EN,  0xD8, 6);\r
    SBIT(STA,   0xD8, 5);\r
    SBIT(STO,   0xD8, 4);\r
@@ -181,7 +181,7 @@ SFR(I2STAT, 0xD9); // I2C status register
    #define STA_1 0x10\r
    #define STA_0 0x08\r
 \r
-SFR(IEN0*, 0xA8); // Interrupt enable 0\r
+SFR(IEN0, 0xA8); // Interrupt enable 0\r
    SBIT(EA,    0xA8, 7);\r
    SBIT(EWDRT, 0xA8, 6);\r
    SBIT(EBO,   0xA8, 5);\r
@@ -192,14 +192,14 @@ SFR(IEN0*, 0xA8); // Interrupt enable 0
    SBIT(ET0,   0xA8, 1);\r
    SBIT(EX0,   0xA8, 0);\r
 \r
-SFR(IEN1*, 0xE8); // Interrupt enable 1\r
+SFR(IEN1, 0xE8); // Interrupt enable 1\r
    SBIT(EAD,  0xE8, 7);\r
    SBIT(EST,  0xE8, 6);\r
    SBIT(EC,   0xE8, 2);\r
    SBIT(EKBI, 0xE8, 1);\r
    SBIT(EI2C, 0xE8, 0);\r
 \r
-SFR(IP0*, 0xB8); // Interrupt priority 0\r
+SFR(IP0, 0xB8); // Interrupt priority 0\r
    SBIT(PWDRT, 0xB8, 6);\r
    SBIT(PBO,   0xB8, 5);\r
    SBIT(PS,    0xB8, 4);\r
@@ -219,7 +219,7 @@ SFR(IP0H, 0xB7); // Interrupt priority 0 HIGH
    #define PT0H   0x02\r
    #define PX0H   0x01\r
 \r
-SFR(IP1*, 0xF8); // Interrupt priority 1\r
+SFR(IP1, 0xF8); // Interrupt priority 1\r
    SBIT(PAD,  0xF8, 7);\r
    SBIT(PST,  0xF8, 6);\r
    SBIT(PC,   0xF8, 2);\r
@@ -241,7 +241,7 @@ SFR(KBMASK, 0x86); // Keypad interrupt register mask
 \r
 SFR(KBPATN, 0x93); // Keypad pattern register\r
 \r
-SFR(P0*, 0x80); // Port 0\r
+SFR(P0, 0x80); // Port 0\r
    SBIT(P0_7, 0x80, 7);\r
    SBIT(P0_6, 0x80, 6);\r
    SBIT(P0_5, 0x80, 5);\r
@@ -252,13 +252,13 @@ SFR(P0*, 0x80); // Port 0
    SBIT(P0_0, 0x80, 0);\r
    //P0 alternate pin functions\r
    SBIT(T1,     0x80, 7);\r
-   SBIT(CMP1,   0x80, 6);\r
+   SBIT(CMP1b,  0x80, 6); //Should be CMP1 but there is SFR with that name\r
    SBIT(CMPREF, 0x80, 5);\r
    SBIT(CIN1A,  0x80, 4);\r
    SBIT(CIN1B,  0x80, 3);\r
    SBIT(CIN2A,  0x80, 2);\r
    SBIT(CIN2B,  0x80, 1);\r
-   SBIT(CMP2,   0x80, 0);\r
+   SBIT(CMP2b,  0x80, 0); //Should be CMP2 but there is SFR with that name\r
    //More P0 alternate pin functions\r
    SBIT(KB7, 0x80, 7);\r
    SBIT(KB6, 0x80, 6);\r
@@ -269,7 +269,7 @@ SFR(P0*, 0x80); // Port 0
    SBIT(KB1, 0x80, 1);\r
    SBIT(KB0, 0x80, 0);\r
 \r
-SFR(P1*, 0x90); // Port 1\r
+SFR(P1, 0x90); // Port 1\r
    SBIT(P1_5, 0x90, 5);\r
    SBIT(P1_4, 0x90, 4);\r
    SBIT(P1_3, 0x90, 3);\r
@@ -286,7 +286,7 @@ SFR(P1*, 0x90); // Port 1
    SBIT(RXD,  0x90, 1);\r
    SBIT(TXD,  0x90, 0);\r
 \r
-SFR(P3*, 0xB0); // Port 3\r
+SFR(P3, 0xB0); // Port 3\r
    SBIT(P3_1, 0xB0, 1);\r
    SBIT(P3_0, 0xB0, 0);\r
    SBIT(XTAL1, 0xB0, 1);\r
@@ -355,7 +355,7 @@ SFR(PCONA, 0xB5); // Power control register A
    #define I2PD  0x08\r
    #define SPD   0x02\r
 \r
-SFR(PSW*, 0xD0); // Program status word\r
+SFR(PSW, 0xD0); // Program status word\r
    SBIT(CY,  0xD0, 7);\r
    SBIT(AC,  0xD0, 6);\r
    SBIT(F0,  0xD0, 5);\r
@@ -397,7 +397,7 @@ SFR(SADEN, 0xB9); // Serial port address enable
 \r
 SFR(SBUF, 0x99); // Serial Port data buffer register\r
 \r
-SFR(SCON*, 0x98); // Serial port control\r
+SFR(SCON, 0x98); // Serial port control\r
    SBIT(FE,  0x98, 7);\r
    SBIT(SM0, 0x98, 7);\r
    SBIT(SM1, 0x98, 6);\r
@@ -424,7 +424,7 @@ SFR(TAMOD, 0x8F); // Timer0 and 1 auxiliary mode
    #define T1M2 0x10\r
    #define T0M2 0x01\r
 \r
-SFR(TCON*, 0x88); // Timer0 and 1 control\r
+SFR(TCON, 0x88); // Timer0 and 1 control\r
    SBIT(TF1, 0x88, 7);\r
    SBIT(TR1, 0x88, 6);\r
    SBIT(TF0, 0x88, 5);\r