Cache invalidation when writing to memory

git-svn-id: svn://svn.berlios.de/openocd/trunk@2708 b42882b7-edfa-0310-969c-e2dbd0fdcd60

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 7a70515322286e78a061956df9405c02eb067778..e73994e9c87ba36b76184f3874a0a546c7c39c5a 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -1253,6 +1253,24 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address,
                        exit(-1);
        }
 
+       /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
+       /* invalidate I-Cache */
+       if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
+       {
+               /* Invalidate ICache single entry with MVA, repeat this for all cache
+                  lines in the address range, Cortex-A8 has fixed 64 byte line length */
+               /* Invalidate Cache single entry with MVA to PoU */
+               for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
+                       armv7a->write_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */
+       }
+       /* invalidate D-Cache */
+       if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
+       {
+               /* Invalidate Cache single entry with MVA to PoC */
+               for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
+                       armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */
+       }
+
        return retval;
 }