} else
LOG_WARNING("automatic write mode detected");
+ uint32_t nvm_param;
+
+ res = target_read_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, &nvm_param);
+
+ if (res != ERROR_OK)
+ return res;
+
+ unsigned nvm_psz = (unsigned) ((nvm_param >> 16) & 0x7);
+ unsigned nvm_nvmp = (unsigned) (nvm_param & 0xffff);
+ LOG_INFO("NVM parameter 0x%08" PRIx32 " PSZ %u NVMP %u", nvm_param, nvm_psz, nvm_nvmp);
+
+ LOG_INFO("page size %d num_pages %d", chip->page_size, chip->num_pages);
+
while (count) {
res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_PBC);
address = bank->base + offset;
pg_offset = offset % chip->page_size;
+ LOG_INFO("writing address 0x%08" PRIx32 " pg_offset 0x%08" PRIx32 " nb %d",
+ address, pg_offset, nb);
+
if (offset % 4 || (offset + nb) % 4) {
/* Either start or end of write is not word aligned */
if (!pb) {