- disabled use of single-step bit for EmbeddedICE version 6 cores

git-svn-id: svn://svn.berlios.de/openocd/trunk@128 b42882b7-edfa-0310-969c-e2dbd0fdcd60

diff --git a/src/openocd.c b/src/openocd.c
index 1e8ceea34c6b3e28b11b61181c9cc117740652a9..502e9740e368249a572644a56ba026a145a7b53f 100644 (file)
--- a/src/openocd.c
+++ b/src/openocd.c
@@ -18,7 +18,7 @@
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
 
-#define OPENOCD_VERSION "Open On-Chip Debugger (2006-01-25 11:30 CET)"
+#define OPENOCD_VERSION "Open On-Chip Debugger (2006-01-26 13:30 CET)"
 
 #ifdef HAVE_CONFIG_H
 #include "config.h"

diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 6cf698161ed0ee5275fac4ebaa0998a510dda486..200a5390a8eb766f81edc78371b3e00e04cb7cb4 100644 (file)
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -169,7 +169,6 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
                case 6:
                        reg_list[EICE_DBG_CTRL].size = 6;
                        reg_list[EICE_DBG_STAT].size = 10;
-                       arm7_9->has_single_step = 1;
                        arm7_9->has_monitor_mode = 1;
                        break;
                default: