Alan Carvalho de Assis <acassis@gmail.com> cfg file to initialize the iMX27ADS board.

git-svn-id: svn://svn.berlios.de/openocd/trunk@1318 b42882b7-edfa-0310-969c-e2dbd0fdcd60

diff --git a/src/target/board/imx27ads.cfg b/src/target/board/imx27ads.cfg
new file mode 100644 (file)
index 0000000..8202f0f
--- /dev/null
+++ b/src/target/board/imx27ads.cfg
@@ -0,0 +1,75 @@
+# The IMX27 ADS eval board has a single IMX27 chip\r
+# Note: tested on IMX27ADS Board REV-2.6 and REV-2.8\r
+source [find target/imx27.cfg]\r
+$_TARGETNAME configure -event gdb-attach { reset init }\r
+$_TARGETNAME configure -event reset-init { imx27ads_init }\r
+\r
+# The IMX27 ADS board has a NOR flash on CS0\r
+flash_bank cfi 0xc0000000 0x00200000 2 2 0\r
+\r
+proc imx27ads_init { } {\r
+       # This setup puts RAM at 0xA0000000\r
+\r
+       # reset the board correctly\r
+       reset run\r
+       reset halt\r
+\r
+       mww 0x10000000 0x20040304\r
+       mww 0x10020000 0x00000000\r
+       mww 0x10000004 0xDFFBFCFB\r
+       mww 0x10020004 0xFFFFFFFF\r
+\r
+       sleep 100\r
+\r
+       # ========================================\r
+       #  Configure DDR on CSD0 -- initial reset\r
+       # ========================================\r
+       mww 0xD8001010 0x00000008 \r
+\r
+       # ========================================\r
+       #  Configure PSRAM on CS5 \r
+       # ========================================\r
+       mww 0xd8002050 0x0000dcf6\r
+       mww 0xd8002054 0x444a4541 \r
+       mww 0xd8002058 0x44443302 \r
+\r
+       #  ========================================\r
+       #         Configure16 bit NorFlash on CS0\r
+       #  ========================================\r
+       mww 0xd8002000 0x0000CC03 \r
+       mww 0xd8002004 0xa0330D01 \r
+       mww 0xd8002008 0x00220800 \r
+\r
+       # ========================================\r
+       #  Configure CPLD on CS4 \r
+       # ========================================\r
+       mww 0xd8002040 0x0000DCF6 \r
+       mww 0xd8002044 0x444A4541 \r
+       mww 0xd8002048 0x44443302 \r
+\r
+       # ========================================\r
+       #  Configure DDR on CSD0 -- wait 5000 cycle \r
+       # ========================================\r
+       mww 0x10027828 0x55555555 \r
+       mww 0x10027830 0x55555555 \r
+       mww 0x10027834 0x55555555 \r
+       mww 0x10027838 0x00005005 \r
+       mww 0x1002783C 0x15555555 \r
+\r
+       mww 0xD8001010 0x00000004 \r
+\r
+       mww 0xD8001004 0x00795729 \r
+\r
+       mww 0xD8001000 0x92200000 \r
+       mww 0xA0000F00 0x0\r
+\r
+       mww 0xD8001000 0xA2200000 \r
+       mww 0xA0000F00 0x0\r
+       mww 0xA0000F00 0x0\r
+\r
+       mww 0xD8001000 0xB2200000 \r
+       mwb 0xA0000033 0xFF\r
+       mwb 0xA1000000 0xAA\r
+\r
+       mww 0xD8001000 0x82228085 \r
+}\r