Added missing comment in SST89x5xRDx.h

git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@4617 4a8a32a2-be11-0410-ad9d-d568d2c75423

diff --git a/device/include/mcs51/SST89x5xRDx.h b/device/include/mcs51/SST89x5xRDx.h
index b9dc7bc3137383d8764ac5ee7adcaa20f27fe0fc..450237fece0a7d3b86db90f0a09a2d775e69d64d 100644 (file)
--- a/device/include/mcs51/SST89x5xRDx.h
+++ b/device/include/mcs51/SST89x5xRDx.h
@@ -125,25 +125,25 @@ SFR(SFCF, 0xB1); // SuperFlash Configuration
    #define SWR    0x02 // Software Reset\r
    #define BSEL   0x01 // Program memory block switching bit\r
 SFR(SFCM, 0xB2); // SuperFlash Command\r
-   #define FIE 0x80 Flash Interrupt Enable\r
-   #define CHIP_ERASE 0x01\r
-   #define SECTOR_ERASE 0x0B\r
-   #define BLOCK_ERASE 0x0D\r
-   #define BYTE_VERIFY 0x0C\r
-   #define BYTE_PROGRAM 0x0E\r
-   #define PROG_SB1 0x0F\r
-   #define PROG_SB2 0x03\r
-   #define PROG_SB3 0x05\r
-   #define PROG_SC0 0x09\r
+   #define FIE                 0x80 // Flash Interrupt Enable\r
+   #define CHIP_ERASE          0x01\r
+   #define SECTOR_ERASE        0x0B\r
+   #define BLOCK_ERASE         0x0D\r
+   #define BYTE_VERIFY         0x0C\r
+   #define BYTE_PROGRAM        0x0E\r
+   #define PROG_SB1            0x0F\r
+   #define PROG_SB2            0x03\r
+   #define PROG_SB3            0x05\r
+   #define PROG_SC0            0x09\r
    #define ENABLE_CLOCK_DOUBLE 0x08\r
 SFR(SFAL, 0xB3); // SuperFlash Address Low Register - A7 to A0\r
 SFR(SFAH, 0xB4); // SuperFlash Address High Register - A15 to A8\r
 SFR(SFDT, 0xB5); // SuperFlash Data Register\r
 SFR(SFST, 0xB6); // SuperFlash Status\r
-   #define SB1_i 0x80 // Security Bit 1 status (inverse of SB1 bit)\r
-   #define SB2_i 0x40 // Security Bit 2 status (inverse of SB2 bit)\r
-   #define SB3_i 0x20 // Security Bit 3 status (inverse of SB3 bit)\r
-   #define EDC_i 0x08 // Double Clock Status\r
+   #define SB1_i      0x80 // Security Bit 1 status (inverse of SB1 bit)\r
+   #define SB2_i      0x40 // Security Bit 2 status (inverse of SB2 bit)\r
+   #define SB3_i      0x20 // Security Bit 3 status (inverse of SB3 bit)\r
+   #define EDC_i      0x08 // Double Clock Status\r
    #define FLASH_BUSY 0x04 // Flash operation completion polling bit\r
 \r
 // TABLE 3-7: Watchdog Timer SFRs\r