This allows for programming the PL part of the Xilinx Zynq 7000
Change-Id: I89e86c0f381951091f6948c46802d17d7f1f3500
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-on: http://openocd.zylin.com/4177
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
+
+pld device virtex2 zynq_pl.bs 1
+
+set XC7_JSHUTDOWN 0x0d
+set XC7_JPROGRAM 0x0b
+set XC7_JSTART 0x0c
+set XC7_BYPASS 0x3f
+
+proc zynqpl_program {tap} {
+ global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
+ irscan $tap $XC7_JSHUTDOWN
+ irscan $tap $XC7_JPROGRAM
+ runtest 60000
+ #JSTART prevents this from working...
+ #irscan $tap $XC7_JSTART
+ runtest 2000
+ irscan $tap $XC7_BYPASS
+ runtest 2000
+}