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git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@3819 4a8a32a2-be11-0410-ad9d-d568d2c75423

diff --git a/device/include/mcs51/8052.h b/device/include/mcs51/8052.h
index ddb505a33bb6c6fcf7f520e80ac4ba10c14f4f14..9783d84b256ef3e406f0c9053710aa8e9e58c35f 100755 (executable)
--- a/device/include/mcs51/8052.h
+++ b/device/include/mcs51/8052.h
@@ -46,7 +46,7 @@ __sfr __at (0xCD) TH2     ;
 __sbit __at (0xAD) ET2    ; /* Enable timer2 interrupt */
 
 /*  IP  */
-__sbit __at 0xBD PT2      ; /* T2 interrupt priority bit */
+__sbit __at (0xBD) PT2    ; /* T2 interrupt priority bit */
 
 /* T2CON bits */
 __sbit __at (0xC8) T2CON_0 ;

diff --git a/device/include/mcs51/msm8xc154s.h b/device/include/mcs51/msm8xc154s.h
index 0cde0bb9b27a13ee78867b26a557ae19e9c54bfb..04ba1f25487308176996beab3c5101f7ec04bc57 100644 (file)
--- a/device/include/mcs51/msm8xc154s.h
+++ b/device/include/mcs51/msm8xc154s.h
@@ -44,7 +44,6 @@ __sbit __at (0xfd)    SERR;   /* Serial port reception flag */
 __sbit __at (0xfe)     T32;    /* interconnect T0 and T1 to 32bit timer/counter */
 
 /* Bits in IP (0xb8) */
-__sbit __at (0xbd)     PT2;    /* Interrupt priority bit for timer interrupt 2 */
 __sbit __at (0xbf)     PCT;    /* Priority interrupt circuit control bit */
 
 /* Bits in PCON (0x87) */