Merge branch 'master' of ssh://dbrownell@openocd.git.sourceforge.net/gitroot/openocd...

diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 0d23c121481d7d1929ee6ee1e5a10b82c96a419c..39f87c790afc1c8b5bb45e90f5b8d66f60292a79 100644 (file)
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -264,7 +264,8 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
                         * in some unusual bits.  Let feroceon.c validate it
                         * and do the appropriate setup itself.
                         */
-                       if (strcmp(target_get_name(target), "feroceon") == 0)
+                       if (strcmp(target_get_name(target), "feroceon") == 0 ||
+                           strcmp(target_get_name(target), "dragonite") == 0)
                                break;
                        LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8" PRIx32 ")", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
        }

diff --git a/tcl/board/dm6446evm.cfg b/tcl/board/dm6446evm.cfg
new file mode 100644 (file)
index 0000000..39607fe
--- /dev/null
+++ b/tcl/board/dm6446evm.cfg
@@ -0,0 +1,74 @@
+# DM6446 EVM board
+#   http://focus.ti.com/docs/toolsw/folders/print/tmdsevm6446.html
+#   http://c6000.spectrumdigital.com/davincievm/
+# EVM is just the board; buy that at Spectrum.
+# The "kit" from TI also has: video camera, LCD video monitor, more.
+
+source [find target/ti_dm6446.cfg]
+
+# J4 controls what CS2 hooks up to, usually NOR or NAND flash.
+# S3.1/S3.2 controls boot mode, which may force J4 and S3.3 settings.
+# S3.3 controls AEMIF bus width.
+
+if { [info exists J4_OPTION] } {
+       # NOR, NAND, SRAM, ...
+       set CS2_MODE $J4_OPTION
+} else {
+       set CS2_MODE ""
+}
+
+# ARM boot:
+#  S3.1 = 0, S3.2 = 0  ==> ROM/UBL boot via NAND (J4 == NAND)
+#  S3.1 = 1, S3.2 = 0  ==> AEMIF boot (J4 == NOR or SRAM)
+#  S3.1 = 0, S3.2 = 1  ==> ROM/UBL boot via HPI
+#  S3.1 = 1, S3.2 = 1  ==> ROM/UBL boot via UART (J4 == don't care)
+# AEMIF bus width:
+#  S3.3 = 0            ==> 8 bit bus width
+#  S3.3 = 1            ==> 16 bit bus width
+# DSP boot:
+#  S3.4 = 0            ==> controlled by ARM
+
+if { $CS2_MODE == "NOR" } {
+       # 16 Mbytes address space; 16 bit bus width
+       # (older boards used 32MB parts, with upper 16 MB unusable)
+       flash bank cfi 0x02000000 0x01000000 2 2 $_TARGETNAME
+       proc flashprobe {} { flash probe 0 }
+} elseif { $CS2_MODE == "NAND" } {
+       # 64 Mbyte small page; 8 bit bus width
+       nand device davinci $_TARGETNAME 0x02000000 hwecc1 0x01e00000
+       proc flashprobe {} { nand probe 0 }
+} elseif { $CS2_MODE == "SRAM" } {
+       # 4 Mbyte address space; 16 bit bus width
+       # loaded via JTAG or HPI
+       proc flashprobe {} {}
+} else {
+       # maybe it's HPI boot?  can't tell...
+       echo "WARNING:  CS2/flash configuration not recognized"
+       proc flashprobe {} {}
+}
+
+# NOTE:  disable or replace this call to dm6446evm_init if you're
+# debugging new UBL code from SRAM (for NAND boot).
+$_TARGETNAME configure -event reset-init { dm6446evm_init }
+
+#
+# This post-reset init is called when the MMU isn't active, all IRQs
+# are disabled, etc.  It should do most of what a UBL does, except for
+# loading code (like U-Boot) into DRAM and running it.
+#
+proc dm6446evm_init {} {
+
+       puts "Initialize DM6446 EVM board"
+
+       # FIXME initialize everything:
+       #  - PLL1
+       #  - PLL2
+       #  - PINMUX
+       #  - PSC
+       #  - DDR
+       #  - AEMIF
+       #  - UART0
+       #  - icache
+
+       flashprobe
+}

diff --git a/tcl/target/dragonite.cfg b/tcl/target/dragonite.cfg
new file mode 100644 (file)
index 0000000..d2e7e32
--- /dev/null
+++ b/tcl/target/dragonite.cfg
@@ -0,0 +1,31 @@
+######################################
+# Target:    Marvell Dragonite CPU core
+######################################
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME dragonite
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x121003d3
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME dragonite -endian $_ENDIAN -chain-position $_TARGETNAME
+
+reset_config trst_and_srst
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+