fixed the:

void test(unsigned char datain)
{
  datain &= 0x39;
  if (datain)
    putchar ('1');
  else
    putchar ('0');
}
bug

git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@695 4a8a32a2-be11-0410-ad9d-d568d2c75423

diff --git a/src/ds390/gen.c b/src/ds390/gen.c
index 7685031fb203c8720fdd21d191649479990e1761..f945a13405be28519d30d0e546b9d9ebfe4c232b 100644 (file)
--- a/src/ds390/gen.c
+++ b/src/ds390/gen.c
@@ -1374,7 +1374,6 @@ genNotFloat (operand * op, operand * res)
                        offset++, FALSE, FALSE, FALSE));
     }
   _endLazyDPSEvaluation ();
-  tlbl = newiTempLabel (NULL);
 
   tlbl = newiTempLabel (NULL);
   aopPut (res->aop, one, 1);

diff --git a/src/ds390/ralloc.c b/src/ds390/ralloc.c
index f7ce298b659badc23e9edec29b96e4043fceebc1..1302506d2724e4c6bd55467ea17b78664c98360a 100644 (file)
--- a/src/ds390/ralloc.c
+++ b/src/ds390/ralloc.c
@@ -2012,17 +2012,17 @@ isBitwiseOptimizable (iCode * ic)
   /* bitwise operations are considered optimizable
      under the following conditions (Jean-Louis VERN) 
 
-     x & lit
+     x & lit   <== jwk: should be x && lit
      bit & bit
      bit & x
      bit ^ bit
      bit ^ x
-     x   ^ lit
-     x   | lit
+     x   ^ lit <== jwk: should be x ^^ lit
+     x   | lit <== jwk: should be x || lit
      bit | bit
      bit | x
    */
-  if (IS_LITERAL (rtype) ||
+  if ( /* jwk IS_LITERAL (rtype) || */
       (IS_BITVAR (ltype) && IN_BITSPACE (SPEC_OCLS (ltype))))
     return TRUE;
   else
@@ -2319,10 +2319,7 @@ packRegisters (eBBlock * ebp)
          is defined in the previous instruction then
          mark the itemp as a conditional */
       if ((IS_CONDITIONAL (ic) ||
-          ((ic->op == BITWISEAND ||
-            ic->op == '|' ||
-            ic->op == '^') &&
-           isBitwiseOptimizable (ic))) &&
+          (IS_BITWISE_OP(ic) && isBitwiseOptimizable(ic))) &&
          ic->next && ic->next->op == IFX &&
          isOperandEqual (IC_RESULT (ic), IC_COND (ic->next)) &&
          OP_SYMBOL (IC_RESULT (ic))->liveTo <= ic->next->seq)

diff --git a/src/mcs51/gen.c b/src/mcs51/gen.c
index 7b208a361970f009d3cd9b297b6b3167e31b8dcf..1e3801225077f425ab8519522f17aaa5dbcfed27 100644 (file)
--- a/src/mcs51/gen.c
+++ b/src/mcs51/gen.c
@@ -1187,7 +1187,6 @@ genNotFloat (operand * op, operand * res)
                aopGet (op->aop,
                        offset++, FALSE, FALSE));
     }
-  tlbl = newiTempLabel (NULL);
 
   tlbl = newiTempLabel (NULL);
   aopPut (res->aop, one, 1);

diff --git a/src/mcs51/ralloc.c b/src/mcs51/ralloc.c
index 30309b8bb81137cdf96c7ce4bbc08e302824755d..e741f9bbf6c64bca3599357cb78189cb942cb503 100644 (file)
--- a/src/mcs51/ralloc.c
+++ b/src/mcs51/ralloc.c
@@ -2016,17 +2016,17 @@ isBitwiseOptimizable (iCode * ic)
   /* bitwise operations are considered optimizable
      under the following conditions (Jean-Louis VERN) 
 
-     x & lit
+     x & lit   <== jwk: should be x && lit
      bit & bit
      bit & x
      bit ^ bit
      bit ^ x
-     x   ^ lit
-     x   | lit
+     x   ^ lit <== jwk: should be x ^^ lit
+     x   | lit <== jwk: should be x || lit
      bit | bit
      bit | x
    */
-  if (IS_LITERAL (rtype) ||
+  if ( /* jwk IS_LITERAL (rtype) || */
       (IS_BITVAR (ltype) && IN_BITSPACE (SPEC_OCLS (ltype))))
     return TRUE;
   else
@@ -2227,8 +2227,6 @@ packRegisters (eBBlock * ebp)
       /* TrueSym := iTempNN:1             */
       for (ic = ebp->sch; ic; ic = ic->next)
        {
-
-
          /* find assignment of the form TrueSym := iTempNN:1 */
          if (ic->op == '=' && !POINTER_SET (ic))
            change += packRegsForAssign (ic, ebp);
@@ -2322,15 +2320,11 @@ packRegisters (eBBlock * ebp)
          is defined in the previous instruction then
          mark the itemp as a conditional */
       if ((IS_CONDITIONAL (ic) ||
-          ((ic->op == BITWISEAND ||
-            ic->op == '|' ||
-            ic->op == '^') &&
-           isBitwiseOptimizable (ic))) &&
+          (IS_BITWISE_OP(ic) && isBitwiseOptimizable (ic))) &&
          ic->next && ic->next->op == IFX &&
          isOperandEqual (IC_RESULT (ic), IC_COND (ic->next)) &&
          OP_SYMBOL (IC_RESULT (ic))->liveTo <= ic->next->seq)
        {
-
          OP_SYMBOL (IC_RESULT (ic))->regType = REG_CND;
          continue;
        }