#include <usrp/db_wbxng.h>
#include <usrp/db_wbxng_adf4350.h>
#include <db_base_impl.h>
+#include <stdio.h>
// d'board i/o pin defs
// Tx and Rx have shared defs, but different i/o regs
#define ENABLE_33 (1 << 6) // enables 3.3V supply
#define RX_TXN (1 << 5) // Tx only: T/R antenna switch for TX/RX port
#define RX2_RX1N (1 << 5) // Rx only: antenna switch between RX2 and TX/RX port
-#define BBAMP_EN (1 << 4)
+#define TXMOD_EN (1 << 4)
#define PLL_CE (1 << 3)
#define PLL_PDBRF (1 << 2)
#define PLL_MUXOUT (1 << 1)
*/
freq_t int_freq = freq_t(freq);
- bool ok = d_common->_set_freq(int_freq);
- double freq_result = (double) d_common->_get_freq();
+ bool ok = d_common->_set_freq(int_freq*2);
+ double freq_result = (double) d_common->_get_freq()/2.0;
struct freq_result_t args = {ok, freq_result};
/* Wait before reading Lock Detect*/
double
wbxng_base::freq_min()
{
- return (double) d_common->_get_min_freq();
+ return (double) d_common->_get_min_freq()/2.0;
}
double
wbxng_base::freq_max()
{
- return (double) d_common->_get_max_freq();
+ return (double) d_common->_get_max_freq()/2.0;
}
// ----------------------------------------------------------------
d_common = new adf4350(_usrp, d_which, d_spi_enable);
// power up the transmit side, but don't enable the mixer
- usrp()->_write_oe(d_which,(PLL_PDBRF|PLL_CE|RX_TXN|ENABLE_33|ENABLE_5), (PLL_PDBRF|PLL_CE|RX_TXN|ENABLE_33|ENABLE_5));
- usrp()->write_io(d_which, (power_on()|PLL_PDBRF|PLL_CE|RX_TXN|ENABLE_33|ENABLE_5), (PLL_PDBRF|PLL_CE|RX_TXN|ENABLE_33|ENABLE_5));
+ usrp()->_write_oe(d_which,(RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5), (RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5));
+ usrp()->write_io(d_which, (power_on()|RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5), (RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5));
+ fprintf(stderr,"Setting WBXNG TXMOD on");
//set_lo_offset(4e6);
//set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
// do whatever there is to do to shutdown
// Power down and leave the T/R switch in the R position
- usrp()->write_io(d_which, (power_off()|RX_TXN), (PLL_PDBRF|PLL_CE|RX_TXN|ENABLE_33|ENABLE_5));
+ usrp()->write_io(d_which, (power_off()|RX_TXN), (RX_TXN|ENABLE_33|ENABLE_5));
- /*
// Power down VCO/PLL
- d_PD = 3;
+ d_common->_enable(false);
+ /*
_write_control(_compute_control_reg());
*/
_enable_refclk(false); // turn off refclk
wbxng_base_tx::set_auto_tr(bool on)
{
bool ok = true;
- /*
if(on) {
ok &= set_atr_mask (RX_TXN | ENABLE_33 | ENABLE_5);
ok &= set_atr_txval(0 | ENABLE_33 | ENABLE_5);
ok &= set_atr_txval(0);
ok &= set_atr_rxval(0);
}
- */
return ok;
}
*/
int v;
- int mask = PLL_PDBRF | PLL_PDBRF | RX_TXN | ENABLE_5 | ENABLE_33;
+ int mask = RX_TXN | ENABLE_5 | ENABLE_33;
if(on) {
- v = PLL_PDBRF | PLL_CE | ENABLE_5 | ENABLE_33;
+ v = ENABLE_5 | ENABLE_33;
}
else {
v = RX_TXN;
usrp()->common_write_io(C_RX, d_which, power_off(), (ENABLE_33|ENABLE_5));
// Power down VCO/PLL
- d_PD = 3;
-
+ d_common->_enable(false);
// fprintf(stderr, "wbxng_base_rx::shutdown before _write_control\n");
//_write_control(_compute_control_reg());
bool
wbxng_base_rx::set_auto_tr(bool on)
{
- //bool ok = true;
- /*
+ bool ok = true;
if(on) {
ok &= set_atr_mask (ENABLE_33|ENABLE_5);
ok &= set_atr_txval( 0);
ok &= set_atr_txval(0);
ok &= set_atr_rxval(0);
}
- */
return true;
}
#define LD_PIN (1 << 0)
adf4350::adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable){
- /* Initialize the pin directions. */
+ /* Initialize the pin directions. */
d_usrp = _usrp;
d_which = _which;
/* Outputs */
d_usrp->_write_oe(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
- d_usrp->write_io(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
+ d_usrp->write_io(d_which, (0), (CE_PIN | PDB_RF_PIN));
- /* Initialize the pin levels. */
- _enable(true);
- /* Initialize the registers. */
- /*
- timespec t;
- t.tv_sec = 1;
- t.tv_nsec = 0;
- while (1) {
- */
+ /* Initialize the pin levels. */
+ _enable(true);
+ /* Initialize the registers. */
d_regs->_load_register(5);
- /*
- nanosleep(&t, NULL);
- }
- */
- d_regs->_load_register(4);
- d_regs->_load_register(3);
- d_regs->_load_register(2);
- d_regs->_load_register(1);
- d_regs->_load_register(0);
+ d_regs->_load_register(4);
+ d_regs->_load_register(3);
+ d_regs->_load_register(2);
+ d_regs->_load_register(1);
+ d_regs->_load_register(0);
}
adf4350::~adf4350(){
freq_t
adf4350::_get_max_freq(void){
- return MAX_FREQ;
+ return MAX_FREQ;
}
freq_t
adf4350::_get_min_freq(void){
- return MIN_FREQ;
+ return MIN_FREQ;
}
bool
void
adf4350::_enable(bool enable){
- if (enable){ /* chip enable */
+ if (enable){ /* chip enable */
d_usrp->write_io(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
- }else{
+ }else{
d_usrp->write_io(d_which, 0, (CE_PIN | PDB_RF_PIN));
- }
+ }
}
void
adf4350::_write(uint8_t addr, uint32_t data){
- data |= addr;
+ data |= addr;
// create str from data here
char s[4];
d_usrp->_write_spi(0, d_spi_enable, d_spi_format, str);
nanosleep(&t, NULL);
- fprintf(stderr, "Wrote to WBXNG SPI address %d with data %8x\n", addr, data);
- /* pulse latch */
+ //fprintf(stderr, "Wrote to WBXNG SPI address %d with data %8x\n", addr, data);
+ /* pulse latch */
//d_usrp->write_io(d_which, 1, LE_PIN);
//d_usrp->write_io(d_which, 0, LE_PIN);
}
bool
adf4350::_set_freq(freq_t freq){
- /* Set the frequency by setting int, frac, mod, r, div */
- if (freq > MAX_FREQ || freq < MIN_FREQ) return false;
- /* Ramp up the RF divider until the VCO is within range. */
- d_regs->d_divider_select = 0;
- while (freq < MIN_VCO_FREQ){
- freq <<= 1; //double the freq
- d_regs->d_divider_select++; //double the divider
- }
- /* Ramp up the R divider until the N divider is at least the minimum. */
- //d_regs->d_10_bit_r_counter = INPUT_REF_FREQ*MIN_INT_DIV/freq;
- d_regs->d_10_bit_r_counter = 2;
- uint64_t n_mod;
- do{
- d_regs->d_10_bit_r_counter++;
- n_mod = freq;
- n_mod *= d_regs->d_10_bit_r_counter;
- n_mod *= d_regs->d_mod;
- n_mod /= INPUT_REF_FREQ;
- /* calculate int and frac */
- d_regs->d_int = n_mod/d_regs->d_mod;
- d_regs->d_frac = (n_mod - (freq_t)d_regs->d_int*d_regs->d_mod) & uint16_t(0xfff);
- fprintf(stderr,
- "VCO %lu KHz, Int %u, Frac %u, Mod %u, R %u, Div %u\n",
- freq, d_regs->d_int, d_regs->d_frac,
- d_regs->d_mod, d_regs->d_10_bit_r_counter, (1 << d_regs->d_divider_select)
- );
- }while(d_regs->d_int < MIN_INT_DIV);
- /* calculate the band select so PFD is under 125 KHz */
- d_regs->d_8_bit_band_select_clock_divider_value = \
- INPUT_REF_FREQ/(FREQ_C(30e3)*d_regs->d_10_bit_r_counter) + 1;
+ /* Set the frequency by setting int, frac, mod, r, div */
+ if (freq > MAX_FREQ || freq < MIN_FREQ) return false;
+ /* Ramp up the RF divider until the VCO is within range. */
+ d_regs->d_divider_select = 0;
+ while (freq < MIN_VCO_FREQ){
+ freq <<= 1; //double the freq
+ d_regs->d_divider_select++; //double the divider
+ }
+ /* Ramp up the R divider until the N divider is at least the minimum. */
+ //d_regs->d_10_bit_r_counter = INPUT_REF_FREQ*MIN_INT_DIV/freq;
+ d_regs->d_10_bit_r_counter = 2;
+ uint64_t n_mod;
+ do{
+ d_regs->d_10_bit_r_counter++;
+ n_mod = freq;
+ n_mod *= d_regs->d_10_bit_r_counter;
+ n_mod *= d_regs->d_mod;
+ n_mod /= INPUT_REF_FREQ;
+ /* calculate int and frac */
+ d_regs->d_int = n_mod/d_regs->d_mod;
+ d_regs->d_frac = (n_mod - (freq_t)d_regs->d_int*d_regs->d_mod) & uint16_t(0xfff);
+ /*
+ fprintf(stderr,
+ "VCO %lu KHz, Int %u, Frac %u, Mod %u, R %u, Div %u\n",
+ freq, d_regs->d_int, d_regs->d_frac,
+ d_regs->d_mod, d_regs->d_10_bit_r_counter, (1 << d_regs->d_divider_select)
+ );
+ */
+ }while(d_regs->d_int < MIN_INT_DIV);
+ /* calculate the band select so PFD is under 125 KHz */
+ d_regs->d_8_bit_band_select_clock_divider_value = \
+ INPUT_REF_FREQ/(FREQ_C(30e3)*d_regs->d_10_bit_r_counter) + 1;
+ /*
fprintf(stderr, "Band Selection: Div %u, Freq %lu\n",
d_regs->d_8_bit_band_select_clock_divider_value,
- INPUT_REF_FREQ/(d_regs->d_8_bit_band_select_clock_divider_value * d_regs->d_10_bit_r_counter) + 1
+ INPUT_REF_FREQ/(d_regs->d_8_bit_band_select_clock_divider_value * d_regs->d_10_bit_r_counter) + 1
);
- d_regs->_load_register(5);
- d_regs->_load_register(3);
- d_regs->_load_register(1);
- /* load involved registers */
- d_regs->_load_register(2);
- d_regs->_load_register(4);
- d_regs->_load_register(0); /* register 0 must be last */
- return true;
+ */
+ d_regs->_load_register(5);
+ d_regs->_load_register(3);
+ d_regs->_load_register(1);
+ /* load involved registers */
+ d_regs->_load_register(2);
+ d_regs->_load_register(4);
+ d_regs->_load_register(0); /* register 0 must be last */
+ return true;
}
freq_t
adf4350::_get_freq(void){
- /* Calculate the freq from int, frac, mod, ref, r, div:
- * freq = (int + frac/mod) * (ref/r)
- * Keep precision by doing multiplies first:
- * freq = (((((((int)*mod) + frac)*ref)/mod)/r)/div)
- */
- uint64_t temp;
- temp = d_regs->d_int;
- temp *= d_regs->d_mod;
- temp += d_regs->d_frac;
- temp *= INPUT_REF_FREQ;
- temp /= d_regs->d_mod;
- temp /= d_regs->d_10_bit_r_counter;
- temp /= (1 << d_regs->d_divider_select);
- return temp;
+ /* Calculate the freq from int, frac, mod, ref, r, div:
+ * freq = (int + frac/mod) * (ref/r)
+ * Keep precision by doing multiplies first:
+ * freq = (((((((int)*mod) + frac)*ref)/mod)/r)/div)
+ */
+ uint64_t temp;
+ temp = d_regs->d_int;
+ temp *= d_regs->d_mod;
+ temp += d_regs->d_frac;
+ temp *= INPUT_REF_FREQ;
+ temp /= d_regs->d_mod;
+ temp /= d_regs->d_10_bit_r_counter;
+ temp /= (1 << d_regs->d_divider_select);
+ return temp;
}
projects / debian / gnuradio / commitdiff