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DM36x: Use enable bit for PLL pre-divider
author
Thomas Koeller
<thomas.koeller@baslerweb.com>
Tue, 10 Aug 2010 12:56:42 +0000
(14:56 +0200)
committer
Øyvind Harboe
<oyvind.harboe@zylin.com>
Thu, 12 Aug 2010 06:59:02 +0000
(08:59 +0200)
The PLL pre- and postdividers seem to have enable bits, although
these are not mentioned in the chip documentation.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
tcl/target/davinci.cfg
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diff --git
a/tcl/target/davinci.cfg
b/tcl/target/davinci.cfg
index 6c6769fa9597d684c6124eb4b866fd181d6f532e..b736c6ef397db04259d881fc5997766b455d165a 100644
(file)
--- a/
tcl/target/davinci.cfg
+++ b/
tcl/target/davinci.cfg
@@
-179,7
+179,7
@@
proc pll_v03_setup {pll_addr mult config} {
mww [expr $pll_addr + 0x0110] [expr ($mult / 2) & 0x1ff]
if { [dict exists $config prediv] } {
set div [dict get $config prediv]
- set div [expr ($div - 1)]
+ set div [expr
0x8000 |
($div - 1)]
mww [expr $pll_addr + 0x0114] $div
}
if { [dict exists $config postdiv] } {