/*-----------------------------------------------------------------*/
/* initAggregates - initialises aggregate variables with initv */
/*-----------------------------------------------------------------*/
-
-/* this has to go */ void printIval (symbol *, sym_link *, initList *, FILE *);
-
ast * initAggregates (symbol * sym, initList * ival, ast * wid) {
- ast *ast;
- symbol *newSym;
-
- if (getenv("TRY_THE_NEW_INITIALIZER")) {
-
- if (!TARGET_IS_MCS51 || !(options.model==MODEL_LARGE)) {
- fprintf (stderr, "Can't \"TRY_THE_NEW_INITIALIZER\" unless "
- "with -mmcs51 and --model-large\n");
- exit(404);
- }
-
- if (SPEC_OCLS(sym->etype)==xdata &&
- getSize(sym->type) > 16) { // else it isn't worth it: do it the old way
-
- // copy this symbol
- newSym=copySymbol (sym);
- SPEC_OCLS(newSym->etype)=code;
- sprintf (newSym->name, "%s_init__", sym->name);
- sprintf (newSym->rname,"%s_init__", sym->rname);
- addSym (SymbolTab, newSym, newSym->name, 0, 0, 1);
-
- // emit it in the static segment
- addSet(&statsg->syms, newSym);
-
- // now memcpy() the entire array from cseg
- ast=newNode (ARRAYINIT, // ASSIGN_AGGREGATE
- newAst_VALUE (symbolVal (sym)),
- newAst_VALUE (symbolVal (newSym)));
- return decorateType(resolveSymbols(ast));
- }
- }
-
return createIval (newAst_VALUE (symbolVal (sym)), sym->type, ival, wid);
}
else
tfprintf (map->oFile, "\t!area\n", map->sname);
}
-
- /* print the area name */
+
for (sym = setFirstItem (map->syms); sym;
sym = setNextItem (map->syms))
{
+ symbol *newSym=NULL;
+
/* if extern then add it into the extern list */
if (IS_EXTERN (sym->etype))
fprintf (map->oFile, "%s$%d$%d", sym->name, sym->level, sym->block);
}
- /* if is has an absolute address then generate
- an equate for this no need to allocate space */
- if (SPEC_ABSA (sym->etype))
- {
- if (options.debug) {
- fprintf (map->oFile, " == 0x%04x\n", SPEC_ADDR (sym->etype));
- }
- fprintf (map->oFile, "%s\t=\t0x%04x\n",
- sym->rname,
- SPEC_ADDR (sym->etype));
- }
- else
- {
- /* allocate space */
- if (options.debug) {
- fprintf (map->oFile, "==.\n");
- }
- if (IS_STATIC (sym->etype))
- tfprintf (map->oFile, "!slabeldef\n", sym->rname);
- else
- tfprintf (map->oFile, "!labeldef\n", sym->rname);
- tfprintf (map->oFile, "\t!ds\n",
- (unsigned int) getSize (sym->type) & 0xffff);
- }
-
/* if it has an initial value then do it only if
it is a global variable */
- if (sym->ival && sym->level == 0)
- {
+ if (sym->ival && sym->level == 0) {
+ // can we copy xidata from xinit?
+ if (port->genXINIT &&
+ SPEC_OCLS(sym->etype)==xdata &&
+ !SPEC_ABSA(sym->etype)) {
+
+ // create a new "XINIT (CODE)" symbol
+ newSym=copySymbol (sym);
+ SPEC_OCLS(newSym->etype)=xinit;
+ sprintf (newSym->name, "_xinit_%s", sym->name);
+ sprintf (newSym->rname,"_xinit_%s", sym->rname);
+ SPEC_CONST(newSym->etype)=1;
+ //SPEC_STAT(newSym->etype)=1;
+ addSym (SymbolTab, newSym, newSym->name, 0, 0, 1);
+
+ // add it to the "XINIT (CODE)" segment
+ addSet(&xinit->syms, newSym);
+
+ // move sym from "XSEG (XDATA)" to "XISEG (XDATA)" segment
+ //deleteSetItem(&xdata->syms, sym);
+ addSet(&xidata->syms, sym);
+ SPEC_OCLS(sym->etype)=xidata;
+
+ //fprintf (stderr, "moved %s from xdata to xidata\n", sym->rname);
+
+ } else {
if (IS_AGGREGATE (sym->type)) {
ival = initAggregates (sym, sym->ival, NULL);
} else {
sym->name, sym->lineDef);
}
ival = newNode ('=', newAst_VALUE (symbolVal (sym)),
- decorateType (resolveSymbols (list2expr (sym->ival))));
+ decorateType (resolveSymbols (list2expr (sym->ival))));
}
codeOutFile = statsg->oFile;
allocInfo = 0;
-
+
// set ival's lineno to where the symbol was defined
if (ival) ival->lineno=sym->lineDef;
eBBlockFromiCode (iCodeFromAst (ival));
allocInfo = 1;
+ }
+
+ /* if the ival is a symbol assigned to an aggregate,
+ (bug #458099 -> #462479)
+ we don't need it anymore, so delete it from its segment */
+ if (sym->ival->type == INIT_NODE &&
+ IS_AST_SYM_VALUE(sym->ival->init.node) &&
+ IS_AGGREGATE (sym->type) ) {
+ symIval=AST_SYMBOL(sym->ival->init.node);
+ segment = SPEC_OCLS (symIval->etype);
+ deleteSetItem (&segment->syms, symIval);
+ }
+
+ sym->ival = NULL;
+ }
- /* if the ival is a symbol assigned to an aggregate,
- (bug #458099 -> #462479)
- we don't need it anymore, so delete it from its segment */
- if (sym->ival->type == INIT_NODE &&
- IS_AST_SYM_VALUE(sym->ival->init.node) &&
- IS_AGGREGATE (sym->type) ) {
- symIval=AST_SYMBOL(sym->ival->init.node);
- segment = SPEC_OCLS (symIval->etype);
- deleteSetItem (&segment->syms, symIval);
+ /* if is has an absolute address then generate
+ an equate for this no need to allocate space */
+ if (SPEC_ABSA (sym->etype))
+ {
+ if (options.debug) {
+ fprintf (map->oFile, " == 0x%04x\n", SPEC_ADDR (sym->etype));
+ }
+ fprintf (map->oFile, "%s\t=\t0x%04x\n",
+ sym->rname,
+ SPEC_ADDR (sym->etype));
+ }
+ else
+ {
+ if (newSym) {
+ // this has been moved to another segment
+ } else {
+ /* allocate space */
+ if (options.debug) {
+ fprintf (map->oFile, "==.\n");
+ }
+ if (IS_STATIC (sym->etype))
+ tfprintf (map->oFile, "!slabeldef\n", sym->rname);
+ else
+ tfprintf (map->oFile, "!labeldef\n", sym->rname);
+ tfprintf (map->oFile, "\t!ds\n",
+ (unsigned int) getSize (sym->type) & 0xffff);
}
-
- sym->ival = NULL;
}
}
}
aopLiteral (val, 0), aopLiteral (val, 1));
break;
case 3:
- /* PENDING: 0x02 or 0x%02x, CDATA? */
- fprintf (oFile, "\t.byte %s,%s,#0x02\n",
- aopLiteral (val, 0), aopLiteral (val, 1));
+ werror (E_LITERAL_GENERIC);
+ fprintf (oFile, "\t.byte %s,%s,%s\n",
+ aopLiteral (val, 0),
+ aopLiteral (val, 1),
+ aopLiteral (val, 2));
+ break;
+ case 4:
+ werror (E_LITERAL_GENERIC);
+ fprintf (oFile, "\t.byte %s,%s,%s,%s\n",
+ aopLiteral (val, 0),
+ aopLiteral (val, 1),
+ aopLiteral (val, 2),
+ aopLiteral (val, 3));
break;
default:
assert (0);
{
symbol *sym;
- /* fprintf(map->oFile,"\t.area\t%s\n",map->sname); */
- if (!out)
- out = code->oFile;
+ fprintf(out, "\t.area\t%s\n", map->sname);
/* for all variables in this segment do */
for (sym = setFirstItem (map->syms); sym;
emitRegularMap (idata, TRUE, TRUE);
emitRegularMap (bit, TRUE, FALSE);
emitRegularMap (xdata, TRUE, TRUE);
+ if (port->genXINIT) {
+ emitRegularMap (xidata, TRUE, TRUE);
+ }
emitRegularMap (sfr, FALSE, FALSE);
emitRegularMap (sfrbit, FALSE, FALSE);
emitRegularMap (home, TRUE, FALSE);
emitRegularMap (code, TRUE, FALSE);
emitStaticSeg (statsg, code->oFile);
+ if (port->genXINIT) {
+ emitStaticSeg (xinit, code->oFile);
+ }
inInitMode--;
}
if (!port->genIVT || !(port->genIVT (vFile, interrupts, maxInterrupts)))
{
/* "generic" interrupt table header (if port doesn't specify one).
-
* Look suspiciously like 8051 code to me...
*/
fprintf (asmFile, "%s", iComments2);
copyFile (asmFile, xdata->oFile);
+ /* copy xternal initialized ram data */
+ fprintf (asmFile, "%s", iComments2);
+ fprintf (asmFile, "; external initialized ram data\n");
+ fprintf (asmFile, "%s", iComments2);
+ copyFile (asmFile, xidata->oFile);
+
/* copy the interrupt vector table */
if (mainf && IFFUNC_HASBODY(mainf->type))
{
fprintf (asmFile, "\tljmp\t__sdcc_program_startup\n");
fprintf (asmFile, "__sdcc_init_data:\n");
+ // if the port can copy the XINIT segment to XISEG
+ if (port->genXINIT) {
+ port->genXINIT(asmFile);
+ }
+
}
copyFile (asmFile, statsg->oFile);
#include "common.h"
/* memory segments */
-memmap *xstack = NULL; /* xternal stack data */
-memmap *istack = NULL; /* internal stack */
-memmap *code = NULL; /* code segment */
-memmap *data = NULL; /* internal data upto 128 */
-memmap *xdata = NULL; /* external data */
-memmap *idata = NULL; /* internal data upto 256 */
-memmap *bit = NULL; /* bit addressable space */
-memmap *statsg = NULL; /* the constant data segment */
+memmap *xstack = NULL; /* xternal stack data */
+memmap *istack = NULL; /* internal stack */
+memmap *code = NULL; /* code segment */
+memmap *data = NULL; /* internal data upto 128 */
+memmap *xdata = NULL; /* external data */
+memmap *xidata = NULL; /* the initialized xdata */
+memmap *xinit = NULL; /* the initializers for xidata */
+memmap *idata = NULL; /* internal data upto 256 */
+memmap *bit = NULL; /* bit addressable space */
+memmap *statsg = NULL; /* the constant data segment */
memmap *sfr = NULL; /* register space */
memmap *reg = NULL; /* register space */
memmap *sfrbit = NULL; /* sfr bit space */
POINTER-TYPE - FPOINTER
*/
xdata = allocMap (0, 1, 0, 0, 0, 0, options.xdata_loc, XDATA_NAME, 'F', FPOINTER);
+ xidata = allocMap (0, 1, 0, 0, 0, 0, 0, XIDATA_NAME, 'F', FPOINTER);
+ xinit = allocMap (0, 1, 0, 0, 0, 1, 0, XINIT_NAME, 'C', CPOINTER);
/* Inderectly addressed internal data segment
SFRSPACE - NO
return TRUE;
}
+/* Generate code to copy XINIT to XISEG */
+static void _ds390_genXINIT (FILE * of) {
+ fprintf (of, "; _ds390_genXINIT() start\n");
+ fprintf (of, " mov a,#s_XINIT\n");
+ fprintf (of, " add a,#l_XINIT\n");
+ fprintf (of, " mov r1,a\n");
+ fprintf (of, " mov a,#s_XINIT>>8\n");
+ fprintf (of, " addc a,#l_XINIT>>8\n");
+ fprintf (of, " mov r2,a\n");
+ fprintf (of, " mov dptr,#s_XINIT\n");
+ fprintf (of, " mov dps,#0x21\n");
+ fprintf (of, " mov dptr,#s_XISEG\n");
+ fprintf (of, "00001$: clr a\n");
+ fprintf (of, " movc a,@a+dptr\n");
+ fprintf (of, " movx @dptr,a\n");
+ fprintf (of, " inc dptr\n");
+ fprintf (of, " inc dptr\n");
+ fprintf (of, "00002$: mov a,dpl\n");
+ fprintf (of, " cjne a,ar1,00001$\n");
+ fprintf (of, " mov a,dph\n");
+ fprintf (of, " cjne a,ar2,00001$\n");
+ fprintf (of, " mov dps,#0\n");
+ fprintf (of, "; _ds390_genXINIT() end\n");
+}
+
/* Do CSE estimation */
static bool cseCostEstimation (iCode *ic, iCode *pdic)
{
"OSEG (OVR,DATA)",
"GSFINAL (CODE)",
"HOME (CODE)",
- NULL, // xidata
- NULL, // xinit
+ "XISEG (XDATA)", // initialized xdata
+ "XINIT (CODE)", // a code copy of xiseg
NULL,
NULL,
1
_ds390_keywords,
_ds390_genAssemblerPreamble,
_ds390_genIVT,
- NULL, // _ds390_genXINIT
+ _ds390_genXINIT,
_ds390_reset_regparm,
_ds390_regparm,
NULL,