wi-9c target scripts

git-svn-id: svn://svn.berlios.de/openocd/trunk@464 b42882b7-edfa-0310-969c-e2dbd0fdcd60

diff --git a/src/target/event/wi-9c_reset.script b/src/target/event/wi-9c_reset.script
new file mode 100644 (file)
index 0000000..cd48370
--- /dev/null
+++ b/src/target/event/wi-9c_reset.script
@@ -0,0 +1,56 @@
+mww 0x90600104 0x33313333\r
+mww 0xA0700000 0x00000001  # Enable the memory controller.\r
+mww 0xA0700024 0x00000006  # Set the refresh counter 6\r
+mww 0xA0700028 0x00000001  # \r
+mww 0xA0700030 0x00000001  # Set the precharge period\r
+mww 0xA0700034 0x00000004  # Active to precharge command period is 16 clock cycles\r
+mww 0xA070003C 0x00000001  # tAPR\r
+mww 0xA0700040 0x00000005  # tDAL\r
+mww 0xA0700044 0x00000001  # tWR\r
+mww 0xA0700048 0x00000006  # tRC 32 clock cycles  \r
+mww 0xA070004C 0x00000006  # tRFC 32 clock cycles\r
+mww 0xA0700054 0x00000001  # tRRD\r
+mww 0xA0700058 0x00000001  # tMRD\r
+mww 0xA0700100 0x00004280  # Dynamic Config 0 (cs4) \r
+mww 0xA0700120 0x00004280  # Dynamic Config 1 (cs5)\r
+mww 0xA0700140 0x00004280  # Dynamic Config 2 (cs6)\r
+mww 0xA0700160 0x00004280  # Dynamic Config 3 (cs7)\r
+#\r
+mww 0xA0700104 0x00000203  # CAS latency is 2 at 100 MHz\r
+mww 0xA0700124 0x00000203  # CAS latency is 2 at 100 MHz\r
+mww 0xA0700144 0x00000203  # CAS latency is 2 at 100 MHz\r
+mww 0xA0700164 0x00000203  # CAS latency is 2 at 100 MHz\r
+#\r
+mww 0xA0700020 0x00000103  # issue SDRAM PALL command\r
+#\r
+mww 0xA0700024 0x00000001  # Set the refresh counter to be as small as possible\r
+#\r
+# Add some dummy writes to give the SDRAM time to settle, it needs two\r
+# AHB clock cycles, here we poke in the debugger flag, this lets\r
+# the software know that we are in the debugger\r
+mww 0xA0900000 0x00000002\r
+mww 0xA0900000 0x00000002\r
+mww 0xA0900000 0x00000002\r
+mww 0xA0900000 0x00000002\r
+mww 0xA0900000 0x00000002\r
+#\r
+mdw 0xA0900000 \r
+mdw 0xA0900000 \r
+mdw 0xA0900000 \r
+mdw 0xA0900000 \r
+mdw 0xA0900000 \r
+#\r
+mww 0xA0700024 0x00000030 # Set the refresh counter to 30\r
+mww 0xA0700020 0x00000083 # Issue SDRAM MODE command\r
+#\r
+# Next we perform a read of RAM.\r
+# mw = move word.\r
+mdw 0x00022000\r
+# mw 0x00022000:P, r3  # 22000 for cas2 latency, 32000 for cas 3\r
+#\r
+mww 0xA0700020 0x00000003   # issue SDRAM NORMAL command\r
+mww 0xA0700100 0x00084280   # Enable buffer access\r
+mww 0xA0700120 0x00084280   # Enable buffer access\r
+mww 0xA0700140 0x00084280   # Enable buffer access\r
+mww 0xA0700160 0x00084280   # Enable buffer access\r
+\r

diff --git a/src/target/target/wi-9c.cfg b/src/target/target/wi-9c.cfg
new file mode 100644 (file)
index 0000000..f18b1e0
--- /dev/null
+++ b/src/target/target/wi-9c.cfg
@@ -0,0 +1,36 @@
+######################################\r
+# Target: DIGI ConnectCore Wi-9C\r
+######################################\r
+\r
+reset_config trst_and_srst\r
+\r
+#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction>\r
+jtag_device 4 0x1 0xf 0xe\r
+\r
+jtag_nsrst_delay 200\r
+jtag_ntrst_delay 0\r
+\r
+######################\r
+# Target configuration\r
+######################\r
+\r
+#target <type> <endianess> <reset mode> <JTAG pos> <variant>\r
+target arm926ejs little reset_init 0 arm926ejs\r
+\r
+target_script 0 reset event/wi-9c_reset.script\r
+run_and_halt_time 0 30\r
+\r
+#working area <target#> <address> <size> <backup|nobackup>\r
+working_area 0 0x00000000 0x1000 backup\r
+\r
+\r
+#####################\r
+# Flash configuration\r
+#####################\r
+\r
+#M29DW323DB - not working\r
+#flash bank cfi <base> <size> <chip width> <bus width> <target#>\r
+flash bank cfi 0x50000000 0x0400000 2 2 0\r
+\r
+\r
+\r