timing fix, delays the ethernet flow control by a cycle to get it across the chip...

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10523 221aa14e-8319-0410-a670-987f0aec2ac5

diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_tx.v b/usrp2/fpga/eth/rtl/verilog/MAC_tx.v
index 50b08dffb89b4e6d7641f3b96614fbd5ec5a9a4b..bbf331022dec53f91e78c404fc9a16ff1b44627b 100644 (file)
--- a/usrp2/fpga/eth/rtl/verilog/MAC_tx.v
+++ b/usrp2/fpga/eth/rtl/verilog/MAC_tx.v
@@ -127,6 +127,11 @@ wire            MAC_tx_addr_init    ;
 wire            MAC_tx_addr_rd      ;\r
 wire[7:0]       MAC_tx_addr_data    ;\r
 \r
+\r
+   reg                 xon_gen_d1, xoff_gen_d1;\r
+   always @(posedge Clk) xon_gen_d1 <= xon_gen;\r
+   always @(posedge Clk) xoff_gen_d1 <= xoff_gen;\r
+   \r
 //******************************************************************************        \r
 //instantiation                                                              \r
 //****************************************************************************** \r
@@ -147,9 +152,9 @@ MAC_tx_ctrl U_MAC_tx_ctrl(
  //flow control           (//flow control         ),           \r
 .pause_apply              (pause_apply            ),            \r
 .pause_quanta_sub         (pause_quanta_sub       ),        \r
-.xoff_gen                 (xoff_gen               ),        \r
+.xoff_gen                 (xoff_gen_d1            ),        \r
 .xoff_gen_complete        (xoff_gen_complete      ),            \r
-.xon_gen                  (xon_gen                ),            \r
+.xon_gen                  (xon_gen_d1             ),            \r
 .xon_gen_complete         (xon_gen_complete       ),        \r
  //MAC_tx_FF              (//MAC_tx_FF            ),           \r
 .Fifo_data                (Fifo_data              ),            \r

diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v b/usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v
index 0fd7c603e09fb1f99acdd0c86b3bceeb2074084a..8da2e253cbc839340026416308ce8cda83ac0a13 100644 (file)
--- a/usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v
+++ b/usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v
@@ -627,7 +627,15 @@ always @ (posedge Clk or posedge Reset)
         pause_quanta_sub    <=0;\r
 \r
 // FIXME  The below probably won't work if the pause request comes when we are in the wrong state\r
-   wire clear_xonxoff = (Current_state==StateSendPauseFrame) & (IPLengthCounter==17);\r
+   reg clear_xonxoff;\r
+   always @(posedge Clk or posedge Reset)\r
+     if(Reset)\r
+       clear_xonxoff <= 0;\r
+     else if((Current_state==StateSendPauseFrame) & (IPLengthCounter==17))\r
+       clear_xonxoff <= 1;\r
+     else if(~xon_gen & ~xoff_gen)\r
+       clear_xonxoff <= 0;\r
+   \r
 always @ (posedge Clk or posedge Reset)\r
     if (Reset) \r
         xoff_gen_complete   <=0;\r