* device/include/mcs51/cc2430.h: inserted _XPAGE

git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@4500 4a8a32a2-be11-0410-ad9d-d568d2c75423

diff --git a/ChangeLog b/ChangeLog
index f45e7c870783df3c77506ed0a865e6220f798751..941257639bc6c23fcece58f4da156050043863b2 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,7 @@
+2006-12-03 Maarten Brock <sourceforge.brock AT dse.nl>
+
+       * device/include/mcs51/cc2430.h: inserted _XPAGE
+
 2006-12-02 Jesus Calvino-Fraga <jesusc at ece.ubc.ca>
 
        * device/include/mcs51/cc2430.h: added

diff --git a/device/include/mcs51/cc2430.h b/device/include/mcs51/cc2430.h
index c07e66c093b1e039d82e1c2a50773f1a8ce3538f..dde01300f4952d843dbd3b6c0dd9f7b5f752cc0f 100644 (file)
--- a/device/include/mcs51/cc2430.h
+++ b/device/include/mcs51/cc2430.h
@@ -30,24 +30,24 @@
 \r
 // Interrupt Vectors\r
 \r
-#define RFERR_VECTOR    0   // RF TX FIFO underflow and RX FIFO overflow. \r
-#define ADC_VECTOR      1   // ADC end of conversion \r
-#define URX0_VECTOR     2   // USART0 RX complete \r
-#define URX1_VECTOR     3   // USART1 RX complete \r
-#define ENC_VECTOR      4   // AES encryption/decryption complete \r
-#define ST_VECTOR       5   // Sleep Timer compare \r
-#define P2INT_VECTOR    6   // Port 2 inputs \r
-#define UTX0_VECTOR     7   // USART0 TX complete \r
-#define DMA_VECTOR      8   // DMA transfer complete \r
-#define T1_VECTOR       9   // Timer 1 (16-bit) capture/compare/overflow \r
-#define T2_VECTOR       10  // Timer 2 (MAC Timer) \r
-#define T3_VECTOR       11  // Timer 3 (8-bit) capture/compare/overflow \r
-#define T4_VECTOR       12  // Timer 4 (8-bit) capture/compare/overflow \r
-#define P0INT_VECTOR    13  // Port 0 inputs \r
-#define UTX1_VECTOR     14  // USART1 TX complete \r
-#define P1INT_VECTOR    15  // Port 1 inputs \r
-#define RF_VECTOR       16  // RF general interrupts \r
-#define WDT_VECTOR      17  // Watchdog overflow in timer mode \r
+#define RFERR_VECTOR    0   // RF TX FIFO underflow and RX FIFO overflow.\r
+#define ADC_VECTOR      1   // ADC end of conversion\r
+#define URX0_VECTOR     2   // USART0 RX complete\r
+#define URX1_VECTOR     3   // USART1 RX complete\r
+#define ENC_VECTOR      4   // AES encryption/decryption complete\r
+#define ST_VECTOR       5   // Sleep Timer compare\r
+#define P2INT_VECTOR    6   // Port 2 inputs\r
+#define UTX0_VECTOR     7   // USART0 TX complete\r
+#define DMA_VECTOR      8   // DMA transfer complete\r
+#define T1_VECTOR       9   // Timer 1 (16-bit) capture/compare/overflow\r
+#define T2_VECTOR       10  // Timer 2 (MAC Timer)\r
+#define T3_VECTOR       11  // Timer 3 (8-bit) capture/compare/overflow\r
+#define T4_VECTOR       12  // Timer 4 (8-bit) capture/compare/overflow\r
+#define P0INT_VECTOR    13  // Port 0 inputs\r
+#define UTX1_VECTOR     14  // USART1 TX complete\r
+#define P1INT_VECTOR    15  // Port 1 inputs\r
+#define RF_VECTOR       16  // RF general interrupts\r
+#define WDT_VECTOR      17  // Watchdog overflow in timer mode\r
 \r
 // SFR Registers and BITs\r
 \r
@@ -68,12 +68,12 @@ SFR(DPH1,     0x85) // Data Pointer 1 High Byte
 SFR(U0CSR,    0x86) // USART 0 Control and Status\r
 SFR(PCON,     0x87) // Power Mode Control\r
 SFR(TCON,     0x88) // Interrupt Flags\r
-   SBIT(IT0,      0x88, 0); // reserved (must always be set to 1) \r
+   SBIT(IT0,      0x88, 0); // reserved (must always be set to 1)\r
    SBIT(RFERRIF,  0x88, 1); // RFERR \96 RF TX/RX FIFO interrupt flag\r
-   SBIT(IT1,      0x88, 2); // reserved (must always be set to 1) \r
-   SBIT(URX0IF,   0x88, 3); // USART0 RX Interrupt Flag \r
-   SBIT(ADCIF,    0x88, 5); // ADC Interrupt Flag \r
-   SBIT(URX1IF,   0x88, 7); // USART1 RX Interrupt Flag \r
+   SBIT(IT1,      0x88, 2); // reserved (must always be set to 1)\r
+   SBIT(URX0IF,   0x88, 3); // USART0 RX Interrupt Flag\r
+   SBIT(ADCIF,    0x88, 5); // ADC Interrupt Flag\r
+   SBIT(URX1IF,   0x88, 7); // USART1 RX Interrupt Flag\r
 SFR(P0IFG,    0x89) // Port 0 Interrupt Status Flag\r
 SFR(P1IFG,    0x8A) // Port 1 Interrupt Status Flag\r
 SFR(P2IFG,    0x8B) // Port 2 Interrupt Status Flag\r
@@ -92,13 +92,14 @@ SFR(P1,       0x90) // Port 1
 SFR(RFIM,     0x91) // RF Interrupt Mask\r
 SFR(DPS,      0x92) // Data Pointer Select\r
 SFR(MPAGE,    0x93) // Memory Page Select\r
+SFR(_XPAGE,   0x93) // Memory Page Select under the name SDCC needs it\r
 SFR(T2CMP,    0x94) // Timer 2 Compare Value\r
 SFR(ST0,      0x95) // Sleep Timer 0\r
 SFR(ST1,      0x96) // Sleep Timer 1\r
 SFR(ST2,      0x97) // Sleep Timer 2\r
 SFR(S0CON,    0x98) // Interrupt Flags 2\r
-   SBIT(ENCIF_0,  0x98, 0); // AES Interrupt Flag 0 \r
-   SBIT(ENCIF_1,  0x98, 1); // AES Interrupt Flag 1 \r
+   SBIT(ENCIF_0,  0x98, 0); // AES Interrupt Flag 0\r
+   SBIT(ENCIF_1,  0x98, 1); // AES Interrupt Flag 1\r
 SFR(IEN2,     0x9A) // Interrupt Enable 2\r
 SFR(S1CON,    0x9B) // Interrupt Flags 3\r
 SFR(T2PEROF0, 0x9C) // Timer 2 Overflow Capture/Compare 0\r
@@ -121,13 +122,13 @@ SFR(T2CAPHPH, 0xA5) // Timer 2 Period High Byte
 SFR(T2TLD,    0xA6) // Timer 2 Timer Value Low Byte\r
 SFR(T2THD,    0xA7) // Timer 2 Timer Value High Byte\r
 SFR(IEN0,     0xA8) // Interrupt Enable 0\r
-   SBIT(RFERRIE,  0xA8, 0); // RF TX/RX FIFO interrupt enable \r
-   SBIT(ADCIE,    0xA8, 1); // ADC Interrupt Enable \r
-   SBIT(URX0IE,   0xA8, 2); // USART0 RX Interrupt Enable \r
+   SBIT(RFERRIE,  0xA8, 0); // RF TX/RX FIFO interrupt enable\r
+   SBIT(ADCIE,    0xA8, 1); // ADC Interrupt Enable\r
+   SBIT(URX0IE,   0xA8, 2); // USART0 RX Interrupt Enable\r
    SBIT(URX1IE,   0xA8, 3); // USART1 RX Interrupt Enable\r
-   SBIT(ENCIE,    0xA8, 4); // AES Encryption/Decryption Interrupt Enable \r
-   SBIT(STIE,     0xA8, 5); // Sleep Timer Interrupt Enable \r
-   SBIT(EA,       0xA8, 7); // Global Interrupt Enable \r
+   SBIT(ENCIE,    0xA8, 4); // AES Encryption/Decryption Interrupt Enable\r
+   SBIT(STIE,     0xA8, 5); // Sleep Timer Interrupt Enable\r
+   SBIT(EA,       0xA8, 7); // Global Interrupt Enable\r
 SFR(IP0,      0xA9) // Interrupt Priority 0\r
 SFR(FWT,      0xAB) // Flash Write Timing\r
 SFR(FADDRL,   0xAC) // Flash Address Low Byte\r
@@ -141,12 +142,12 @@ SFR(ADCCON1,  0xB4) // ADC Control 1
 SFR(ADCCON2,  0xB5) // ADC Control 2\r
 SFR(ADCCON3,  0xB6) // ADC Control 3\r
 SFR(IEN1,     0xB8) // Interrupt Enable 1\r
-   SBIT(DMAIE,    0xB8, 0); // DMA Transfer Interrupt Enable \r
-   SBIT(T1IE,     0xB8, 1); // Timer 1 Interrupt Enable \r
-   SBIT(T2IE,     0xB8, 2); // Timer 2 Interrupt Enable \r
-   SBIT(T3IE,     0xB8, 3); // Timer 3 Interrupt Enable \r
-   SBIT(T4IE,     0xB8, 4); // Timer 4 Interrupt Enable \r
-   SBIT(P0IE,     0xB8, 5); // Port 0 Interrupt Enable \r
+   SBIT(DMAIE,    0xB8, 0); // DMA Transfer Interrupt Enable\r
+   SBIT(T1IE,     0xB8, 1); // Timer 1 Interrupt Enable\r
+   SBIT(T2IE,     0xB8, 2); // Timer 2 Interrupt Enable\r
+   SBIT(T3IE,     0xB8, 3); // Timer 3 Interrupt Enable\r
+   SBIT(T4IE,     0xB8, 4); // Timer 4 Interrupt Enable\r
+   SBIT(P0IE,     0xB8, 5); // Port 0 Interrupt Enable\r
 SFR(IP1,      0xB9) // Interrupt Priority 1\r
 SFR(ADCL,     0xBA) // ADC Data Low\r
 SFR(ADCH,     0xBB) // ADC Data High\r
@@ -154,13 +155,13 @@ SFR(RNDL,     0xBC) // Random Number Generator Data Low Byte
 SFR(RNDH,     0xBD) // Random Number Generator Data High Byte\r
 SFR(SLEEP,    0xBE) // Sleep Mode Control\r
 SFR(IRCON,    0xC0) // Interrupt Flags 4\r
-   SBIT(DMAIF,    0xC0, 0); // DMA Complete Interrupt Flag \r
-   SBIT(T1IF,     0xC0, 1); // Timer 1 Interrupt Flag \r
-   SBIT(T2IF,     0xC0, 2); // Timer 2 Interrupt Flag \r
-   SBIT(T3IF,     0xC0, 3); // Timer 3 Interrupt Flag \r
-   SBIT(T4IF,     0xC0, 4); // Timer 4 Interrupt Flag \r
-   SBIT(P0IF,     0xC0, 5); // Port 0 Interrupt Flag \r
-   SBIT(STIF,     0xC0, 7); // Sleep Timer Interrupt Flag \r
+   SBIT(DMAIF,    0xC0, 0); // DMA Complete Interrupt Flag\r
+   SBIT(T1IF,     0xC0, 1); // Timer 1 Interrupt Flag\r
+   SBIT(T2IF,     0xC0, 2); // Timer 2 Interrupt Flag\r
+   SBIT(T3IF,     0xC0, 3); // Timer 3 Interrupt Flag\r
+   SBIT(T4IF,     0xC0, 4); // Timer 4 Interrupt Flag\r
+   SBIT(P0IF,     0xC0, 5); // Port 0 Interrupt Flag\r
+   SBIT(STIF,     0xC0, 7); // Sleep Timer Interrupt Flag\r
 SFR(U0DBUF,   0xC1) // USART 0 Receive/Transmit Data Buffer\r
 SFR(U0BAUD,   0xC2) // USART 0 Baud Rate Control\r
 SFR(T2CNF,    0xC3) // Timer 2 Configuration\r
@@ -176,14 +177,14 @@ SFR(T3CC0,    0xCD) // Timer 3 Channel 0 Capture/Compare Value
 SFR(T3CCTL1,  0xCE) // Timer 3 Channel 1 Capture/Compare Control\r
 SFR(T3CC1,    0xCF) // Timer 3 Channel 1 Capture/Compare Value\r
 SFR(PSW,      0xD0) // Program Status Word\r
-   SBIT(P,        0xD0, 0); // Parity Flag \r
+   SBIT(P,        0xD0, 0); // Parity Flag\r
    SBIT(F1,       0xD0, 1); // User-Defined Flag\r
-   SBIT(OV,       0xD0, 2); // Overflow Flag \r
-   SBIT(RS0,      0xD0, 3); // Register Bank Select 0 \r
-   SBIT(RS1,      0xD0, 4); // Register Bank Select 1 \r
+   SBIT(OV,       0xD0, 2); // Overflow Flag\r
+   SBIT(RS0,      0xD0, 3); // Register Bank Select 0\r
+   SBIT(RS1,      0xD0, 4); // Register Bank Select 1\r
    SBIT(F0,       0xD0, 5); // User-Defined Flag\r
-   SBIT(AC,       0xD0, 6); // Auxiliary Carry Flag \r
-   SBIT(CY,       0xD0, 7); // Carry Flag \r
+   SBIT(AC,       0xD0, 6); // Auxiliary Carry Flag\r
+   SBIT(CY,       0xD0, 7); // Carry Flag\r
 SFR(DMAIRQ,   0xD1) // DMA Interrupt Flag\r
 SFR(DMA1CFGL, 0xD2) // DMA Channel 1-4 Configuration Address Low Byte\r
 SFR(DMA1CFGH, 0xD3) // DMA Channel 1-4 Configuration Address High Byte\r
@@ -223,11 +224,11 @@ SFR(T1CCTL0,  0xE5) // Timer 1 Channel 0 Capture/Compare Control
 SFR(T1CCTL1,  0xE6) // Timer 1 Channel 1 Capture/Compare Control\r
 SFR(T1CCTL2,  0xE7) // Timer 1 Channel 2 Capture/Compare Control\r
 SFR(IRCON2,   0xE8) // Interrupt Flags 5\r
-   SBIT(P2IF,     0xE8, 0); // Port 2 Interrupt Flag \r
-   SBIT(UTX0IF,   0xE8, 1); // USART0 TX Interrupt Flag \r
-   SBIT(UTX1IF,   0xE8, 2); // USART1 TX Interrupt Flag \r
-   SBIT(P1IF,     0xE8, 3); // Port 1 Interrupt Flag \r
-   SBIT(WDTIF,    0xE8, 4); // Watchdog Timer Interrupt Flag \r
+   SBIT(P2IF,     0xE8, 0); // Port 2 Interrupt Flag\r
+   SBIT(UTX0IF,   0xE8, 1); // USART0 TX Interrupt Flag\r
+   SBIT(UTX1IF,   0xE8, 2); // USART1 TX Interrupt Flag\r
+   SBIT(P1IF,     0xE8, 3); // Port 1 Interrupt Flag\r
+   SBIT(WDTIF,    0xE8, 4); // Watchdog Timer Interrupt Flag\r
 SFR(RFIF,     0xE9) // RF Interrupt Flags\r
 SFR(T4CNT,    0xEA) // Timer 4 Counter\r
 SFR(T4CTL,    0xEB) // Timer 4 Control\r