~usrp2_base();
std::string mac_addr() const;
+ std::string ifc_name() const;
%rename(_real_fpga_master_clock_freq) fpga_master_clock_freq;
bool fpga_master_clock_freq(long *freq);
bool sync_to_pps();
return d_u2->mac_addr();
}
+std::string
+usrp2_base::ifc_name() const
+{
+ return d_u2->ifc_name();
+}
+
bool
usrp2_base::fpga_master_clock_freq(long *freq) const
{
*/
std::string mac_addr() const;
+ /*!
+ * \brief Get interface name used to communicat with USRP2
+ */
+ std::string ifc_name() const;
+
/*!
* \brief Get USRP2 master clock rate
*/
*/
std::string mac_addr();
+ /*!
+ * Returns the GbE interface name associated with this USRP
+ */
+ std::string ifc_name();
+
/*
* ----------------------------------------------------------------
* Rx configuration and control
return d_impl->mac_addr();
}
+ std::string
+ usrp2::ifc_name()
+ {
+ return d_impl->ifc_name();
+ }
+
// Receive
bool
usrp2::impl::impl(const std::string &ifc, props *p)
- : d_eth_buf(new eth_buffer()), d_pf(0), d_bg_thread(0), d_bg_running(false),
- d_rx_seqno(-1), d_tx_seqno(0), d_next_rid(0),
+ : d_eth_buf(new eth_buffer()), d_ifc_name(ifc), d_pf(0), d_bg_thread(0),
+ d_bg_running(false), d_rx_seqno(-1), d_tx_seqno(0), d_next_rid(0),
d_num_rx_frames(0), d_num_rx_missing(0), d_num_rx_overruns(0), d_num_rx_bytes(0),
d_num_enqueued(0), d_enqueued_mutex(), d_bg_pending_cond(&d_enqueued_mutex),
d_channel_rings(NCHANS), d_tx_interp(0), d_rx_decim(0)
static const size_t NCHANS = 32;
eth_buffer *d_eth_buf;
+ std::string d_ifc_name;
pktfilter *d_pf;
std::string d_addr; // FIXME: use u2_mac_addr_t instead
usrp2_thread *d_bg_thread;
void bg_loop();
std::string mac_addr() const { return d_addr; } // FIXME: convert from u2_mac_addr_t
+ std::string ifc_name() const { return d_ifc_name; }
// Rx