*.lo
*.py[oc]
*.gz
+*.exe
*.patch
*~
\#*#
then
AC_PROG_F77
AC_F77_LIBRARY_LDFLAGS
- AC_PROG_CC dnl bux fix to restore $ac_ext
fi
+ AC_PROG_CC dnl bux fix to restore $ac_ext
])
])
fi
- if x$USB_INCLUDEDIR != x; then
- USB_INCLUDES=-I$USB_INCLUDEDIR
- fi
-
if test x$libusbok = xyes; then
+ if test x$USB_INCLUDEDIR != x; then
+ USB_INCLUDES="-I$USB_INCLUDEDIR"
+ AC_SUBST(USB_INCLUDES)
+ fi
AC_SUBST(USB_LIBS)
ifelse([$2], , :, [$2])
else
libgnuradio_atsc_la_LIBADD = \
$(GNURADIO_CORE_LA)
+libgnuradio_atsc_la_LDFLAGS = \
+ $(NO_UNDEFINED)
+
noinst_LTLIBRARIES = libgnuradio-atsc-qa.la
libgnuradio_atsc_qa_la_SOURCES = \
libgnuradio_atsc_qa_la_LIBADD = \
$(GNURADIO_CORE_LA)
+libgnuradio_atsc_qa_la_LDFLAGS = \
+ $(NO_UNDEFINED)
+
# These headers get installed in ${prefix}/include/gnuradio
grinclude_HEADERS = \
renderer = gtk.CellRendererText()
column = gtk.TreeViewColumn('Blocks', renderer, text=NAME_INDEX)
self.treeview.append_column(column)
+ #setup the search
+ self.treeview.set_enable_search(True)
+ self.treeview.set_search_equal_func(self._handle_search)
#try to enable the tooltips (available in pygtk 2.12 and above)
try: self.treeview.set_tooltip_column(DOC_INDEX)
except: pass
############################################################
## Event Handlers
############################################################
+ def _handle_search(self, model, column, key, iter):
+ #determine which blocks match the search key
+ blocks = self.get_flow_graph().get_parent().get_blocks()
+ matching_blocks = filter(lambda b: key in b.get_key() or key in b.get_name().lower(), blocks)
+ #remove the old search category
+ try: self.treestore.remove(self._categories.pop((self._search_category, )))
+ except (KeyError, AttributeError): pass #nothing to remove
+ #create a search category
+ if not matching_blocks: return
+ self._search_category = 'Search: %s'%key
+ for block in matching_blocks: self.add_block(self._search_category, block)
+ #expand the search category
+ path = self.treestore.get_path(self._categories[(self._search_category, )])
+ self.treeview.collapse_all()
+ self.treeview.expand_row(path, open_all=False)
+
def _handle_drag_get_data(self, widget, drag_context, selection_data, info, time):
"""
Handle a drag and drop by setting the key to the selection object.
#extract descriptions
comp_name = extract_txt(xml.xpath(DOXYGEN_NAME_XPATH)[0]).strip()
comp_name = ' --- ' + comp_name + ' --- '
- if re.match('(gr|usrp2|trellis)_.*', key):
+ if re.match('(gr|usrp2|trellis|noaa)_.*', key):
brief_desc = extract_txt(xml.xpath(DOXYGEN_BRIEFDESC_GR_XPATH)[0]).strip()
detailed_desc = extract_txt(xml.xpath(DOXYGEN_DETAILDESC_GR_XPATH)[0]).strip()
else:
* remove blocks in block tree covered by doxygen
* param editor, expand entry boxes in focus
* change param dialog to panel within main window
-* search for blocks in category window
* gui grid editor for configuring grid params/placing wxgui plots and controls
* drag from one port to another to connect
* per parameter docs
# ----------------------------------------------------------------
test_gruel_SOURCES = test_gruel.cc
-test_gruel_LDADD = libgruel.la pmt/libpmt-qa.la
+test_gruel_LDADD = pmt/libpmt-qa.la libgruel.la
#!/usr/bin/env python
#
-# Copyright 2005,2007 Free Software Foundation, Inc.
-#
+# Copyright 2005,2007,2009 Free Software Foundation, Inc.
+#
# This file is part of GNU Radio
-#
+#
# GNU Radio is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
-#
+#
# GNU Radio is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License
# along with GNU Radio; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
-#
+#
from usrpm.usrp_prims import *
from optparse import OptionParser
'lftx' : ((LF_TX, 0x0000), None),
'lfrx' : (None, (LF_RX, 0x0000)),
'wbx_lo' : ((WBX_LO_TX, 0x0000), (WBX_LO_RX, 0x0000)),
+ 'wbx_ng' : ((WBX_NG_TX, 0x0000), (WBX_NG_RX, 0x0000)),
'xcvr2450' : ((XCVR2450_TX, 0x0000), (XCVR2450_RX, 0x0000)),
'experimental_tx' : ((EXPERIMENTAL_TX, 0x0000), None),
'experimental_rx' : (None, (EXPERIMENTAL_RX, 0x0000)),
if not e:
print "%s: no d'board, skipped" % (slot_name,)
return True
-
+
if not force and (sum (map (ord, e)) & 0xff) == 0 and ord (e[0]) == 0xDB:
print "%s: already initialized, skipped" % (slot_name,)
return True
-
+
if not write_dboard_eeprom (u, i2c_addr, dbid, oe):
print "%s: failed to write d'board EEPROM" % (slot_name,)
return False
if __name__ == "__main__":
main ()
-
+
#
# Copyright 2009 Free Software Foundation, Inc.
-#
+#
# This file is part of GNU Radio
-#
+#
# GNU Radio is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
-#
+#
# GNU Radio is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License
# along with GNU Radio; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
-#
+#
include $(top_srcdir)/Makefile.common
db_flexrf.h \
db_flexrf_mimo.h \
db_tv_rx.h \
- db_tv_rx_mimo.h \
+ db_tv_rx_mimo.h \
+ db_wbxng.h \
db_xcvr2450.h \
libusb_types.h \
usrp_basic.h \
--- /dev/null
+/* -*- c++ -*- */
+//
+// Copyright 2009 Free Software Foundation, Inc.
+//
+// This file is part of GNU Radio
+//
+// GNU Radio is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either asversion 3, or (at your option)
+// any later version.
+//
+// GNU Radio is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with GNU Radio; see the file COPYING. If not, write to
+// the Free Software Foundation, Inc., 51 Franklin Street,
+// Boston, MA 02110-1301, USA.
+
+#ifndef INCLUDED_DB_WBXNG_H
+#define INCLUDED_DB_WBXNG_H
+
+#include <usrp/db_base.h>
+#include <cmath>
+
+class adf4350;
+
+class wbxng_base : public db_base
+{
+public:
+ wbxng_base(usrp_basic_sptr usrp, int which, int _power_on=0);
+ ~wbxng_base();
+
+ struct freq_result_t set_freq(double freq);
+
+ bool is_quadrature();
+ double freq_min();
+ double freq_max();
+
+protected:
+ bool _lock_detect();
+ bool _set_pga(float pga_gain);
+
+ int power_on() { return d_power_on; }
+ int power_off() { return 0; }
+
+ bool d_first;
+ int d_spi_format;
+ int d_spi_enable;
+ int d_power_on;
+ int d_PD;
+
+ adf4350 *d_common;
+};
+
+// ----------------------------------------------------------------
+
+class wbxng_base_tx : public wbxng_base
+{
+protected:
+ void shutdown();
+
+public:
+ wbxng_base_tx(usrp_basic_sptr usrp, int which, int _power_on=0);
+ ~wbxng_base_tx();
+
+ float gain_min();
+ float gain_max();
+ float gain_db_per_step();
+
+ bool set_auto_tr(bool on);
+ bool set_enable(bool on);
+ bool set_gain(float gain);
+};
+
+class wbxng_base_rx : public wbxng_base
+{
+protected:
+ void shutdown();
+ bool _set_attn(float attn);
+
+public:
+ wbxng_base_rx(usrp_basic_sptr usrp, int which, int _power_on=0);
+ ~wbxng_base_rx();
+
+ bool set_auto_tr(bool on);
+ bool select_rx_antenna(int which_antenna);
+ bool select_rx_antenna(const std::string &which_antenna);
+ bool set_gain(float gain);
+};
+
+// ----------------------------------------------------------------
+
+class db_wbxng_tx : public wbxng_base_tx
+{
+ public:
+ db_wbxng_tx(usrp_basic_sptr usrp, int which);
+ ~db_wbxng_tx();
+};
+
+class db_wbxng_rx : public wbxng_base_rx
+{
+public:
+ db_wbxng_rx(usrp_basic_sptr usrp, int which);
+ ~db_wbxng_rx();
+
+ float gain_min();
+ float gain_max();
+ float gain_db_per_step();
+ bool i_and_q_swapped();
+};
+
+#endif /* INCLUDED_DB_WBXNG_H */
#
# USRP - Universal Software Radio Peripheral
-#
+#
# Copyright (C) 2003,2004,2006,2007,2008,2009 Free Software Foundation, Inc.
-#
+#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
-#
+#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
-#
+#
include $(top_srcdir)/Makefile.common
usrp_local_sighandler.cc \
usrp_prims_common.cc \
usrp_standard.cc \
+ db_wbxng_adf4350.cc \
+ db_wbxng_adf4350_regs.cc \
db_boards.cc \
db_base.cc \
db_basic.cc \
db_flexrf.cc \
db_flexrf_mimo.cc \
db_dbs_rx.cc \
+ db_wbxng.cc \
db_xcvr2450.cc \
db_dtt754.cc \
db_dtt768.cc \
db_base_impl.h \
db_boards.h \
db_util.h \
+ db_wbxng_adf4350.h \
+ db_wbxng_adf4350_regs.h \
fusb.h \
fusb_darwin.h \
fusb_generic.h \
/* -*- c++ -*- */
//
// Copyright 2008,2009 Free Software Foundation, Inc.
-//
+//
// This file is part of GNU Radio
-//
+//
// GNU Radio is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either asversion 3, or (at your option)
// any later version.
-//
+//
// GNU Radio is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
-//
+//
// You should have received a copy of the GNU General Public License
// along with GNU Radio; see the file COPYING. If not, write to
// the Free Software Foundation, Inc., 51 Franklin Street,
#include <usrp/db_dbs_rx.h>
#include <usrp/db_flexrf.h>
#include <usrp/db_flexrf_mimo.h>
+#include <usrp/db_wbxng.h>
#include <usrp/db_xcvr2450.h>
#include <usrp/db_dtt754.h>
#include <usrp/db_dtt768.h>
db.push_back(db_base_sptr(new db_lf_rx(usrp, which_side, 1)));
db.push_back(db_base_sptr(new db_lf_rx(usrp, which_side, 2)));
break;
-
+
case(USRP_DBID_DBS_RX):
db.push_back(db_base_sptr(new db_dbs_rx(usrp, which_side)));
break;
case(USRP_DBID_XCVR2450_RX):
db.push_back(db_base_sptr(new db_xcvr2450_rx(usrp, which_side)));
break;
-
+
#if 0 // FIXME wbx doesn't compile
case(USRP_DBID_WBX_LO_TX):
db.push_back(db_base_sptr(new db_wbx_lo_tx(usrp, which_side)));
break;
#endif
+ case(USRP_DBID_WBX_NG_TX):
+ db.push_back(db_base_sptr(new db_wbxng_tx(usrp, which_side)));
+ break;
+ case(USRP_DBID_WBX_NG_RX):
+ db.push_back(db_base_sptr(new db_wbxng_rx(usrp, which_side)));
+ break;
+
case(USRP_DBID_DTT754):
db.push_back(db_base_sptr(new db_dtt754(usrp, which_side)));
break;
db.push_back(db_base_sptr(new db_basic_rx(usrp, which_side, 1)));
}
break;
-
+
case(-2):
default:
if (boost::dynamic_pointer_cast<usrp_basic_tx>(usrp)){
--- /dev/null
+//
+// Copyright 2008,2009 Free Software Foundation, Inc.
+//
+// This file is part of GNU Radio
+//
+// GNU Radio is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either asversion 3, or (at your option)
+// any later version.
+//
+// GNU Radio is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with GNU Radio; see the file COPYING. If not, write to
+// the Free Software Foundation, Inc., 51 Franklin Street,
+// Boston, MA 02110-1301, USA.
+
+#include <usrp/db_wbxng.h>
+#include "db_wbxng_adf4350.h"
+#include <db_base_impl.h>
+#include <stdio.h>
+
+// d'board i/o pin defs
+// Tx and Rx have shared defs, but different i/o regs
+#define ENABLE_5 (1 << 7) // enables 5.0V power supply
+#define ENABLE_33 (1 << 6) // enables 3.3V supply
+#define RX_TXN (1 << 5) // Tx only: T/R antenna switch for TX/RX port
+#define RX2_RX1N (1 << 5) // Rx only: antenna switch between RX2 and TX/RX port
+#define RXBB_EN (1 << 4)
+#define TXMOD_EN (1 << 4)
+#define PLL_CE (1 << 3)
+#define PLL_PDBRF (1 << 2)
+#define PLL_MUXOUT (1 << 1)
+#define PLL_LOCK_DETECT (1 << 0)
+
+// RX Attenuator constants
+#define ATTN_SHIFT 8
+#define ATTN_MASK (63 << ATTN_SHIFT)
+
+wbxng_base::wbxng_base(usrp_basic_sptr _usrp, int which, int _power_on)
+ : db_base(_usrp, which), d_power_on(_power_on)
+{
+ /*
+ @param usrp: instance of usrp.source_c
+ @param which: which side: 0 or 1 corresponding to side A or B respectively
+ @type which: int
+ */
+
+ usrp()->_write_oe(d_which, 0, 0xffff); // turn off all outputs
+
+ d_first = true;
+ d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0;
+
+ _enable_refclk(false); // disable refclk
+
+ set_auto_tr(false);
+}
+
+wbxng_base::~wbxng_base()
+{
+ if (d_common)
+ delete d_common;
+}
+
+struct freq_result_t
+wbxng_base::set_freq(double freq)
+{
+ /*
+ @returns (ok, actual_baseband_freq) where:
+ ok is True or False and indicates success or failure,
+ actual_baseband_freq is the RF frequency that corresponds to DC in the IF.
+ */
+
+ freq_t int_freq = freq_t(freq);
+ bool ok = d_common->_set_freq(int_freq*2);
+ double freq_result = (double) d_common->_get_freq()/2.0;
+ struct freq_result_t args = {ok, freq_result};
+
+ /* Wait before reading Lock Detect*/
+ timespec t;
+ t.tv_sec = 0;
+ t.tv_nsec = 10000000;
+ nanosleep(&t, NULL);
+
+ fprintf(stderr,"Setting WBXNG frequency, requested %d, obtained %f, lock_detect %d\n",
+ int_freq, freq_result, d_common->_get_locked());
+
+ // FIXME
+ // Offsetting the LO helps get the Tx carrier leakage out of the way.
+ // This also ensures that on Rx, we're not getting hosed by the
+ // FPGA's DC removal loop's time constant. We were seeing a
+ // problem when running with discontinuous transmission.
+ // Offsetting the LO made the problem go away.
+ //freq += d_lo_offset;
+
+ return args;
+}
+
+bool
+wbxng_base::_set_pga(float pga_gain)
+{
+ if(d_which == 0) {
+ usrp()->set_pga(0, pga_gain);
+ usrp()->set_pga(1, pga_gain);
+ }
+ else {
+ usrp()->set_pga(2, pga_gain);
+ usrp()->set_pga(3, pga_gain);
+ }
+ return true;
+}
+
+bool
+wbxng_base::is_quadrature()
+{
+ /*
+ Return True if this board requires both I & Q analog channels.
+
+ This bit of info is useful when setting up the USRP Rx mux register.
+ */
+ return true;
+}
+
+double
+wbxng_base::freq_min()
+{
+ return (double) d_common->_get_min_freq()/2.0;
+}
+
+double
+wbxng_base::freq_max()
+{
+ return (double) d_common->_get_max_freq()/2.0;
+}
+
+// ----------------------------------------------------------------
+
+wbxng_base_tx::wbxng_base_tx(usrp_basic_sptr _usrp, int which, int _power_on)
+ : wbxng_base(_usrp, which, _power_on)
+{
+ /*
+ @param usrp: instance of usrp.sink_c
+ @param which: 0 or 1 corresponding to side TX_A or TX_B respectively.
+ */
+
+ if(which == 0) {
+ d_spi_enable = SPI_ENABLE_TX_A;
+ }
+ else {
+ d_spi_enable = SPI_ENABLE_TX_B;
+ }
+
+ d_common = new adf4350(_usrp, d_which, d_spi_enable);
+
+ // FIXME: power up the transmit side, but don't enable the mixer
+ usrp()->_write_oe(d_which,(RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5), (RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5));
+ usrp()->write_io(d_which, (power_on()|RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5), (RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5));
+ fprintf(stderr,"Setting WBXNG TXMOD on");
+ //set_lo_offset(4e6);
+
+ set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
+}
+
+wbxng_base_tx::~wbxng_base_tx()
+{
+ shutdown();
+}
+
+
+void
+wbxng_base_tx::shutdown()
+{
+ // fprintf(stderr, "wbxng_base_tx::shutdown d_is_shutdown = %d\n", d_is_shutdown);
+
+ if (!d_is_shutdown){
+ d_is_shutdown = true;
+ // do whatever there is to do to shutdown
+
+ // Power down and leave the T/R switch in the R position
+ usrp()->write_io(d_which, (power_off()|RX_TXN), (RX_TXN|ENABLE_33|ENABLE_5));
+
+ // Power down VCO/PLL
+ d_common->_enable(false);
+
+ /*
+ _write_control(_compute_control_reg());
+ */
+ _enable_refclk(false); // turn off refclk
+ set_auto_tr(false);
+ }
+}
+
+bool
+wbxng_base_tx::set_auto_tr(bool on)
+{
+ bool ok = true;
+ if(on) {
+ ok &= set_atr_mask (RX_TXN | ENABLE_33 | ENABLE_5);
+ ok &= set_atr_txval(0 | ENABLE_33 | ENABLE_5);
+ ok &= set_atr_rxval(RX_TXN | 0);
+ }
+ else {
+ ok &= set_atr_mask (0);
+ ok &= set_atr_txval(0);
+ ok &= set_atr_rxval(0);
+ }
+ return ok;
+}
+
+bool
+wbxng_base_tx::set_enable(bool on)
+{
+ /*
+ Enable transmitter if on is true
+ */
+
+ int v;
+ int mask = RX_TXN | ENABLE_5 | ENABLE_33;
+ if(on) {
+ v = ENABLE_5 | ENABLE_33;
+ }
+ else {
+ v = RX_TXN;
+ }
+ return usrp()->write_io(d_which, v, mask);
+}
+
+float
+wbxng_base_tx::gain_min()
+{
+ return usrp()->pga_max();
+}
+
+float
+wbxng_base_tx::gain_max()
+{
+ return usrp()->pga_max() + 25.0;
+}
+
+float
+wbxng_base_tx::gain_db_per_step()
+{
+ return 1;
+}
+
+bool
+wbxng_base_tx::set_gain(float gain)
+{
+ /*
+ Set the gain.
+
+ @param gain: gain in decibels
+ @returns True/False
+ */
+
+ // clamp gain
+ gain = std::max(gain_min(), std::min(gain, gain_max()));
+
+ float pga_gain, agc_gain;
+ float V_maxgain, V_mingain, V_fullscale, dac_value;
+
+ float maxgain = gain_max() - usrp()->pga_max();
+ float mingain = gain_min();
+ if(gain > maxgain) {
+ pga_gain = gain-maxgain;
+ assert(pga_gain <= usrp()->pga_max());
+ agc_gain = maxgain;
+ }
+ else {
+ pga_gain = 0;
+ agc_gain = gain;
+ }
+
+ V_maxgain = 0.7;
+ V_mingain = 1.4;
+ V_fullscale = 3.3;
+ dac_value = (agc_gain*(V_maxgain-V_mingain)/(maxgain-mingain) + V_mingain)*4096/V_fullscale;
+
+ fprintf(stderr, "TXGAIN: %f dB, Dac Code: %d, Voltage: %f\n", gain, int(dac_value), float((dac_value/4096.0)*V_fullscale));
+ assert(dac_value>=0 && dac_value<4096);
+
+ return (usrp()->write_aux_dac(d_which, 0, int(dac_value))
+ && _set_pga(int(pga_gain)));
+}
+
+
+/**************************************************************************/
+
+
+wbxng_base_rx::wbxng_base_rx(usrp_basic_sptr _usrp, int which, int _power_on)
+ : wbxng_base(_usrp, which, _power_on)
+{
+ /*
+ @param usrp: instance of usrp.source_c
+ @param which: 0 or 1 corresponding to side RX_A or RX_B respectively.
+ */
+
+ if(which == 0) {
+ d_spi_enable = SPI_ENABLE_RX_A;
+ }
+ else {
+ d_spi_enable = SPI_ENABLE_RX_B;
+ }
+
+ d_common = new adf4350(_usrp, d_which, d_spi_enable);
+
+ usrp()->_write_oe(d_which, (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5), (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
+ usrp()->write_io(d_which, (power_on()|RX2_RX1N|RXBB_EN|ENABLE_33|ENABLE_5), (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
+ fprintf(stderr,"Setting WBXNG RXBB on");
+
+ // set up for RX on TX/RX port
+ select_rx_antenna("TX/RX");
+
+ bypass_adc_buffers(true);
+
+ /*
+ set_lo_offset(-4e6);
+ */
+}
+
+wbxng_base_rx::~wbxng_base_rx()
+{
+ shutdown();
+}
+
+void
+wbxng_base_rx::shutdown()
+{
+ // fprintf(stderr, "wbxng_base_rx::shutdown d_is_shutdown = %d\n", d_is_shutdown);
+
+ if (!d_is_shutdown){
+ d_is_shutdown = true;
+ // do whatever there is to do to shutdown
+
+ // Power down
+ usrp()->common_write_io(C_RX, d_which, power_off(), (ENABLE_33|ENABLE_5));
+
+ // Power down VCO/PLL
+ d_common->_enable(false);
+
+ // fprintf(stderr, "wbxng_base_rx::shutdown before _write_control\n");
+ //_write_control(_compute_control_reg());
+
+ // fprintf(stderr, "wbxng_base_rx::shutdown before _enable_refclk\n");
+ _enable_refclk(false); // turn off refclk
+
+ // fprintf(stderr, "wbxng_base_rx::shutdown before set_auto_tr\n");
+ set_auto_tr(false);
+
+ // fprintf(stderr, "wbxng_base_rx::shutdown after set_auto_tr\n");
+ }
+}
+
+bool
+wbxng_base_rx::set_auto_tr(bool on)
+{
+ bool ok = true;
+ if(on) {
+ ok &= set_atr_mask (ENABLE_33|ENABLE_5);
+ ok &= set_atr_txval( 0);
+ ok &= set_atr_rxval(ENABLE_33|ENABLE_5);
+ }
+ else {
+ ok &= set_atr_mask (0);
+ ok &= set_atr_txval(0);
+ ok &= set_atr_rxval(0);
+ }
+ return true;
+}
+
+bool
+wbxng_base_rx::select_rx_antenna(int which_antenna)
+{
+ /*
+ Specify which antenna port to use for reception.
+ @param which_antenna: either 'TX/RX' or 'RX2'
+ */
+
+ if(which_antenna == 0) {
+ usrp()->write_io(d_which, 0,RX2_RX1N);
+ }
+ else if(which_antenna == 1) {
+ usrp()->write_io(d_which, RX2_RX1N, RX2_RX1N);
+ }
+ else {
+ return false;
+ }
+ return true;
+}
+
+bool
+wbxng_base_rx::select_rx_antenna(const std::string &which_antenna)
+{
+ /*
+ Specify which antenna port to use for reception.
+ @param which_antenna: either 'TX/RX' or 'RX2'
+ */
+
+
+ if(which_antenna == "TX/RX") {
+ usrp()->write_io(d_which, 0, RX2_RX1N);
+ }
+ else if(which_antenna == "RX2") {
+ usrp()->write_io(d_which, RX2_RX1N, RX2_RX1N);
+ }
+ else {
+ return false;
+ }
+
+ return true;
+}
+
+bool
+wbxng_base_rx::set_gain(float gain)
+{
+ /*
+ Set the gain.
+
+ @param gain: gain in decibels
+ @returns True/False
+ */
+
+ // clamp gain
+ gain = std::max(gain_min(), std::min(gain, gain_max()));
+
+ float pga_gain, agc_gain;
+
+ float maxgain = gain_max() - usrp()->pga_max();
+ float mingain = gain_min();
+ if(gain > maxgain) {
+ pga_gain = gain-maxgain;
+ assert(pga_gain <= usrp()->pga_max());
+ agc_gain = maxgain;
+ }
+ else {
+ pga_gain = 0;
+ agc_gain = gain;
+ }
+
+ return _set_attn(maxgain-agc_gain) && _set_pga(int(pga_gain));
+}
+
+bool
+wbxng_base_rx::_set_attn(float attn)
+{
+ int attn_code = int(floor(attn/0.5));
+ unsigned int iobits = (~attn_code) << ATTN_SHIFT;
+ fprintf(stderr, "Attenuation: %f dB, Code: %d, IO Bits %x, Mask: %x \n", attn, attn_code, iobits & ATTN_MASK, ATTN_MASK);
+ return usrp()->write_io(d_which, iobits, ATTN_MASK);
+}
+
+// ----------------------------------------------------------------
+
+db_wbxng_tx::db_wbxng_tx(usrp_basic_sptr usrp, int which)
+ : wbxng_base_tx(usrp, which)
+{
+}
+
+db_wbxng_tx::~db_wbxng_tx()
+{
+}
+
+db_wbxng_rx::db_wbxng_rx(usrp_basic_sptr usrp, int which)
+ : wbxng_base_rx(usrp, which)
+{
+ set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
+}
+
+db_wbxng_rx::~db_wbxng_rx()
+{
+}
+
+float
+db_wbxng_rx::gain_min()
+{
+ return usrp()->pga_min();
+}
+
+float
+db_wbxng_rx::gain_max()
+{
+ return usrp()->pga_max()+30.5;
+}
+
+float
+db_wbxng_rx::gain_db_per_step()
+{
+ return 0.05;
+}
+
+
+bool
+db_wbxng_rx::i_and_q_swapped()
+{
+ return false;
+}
--- /dev/null
+//
+// Copyright 2009 Free Software Foundation, Inc.
+//
+// This file is part of GNU Radio
+//
+// GNU Radio is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either asversion 3, or (at your option)
+// any later version.
+//
+// GNU Radio is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with GNU Radio; see the file COPYING. If not, write to
+// the Free Software Foundation, Inc., 51 Franklin Street,
+// Boston, MA 02110-1301, USA.
+
+#ifdef HAVE_CONFIG_H
+#include <config.h>
+#endif
+
+#include "db_wbxng_adf4350.h"
+#include <db_base_impl.h>
+#include <stdio.h>
+
+#define INPUT_REF_FREQ FREQ_C(64e6)
+#define DIV_ROUND(num, denom) (((num) + ((denom)/2))/(denom))
+#define FREQ_C(freq) uint64_t(freq)
+#define INPUT_REF_FREQ_2X (2*INPUT_REF_FREQ) /* input ref freq with doubler turned on */
+#define MIN_INT_DIV uint16_t(23) /* minimum int divider, prescaler 4/5 only */
+#define MAX_RF_DIV uint8_t(16) /* max rf divider, divides rf output */
+#define MIN_VCO_FREQ FREQ_C(2.2e9) /* minimum vco freq */
+#define MAX_VCO_FREQ FREQ_C(4.4e9) /* minimum vco freq */
+#define MAX_FREQ MAX_VCO_FREQ /* upper bound freq (rf div = 1) */
+#define MIN_FREQ DIV_ROUND(MIN_VCO_FREQ, MAX_RF_DIV) /* calculated lower bound freq */
+
+#define CE_PIN (1 << 3)
+#define PDB_RF_PIN (1 << 2)
+#define MUX_PIN (1 << 1)
+#define LD_PIN (1 << 0)
+
+adf4350::adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable)
+{
+ /* Initialize the pin directions. */
+
+ d_usrp = _usrp;
+ d_which = _which;
+ d_spi_enable = _spi_enable;
+ d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0;
+
+ d_regs = new adf4350_regs(this);
+
+ /* Outputs */
+ d_usrp->_write_oe(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
+ d_usrp->write_io(d_which, (0), (CE_PIN | PDB_RF_PIN));
+
+ /* Initialize the pin levels. */
+ _enable(true);
+ /* Initialize the registers. */
+ d_regs->_load_register(5);
+ d_regs->_load_register(4);
+ d_regs->_load_register(3);
+ d_regs->_load_register(2);
+ d_regs->_load_register(1);
+ d_regs->_load_register(0);
+}
+
+adf4350::~adf4350()
+{
+ delete d_regs;
+}
+
+freq_t
+adf4350::_get_max_freq(void)
+{
+ return MAX_FREQ;
+}
+
+freq_t
+adf4350::_get_min_freq(void)
+{
+ return MIN_FREQ;
+}
+
+bool
+adf4350::_get_locked(void)
+{
+ return d_usrp->read_io(d_which) & LD_PIN;
+}
+
+void
+adf4350::_enable(bool enable)
+{
+ if (enable){ /* chip enable */
+ d_usrp->write_io(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
+ }else{
+ d_usrp->write_io(d_which, 0, (CE_PIN | PDB_RF_PIN));
+ }
+}
+
+void
+adf4350::_write(uint8_t addr, uint32_t data)
+{
+ data |= addr;
+
+ // create str from data here
+ char s[4];
+ s[0] = (char)((data >> 24) & 0xff);
+ s[1] = (char)((data >> 16) & 0xff);
+ s[2] = (char)((data >> 8) & 0xff);
+ s[3] = (char)(data & 0xff);
+ std::string str(s, 4);
+
+ timespec t;
+ t.tv_sec = 0;
+ t.tv_nsec = 5e6;
+
+ nanosleep(&t, NULL);
+ d_usrp->_write_spi(0, d_spi_enable, d_spi_format, str);
+ nanosleep(&t, NULL);
+
+ //fprintf(stderr, "Wrote to WBXNG SPI address %d with data %8x\n", addr, data);
+ /* pulse latch */
+ //d_usrp->write_io(d_which, 1, LE_PIN);
+ //d_usrp->write_io(d_which, 0, LE_PIN);
+}
+
+bool
+adf4350::_set_freq(freq_t freq)
+{
+ /* Set the frequency by setting int, frac, mod, r, div */
+ if (freq > MAX_FREQ || freq < MIN_FREQ) return false;
+ /* Ramp up the RF divider until the VCO is within range. */
+ d_regs->d_divider_select = 0;
+ while (freq < MIN_VCO_FREQ){
+ freq <<= 1; //double the freq
+ d_regs->d_divider_select++; //double the divider
+ }
+ /* Ramp up the R divider until the N divider is at least the minimum. */
+ //d_regs->d_10_bit_r_counter = INPUT_REF_FREQ*MIN_INT_DIV/freq;
+ d_regs->d_10_bit_r_counter = 2;
+ uint64_t n_mod;
+ do{
+ d_regs->d_10_bit_r_counter++;
+ n_mod = freq;
+ n_mod *= d_regs->d_10_bit_r_counter;
+ n_mod *= d_regs->d_mod;
+ n_mod /= INPUT_REF_FREQ;
+ /* calculate int and frac */
+ d_regs->d_int = n_mod/d_regs->d_mod;
+ d_regs->d_frac = (n_mod - (freq_t)d_regs->d_int*d_regs->d_mod) & uint16_t(0xfff);
+ /*
+ fprintf(stderr,
+ "VCO %lu KHz, Int %u, Frac %u, Mod %u, R %u, Div %u\n",
+ freq, d_regs->d_int, d_regs->d_frac,
+ d_regs->d_mod, d_regs->d_10_bit_r_counter, (1 << d_regs->d_divider_select)
+ );
+ */
+ }while(d_regs->d_int < MIN_INT_DIV);
+ /* calculate the band select so PFD is under 125 KHz */
+ d_regs->d_8_bit_band_select_clock_divider_value = \
+ INPUT_REF_FREQ/(FREQ_C(30e3)*d_regs->d_10_bit_r_counter) + 1;
+ /*
+ fprintf(stderr, "Band Selection: Div %u, Freq %lu\n",
+ d_regs->d_8_bit_band_select_clock_divider_value,
+ INPUT_REF_FREQ/(d_regs->d_8_bit_band_select_clock_divider_value * d_regs->d_10_bit_r_counter) + 1
+ );
+ */
+ d_regs->_load_register(5);
+ d_regs->_load_register(3);
+ d_regs->_load_register(1);
+ /* load involved registers */
+ d_regs->_load_register(2);
+ d_regs->_load_register(4);
+ d_regs->_load_register(0); /* register 0 must be last */
+ return true;
+}
+
+freq_t
+adf4350::_get_freq(void)
+{
+ /* Calculate the freq from int, frac, mod, ref, r, div:
+ * freq = (int + frac/mod) * (ref/r)
+ * Keep precision by doing multiplies first:
+ * freq = (((((((int)*mod) + frac)*ref)/mod)/r)/div)
+ */
+ uint64_t temp;
+ temp = d_regs->d_int;
+ temp *= d_regs->d_mod;
+ temp += d_regs->d_frac;
+ temp *= INPUT_REF_FREQ;
+ temp /= d_regs->d_mod;
+ temp /= d_regs->d_10_bit_r_counter;
+ temp /= (1 << d_regs->d_divider_select);
+ return temp;
+}
--- /dev/null
+//
+// Copyright 2009 Free Software Foundation, Inc.
+//
+// This file is part of GNU Radio
+//
+// GNU Radio is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either asversion 3, or (at your option)
+// any later version.
+//
+// GNU Radio is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with GNU Radio; see the file COPYING. If not, write to
+// the Free Software Foundation, Inc., 51 Franklin Street,
+// Boston, MA 02110-1301, USA.
+
+#ifndef INCLUDED_ADF4350_H
+#define INCLUDED_ADF4350_H
+
+#include "db_wbxng_adf4350_regs.h"
+#include <usrp/db_base.h>
+#include <stdint.h>
+
+typedef uint64_t freq_t;
+class adf4350_regs;
+
+class adf4350
+{
+public:
+ adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable);
+ ~adf4350();
+ void _update();
+ bool _get_locked();
+ void _enable(bool enable);
+ void _write(uint8_t addr, uint32_t data);
+ bool _set_freq(freq_t freq);
+ freq_t _get_freq();
+ freq_t _get_max_freq();
+ freq_t _get_min_freq();
+
+protected:
+ usrp_basic_sptr d_usrp;
+ int d_which;
+ int d_spi_enable;
+ int d_spi_format;
+ adf4350_regs *d_regs;
+};
+
+#endif /* INCLUDED_ADF4350_H */
--- /dev/null
+/*
+ * Copyright 2009 Ettus Research LLC
+ */
+
+#include "db_wbxng_adf4350_regs.h"
+#include "db_wbxng_adf4350.h"
+
+//#include "cal_div.h"
+
+/* reg 0 */
+/* reg 1 */
+const uint8_t adf4350_regs::s_prescaler = 0;
+const uint16_t adf4350_regs::s_phase = 0;
+/* reg 2 */
+const uint8_t adf4350_regs::s_low_noise_and_low_spur_modes = 0;
+const uint8_t adf4350_regs::s_muxout = 6;
+const uint8_t adf4350_regs::s_reference_doubler = 0;
+const uint8_t adf4350_regs::s_rdiv2 = 0;
+const uint8_t adf4350_regs::s_double_buff = 0;
+const uint8_t adf4350_regs::s_charge_pump_setting = 5;
+const uint8_t adf4350_regs::s_ldf = 0;
+const uint8_t adf4350_regs::s_ldp = 0;
+const uint8_t adf4350_regs::s_pd_polarity = 1;
+const uint8_t adf4350_regs::s_power_down = 0;
+const uint8_t adf4350_regs::s_cp_three_state = 0;
+const uint8_t adf4350_regs::s_counter_reset = 0;
+/* reg 3 */
+const uint8_t adf4350_regs::s_csr = 0;
+const uint8_t adf4350_regs::s_clk_div_mode = 0;
+const uint16_t adf4350_regs::s_12_bit_clock_divider_value = 0;
+/* reg 4 */
+const uint8_t adf4350_regs::s_feedback_select = 1;
+const uint8_t adf4350_regs::s_vco_power_down = 0;
+const uint8_t adf4350_regs::s_mtld = 0;
+const uint8_t adf4350_regs::s_aux_output_select = 0;
+const uint8_t adf4350_regs::s_aux_output_enable = 1;
+const uint8_t adf4350_regs::s_aux_output_power = 3;
+const uint8_t adf4350_regs::s_rf_output_enable = 1;
+const uint8_t adf4350_regs::s_output_power = 3;
+/* reg 5 */
+const uint8_t adf4350_regs::s_ld_pin_mode = 1;
+
+adf4350_regs::adf4350_regs(adf4350* _adf4350){
+ d_adf4350 = _adf4350;
+
+ /* reg 0 */
+ d_int = uint16_t(100);
+ d_frac = 0;
+ /* reg 1 */
+ d_mod = uint16_t(0xfff); /* max fractional accuracy */
+ /* reg 2 */
+ d_10_bit_r_counter = uint16_t(2);
+ /* reg 3 */
+ /* reg 4 */
+ d_divider_select = 0;
+ d_8_bit_band_select_clock_divider_value = 0;
+ /* reg 5 */
+}
+
+adf4350_regs::~adf4350_regs(void){
+}
+
+uint32_t
+adf4350_regs::_reg_shift(uint32_t data, uint32_t shift){
+ return data << shift;
+ }
+
+void
+adf4350_regs::_load_register(uint8_t addr){
+ uint32_t data;
+ switch (addr){
+ case 0: data = (
+ _reg_shift(d_int, 15) |
+ _reg_shift(d_frac, 3)); break;
+ case 1: data = (
+ _reg_shift(s_prescaler, 27) |
+ _reg_shift(s_phase, 15) |
+ _reg_shift(d_mod, 3)); break;
+ case 2: data = (
+ _reg_shift(s_low_noise_and_low_spur_modes, 29) |
+ _reg_shift(s_muxout, 26) |
+ _reg_shift(s_reference_doubler, 25) |
+ _reg_shift(s_rdiv2, 24) |
+ _reg_shift(d_10_bit_r_counter, 14) |
+ _reg_shift(s_double_buff, 13) |
+ _reg_shift(s_charge_pump_setting, 9) |
+ _reg_shift(s_ldf, 8) |
+ _reg_shift(s_ldp, 7) |
+ _reg_shift(s_pd_polarity, 6) |
+ _reg_shift(s_power_down, 5) |
+ _reg_shift(s_cp_three_state, 4) |
+ _reg_shift(s_counter_reset, 3)); break;
+ case 3: data = (
+ _reg_shift(s_csr, 18) |
+ _reg_shift(s_clk_div_mode, 15) |
+ _reg_shift(s_12_bit_clock_divider_value, 3)); break;
+ case 4: data = (
+ _reg_shift(s_feedback_select, 23) |
+ _reg_shift(d_divider_select, 20) |
+ _reg_shift(d_8_bit_band_select_clock_divider_value, 12) |
+ _reg_shift(s_vco_power_down, 11) |
+ _reg_shift(s_mtld, 10) |
+ _reg_shift(s_aux_output_select, 9) |
+ _reg_shift(s_aux_output_enable, 8) |
+ _reg_shift(s_aux_output_power, 6) |
+ _reg_shift(s_rf_output_enable, 5) |
+ _reg_shift(s_output_power, 3)); break;
+ case 5: data = (
+ _reg_shift(s_ld_pin_mode, 22)); break;
+ default: return;
+ }
+ /* write the data out to spi */
+ d_adf4350->_write(addr, data);
+}
--- /dev/null
+/*
+ * Copyright 2009 Ettus Research LLC
+ */
+
+#ifndef ADF4350_REGS_H
+#define ADF4350_REGS_H
+
+#include <usrp/db_base.h>
+#include <stdint.h>
+
+class adf4350;
+
+class adf4350_regs
+{
+public:
+ adf4350_regs(adf4350* _adf4350);
+ ~adf4350_regs();
+
+ adf4350* d_adf4350;
+
+ uint32_t _reg_shift(uint32_t data, uint32_t shift);
+ void _load_register(uint8_t addr);
+
+ /* reg 0 */
+ uint16_t d_int;
+ uint16_t d_frac;
+ /* reg 1 */
+ static const uint8_t s_prescaler;
+ static const uint16_t s_phase;
+ uint16_t d_mod;
+ /* reg 2 */
+ static const uint8_t s_low_noise_and_low_spur_modes;
+ static const uint8_t s_muxout;
+ static const uint8_t s_reference_doubler;
+ static const uint8_t s_rdiv2;
+ uint16_t d_10_bit_r_counter;
+ static const uint8_t s_double_buff;
+ static const uint8_t s_charge_pump_setting;
+ static const uint8_t s_ldf;
+ static const uint8_t s_ldp;
+ static const uint8_t s_pd_polarity;
+ static const uint8_t s_power_down;
+ static const uint8_t s_cp_three_state;
+ static const uint8_t s_counter_reset;
+ /* reg 3 */
+ static const uint8_t s_csr;
+ static const uint8_t s_clk_div_mode;
+ static const uint16_t s_12_bit_clock_divider_value;
+ /* reg 4 */
+ static const uint8_t s_feedback_select;
+ uint8_t d_divider_select;
+ uint8_t d_8_bit_band_select_clock_divider_value;
+ static const uint8_t s_vco_power_down;
+ static const uint8_t s_mtld;
+ static const uint8_t s_aux_output_select;
+ static const uint8_t s_aux_output_enable;
+ static const uint8_t s_aux_output_power;
+ static const uint8_t s_rf_output_enable;
+ static const uint8_t s_output_power;
+ /* reg 5 */
+ static const uint8_t s_ld_pin_mode;
+};
+
+#endif /* ADF4350_REGS_H */
+++ /dev/null
-class fusb_devhandle;
-class fusb_ephandle;
-
-enum txrx_t {
- C_RX = 0,
- C_TX = 1
-};
-
-/*
- * ----------------------------------------------------------------------
- * Mid level interface to the Universal Software Radio Peripheral (Rev 1)
- *
- * These classes implement the basic functionality for talking to the
- * USRP. They try to be as independent of the signal processing code
- * in FPGA as possible. They implement access to the low level
- * peripherals on the board, provide a common way for reading and
- * writing registers in the FPGA, and provide the high speed interface
- * to streaming data across the USB.
- *
- * It is expected that subclasses will be derived that provide
- * access to the functionality to a particular FPGA configuration.
- * ----------------------------------------------------------------------
- */
-
-
-/*!
- * \brief abstract base class for usrp operations
- * \ingroup usrp
- */
-class usrp_basic : boost::noncopyable
-{
-protected:
- void shutdown_daughterboards();
-
-protected:
- libusb_device_handle *d_udh;
- struct libusb_context *d_ctx;
- int d_usb_data_rate; // bytes/sec
- int d_bytes_per_poll; // how often to poll for overruns
- bool d_verbose;
- long d_fpga_master_clock_freq;
-
- static const int MAX_REGS = 128;
- unsigned int d_fpga_shadows[MAX_REGS];
-
- int d_dbid[2]; // daughterboard ID's (side A, side B)
-
- /*!
- * Shared pointers to subclasses of db_base.
- *
- * The outer vector is of length 2 (0 = side A, 1 = side B). The
- * inner vectors are of length 1, 2 or 3 depending on the number of
- * subdevices implemented by the daugherboard. At this time, only
- * the Basic Rx and LF Rx implement more than 1 subdevice.
- */
- std::vector< std::vector<db_base_sptr> > d_db;
-
- //! One time call, made only only from usrp_standard_*::make after shared_ptr is created.
- void init_db(usrp_basic_sptr u);
-
-
- usrp_basic (int which_board,
- libusb_device_handle *open_interface (libusb_device *dev),
- const std::string fpga_filename = "",
- const std::string firmware_filename = "");
-
- /*!
- * \brief advise usrp_basic of usb data rate (bytes/sec)
- *
- * N.B., this doesn't tweak any hardware. Derived classes
- * should call this to inform us of the data rate whenever it's
- * first set or if it changes.
- *
- * \param usb_data_rate bytes/sec
- */
- void set_usb_data_rate (int usb_data_rate);
-
- /*!
- * \brief Write auxiliary digital to analog converter.
- *
- * \param slot Which Tx or Rx slot to write.
- * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
- * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
- * \param which_dac [0,3] RX slots must use only 0 and 1. TX slots must use only 2 and 3.
- * \param value [0,4095]
- * \returns true iff successful
- */
- bool _write_aux_dac (int slot, int which_dac, int value);
-
- /*!
- * \brief Read auxiliary analog to digital converter.
- *
- * \param slot 2-bit slot number. E.g., SLOT_TX_A
- * \param which_adc [0,1]
- * \param value return 12-bit value [0,4095]
- * \returns true iff successful
- */
- bool _read_aux_adc (int slot, int which_adc, int *value);
-
- /*!
- * \brief Read auxiliary analog to digital converter.
- *
- * \param slot 2-bit slot number. E.g., SLOT_TX_A
- * \param which_adc [0,1]
- * \returns value in the range [0,4095] if successful, else READ_FAILED.
- */
- int _read_aux_adc (int slot, int which_adc);
-
-
-public:
- virtual ~usrp_basic ();
-
-
- /*!
- * Return a vector of vectors that contain shared pointers
- * to the daughterboard instance(s) associated with the specified side.
- *
- * It is an error to use the returned objects after the usrp_basic
- * object has been destroyed.
- */
- std::vector<std::vector<db_base_sptr> > db() const { return d_db; }
-
- /*!
- * Return a vector of size >= 1 that contains shared pointers
- * to the daughterboard instance(s) associated with the specified side.
- *
- * \param which_side [0,1] which daughterboard
- *
- * It is an error to use the returned objects after the usrp_basic
- * object has been destroyed.
- */
- std::vector<db_base_sptr> db(int which_side);
-
- /*!
- * \brief is the subdev_spec valid?
- */
- bool is_valid(const usrp_subdev_spec &ss);
-
- /*!
- * \brief given a subdev_spec, return the corresponding daughterboard object.
- * \throws std::invalid_ argument if ss is invalid.
- *
- * \param ss specifies the side and subdevice
- */
- db_base_sptr selected_subdev(const usrp_subdev_spec &ss);
-
- /*!
- * \brief return frequency of master oscillator on USRP
- */
- long fpga_master_clock_freq () const { return d_fpga_master_clock_freq; }
-
- /*!
- * Tell API that the master oscillator on the USRP is operating at a non-standard
- * fixed frequency. This is only needed for custom USRP hardware modified to
- * operate at a different frequency from the default factory configuration. This
- * function must be called prior to any other API function.
- * \param master_clock USRP2 FPGA master clock frequency in Hz (10..64 MHz)
- */
- void set_fpga_master_clock_freq (long master_clock) { d_fpga_master_clock_freq = master_clock; }
-
- /*!
- * \returns usb data rate in bytes/sec
- */
- int usb_data_rate () const { return d_usb_data_rate; }
-
- void set_verbose (bool on) { d_verbose = on; }
-
- //! magic value used on alternate register read interfaces
- static const int READ_FAILED = -99999;
-
- /*!
- * \brief Write EEPROM on motherboard or any daughterboard.
- * \param i2c_addr I2C bus address of EEPROM
- * \param eeprom_offset byte offset in EEPROM to begin writing
- * \param buf the data to write
- * \returns true iff sucessful
- */
- bool write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf);
-
- /*!
- * \brief Read EEPROM on motherboard or any daughterboard.
- * \param i2c_addr I2C bus address of EEPROM
- * \param eeprom_offset byte offset in EEPROM to begin reading
- * \param len number of bytes to read
- * \returns the data read if successful, else a zero length string.
- */
- std::string read_eeprom (int i2c_addr, int eeprom_offset, int len);
-
- /*!
- * \brief Write to I2C peripheral
- * \param i2c_addr I2C bus address (7-bits)
- * \param buf the data to write
- * \returns true iff successful
- * Writes are limited to a maximum of of 64 bytes.
- */
- bool write_i2c (int i2c_addr, const std::string buf);
-
- /*!
- * \brief Read from I2C peripheral
- * \param i2c_addr I2C bus address (7-bits)
- * \param len number of bytes to read
- * \returns the data read if successful, else a zero length string.
- * Reads are limited to a maximum of 64 bytes.
- */
- std::string read_i2c (int i2c_addr, int len);
-
- /*!
- * \brief Set ADC offset correction
- * \param which_adc which ADC[0,3]: 0 = RX_A I, 1 = RX_A Q...
- * \param offset 16-bit value to subtract from raw ADC input.
- */
- bool set_adc_offset (int which_adc, int offset);
-
- /*!
- * \brief Set DAC offset correction
- * \param which_dac which DAC[0,3]: 0 = TX_A I, 1 = TX_A Q...
- * \param offset 10-bit offset value (ambiguous format: See AD9862 datasheet).
- * \param offset_pin 1-bit value. If 0 offset applied to -ve differential pin;
- * If 1 offset applied to +ve differential pin.
- */
- bool set_dac_offset (int which_dac, int offset, int offset_pin);
-
- /*!
- * \brief Control ADC input buffer
- * \param which_adc which ADC[0,3]
- * \param bypass if non-zero, bypass input buffer and connect input
- * directly to switched cap SHA input of RxPGA.
- */
- bool set_adc_buffer_bypass (int which_adc, bool bypass);
-
- /*!
- * \brief Enable/disable automatic DC offset removal control loop in FPGA
- *
- * \param bits which control loops to enable
- * \param mask which \p bits to pay attention to
- *
- * If the corresponding bit is set, enable the automatic DC
- * offset correction control loop.
- *
- * <pre>
- * The 4 low bits are significant:
- *
- * ADC0 = (1 << 0)
- * ADC1 = (1 << 1)
- * ADC2 = (1 << 2)
- * ADC3 = (1 << 3)
- * </pre>
- *
- * By default the control loop is enabled on all ADC's.
- */
- bool set_dc_offset_cl_enable(int bits, int mask);
-
- /*!
- * \brief return the usrp's serial number.
- *
- * \returns non-zero length string iff successful.
- */
- std::string serial_number();
-
- /*!
- * \brief Return daughterboard ID for given side [0,1].
- *
- * \param which_side [0,1] which daughterboard
- *
- * \return daughterboard id >= 0 if successful
- * \return -1 if no daugherboard
- * \return -2 if invalid EEPROM on daughterboard
- */
- virtual int daughterboard_id (int which_side) const = 0;
-
- /*!
- * \brief Clock ticks to delay rising of T/R signal
- * \sa write_atr_mask, write_atr_txval, write_atr_rxval
- */
- bool write_atr_tx_delay(int value);
-
- /*!
- * \brief Clock ticks to delay falling edge of T/R signal
- * \sa write_atr_mask, write_atr_txval, write_atr_rxval
- */
- bool write_atr_rx_delay(int value);
-
-
-\f // ================================================================
- // Routines to access and control daughterboard specific i/o
- //
- // Those with a common_ prefix access either the Tx or Rx side depending
- // on the txrx parameter. Those without the common_ prefix are virtual
- // and are overriden in usrp_basic_rx and usrp_basic_tx to access the
- // the Rx or Tx sides automatically. We provide the common_ versions
- // for those daughterboards such as the WBX and XCVR2450 that share
- // h/w resources (such as the LO) between the Tx and Rx sides.
-
- // ----------------------------------------------------------------
- // BEGIN common_ daughterboard control functions
-
- /*!
- * \brief Set Programmable Gain Amplifier(PGA)
- *
- * \param txrx Tx or Rx?
- * \param which_amp which amp [0,3]
- * \param gain_in_db gain value(linear in dB)
- *
- * gain is rounded to closest setting supported by hardware.
- *
- * \returns true iff sucessful.
- *
- * \sa pga_min(), pga_max(), pga_db_per_step()
- */
- bool common_set_pga(txrx_t txrx, int which_amp, double gain_in_db);
-
- /*!
- * \brief Return programmable gain amplifier gain setting in dB.
- *
- * \param txrx Tx or Rx?
- * \param which_amp which amp [0,3]
- */
- double common_pga(txrx_t txrx, int which_amp) const;
-
- /*!
- * \brief Return minimum legal PGA gain in dB.
- * \param txrx Tx or Rx?
- */
- double common_pga_min(txrx_t txrx) const;
-
- /*!
- * \brief Return maximum legal PGA gain in dB.
- * \param txrx Tx or Rx?
- */
- double common_pga_max(txrx_t txrx) const;
-
- /*!
- * \brief Return hardware step size of PGA(linear in dB).
- * \param txrx Tx or Rx?
- */
- double common_pga_db_per_step(txrx_t txrx) const;
-
- /*!
- * \brief Write direction register(output enables) for pins that go to daughterboard.
- *
- * \param txrx Tx or Rx?
- * \param which_side [0,1] which size
- * \param value value to write into register
- * \param mask which bits of value to write into reg
- *
- * Each d'board has 16-bits of general purpose i/o.
- * Setting the bit makes it an output from the FPGA to the d'board.
- *
- * This register is initialized based on a value stored in the
- * d'board EEPROM. In general, you shouldn't be using this routine
- * without a very good reason. Using this method incorrectly will
- * kill your USRP motherboard and/or daughterboard.
- */
- bool _common_write_oe(txrx_t txrx, int which_side, int value, int mask);
-
- /*!
- * \brief Write daughterboard i/o pin value
- *
- * \param txrx Tx or Rx?
- * \param which_side [0,1] which d'board
- * \param value value to write into register
- * \param mask which bits of value to write into reg
- */
- bool common_write_io(txrx_t txrx, int which_side, int value, int mask);
-
- /*!
- * \brief Read daughterboard i/o pin value
- *
- * \param txrx Tx or Rx?
- * \param which_side [0,1] which d'board
- * \param value output
- */
- bool common_read_io(txrx_t txrx, int which_side, int *value);
-
- /*!
- * \brief Read daughterboard i/o pin value
- *
- * \param txrx Tx or Rx?
- * \param which_side [0,1] which d'board
- * \returns register value if successful, else READ_FAILED
- */
- int common_read_io(txrx_t txrx, int which_side);
-
- /*!
- * \brief Write daughterboard refclk config register
- *
- * \param txrx Tx or Rx?
- * \param which_side [0,1] which d'board
- * \param value value to write into register, see below
- *
- * <pre>
- * Control whether a reference clock is sent to the daughterboards,
- * and what frequency. The refclk is sent on d'board i/o pin 0.
- *
- * 3 2 1
- * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-----------------------------------------------+-+------------+
- * | Reserved (Must be zero) |E| DIVISOR |
- * +-----------------------------------------------+-+------------+
- *
- * Bit 7 -- 1 turns on refclk, 0 allows IO use
- * Bits 6:0 Divider value
- * </pre>
- */
- bool common_write_refclk(txrx_t txrx, int which_side, int value);
-
- /*!
- * \brief Automatic Transmit/Receive switching
- * <pre>
- *
- * If automatic transmit/receive (ATR) switching is enabled in the
- * FR_ATR_CTL register, the presence or absence of data in the FPGA
- * transmit fifo selects between two sets of values for each of the 4
- * banks of daughterboard i/o pins.
- *
- * Each daughterboard slot has 3 16-bit registers associated with it:
- * FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
- *
- * FR_ATR_MASK_{0,1,2,3}:
- *
- * These registers determine which of the daugherboard i/o pins are
- * affected by ATR switching. If a bit in the mask is set, the
- * corresponding i/o bit is controlled by ATR, else it's output
- * value comes from the normal i/o pin output register:
- * FR_IO_{0,1,2,3}.
- *
- * FR_ATR_TXVAL_{0,1,2,3}:
- * FR_ATR_RXVAL_{0,1,2,3}:
- *
- * If the Tx fifo contains data, then the bits from TXVAL that are
- * selected by MASK are output. Otherwise, the bits from RXVAL that
- * are selected by MASK are output.
- * </pre>
- */
- bool common_write_atr_mask(txrx_t txrx, int which_side, int value);
- bool common_write_atr_txval(txrx_t txrx, int which_side, int value);
- bool common_write_atr_rxval(txrx_t txrx, int which_side, int value);
-
- /*!
- * \brief Write auxiliary digital to analog converter.
- *
- * \param txrx Tx or Rx?
- * \param which_side [0,1] which d'board
- * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
- * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
- * \param which_dac [2,3] TX slots must use only 2 and 3.
- * \param value [0,4095]
- * \returns true iff successful
- */
- bool common_write_aux_dac(txrx_t txrx, int which_side, int which_dac, int value);
-
- /*!
- * \brief Read auxiliary analog to digital converter.
- *
- * \param txrx Tx or Rx?
- * \param which_side [0,1] which d'board
- * \param which_adc [0,1]
- * \param value return 12-bit value [0,4095]
- * \returns true iff successful
- */
- bool common_read_aux_adc(txrx_t txrx, int which_side, int which_adc, int *value);
-
- /*!
- * \brief Read auxiliary analog to digital converter.
- *
- * \param txrx Tx or Rx?
- * \param which_side [0,1] which d'board
- * \param which_adc [0,1]
- * \returns value in the range [0,4095] if successful, else READ_FAILED.
- */
- int common_read_aux_adc(txrx_t txrx, int which_side, int which_adc);
-
- // END common_ daughterboard control functions\f
- // ----------------------------------------------------------------
- // BEGIN virtual daughterboard control functions
-
- /*!
- * \brief Set Programmable Gain Amplifier (PGA)
- *
- * \param which_amp which amp [0,3]
- * \param gain_in_db gain value (linear in dB)
- *
- * gain is rounded to closest setting supported by hardware.
- *
- * \returns true iff sucessful.
- *
- * \sa pga_min(), pga_max(), pga_db_per_step()
- */
- virtual bool set_pga (int which_amp, double gain_in_db) = 0;
-
- /*!
- * \brief Return programmable gain amplifier gain setting in dB.
- *
- * \param which_amp which amp [0,3]
- */
- virtual double pga (int which_amp) const = 0;
-
- /*!
- * \brief Return minimum legal PGA gain in dB.
- */
- virtual double pga_min () const = 0;
-
- /*!
- * \brief Return maximum legal PGA gain in dB.
- */
- virtual double pga_max () const = 0;
-
- /*!
- * \brief Return hardware step size of PGA (linear in dB).
- */
- virtual double pga_db_per_step () const = 0;
-
- /*!
- * \brief Write direction register (output enables) for pins that go to daughterboard.
- *
- * \param which_side [0,1] which size
- * \param value value to write into register
- * \param mask which bits of value to write into reg
- *
- * Each d'board has 16-bits of general purpose i/o.
- * Setting the bit makes it an output from the FPGA to the d'board.
- *
- * This register is initialized based on a value stored in the
- * d'board EEPROM. In general, you shouldn't be using this routine
- * without a very good reason. Using this method incorrectly will
- * kill your USRP motherboard and/or daughterboard.
- */
- virtual bool _write_oe (int which_side, int value, int mask) = 0;
-
- /*!
- * \brief Write daughterboard i/o pin value
- *
- * \param which_side [0,1] which d'board
- * \param value value to write into register
- * \param mask which bits of value to write into reg
- */
- virtual bool write_io (int which_side, int value, int mask) = 0;
-
- /*!
- * \brief Read daughterboard i/o pin value
- *
- * \param which_side [0,1] which d'board
- * \param value output
- */
- virtual bool read_io (int which_side, int *value) = 0;
-
- /*!
- * \brief Read daughterboard i/o pin value
- *
- * \param which_side [0,1] which d'board
- * \returns register value if successful, else READ_FAILED
- */
- virtual int read_io (int which_side) = 0;
-
- /*!
- * \brief Write daughterboard refclk config register
- *
- * \param which_side [0,1] which d'board
- * \param value value to write into register, see below
- *
- * <pre>
- * Control whether a reference clock is sent to the daughterboards,
- * and what frequency. The refclk is sent on d'board i/o pin 0.
- *
- * 3 2 1
- * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-----------------------------------------------+-+------------+
- * | Reserved (Must be zero) |E| DIVISOR |
- * +-----------------------------------------------+-+------------+
- *
- * Bit 7 -- 1 turns on refclk, 0 allows IO use
- * Bits 6:0 Divider value
- * </pre>
- */
- virtual bool write_refclk(int which_side, int value) = 0;
-
- virtual bool write_atr_mask(int which_side, int value) = 0;
- virtual bool write_atr_txval(int which_side, int value) = 0;
- virtual bool write_atr_rxval(int which_side, int value) = 0;
-
- /*!
- * \brief Write auxiliary digital to analog converter.
- *
- * \param which_side [0,1] which d'board
- * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
- * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
- * \param which_dac [2,3] TX slots must use only 2 and 3.
- * \param value [0,4095]
- * \returns true iff successful
- */
- virtual bool write_aux_dac (int which_side, int which_dac, int value) = 0;
-
- /*!
- * \brief Read auxiliary analog to digital converter.
- *
- * \param which_side [0,1] which d'board
- * \param which_adc [0,1]
- * \param value return 12-bit value [0,4095]
- * \returns true iff successful
- */
- virtual bool read_aux_adc (int which_side, int which_adc, int *value) = 0;
-
- /*!
- * \brief Read auxiliary analog to digital converter.
- *
- * \param which_side [0,1] which d'board
- * \param which_adc [0,1]
- * \returns value in the range [0,4095] if successful, else READ_FAILED.
- */
- virtual int read_aux_adc (int which_side, int which_adc) = 0;
-
- /*!
- * \brief returns current fusb block size
- */
- virtual int block_size() const = 0;
-
- /*!
- * \brief returns A/D or D/A converter rate in Hz
- */
- virtual long converter_rate() const = 0;
-
- // END virtual daughterboard control functions\f
-
- // ----------------------------------------------------------------
- // Low level implementation routines.
- // You probably shouldn't be using these...
- //
-
- bool _set_led (int which_led, bool on);
-
- /*!
- * \brief Write FPGA register.
- * \param regno 7-bit register number
- * \param value 32-bit value
- * \returns true iff successful
- */
- bool _write_fpga_reg (int regno, int value); //< 7-bit regno, 32-bit value
-
- /*!
- * \brief Read FPGA register.
- * \param regno 7-bit register number
- * \param value 32-bit value
- * \returns true iff successful
- */
- bool _read_fpga_reg (int regno, int *value); //< 7-bit regno, 32-bit value
-
- /*!
- * \brief Read FPGA register.
- * \param regno 7-bit register number
- * \returns register value if successful, else READ_FAILED
- */
- int _read_fpga_reg (int regno);
-
- /*!
- * \brief Write FPGA register with mask.
- * \param regno 7-bit register number
- * \param value 16-bit value
- * \param mask 16-bit value
- * \returns true if successful
- * Only use this for registers who actually implement a mask in the verilog firmware, like FR_RX_MASTER_SLAVE
- */
- bool _write_fpga_reg_masked (int regno, int value, int mask);
-
- /*!
- * \brief Write AD9862 register.
- * \param which_codec 0 or 1
- * \param regno 6-bit register number
- * \param value 8-bit value
- * \returns true iff successful
- */
- bool _write_9862 (int which_codec, int regno, unsigned char value);
-
- /*!
- * \brief Read AD9862 register.
- * \param which_codec 0 or 1
- * \param regno 6-bit register number
- * \param value 8-bit value
- * \returns true iff successful
- */
- bool _read_9862 (int which_codec, int regno, unsigned char *value) const;
-
- /*!
- * \brief Read AD9862 register.
- * \param which_codec 0 or 1
- * \param regno 6-bit register number
- * \returns register value if successful, else READ_FAILED
- */
- int _read_9862 (int which_codec, int regno) const;
-
- /*!
- * \brief Write data to SPI bus peripheral.
- *
- * \param optional_header 0,1 or 2 bytes to write before buf.
- * \param enables bitmask of peripherals to write. See usrp_spi_defs.h
- * \param format transaction format. See usrp_spi_defs.h SPI_FMT_*
- * \param buf the data to write
- * \returns true iff successful
- * Writes are limited to a maximum of 64 bytes.
- *
- * If \p format specifies that optional_header bytes are present, they are
- * written to the peripheral immediately prior to writing \p buf.
- */
- bool _write_spi (int optional_header, int enables, int format, std::string buf);
-
- /*
- * \brief Read data from SPI bus peripheral.
- *
- * \param optional_header 0,1 or 2 bytes to write before buf.
- * \param enables bitmask of peripheral to read. See usrp_spi_defs.h
- * \param format transaction format. See usrp_spi_defs.h SPI_FMT_*
- * \param len number of bytes to read. Must be in [0,64].
- * \returns the data read if sucessful, else a zero length string.
- *
- * Reads are limited to a maximum of 64 bytes.
- *
- * If \p format specifies that optional_header bytes are present, they
- * are written to the peripheral first. Then \p len bytes are read from
- * the peripheral and returned.
- */
- std::string _read_spi (int optional_header, int enables, int format, int len);
-
- /*!
- * \brief Start data transfers.
- * Called in base class to derived class order.
- */
- bool start ();
-
- /*!
- * \brief Stop data transfers.
- * Called in base class to derived class order.
- */
- bool stop ();
-};
-
-\f/*!
- * \brief class for accessing the receive side of the USRP
- * \ingroup usrp
- */
-class usrp_basic_rx : public usrp_basic
-{
-private:
- fusb_devhandle *d_devhandle;
- fusb_ephandle *d_ephandle;
- int d_bytes_seen; // how many bytes we've seen
- bool d_first_read;
- bool d_rx_enable;
-
-protected:
- /*!
- * \param which_board Which USRP board on usb (not particularly useful; use 0)
- * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
- * Use zero for a reasonable default.
- * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
- * \param fpga_filename name of the rbf file to load
- * \param firmware_filename name of ihx file to load
- */
- usrp_basic_rx (int which_board,
- int fusb_block_size=0,
- int fusb_nblocks=0,
- const std::string fpga_filename = "",
- const std::string firmware_filename = ""
- ); // throws if trouble
-
- bool set_rx_enable (bool on);
- bool rx_enable () const { return d_rx_enable; }
-
- bool disable_rx (); // conditional disable, return prev state
- void restore_rx (bool on); // conditional set
-
- void probe_rx_slots (bool verbose);
-
-public:
- ~usrp_basic_rx ();
-
- /*!
- * \brief invokes constructor, returns instance or 0 if trouble
- *
- * \param which_board Which USRP board on usb (not particularly useful; use 0)
- * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
- * Use zero for a reasonable default.
- * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
- * \param fpga_filename name of file that contains image to load into FPGA
- * \param firmware_filename name of file that contains image to load into FX2
- */
- static usrp_basic_rx *make (int which_board,
- int fusb_block_size=0,
- int fusb_nblocks=0,
- const std::string fpga_filename = "",
- const std::string firmware_filename = ""
- );
-
- /*!
- * \brief tell the fpga the rate rx samples are coming from the A/D's
- *
- * div = fpga_master_clock_freq () / sample_rate
- *
- * sample_rate is determined by a myriad of registers
- * in the 9862. That's why you have to tell us, so
- * we can tell the fpga.
- */
- bool set_fpga_rx_sample_rate_divisor (unsigned int div);
-
- /*!
- * \brief read data from the D/A's via the FPGA.
- * \p len must be a multiple of 512 bytes.
- *
- * \returns the number of bytes read, or -1 on error.
- *
- * If overrun is non-NULL it will be set true iff an RX overrun is detected.
- */
- int read (void *buf, int len, bool *overrun);
-
-
- //! sampling rate of A/D converter
- virtual long converter_rate() const { return fpga_master_clock_freq(); } // 64M
- long adc_rate() const { return converter_rate(); }
- int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; }
-
- bool set_pga (int which_amp, double gain_in_db);
- double pga (int which_amp) const;
- double pga_min () const;
- double pga_max () const;
- double pga_db_per_step () const;
-
- bool _write_oe (int which_side, int value, int mask);
- bool write_io (int which_side, int value, int mask);
- bool read_io (int which_side, int *value);
- int read_io (int which_side);
- bool write_refclk(int which_side, int value);
- bool write_atr_mask(int which_side, int value);
- bool write_atr_txval(int which_side, int value);
- bool write_atr_rxval(int which_side, int value);
-
- bool write_aux_dac (int which_side, int which_dac, int value);
- bool read_aux_adc (int which_side, int which_adc, int *value);
- int read_aux_adc (int which_side, int which_adc);
-
- int block_size() const;
-
- // called in base class to derived class order
- bool start ();
- bool stop ();
-};
-
-\f/*!
- * \brief class for accessing the transmit side of the USRP
- * \ingroup usrp
- */
-class usrp_basic_tx : public usrp_basic
-{
-private:
- fusb_devhandle *d_devhandle;
- fusb_ephandle *d_ephandle;
- int d_bytes_seen; // how many bytes we've seen
- bool d_first_write;
- bool d_tx_enable;
-
- protected:
- /*!
- * \param which_board Which USRP board on usb (not particularly useful; use 0)
- * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
- * Use zero for a reasonable default.
- * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
- * \param fpga_filename name of file that contains image to load into FPGA
- * \param firmware_filename name of file that contains image to load into FX2
- */
- usrp_basic_tx (int which_board,
- int fusb_block_size=0,
- int fusb_nblocks=0,
- const std::string fpga_filename = "",
- const std::string firmware_filename = ""
- ); // throws if trouble
-
- bool set_tx_enable (bool on);
- bool tx_enable () const { return d_tx_enable; }
-
- bool disable_tx (); // conditional disable, return prev state
- void restore_tx (bool on); // conditional set
-
- void probe_tx_slots (bool verbose);
-
-public:
-
- ~usrp_basic_tx ();
-
- /*!
- * \brief invokes constructor, returns instance or 0 if trouble
- *
- * \param which_board Which USRP board on usb (not particularly useful; use 0)
- * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
- * Use zero for a reasonable default.
- * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
- * \param fpga_filename name of file that contains image to load into FPGA
- * \param firmware_filename name of file that contains image to load into FX2
- */
- static usrp_basic_tx *make (int which_board, int fusb_block_size=0, int fusb_nblocks=0,
- const std::string fpga_filename = "",
- const std::string firmware_filename = ""
- );
-
- /*!
- * \brief tell the fpga the rate tx samples are going to the D/A's
- *
- * div = fpga_master_clock_freq () * 2
- *
- * sample_rate is determined by a myriad of registers
- * in the 9862. That's why you have to tell us, so
- * we can tell the fpga.
- */
- bool set_fpga_tx_sample_rate_divisor (unsigned int div);
-
- /*!
- * \brief Write data to the A/D's via the FPGA.
- *
- * \p len must be a multiple of 512 bytes.
- * \returns number of bytes written or -1 on error.
- *
- * if \p underrun is non-NULL, it will be set to true iff
- * a transmit underrun condition is detected.
- */
- int write (const void *buf, int len, bool *underrun);
-
- /*
- * Block until all outstanding writes have completed.
- * This is typically used to assist with benchmarking
- */
- void wait_for_completion ();
-
- //! sampling rate of D/A converter
- virtual long converter_rate() const { return fpga_master_clock_freq () * 2; } // 128M
- long dac_rate() const { return converter_rate(); }
- int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; }
-
- bool set_pga (int which_amp, double gain_in_db);
- double pga (int which_amp) const;
- double pga_min () const;
- double pga_max () const;
- double pga_db_per_step () const;
-
- bool _write_oe (int which_side, int value, int mask);
- bool write_io (int which_side, int value, int mask);
- bool read_io (int which_side, int *value);
- int read_io (int which_side);
- bool write_refclk(int which_side, int value);
- bool write_atr_mask(int which_side, int value);
- bool write_atr_txval(int which_side, int value);
- bool write_atr_rxval(int which_side, int value);
-
- bool write_aux_dac (int which_side, int which_dac, int value);
- bool read_aux_adc (int which_side, int which_adc, int *value);
- int read_aux_adc (int which_side, int which_adc);
-
- int block_size() const;
-
- // called in base class to derived class order
- bool start ();
- bool stop ();
-};
-
-#endif
#
# Copyright 2005,2009 Free Software Foundation, Inc.
-#
+#
# This file is part of GNU Radio
-#
+#
# GNU Radio is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
-#
+#
# GNU Radio is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
"WBX LO TX" 0x0050
"WBX LO RX" 0x0051
+"WBX NG TX" 0x0052
+"WBX NG RX" 0x0053
+
"XCVR2450 Tx" 0x0060
"XCVR2450 Rx" 0x0061
projects / debian / gnuradio / commitdiff