cortex_m: add detection of Cortex M35P and M55

Change-Id: I52599b2b09c2dc50c95d64059213c832d380ea31
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5799
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 4b0ea50ccc9402257f84a096859cafd9472bfa42..e52332dd620dfdfcc32185dc561a4f96dd3805bf 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2176,11 +2176,15 @@ int cortex_m_examine(struct target *target)
                        case CORTEX_M23_PARTNO:
                                i = 23;
                                break;
-
                        case CORTEX_M33_PARTNO:
                                i = 33;
                                break;
-
+                       case CORTEX_M35P_PARTNO:
+                               i = 35;
+                               break;
+                       case CORTEX_M55_PARTNO:
+                               i = 55;
+                               break;
                        default:
                                armv7m->arm.is_armv8m = false;
                                break;
@@ -2213,7 +2217,7 @@ int cortex_m_examine(struct target *target)
                                LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
                                armv7m->fp_feature = FPv4_SP;
                        }
-               } else if (i == 7 || i == 33) {
+               } else if (i == 7 || i == 33 || i == 35 || i == 55) {
                        target_read_u32(target, MVFR0, &mvfr0);
                        target_read_u32(target, MVFR1, &mvfr1);
 

diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 354532823d2404a85d3e45682fc7cafc77a3e371..415a6c22f301d001403c92c0f765e04fb42783ac 100644 (file)
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -44,6 +44,8 @@
 
 #define CORTEX_M23_PARTNO      0xD200
 #define CORTEX_M33_PARTNO      0xD210
+#define CORTEX_M35P_PARTNO     0xD310
+#define CORTEX_M55_PARTNO      0xD220
 
 /* Debug Control Block */
 #define DCB_DHCSR      0xE000EDF0