target/cortex_a: fix memory leak of register cache

There is no method to free the register cache, allocated in
armv4_5, so we get a memory leak.
Issue identified by valgrind.

Implement the method arm_free_reg_cache() and call it in cortex_a
deinit and to exit for error during arm_dpm_setup().
Tested on dual cortex-A stm32mp15x.
This change is inspired from similar fix in commit b01b5fe13a67
("armv7m: Fix memory leak in register caching.").

The same allocation is also used by target types "arm7tdmi",
"arm9tdmi", "arm11" and "xscale" but they all lack the deinit
method and I do not have relevant HW to test the fix. For such
reasons they are not addressed in this patch.

Change-Id: I4da1e1f12e36ec245d1f3b11a4eafcbd9a1d2e25
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5693
Tested-by: jenkins

diff --git a/src/target/arm.h b/src/target/arm.h
index b39957495f6008130772a397b8762f4ad5531dc8..3450260f08c5243f8086716610caa2d7008cb991 100644 (file)
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -272,6 +272,8 @@ struct arm_reg {
 };
 
 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
+void arm_free_reg_cache(struct arm *arm);
+
 struct reg_cache *armv8_build_reg_cache(struct target *target);
 
 extern const struct command_registration arm_command_handlers[];

diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 495d63ec2829341fd44ed1955f30bf199b147e44..72215f90b86ad0810b3d868569ee2a924489b1c2 100644 (file)
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -1100,6 +1100,7 @@ int arm_dpm_setup(struct arm_dpm *dpm)
        dpm->dwp = calloc(dpm->nwp, sizeof(*dpm->dwp));
 
        if (!dpm->dbp || !dpm->dwp) {
+               arm_free_reg_cache(arm);
                free(dpm->dbp);
                free(dpm->dwp);
                return ERROR_FAIL;

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index b4581d5f1731b15acba2f7fc44e1634824a10921..58bc3390a923ec1c8f17ae6d71e6130fbfb58182 100644 (file)
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -769,6 +769,27 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
        return cache;
 }
 
+void arm_free_reg_cache(struct arm *arm)
+{
+       if (!arm || !arm->core_cache)
+               return;
+
+       struct reg_cache *cache = arm->core_cache;
+
+       for (unsigned int i = 0; i < cache->num_regs; i++) {
+               struct reg *reg = &cache->reg_list[i];
+
+               free(reg->feature);
+               free(reg->reg_data_type);
+       }
+
+       free(cache->reg_list[0].arch_info);
+       free(cache->reg_list);
+       free(cache);
+
+       arm->core_cache = NULL;
+}
+
 int arm_arch_state(struct target *target)
 {
        struct arm *arm = target_to_arm(target);

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index f71b1552418aad0b9d928b82d5fc7b896d9d2d3f..f562a76147d2f572ca7fd6926cf50be3590c6ee6 100644 (file)
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2959,6 +2959,7 @@ static void cortex_a_deinit_target(struct target *target)
        }
 
        free(cortex_a->brp_list);
+       arm_free_reg_cache(dpm->arm);
        free(dpm->dbp);
        free(dpm->dwp);
        free(target->private_config);