~usrp2_base();
std::string mac_addr() const;
+ %rename(_real_fpga_master_clock_freq) fpga_master_clock_freq;
+ bool fpga_master_clock_freq(long *freq);
};
// ----------------------------------------------------------------
%rename(_real_set_center_freq) set_center_freq;
bool set_center_freq(double frequency, usrp2::tune_result *r);
bool set_decim(int decimation_factor);
+ bool set_scale_iq(int scale_i, int scale_q);
+ int decim();
+ %rename(_real_adc_rate) adc_rate;
+ bool adc_rate(long *rate);
+ double gain_min();
+ double gain_max();
+ double gain_db_per_step();
+ double freq_min();
+ double freq_max();
+ %rename(_real_daughterboard_id) daughterboard_id;
+ bool daughterboard_id(int *dbid);
+ unsigned int overruns();
+ unsigned int missing();
};
// ----------------------------------------------------------------
%rename(_real_set_center_freq) set_center_freq;
bool set_center_freq(double frequency, usrp2::tune_result *r);
bool set_interp(int interp_factor);
+ bool set_scale_iq(int scale_i, int scale_q);
+ int interp();
+ %rename(_real_dac_rate) dac_rate;
+ bool dac_rate(long *rate);
+ double gain_min();
+ double gain_max();
+ double gain_db_per_step();
+ double freq_min();
+ double freq_max();
+ %rename(_real_daughterboard_id) daughterboard_id;
+ bool daughterboard_id(int *dbid);
};
// ----------------------------------------------------------------
// ----------------------------------------------------------------
+// some utility functions to allow Python to deal with pointers
+%{
+ long *make_long_ptr() { return (long *)malloc(sizeof(long)); }
+ long deref_long_ptr(long *l) { return *l; }
+ void free_long_ptr(long *l) { free(l); }
+ int *make_int_ptr() { return (int *)malloc(sizeof(int)); }
+ int deref_int_ptr(int *l) { return *l; }
+ void free_int_ptr(int *l) { free(l); }
+%}
+
+long *make_long_ptr();
+long deref_long_ptr(long *l);
+void free_long_ptr(long *l);
+int *make_int_ptr();
+int deref_int_ptr(int *l);
+void free_int_ptr(int *l);
+
// create a more pythonic interface
%pythoncode %{
else:
return None
+def __fpga_master_clock_freq(self):
+ f = make_long_ptr();
+ r = self._real_fpga_master_clock_freq(f)
+ if r:
+ result = deref_long_ptr(f)
+ else:
+ result = None
+ free_long_ptr(f)
+ return result
+
+def __adc_rate(self):
+ rate = make_long_ptr();
+ r = self._real_adc_rate(rate)
+ if r:
+ result = deref_long_ptr(rate)
+ else:
+ result = None
+ free_long_ptr(rate)
+ return result
+
+def __dac_rate(self):
+ rate = make_long_ptr();
+ r = self._real_dac_rate(rate)
+ if r:
+ result = deref_long_ptr(rate)
+ else:
+ result = None
+ free_long_ptr(rate)
+ return result
+
+def __gain_range(self):
+ return [self.gain_min(),
+ self.gain_max(),
+ self.gain_db_per_step()]
+
+# NOTE: USRP1 uses a length three tuple here (3rd value is 'freq step'),
+# but it's not really useful. We let an index error happen here
+# to identify code using it.
+def __freq_range(self):
+ return [self.freq_min(),
+ self.freq_max()]
+
+def __daughterboard_id(self):
+ dbid = make_int_ptr();
+ r = self._real_daughterboard_id(dbid)
+ if r:
+ result = deref_int_ptr(dbid)
+ else:
+ result = None
+ free_int_ptr(dbid)
+ return result
+
usrp2_source_32fc_sptr.set_center_freq = __set_center_freq
usrp2_source_16sc_sptr.set_center_freq = __set_center_freq
usrp2_sink_32fc_sptr.set_center_freq = __set_center_freq
usrp2_sink_16sc_sptr.set_center_freq = __set_center_freq
+
+usrp2_source_32fc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
+usrp2_source_16sc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
+usrp2_sink_32fc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
+usrp2_sink_16sc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
+
+usrp2_source_32fc_sptr.adc_rate = __adc_rate
+usrp2_source_16sc_sptr.adc_rate = __adc_rate
+usrp2_sink_32fc_sptr.dac_rate = __dac_rate
+usrp2_sink_16sc_sptr.dac_rate = __dac_rate
+
+usrp2_source_32fc_sptr.gain_range = __gain_range
+usrp2_source_16sc_sptr.gain_range = __gain_range
+usrp2_sink_32fc_sptr.gain_range = __gain_range
+usrp2_sink_16sc_sptr.gain_range = __gain_range
+
+usrp2_source_32fc_sptr.freq_range = __freq_range
+usrp2_source_16sc_sptr.freq_range = __freq_range
+usrp2_sink_32fc_sptr.freq_range = __freq_range
+usrp2_sink_16sc_sptr.freq_range = __freq_range
+
+usrp2_source_32fc_sptr.daughterboard_id = __daughterboard_id
+usrp2_source_16sc_sptr.daughterboard_id = __daughterboard_id
+usrp2_sink_32fc_sptr.daughterboard_id = __daughterboard_id
+usrp2_sink_16sc_sptr.daughterboard_id = __daughterboard_id
+
%}
return d_u2->mac_addr();
}
+bool
+usrp2_base::fpga_master_clock_freq(long *freq) const
+{
+ return d_u2->fpga_master_clock_freq(freq);
+}
+
bool
usrp2_base::start()
{
*/
std::string mac_addr() const;
+ /*!
+ * \brief Get USRP2 master clock rate
+ */
+ bool fpga_master_clock_freq(long *freq) const;
+
/*!
* \brief Called by scheduler when starting flowgraph
*/
{
return d_u2->set_tx_interp(interp_factor);
}
+
+bool
+usrp2_sink_base::set_scale_iq(int scale_i, int scale_q)
+{
+ return d_u2->set_tx_scale_iq(scale_i, scale_q);
+}
+
+int
+usrp2_sink_base::interp()
+{
+ return d_u2->tx_interp();
+}
+
+bool
+usrp2_sink_base::dac_rate(long *rate)
+{
+ return d_u2->dac_rate(rate);
+}
+
+double
+usrp2_sink_base::gain_min()
+{
+ return d_u2->tx_gain_min();
+}
+
+double
+usrp2_sink_base::gain_max()
+{
+ return d_u2->tx_gain_max();
+}
+
+double
+usrp2_sink_base::gain_db_per_step()
+{
+ return d_u2->tx_gain_db_per_step();
+}
+
+double
+usrp2_sink_base::freq_min()
+{
+ return d_u2->tx_freq_min();
+}
+
+double
+usrp2_sink_base::freq_max()
+{
+ return d_u2->tx_freq_max();
+}
+
+bool
+usrp2_sink_base::daughterboard_id(int *dbid)
+{
+ return d_u2->tx_daughterboard_id(dbid);
+}
* \brief Set transmit interpolation rate
*/
bool set_interp(int interp_factor);
+
+ /*!
+ * \brief Set transmit IQ scale factors
+ */
+ bool set_scale_iq(int scale_i, int scale_q);
+
+ /*!
+ * \brief Get transmit interpolation rate
+ */
+ int interp();
+
+ /*!
+ * \brief Get DAC sample rate in Hz
+ */
+ bool dac_rate(long *rate);
+
+ /*!
+ * \brief Returns minimum Tx gain
+ */
+ double gain_min();
+
+ /*!
+ * \brief Returns maximum Tx gain
+ */
+ double gain_max();
+
+ /*!
+ * \brief Returns Tx gain db_per_step
+ */
+ double gain_db_per_step();
+
+ /*!
+ * \brief Returns minimum Tx center frequency
+ */
+ double freq_min();
+
+ /*!
+ * \brief Returns maximum Tx center frequency
+ */
+ double freq_max();
+
+ /*!
+ * \brief Get Tx daughterboard ID
+ *
+ * \param[out] dbid returns the daughterboard id.
+ *
+ * daughterboard id >= 0 if successful, -1 if no daugherboard installed,
+ * -2 if invalid EEPROM on daughterboard.
+ */
+ bool daughterboard_id(int *dbid);
};
#endif /* INCLUDED_USRP2_SINK_BASE_H */
return d_u2->set_rx_decim(decimation_factor);
}
+bool
+usrp2_source_base::set_scale_iq(int scale_i, int scale_q)
+{
+ return d_u2->set_rx_scale_iq(scale_i, scale_q);
+}
+
+int
+usrp2_source_base::decim()
+{
+ return d_u2->rx_decim();
+}
+
+bool
+usrp2_source_base::adc_rate(long *rate)
+{
+ return d_u2->adc_rate(rate);
+}
+
+double
+usrp2_source_base::gain_min()
+{
+ return d_u2->rx_gain_min();
+}
+
+double
+usrp2_source_base::gain_max()
+{
+ return d_u2->rx_gain_max();
+}
+
+double
+usrp2_source_base::gain_db_per_step()
+{
+ return d_u2->rx_gain_db_per_step();
+}
+
+double
+usrp2_source_base::freq_min()
+{
+ return d_u2->rx_freq_min();
+}
+
+double
+usrp2_source_base::freq_max()
+{
+ return d_u2->rx_freq_max();
+}
+
+bool
+usrp2_source_base::daughterboard_id(int *dbid)
+{
+ return d_u2->rx_daughterboard_id(dbid);
+}
+
+unsigned int
+usrp2_source_base::overruns()
+{
+ return d_u2->rx_overruns();
+}
+
+unsigned int
+usrp2_source_base::missing()
+{
+ return d_u2->rx_missing();
+}
+
bool
usrp2_source_base::start()
{
*/
bool set_decim(int decimation_factor);
+ /*!
+ * \brief Set receive IQ scale factors
+ */
+ bool set_scale_iq(int scale_i, int scale_q);
+
+ /*!
+ * \brief Get receive decimation rate
+ */
+ int decim();
+
+ /*!
+ * \brief Get the ADC sample rate
+ */
+ bool adc_rate(long *rate);
+
+ /*!
+ * \brief Returns minimum Rx gain
+ */
+ double gain_min();
+
+ /*!
+ * \brief Returns maximum Rx gain
+ */
+ double gain_max();
+
+ /*!
+ * \brief Returns Rx gain db_per_step
+ */
+ double gain_db_per_step();
+
+ /*!
+ * \brief Returns minimum Rx center frequency
+ */
+ double freq_min();
+
+ /*!
+ * \brief Returns maximum Rx center frequency
+ */
+ double freq_max();
+
+ /*!
+ * \brief Get Rx daughterboard ID
+ *
+ * \param[out] dbid returns the daughterboard id.
+ *
+ * daughterboard id >= 0 if successful, -1 if no daugherboard installed,
+ * -2 if invalid EEPROM on daughterboard.
+ */
+ bool daughterboard_id(int *dbid);
+
+ /*!
+ * \brief Returns number of receiver overruns
+ */
+ unsigned int overruns();
+
+ /*!
+ * \brief Returns number of missing sequence numbers
+ */
+ unsigned int missing();
+
/*!
* \brief Called by scheduler when starting flowgraph
*/
#include <boost/utility.hpp>
#include <vector>
#include <complex>
-//#include <iosfwd>
#include <usrp2/rx_sample_handler.h>
#include <usrp2/tune_result.h>
projects / debian / gnuradio / commitdiff