return d_usrp_basic->fpga_master_clock_freq();
}
+void
+usrp_base::set_fpga_master_clock_freq(long master_clock)
+{
+ d_usrp_basic->set_fpga_master_clock_freq(master_clock);
+}
+
void
usrp_base::set_verbose (bool verbose)
{
/*!
* \brief return frequency of master oscillator on USRP
*/
- long fpga_master_clock_freq() const;
+ long fpga_master_clock_freq() const;
+
+ /*!
+ * Tell API that the master oscillator on the USRP is operating at a non-standard
+ * fixed frequency. This is only needed for custom USRP hardware modified to
+ * operate at a different frequency from the default factory configuration. This
+ * function must be called prior to any other API function.
+ * \param master_clock USRP2 FPGA master clock frequency in Hz (10..64 MHz)
+ */
+ void set_fpga_master_clock_freq (long master_clock);
void set_verbose (bool on);
db_base_sptr db(int which_side, int which_dev);
%rename (_real_selected_subdev) selected_subdev;
db_base_sptr selected_subdev(usrp_subdev_spec ss);
- long fpga_master_clock_freq() const;
+ long fpga_master_clock_freq() const;
+ void set_fpga_master_clock_freq(long master_clock);
void set_verbose (bool on);
static const int READ_FAILED = -99999;
bool write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf);
: d_udh (0),
d_usb_data_rate (16000000), // SWAG, see below
d_bytes_per_poll ((int) (POLLING_INTERVAL * d_usb_data_rate)),
- d_verbose (false), d_db(2)
+ d_verbose (false), d_fpga_master_clock_freq(64000000), d_db(2)
{
/*
* SWAG: Scientific Wild Ass Guess.
-
/* -*- c++ -*- */
/*
* Copyright 2003,2004,2008 Free Software Foundation, Inc.
int d_usb_data_rate; // bytes/sec
int d_bytes_per_poll; // how often to poll for overruns
bool d_verbose;
+ long d_fpga_master_clock_freq;
static const int MAX_REGS = 128;
unsigned int d_fpga_shadows[MAX_REGS];
/*!
* \brief return frequency of master oscillator on USRP
*/
- long fpga_master_clock_freq () const { return 64000000; }
+ long fpga_master_clock_freq () const { return d_fpga_master_clock_freq; }
+
+ /*!
+ * Tell API that the master oscillator on the USRP is operating at a non-standard
+ * fixed frequency. This is only needed for custom USRP hardware modified to
+ * operate at a different frequency from the default factory configuration. This
+ * function must be called prior to any other API function.
+ * \param master_clock USRP2 FPGA master clock frequency in Hz (10..64 MHz)
+ */
+ void set_fpga_master_clock_freq (long master_clock) { d_fpga_master_clock_freq = master_clock; }
/*!
* \returns usb data rate in bytes/sec