Minor impreovement to cse - prefer register equivalent (if iTemps share the

same spil location)

git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@1557 4a8a32a2-be11-0410-ad9d-d568d2c75423

diff --git a/src/SDCCcse.c b/src/SDCCcse.c
index 1b496915cac873388bbd02c700332f3221aebd8c..1f444374f4af883a9bd4fd54bf50da733f6b2c36 100644 (file)
--- a/src/SDCCcse.c
+++ b/src/SDCCcse.c
@@ -276,6 +276,7 @@ DEFSETFUNC (findCheaperOp)
                IS_ITEMP (IC_RESULT (cdp->diCode)) &&
                IS_ITEMP (IC_RIGHT (cdp->diCode)) &&
                !OP_SYMBOL (IC_RIGHT (cdp->diCode))->isind &&
+               !OP_SYMBOL(IC_RIGHT (cdp->diCode))->isreqv &&
                ((!SPIL_LOC (IC_RIGHT (cdp->diCode)) &&
                  SPIL_LOC (IC_RESULT (cdp->diCode))) ||
                 (SPIL_LOC (IC_RESULT (cdp->diCode)) &&
@@ -301,7 +302,8 @@ DEFSETFUNC (findCheaperOp)
     *opp = IC_RESULT (cdp->diCode);
 
   if ((*opp) && 
-      (isOperandLiteral(*opp) ||
+      (isOperandLiteral(*opp) || 
+       getSize(operandType(*opp)) == getSize(operandType(cop)) ||
        (SPEC_USIGN(operandType (cop))==SPEC_USIGN(operandType (*opp)) &&
        (SPEC_LONG(operandType (cop))==SPEC_LONG(operandType (*opp))))))
     {