else
manual_wp = false;
- res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_PBC);
- if (res != ERROR_OK) {
- LOG_ERROR("%s: %d", __func__, __LINE__);
- return res;
- }
+ if (manual_wp) {
+ LOG_WARNING("manual write mode detected");
+ nvm_ctrlb &= ~SAMD_NVM_CTRLB_MANW;
+ res = target_write_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, nvm_ctrlb);
+ if (res != ERROR_OK) {
+ LOG_ERROR("select automatic mode write_u32 failed");
+ return res;
+ }
+
+ res = target_read_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
+
+ if (res != ERROR_OK)
+ return res;
+
+ if (nvm_ctrlb & SAMD_NVM_CTRLB_MANW) {
+ LOG_ERROR("select automatic mode failed");
+ return ERROR_FAIL;
+ }
+
+ manual_wp = false;
+ } else
+ LOG_WARNING("automatic write mode detected");
while (count) {
+
+ res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_PBC);
+ if (res != ERROR_OK) {
+ LOG_ERROR("%s: %d", __func__, __LINE__);
+ return res;
+ }
+
nb = chip->page_size - offset % chip->page_size;
if (count < nb)
nb = count;
res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_WP);
} else {
/* Access through AHB is stalled while flash is being programmed */
- usleep(200);
+ usleep(1000);
res = samd_check_error(bank->target);
}