pcb-rnd --gui batch $(PROJECT).lht
# echo "Run pcb-rnd and import $(PROJECT).tdx"
+define pcb_drc
+ echo "Atomic(Save); DeleteRats(AllRats); Atomic(Restore); AddRats(AllRats); Atomic(Close)" | pcb-rnd --gui batch $(PROJECT).lht | grep "The layout is complete and has no shorted nets."
+endef
+
define emit_xyrs
pcb-rnd -x XY $(PROJECT).lht
endef
ac: $(PROJECT)-ac-pcb.zip $(PROJECT)-ac-asy.zip
$(PROJECT)-ac-pcb.zip: $(PROJECT).lht $(CONFIG)
+ $(call pcb_drc)
pcb-rnd -x cam gerber:universal --outfile out/$(PROJECT) $(PROJECT).lht
rm -f $@ && zip -j $@ out/*
oshpark: $(PROJECT)-oshpark.zip
$(PROJECT)-oshpark.zip: $(PROJECT).lht $(CONFIG)
+ $(call pcb_drc)
pcb-rnd -x cam gerber:OSH_Park --outfile out/$(PROJECT) $(PROJECT).lht
$(call emit_xyrs)
rm -f $@ && zip -j $@ out/* $(PROJECT).xy
seeed: $(PROJECT)-seeed.zip $(PROJECT)-seeed.csv
$(PROJECT)-seeed.zip: $(PROJECT).lht $(CONFIG) $(PROJECT)-sch.pdf $(SEEED_EXTRA)
+ $(call pcb_drc)
pcb-rnd -x cam doc_pnp_gerber --outfile out/$(PROJECT) $(PROJECT).lht
pcb-rnd -x cam gerber:Seeed --outfile out/$(PROJECT) $(PROJECT).lht
$(call emit_xyrs)
jlcpcb: $(PROJECT)-jlcpcb.zip
$(PROJECT)-jlcpcb.zip: $(PROJECT).lht $(CONFIG)
+ $(call pcb_drc)
pcb-rnd -x cam gerber:JLC_PCB --outfile out/$(PROJECT) $(PROJECT).lht
$(call emit_xyrs)
rm -f $@ && zip -j $@ out/* $(PROJECT).xy
jlcpcba: $(PROJECT)-jlcpcba.zip
$(PROJECT)-jlcpcba.zip: $(PROJECT).lht $(CONFIG) $(PROJECT)-jlcpcb.csv
+ $(call pcb_drc)
pcb-rnd -x cam gerber:JLC_PCB --outfile out/$(PROJECT) $(PROJECT).lht
$(call emit_xyrs)
rm -f $@ && zip -j $@ out/* $(PROJECT).xy $(PROJECT)-jlcpcb.csv