+2006-05-01 Raphael Neider <rneider AT web.de>
+
+ * src/pic/device.c (sanitise_processor_name): only remove p(ic) prefix,
+ (create_pic): store only prefix-free device name,
+ (init_pic): check for device names with "16" prefix,
+ (list_valid_pics),
+ * src/pic/device.h (struct PIC_device),
+ * src/pic/main.c (_pic14_genAssemblerPreamble): adapted to single
+ stored device name,
+ * device/include/pic/pic12f{635,675,629,683}.h,
+ * device/lib/pic/libdev/pic12f{635,675,629,683}.c: NEW device libraries
+ * device/lib/pic/libdev/Makefile.in: allow pic12* devices,
+ * device/include/pic/pic16f505.h,
+ * device/lib/pic/libdev/pic16f505.c: removed
+ * device/include/pic/pic14devices.txt: added support for pic12f
+ devices, removed unsupported non 16-bit devices
+ [above changes provided by patch from Zik Saleeba]
+ * src/pic/*, src/pic16/*, device/include/pic16/*,
+ device/lib/pic/**, device/lib/pic16/**: obfuscated email address
+
2006-05-01 Borut Razem <borut.razem AT siol.net>
* configure.in, configure, doc/Makefile.in:
--- /dev/null
+//
+// Register Declarations for Microchip 12F629 Processor
+//
+//
+// This header file was automatically generated by:
+//
+// inc2h.pl V1.7
+//
+// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
+//
+// SDCC is licensed under the GNU Public license (GPL) v2. Note that
+// this license covers the code to the compiler and other executables,
+// but explicitly does not cover any code or objects generated by sdcc.
+// We have not yet decided on a license for the run time libraries, but
+// it will not put any requirements on code linked against it. See:
+//
+// http://www.gnu.org/copyleft/gpl/html
+//
+// See http://sdcc.sourceforge.net/ for the latest information on sdcc.
+//
+//
+#ifndef P12F629_H
+#define P12F629_H
+
+//
+// Register addresses.
+//
+#define INDF_ADDR 0x0000
+#define TMR0_ADDR 0x0001
+#define PCL_ADDR 0x0002
+#define STATUS_ADDR 0x0003
+#define FSR_ADDR 0x0004
+#define GPIO_ADDR 0x0005
+#define PCLATH_ADDR 0x000A
+#define INTCON_ADDR 0x000B
+#define PIR1_ADDR 0x000C
+#define TMR1L_ADDR 0x000E
+#define TMR1H_ADDR 0x000F
+#define T1CON_ADDR 0x0010
+#define CMCON_ADDR 0x0019
+#define OPTION_REG_ADDR 0x0081
+#define TRISIO_ADDR 0x0085
+#define PIE1_ADDR 0x008C
+#define PCON_ADDR 0x008E
+#define OSCCAL_ADDR 0x0090
+#define WPU_ADDR 0x0095
+#define IOCB_ADDR 0x0096
+#define IOC_ADDR 0x0096
+#define VRCON_ADDR 0x0099
+#define EEDATA_ADDR 0x009A
+#define EEDAT_ADDR 0x009A
+#define EEADR_ADDR 0x009B
+#define EECON1_ADDR 0x009C
+#define EECON2_ADDR 0x009D
+
+//
+// Memory organization.
+//
+
+#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
+#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
+#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
+#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
+#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
+#pragma memmap GPIO_ADDR GPIO_ADDR SFR 0x000 // GPIO
+#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
+#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
+#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
+#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
+#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
+#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
+#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON
+#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
+#pragma memmap TRISIO_ADDR TRISIO_ADDR SFR 0x000 // TRISIO
+#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
+#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
+#pragma memmap OSCCAL_ADDR OSCCAL_ADDR SFR 0x000 // OSCCAL
+#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU
+#pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB
+#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC
+#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
+#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
+#pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT
+#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
+#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
+#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
+
+
+// LIST
+// P12F629.INC Standard Header File, Version 1.04 Microchip Technology, Inc.
+// NOLIST
+
+// This header file defines configurations, registers, and other useful bits of
+// information for the PIC12F629 microcontroller. These names are taken to match
+// the data sheets as closely as possible.
+
+// Note that the processor must be selected before this file is
+// included. The processor may be selected the following ways:
+
+// 1. Command line switch:
+// C:\ MPASM MYFILE.ASM /PIC12F629
+// 2. LIST directive in the source file
+// LIST P=PIC12F629
+// 3. Processor Type entry in the MPASM full-screen interface
+
+//==========================================================================
+//
+// Revision History
+//
+//==========================================================================
+//1.04 07/01/02 Updated configuration bit names
+//1.03 05/10/02 Added IOC register
+//1.02 02/28/02 Updated per datasheet
+//1.01 01/31/02 Updated per datasheet
+//1.00 08/24/01 Original
+
+//==========================================================================
+//
+// Verify Processor
+//
+//==========================================================================
+
+// IFNDEF __12F629
+// MESSG "Processor-header file mismatch. Verify selected processor."
+// ENDIF
+
+//==========================================================================
+//
+// Register Definitions
+//
+//==========================================================================
+
+#define W 0x0000
+#define F 0x0001
+
+//----- Register Files------------------------------------------------------
+
+extern __data __at (INDF_ADDR) volatile char INDF;
+extern __sfr __at (TMR0_ADDR) TMR0;
+extern __data __at (PCL_ADDR) volatile char PCL;
+extern __sfr __at (STATUS_ADDR) STATUS;
+extern __sfr __at (FSR_ADDR) FSR;
+extern __sfr __at (GPIO_ADDR) GPIO;
+
+extern __sfr __at (PCLATH_ADDR) PCLATH;
+extern __sfr __at (INTCON_ADDR) INTCON;
+extern __sfr __at (PIR1_ADDR) PIR1;
+
+extern __sfr __at (TMR1L_ADDR) TMR1L;
+extern __sfr __at (TMR1H_ADDR) TMR1H;
+extern __sfr __at (T1CON_ADDR) T1CON;
+
+extern __sfr __at (CMCON_ADDR) CMCON;
+
+extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
+
+extern __sfr __at (TRISIO_ADDR) TRISIO;
+
+extern __sfr __at (PIE1_ADDR) PIE1;
+
+extern __sfr __at (PCON_ADDR) PCON;
+
+extern __sfr __at (OSCCAL_ADDR) OSCCAL;
+
+extern __sfr __at (WPU_ADDR) WPU;
+extern __sfr __at (IOCB_ADDR) IOCB;
+extern __sfr __at (IOC_ADDR) IOC;
+
+extern __sfr __at (VRCON_ADDR) VRCON;
+extern __sfr __at (EEDATA_ADDR) EEDATA;
+extern __sfr __at (EEDAT_ADDR) EEDAT;
+extern __sfr __at (EEADR_ADDR) EEADR;
+extern __sfr __at (EECON1_ADDR) EECON1;
+extern __sfr __at (EECON2_ADDR) EECON2;
+
+//----- STATUS Bits --------------------------------------------------------
+
+
+//----- GPIO Bits --------------------------------------------------------
+
+
+
+
+//----- INTCON Bits --------------------------------------------------------
+
+
+//----- PIR1 Bits ----------------------------------------------------------
+
+
+//----- T1CON Bits ---------------------------------------------------------
+
+
+//----- CMCON Bits --------------------------------------------------------
+
+
+//----- OPTION Bits --------------------------------------------------------
+
+
+//----- PIE1 Bits ----------------------------------------------------------
+
+
+//----- PCON Bits ----------------------------------------------------------
+
+
+//----- OSCCAL Bits --------------------------------------------------------
+
+
+//----- IOCB Bits --------------------------------------------------------
+
+
+//----- IOC Bits --------------------------------------------------------
+
+
+//----- VRCON Bits ---------------------------------------------------------
+
+
+//----- EECON1 -------------------------------------------------------------
+
+
+//==========================================================================
+//
+// RAM Definition
+//
+//==========================================================================
+
+// __MAXRAM H'FF'
+// __BADRAM H'06'-H'09', H'0D', H'11'-H'18', H'1A'-H'1F', H'60'-H'7F'
+// __BADRAM H'86'-H'89', H'8D', H'8F', H'91'-H'94', H'97'-H'98', H'9E'-H'9F', H'E0'-H'FF'
+
+//==========================================================================
+//
+// Configuration Bits
+//
+//==========================================================================
+
+#define _CPD_ON 0x3EFF
+#define _CPD_OFF 0x3FFF
+#define _CP_ON 0x3F7F
+#define _CP_OFF 0x3FFF
+#define _BODEN_ON 0x3FFF
+#define _BODEN_OFF 0x3FBF
+#define _MCLRE_ON 0x3FFF
+#define _MCLRE_OFF 0x3FDF
+#define _PWRTE_OFF 0x3FFF
+#define _PWRTE_ON 0x3FEF
+#define _WDT_ON 0x3FFF
+#define _WDT_OFF 0x3FF7
+#define _LP_OSC 0x3FF8
+#define _XT_OSC 0x3FF9
+#define _HS_OSC 0x3FFA
+#define _EC_OSC 0x3FFB
+#define _INTRC_OSC_NOCLKOUT 0x3FFC
+#define _INTRC_OSC_CLKOUT 0x3FFD
+#define _EXTRC_OSC_NOCLKOUT 0x3FFE
+#define _EXTRC_OSC_CLKOUT 0x3FFF
+
+// LIST
+
+// ----- CMCON bits --------------------
+typedef union {
+ struct {
+ unsigned char CM0:1;
+ unsigned char CM1:1;
+ unsigned char CM2:1;
+ unsigned char CIS:1;
+ unsigned char CINV:1;
+ unsigned char :1;
+ unsigned char COUT:1;
+ unsigned char :1;
+ };
+} __CMCON_bits_t;
+extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
+
+#define CM0 CMCON_bits.CM0
+#define CM1 CMCON_bits.CM1
+#define CM2 CMCON_bits.CM2
+#define CIS CMCON_bits.CIS
+#define CINV CMCON_bits.CINV
+#define COUT CMCON_bits.COUT
+
+// ----- GPIO bits --------------------
+typedef union {
+ struct {
+ unsigned char GP0:1;
+ unsigned char GP1:1;
+ unsigned char GP2:1;
+ unsigned char GP3:1;
+ unsigned char GP4:1;
+ unsigned char GP5:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+ struct {
+ unsigned char GPIO0:1;
+ unsigned char GPIO1:1;
+ unsigned char GPIO2:1;
+ unsigned char GPIO3:1;
+ unsigned char GPIO4:1;
+ unsigned char GPIO5:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __GPIO_bits_t;
+extern volatile __GPIO_bits_t __at(GPIO_ADDR) GPIO_bits;
+
+#define GP0 GPIO_bits.GP0
+#define GPIO0 GPIO_bits.GPIO0
+#define GP1 GPIO_bits.GP1
+#define GPIO1 GPIO_bits.GPIO1
+#define GP2 GPIO_bits.GP2
+#define GPIO2 GPIO_bits.GPIO2
+#define GP3 GPIO_bits.GP3
+#define GPIO3 GPIO_bits.GPIO3
+#define GP4 GPIO_bits.GP4
+#define GPIO4 GPIO_bits.GPIO4
+#define GP5 GPIO_bits.GP5
+#define GPIO5 GPIO_bits.GPIO5
+
+// ----- INTCON bits --------------------
+typedef union {
+ struct {
+ unsigned char GPIF:1;
+ unsigned char INTF:1;
+ unsigned char T0IF:1;
+ unsigned char GPIE:1;
+ unsigned char INTE:1;
+ unsigned char T0IE:1;
+ unsigned char PEIE:1;
+ unsigned char GIE:1;
+ };
+} __INTCON_bits_t;
+extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
+
+#define GPIF INTCON_bits.GPIF
+#define INTF INTCON_bits.INTF
+#define T0IF INTCON_bits.T0IF
+#define GPIE INTCON_bits.GPIE
+#define INTE INTCON_bits.INTE
+#define T0IE INTCON_bits.T0IE
+#define PEIE INTCON_bits.PEIE
+#define GIE INTCON_bits.GIE
+
+// ----- IOC bits --------------------
+typedef union {
+ struct {
+ unsigned char IOC0:1;
+ unsigned char IOC1:1;
+ unsigned char IOC2:1;
+ unsigned char IOC3:1;
+ unsigned char IOC4:1;
+ unsigned char IOC5:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __IOC_bits_t;
+extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
+
+#define IOC0 IOC_bits.IOC0
+#define IOC1 IOC_bits.IOC1
+#define IOC2 IOC_bits.IOC2
+#define IOC3 IOC_bits.IOC3
+#define IOC4 IOC_bits.IOC4
+#define IOC5 IOC_bits.IOC5
+
+// ----- IOCB bits --------------------
+typedef union {
+ struct {
+ unsigned char IOCB0:1;
+ unsigned char IOCB1:1;
+ unsigned char IOCB2:1;
+ unsigned char IOCB3:1;
+ unsigned char IOCB4:1;
+ unsigned char IOCB5:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __IOCB_bits_t;
+extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
+
+#define IOCB0 IOCB_bits.IOCB0
+#define IOCB1 IOCB_bits.IOCB1
+#define IOCB2 IOCB_bits.IOCB2
+#define IOCB3 IOCB_bits.IOCB3
+#define IOCB4 IOCB_bits.IOCB4
+#define IOCB5 IOCB_bits.IOCB5
+
+// ----- OPTION_REG bits --------------------
+typedef union {
+ struct {
+ unsigned char PS0:1;
+ unsigned char PS1:1;
+ unsigned char PS2:1;
+ unsigned char PSA:1;
+ unsigned char T0SE:1;
+ unsigned char T0CS:1;
+ unsigned char INTEDG:1;
+ unsigned char NOT_GPPU:1;
+ };
+} __OPTION_REG_bits_t;
+extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
+
+#define PS0 OPTION_REG_bits.PS0
+#define PS1 OPTION_REG_bits.PS1
+#define PS2 OPTION_REG_bits.PS2
+#define PSA OPTION_REG_bits.PSA
+#define T0SE OPTION_REG_bits.T0SE
+#define T0CS OPTION_REG_bits.T0CS
+#define INTEDG OPTION_REG_bits.INTEDG
+#define NOT_GPPU OPTION_REG_bits.NOT_GPPU
+
+// ----- OSCCAL bits --------------------
+typedef union {
+ struct {
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char CAL0:1;
+ unsigned char CAL1:1;
+ unsigned char CAL2:1;
+ unsigned char CAL3:1;
+ unsigned char CAL4:1;
+ unsigned char CAL5:1;
+ };
+} __OSCCAL_bits_t;
+extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits;
+
+#define CAL0 OSCCAL_bits.CAL0
+#define CAL1 OSCCAL_bits.CAL1
+#define CAL2 OSCCAL_bits.CAL2
+#define CAL3 OSCCAL_bits.CAL3
+#define CAL4 OSCCAL_bits.CAL4
+#define CAL5 OSCCAL_bits.CAL5
+
+// ----- PCON bits --------------------
+typedef union {
+ struct {
+ unsigned char NOT_BOD:1;
+ unsigned char NOT_POR:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __PCON_bits_t;
+extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
+
+#define NOT_BOD PCON_bits.NOT_BOD
+#define NOT_POR PCON_bits.NOT_POR
+
+// ----- PIE1 bits --------------------
+typedef union {
+ struct {
+ unsigned char T1IE:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char CMIE:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char ADIE:1;
+ unsigned char EEIE:1;
+ };
+ struct {
+ unsigned char TMR1IE:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __PIE1_bits_t;
+extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
+
+#define T1IE PIE1_bits.T1IE
+#define TMR1IE PIE1_bits.TMR1IE
+#define CMIE PIE1_bits.CMIE
+#define ADIE PIE1_bits.ADIE
+#define EEIE PIE1_bits.EEIE
+
+// ----- PIR1 bits --------------------
+typedef union {
+ struct {
+ unsigned char T1IF:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char CMIF:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char ADIF:1;
+ unsigned char EEIF:1;
+ };
+ struct {
+ unsigned char TMR1IF:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __PIR1_bits_t;
+extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
+
+#define T1IF PIR1_bits.T1IF
+#define TMR1IF PIR1_bits.TMR1IF
+#define CMIF PIR1_bits.CMIF
+#define ADIF PIR1_bits.ADIF
+#define EEIF PIR1_bits.EEIF
+
+// ----- STATUS bits --------------------
+typedef union {
+ struct {
+ unsigned char C:1;
+ unsigned char DC:1;
+ unsigned char Z:1;
+ unsigned char NOT_PD:1;
+ unsigned char NOT_TO:1;
+ unsigned char RP0:1;
+ unsigned char RP1:1;
+ unsigned char IRP:1;
+ };
+} __STATUS_bits_t;
+extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
+
+#define C STATUS_bits.C
+#define DC STATUS_bits.DC
+#define Z STATUS_bits.Z
+#define NOT_PD STATUS_bits.NOT_PD
+#define NOT_TO STATUS_bits.NOT_TO
+#define RP0 STATUS_bits.RP0
+#define RP1 STATUS_bits.RP1
+#define IRP STATUS_bits.IRP
+
+// ----- T1CON bits --------------------
+typedef union {
+ struct {
+ unsigned char TMR1ON:1;
+ unsigned char TMR1CS:1;
+ unsigned char NOT_T1SYNC:1;
+ unsigned char T1OSCEN:1;
+ unsigned char T1CKPS0:1;
+ unsigned char T1CKPS1:1;
+ unsigned char TMR1GE:1;
+ unsigned char :1;
+ };
+} __T1CON_bits_t;
+extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
+
+#define TMR1ON T1CON_bits.TMR1ON
+#define TMR1CS T1CON_bits.TMR1CS
+#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
+#define T1OSCEN T1CON_bits.T1OSCEN
+#define T1CKPS0 T1CON_bits.T1CKPS0
+#define T1CKPS1 T1CON_bits.T1CKPS1
+#define TMR1GE T1CON_bits.TMR1GE
+
+// ----- VRCON bits --------------------
+typedef union {
+ struct {
+ unsigned char VR0:1;
+ unsigned char VR1:1;
+ unsigned char VR2:1;
+ unsigned char VR3:1;
+ unsigned char :1;
+ unsigned char VRR:1;
+ unsigned char :1;
+ unsigned char VREN:1;
+ };
+ struct {
+ unsigned char RD:1;
+ unsigned char WR:1;
+ unsigned char WREN:1;
+ unsigned char WRERR:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __VRCON_bits_t;
+extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
+
+#define VR0 VRCON_bits.VR0
+#define RD VRCON_bits.RD
+#define VR1 VRCON_bits.VR1
+#define WR VRCON_bits.WR
+#define VR2 VRCON_bits.VR2
+#define WREN VRCON_bits.WREN
+#define VR3 VRCON_bits.VR3
+#define WRERR VRCON_bits.WRERR
+#define VRR VRCON_bits.VRR
+#define VREN VRCON_bits.VREN
+
+#endif
--- /dev/null
+//
+// Register Declarations for Microchip 12F635 Processor
+//
+//
+// This header file was automatically generated by:
+//
+// inc2h.pl V1.7
+//
+// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
+//
+// SDCC is licensed under the GNU Public license (GPL) v2. Note that
+// this license covers the code to the compiler and other executables,
+// but explicitly does not cover any code or objects generated by sdcc.
+// We have not yet decided on a license for the run time libraries, but
+// it will not put any requirements on code linked against it. See:
+//
+// http://www.gnu.org/copyleft/gpl/html
+//
+// See http://sdcc.sourceforge.net/ for the latest information on sdcc.
+//
+//
+#ifndef P12F635_H
+#define P12F635_H
+
+//
+// Register addresses.
+//
+#define INDF_ADDR 0x0000
+#define TMR0_ADDR 0x0001
+#define PCL_ADDR 0x0002
+#define STATUS_ADDR 0x0003
+#define FSR_ADDR 0x0004
+#define PORTA_ADDR 0x0005
+#define GPIO_ADDR 0x0005
+#define PCLATH_ADDR 0x000A
+#define INTCON_ADDR 0x000B
+#define PIR1_ADDR 0x000C
+#define TMR1L_ADDR 0x000E
+#define TMR1H_ADDR 0x000F
+#define T1CON_ADDR 0x0010
+#define WDTCON_ADDR 0x0018
+#define CMCON0_ADDR 0x0019
+#define CMCON1_ADDR 0x001A
+#define OPTION_REG_ADDR 0x0081
+#define TRISA_ADDR 0x0085
+#define TRISIO_ADDR 0x0085
+#define PIE1_ADDR 0x008C
+#define PCON_ADDR 0x008E
+#define OSCCON_ADDR 0x008F
+#define OSCTUNE_ADDR 0x0090
+#define LVDCON_ADDR 0x0094
+#define WPUDA_ADDR 0x0095
+#define IOCA_ADDR 0x0096
+#define WDA_ADDR 0x0097
+#define VRCON_ADDR 0x0099
+#define EEDAT_ADDR 0x009A
+#define EEDATA_ADDR 0x009A
+#define EEADR_ADDR 0x009B
+#define EECON1_ADDR 0x009C
+#define EECON2_ADDR 0x009D
+#define CRCON_ADDR 0x0110
+#define CRDAT0_ADDR 0x0111
+#define CRDAT1_ADDR 0x0112
+#define CRDAT2_ADDR 0x0113
+#define CRDAT3_ADDR 0x0114
+
+//
+// Memory organization.
+//
+
+#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
+#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
+#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
+#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
+#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
+#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
+#pragma memmap GPIO_ADDR GPIO_ADDR SFR 0x000 // GPIO
+#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
+#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
+#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
+#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
+#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
+#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
+#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
+#pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0
+#pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1
+#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
+#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
+#pragma memmap TRISIO_ADDR TRISIO_ADDR SFR 0x000 // TRISIO
+#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
+#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
+#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
+#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
+#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON
+#pragma memmap WPUDA_ADDR WPUDA_ADDR SFR 0x000 // WPUDA
+#pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA
+#pragma memmap WDA_ADDR WDA_ADDR SFR 0x000 // WDA
+#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
+#pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT
+#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
+#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
+#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
+#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
+#pragma memmap CRCON_ADDR CRCON_ADDR SFR 0x000 // CRCON
+#pragma memmap CRDAT0_ADDR CRDAT0_ADDR SFR 0x000 // CRDAT0
+#pragma memmap CRDAT1_ADDR CRDAT1_ADDR SFR 0x000 // CRDAT1
+#pragma memmap CRDAT2_ADDR CRDAT2_ADDR SFR 0x000 // CRDAT2
+#pragma memmap CRDAT3_ADDR CRDAT3_ADDR SFR 0x000 // CRDAT3
+
+
+// LIST
+// P12F635.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
+// NOLIST
+
+// This header file defines configurations, registers, and other useful bits of
+// information for the PIC12F635 microcontroller. These names are taken to match
+// the data sheets as closely as possible.
+
+// Note that the processor must be selected before this file is
+// included. The processor may be selected the following ways:
+
+// 1. Command line switch:
+// C:\ MPASM MYFILE.ASM /PIC12F635
+// 2. LIST directive in the source file
+// LIST P=PIC12F635
+// 3. Processor Type entry in the MPASM full-screen interface
+
+//==========================================================================
+//
+// Revision History
+//
+//==========================================================================
+//1.00 12/07/03 Original
+//1.10 04/19/04 Release to match first revision datasheet --kjd
+//1.20 06/07/04 Update and correct badram definitions --kjd
+//==========================================================================
+//
+// Verify Processor
+//
+//==========================================================================
+
+// IFNDEF __12F635
+// MESSG "Processor-header file mismatch. Verify selected processor."
+// ENDIF
+
+//==========================================================================
+//
+// Register Definitions
+//
+//==========================================================================
+
+#define W 0x0000
+#define F 0x0001
+
+//----- Register Files------------------------------------------------------
+//Bank 0
+extern __data __at (INDF_ADDR) volatile char INDF;
+extern __sfr __at (TMR0_ADDR) TMR0;
+extern __data __at (PCL_ADDR) volatile char PCL;
+extern __sfr __at (STATUS_ADDR) STATUS;
+extern __sfr __at (FSR_ADDR) FSR;
+extern __sfr __at (PORTA_ADDR) PORTA;
+extern __sfr __at (GPIO_ADDR) GPIO;
+
+extern __sfr __at (PCLATH_ADDR) PCLATH;
+extern __sfr __at (INTCON_ADDR) INTCON;
+extern __sfr __at (PIR1_ADDR) PIR1;
+
+extern __sfr __at (TMR1L_ADDR) TMR1L;
+extern __sfr __at (TMR1H_ADDR) TMR1H;
+extern __sfr __at (T1CON_ADDR) T1CON;
+
+extern __sfr __at (WDTCON_ADDR) WDTCON;
+extern __sfr __at (CMCON0_ADDR) CMCON0;
+extern __sfr __at (CMCON1_ADDR) CMCON1;
+
+//Bank 1
+extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
+
+extern __sfr __at (TRISA_ADDR) TRISA;
+extern __sfr __at (TRISIO_ADDR) TRISIO;
+
+extern __sfr __at (PIE1_ADDR) PIE1;
+
+extern __sfr __at (PCON_ADDR) PCON;
+extern __sfr __at (OSCCON_ADDR) OSCCON;
+extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
+
+extern __sfr __at (LVDCON_ADDR) LVDCON;
+extern __sfr __at (WPUDA_ADDR) WPUDA;
+extern __sfr __at (IOCA_ADDR) IOCA;
+extern __sfr __at (WDA_ADDR) WDA;
+
+extern __sfr __at (VRCON_ADDR) VRCON;
+extern __sfr __at (EEDAT_ADDR) EEDAT;
+extern __sfr __at (EEDATA_ADDR) EEDATA;
+extern __sfr __at (EEADR_ADDR) EEADR;
+extern __sfr __at (EECON1_ADDR) EECON1;
+extern __sfr __at (EECON2_ADDR) EECON2;
+
+//Bank 2
+extern __sfr __at (CRCON_ADDR) CRCON;
+extern __sfr __at (CRDAT0_ADDR) CRDAT0;
+extern __sfr __at (CRDAT1_ADDR) CRDAT1;
+extern __sfr __at (CRDAT2_ADDR) CRDAT2;
+extern __sfr __at (CRDAT3_ADDR) CRDAT3;
+
+//----- STATUS Bits --------------------------------------------------------
+
+
+//----- INTCON Bits --------------------------------------------------------
+
+
+//----- PIR1 Bits ----------------------------------------------------------
+
+
+//----- T1CON Bits ---------------------------------------------------------
+
+
+//----- WDTCON Bits --------------------------------------------------------
+
+
+//----- CMCON0 Bits -------------------------------------------------------
+
+
+//----- CMCON1 Bits -------------------------------------------------------
+
+
+//----- OPTION Bits --------------------------------------------------------
+
+
+//----- PIE1 Bits ----------------------------------------------------------
+
+
+//----- PCON Bits ----------------------------------------------------------
+
+
+//----- OSCCON Bits --------------------------------------------------------
+
+
+//----- OSCTUNE Bits -------------------------------------------------------
+
+
+//----- IOCA --------------------------------------------------------------
+
+
+//----- EECON1 -------------------------------------------------------------
+
+
+//----- VRCON ---------------------------------------------------------
+
+
+
+//----- CRCON -------------------------------------------------------------
+
+
+//----- LVDCON -------------------------------------------------------------
+
+
+//----- WDA -------------------------------------------------------------
+
+
+//----- WPUDA -------------------------------------------------------------
+
+
+//----- PORTA -------------------------------------------------------------
+
+
+//----- GPIO -------------------------------------------------------------
+
+
+//==========================================================================
+//
+// RAM Definition
+//
+//==========================================================================
+
+// __MAXRAM H'1FF'
+// __BADRAM H'06'-H'09', H'0D', H'11'-H'17', H'1B'-H'1F', H'20'-H'3F'
+// __BADRAM H'86'-H'89', H'8D', H'91'-H'93', H'98', H'9E'-H'9F', H'A0'-H'EF'
+// __BADRAM H'10C'-H'10F', H'115'-H'16F', H'106'-H'109', H'186'-H'189'
+// __BADRAM H'18C'-H'1EF'
+
+//==========================================================================
+//
+// Configuration Bits
+//
+//==========================================================================
+#define _WUREN_ON 0x2FFF
+#define _WUREN_OFF 0x3FFF
+#define _FCMEN_ON 0x3FFF
+#define _FCMEN_OFF 0x37FF
+#define _IESO_ON 0x3FFF
+#define _IESO_OFF 0x3BFF
+#define _BOD_ON 0x3FFF
+#define _BOD_NSLEEP 0x3EFF
+#define _BOD_SBODEN 0x3DFF
+#define _BOD_OFF 0x3CFF
+#define _CPD_ON 0x3F7F
+#define _CPD_OFF 0x3FFF
+#define _CP_ON 0x3FBF
+#define _CP_OFF 0x3FFF
+#define _MCLRE_ON 0x3FFF
+#define _MCLRE_OFF 0x3FDF
+#define _PWRTE_OFF 0x3FFF
+#define _PWRTE_ON 0x3FEF
+#define _WDT_ON 0x3FFF
+#define _WDT_OFF 0x3FF7
+#define _LP_OSC 0x3FF8
+#define _XT_OSC 0x3FF9
+#define _HS_OSC 0x3FFA
+#define _EC_OSC 0x3FFB
+#define _INTRC_OSC_NOCLKOUT 0x3FFC
+#define _INTRC_OSC_CLKOUT 0x3FFD
+#define _EXTRC_OSC_NOCLKOUT 0x3FFE
+#define _EXTRC_OSC_CLKOUT 0x3FFF
+
+// LIST
+
+// ----- CMCON0 bits --------------------
+typedef union {
+ struct {
+ unsigned char CM0:1;
+ unsigned char CM1:1;
+ unsigned char CM2:1;
+ unsigned char CIS:1;
+ unsigned char C1INV:1;
+ unsigned char :1;
+ unsigned char C1OUT:1;
+ unsigned char :1;
+ };
+} __CMCON0_bits_t;
+extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
+
+#define CM0 CMCON0_bits.CM0
+#define CM1 CMCON0_bits.CM1
+#define CM2 CMCON0_bits.CM2
+#define CIS CMCON0_bits.CIS
+#define C1INV CMCON0_bits.C1INV
+#define C1OUT CMCON0_bits.C1OUT
+
+// ----- CMCON1 bits --------------------
+typedef union {
+ struct {
+ unsigned char C1SYNC:1;
+ unsigned char T1GSS:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __CMCON1_bits_t;
+extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
+
+#define C1SYNC CMCON1_bits.C1SYNC
+#define T1GSS CMCON1_bits.T1GSS
+
+// ----- INTCON bits --------------------
+typedef union {
+ struct {
+ unsigned char RAIF:1;
+ unsigned char INTF:1;
+ unsigned char T0IF:1;
+ unsigned char RAIE:1;
+ unsigned char INTE:1;
+ unsigned char T0IE:1;
+ unsigned char PEIE:1;
+ unsigned char GIE:1;
+ };
+} __INTCON_bits_t;
+extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
+
+#define RAIF INTCON_bits.RAIF
+#define INTF INTCON_bits.INTF
+#define T0IF INTCON_bits.T0IF
+#define RAIE INTCON_bits.RAIE
+#define INTE INTCON_bits.INTE
+#define T0IE INTCON_bits.T0IE
+#define PEIE INTCON_bits.PEIE
+#define GIE INTCON_bits.GIE
+
+// ----- OPTION_REG bits --------------------
+typedef union {
+ struct {
+ unsigned char PS0:1;
+ unsigned char PS1:1;
+ unsigned char PS2:1;
+ unsigned char PSA:1;
+ unsigned char T0SE:1;
+ unsigned char T0CS:1;
+ unsigned char INTEDG:1;
+ unsigned char NOT_RAPU:1;
+ };
+} __OPTION_REG_bits_t;
+extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
+
+#define PS0 OPTION_REG_bits.PS0
+#define PS1 OPTION_REG_bits.PS1
+#define PS2 OPTION_REG_bits.PS2
+#define PSA OPTION_REG_bits.PSA
+#define T0SE OPTION_REG_bits.T0SE
+#define T0CS OPTION_REG_bits.T0CS
+#define INTEDG OPTION_REG_bits.INTEDG
+#define NOT_RAPU OPTION_REG_bits.NOT_RAPU
+
+// ----- OSCCON bits --------------------
+typedef union {
+ struct {
+ unsigned char SCS:1;
+ unsigned char LTS:1;
+ unsigned char HTS:1;
+ unsigned char OSTS:1;
+ unsigned char IRCF0:1;
+ unsigned char IRCF1:1;
+ unsigned char IRCF2:1;
+ unsigned char :1;
+ };
+} __OSCCON_bits_t;
+extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
+
+#define SCS OSCCON_bits.SCS
+#define LTS OSCCON_bits.LTS
+#define HTS OSCCON_bits.HTS
+#define OSTS OSCCON_bits.OSTS
+#define IRCF0 OSCCON_bits.IRCF0
+#define IRCF1 OSCCON_bits.IRCF1
+#define IRCF2 OSCCON_bits.IRCF2
+
+// ----- OSCTUNE bits --------------------
+typedef union {
+ struct {
+ unsigned char TUN0:1;
+ unsigned char TUN1:1;
+ unsigned char TUN2:1;
+ unsigned char TUN3:1;
+ unsigned char TUN4:1;
+ unsigned char IOCA5:1;
+ unsigned char ENC_DEC:1;
+ unsigned char VREN:1;
+ };
+ struct {
+ unsigned char IOCA0:1;
+ unsigned char IOCA1:1;
+ unsigned char IOCA2:1;
+ unsigned char IOCA3:1;
+ unsigned char IOCA4:1;
+ unsigned char VRR:1;
+ unsigned char :1;
+ unsigned char GO:1;
+ };
+ struct {
+ unsigned char RD:1;
+ unsigned char WR:1;
+ unsigned char WREN:1;
+ unsigned char WRERR:1;
+ unsigned char PLVDEN:1;
+ unsigned char IRVST:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+ struct {
+ unsigned char VR0:1;
+ unsigned char VR1:1;
+ unsigned char VR2:1;
+ unsigned char VR3:1;
+ unsigned char WDA4:1;
+ unsigned char WDA5:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+ struct {
+ unsigned char CRREG0:1;
+ unsigned char CRREG1:1;
+ unsigned char LVDL2:1;
+ unsigned char RA3:1;
+ unsigned char WPUDA4:1;
+ unsigned char WPUDA5:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+ struct {
+ unsigned char LVDL0:1;
+ unsigned char LVDL1:1;
+ unsigned char WDA2:1;
+ unsigned char GP3:1;
+ unsigned char RA4:1;
+ unsigned char RA5:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+ struct {
+ unsigned char WDA0:1;
+ unsigned char WDA1:1;
+ unsigned char WPUDA2:1;
+ unsigned char :1;
+ unsigned char GP4:1;
+ unsigned char GP5:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+ struct {
+ unsigned char WPUDA0:1;
+ unsigned char WPUDA1:1;
+ unsigned char RA2:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+ struct {
+ unsigned char RA0:1;
+ unsigned char RA1:1;
+ unsigned char GP2:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+ struct {
+ unsigned char GP0:1;
+ unsigned char GP1:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __OSCTUNE_bits_t;
+extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
+
+#define TUN0 OSCTUNE_bits.TUN0
+#define IOCA0 OSCTUNE_bits.IOCA0
+#define RD OSCTUNE_bits.RD
+#define VR0 OSCTUNE_bits.VR0
+#define CRREG0 OSCTUNE_bits.CRREG0
+#define LVDL0 OSCTUNE_bits.LVDL0
+#define WDA0 OSCTUNE_bits.WDA0
+#define WPUDA0 OSCTUNE_bits.WPUDA0
+#define RA0 OSCTUNE_bits.RA0
+#define GP0 OSCTUNE_bits.GP0
+#define TUN1 OSCTUNE_bits.TUN1
+#define IOCA1 OSCTUNE_bits.IOCA1
+#define WR OSCTUNE_bits.WR
+#define VR1 OSCTUNE_bits.VR1
+#define CRREG1 OSCTUNE_bits.CRREG1
+#define LVDL1 OSCTUNE_bits.LVDL1
+#define WDA1 OSCTUNE_bits.WDA1
+#define WPUDA1 OSCTUNE_bits.WPUDA1
+#define RA1 OSCTUNE_bits.RA1
+#define GP1 OSCTUNE_bits.GP1
+#define TUN2 OSCTUNE_bits.TUN2
+#define IOCA2 OSCTUNE_bits.IOCA2
+#define WREN OSCTUNE_bits.WREN
+#define VR2 OSCTUNE_bits.VR2
+#define LVDL2 OSCTUNE_bits.LVDL2
+#define WDA2 OSCTUNE_bits.WDA2
+#define WPUDA2 OSCTUNE_bits.WPUDA2
+#define RA2 OSCTUNE_bits.RA2
+#define GP2 OSCTUNE_bits.GP2
+#define TUN3 OSCTUNE_bits.TUN3
+#define IOCA3 OSCTUNE_bits.IOCA3
+#define WRERR OSCTUNE_bits.WRERR
+#define VR3 OSCTUNE_bits.VR3
+#define RA3 OSCTUNE_bits.RA3
+#define GP3 OSCTUNE_bits.GP3
+#define TUN4 OSCTUNE_bits.TUN4
+#define IOCA4 OSCTUNE_bits.IOCA4
+#define PLVDEN OSCTUNE_bits.PLVDEN
+#define WDA4 OSCTUNE_bits.WDA4
+#define WPUDA4 OSCTUNE_bits.WPUDA4
+#define RA4 OSCTUNE_bits.RA4
+#define GP4 OSCTUNE_bits.GP4
+#define IOCA5 OSCTUNE_bits.IOCA5
+#define VRR OSCTUNE_bits.VRR
+#define IRVST OSCTUNE_bits.IRVST
+#define WDA5 OSCTUNE_bits.WDA5
+#define WPUDA5 OSCTUNE_bits.WPUDA5
+#define RA5 OSCTUNE_bits.RA5
+#define GP5 OSCTUNE_bits.GP5
+#define ENC_DEC OSCTUNE_bits.ENC_DEC
+#define VREN OSCTUNE_bits.VREN
+#define GO OSCTUNE_bits.GO
+
+// ----- PCON bits --------------------
+typedef union {
+ struct {
+ unsigned char NOT_BOD:1;
+ unsigned char NOT_POR:1;
+ unsigned char :1;
+ unsigned char NOT_WUR:1;
+ unsigned char SBODEN:1;
+ unsigned char ULPWUE:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __PCON_bits_t;
+extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
+
+#define NOT_BOD PCON_bits.NOT_BOD
+#define NOT_POR PCON_bits.NOT_POR
+#define NOT_WUR PCON_bits.NOT_WUR
+#define SBODEN PCON_bits.SBODEN
+#define ULPWUE PCON_bits.ULPWUE
+
+// ----- PIE1 bits --------------------
+typedef union {
+ struct {
+ unsigned char TMR1IE:1;
+ unsigned char :1;
+ unsigned char OSFIE:1;
+ unsigned char C1IE:1;
+ unsigned char :1;
+ unsigned char CRIE:1;
+ unsigned char LVDIE:1;
+ unsigned char EEIE:1;
+ };
+} __PIE1_bits_t;
+extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
+
+#define TMR1IE PIE1_bits.TMR1IE
+#define OSFIE PIE1_bits.OSFIE
+#define C1IE PIE1_bits.C1IE
+#define CRIE PIE1_bits.CRIE
+#define LVDIE PIE1_bits.LVDIE
+#define EEIE PIE1_bits.EEIE
+
+// ----- PIR1 bits --------------------
+typedef union {
+ struct {
+ unsigned char TMR1IF:1;
+ unsigned char :1;
+ unsigned char OSFIF:1;
+ unsigned char C1IF:1;
+ unsigned char :1;
+ unsigned char CRIF:1;
+ unsigned char LVDIF:1;
+ unsigned char EEIF:1;
+ };
+} __PIR1_bits_t;
+extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
+
+#define TMR1IF PIR1_bits.TMR1IF
+#define OSFIF PIR1_bits.OSFIF
+#define C1IF PIR1_bits.C1IF
+#define CRIF PIR1_bits.CRIF
+#define LVDIF PIR1_bits.LVDIF
+#define EEIF PIR1_bits.EEIF
+
+// ----- STATUS bits --------------------
+typedef union {
+ struct {
+ unsigned char C:1;
+ unsigned char DC:1;
+ unsigned char Z:1;
+ unsigned char NOT_PD:1;
+ unsigned char NOT_TO:1;
+ unsigned char RP0:1;
+ unsigned char RP1:1;
+ unsigned char IRP:1;
+ };
+} __STATUS_bits_t;
+extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
+
+#define C STATUS_bits.C
+#define DC STATUS_bits.DC
+#define Z STATUS_bits.Z
+#define NOT_PD STATUS_bits.NOT_PD
+#define NOT_TO STATUS_bits.NOT_TO
+#define RP0 STATUS_bits.RP0
+#define RP1 STATUS_bits.RP1
+#define IRP STATUS_bits.IRP
+
+// ----- T1CON bits --------------------
+typedef union {
+ struct {
+ unsigned char TMR1ON:1;
+ unsigned char TMR1CS:1;
+ unsigned char NOT_T1SYNC:1;
+ unsigned char T1OSCEN:1;
+ unsigned char T1CKPS0:1;
+ unsigned char T1CKPS1:1;
+ unsigned char TMR1GE:1;
+ unsigned char T1GINV:1;
+ };
+} __T1CON_bits_t;
+extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
+
+#define TMR1ON T1CON_bits.TMR1ON
+#define TMR1CS T1CON_bits.TMR1CS
+#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
+#define T1OSCEN T1CON_bits.T1OSCEN
+#define T1CKPS0 T1CON_bits.T1CKPS0
+#define T1CKPS1 T1CON_bits.T1CKPS1
+#define TMR1GE T1CON_bits.TMR1GE
+#define T1GINV T1CON_bits.T1GINV
+
+// ----- WDTCON bits --------------------
+typedef union {
+ struct {
+ unsigned char SWDTEN:1;
+ unsigned char WDTPS0:1;
+ unsigned char WDTPS1:1;
+ unsigned char WDTPS2:1;
+ unsigned char WDTPS3:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __WDTCON_bits_t;
+extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
+
+#define SWDTEN WDTCON_bits.SWDTEN
+#define WDTPS0 WDTCON_bits.WDTPS0
+#define WDTPS1 WDTCON_bits.WDTPS1
+#define WDTPS2 WDTCON_bits.WDTPS2
+#define WDTPS3 WDTCON_bits.WDTPS3
+
+#endif
--- /dev/null
+//
+// Register Declarations for Microchip 12F675 Processor
+//
+//
+// This header file was automatically generated by:
+//
+// inc2h.pl V1.7
+//
+// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
+//
+// SDCC is licensed under the GNU Public license (GPL) v2. Note that
+// this license covers the code to the compiler and other executables,
+// but explicitly does not cover any code or objects generated by sdcc.
+// We have not yet decided on a license for the run time libraries, but
+// it will not put any requirements on code linked against it. See:
+//
+// http://www.gnu.org/copyleft/gpl/html
+//
+// See http://sdcc.sourceforge.net/ for the latest information on sdcc.
+//
+//
+#ifndef P12F675_H
+#define P12F675_H
+
+//
+// Register addresses.
+//
+#define INDF_ADDR 0x0000
+#define TMR0_ADDR 0x0001
+#define PCL_ADDR 0x0002
+#define STATUS_ADDR 0x0003
+#define FSR_ADDR 0x0004
+#define GPIO_ADDR 0x0005
+#define PCLATH_ADDR 0x000A
+#define INTCON_ADDR 0x000B
+#define PIR1_ADDR 0x000C
+#define TMR1L_ADDR 0x000E
+#define TMR1H_ADDR 0x000F
+#define T1CON_ADDR 0x0010
+#define CMCON_ADDR 0x0019
+#define ADRESH_ADDR 0x001E
+#define ADCON0_ADDR 0x001F
+#define OPTION_REG_ADDR 0x0081
+#define TRISIO_ADDR 0x0085
+#define PIE1_ADDR 0x008C
+#define PCON_ADDR 0x008E
+#define OSCCAL_ADDR 0x0090
+#define WPU_ADDR 0x0095
+#define IOC_ADDR 0x0096
+#define IOCB_ADDR 0x0096
+#define VRCON_ADDR 0x0099
+#define EEDATA_ADDR 0x009A
+#define EEDAT_ADDR 0x009A
+#define EEADR_ADDR 0x009B
+#define EECON1_ADDR 0x009C
+#define EECON2_ADDR 0x009D
+#define ADRESL_ADDR 0x009E
+#define ANSEL_ADDR 0x009F
+
+//
+// Memory organization.
+//
+
+#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
+#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
+#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
+#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
+#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
+#pragma memmap GPIO_ADDR GPIO_ADDR SFR 0x000 // GPIO
+#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
+#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
+#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
+#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
+#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
+#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
+#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON
+#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
+#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
+#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
+#pragma memmap TRISIO_ADDR TRISIO_ADDR SFR 0x000 // TRISIO
+#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
+#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
+#pragma memmap OSCCAL_ADDR OSCCAL_ADDR SFR 0x000 // OSCCAL
+#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU
+#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC
+#pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB
+#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
+#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
+#pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT
+#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
+#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
+#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
+#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
+#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL
+
+
+// LIST
+// P12F675.INC Standard Header File, Version 1.04 Microchip Technology, Inc.
+// NOLIST
+
+// This header file defines configurations, registers, and other useful bits of
+// information for the PIC12F675 microcontroller. These names are taken to match
+// the data sheets as closely as possible.
+
+// Note that the processor must be selected before this file is
+// included. The processor may be selected the following ways:
+
+// 1. Command line switch:
+// C:\ MPASM MYFILE.ASM /PIC12F675
+// 2. LIST directive in the source file
+// LIST P=PIC12F675
+// 3. Processor Type entry in the MPASM full-screen interface
+
+//==========================================================================
+//
+// Revision History
+//
+//==========================================================================
+//1.04 07/01/02 Updated configuration bit names
+//1.03 05/10/02 Corrected ADCON0 register, added IOC register
+//1.02 02/28/02 Updated per datasheet
+//1.01 01/31/02 Updated per datasheet
+//1.00 08/24/01 Original
+
+//==========================================================================
+//
+// Verify Processor
+//
+//==========================================================================
+
+// IFNDEF __12F675
+// MESSG "Processor-header file mismatch. Verify selected processor."
+// ENDIF
+
+//==========================================================================
+//
+// Register Definitions
+//
+//==========================================================================
+
+#define W 0x0000
+#define F 0x0001
+
+//----- Register Files------------------------------------------------------
+
+extern __data __at (INDF_ADDR) volatile char INDF;
+extern __sfr __at (TMR0_ADDR) TMR0;
+extern __data __at (PCL_ADDR) volatile char PCL;
+extern __sfr __at (STATUS_ADDR) STATUS;
+extern __sfr __at (FSR_ADDR) FSR;
+extern __sfr __at (GPIO_ADDR) GPIO;
+
+extern __sfr __at (PCLATH_ADDR) PCLATH;
+extern __sfr __at (INTCON_ADDR) INTCON;
+extern __sfr __at (PIR1_ADDR) PIR1;
+
+extern __sfr __at (TMR1L_ADDR) TMR1L;
+extern __sfr __at (TMR1H_ADDR) TMR1H;
+extern __sfr __at (T1CON_ADDR) T1CON;
+
+extern __sfr __at (CMCON_ADDR) CMCON;
+
+extern __sfr __at (ADRESH_ADDR) ADRESH;
+extern __sfr __at (ADCON0_ADDR) ADCON0;
+
+
+extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
+
+extern __sfr __at (TRISIO_ADDR) TRISIO;
+
+extern __sfr __at (PIE1_ADDR) PIE1;
+
+extern __sfr __at (PCON_ADDR) PCON;
+
+extern __sfr __at (OSCCAL_ADDR) OSCCAL;
+
+extern __sfr __at (WPU_ADDR) WPU;
+extern __sfr __at (IOC_ADDR) IOC;
+extern __sfr __at (IOCB_ADDR) IOCB;
+
+extern __sfr __at (VRCON_ADDR) VRCON;
+extern __sfr __at (EEDATA_ADDR) EEDATA;
+extern __sfr __at (EEDAT_ADDR) EEDAT;
+extern __sfr __at (EEADR_ADDR) EEADR;
+extern __sfr __at (EECON1_ADDR) EECON1;
+extern __sfr __at (EECON2_ADDR) EECON2;
+extern __sfr __at (ADRESL_ADDR) ADRESL;
+extern __sfr __at (ANSEL_ADDR) ANSEL;
+
+
+//----- STATUS Bits --------------------------------------------------------
+
+
+//----- GPIO Bits --------------------------------------------------------
+
+
+//----- INTCON Bits --------------------------------------------------------
+
+
+//----- PIR1 Bits ----------------------------------------------------------
+
+
+//----- T1CON Bits ---------------------------------------------------------
+
+
+//----- CMCON Bits --------------------------------------------------------
+
+
+//----- ADCON0 Bits --------------------------------------------------------
+
+
+//----- OPTION Bits --------------------------------------------------------
+
+
+//----- PIE1 Bits ----------------------------------------------------------
+
+
+//----- PCON Bits ----------------------------------------------------------
+
+
+//----- OSCCAL Bits --------------------------------------------------------
+
+
+//----- IOCB Bits --------------------------------------------------------
+
+
+//----- IOC Bits --------------------------------------------------------
+
+
+//----- VRCON Bits ---------------------------------------------------------
+
+
+//----- EECON1 -------------------------------------------------------------
+
+
+//----- ANSEL --------------------------------------------------------------
+
+
+//==========================================================================
+//
+// RAM Definition
+//
+//==========================================================================
+
+// __MAXRAM H'FF'
+// __BADRAM H'06'-H'09', H'0D', H'11'-H'18', H'1A'-H'1D', H'60'-H'7F'
+// __BADRAM H'86'-H'89', H'8D', H'8F', H'91'-H'94', H'97'-H'98', H'E0'-H'FF'
+
+//==========================================================================
+//
+// Configuration Bits
+//
+//==========================================================================
+
+#define _CPD_ON 0x3EFF
+#define _CPD_OFF 0x3FFF
+#define _CP_ON 0x3F7F
+#define _CP_OFF 0x3FFF
+#define _BODEN_ON 0x3FFF
+#define _BODEN_OFF 0x3FBF
+#define _MCLRE_ON 0x3FFF
+#define _MCLRE_OFF 0x3FDF
+#define _PWRTE_OFF 0x3FFF
+#define _PWRTE_ON 0x3FEF
+#define _WDT_ON 0x3FFF
+#define _WDT_OFF 0x3FF7
+#define _LP_OSC 0x3FF8
+#define _XT_OSC 0x3FF9
+#define _HS_OSC 0x3FFA
+#define _EC_OSC 0x3FFB
+#define _INTRC_OSC_NOCLKOUT 0x3FFC
+#define _INTRC_OSC_CLKOUT 0x3FFD
+#define _EXTRC_OSC_NOCLKOUT 0x3FFE
+#define _EXTRC_OSC_CLKOUT 0x3FFF
+
+// LIST
+
+// ----- ADCON0 bits --------------------
+typedef union {
+ struct {
+ unsigned char ADON:1;
+ unsigned char GO:1;
+ unsigned char CHS0:1;
+ unsigned char CHS1:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char VCFG:1;
+ unsigned char ADFM:1;
+ };
+ struct {
+ unsigned char :1;
+ unsigned char NOT_DONE:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+ struct {
+ unsigned char :1;
+ unsigned char GO_DONE:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __ADCON0_bits_t;
+extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
+
+#define ADON ADCON0_bits.ADON
+#define GO ADCON0_bits.GO
+#define NOT_DONE ADCON0_bits.NOT_DONE
+#define GO_DONE ADCON0_bits.GO_DONE
+#define CHS0 ADCON0_bits.CHS0
+#define CHS1 ADCON0_bits.CHS1
+#define VCFG ADCON0_bits.VCFG
+#define ADFM ADCON0_bits.ADFM
+
+// ----- CMCON bits --------------------
+typedef union {
+ struct {
+ unsigned char CM0:1;
+ unsigned char CM1:1;
+ unsigned char CM2:1;
+ unsigned char CIS:1;
+ unsigned char CINV:1;
+ unsigned char :1;
+ unsigned char COUT:1;
+ unsigned char :1;
+ };
+} __CMCON_bits_t;
+extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
+
+#define CM0 CMCON_bits.CM0
+#define CM1 CMCON_bits.CM1
+#define CM2 CMCON_bits.CM2
+#define CIS CMCON_bits.CIS
+#define CINV CMCON_bits.CINV
+#define COUT CMCON_bits.COUT
+
+// ----- GPIO bits --------------------
+typedef union {
+ struct {
+ unsigned char GP0:1;
+ unsigned char GP1:1;
+ unsigned char GP2:1;
+ unsigned char GP3:1;
+ unsigned char GP4:1;
+ unsigned char GP5:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+ struct {
+ unsigned char GPIO0:1;
+ unsigned char GPIO1:1;
+ unsigned char GPIO2:1;
+ unsigned char GPIO3:1;
+ unsigned char GPIO4:1;
+ unsigned char GPIO5:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __GPIO_bits_t;
+extern volatile __GPIO_bits_t __at(GPIO_ADDR) GPIO_bits;
+
+#define GP0 GPIO_bits.GP0
+#define GPIO0 GPIO_bits.GPIO0
+#define GP1 GPIO_bits.GP1
+#define GPIO1 GPIO_bits.GPIO1
+#define GP2 GPIO_bits.GP2
+#define GPIO2 GPIO_bits.GPIO2
+#define GP3 GPIO_bits.GP3
+#define GPIO3 GPIO_bits.GPIO3
+#define GP4 GPIO_bits.GP4
+#define GPIO4 GPIO_bits.GPIO4
+#define GP5 GPIO_bits.GP5
+#define GPIO5 GPIO_bits.GPIO5
+
+// ----- INTCON bits --------------------
+typedef union {
+ struct {
+ unsigned char GPIF:1;
+ unsigned char INTF:1;
+ unsigned char T0IF:1;
+ unsigned char GPIE:1;
+ unsigned char INTE:1;
+ unsigned char T0IE:1;
+ unsigned char PEIE:1;
+ unsigned char GIE:1;
+ };
+} __INTCON_bits_t;
+extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
+
+#define GPIF INTCON_bits.GPIF
+#define INTF INTCON_bits.INTF
+#define T0IF INTCON_bits.T0IF
+#define GPIE INTCON_bits.GPIE
+#define INTE INTCON_bits.INTE
+#define T0IE INTCON_bits.T0IE
+#define PEIE INTCON_bits.PEIE
+#define GIE INTCON_bits.GIE
+
+// ----- IOC bits --------------------
+typedef union {
+ struct {
+ unsigned char IOC0:1;
+ unsigned char IOC1:1;
+ unsigned char IOC2:1;
+ unsigned char IOC3:1;
+ unsigned char IOC4:1;
+ unsigned char IOC5:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __IOC_bits_t;
+extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
+
+#define IOC0 IOC_bits.IOC0
+#define IOC1 IOC_bits.IOC1
+#define IOC2 IOC_bits.IOC2
+#define IOC3 IOC_bits.IOC3
+#define IOC4 IOC_bits.IOC4
+#define IOC5 IOC_bits.IOC5
+
+// ----- IOCB bits --------------------
+typedef union {
+ struct {
+ unsigned char IOCB0:1;
+ unsigned char IOCB1:1;
+ unsigned char IOCB2:1;
+ unsigned char IOCB3:1;
+ unsigned char IOCB4:1;
+ unsigned char IOCB5:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __IOCB_bits_t;
+extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
+
+#define IOCB0 IOCB_bits.IOCB0
+#define IOCB1 IOCB_bits.IOCB1
+#define IOCB2 IOCB_bits.IOCB2
+#define IOCB3 IOCB_bits.IOCB3
+#define IOCB4 IOCB_bits.IOCB4
+#define IOCB5 IOCB_bits.IOCB5
+
+// ----- OPTION_REG bits --------------------
+typedef union {
+ struct {
+ unsigned char PS0:1;
+ unsigned char PS1:1;
+ unsigned char PS2:1;
+ unsigned char PSA:1;
+ unsigned char T0SE:1;
+ unsigned char T0CS:1;
+ unsigned char INTEDG:1;
+ unsigned char NOT_GPPU:1;
+ };
+} __OPTION_REG_bits_t;
+extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
+
+#define PS0 OPTION_REG_bits.PS0
+#define PS1 OPTION_REG_bits.PS1
+#define PS2 OPTION_REG_bits.PS2
+#define PSA OPTION_REG_bits.PSA
+#define T0SE OPTION_REG_bits.T0SE
+#define T0CS OPTION_REG_bits.T0CS
+#define INTEDG OPTION_REG_bits.INTEDG
+#define NOT_GPPU OPTION_REG_bits.NOT_GPPU
+
+// ----- OSCCAL bits --------------------
+typedef union {
+ struct {
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char CAL0:1;
+ unsigned char CAL1:1;
+ unsigned char CAL2:1;
+ unsigned char CAL3:1;
+ unsigned char CAL4:1;
+ unsigned char CAL5:1;
+ };
+} __OSCCAL_bits_t;
+extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits;
+
+#define CAL0 OSCCAL_bits.CAL0
+#define CAL1 OSCCAL_bits.CAL1
+#define CAL2 OSCCAL_bits.CAL2
+#define CAL3 OSCCAL_bits.CAL3
+#define CAL4 OSCCAL_bits.CAL4
+#define CAL5 OSCCAL_bits.CAL5
+
+// ----- PCON bits --------------------
+typedef union {
+ struct {
+ unsigned char NOT_BOD:1;
+ unsigned char NOT_POR:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __PCON_bits_t;
+extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
+
+#define NOT_BOD PCON_bits.NOT_BOD
+#define NOT_POR PCON_bits.NOT_POR
+
+// ----- PIE1 bits --------------------
+typedef union {
+ struct {
+ unsigned char T1IE:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char CMIE:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char ADIE:1;
+ unsigned char EEIE:1;
+ };
+ struct {
+ unsigned char TMR1IE:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __PIE1_bits_t;
+extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
+
+#define T1IE PIE1_bits.T1IE
+#define TMR1IE PIE1_bits.TMR1IE
+#define CMIE PIE1_bits.CMIE
+#define ADIE PIE1_bits.ADIE
+#define EEIE PIE1_bits.EEIE
+
+// ----- PIR1 bits --------------------
+typedef union {
+ struct {
+ unsigned char T1IF:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char CMIF:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char ADIF:1;
+ unsigned char EEIF:1;
+ };
+ struct {
+ unsigned char TMR1IF:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __PIR1_bits_t;
+extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
+
+#define T1IF PIR1_bits.T1IF
+#define TMR1IF PIR1_bits.TMR1IF
+#define CMIF PIR1_bits.CMIF
+#define ADIF PIR1_bits.ADIF
+#define EEIF PIR1_bits.EEIF
+
+// ----- STATUS bits --------------------
+typedef union {
+ struct {
+ unsigned char C:1;
+ unsigned char DC:1;
+ unsigned char Z:1;
+ unsigned char NOT_PD:1;
+ unsigned char NOT_TO:1;
+ unsigned char RP0:1;
+ unsigned char RP1:1;
+ unsigned char IRP:1;
+ };
+} __STATUS_bits_t;
+extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
+
+#define C STATUS_bits.C
+#define DC STATUS_bits.DC
+#define Z STATUS_bits.Z
+#define NOT_PD STATUS_bits.NOT_PD
+#define NOT_TO STATUS_bits.NOT_TO
+#define RP0 STATUS_bits.RP0
+#define RP1 STATUS_bits.RP1
+#define IRP STATUS_bits.IRP
+
+// ----- T1CON bits --------------------
+typedef union {
+ struct {
+ unsigned char TMR1ON:1;
+ unsigned char TMR1CS:1;
+ unsigned char NOT_T1SYNC:1;
+ unsigned char T1OSCEN:1;
+ unsigned char T1CKPS0:1;
+ unsigned char T1CKPS1:1;
+ unsigned char TMR1GE:1;
+ unsigned char :1;
+ };
+} __T1CON_bits_t;
+extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
+
+#define TMR1ON T1CON_bits.TMR1ON
+#define TMR1CS T1CON_bits.TMR1CS
+#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
+#define T1OSCEN T1CON_bits.T1OSCEN
+#define T1CKPS0 T1CON_bits.T1CKPS0
+#define T1CKPS1 T1CON_bits.T1CKPS1
+#define TMR1GE T1CON_bits.TMR1GE
+
+// ----- VRCON bits --------------------
+typedef union {
+ struct {
+ unsigned char VR0:1;
+ unsigned char VR1:1;
+ unsigned char VR2:1;
+ unsigned char VR3:1;
+ unsigned char ADCS0:1;
+ unsigned char VRR:1;
+ unsigned char ADCS2:1;
+ unsigned char VREN:1;
+ };
+ struct {
+ unsigned char RD:1;
+ unsigned char WR:1;
+ unsigned char WREN:1;
+ unsigned char WRERR:1;
+ unsigned char :1;
+ unsigned char ADCS1:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+ struct {
+ unsigned char ANS0:1;
+ unsigned char ANS1:1;
+ unsigned char ANS2:1;
+ unsigned char ANS3:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __VRCON_bits_t;
+extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
+
+#define VR0 VRCON_bits.VR0
+#define RD VRCON_bits.RD
+#define ANS0 VRCON_bits.ANS0
+#define VR1 VRCON_bits.VR1
+#define WR VRCON_bits.WR
+#define ANS1 VRCON_bits.ANS1
+#define VR2 VRCON_bits.VR2
+#define WREN VRCON_bits.WREN
+#define ANS2 VRCON_bits.ANS2
+#define VR3 VRCON_bits.VR3
+#define WRERR VRCON_bits.WRERR
+#define ANS3 VRCON_bits.ANS3
+#define ADCS0 VRCON_bits.ADCS0
+#define VRR VRCON_bits.VRR
+#define ADCS1 VRCON_bits.ADCS1
+#define ADCS2 VRCON_bits.ADCS2
+#define VREN VRCON_bits.VREN
+
+#endif
--- /dev/null
+//
+// Register Declarations for Microchip 12F683 Processor
+//
+//
+// This header file was automatically generated by:
+//
+// inc2h.pl V1.7
+//
+// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
+//
+// SDCC is licensed under the GNU Public license (GPL) v2. Note that
+// this license covers the code to the compiler and other executables,
+// but explicitly does not cover any code or objects generated by sdcc.
+// We have not yet decided on a license for the run time libraries, but
+// it will not put any requirements on code linked against it. See:
+//
+// http://www.gnu.org/copyleft/gpl/html
+//
+// See http://sdcc.sourceforge.net/ for the latest information on sdcc.
+//
+//
+#ifndef P12F683_H
+#define P12F683_H
+
+//
+// Register addresses.
+//
+#define INDF_ADDR 0x0000
+#define TMR0_ADDR 0x0001
+#define PCL_ADDR 0x0002
+#define STATUS_ADDR 0x0003
+#define FSR_ADDR 0x0004
+#define GPIO_ADDR 0x0005
+#define PCLATH_ADDR 0x000A
+#define INTCON_ADDR 0x000B
+#define PIR1_ADDR 0x000C
+#define TMR1L_ADDR 0x000E
+#define TMR1H_ADDR 0x000F
+#define T1CON_ADDR 0x0010
+#define TMR2_ADDR 0x0011
+#define T2CON_ADDR 0x0012
+#define CCPR1L_ADDR 0x0013
+#define CCPR1H_ADDR 0x0014
+#define CCP1CON_ADDR 0x0015
+#define WDTCON_ADDR 0x0018
+#define CMCON0_ADDR 0x0019
+#define CMCON1_ADDR 0x001A
+#define ADRESH_ADDR 0x001E
+#define ADCON0_ADDR 0x001F
+#define OPTION_REG_ADDR 0x0081
+#define TRISIO_ADDR 0x0085
+#define PIE1_ADDR 0x008C
+#define PCON_ADDR 0x008E
+#define OSCCON_ADDR 0x008F
+#define OSCTUNE_ADDR 0x0090
+#define PR2_ADDR 0x0092
+#define WPU_ADDR 0x0095
+#define WPUA_ADDR 0x0095
+#define IOC_ADDR 0x0096
+#define IOCA_ADDR 0x0096
+#define VRCON_ADDR 0x0099
+#define EEDATA_ADDR 0x009A
+#define EEDAT_ADDR 0x009A
+#define EEADR_ADDR 0x009B
+#define EECON1_ADDR 0x009C
+#define EECON2_ADDR 0x009D
+#define ADRESL_ADDR 0x009E
+#define ANSEL_ADDR 0x009F
+
+//
+// Memory organization.
+//
+
+#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
+#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
+#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
+#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
+#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
+#pragma memmap GPIO_ADDR GPIO_ADDR SFR 0x000 // GPIO
+#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
+#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
+#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
+#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
+#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
+#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
+#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
+#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
+#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
+#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
+#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
+#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
+#pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0
+#pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1
+#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
+#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
+#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
+#pragma memmap TRISIO_ADDR TRISIO_ADDR SFR 0x000 // TRISIO
+#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
+#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
+#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
+#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
+#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
+#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU
+#pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA
+#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC
+#pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA
+#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
+#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
+#pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT
+#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
+#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
+#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
+#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
+#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL
+
+
+// LIST
+// P12F683.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
+// NOLIST
+
+// This header file defines configurations, registers, and other useful bits of
+// information for the PIC12F683 microcontroller. These names are taken to match
+// the data sheets as closely as possible.
+
+// Note that the processor must be selected before this file is
+// included. The processor may be selected the following ways:
+
+// 1. Command line switch:
+// C:\ MPASM MYFILE.ASM /PIC16F684
+// 2. LIST directive in the source file
+// LIST P=PIC12F683
+// 3. Processor Type entry in the MPASM full-screen interface
+
+//==========================================================================
+//
+// Revision History
+//
+//==========================================================================
+//1.00 12/09/03 Original
+
+//==========================================================================
+//
+// Verify Processor
+//
+//==========================================================================
+
+// IFNDEF __12F683
+// MESSG "Processor-header file mismatch. Verify selected processor."
+// ENDIF
+
+//==========================================================================
+//
+// Register Definitions
+//
+//==========================================================================
+
+#define W 0x0000
+#define F 0x0001
+
+//----- Register Files------------------------------------------------------
+
+extern __data __at (INDF_ADDR) volatile char INDF;
+extern __sfr __at (TMR0_ADDR) TMR0;
+extern __data __at (PCL_ADDR) volatile char PCL;
+extern __sfr __at (STATUS_ADDR) STATUS;
+extern __sfr __at (FSR_ADDR) FSR;
+extern __sfr __at (GPIO_ADDR) GPIO;
+
+extern __sfr __at (PCLATH_ADDR) PCLATH;
+extern __sfr __at (INTCON_ADDR) INTCON;
+extern __sfr __at (PIR1_ADDR) PIR1;
+
+extern __sfr __at (TMR1L_ADDR) TMR1L;
+extern __sfr __at (TMR1H_ADDR) TMR1H;
+extern __sfr __at (T1CON_ADDR) T1CON;
+extern __sfr __at (TMR2_ADDR) TMR2;
+extern __sfr __at (T2CON_ADDR) T2CON;
+extern __sfr __at (CCPR1L_ADDR) CCPR1L;
+extern __sfr __at (CCPR1H_ADDR) CCPR1H;
+extern __sfr __at (CCP1CON_ADDR) CCP1CON;
+
+extern __sfr __at (WDTCON_ADDR) WDTCON;
+extern __sfr __at (CMCON0_ADDR) CMCON0;
+extern __sfr __at (CMCON1_ADDR) CMCON1;
+
+extern __sfr __at (ADRESH_ADDR) ADRESH;
+extern __sfr __at (ADCON0_ADDR) ADCON0;
+
+extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
+
+extern __sfr __at (TRISIO_ADDR) TRISIO;
+
+extern __sfr __at (PIE1_ADDR) PIE1;
+
+extern __sfr __at (PCON_ADDR) PCON;
+extern __sfr __at (OSCCON_ADDR) OSCCON;
+extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
+
+extern __sfr __at (PR2_ADDR) PR2;
+
+extern __sfr __at (WPU_ADDR) WPU;
+extern __sfr __at (WPUA_ADDR) WPUA;
+extern __sfr __at (IOC_ADDR) IOC;
+extern __sfr __at (IOCA_ADDR) IOCA;
+
+extern __sfr __at (VRCON_ADDR) VRCON;
+extern __sfr __at (EEDATA_ADDR) EEDATA;
+extern __sfr __at (EEDAT_ADDR) EEDAT;
+extern __sfr __at (EEADR_ADDR) EEADR;
+extern __sfr __at (EECON1_ADDR) EECON1;
+extern __sfr __at (EECON2_ADDR) EECON2;
+extern __sfr __at (ADRESL_ADDR) ADRESL;
+extern __sfr __at (ANSEL_ADDR) ANSEL;
+
+
+//----- STATUS Bits --------------------------------------------------------
+
+
+//----- INTCON Bits --------------------------------------------------------
+
+
+//----- PIR1 Bits ----------------------------------------------------------
+
+
+//----- T1CON Bits ---------------------------------------------------------
+
+
+//----- T2CON Bits ---------------------------------------------------------
+
+
+//----- CCP1CON Bits -------------------------------------------------------
+
+
+//----- WDTCON Bits --------------------------------------------------------
+
+
+//----- CMCON0 Bits -------------------------------------------------------
+
+
+//----- CMCON1 Bits -------------------------------------------------------
+
+
+//----- ADCON0 Bits --------------------------------------------------------
+
+
+//----- OPTION Bits --------------------------------------------------------
+
+
+
+//----- PIE1 Bits ----------------------------------------------------------
+
+
+//----- PCON Bits ----------------------------------------------------------
+
+
+//----- OSCCON Bits --------------------------------------------------------
+
+
+//----- OSCTUNE Bits -------------------------------------------------------
+
+
+
+//----- IOC --------------------------------------------------------------
+
+
+//----- IOCA --------------------------------------------------------------
+
+
+//----- VRCON Bits ---------------------------------------------------------
+
+
+//----- EECON1 -------------------------------------------------------------
+
+
+//----- ANSEL --------------------------------------------------------------
+
+
+//==========================================================================
+//
+// RAM Definition
+//
+//==========================================================================
+
+// __MAXRAM H'FF'
+// __BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D'
+// __BADRAM H'86', H'88'-H'89', H'8D', H'93'-H'94', H'97'-H'98', H'C0'-H'EF'
+
+//==========================================================================
+//
+// Configuration Bits
+//
+//==========================================================================
+
+#define _FCMEN_ON 0x3FFF
+#define _FCMEN_OFF 0x37FF
+#define _IESO_ON 0x3FFF
+#define _IESO_OFF 0x3BFF
+#define _BOD_ON 0x3FFF
+#define _BOD_NSLEEP 0x3EFF
+#define _BOD_SBODEN 0x3DFF
+#define _BOD_OFF 0x3CFF
+#define _CPD_ON 0x3F7F
+#define _CPD_OFF 0x3FFF
+#define _CP_ON 0x3FBF
+#define _CP_OFF 0x3FFF
+#define _MCLRE_ON 0x3FFF
+#define _MCLRE_OFF 0x3FDF
+#define _PWRTE_OFF 0x3FFF
+#define _PWRTE_ON 0x3FEF
+#define _WDT_ON 0x3FFF
+#define _WDT_OFF 0x3FF7
+#define _LP_OSC 0x3FF8
+#define _XT_OSC 0x3FF9
+#define _HS_OSC 0x3FFA
+#define _EC_OSC 0x3FFB
+#define _INTRC_OSC_NOCLKOUT 0x3FFC
+#define _INTOSCIO 0x3FFC
+#define _INTRC_OSC_CLKOUT 0x3FFD
+#define _INTOSC 0x3FFD
+#define _EXTRC_OSC_NOCLKOUT 0x3FFE
+#define _EXTRCIO 0x3FFE
+#define _EXTRC_OSC_CLKOUT 0x3FFF
+#define _EXTRC 0x3FFF
+
+// LIST
+
+// ----- ADCON0 bits --------------------
+typedef union {
+ struct {
+ unsigned char ADON:1;
+ unsigned char GO:1;
+ unsigned char CHS0:1;
+ unsigned char CHS1:1;
+ unsigned char CHS2:1;
+ unsigned char :1;
+ unsigned char VCFG:1;
+ unsigned char ADFM:1;
+ };
+ struct {
+ unsigned char :1;
+ unsigned char NOT_DONE:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+ struct {
+ unsigned char :1;
+ unsigned char GO_DONE:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __ADCON0_bits_t;
+extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
+
+#define ADON ADCON0_bits.ADON
+#define GO ADCON0_bits.GO
+#define NOT_DONE ADCON0_bits.NOT_DONE
+#define GO_DONE ADCON0_bits.GO_DONE
+#define CHS0 ADCON0_bits.CHS0
+#define CHS1 ADCON0_bits.CHS1
+#define CHS2 ADCON0_bits.CHS2
+#define VCFG ADCON0_bits.VCFG
+#define ADFM ADCON0_bits.ADFM
+
+// ----- CCP1CON bits --------------------
+typedef union {
+ struct {
+ unsigned char CCP1M0:1;
+ unsigned char CCP1M1:1;
+ unsigned char CCP1M2:1;
+ unsigned char CCP1M3:1;
+ unsigned char DC1B0:1;
+ unsigned char DC1B1:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __CCP1CON_bits_t;
+extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
+
+#define CCP1M0 CCP1CON_bits.CCP1M0
+#define CCP1M1 CCP1CON_bits.CCP1M1
+#define CCP1M2 CCP1CON_bits.CCP1M2
+#define CCP1M3 CCP1CON_bits.CCP1M3
+#define DC1B0 CCP1CON_bits.DC1B0
+#define DC1B1 CCP1CON_bits.DC1B1
+
+// ----- CMCON0 bits --------------------
+typedef union {
+ struct {
+ unsigned char CM0:1;
+ unsigned char CM1:1;
+ unsigned char CM2:1;
+ unsigned char CIS:1;
+ unsigned char CINV:1;
+ unsigned char :1;
+ unsigned char COUT:1;
+ unsigned char :1;
+ };
+} __CMCON0_bits_t;
+extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
+
+#define CM0 CMCON0_bits.CM0
+#define CM1 CMCON0_bits.CM1
+#define CM2 CMCON0_bits.CM2
+#define CIS CMCON0_bits.CIS
+#define CINV CMCON0_bits.CINV
+#define COUT CMCON0_bits.COUT
+
+// ----- CMCON1 bits --------------------
+typedef union {
+ struct {
+ unsigned char CMSYNC:1;
+ unsigned char T1GSS:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __CMCON1_bits_t;
+extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
+
+#define CMSYNC CMCON1_bits.CMSYNC
+#define T1GSS CMCON1_bits.T1GSS
+
+// ----- INTCON bits --------------------
+typedef union {
+ struct {
+ unsigned char GPIF:1;
+ unsigned char INTF:1;
+ unsigned char T0IF:1;
+ unsigned char GPIE:1;
+ unsigned char INTE:1;
+ unsigned char T0IE:1;
+ unsigned char PEIE:1;
+ unsigned char GIE:1;
+ };
+} __INTCON_bits_t;
+extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
+
+#define GPIF INTCON_bits.GPIF
+#define INTF INTCON_bits.INTF
+#define T0IF INTCON_bits.T0IF
+#define GPIE INTCON_bits.GPIE
+#define INTE INTCON_bits.INTE
+#define T0IE INTCON_bits.T0IE
+#define PEIE INTCON_bits.PEIE
+#define GIE INTCON_bits.GIE
+
+// ----- OPTION_REG bits --------------------
+typedef union {
+ struct {
+ unsigned char PS0:1;
+ unsigned char PS1:1;
+ unsigned char PS2:1;
+ unsigned char PSA:1;
+ unsigned char T0SE:1;
+ unsigned char T0CS:1;
+ unsigned char INTEDG:1;
+ unsigned char NOT_GPPU:1;
+ };
+} __OPTION_REG_bits_t;
+extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
+
+#define PS0 OPTION_REG_bits.PS0
+#define PS1 OPTION_REG_bits.PS1
+#define PS2 OPTION_REG_bits.PS2
+#define PSA OPTION_REG_bits.PSA
+#define T0SE OPTION_REG_bits.T0SE
+#define T0CS OPTION_REG_bits.T0CS
+#define INTEDG OPTION_REG_bits.INTEDG
+#define NOT_GPPU OPTION_REG_bits.NOT_GPPU
+
+// ----- OSCCON bits --------------------
+typedef union {
+ struct {
+ unsigned char SCS:1;
+ unsigned char LTS:1;
+ unsigned char HTS:1;
+ unsigned char OSTS:1;
+ unsigned char IRCF0:1;
+ unsigned char IRCF1:1;
+ unsigned char IRCF2:1;
+ unsigned char :1;
+ };
+} __OSCCON_bits_t;
+extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
+
+#define SCS OSCCON_bits.SCS
+#define LTS OSCCON_bits.LTS
+#define HTS OSCCON_bits.HTS
+#define OSTS OSCCON_bits.OSTS
+#define IRCF0 OSCCON_bits.IRCF0
+#define IRCF1 OSCCON_bits.IRCF1
+#define IRCF2 OSCCON_bits.IRCF2
+
+// ----- OSCTUNE bits --------------------
+typedef union {
+ struct {
+ unsigned char TUN0:1;
+ unsigned char TUN1:1;
+ unsigned char TUN2:1;
+ unsigned char TUN3:1;
+ unsigned char TUN4:1;
+ unsigned char IOC5:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+ struct {
+ unsigned char IOC0:1;
+ unsigned char IOC1:1;
+ unsigned char IOC2:1;
+ unsigned char IOC3:1;
+ unsigned char IOC4:1;
+ unsigned char IOCA5:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+ struct {
+ unsigned char IOCA0:1;
+ unsigned char IOCA1:1;
+ unsigned char IOCA2:1;
+ unsigned char IOCA3:1;
+ unsigned char IOCA4:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __OSCTUNE_bits_t;
+extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
+
+#define TUN0 OSCTUNE_bits.TUN0
+#define IOC0 OSCTUNE_bits.IOC0
+#define IOCA0 OSCTUNE_bits.IOCA0
+#define TUN1 OSCTUNE_bits.TUN1
+#define IOC1 OSCTUNE_bits.IOC1
+#define IOCA1 OSCTUNE_bits.IOCA1
+#define TUN2 OSCTUNE_bits.TUN2
+#define IOC2 OSCTUNE_bits.IOC2
+#define IOCA2 OSCTUNE_bits.IOCA2
+#define TUN3 OSCTUNE_bits.TUN3
+#define IOC3 OSCTUNE_bits.IOC3
+#define IOCA3 OSCTUNE_bits.IOCA3
+#define TUN4 OSCTUNE_bits.TUN4
+#define IOC4 OSCTUNE_bits.IOC4
+#define IOCA4 OSCTUNE_bits.IOCA4
+#define IOC5 OSCTUNE_bits.IOC5
+#define IOCA5 OSCTUNE_bits.IOCA5
+
+// ----- PCON bits --------------------
+typedef union {
+ struct {
+ unsigned char NOT_BOD:1;
+ unsigned char NOT_POR:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char SBODEN:1;
+ unsigned char ULPWUE:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __PCON_bits_t;
+extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
+
+#define NOT_BOD PCON_bits.NOT_BOD
+#define NOT_POR PCON_bits.NOT_POR
+#define SBODEN PCON_bits.SBODEN
+#define ULPWUE PCON_bits.ULPWUE
+
+// ----- PIE1 bits --------------------
+typedef union {
+ struct {
+ unsigned char T1IE:1;
+ unsigned char T2IE:1;
+ unsigned char OSFIE:1;
+ unsigned char CMIE:1;
+ unsigned char :1;
+ unsigned char CCP1IE:1;
+ unsigned char ADIE:1;
+ unsigned char EEIE:1;
+ };
+ struct {
+ unsigned char TMR1IE:1;
+ unsigned char TMR2IE:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __PIE1_bits_t;
+extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
+
+#define T1IE PIE1_bits.T1IE
+#define TMR1IE PIE1_bits.TMR1IE
+#define T2IE PIE1_bits.T2IE
+#define TMR2IE PIE1_bits.TMR2IE
+#define OSFIE PIE1_bits.OSFIE
+#define CMIE PIE1_bits.CMIE
+#define CCP1IE PIE1_bits.CCP1IE
+#define ADIE PIE1_bits.ADIE
+#define EEIE PIE1_bits.EEIE
+
+// ----- PIR1 bits --------------------
+typedef union {
+ struct {
+ unsigned char T1IF:1;
+ unsigned char T2IF:1;
+ unsigned char OSFIF:1;
+ unsigned char CMIF:1;
+ unsigned char :1;
+ unsigned char CCP1IF:1;
+ unsigned char ADIF:1;
+ unsigned char EEIF:1;
+ };
+ struct {
+ unsigned char TMR1IF:1;
+ unsigned char TMR2IF:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __PIR1_bits_t;
+extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
+
+#define T1IF PIR1_bits.T1IF
+#define TMR1IF PIR1_bits.TMR1IF
+#define T2IF PIR1_bits.T2IF
+#define TMR2IF PIR1_bits.TMR2IF
+#define OSFIF PIR1_bits.OSFIF
+#define CMIF PIR1_bits.CMIF
+#define CCP1IF PIR1_bits.CCP1IF
+#define ADIF PIR1_bits.ADIF
+#define EEIF PIR1_bits.EEIF
+
+// ----- STATUS bits --------------------
+typedef union {
+ struct {
+ unsigned char C:1;
+ unsigned char DC:1;
+ unsigned char Z:1;
+ unsigned char NOT_PD:1;
+ unsigned char NOT_TO:1;
+ unsigned char RP0:1;
+ unsigned char RP1:1;
+ unsigned char IRP:1;
+ };
+} __STATUS_bits_t;
+extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
+
+#define C STATUS_bits.C
+#define DC STATUS_bits.DC
+#define Z STATUS_bits.Z
+#define NOT_PD STATUS_bits.NOT_PD
+#define NOT_TO STATUS_bits.NOT_TO
+#define RP0 STATUS_bits.RP0
+#define RP1 STATUS_bits.RP1
+#define IRP STATUS_bits.IRP
+
+// ----- T1CON bits --------------------
+typedef union {
+ struct {
+ unsigned char TMR1ON:1;
+ unsigned char TMR1CS:1;
+ unsigned char NOT_T1SYNC:1;
+ unsigned char T1OSCEN:1;
+ unsigned char T1CKPS0:1;
+ unsigned char T1CKPS1:1;
+ unsigned char T1GE:1;
+ unsigned char T1GINV:1;
+ };
+} __T1CON_bits_t;
+extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
+
+#define TMR1ON T1CON_bits.TMR1ON
+#define TMR1CS T1CON_bits.TMR1CS
+#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
+#define T1OSCEN T1CON_bits.T1OSCEN
+#define T1CKPS0 T1CON_bits.T1CKPS0
+#define T1CKPS1 T1CON_bits.T1CKPS1
+#define T1GE T1CON_bits.T1GE
+#define T1GINV T1CON_bits.T1GINV
+
+// ----- T2CON bits --------------------
+typedef union {
+ struct {
+ unsigned char T2CKPS0:1;
+ unsigned char T2CKPS1:1;
+ unsigned char TMR2ON:1;
+ unsigned char TOUTPS0:1;
+ unsigned char TOUTPS1:1;
+ unsigned char TOUTPS2:1;
+ unsigned char TOUTPS3:1;
+ unsigned char :1;
+ };
+} __T2CON_bits_t;
+extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
+
+#define T2CKPS0 T2CON_bits.T2CKPS0
+#define T2CKPS1 T2CON_bits.T2CKPS1
+#define TMR2ON T2CON_bits.TMR2ON
+#define TOUTPS0 T2CON_bits.TOUTPS0
+#define TOUTPS1 T2CON_bits.TOUTPS1
+#define TOUTPS2 T2CON_bits.TOUTPS2
+#define TOUTPS3 T2CON_bits.TOUTPS3
+
+// ----- VRCON bits --------------------
+typedef union {
+ struct {
+ unsigned char VR0:1;
+ unsigned char VR1:1;
+ unsigned char VR2:1;
+ unsigned char VR3:1;
+ unsigned char ADCS0:1;
+ unsigned char VRR:1;
+ unsigned char ADCS2:1;
+ unsigned char VREN:1;
+ };
+ struct {
+ unsigned char RD:1;
+ unsigned char WR:1;
+ unsigned char WREN:1;
+ unsigned char WRERR:1;
+ unsigned char :1;
+ unsigned char ADCS1:1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+ struct {
+ unsigned char ANS0:1;
+ unsigned char ANS1:1;
+ unsigned char ANS2:1;
+ unsigned char ANS3:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __VRCON_bits_t;
+extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
+
+#define VR0 VRCON_bits.VR0
+#define RD VRCON_bits.RD
+#define ANS0 VRCON_bits.ANS0
+#define VR1 VRCON_bits.VR1
+#define WR VRCON_bits.WR
+#define ANS1 VRCON_bits.ANS1
+#define VR2 VRCON_bits.VR2
+#define WREN VRCON_bits.WREN
+#define ANS2 VRCON_bits.ANS2
+#define VR3 VRCON_bits.VR3
+#define WRERR VRCON_bits.WRERR
+#define ANS3 VRCON_bits.ANS3
+#define ADCS0 VRCON_bits.ADCS0
+#define VRR VRCON_bits.VRR
+#define ADCS1 VRCON_bits.ADCS1
+#define ADCS2 VRCON_bits.ADCS2
+#define VREN VRCON_bits.VREN
+
+// ----- WDTCON bits --------------------
+typedef union {
+ struct {
+ unsigned char SWDTEN:1;
+ unsigned char WDTPS0:1;
+ unsigned char WDTPS1:1;
+ unsigned char WDTPS2:1;
+ unsigned char WDTPS3:1;
+ unsigned char :1;
+ unsigned char :1;
+ unsigned char :1;
+ };
+} __WDTCON_bits_t;
+extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
+
+#define SWDTEN WDTCON_bits.SWDTEN
+#define WDTPS0 WDTCON_bits.WDTPS0
+#define WDTPS1 WDTCON_bits.WDTPS1
+#define WDTPS2 WDTCON_bits.WDTPS2
+#define WDTPS3 WDTCON_bits.WDTPS3
+
+#endif
#
-# PIC14: 16Fxxx / 16Cxxx series device file for SDCC
+# PIC14: 14 bit 16Fxxx / 16Cxxx / 12Fxxx series device file for SDCC
#
# by Zik Saleeba <zik@zikzak.net> 2006-03-04
#
#
# 16F series
#
-processor 16f54
- program 512
- data 25
- eeprom 0
- io 12
- maxram 0x1f
- bankmsk 0x00
- confsiz 1
- memmap 0x0007 0x001f 0x000
-
-processor 16f57
- program 2K
- data 72
- eeprom 0
- io 20
- maxram 0x7f
- bankmsk 0x60
- confsiz 1
- regmap 0x60 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
- memmap 0x0008 0x000f 0x060
- memmap 0x0010 0x001f 0x000
- memmap 0x0030 0x003f 0x000
- memmap 0x0050 0x005f 0x000
- memmap 0x0070 0x007f 0x000
-
-processor 16f59
- program 2K
- data 134
- eeprom 0
- io 32
- maxram 0x7f
- bankmsk 0xe0
- confsiz 1
- regmap 0xe0 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09
- memmap 0x000a 0x000f 0x000
- memmap 0x0010 0x001f 0x0e0
- memmap 0x0030 0x003f 0x000
- memmap 0x0050 0x005f 0x000
- memmap 0x0070 0x007f 0x000
- memmap 0x0090 0x009f 0x000
- memmap 0x00b0 0x00bf 0x000
- memmap 0x00d0 0x00df 0x000
- memmap 0x00e0 0x00ef 0x000
-
processor 16f72
program 2K
data 128
memmap 0x0110 0x016f 0x000
memmap 0x0190 0x01ef 0x000
-processor 16f505
- program 1K
- data 72
- eeprom 0
- io 12
- maxram 0x7f
- bankmsk 0x60
- confsiz 1
- regmap 0x60 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
- memmap 0x0008 0x000f 0x060
- memmap 0x0010 0x001f 0x000
- memmap 0x0030 0x003f 0x000
- memmap 0x0050 0x005f 0x000
- memmap 0x0070 0x007f 0x000
-
-processor 16f506
- program 1K
- data 67
+processor 16f616, 16hv616
+ program 2K
+ data 128
eeprom 0
- io 12
- maxram 0x7f
- bankmsk 0x60
+ io 11
+ maxram 0xff
+ bankmsk 0x80
confsiz 1
- regmap 0x60 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c
- memmap 0x000d 0x000f 0x060
- memmap 0x0010 0x001f 0x000
- memmap 0x0030 0x003f 0x000
- memmap 0x0050 0x005f 0x000
- memmap 0x0070 0x007f 0x000
+ regmap 0x080 0x00 0x02 0x03 0x04 0x0a 0x0b
+ memmap 0x0020 0x006f 0x000
+ memmap 0x0070 0x007f 0x080
+ memmap 0x00a0 0x00bf 0x000
processor 16f627, 16f627a
program 1K
regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b
memmap 0x0020 0x005f 0x080
-processor 16f635
- program 1K
- data 64
- eeprom 128
- io 6
- maxram 0x1ff
- bankmsk 0x180
- confsiz 1
- regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b
- regmap 0x100 0x01 0x81 0x05 0x85
- memmap 0x0040 0x006f 0x000
- memmap 0x0070 0x007f 0x180
-
processor 16f636, 16f639
program 2K
data 128
#
# 16c series
#
-processor 16c54, 16c54a, 16c54c, 16cr54a, 16cr54c, 16hv540
- program 512
- data 25
- eeprom 0
- io 12
- maxram 0x1f
- bankmsk 0x00
- confsiz 1
- memmap 0x0007 0x001f 0x000
-
-processor 16c55, 16c55a
- program 512
- data 24
- eeprom 0
- io 20
- maxram 0x1f
- bankmsk 0x00
- confsiz 1
- memmap 0x0008 0x001f 0x000
-
-processor 16c56, 16c56a, 16cr56a
- program 1K
- data 25
- eeprom 0
- io 12
- maxram 0x1f
- bankmsk 0x00
- confsiz 1
- memmap 0x0007 0x001f 0x000
-
-processor 16c57, 16c57c, 16cr57c
- program 2K
- data 72
- eeprom 0
- io 20
- maxram 0x7f
- bankmsk 0x60
- confsiz 1
- regmap 0x60 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
- memmap 0x0008 0x000f 0x060
- memmap 0x0010 0x001f 0x000
- memmap 0x0030 0x003f 0x000
- memmap 0x0050 0x005f 0x000
- memmap 0x0070 0x007f 0x000
-
-processor 16c58b, 16cr58b
- program 2K
- data 73
- eeprom 0
- io 12
- maxram 0x7f
- bankmsk 0x60
- confsiz 1
- regmap 0x60 0x00 0x01 0x02 0x03 0x04 0x05 0x06
- memmap 0x0007 0x000f 0x060
- memmap 0x0010 0x001f 0x000
- memmap 0x0030 0x003f 0x000
- memmap 0x0050 0x005f 0x000
- memmap 0x0070 0x007f 0x000
-
processor 16c62, 16c72
program 2K
data 128
memmap 0x0020 0x007f 0x000
memmap 0x00a0 0x00ff 0x000
+processor 16cr73
+ program 4K
+ data 192
+ eeprom 0
+ io 22
+ maxram 0x1ff
+ bankmsk 0x180
+ confsiz 1
+ regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b
+ regmap 0x100 0x01 0x81
+ memmap 0x0020 0x007f 0x000
+ memmap 0x00a0 0x00ff 0x000
+
+processor 16cr74
+ program 4K
+ data 192
+ eeprom 0
+ io 33
+ maxram 0x1ff
+ bankmsk 0x180
+ confsiz 1
+ regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b
+ regmap 0x100 0x01 0x81
+ memmap 0x0020 0x007f 0x000
+ memmap 0x00a0 0x00ff 0x000
+
+processor 16cr76
+ program 8K
+ data 368
+ eeprom 0
+ io 22
+ maxram 0x1ff
+ bankmsk 0x180
+ confsiz 1
+ regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b
+ regmap 0x180 0x01 0x81
+ memmap 0x0020 0x006f 0x000
+ memmap 0x00a0 0x00ef 0x000
+ memmap 0x0110 0x016f 0x000
+ memmap 0x0190 0x01ef 0x000
+ memmap 0x0070 0x007f 0x180
+
+processor 16cr77
+ program 8K
+ data 368
+ eeprom 0
+ io 33
+ maxram 0x1ff
+ bankmsk 0x180
+ confsiz 1
+ regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b
+ regmap 0x180 0x01 0x81
+ memmap 0x0020 0x006f 0x000
+ memmap 0x00a0 0x00ef 0x000
+ memmap 0x0110 0x016f 0x000
+ memmap 0x0190 0x01ef 0x000
+ memmap 0x0070 0x007f 0x180
+
processor 16c432
program 2K
data 128
memmap 0x00a0 0x00bf 0x000
memmap 0x0120 0x016f 0x000
memmap 0x01a0 0x01bf 0x000
+
+#
+# 12F series devices with 14 bit core
+#
+processor 12f629, 12f675
+ program 1K
+ data 64
+ eeprom 128
+ io 6
+ maxram 0xff
+ bankmsk 0x80
+ confsiz 1
+ regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b
+ memmap 0x0020 0x005f 0x000
+ memmap 0x00a0 0x00df 0x000
+
+processor 12f635
+ program 1K
+ data 64
+ eeprom 128
+ io 6
+ maxram 0x1ff
+ bankmsk 0x180
+ confsiz 1
+ regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b
+ regmap 0x100 0x01 0x81 0x05 0x85
+ memmap 0x0040 0x006f 0x000
+ memmap 0x0070 0x007f 0x180
+
+processor 12f683
+ program 2K
+ data 128
+ eeprom 256
+ io 6
+ maxram 0xff
+ bankmsk 0x80
+ confsiz 1
+ regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b
+ memmap 0x0020 0x006f 0x000
+ memmap 0x0070 0x007f 0x080
+ memmap 0x00a0 0x00bf 0x000
+++ /dev/null
-//
-// Register Declarations for Microchip 16F505 Processor
-//
-//
-// This header file was automatically generated by:
-//
-// inc2h.pl V1.6
-//
-// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
-//
-// SDCC is licensed under the GNU Public license (GPL) v2. Note that
-// this license covers the code to the compiler and other executables,
-// but explicitly does not cover any code or objects generated by sdcc.
-// We have not yet decided on a license for the run time libraries, but
-// it will not put any requirements on code linked against it. See:
-//
-// http://www.gnu.org/copyleft/gpl/html
-//
-// See http://sdcc.sourceforge.net/ for the latest information on sdcc.
-//
-//
-#ifndef P16F505_H
-#define P16F505_H
-
-//
-// Register addresses.
-//
-#define INDF_ADDR 0x0000
-#define TMR0_ADDR 0x0001
-#define PCL_ADDR 0x0002
-#define STATUS_ADDR 0x0003
-#define FSR_ADDR 0x0004
-#define OSCCAL_ADDR 0x0005
-#define PORTB_ADDR 0x0006
-#define PORTC_ADDR 0x0007
-#define OPTION_REG_ADDR 0x0081
-
-//
-// Memory organization.
-//
-
-#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
-#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
-#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
-#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
-#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
-#pragma memmap OSCCAL_ADDR OSCCAL_ADDR SFR 0x000 // OSCCAL
-#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
-#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
-#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
-
-
-// LIST
-// P16F505.INC Standard Header File, Version 1.10 Microchip Technology, Inc.
-// NOLIST
-
-// This header file defines configurations, registers, and other useful bits of
-// information for the PIC16F505 microcontroller. These names are taken to match
-// the data sheets as closely as possible.
-
-// Note that the processor must be selected before this file is
-// included. The processor may be selected the following ways:
-
-// 1. Command line switch:
-// C:\ MPASM MYFILE.ASM /P16F505
-// 2. LIST directive in the source file
-// LIST P=16F505
-// 3. Processor Type entry in the MPASM full-screen interface
-
-//==========================================================================
-//
-// Revision History
-//
-//==========================================================================
-
-//Rev: Date: Reason:
-
-//1.00 12/09/03 Initial Release
-//1.01 04/14/04 Update for EC osc mode
-
-
-//==========================================================================
-//
-// Verify Processor
-//
-//==========================================================================
-
-// IFNDEF __16F505
-// MESSG "Processor-header file mismatch. Verify selected processor."
-// ENDIF
-
-//==========================================================================
-//
-// Register Definitions
-//
-//==========================================================================
-
-#define W 0x0000
-#define F 0x0001
-
-//----- Register Files -----------------------------------------------------
-
-extern __data __at (INDF_ADDR) volatile char INDF;
-extern __sfr __at (TMR0_ADDR) TMR0;
-extern __data __at (PCL_ADDR) volatile char PCL;
-extern __sfr __at (STATUS_ADDR) STATUS;
-extern __sfr __at (FSR_ADDR) FSR;
-extern __sfr __at (OSCCAL_ADDR) OSCCAL;
-extern __sfr __at (PORTB_ADDR) PORTB;
-extern __sfr __at (PORTC_ADDR) PORTC;
-extern __sfr __at (OPTION_REG_ADDR) OPTION_REG; // not verified
-
-//----- STATUS Bits --------------------------------------------------------
-
-
-//----- OPTION Bits --------------------------------------------------------
-
-
-//----- OSCCAL Bits --------------------------------------------------------
-
-
-//==========================================================================
-//
-// RAM Definition
-//
-//==========================================================================
-
-// __MAXRAM H'7F'
-
-//==========================================================================
-//
-// Configuration Bits
-//
-//==========================================================================
-
-#define _MCLRE_ON 0x0FFF
-#define _MCLRE_OFF 0x0FDF
-#define _CP_ON 0x002F
-#define _CP_OFF 0x0FFF
-#define _WDT_ON 0x0FFF
-#define _WDT_OFF 0x0FF7
-#define _LP_OSC 0x0FF8
-#define _XT_OSC 0x0FF9
-#define _HS_OSC 0x0FFA
-#define _EC_RB4EN 0x0FFB
-#define _IntRC_OSC_RB4EN 0x0FFC
-#define _IntRC_OSC_CLKOUTEN 0x0FFD
-#define _ExtRC_OSC_RB4EN 0x0FFE
-#define _ExtRC_OSC_CLKOUTEN 0x0FFF
-
-// LIST
-
-// ----- OPTION_REG bits --------------------
-typedef union {
- struct {
- unsigned char PS0:1;
- unsigned char PS1:1;
- unsigned char PS2:1;
- unsigned char PSA:1;
- unsigned char T0SE:1;
- unsigned char T0CS:1;
- unsigned char NOT_RBPU:1;
- unsigned char NOT_RBWU:1;
- };
-} __OPTION_REG_bits_t;
-extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
-
-#define PS0 OPTION_REG_bits.PS0
-#define PS1 OPTION_REG_bits.PS1
-#define PS2 OPTION_REG_bits.PS2
-#define PSA OPTION_REG_bits.PSA
-#define T0SE OPTION_REG_bits.T0SE
-#define T0CS OPTION_REG_bits.T0CS
-#define NOT_RBPU OPTION_REG_bits.NOT_RBPU
-#define NOT_RBWU OPTION_REG_bits.NOT_RBWU
-
-// ----- OSCCAL bits --------------------
-typedef union {
- struct {
- unsigned char :1;
- unsigned char CAL0:1;
- unsigned char CAL1:1;
- unsigned char CAL2:1;
- unsigned char CAL3:1;
- unsigned char CAL4:1;
- unsigned char CAL5:1;
- unsigned char CAL6:1;
- };
-} __OSCCAL_bits_t;
-extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits;
-
-#define CAL0 OSCCAL_bits.CAL0
-#define CAL1 OSCCAL_bits.CAL1
-#define CAL2 OSCCAL_bits.CAL2
-#define CAL3 OSCCAL_bits.CAL3
-#define CAL4 OSCCAL_bits.CAL4
-#define CAL5 OSCCAL_bits.CAL5
-#define CAL6 OSCCAL_bits.CAL6
-
-// ----- STATUS bits --------------------
-typedef union {
- struct {
- unsigned char C:1;
- unsigned char DC:1;
- unsigned char Z:1;
- unsigned char NOT_PD:1;
- unsigned char NOT_TO:1;
- unsigned char PA0:1;
- unsigned char :1;
- unsigned char RBWUF:1;
- };
-} __STATUS_bits_t;
-extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
-
-#define C STATUS_bits.C
-#define DC STATUS_bits.DC
-#define Z STATUS_bits.Z
-#define NOT_PD STATUS_bits.NOT_PD
-#define NOT_TO STATUS_bits.NOT_TO
-#define PA0 STATUS_bits.PA0
-#define RBWUF STATUS_bits.RBWUF
-
-#endif
*
* May, 2005
* The GNU PIC Library is maintained by
- * Raphael Neider <rneider@web.de>
+ * Raphael Neider <rneider AT web.de>
*
* originally designed by
* Vangelis Rokas <vrokas@otenet.gr>
*
* May, 2005
* The GNU PIC Library is maintained by
- * Raphael Neider <rneider@web.de>
+ * Raphael Neider <rneider AT web.de>
*
* originally designed by
* Vangelis Rokas <vrokas@otenet.gr>
*
* May, 2005
* The GNU PIC Library is maintained by
- * Raphael Neider <rneider@web.de>
+ * Raphael Neider <rneider AT web.de>
*
* originally designed by
* Vangelis Rokas <vrokas@otenet.gr>
*
* May, 2005
* The GNU PIC Library is maintained by
- * Raphael Neider <rneider@web.de>
+ * Raphael Neider <rneider AT web.de>
*
* originally designed by
* Vangelis Rokas <vrokas@otenet.gr>
*
* May, 2005
* The GNU PIC Library is maintained by
- * Raphael Neider <rneider@web.de>
+ * Raphael Neider <rneider AT web.de>
*
* originally designed by
* Vangelis Rokas <vrokas@otenet.gr>
/*-------------------------------------------------------------------------
stdbool.h - ANSI functions forward declarations
- Ported to PIC16 port by Raphael Neider 2005 (RNeider@web.de)
+ Ported to PIC16 port by Raphael Neider <rneider AT web.de> (2005)
Written By - Maarten Brock, sourceforge.brock@dse.nl (2004)
/*-------------------------------------------------------------------------
stddef.h - ANSI functions forward declarations
- Ported to PIC16 port by Raphael Neider, 2005 (rneider@web.de)
+ Ported to PIC16 port by Raphael Neider <rneider AT web.de> (2005)
Written By - Maarten Brock / sourceforge.brock@dse.nl (June 2004)
###########################################################
### Makefile.common.in for the SDCC/PIC14 Library
###
-### Copyright (C) 2005 by Raphael Neider <rneider@web.de>
+### Copyright (C) 2005 by Raphael Neider <rneider AT web.de>
###
### The library is currently maintained by
-### Raphael Neider <rneider@web.de>
+### Raphael Neider <rneider AT web.de>
###
### This file may be distributed under the terms of the the
### GNU General Public License (GPL). See GPL for details.
###########################################################
### Makefile for the SDCC/PIC14 Library
###
-### Copyright (C) 2005 by Raphael Neider <rneider@web.de>
+### Copyright (C) 2005 by Raphael Neider <rneider AT web.de>
###
### The library is currently maintained by
-### Raphael Neider <rneider@web.de>
+### Raphael Neider <rneider AT web.de>
###
### This file may be distributed under the terms of the the
### GNU General Public License (GPL). See GPL for details.
###########################################################
### Makefile.rules for the SDCC/PIC14 Library
###
-### Copyright (C) 2005 by Raphael Neider <rneider@web.de>
+### Copyright (C) 2005 by Raphael Neider <rneider AT web.de>
###
### The library is currently maintained by
-### Raphael Neider <rneider@web.de>
+### Raphael Neider <rneider AT web.de>
###
### This file may be distributed under the terms of the the
### GNU General Public License (GPL). See GPL for details.
###########################################################
### Makefile.subdir for the SDCC/PIC14 Library
###
-### Copyright (C) 2005 by Raphael Neider <rneider@web.de>
+### Copyright (C) 2005 by Raphael Neider <rneider AT web.de>
###
### The library is currently maintained by
-### Raphael Neider <rneider@web.de>
+### Raphael Neider <rneider AT web.de>
###
### This file may be distributed under the terms of the the
### GNU General Public License (GPL). See GPL for details.
common to all pic14 chips. This part is currently absent...
The SDCC/pic14 library has been created by
- Raphael Neider (2005), rneider@web.de
+ Raphael Neider <rneider AT web.de> (2005)
It is currently maintained by
- Raphael Neider, rneider@web.de
+ Raphael Neider <rneider AT web.de>
The pic14 and the device specific parts (whose sources are found
in device/lib/pic/) are to be licensed nuder the terms of the
; -------------------------------------------------------------------------
; TEMPLATE.S : template for creating library assembler sources
;
-; Written By Raphael Neider, rneider@web.de (2005)
+; Written By Raphael Neider <rneider AT web.de> (2005)
;
; This library is free software; you can redistribute it and/or
; modify it under the terms of the GNU Library General Public
/* ---------------------------------------------------------------------------
TEMPLATE.c : template for creating library sources
- Written By Raphael Neider, rneider@web.de (2005)
+ Written By Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
# Vangelis Rokas <vrokas@otenet.gr>
#
# Adopted for the SDCC/pic14 library by
-# Raphael Neider <rneider@web.de>
+# Raphael Neider <rneider AT web.de>
#
# $Id$
#
CPPFLAGS = -I$(srcdir)/../../../include/pic
-C_SRC = $(notdir $(wildcard $(srcdir)/pic16*.c))
+C_SRC = $(notdir $(wildcard $(srcdir)/pic1*.c))
OBJS = $(C_SRC:.c=.o)
LIBS = $(addprefix $(INSTALL_DIR)/,$(OBJS:.o=.lib))
--- /dev/null
+/* Register definitions for pic12f629.
+ * This file was automatically generated by:
+ * inc2h.pl V1.7
+ * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
+ */
+#include <pic12f629.h>
+
+__data __at (INDF_ADDR) volatile char INDF;
+__sfr __at (TMR0_ADDR) TMR0;
+__data __at (PCL_ADDR) volatile char PCL;
+__sfr __at (STATUS_ADDR) STATUS;
+__sfr __at (FSR_ADDR) FSR;
+__sfr __at (GPIO_ADDR) GPIO;
+__sfr __at (PCLATH_ADDR) PCLATH;
+__sfr __at (INTCON_ADDR) INTCON;
+__sfr __at (PIR1_ADDR) PIR1;
+__sfr __at (TMR1L_ADDR) TMR1L;
+__sfr __at (TMR1H_ADDR) TMR1H;
+__sfr __at (T1CON_ADDR) T1CON;
+__sfr __at (CMCON_ADDR) CMCON;
+__sfr __at (OPTION_REG_ADDR) OPTION_REG;
+__sfr __at (TRISIO_ADDR) TRISIO;
+__sfr __at (PIE1_ADDR) PIE1;
+__sfr __at (PCON_ADDR) PCON;
+__sfr __at (OSCCAL_ADDR) OSCCAL;
+__sfr __at (WPU_ADDR) WPU;
+__sfr __at (IOCB_ADDR) IOCB;
+__sfr __at (IOC_ADDR) IOC;
+__sfr __at (VRCON_ADDR) VRCON;
+__sfr __at (EEDATA_ADDR) EEDATA;
+__sfr __at (EEDAT_ADDR) EEDAT;
+__sfr __at (EEADR_ADDR) EEADR;
+__sfr __at (EECON1_ADDR) EECON1;
+__sfr __at (EECON2_ADDR) EECON2;
+
+//
+// bitfield definitions
+//
+volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
+volatile __GPIO_bits_t __at(GPIO_ADDR) GPIO_bits;
+volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
+volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
+volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
+volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
+volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits;
+volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
+volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
+volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
+volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
+volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
+volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
+
--- /dev/null
+/* Register definitions for pic12f635.
+ * This file was automatically generated by:
+ * inc2h.pl V1.7
+ * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
+ */
+#include <pic12f635.h>
+
+__data __at (INDF_ADDR) volatile char INDF;
+__sfr __at (TMR0_ADDR) TMR0;
+__data __at (PCL_ADDR) volatile char PCL;
+__sfr __at (STATUS_ADDR) STATUS;
+__sfr __at (FSR_ADDR) FSR;
+__sfr __at (PORTA_ADDR) PORTA;
+__sfr __at (GPIO_ADDR) GPIO;
+__sfr __at (PCLATH_ADDR) PCLATH;
+__sfr __at (INTCON_ADDR) INTCON;
+__sfr __at (PIR1_ADDR) PIR1;
+__sfr __at (TMR1L_ADDR) TMR1L;
+__sfr __at (TMR1H_ADDR) TMR1H;
+__sfr __at (T1CON_ADDR) T1CON;
+__sfr __at (WDTCON_ADDR) WDTCON;
+__sfr __at (CMCON0_ADDR) CMCON0;
+__sfr __at (CMCON1_ADDR) CMCON1;
+__sfr __at (OPTION_REG_ADDR) OPTION_REG;
+__sfr __at (TRISA_ADDR) TRISA;
+__sfr __at (TRISIO_ADDR) TRISIO;
+__sfr __at (PIE1_ADDR) PIE1;
+__sfr __at (PCON_ADDR) PCON;
+__sfr __at (OSCCON_ADDR) OSCCON;
+__sfr __at (OSCTUNE_ADDR) OSCTUNE;
+__sfr __at (LVDCON_ADDR) LVDCON;
+__sfr __at (WPUDA_ADDR) WPUDA;
+__sfr __at (IOCA_ADDR) IOCA;
+__sfr __at (WDA_ADDR) WDA;
+__sfr __at (VRCON_ADDR) VRCON;
+__sfr __at (EEDAT_ADDR) EEDAT;
+__sfr __at (EEDATA_ADDR) EEDATA;
+__sfr __at (EEADR_ADDR) EEADR;
+__sfr __at (EECON1_ADDR) EECON1;
+__sfr __at (EECON2_ADDR) EECON2;
+__sfr __at (CRCON_ADDR) CRCON;
+__sfr __at (CRDAT0_ADDR) CRDAT0;
+__sfr __at (CRDAT1_ADDR) CRDAT1;
+__sfr __at (CRDAT2_ADDR) CRDAT2;
+__sfr __at (CRDAT3_ADDR) CRDAT3;
+
+//
+// bitfield definitions
+//
+volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
+volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
+volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
+volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
+volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
+volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
+volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
+volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
+volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
+volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
+volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
+volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
+
--- /dev/null
+/* Register definitions for pic12f675.
+ * This file was automatically generated by:
+ * inc2h.pl V1.7
+ * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
+ */
+#include <pic12f675.h>
+
+__data __at (INDF_ADDR) volatile char INDF;
+__sfr __at (TMR0_ADDR) TMR0;
+__data __at (PCL_ADDR) volatile char PCL;
+__sfr __at (STATUS_ADDR) STATUS;
+__sfr __at (FSR_ADDR) FSR;
+__sfr __at (GPIO_ADDR) GPIO;
+__sfr __at (PCLATH_ADDR) PCLATH;
+__sfr __at (INTCON_ADDR) INTCON;
+__sfr __at (PIR1_ADDR) PIR1;
+__sfr __at (TMR1L_ADDR) TMR1L;
+__sfr __at (TMR1H_ADDR) TMR1H;
+__sfr __at (T1CON_ADDR) T1CON;
+__sfr __at (CMCON_ADDR) CMCON;
+__sfr __at (ADRESH_ADDR) ADRESH;
+__sfr __at (ADCON0_ADDR) ADCON0;
+__sfr __at (OPTION_REG_ADDR) OPTION_REG;
+__sfr __at (TRISIO_ADDR) TRISIO;
+__sfr __at (PIE1_ADDR) PIE1;
+__sfr __at (PCON_ADDR) PCON;
+__sfr __at (OSCCAL_ADDR) OSCCAL;
+__sfr __at (WPU_ADDR) WPU;
+__sfr __at (IOC_ADDR) IOC;
+__sfr __at (IOCB_ADDR) IOCB;
+__sfr __at (VRCON_ADDR) VRCON;
+__sfr __at (EEDATA_ADDR) EEDATA;
+__sfr __at (EEDAT_ADDR) EEDAT;
+__sfr __at (EEADR_ADDR) EEADR;
+__sfr __at (EECON1_ADDR) EECON1;
+__sfr __at (EECON2_ADDR) EECON2;
+__sfr __at (ADRESL_ADDR) ADRESL;
+__sfr __at (ANSEL_ADDR) ANSEL;
+
+//
+// bitfield definitions
+//
+volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
+volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
+volatile __GPIO_bits_t __at(GPIO_ADDR) GPIO_bits;
+volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
+volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
+volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
+volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
+volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits;
+volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
+volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
+volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
+volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
+volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
+volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
+
--- /dev/null
+/* Register definitions for pic12f683.
+ * This file was automatically generated by:
+ * inc2h.pl V1.7
+ * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
+ */
+#include <pic12f683.h>
+
+__data __at (INDF_ADDR) volatile char INDF;
+__sfr __at (TMR0_ADDR) TMR0;
+__data __at (PCL_ADDR) volatile char PCL;
+__sfr __at (STATUS_ADDR) STATUS;
+__sfr __at (FSR_ADDR) FSR;
+__sfr __at (GPIO_ADDR) GPIO;
+__sfr __at (PCLATH_ADDR) PCLATH;
+__sfr __at (INTCON_ADDR) INTCON;
+__sfr __at (PIR1_ADDR) PIR1;
+__sfr __at (TMR1L_ADDR) TMR1L;
+__sfr __at (TMR1H_ADDR) TMR1H;
+__sfr __at (T1CON_ADDR) T1CON;
+__sfr __at (TMR2_ADDR) TMR2;
+__sfr __at (T2CON_ADDR) T2CON;
+__sfr __at (CCPR1L_ADDR) CCPR1L;
+__sfr __at (CCPR1H_ADDR) CCPR1H;
+__sfr __at (CCP1CON_ADDR) CCP1CON;
+__sfr __at (WDTCON_ADDR) WDTCON;
+__sfr __at (CMCON0_ADDR) CMCON0;
+__sfr __at (CMCON1_ADDR) CMCON1;
+__sfr __at (ADRESH_ADDR) ADRESH;
+__sfr __at (ADCON0_ADDR) ADCON0;
+__sfr __at (OPTION_REG_ADDR) OPTION_REG;
+__sfr __at (TRISIO_ADDR) TRISIO;
+__sfr __at (PIE1_ADDR) PIE1;
+__sfr __at (PCON_ADDR) PCON;
+__sfr __at (OSCCON_ADDR) OSCCON;
+__sfr __at (OSCTUNE_ADDR) OSCTUNE;
+__sfr __at (PR2_ADDR) PR2;
+__sfr __at (WPU_ADDR) WPU;
+__sfr __at (WPUA_ADDR) WPUA;
+__sfr __at (IOC_ADDR) IOC;
+__sfr __at (IOCA_ADDR) IOCA;
+__sfr __at (VRCON_ADDR) VRCON;
+__sfr __at (EEDATA_ADDR) EEDATA;
+__sfr __at (EEDAT_ADDR) EEDAT;
+__sfr __at (EEADR_ADDR) EEADR;
+__sfr __at (EECON1_ADDR) EECON1;
+__sfr __at (EECON2_ADDR) EECON2;
+__sfr __at (ADRESL_ADDR) ADRESL;
+__sfr __at (ANSEL_ADDR) ANSEL;
+
+//
+// bitfield definitions
+//
+volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
+volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
+volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
+volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
+volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
+volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
+volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
+volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
+volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
+volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
+volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
+volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
+volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
+volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
+volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
+volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
+
+++ /dev/null
-/* Register definitions for pic16f505.
- * This file was automatically generated by:
- * inc2h.pl V1.6
- * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
- */
-#include <pic16f505.h>
-
-__data __at (INDF_ADDR) volatile char INDF;
-__sfr __at (TMR0_ADDR) TMR0;
-__data __at (PCL_ADDR) volatile char PCL;
-__sfr __at (STATUS_ADDR) STATUS;
-__sfr __at (FSR_ADDR) FSR;
-__sfr __at (OSCCAL_ADDR) OSCCAL;
-__sfr __at (PORTB_ADDR) PORTB;
-__sfr __at (PORTC_ADDR) PORTC;
-__sfr __at (OPTION_REG_ADDR) OPTION_REG;
-
-//
-// bitfield definitions
-//
-volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
-volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits;
-volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
-
/* ---------------------------------------------------------------------------
_divschar.c : 8 bit division routines for pic14 devices
- Written By Raphael Neider, rneider@web.de (2005)
+ Written By Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
/* ---------------------------------------------------------------------------
_divsint.c : 16 bit division routines for pic14 devices
- Written By Raphael Neider, rneider@web.de (2005)
+ Written By Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
/* ---------------------------------------------------------------------------
_divslong.c : 32 bit division routines for pic14 devices
- Written By Raphael Neider, rneider@web.de (2005)
+ Written By Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
/* ---------------------------------------------------------------------------
_divuchar.c : 8 bit division routines for pic14 devices
- Written By Raphael Neider, rneider@web.de (2005)
+ Written By Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
/* ---------------------------------------------------------------------------
_divuint.c : 16 bit division routines for pic14 devices
- Written By Raphael Neider, rneider@web.de (2005)
+ Written By Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
/* ---------------------------------------------------------------------------
_divulong.c : 32 bit division routines for pic14 devices
- Written By Raphael Neider, rneider@web.de (2005)
+ Written By Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
; -------------------------------------------------------------------------
; _gptrget1.S - read one byte pointed to by a generic pointer
;
-; Written By Raphael Neider, rneider@web.de (2005)
+; Written By Raphael Neider <rneider AT web.de> (2005)
;
; This library is free software; you can redistribute it and/or
; modify it under the terms of the GNU Library General Public
; -------------------------------------------------------------------------
; _gptrget2.S - read two bytes pointed to by a generic pointer
;
-; Written By Raphael Neider, rneider@web.de (2005)
+; Written By Raphael Neider <rneider AT web.de> (2005)
;
; This library is free software; you can redistribute it and/or
; modify it under the terms of the GNU Library General Public
; -------------------------------------------------------------------------
; _gptrget3.S - read three bytes pointed to by a generic pointer
;
-; Written By Raphael Neider, rneider@web.de (2005)
+; Written By Raphael Neider <rneider AT web.de> (2005)
;
; This library is free software; you can redistribute it and/or
; modify it under the terms of the GNU Library General Public
; -------------------------------------------------------------------------
; _gptrget4.S - read four bytes pointed to by a generic pointer
;
-; Written By Raphael Neider, rneider@web.de (2005)
+; Written By Raphael Neider <rneider AT web.de> (2005)
;
; This library is free software; you can redistribute it and/or
; modify it under the terms of the GNU Library General Public
; -------------------------------------------------------------------------
; _gptrput1.S : write one byte pointed to by a generic pointer
;
-; Written By Raphael Neider, rneider@web.de (2005)
+; Written By Raphael Neider <rneider AT web.de> (2005)
;
; This library is free software; you can redistribute it and/or
; modify it under the terms of the GNU Library General Public
; -------------------------------------------------------------------------
; _gptrput2.S : write two bytes pointed to by a generic pointer
;
-; Written By Raphael Neider, rneider@web.de (2005)
+; Written By Raphael Neider <rneider AT web.de> (2005)
;
; This library is free software; you can redistribute it and/or
; modify it under the terms of the GNU Library General Public
; -------------------------------------------------------------------------
; _gptrput3.S : write three bytes pointed to by a generic pointer
;
-; Written By Raphael Neider, rneider@web.de (2005)
+; Written By Raphael Neider <rneider AT web.de> (2005)
;
; This library is free software; you can redistribute it and/or
; modify it under the terms of the GNU Library General Public
; -------------------------------------------------------------------------
; _gptrput4.S : write four bytes pointed to by a generic pointer
;
-; Written By Raphael Neider, rneider@web.de (2005)
+; Written By Raphael Neider <rneider AT web.de> (2005)
;
; This library is free software; you can redistribute it and/or
; modify it under the terms of the GNU Library General Public
/* ---------------------------------------------------------------------------
_modschar.c : 8 bit modulus routines for pic14 devices
- Written By Raphael Neider, rneider@web.de (2005)
+ Written By Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
/* ---------------------------------------------------------------------------
_modsint.c : 16 bit modulus routines for pic14 devices
- Written By Raphael Neider, rneider@web.de (2005)
+ Written By Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
/* ---------------------------------------------------------------------------
_modslong.c : 32 bit modulus routines for pic14 devices
- Written By Raphael Neider, rneider@web.de (2005)
+ Written By Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
/* ---------------------------------------------------------------------------
_moduchar.c : 8 bit modulus routines for pic14 devices
- Written By Raphael Neider, rneider@web.de (2005)
+ Written By Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
/* ---------------------------------------------------------------------------
_moduint.c : 16 bit modulus routines for pic14 devices
- Written By Raphael Neider, rneider@web.de (2005)
+ Written By Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
/* ---------------------------------------------------------------------------
_modulong.c : 32 bit modulus routines for pic14 devices
- Written By Raphael Neider, rneider@web.de (2005)
+ Written By Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
/* ---------------------------------------------------------------------------
_mulchar.c : routine for 8 bit multiplication
- Written By Raphael Neider, rneider@web.de (2005)
+ Written By Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU Library General Public License as published by
/* ---------------------------------------------------------------------------
_mulint.c : routine for 16 bit multiplication
- Written By Raphael Neider, rneider@web.de (2005)
+ Written By Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU Library General Public License as published by
/* ---------------------------------------------------------------------------
_mullong.c : routine for 32 bit multiplication
- Written By Raphael Neider, rneider@web.de (2005)
+ Written By Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU Library General Public License as published by
###########################################################
### Makefile.common.in for the GNU PIC Library
###
-### Copyright (C) 2005 by Raphael Neider <rneider@web.de>
+### Copyright (C) 2005 by Raphael Neider <rneider AT web.de>
###
### The GNU PIC Library was originally designed and
### implemented by
### Vangelis Rokas <vrokas@otenet.gr>
###
### It is currently maintained by
-### Raphael Neider <rneider@web.de>
+### Raphael Neider <rneider AT web.de>
###
### This file may be distributed under the terms of the the
### GNU General Public License (GPL). See COPYING for details.
###########################################################
### Makefile for the GNU PIC Library
###
-### Copyright (C) 2005 by Raphael Neider <rneider@web.de>
+### Copyright (C) 2005 by Raphael Neider <rneider AT web.de>
###
### The GNU PIC Library was originally designed and
### implemented by
### Vangelis Rokas <vrokas@otenet.gr>
###
### It is currently maintained by
-### Raphael Neider <rneider@web.de>
+### Raphael Neider <rneider AT web.de>
###
### This file may be distributed under the terms of the the
### GNU General Public License (GPL). See COPYING for details.
###########################################################
### Makefile.rules for the GNU PIC Library
###
-### Copyright (C) 2005 by Raphael Neider <rneider@web.de>
+### Copyright (C) 2005 by Raphael Neider <rneider AT web.de>
###
### The GNU PIC Library was originally designed and
### implemented by
### Vangelis Rokas <vrokas@otenet.gr>
###
### It is currently maintained by
-### Raphael Neider <rneider@web.de>
+### Raphael Neider <rneider AT web.de>
###
### This file may be distributed under the terms of the the
### GNU General Public License (GPL). See COPYING for details.
###########################################################
### Makefile.subdir for the GNU PIC Library
###
-### Copyright (C) 2005 by Raphael Neider <rneider@web.de>
+### Copyright (C) 2005 by Raphael Neider <rneider AT web.de>
###
### The GNU PIC Library was originally designed and
### implemented by
### Vangelis Rokas <vrokas@otenet.gr>
###
### It is currently maintained by
-### Raphael Neider <rneider@web.de>
+### Raphael Neider <rneider AT web.de>
###
### This file may be distributed under the terms of the the
### GNU General Public License (GPL). See COPYING for details.
/*-------------------------------------------------------------------
itoa.c - convert (unsigned) int to strings
- written by: Raphael Neider <rneider@web.de>
+ written by: Raphael Neider <rneider AT web.de>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
###########################################################
### Makefile for the GNU PIC Library
###
-### Copyright (C) 2005 by Raphael Neider <rneider@web.de>
+### Copyright (C) 2005 by Raphael Neider <rneider AT web.de>
###
### The GNU PIC Library was originally designed and
### implemented by
### Vangelis Rokas <vrokas@otenet.gr>
###
### It is currently maintained by
-### Raphael Neider <rneider@web.de>
+### Raphael Neider <rneider AT web.de>
###
### This file may be distributed under the terms of the the
### GNU General Public License (GPL). See COPYING for details.
*
* May, 2005
* The GNU PIC Library is maintained by
- * Raphael Neider <rneider@web.de>
+ * Raphael Neider <rneider AT web.de>
*
* originally designed by
* Vangelis Rokas <vrokas@otenet.gr>
*
* May, 2005
* The GNU PIC Library is maintained by
- * Raphael Neider <rneider@web.de>
+ * Raphael Neider <rneider AT web.de>
*
* originally designed by
* Vangelis Rokas <vrokas@otenet.gr>
*
* May, 2005
* The GNU PIC Library is maintained by
- * Raphael Neider <rneider@web.de>
+ * Raphael Neider <rneider AT web.de>
*
* originally designed by
* Vangelis Rokas <vrokas@otenet.gr>
*
* May, 2005
* The GNU PIC Library is maintained by
- * Raphael Neider <rneider@web.de>
+ * Raphael Neider <rneider AT web.de>
*
* originally designed by
* Vangelis Rokas <vrokas@otenet.gr>
*
* May, 2005
* The GNU PIC Library is maintained by
- * Raphael Neider <rneider@web.de>
+ * Raphael Neider <rneider AT web.de>
*
* originally designed by
* Vangelis Rokas <vrokas@otenet.gr>
*
* May, 2005
* The GNU PIC Library is maintained by
- * Raphael Neider <rneider@web.de>
+ * Raphael Neider <rneider AT web.de>
*
* originally designed by
* Vangelis Rokas <vrokas@otenet.gr>
###########################################################
### Makefile for the GNU PIC Library
###
-### Copyright (C) 2005 by Raphael Neider <rneider@web.de>
+### Copyright (C) 2005 by Raphael Neider <rneider AT web.de>
###
### The GNU PIC Library was originally designed and
### implemented by
### Vangelis Rokas <vrokas@otenet.gr>
###
### It is currently maintained by
-### Raphael Neider <rneider@web.de>
+### Raphael Neider <rneider AT web.de>
###
### This file may be distributed under the terms of the the
### GNU General Public License (GPL). See COPYING for details.
/*-------------------------------------------------------------------------
fps16x16_eq.c - compare two __fixed16x16 values for equality
- written by - Raphael Neider, rneider@web.de (2005)
+ written by - Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU Library General Public License as published by the
/*-------------------------------------------------------------------------
fps16x16_gt.c - compare two __fixed16x16 values
- written by - Raphael Neider, rneider@web.de (2005)
+ written by - Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU Library General Public License as published by the
/*-------------------------------------------------------------------------
fps16x16_gteq.c - compare two __fixed16x16 values
- written by - Raphael Neider, rneider@web.de (2005)
+ written by - Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU Library General Public License as published by the
/*-------------------------------------------------------------------------
fps16x16_lt.c - compare two __fixed16x16 values
- written by - Raphael Neider, rneider@web.de (2005)
+ written by - Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU Library General Public License as published by the
/*-------------------------------------------------------------------------
fps16x16_lteq.c - compare two __fixed16x16 values
- written by - Raphael Neider, rneider@web.de (2005)
+ written by - Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU Library General Public License as published by the
/*-------------------------------------------------------------------------
fps16x16_neq.c - compare two __fixed16x16 values for inequality
- written by - Raphael Neider, rneider@web.de (2005)
+ written by - Raphael Neider <rneider AT web.de> (2005)
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU Library General Public License as published by the
if (name == NULL)
return NULL;
- if (STRNCASECMP(proc_pos, "pic16", 5) == 0)
- proc_pos += 5;
-
- else if (STRNCASECMP(proc_pos, "p16", 3) == 0)
+ if (STRNCASECMP(proc_pos, "pic", 3) == 0)
proc_pos += 3;
+
+ else if (tolower(*proc_pos) == 'p')
+ proc_pos += 1;
- else if (STRNCASECMP(proc_pos, "16", 2) == 0)
- proc_pos += 2;
-
return proc_pos;
}
char *simple_pic_name = sanitise_processor_name(pic_name);
new_pic = Safe_calloc(1, sizeof(PIC_device));
- new_pic->name[0] = Safe_calloc(strlen(simple_pic_name)+3, sizeof(char));
- sprintf(new_pic->name[0], "16%s", simple_pic_name);
- new_pic->name[1] = Safe_calloc(strlen(simple_pic_name)+4, sizeof(char));
- sprintf(new_pic->name[1], "p16%s", simple_pic_name);
- new_pic->name[2] = Safe_calloc(strlen(simple_pic_name)+6, sizeof(char));
- sprintf(new_pic->name[2], "pic16%s", simple_pic_name);
- new_pic->name[3] = Safe_calloc(strlen(simple_pic_name)+1, sizeof(char));
- strcpy(new_pic->name[3], simple_pic_name);
+ new_pic->name = Safe_calloc(strlen(simple_pic_name)+1, sizeof(char));
+ strcpy(new_pic->name, simple_pic_name);
new_pic->defMaxRAMaddrs = maxram;
new_pic->bankMask = bankmsk;
char filename[512];
int len = 512;
+ /* allow abbreviations of the form "f877" - convert to "16f877" */
simple_pic_name = sanitise_processor_name(pic_name);
-
num_of_supported_PICS = 0;
/* open the piclist file */
* list_alias - if non-zero, print all of the supported aliases
* for a device (e.g. F84, 16F84, etc...)
*-----------------------------------------------------------------*/
-void list_valid_pics(int ncols, int list_alias)
+void list_valid_pics(int ncols)
{
int col=0,longest;
- int i,j,k,l;
- int max_alias = 1;
+ int i,k,l;
if (num_of_supported_PICS == 0)
find_device(NULL); /* load all the definitions */
- if(list_alias)
- max_alias = PROCESSOR_NAMES;
-
/* decrement the column number if it's greater than zero */
ncols = (ncols > 1) ? ncols-1 : 4;
/* Find the device with the longest name */
for(i=0,longest=0; i<num_of_supported_PICS; i++) {
- for(j=0; j<max_alias; j++) {
- k = strlen(Pics[i]->name[j]);
- if(k>longest)
- longest = k;
- }
+ k = strlen(Pics[i]->name);
+ if(k>longest)
+ longest = k;
}
#if 1
fprintf(stderr, "-----------------------------------------------------\n");
for(i=0; i < num_of_supported_PICS; i++) {
- fprintf(stderr," %s", Pics[i]->name[0]);
- l = longest + 2 - strlen(Pics[i]->name[0]);
+ fprintf(stderr," %s", Pics[i]->name);
+ l = longest + 2 - strlen(Pics[i]->name);
for(k=0; k<l; k++)
fputc(' ',stderr);
fprintf(stderr, "\nPIC14 processors supported:\n");
for(i=0; i < num_of_supported_PICS; i++) {
- for (j = 0; j<max_alias; j++) {
-
- fprintf(stderr,"%s", Pics[i]->name[j]);
- if(col<ncols) {
- l = longest + 2 - strlen(Pics[i]->name[j]);
- for(k=0; k<l; k++)
- fputc(' ',stderr);
+ fprintf(stderr,"%s", Pics[i]->name);
+ if(col<ncols) {
+ l = longest + 2 - strlen(Pics[i]->name);
+ for(k=0; k<l; k++)
+ fputc(' ',stderr);
- col++;
+ col++;
- } else {
- fputc('\n',stderr);
- col = 0;
- }
-
+ } else {
+ fputc('\n',stderr);
+ col = 0;
}
}
*-----------------------------------------------------------------*/
void init_pic(char *pic_type)
{
+ char long_name[PIC14_STRING_LEN];
+
pic = find_device(pic_type);
- if(!pic) {
- if(pic_type)
- fprintf(stderr, "'%s' was not found.\n", pic_type);
- else
- fprintf(stderr, "No processor has been specified (use -pPROCESSOR_NAME)\n");
+ if (pic == NULL) {
+ /* check for shortened "16xxx" form */
+ sprintf(long_name, "16%s", pic_type);
+ pic = find_device(long_name);
+ if (pic == NULL) {
+ if(pic_type != NULL && pic_type[0] != '\0')
+ fprintf(stderr, "'%s' was not found.\n", pic_type);
+ else
+ fprintf(stderr, "No processor has been specified (use -pPROCESSOR_NAME)\n");
- list_valid_pics(7,0);
- exit(1);
+ list_valid_pics(7);
+ exit(1);
+ }
}
}
if(!pic)
return NULL;
- return pic->name[1];
+ return pic->name;
}
/*-----------------------------------------------------------------*
*/
extern AssignedMemory *finalMapping;
-#define PROCESSOR_NAMES 4
/* Processor unique attributes */
typedef struct PIC_device {
- char *name[PROCESSOR_NAMES];/* aliases for the processor name */
+ char *name; /* the processor name */
memRange *ram; /* RAM memory map */
memRange *sfr; /* SFR memory map */
and - Jean-Louis VERN.jlvern@writeme.com (1999)
Bug Fixes - Wojciech Stryjewski wstryj1@tiger.lsu.edu (1999 v2.1.9a)
PIC port - Scott Dattalo scott@dattalo.com (2000)
- cont'd - Raphael Neider rneider@web.de (2005)
+ cont'd - Raphael Neider <rneider AT web.de> (2005)
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
if(!name) {
- name = "p16f877";
+ name = "16f877";
fprintf(stderr,"WARNING: No Pic has been selected, defaulting to %s\n",name);
}
- fprintf (of, "\tlist\tp=%s\n",&name[1]);
+ fprintf (of, "\tlist\tp=%s\n",name);
fprintf (of, "\tradix dec\n");
- fprintf (of, "\tinclude \"%s.inc\"\n",name);
+ fprintf (of, "\tinclude \"p%s.inc\"\n",name);
}
/* Generate interrupt vector table. */
char temp[128];
set *tSet=NULL;
int ret;
+ char * procName;
/*
* link command format:
shash_add(&linkValues, "ofiles", joinStrSet(relFilesSet));
/* LIBRARIES */
+ procName = processor_base_name();
+ if (!procName) {
+ procName = "16f877";
+ }
+
addSet(&libFilesSet, "libsdcc.lib");
- SNPRINTF(&temp[0], 128, "pic%s.lib", port->processor);
+ SNPRINTF(&temp[0], 128, "pic%s.lib", procName);
addSet(&libFilesSet, temp);
shash_add(&linkValues, "libs", joinStrSet(libFilesSet));
Written By - Scott Dattalo scott@dattalo.com
Ported to PIC16 By - Martin Dubuc m.dubuc@rogers.com
- Moved from device.c - Raphael Neider, rneider@web.de
+ Moved from device.c - Raphael Neider <rneider AT web.de>
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
PIC port - Scott Dattalo scott@dattalo.com (2000)
PIC16 port - Martin Dubuc m.dubuc@rogers.com (2002)
- Vangelis Rokas vrokas@otenet.gr (2003,2004,2005)
- Bug Fixes - Raphael Neider rneider@web.de (2004,2005)
+ Bug Fixes - Raphael Neider <rneider AT web.de> (2004,2005)
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
graph.c - implementation of general graphs
- Written By - Raphael Neider rneider@web.de (2005)
+ Written By - Raphael Neider <rneider AT web.de> (2005)
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
graph.h - header file for graph.c
- Written By - Raphael Neider rneider@web.de (2005)
+ Written By - Raphael Neider <rneider AT web.de> (2005)
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
projects / fw / sdcc / commitdiff