--- /dev/null
+#
+# The following turn off LF->CRLF conversion for some files on Windows.
+# these conversions cause syntax errors on MinGW/MSYS. They should not
+# have any effect on non-Windows systems or on Cygwin. Any files that
+# required svn:eof-style=lf under subversion should be included here.
+#
+*.m4 -crlf
+*.ac -crlf
+*.scm -crlf
*.lo
*.py[oc]
*.gz
+*.exe
*.patch
*~
\#*#
.libs
TAGS
*-stamp
+!.gitattributes
!.gitignore
make.log
/configure
then
AC_PROG_F77
AC_F77_LIBRARY_LDFLAGS
- AC_PROG_CC dnl bux fix to restore $ac_ext
fi
+ AC_PROG_CC dnl bux fix to restore $ac_ext
])
long tv_nsec;
};
#endif
+#if HAVE_UNISTD_H
+#include <unistd.h>
+#endif
static inline int nanosleep(const struct timespec *req, struct timespec *rem) { return usleep(req->tv_sec*1000000+req->tv_nsec/1000); }
#endif
;;
esac
+ case $host_os in
+ *mingw* )
+ # Python 2.5 requires ".pyd" instead of ".dll" for extensions
+ PYTHON_LDFLAGS="-shrext .pyd ${PYTHON_LDFLAGS}"
+ esac
+
AC_SUBST(PYTHON_LDFLAGS)
fi
])
-dnl Copyright 2001,2002,2003,2004,2005,2006,2008 Free Software Foundation, Inc.
+dnl Copyright 2001,2002,2003,2004,2005,2006,2008,2009 Free Software Foundation, Inc.
dnl
dnl This file is part of GNU Radio
dnl
AC_CONFIG_FILES([ \
gnuradio-examples/Makefile \
- gnuradio-examples/c++/Makefile \
- gnuradio-examples/python/Makefile \
- gnuradio-examples/grc/Makefile \
- gnuradio-examples/python/apps/hf_explorer/Makefile \
+ gnuradio-examples/c++/Makefile \
+ gnuradio-examples/python/Makefile \
+ gnuradio-examples/grc/Makefile \
+ gnuradio-examples/python/apps/hf_explorer/Makefile \
gnuradio-examples/python/apps/hf_radio/Makefile \
gnuradio-examples/python/apps/Makefile \
gnuradio-examples/python/audio/Makefile \
gnuradio-examples/python/digital/Makefile \
gnuradio-examples/python/digital_voice/Makefile \
- gnuradio-examples/python/digital-bert/Makefile \
+ gnuradio-examples/python/digital-bert/Makefile \
gnuradio-examples/python/mp-sched/Makefile \
gnuradio-examples/python/multi-antenna/Makefile \
gnuradio-examples/python/multi_usrp/Makefile \
gnuradio-examples/python/ofdm/Makefile \
gnuradio-examples/python/pfb/Makefile \
gnuradio-examples/python/usrp/Makefile \
- gnuradio-examples/python/usrp2/Makefile \
+ gnuradio-examples/python/usrp2/Makefile \
])
GRC_BUILD_CONDITIONAL(gnuradio-examples)
dnl Don't do gr-msdd6000 if gnuradio-core skipped
GRC_CHECK_DEPENDENCY(gr-msdd6000, gnuradio-core)
- AC_CHECK_HEADERS(netinet/in.h arpa/inet.h sys/socket.h netdb.h)
+ AC_CHECK_HEADERS(netinet/in.h arpa/inet.h sys/socket.h netdb.h, [], [passed=no])
GRC_BUILD_CONDITIONAL([gr-msdd6000],[
dnl run_tests is created from run_tests.in. Make it executable.
dnl with : if the --with code didn't error out
dnl yes : if the --enable code passed muster and all dependencies are met
dnl no : otherwise
+ if test $passed = yes; then
+ dnl Don't do gruel if guile not available
+ GRC_CHECK_GUILE(gruel)
+ fi
if test $passed != with; then
dnl how and where to find INCLUDES and LA and such
gruel_INCLUDES="\
])
fi
- if x$USB_INCLUDEDIR != x; then
- USB_INCLUDES=-I$USB_INCLUDEDIR
- fi
-
if test x$libusbok = xyes; then
+ if test x$USB_INCLUDEDIR != x; then
+ USB_INCLUDES="-I$USB_INCLUDEDIR"
+ AC_SUBST(USB_INCLUDES)
+ fi
AC_SUBST(USB_LIBS)
ifelse([$2], , :, [$2])
else
$EXTRACT gnuradio-examples/python/usrp/Makefile dist_ourdata_SCRIPTS >>$NAME
$EXTRACT gnuradio-examples/python/usrp2/Makefile dist_ourdata_SCRIPTS >>$NAME
$EXTRACT gnuradio-examples/python/usrp2/Makefile dist_ourdata_DATA >>$NAME
+$EXTRACT gnuradio-examples/grc/Makefile dist_audiodata_DATA >>$NAME
+$EXTRACT gnuradio-examples/grc/Makefile dist_demoddata_DATA >>$NAME
+$EXTRACT gnuradio-examples/grc/Makefile dist_simpledata_DATA >>$NAME
+$EXTRACT gnuradio-examples/grc/Makefile dist_trellisdata_DATA >>$NAME
+$EXTRACT gnuradio-examples/grc/Makefile dist_usrpdata_DATA >>$NAME
+$EXTRACT gnuradio-examples/grc/Makefile dist_xmlrpcdata_DATA >>$NAME
# gnuradio-pager
NAME=debian/gnuradio-pager.install
$EXTRACT grc/base/Makefile ourpython_PYTHON >>$NAME
$EXTRACT grc/base/Makefile dist_ourdata_DATA >>$NAME
$EXTRACT grc/blocks/Makefile dist_ourdata_DATA >>$NAME
-$EXTRACT grc/examples/Makefile dist_audiodata_DATA >>$NAME
-$EXTRACT grc/examples/Makefile dist_simpledata_DATA >>$NAME
-$EXTRACT grc/examples/Makefile dist_trellisdata_DATA >>$NAME
-$EXTRACT grc/examples/Makefile dist_usrpdata_DATA >>$NAME
-$EXTRACT grc/examples/Makefile dist_xmlrpcdata_DATA >>$NAME
$EXTRACT grc/freedesktop/Makefile dist_ourdata_DATA >>$NAME
$EXTRACT grc/freedesktop/Makefile dist_bin_SCRIPTS >>$NAME
$EXTRACT grc/grc_gnuradio/Makefile root_python_PYTHON >>$NAME
Description: GNU Radio Utilities
This package provides commonly used utilities for GNU Radio
-Package: gnuradio-examples
-Architecture: any
-Depends: ${python:Depends}, python-gnuradio-core
-Provides: ${python:Provides}
-Recommends: python-gnuradio-wxgui, python-gnuradio
-Section: comm
-XB-Python-Version: ${python:Versions}
-Description: GNU Radio Example Programs
- This package provides examples of GNU Radio usage using Python.
-
Package: gnuradio-pager
Architecture: any
Depends: ${python:Depends}, ${shlibs:Depends}, python-gnuradio-usrp
Description: The GNU Radio Companion
GRC is a graphical flowgraph editor for the GNU Software Radio
+Package: gnuradio-examples
+Architecture: any
+Depends: ${python:Depends}, python-gnuradio-core, gnuradio-companion
+Provides: ${python:Provides}
+Recommends: python-gnuradio-wxgui, python-gnuradio
+Section: comm
+XB-Python-Version: ${python:Versions}
+Description: GNU Radio Example Programs
+ This package provides examples of GNU Radio usage using Python.
+
################################################################################
# Documentation packages #
################################################################################
gr_complex_to_interleaved_short.cc \
gr_complex_to_xxx.cc \
gr_conjugate_cc.cc \
+ gr_copy.cc \
gr_constellation_decoder_cb.cc \
gr_correlate_access_code_bb.cc \
gr_costas_loop_cc.cc \
gr_complex_to_xxx.h \
gr_conjugate_cc.h \
gr_constellation_decoder_cb.h \
+ gr_copy.h \
gr_correlate_access_code_bb.h \
gr_costas_loop_cc.h \
gr_count_bits.h \
gr_complex_to_xxx.i \
gr_conjugate_cc.i \
gr_constellation_decoder_cb.i \
+ gr_copy.i \
gr_correlate_access_code_bb.i \
gr_costas_loop_cc.i \
gr_cpfsk_bc.i \
/* -*- c++ -*- */
/*
- * Copyright 2004,2005,2006,2007,2008 Free Software Foundation, Inc.
+ * Copyright 2004,2005,2006,2007,2008,2009 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
#include <gr_stretch_ff.h>
#include <gr_wavelet_ff.h>
#include <gr_wvps_ff.h>
-
+#include <gr_copy.h>
%}
%include "gr_nop.i"
%include "gr_stretch_ff.i"
%include "gr_wavelet_ff.i"
%include "gr_wvps_ff.i"
+%include "gr_copy.i"
--- /dev/null
+/* -*- c++ -*- */
+/*
+ * Copyright 2006,2009 Free Software Foundation, Inc.
+ *
+ * This file is part of GNU Radio
+ *
+ * GNU Radio is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+ *
+ * GNU Radio is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with GNU Radio; see the file COPYING. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <gr_copy.h>
+#include <gr_io_signature.h>
+#include <string.h>
+
+gr_copy_sptr
+gr_make_copy(size_t itemsize)
+{
+ return gnuradio::get_initial_sptr(new gr_copy(itemsize));
+}
+
+gr_copy::gr_copy(size_t itemsize)
+ : gr_block ("copy",
+ gr_make_io_signature (1, 1, itemsize),
+ gr_make_io_signature (1, 1, itemsize)),
+ d_itemsize(itemsize),
+ d_enabled(true)
+{
+}
+
+bool
+gr_copy::check_topology(int ninputs, int noutputs)
+{
+ return ninputs == noutputs;
+}
+
+int
+gr_copy::general_work(int noutput_items,
+ gr_vector_int &ninput_items,
+ gr_vector_const_void_star &input_items,
+ gr_vector_void_star &output_items)
+{
+ const uint8_t *in = (const uint8_t *) input_items[0];
+ uint8_t *out = (uint8_t *) output_items[0];
+
+ int n = std::min<int>(ninput_items[0], noutput_items);
+ int j = 0;
+
+ if (d_enabled) {
+ memcpy(out, in, n*d_itemsize);
+ j = n;
+ }
+
+ consume_each(n);
+ return j;
+}
--- /dev/null
+/* -*- c++ -*- */
+/*
+ * Copyright 2006,2009 Free Software Foundation, Inc.
+ *
+ * This file is part of GNU Radio
+ *
+ * GNU Radio is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+ *
+ * GNU Radio is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with GNU Radio; see the file COPYING. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#ifndef INCLUDED_GR_COPY_H
+#define INCLUDED_GR_COPY_H
+
+#include <gr_block.h>
+
+class gr_copy;
+typedef boost::shared_ptr<gr_copy> gr_copy_sptr;
+
+gr_copy_sptr gr_make_copy(size_t itemsize);
+
+/*!
+ * \brief output[i] = input[i]
+ * \ingroup misc_blk
+ *
+ * When enabled (default), this block copies its input to its output.
+ * When disabled, this block drops its input on the floor.
+ *
+ */
+class gr_copy : public gr_block
+{
+ size_t d_itemsize;
+ bool d_enabled;
+
+ friend gr_copy_sptr gr_make_copy(size_t itemsize);
+ gr_copy(size_t itemsize);
+
+ public:
+
+ bool check_topology(int ninputs, int noutputs);
+
+ void set_enabled(bool enable) { d_enabled = enable; }
+ bool enabled() const { return d_enabled;}
+
+ int general_work(int noutput_items,
+ gr_vector_int &ninput_items,
+ gr_vector_const_void_star &input_items,
+ gr_vector_void_star &output_items);
+};
+
+#endif
--- /dev/null
+/* -*- c++ -*- */
+/*
+ * Copyright 2006,2009 Free Software Foundation, Inc.
+ *
+ * This file is part of GNU Radio
+ *
+ * GNU Radio is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+ *
+ * GNU Radio is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with GNU Radio; see the file COPYING. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+GR_SWIG_BLOCK_MAGIC(gr,copy)
+
+gr_copy_sptr gr_make_copy(size_t itemsize);
+
+class gr_copy : public gr_block
+{
+ private:
+ gr_copy(size_t itemsize);
+
+public:
+
+ void set_enabled(bool enabled);
+ bool enabled();
+};
: gr_sync_block ("histo_sink_f", gr_make_io_signature (1, 1, sizeof (float)), gr_make_io_signature (0, 0, 0)),
d_msgq (msgq), d_num_bins(11), d_frame_size(1000), d_sample_count(0), d_bins(NULL), d_samps(NULL)
{
- pthread_mutex_init(&d_mutex, 0);
//allocate arrays and clear
set_num_bins(d_num_bins);
set_frame_size(d_frame_size);
gr_histo_sink_f::~gr_histo_sink_f (void)
{
- pthread_mutex_destroy(&d_mutex);
delete [] d_samps;
delete [] d_bins;
}
gr_vector_void_star &output_items)
{
const float *in = (const float *) input_items[0];
- pthread_mutex_lock(&d_mutex);
+ gruel::scoped_lock guard(d_mutex); // hold mutex for duration of this function
for (unsigned int i = 0; i < (unsigned int)noutput_items; i++){
d_samps[d_sample_count] = in[i];
d_sample_count++;
clear();
}
}
- pthread_mutex_unlock(&d_mutex);
return noutput_items;
}
**************************************************/
void
gr_histo_sink_f::set_frame_size(unsigned int frame_size){
- pthread_mutex_lock(&d_mutex);
+ gruel::scoped_lock guard(d_mutex); // hold mutex for duration of this function
d_frame_size = frame_size;
/* allocate a new sample array */
delete [] d_samps;
d_samps = new float[d_frame_size];
clear();
- pthread_mutex_unlock(&d_mutex);
}
void
gr_histo_sink_f::set_num_bins(unsigned int num_bins){
- pthread_mutex_lock(&d_mutex);
+ gruel::scoped_lock guard(d_mutex); // hold mutex for duration of this function
d_num_bins = num_bins;
/* allocate a new bin array */
delete [] d_bins;
d_bins = new unsigned int[d_num_bins];
clear();
- pthread_mutex_unlock(&d_mutex);
}
#include <gr_sync_block.h>
#include <gr_msg_queue.h>
-#include <pthread.h>
+#include <gruel/thread.h>
class gr_histo_sink_f;
typedef boost::shared_ptr<gr_histo_sink_f> gr_histo_sink_f_sptr;
unsigned int d_sample_count;
unsigned int *d_bins;
float *d_samps;
- pthread_mutex_t d_mutex;
+ gruel::mutex d_mutex;
friend gr_histo_sink_f_sptr gr_make_histo_sink_f (gr_msg_queue_sptr msgq);
gr_histo_sink_f (gr_msg_queue_sptr msgq);
#
-# Copyright 2003,2004,2008 Free Software Foundation, Inc.
+# Copyright 2003,2004,2008,2009 Free Software Foundation, Inc.
#
# This file is part of GNU Radio
#
noinst_LTLIBRARIES = libmissing.la
-libmissing_la_SOURCES = \
- bug_work_around_8.cc \
+libmissing_la_common_SOURCES = \
+ bug_work_around_8.cc
+
+powerpc_CODE = \
posix_memalign.cc
+
+if MD_CPU_powerpc
+libmissing_la_SOURCES = $(libmissing_la_common_SOURCES) $(powerpc_CODE)
+else
+libmissing_la_SOURCES = $(libmissing_la_common_SOURCES)
+endif
#
-# Copyright 2005,2006,2007 Free Software Foundation, Inc.
+# Copyright 2005,2006,2007,2009 Free Software Foundation, Inc.
#
# This file is part of GNU Radio
#
#
-# Copyright 2005,2006,2007 Free Software Foundation, Inc.
+# Copyright 2005,2006,2007,2009 Free Software Foundation, Inc.
#
# This file is part of GNU Radio
#
self._setup_logging()
# Connect & Initialize base class
- self.connect(self, self.pre_scaler, self.agc, self.rrc_filter, #self.receiver,
+ self.connect(self, self.pre_scaler, self.agc, self.rrc_filter, self.receiver,
self.diffdec, self.slicer, self.symbol_mapper, self.unpack, self)
def samples_per_symbol(self):
qa_cma_equalizer.py \
qa_complex_to_xxx.py \
qa_constellation_decoder_cb.py \
+ qa_copy.py \
qa_correlate_access_code.py \
qa_delay.py \
qa_diff_encoder.py \
--- /dev/null
+#!/usr/bin/env python
+#
+# Copyright 2009 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+from gnuradio import gr, gr_unittest
+
+class test_copy(gr_unittest.TestCase):
+
+ def setUp (self):
+ self.tb = gr.top_block ()
+
+ def tearDown (self):
+ self.tb = None
+
+ def test_copy (self):
+ src_data = (1, 2, 3, 4, 5, 6, 7, 8, 9, 10)
+ expected_result = (1, 2, 3, 4, 5, 6, 7, 8, 9, 10)
+ src = gr.vector_source_b(src_data)
+ op = gr.copy(gr.sizeof_char)
+ dst = gr.vector_sink_b()
+ self.tb.connect(src, op, dst)
+ self.tb.run()
+ dst_data = dst.data()
+ self.assertEqual(expected_result, dst_data)
+
+ def test_copy_drop (self):
+ src_data = (1, 2, 3, 4, 5, 6, 7, 8, 9, 10)
+ expected_result = ()
+ src = gr.vector_source_b(src_data)
+ op = gr.copy(gr.sizeof_char)
+ op.set_enabled(False)
+ dst = gr.vector_sink_b()
+ self.tb.connect(src, op, dst)
+ self.tb.run()
+ dst_data = dst.data()
+ self.assertEqual(expected_result, dst_data)
+
+
+if __name__ == '__main__':
+ gr_unittest.main ()
libgnuradio_atsc_la_LIBADD = \
$(GNURADIO_CORE_LA)
+libgnuradio_atsc_la_LDFLAGS = \
+ $(NO_UNDEFINED)
+
noinst_LTLIBRARIES = libgnuradio-atsc-qa.la
libgnuradio_atsc_qa_la_SOURCES = \
libgnuradio_atsc_qa_la_LIBADD = \
$(GNURADIO_CORE_LA)
+libgnuradio_atsc_qa_la_LDFLAGS = \
+ $(NO_UNDEFINED)
+
# These headers get installed in ${prefix}/include/gnuradio
grinclude_HEADERS = \
# Boston, MA 02110-1301, USA.
#
+##################################################
+# conditional disconnections of wx flow graph
+##################################################
+import wx
+from gnuradio import gr
+
+class wxgui_hb(object):
+ """
+ The wxgui hier block helper/wrapper class:
+ A hier block should inherit from this class to make use of the wxgui connect method.
+ To use, call wxgui_connect in place of regular connect; self.win must be defined.
+ The implementation will conditionally enable the copy block after the source (self).
+ This condition depends on weather or not the window is visible with the parent notebooks.
+ This condition will be re-checked on every ui update event.
+ """
+
+ def wxgui_connect(self, *points):
+ """
+ Use wxgui connect when the first point is the self source of the hb.
+ The win property of this object should be set to the wx window.
+ When this method tries to connect self to the next point,
+ it will conditionally make this connection based on the visibility state.
+ All other points will be connected normally.
+ """
+ try:
+ assert points[0] == self or points[0][0] == self
+ copy = gr.copy(self._hb.input_signature().sizeof_stream_item(0))
+ handler = self._handler_factory(copy.set_enabled)
+ handler(False) #initially disable the copy block
+ self._bind_to_visible_event(win=self.win, handler=handler)
+ points = list(points)
+ points.insert(1, copy) #insert the copy block into the chain
+ except (AssertionError, IndexError): pass
+ self.connect(*points) #actually connect the blocks
+
+ @staticmethod
+ def _handler_factory(handler):
+ """
+ Create a function that will cache the visibility flag,
+ and only call the handler when that flag changes.
+ @param handler the function to call on a change
+ @return a function of 1 argument
+ """
+ cache = [None]
+ def callback(visible):
+ if cache[0] == visible: return
+ cache[0] = visible
+ #print visible, handler
+ handler(visible)
+ return callback
+
+ @staticmethod
+ def _bind_to_visible_event(win, handler):
+ """
+ Bind a handler to a window when its visibility changes.
+ Specifically, call the handler when the window visibility changes.
+ This condition is checked on every update ui event.
+ @param win the wx window
+ @param handler a function of 1 param
+ """
+ #is the window visible in the hierarchy
+ def is_wx_window_visible(my_win):
+ while True:
+ parent = my_win.GetParent()
+ if not parent: return True #reached the top of the hierarchy
+ #if we are hidden, then finish, otherwise keep traversing up
+ if isinstance(parent, wx.Notebook) and parent.GetCurrentPage() != my_win: return False
+ my_win = parent
+ #call the handler, the arg is shown or not
+ def handler_factory(my_win, my_handler):
+ return lambda *args: my_handler(is_wx_window_visible(my_win))
+ handler = handler_factory(win, handler)
+ #bind the handler to all the parent notebooks
+ win.Bind(wx.EVT_UPDATE_UI, handler)
+
+##################################################
+# Helpful Functions
+##################################################
+
#A macro to apply an index to a key
index_key = lambda key, i: "%s_%d"%(key, i+1)
##################################################
# Constellation sink block (wrapper for old wxgui)
##################################################
-class const_sink_c(gr.hier_block2):
+class const_sink_c(gr.hier_block2, common.wxgui_hb):
"""
A constellation block with a gui window.
"""
agc = gr.feedforward_agc_cc(16, 1)
msgq = gr.msg_queue(2)
sink = gr.message_sink(gr.sizeof_gr_complex*const_size, msgq, True)
- #connect
- self.connect(self, self._costas, self._retime, agc, sd, sink)
#controller
def setter(p, k, x): p[k] = x
self.controller = pubsub()
sample_rate_key=SAMPLE_RATE_KEY,
)
common.register_access_methods(self, self.win)
+ #connect
+ self.wxgui_connect(self, self._costas, self._retime, agc, sd, sink)
##################################################
# FFT sink block (wrapper for old wxgui)
##################################################
-class _fft_sink_base(gr.hier_block2):
+class _fft_sink_base(gr.hier_block2, common.wxgui_hb):
"""
An fft block with real/complex inputs and a gui window.
"""
)
msgq = gr.msg_queue(2)
sink = gr.message_sink(gr.sizeof_float*fft_size, msgq, True)
- #connect
- self.connect(self, fft, sink)
#controller
self.controller = pubsub()
self.controller.subscribe(AVERAGE_KEY, fft.set_average)
common.register_access_methods(self, self.win)
setattr(self.win, 'set_baseband_freq', getattr(self, 'set_baseband_freq')) #BACKWARDS
setattr(self.win, 'set_peak_hold', getattr(self, 'set_peak_hold')) #BACKWARDS
+ #connect
+ self.wxgui_connect(self, fft, sink)
class fft_sink_f(_fft_sink_base):
_fft_chain = blks2.logpwrfft_f
##################################################
# histo sink block (wrapper for old wxgui)
##################################################
-class histo_sink_f(gr.hier_block2):
+class histo_sink_f(gr.hier_block2, common.wxgui_hb):
"""
A histogram block and a gui window.
"""
histo = gr.histo_sink_f(msgq)
histo.set_num_bins(num_bins)
histo.set_frame_size(frame_size)
- #connect
- self.connect(self, histo)
#controller
self.controller = pubsub()
self.controller.subscribe(NUM_BINS_KEY, histo.set_num_bins)
msg_key=MSG_KEY,
)
common.register_access_methods(self, self.win)
+ #connect
+ self.wxgui_connect(self, histo)
# ----------------------------------------------------------------
# Standalone test app
##################################################
# Number sink block (wrapper for old wxgui)
##################################################
-class _number_sink_base(gr.hier_block2):
+class _number_sink_base(gr.hier_block2, common.wxgui_hb):
"""
An decimator block with a number window display
"""
avg = gr.single_pole_iir_filter_cc(1.0)
msgq = gr.msg_queue(2)
sink = gr.message_sink(self._item_size, msgq, True)
- #connect
- self.connect(self, sd, mult, add, avg, sink)
#controller
self.controller = pubsub()
self.controller.subscribe(SAMPLE_RATE_KEY, sd.set_sample_rate)
common.register_access_methods(self, self.controller)
#backwards compadibility
self.set_show_gauge = self.win.show_gauges
+ #connect
+ self.wxgui_connect(self, sd, mult, add, avg, sink)
class number_sink_f(_number_sink_base):
_item_size = gr.sizeof_float
#bind plotter mouse events
self._plotter.Bind(wx.EVT_MOTION, lambda evt: self.enqueue(evt.GetPosition()))
self._plotter.Bind(wx.EVT_LEAVE_WINDOW, lambda evt: self.enqueue(None))
+ self._plotter.Bind(wx.EVT_RIGHT_DOWN, lambda evt: plotter.enable_point_label(not plotter.enable_point_label()))
#start the thread
threading.Thread.__init__(self)
self.start()
TICK_LABEL_PADDING = 5
TITLE_LABEL_PADDING = 7
POINT_LABEL_FONT_SIZE = 8
-POINT_LABEL_COLOR_SPEC = (1, 1, .5)
+POINT_LABEL_COLOR_SPEC = (1, 1, 0.5, 0.75)
POINT_LABEL_PADDING = 3
+POINT_LABEL_OFFSET = 10
GRID_LINE_DASH_LEN = 4
##################################################
if not label_str: return
txt = gltext.Text(label_str, font_size=POINT_LABEL_FONT_SIZE)
w, h = txt.get_size()
+ #enable transparency
+ GL.glEnable(GL.GL_BLEND)
+ GL.glBlendFunc(GL.GL_SRC_ALPHA, GL.GL_ONE_MINUS_SRC_ALPHA)
#draw rect + text
- GL.glColor3f(*POINT_LABEL_COLOR_SPEC)
- if x > self.width/2: x -= w+2*POINT_LABEL_PADDING
+ GL.glColor4f(*POINT_LABEL_COLOR_SPEC)
+ if x > self.width/2: x -= w+2*POINT_LABEL_PADDING + POINT_LABEL_OFFSET
+ else: x += POINT_LABEL_OFFSET
self._draw_rect(x, y-h-2*POINT_LABEL_PADDING, w+2*POINT_LABEL_PADDING, h+2*POINT_LABEL_PADDING)
txt.draw_text(wx.Point(x+POINT_LABEL_PADDING, y-h-POINT_LABEL_PADDING))
Mute the low pass filter to disable ac coupling.
"""
- def __init__(self, controller, ac_couple_key, ac_couple, sample_rate_key):
+ def __init__(self, controller, ac_couple_key, sample_rate_key):
gr.hier_block2.__init__(
self,
"ac_couple",
controller.subscribe(ac_couple_key, lambda x: mute.set_mute(not x))
controller.subscribe(sample_rate_key, lambda x: lpf.set_taps(0.05))
#initialize
- controller[ac_couple_key] = ac_couple
+ controller[ac_couple_key] = controller[ac_couple_key]
controller[sample_rate_key] = controller[sample_rate_key]
##################################################
# Scope sink block (wrapper for old wxgui)
##################################################
-class _scope_sink_base(gr.hier_block2):
+class _scope_sink_base(gr.hier_block2, common.wxgui_hb):
"""
A scope block with a gui window.
"""
self.controller.publish(TRIGGER_SLOPE_KEY, scope.get_trigger_slope)
self.controller.subscribe(TRIGGER_CHANNEL_KEY, scope.set_trigger_channel)
self.controller.publish(TRIGGER_CHANNEL_KEY, scope.get_trigger_channel)
- #connect
- if self._real:
- for i in range(num_inputs):
- self.connect(
- (self, i),
- ac_couple_block(self.controller, common.index_key(AC_COUPLE_KEY, i), ac_couple, SAMPLE_RATE_KEY),
- (scope, i),
- )
- else:
- for i in range(num_inputs):
- c2f = gr.complex_to_float()
- self.connect((self, i), c2f)
- for j in range(2):
- self.connect(
- (c2f, j),
- ac_couple_block(self.controller, common.index_key(AC_COUPLE_KEY, 2*i+j), ac_couple, SAMPLE_RATE_KEY),
- (scope, 2*i+j),
- )
- num_inputs *= 2
+ actual_num_inputs = self._real and num_inputs or num_inputs*2
+ #init ac couple
+ for i in range(actual_num_inputs):
+ self.controller[common.index_key(AC_COUPLE_KEY, i)] = ac_couple
#start input watcher
common.input_watcher(msgq, self.controller, MSG_KEY)
#create window
size=size,
title=title,
frame_rate=frame_rate,
- num_inputs=num_inputs,
+ num_inputs=actual_num_inputs,
sample_rate_key=SAMPLE_RATE_KEY,
t_scale=t_scale,
v_scale=v_scale,
msg_key=MSG_KEY,
)
common.register_access_methods(self, self.win)
+ #connect
+ if self._real:
+ for i in range(num_inputs):
+ self.wxgui_connect(
+ (self, i),
+ ac_couple_block(self.controller, common.index_key(AC_COUPLE_KEY, i), SAMPLE_RATE_KEY),
+ (scope, i),
+ )
+ else:
+ for i in range(num_inputs):
+ c2f = gr.complex_to_float()
+ self.wxgui_connect((self, i), c2f)
+ for j in range(2):
+ self.connect(
+ (c2f, j),
+ ac_couple_block(self.controller, common.index_key(AC_COUPLE_KEY, 2*i+j), SAMPLE_RATE_KEY),
+ (scope, 2*i+j),
+ )
class scope_sink_f(_scope_sink_base):
_item_size = gr.sizeof_float
##################################################
# Waterfall sink block (wrapper for old wxgui)
##################################################
-class _waterfall_sink_base(gr.hier_block2):
+class _waterfall_sink_base(gr.hier_block2, common.wxgui_hb):
"""
An fft block with real/complex inputs and a gui window.
"""
)
msgq = gr.msg_queue(2)
sink = gr.message_sink(gr.sizeof_float*fft_size, msgq, True)
- #connect
- self.connect(self, fft, sink)
#controller
self.controller = pubsub()
self.controller.subscribe(AVERAGE_KEY, fft.set_average)
)
common.register_access_methods(self, self.win)
setattr(self.win, 'set_baseband_freq', getattr(self, 'set_baseband_freq')) #BACKWARDS
+ #connect
+ self.wxgui_connect(self, fft, sink)
class waterfall_sink_f(_waterfall_sink_base):
_fft_chain = blks2.logpwrfft_f
gr_complex_to_real.xml \
gr_conjugate_cc.xml \
gr_constellation_decoder_cb.xml \
+ gr_copy.xml \
gr_correlate_access_code_bb.xml \
gr_costas_loop_cc.xml \
gr_cpfsk_bc.xml \
gr_simple_squelch_cc.xml \
gr_single_pole_iir_filter_xx.xml \
gr_skiphead.xml \
+ gr_stream_mux.xml \
gr_stream_to_streams.xml \
gr_stream_to_vector.xml \
gr_streams_to_stream.xml \
<block>gr_stream_to_vector</block>
<block>gr_vector_to_stream</block>
-
+
<block>blks2_stream_to_vector_decimator</block>
+
+ <block>gr_stream_mux</block>
</cat>
<cat>
<name>Misc Conversions</name>
<block>gr_skiphead</block>
<block>gr_kludge_copy</block>
+ <block>gr_copy</block>
<block>gr_nop</block>
<block>xmlrpc_server</block>
<value>2</value>
<type>int</type>
</param>
+ <param>
+ <name>Num Ports</name>
+ <key>num_ports</key>
+ <value>1</value>
+ <type>int</type>
+ </param>
+ <check>$num_ports > 0</check>
<sink>
<name>in</name>
<type>$in_type</type>
+ <nports>$num_ports</nports>
</sink>
<source>
<name>out</name>
<type>$out_type</type>
+ <nports>$num_ports</nports>
</source>
</block>
--- /dev/null
+<?xml version="1.0"?>
+<!--
+###################################################
+##Copy
+###################################################
+ -->
+<block>
+ <name>Copy</name>
+ <key>gr_copy</key>
+ <import>from gnuradio import gr</import>
+ <make>gr.copy($type.size*$vlen)
+self.$(id).set_enabled($enabled)</make>
+ <callback>set_enabled($enabled)</callback>
+ <param>
+ <name>Type</name>
+ <key>type</key>
+ <type>enum</type>
+ <option>
+ <name>Complex</name>
+ <key>complex</key>
+ <opt>size:gr.sizeof_gr_complex</opt>
+ </option>
+ <option>
+ <name>Float</name>
+ <key>float</key>
+ <opt>size:gr.sizeof_float</opt>
+ </option>
+ <option>
+ <name>Int</name>
+ <key>int</key>
+ <opt>size:gr.sizeof_int</opt>
+ </option>
+ <option>
+ <name>Short</name>
+ <key>short</key>
+ <opt>size:gr.sizeof_short</opt>
+ </option>
+ <option>
+ <name>Byte</name>
+ <key>byte</key>
+ <opt>size:gr.sizeof_char</opt>
+ </option>
+ </param>
+ <param>
+ <name>Enabled</name>
+ <key>enabled</key>
+ <value>True</value>
+ <type>bool</type>
+ <option>
+ <name>Enabled</name>
+ <key>True</key>
+ </option>
+ <option>
+ <name>Disabled</name>
+ <key>False</key>
+ </option>
+ </param>
+ <param>
+ <name>Vec Length</name>
+ <key>vlen</key>
+ <value>1</value>
+ <type>int</type>
+ </param>
+ <check>$vlen > 0</check>
+ <sink>
+ <name>in</name>
+ <type>$type</type>
+ <vlen>$vlen</vlen>
+ </sink>
+ <source>
+ <name>out</name>
+ <type>$type</type>
+ <vlen>$vlen</vlen>
+ </source>
+</block>
<value>0</value>
<type>int</type>
</param>
+ <param>
+ <name>Num Ports</name>
+ <key>num_ports</key>
+ <value>1</value>
+ <type>int</type>
+ </param>
<param>
<name>Vec Length</name>
<key>vlen</key>
<value>1</value>
<type>int</type>
</param>
+ <check>$num_ports > 0</check>
<check>$vlen > 0</check>
<sink>
<name>in</name>
<type>$type</type>
<vlen>$vlen</vlen>
+ <nports>$num_ports</nports>
</sink>
<source>
<name>out</name>
<type>$type</type>
<vlen>$vlen</vlen>
+ <nports>$num_ports</nports>
</source>
</block>
###################################################
-->
<block>
- <name>Copy</name>
+ <name>Kludge Copy</name>
<key>gr_kludge_copy</key>
<import>from gnuradio import gr</import>
<make>gr.kludge_copy($type.size*$vlen)</make>
<opt>size:gr.sizeof_char</opt>
</option>
</param>
+ <param>
+ <name>Num Ports</name>
+ <key>num_ports</key>
+ <value>1</value>
+ <type>int</type>
+ </param>
<param>
<name>Vec Length</name>
<key>vlen</key>
<value>1</value>
<type>int</type>
</param>
+ <check>$num_ports > 0</check>
<check>$vlen > 0</check>
<sink>
<name>in</name>
<type>$type</type>
<vlen>$vlen</vlen>
+ <nports>$num_ports</nports>
</sink>
<source>
<name>out</name>
<type>$type</type>
<vlen>$vlen</vlen>
+ <nports>$num_ports</nports>
</source>
</block>
<opt>size:gr.sizeof_char</opt>
</option>
</param>
+ <param>
+ <name>Num Ports</name>
+ <key>num_ports</key>
+ <value>1</value>
+ <type>int</type>
+ </param>
<param>
<name>Vec Length</name>
<key>vlen</key>
<value>1</value>
<type>int</type>
</param>
+ <check>$num_ports > 0</check>
<check>$vlen > 0</check>
<sink>
<name>in</name>
<type>$type</type>
<vlen>$vlen</vlen>
+ <nports>$num_ports</nports>
</sink>
<source>
<name>out</name>
<type>$type</type>
<vlen>$vlen</vlen>
+ <nports>$num_ports</nports>
</source>
</block>
<param>
<name>Endianness</name>
<key>endianness</key>
- <type>enum</type>
+ <type>int</type>
<option>
<name>MSB</name>
<key>gr.GR_MSB_FIRST</key>
<key>gr.GR_LSB_FIRST</key>
</option>
</param>
+ <param>
+ <name>Num Ports</name>
+ <key>num_ports</key>
+ <value>1</value>
+ <type>int</type>
+ </param>
+ <check>$num_ports > 0</check>
<sink>
<name>in</name>
<type>$type</type>
+ <nports>$num_ports</nports>
</sink>
<source>
<name>out</name>
<type>$type</type>
+ <nports>$num_ports</nports>
</source>
</block>
--- /dev/null
+<?xml version="1.0"?>
+<!--
+###################################################
+##Stream Mux:
+## all types, many inputs, only one output
+###################################################
+ -->
+<block>
+ <name>Stream Mux</name>
+ <key>gr_stream_mux</key>
+ <import>from gnuradio import gr</import>
+ <make>gr.stream_mux($type.size*$vlen, $lengths)</make>
+ <param>
+ <name>Type</name>
+ <key>type</key>
+ <type>enum</type>
+ <option>
+ <name>Complex</name>
+ <key>complex</key>
+ <opt>size:gr.sizeof_gr_complex</opt>
+ </option>
+ <option>
+ <name>Float</name>
+ <key>float</key>
+ <opt>size:gr.sizeof_float</opt>
+ </option>
+ <option>
+ <name>Int</name>
+ <key>int</key>
+ <opt>size:gr.sizeof_int</opt>
+ </option>
+ <option>
+ <name>Short</name>
+ <key>short</key>
+ <opt>size:gr.sizeof_short</opt>
+ </option>
+ <option>
+ <name>Byte</name>
+ <key>byte</key>
+ <opt>size:gr.sizeof_char</opt>
+ </option>
+ </param>
+ <param>
+ <name>Lengths</name>
+ <key>lengths</key>
+ <value>1, 1</value>
+ <type>int_vector</type>
+ </param>
+ <param>
+ <name>Num Inputs</name>
+ <key>num_inputs</key>
+ <value>2</value>
+ <type>int</type>
+ </param>
+ <param>
+ <name>Vec Length</name>
+ <key>vlen</key>
+ <value>1</value>
+ <type>int</type>
+ </param>
+ <check>$num_inputs > 0</check>
+ <check>$num_inputs == len($lengths)</check>
+ <check>$vlen > 0</check>
+ <sink>
+ <name>in</name>
+ <type>$type</type>
+ <vlen>$vlen</vlen>
+ <nports>$num_inputs</nports>
+ </sink>
+ <source>
+ <name>out</name>
+ <type>$type</type>
+ <vlen>$vlen</vlen>
+ </source>
+</block>
<param>
<name>Endianness</name>
<key>endianness</key>
- <type>enum</type>
+ <type>int</type>
<option>
<name>MSB</name>
<key>gr.GR_MSB_FIRST</key>
<key>gr.GR_LSB_FIRST</key>
</option>
</param>
+ <param>
+ <name>Num Ports</name>
+ <key>num_ports</key>
+ <value>1</value>
+ <type>int</type>
+ </param>
+ <check>$num_ports > 0</check>
<sink>
<name>in</name>
<type>$type</type>
+ <nports>$num_ports</nports>
</sink>
<source>
<name>out</name>
<type>$type</type>
+ <nports>$num_ports</nports>
</source>
</block>
renderer = gtk.CellRendererText()
column = gtk.TreeViewColumn('Blocks', renderer, text=NAME_INDEX)
self.treeview.append_column(column)
+ #setup the search
+ self.treeview.set_enable_search(True)
+ self.treeview.set_search_equal_func(self._handle_search)
#try to enable the tooltips (available in pygtk 2.12 and above)
try: self.treeview.set_tooltip_column(DOC_INDEX)
except: pass
############################################################
## Event Handlers
############################################################
+ def _handle_search(self, model, column, key, iter):
+ #determine which blocks match the search key
+ blocks = self.get_flow_graph().get_parent().get_blocks()
+ matching_blocks = filter(lambda b: key in b.get_key() or key in b.get_name().lower(), blocks)
+ #remove the old search category
+ try: self.treestore.remove(self._categories.pop((self._search_category, )))
+ except (KeyError, AttributeError): pass #nothing to remove
+ #create a search category
+ if not matching_blocks: return
+ self._search_category = 'Search: %s'%key
+ for block in matching_blocks: self.add_block(self._search_category, block)
+ #expand the search category
+ path = self.treestore.get_path(self._categories[(self._search_category, )])
+ self.treeview.collapse_all()
+ self.treeview.expand_row(path, open_all=False)
+
def _handle_drag_get_data(self, widget, drag_context, selection_data, info, time):
"""
Handle a drag and drop by setting the key to the selection object.
#extract descriptions
comp_name = extract_txt(xml.xpath(DOXYGEN_NAME_XPATH)[0]).strip()
comp_name = ' --- ' + comp_name + ' --- '
- if re.match('(gr|usrp2|trellis)_.*', key):
+ if re.match('(gr|usrp2|trellis|noaa)_.*', key):
brief_desc = extract_txt(xml.xpath(DOXYGEN_BRIEFDESC_GR_XPATH)[0]).strip()
detailed_desc = extract_txt(xml.xpath(DOXYGEN_DETAILDESC_GR_XPATH)[0]).strip()
else:
* remove blocks in block tree covered by doxygen
* param editor, expand entry boxes in focus
* change param dialog to panel within main window
-* search for blocks in category window
* gui grid editor for configuring grid params/placing wxgui plots and controls
* drag from one port to another to connect
* per parameter docs
# ----------------------------------------------------------------
test_gruel_SOURCES = test_gruel.cc
-test_gruel_LDADD = libgruel.la pmt/libpmt-qa.la
+test_gruel_LDADD = pmt/libpmt-qa.la libgruel.la
#!/usr/bin/env python
#
-# Copyright 2005,2007 Free Software Foundation, Inc.
-#
+# Copyright 2005,2007,2009 Free Software Foundation, Inc.
+#
# This file is part of GNU Radio
-#
+#
# GNU Radio is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
-#
+#
# GNU Radio is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License
# along with GNU Radio; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
-#
+#
from usrpm.usrp_prims import *
from optparse import OptionParser
'lftx' : ((LF_TX, 0x0000), None),
'lfrx' : (None, (LF_RX, 0x0000)),
'wbx_lo' : ((WBX_LO_TX, 0x0000), (WBX_LO_RX, 0x0000)),
+ 'wbx_ng' : ((WBX_NG_TX, 0x0000), (WBX_NG_RX, 0x0000)),
'xcvr2450' : ((XCVR2450_TX, 0x0000), (XCVR2450_RX, 0x0000)),
'experimental_tx' : ((EXPERIMENTAL_TX, 0x0000), None),
'experimental_rx' : (None, (EXPERIMENTAL_RX, 0x0000)),
if not e:
print "%s: no d'board, skipped" % (slot_name,)
return True
-
+
if not force and (sum (map (ord, e)) & 0xff) == 0 and ord (e[0]) == 0xDB:
print "%s: already initialized, skipped" % (slot_name,)
return True
-
+
if not write_dboard_eeprom (u, i2c_addr, dbid, oe):
print "%s: failed to write d'board EEPROM" % (slot_name,)
return False
if __name__ == "__main__":
main ()
-
+
#
# Copyright 2009 Free Software Foundation, Inc.
-#
+#
# This file is part of GNU Radio
-#
+#
# GNU Radio is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
-#
+#
# GNU Radio is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License
# along with GNU Radio; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
-#
+#
include $(top_srcdir)/Makefile.common
db_flexrf.h \
db_flexrf_mimo.h \
db_tv_rx.h \
- db_tv_rx_mimo.h \
+ db_tv_rx_mimo.h \
+ db_wbxng.h \
db_xcvr2450.h \
libusb_types.h \
usrp_basic.h \
--- /dev/null
+/* -*- c++ -*- */
+//
+// Copyright 2009 Free Software Foundation, Inc.
+//
+// This file is part of GNU Radio
+//
+// GNU Radio is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either asversion 3, or (at your option)
+// any later version.
+//
+// GNU Radio is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with GNU Radio; see the file COPYING. If not, write to
+// the Free Software Foundation, Inc., 51 Franklin Street,
+// Boston, MA 02110-1301, USA.
+
+#ifndef INCLUDED_DB_WBXNG_H
+#define INCLUDED_DB_WBXNG_H
+
+#include <usrp/db_base.h>
+#include <cmath>
+
+class adf4350;
+
+class wbxng_base : public db_base
+{
+public:
+ wbxng_base(usrp_basic_sptr usrp, int which, int _power_on=0);
+ ~wbxng_base();
+
+ struct freq_result_t set_freq(double freq);
+
+ bool is_quadrature();
+ double freq_min();
+ double freq_max();
+
+protected:
+ bool _lock_detect();
+ bool _set_pga(float pga_gain);
+
+ int power_on() { return d_power_on; }
+ int power_off() { return 0; }
+
+ bool d_first;
+ int d_spi_format;
+ int d_spi_enable;
+ int d_power_on;
+ int d_PD;
+
+ adf4350 *d_common;
+};
+
+// ----------------------------------------------------------------
+
+class wbxng_base_tx : public wbxng_base
+{
+protected:
+ void shutdown();
+
+public:
+ wbxng_base_tx(usrp_basic_sptr usrp, int which, int _power_on=0);
+ ~wbxng_base_tx();
+
+ float gain_min();
+ float gain_max();
+ float gain_db_per_step();
+
+ bool set_auto_tr(bool on);
+ bool set_enable(bool on);
+ bool set_gain(float gain);
+};
+
+class wbxng_base_rx : public wbxng_base
+{
+protected:
+ void shutdown();
+ bool _set_attn(float attn);
+
+public:
+ wbxng_base_rx(usrp_basic_sptr usrp, int which, int _power_on=0);
+ ~wbxng_base_rx();
+
+ bool set_auto_tr(bool on);
+ bool select_rx_antenna(int which_antenna);
+ bool select_rx_antenna(const std::string &which_antenna);
+ bool set_gain(float gain);
+};
+
+// ----------------------------------------------------------------
+
+class db_wbxng_tx : public wbxng_base_tx
+{
+ public:
+ db_wbxng_tx(usrp_basic_sptr usrp, int which);
+ ~db_wbxng_tx();
+};
+
+class db_wbxng_rx : public wbxng_base_rx
+{
+public:
+ db_wbxng_rx(usrp_basic_sptr usrp, int which);
+ ~db_wbxng_rx();
+
+ float gain_min();
+ float gain_max();
+ float gain_db_per_step();
+ bool i_and_q_swapped();
+};
+
+#endif /* INCLUDED_DB_WBXNG_H */
#
# USRP - Universal Software Radio Peripheral
-#
+#
# Copyright (C) 2003,2004,2006,2007,2008,2009 Free Software Foundation, Inc.
-#
+#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
-#
+#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
-#
+#
include $(top_srcdir)/Makefile.common
usrp_local_sighandler.cc \
usrp_prims_common.cc \
usrp_standard.cc \
+ db_wbxng_adf4350.cc \
+ db_wbxng_adf4350_regs.cc \
db_boards.cc \
db_base.cc \
db_basic.cc \
db_flexrf.cc \
db_flexrf_mimo.cc \
db_dbs_rx.cc \
+ db_wbxng.cc \
db_xcvr2450.cc \
db_dtt754.cc \
db_dtt768.cc \
db_base_impl.h \
db_boards.h \
db_util.h \
+ db_wbxng_adf4350.h \
+ db_wbxng_adf4350_regs.h \
fusb.h \
fusb_darwin.h \
fusb_generic.h \
/* -*- c++ -*- */
//
// Copyright 2008,2009 Free Software Foundation, Inc.
-//
+//
// This file is part of GNU Radio
-//
+//
// GNU Radio is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either asversion 3, or (at your option)
// any later version.
-//
+//
// GNU Radio is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
-//
+//
// You should have received a copy of the GNU General Public License
// along with GNU Radio; see the file COPYING. If not, write to
// the Free Software Foundation, Inc., 51 Franklin Street,
#include <usrp/db_dbs_rx.h>
#include <usrp/db_flexrf.h>
#include <usrp/db_flexrf_mimo.h>
+#include <usrp/db_wbxng.h>
#include <usrp/db_xcvr2450.h>
#include <usrp/db_dtt754.h>
#include <usrp/db_dtt768.h>
db.push_back(db_base_sptr(new db_lf_rx(usrp, which_side, 1)));
db.push_back(db_base_sptr(new db_lf_rx(usrp, which_side, 2)));
break;
-
+
case(USRP_DBID_DBS_RX):
db.push_back(db_base_sptr(new db_dbs_rx(usrp, which_side)));
break;
case(USRP_DBID_XCVR2450_RX):
db.push_back(db_base_sptr(new db_xcvr2450_rx(usrp, which_side)));
break;
-
+
#if 0 // FIXME wbx doesn't compile
case(USRP_DBID_WBX_LO_TX):
db.push_back(db_base_sptr(new db_wbx_lo_tx(usrp, which_side)));
break;
#endif
+ case(USRP_DBID_WBX_NG_TX):
+ db.push_back(db_base_sptr(new db_wbxng_tx(usrp, which_side)));
+ break;
+ case(USRP_DBID_WBX_NG_RX):
+ db.push_back(db_base_sptr(new db_wbxng_rx(usrp, which_side)));
+ break;
+
case(USRP_DBID_DTT754):
db.push_back(db_base_sptr(new db_dtt754(usrp, which_side)));
break;
db.push_back(db_base_sptr(new db_basic_rx(usrp, which_side, 1)));
}
break;
-
+
case(-2):
default:
if (boost::dynamic_pointer_cast<usrp_basic_tx>(usrp)){
--- /dev/null
+//
+// Copyright 2008,2009 Free Software Foundation, Inc.
+//
+// This file is part of GNU Radio
+//
+// GNU Radio is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either asversion 3, or (at your option)
+// any later version.
+//
+// GNU Radio is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with GNU Radio; see the file COPYING. If not, write to
+// the Free Software Foundation, Inc., 51 Franklin Street,
+// Boston, MA 02110-1301, USA.
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <usrp/db_wbxng.h>
+#include "db_wbxng_adf4350.h"
+#include <db_base_impl.h>
+#include <stdio.h>
+
+// d'board i/o pin defs
+// Tx and Rx have shared defs, but different i/o regs
+#define ENABLE_5 (1 << 7) // enables 5.0V power supply
+#define ENABLE_33 (1 << 6) // enables 3.3V supply
+#define RX_TXN (1 << 5) // Tx only: T/R antenna switch for TX/RX port
+#define RX2_RX1N (1 << 5) // Rx only: antenna switch between RX2 and TX/RX port
+#define RXBB_EN (1 << 4)
+#define TXMOD_EN (1 << 4)
+#define PLL_CE (1 << 3)
+#define PLL_PDBRF (1 << 2)
+#define PLL_MUXOUT (1 << 1)
+#define PLL_LOCK_DETECT (1 << 0)
+
+// RX Attenuator constants
+#define ATTN_SHIFT 8
+#define ATTN_MASK (63 << ATTN_SHIFT)
+
+wbxng_base::wbxng_base(usrp_basic_sptr _usrp, int which, int _power_on)
+ : db_base(_usrp, which), d_power_on(_power_on)
+{
+ /*
+ @param usrp: instance of usrp.source_c
+ @param which: which side: 0 or 1 corresponding to side A or B respectively
+ @type which: int
+ */
+
+ usrp()->_write_oe(d_which, 0, 0xffff); // turn off all outputs
+
+ d_first = true;
+ d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0;
+
+ _enable_refclk(false); // disable refclk
+
+ set_auto_tr(false);
+}
+
+wbxng_base::~wbxng_base()
+{
+ if (d_common)
+ delete d_common;
+}
+
+struct freq_result_t
+wbxng_base::set_freq(double freq)
+{
+ /*
+ @returns (ok, actual_baseband_freq) where:
+ ok is True or False and indicates success or failure,
+ actual_baseband_freq is the RF frequency that corresponds to DC in the IF.
+ */
+
+ freq_t int_freq = freq_t(freq);
+ bool ok = d_common->_set_freq(int_freq*2);
+ double freq_result = (double) d_common->_get_freq()/2.0;
+ struct freq_result_t args = {ok, freq_result};
+
+ /* Wait before reading Lock Detect*/
+ timespec t;
+ t.tv_sec = 0;
+ t.tv_nsec = 10000000;
+ nanosleep(&t, NULL);
+
+ fprintf(stderr,"Setting WBXNG frequency, requested %d, obtained %f, lock_detect %d\n",
+ int_freq, freq_result, d_common->_get_locked());
+
+ // FIXME
+ // Offsetting the LO helps get the Tx carrier leakage out of the way.
+ // This also ensures that on Rx, we're not getting hosed by the
+ // FPGA's DC removal loop's time constant. We were seeing a
+ // problem when running with discontinuous transmission.
+ // Offsetting the LO made the problem go away.
+ //freq += d_lo_offset;
+
+ return args;
+}
+
+bool
+wbxng_base::_set_pga(float pga_gain)
+{
+ if(d_which == 0) {
+ usrp()->set_pga(0, pga_gain);
+ usrp()->set_pga(1, pga_gain);
+ }
+ else {
+ usrp()->set_pga(2, pga_gain);
+ usrp()->set_pga(3, pga_gain);
+ }
+ return true;
+}
+
+bool
+wbxng_base::is_quadrature()
+{
+ /*
+ Return True if this board requires both I & Q analog channels.
+
+ This bit of info is useful when setting up the USRP Rx mux register.
+ */
+ return true;
+}
+
+double
+wbxng_base::freq_min()
+{
+ return (double) d_common->_get_min_freq()/2.0;
+}
+
+double
+wbxng_base::freq_max()
+{
+ return (double) d_common->_get_max_freq()/2.0;
+}
+
+// ----------------------------------------------------------------
+
+wbxng_base_tx::wbxng_base_tx(usrp_basic_sptr _usrp, int which, int _power_on)
+ : wbxng_base(_usrp, which, _power_on)
+{
+ /*
+ @param usrp: instance of usrp.sink_c
+ @param which: 0 or 1 corresponding to side TX_A or TX_B respectively.
+ */
+
+ if(which == 0) {
+ d_spi_enable = SPI_ENABLE_TX_A;
+ }
+ else {
+ d_spi_enable = SPI_ENABLE_TX_B;
+ }
+
+ d_common = new adf4350(_usrp, d_which, d_spi_enable);
+
+ // FIXME: power up the transmit side, but don't enable the mixer
+ usrp()->_write_oe(d_which,(RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5), (RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5));
+ usrp()->write_io(d_which, (power_on()|RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5), (RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5));
+ fprintf(stderr,"Setting WBXNG TXMOD on");
+ //set_lo_offset(4e6);
+
+ set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
+}
+
+wbxng_base_tx::~wbxng_base_tx()
+{
+ shutdown();
+}
+
+
+void
+wbxng_base_tx::shutdown()
+{
+ // fprintf(stderr, "wbxng_base_tx::shutdown d_is_shutdown = %d\n", d_is_shutdown);
+
+ if (!d_is_shutdown){
+ d_is_shutdown = true;
+ // do whatever there is to do to shutdown
+
+ // Power down and leave the T/R switch in the R position
+ usrp()->write_io(d_which, (power_off()|RX_TXN), (RX_TXN|ENABLE_33|ENABLE_5));
+
+ // Power down VCO/PLL
+ d_common->_enable(false);
+
+ /*
+ _write_control(_compute_control_reg());
+ */
+ _enable_refclk(false); // turn off refclk
+ set_auto_tr(false);
+ }
+}
+
+bool
+wbxng_base_tx::set_auto_tr(bool on)
+{
+ bool ok = true;
+ if(on) {
+ ok &= set_atr_mask (RX_TXN | ENABLE_33 | ENABLE_5);
+ ok &= set_atr_txval(0 | ENABLE_33 | ENABLE_5);
+ ok &= set_atr_rxval(RX_TXN | 0);
+ }
+ else {
+ ok &= set_atr_mask (0);
+ ok &= set_atr_txval(0);
+ ok &= set_atr_rxval(0);
+ }
+ return ok;
+}
+
+bool
+wbxng_base_tx::set_enable(bool on)
+{
+ /*
+ Enable transmitter if on is true
+ */
+
+ int v;
+ int mask = RX_TXN | ENABLE_5 | ENABLE_33;
+ if(on) {
+ v = ENABLE_5 | ENABLE_33;
+ }
+ else {
+ v = RX_TXN;
+ }
+ return usrp()->write_io(d_which, v, mask);
+}
+
+float
+wbxng_base_tx::gain_min()
+{
+ return usrp()->pga_max();
+}
+
+float
+wbxng_base_tx::gain_max()
+{
+ return usrp()->pga_max() + 25.0;
+}
+
+float
+wbxng_base_tx::gain_db_per_step()
+{
+ return 1;
+}
+
+bool
+wbxng_base_tx::set_gain(float gain)
+{
+ /*
+ Set the gain.
+
+ @param gain: gain in decibels
+ @returns True/False
+ */
+
+ // clamp gain
+ gain = std::max(gain_min(), std::min(gain, gain_max()));
+
+ float pga_gain, agc_gain;
+ float V_maxgain, V_mingain, V_fullscale, dac_value;
+
+ float maxgain = gain_max() - usrp()->pga_max();
+ float mingain = gain_min();
+ if(gain > maxgain) {
+ pga_gain = gain-maxgain;
+ assert(pga_gain <= usrp()->pga_max());
+ agc_gain = maxgain;
+ }
+ else {
+ pga_gain = 0;
+ agc_gain = gain;
+ }
+
+ V_maxgain = 0.7;
+ V_mingain = 1.4;
+ V_fullscale = 3.3;
+ dac_value = (agc_gain*(V_maxgain-V_mingain)/(maxgain-mingain) + V_mingain)*4096/V_fullscale;
+
+ fprintf(stderr, "TXGAIN: %f dB, Dac Code: %d, Voltage: %f\n", gain, int(dac_value), float((dac_value/4096.0)*V_fullscale));
+ assert(dac_value>=0 && dac_value<4096);
+
+ return (usrp()->write_aux_dac(d_which, 0, int(dac_value))
+ && _set_pga(int(pga_gain)));
+}
+
+
+/**************************************************************************/
+
+
+wbxng_base_rx::wbxng_base_rx(usrp_basic_sptr _usrp, int which, int _power_on)
+ : wbxng_base(_usrp, which, _power_on)
+{
+ /*
+ @param usrp: instance of usrp.source_c
+ @param which: 0 or 1 corresponding to side RX_A or RX_B respectively.
+ */
+
+ if(which == 0) {
+ d_spi_enable = SPI_ENABLE_RX_A;
+ }
+ else {
+ d_spi_enable = SPI_ENABLE_RX_B;
+ }
+
+ d_common = new adf4350(_usrp, d_which, d_spi_enable);
+
+ usrp()->_write_oe(d_which, (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5), (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
+ usrp()->write_io(d_which, (power_on()|RX2_RX1N|RXBB_EN|ENABLE_33|ENABLE_5), (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
+ fprintf(stderr,"Setting WBXNG RXBB on");
+
+ // set up for RX on TX/RX port
+ select_rx_antenna("TX/RX");
+
+ bypass_adc_buffers(true);
+
+ /*
+ set_lo_offset(-4e6);
+ */
+}
+
+wbxng_base_rx::~wbxng_base_rx()
+{
+ shutdown();
+}
+
+void
+wbxng_base_rx::shutdown()
+{
+ // fprintf(stderr, "wbxng_base_rx::shutdown d_is_shutdown = %d\n", d_is_shutdown);
+
+ if (!d_is_shutdown){
+ d_is_shutdown = true;
+ // do whatever there is to do to shutdown
+
+ // Power down
+ usrp()->common_write_io(C_RX, d_which, power_off(), (ENABLE_33|ENABLE_5));
+
+ // Power down VCO/PLL
+ d_common->_enable(false);
+
+ // fprintf(stderr, "wbxng_base_rx::shutdown before _write_control\n");
+ //_write_control(_compute_control_reg());
+
+ // fprintf(stderr, "wbxng_base_rx::shutdown before _enable_refclk\n");
+ _enable_refclk(false); // turn off refclk
+
+ // fprintf(stderr, "wbxng_base_rx::shutdown before set_auto_tr\n");
+ set_auto_tr(false);
+
+ // fprintf(stderr, "wbxng_base_rx::shutdown after set_auto_tr\n");
+ }
+}
+
+bool
+wbxng_base_rx::set_auto_tr(bool on)
+{
+ bool ok = true;
+ if(on) {
+ ok &= set_atr_mask (ENABLE_33|ENABLE_5);
+ ok &= set_atr_txval( 0);
+ ok &= set_atr_rxval(ENABLE_33|ENABLE_5);
+ }
+ else {
+ ok &= set_atr_mask (0);
+ ok &= set_atr_txval(0);
+ ok &= set_atr_rxval(0);
+ }
+ return true;
+}
+
+bool
+wbxng_base_rx::select_rx_antenna(int which_antenna)
+{
+ /*
+ Specify which antenna port to use for reception.
+ @param which_antenna: either 'TX/RX' or 'RX2'
+ */
+
+ if(which_antenna == 0) {
+ usrp()->write_io(d_which, 0,RX2_RX1N);
+ }
+ else if(which_antenna == 1) {
+ usrp()->write_io(d_which, RX2_RX1N, RX2_RX1N);
+ }
+ else {
+ return false;
+ }
+ return true;
+}
+
+bool
+wbxng_base_rx::select_rx_antenna(const std::string &which_antenna)
+{
+ /*
+ Specify which antenna port to use for reception.
+ @param which_antenna: either 'TX/RX' or 'RX2'
+ */
+
+
+ if(which_antenna == "TX/RX") {
+ usrp()->write_io(d_which, 0, RX2_RX1N);
+ }
+ else if(which_antenna == "RX2") {
+ usrp()->write_io(d_which, RX2_RX1N, RX2_RX1N);
+ }
+ else {
+ return false;
+ }
+
+ return true;
+}
+
+bool
+wbxng_base_rx::set_gain(float gain)
+{
+ /*
+ Set the gain.
+
+ @param gain: gain in decibels
+ @returns True/False
+ */
+
+ // clamp gain
+ gain = std::max(gain_min(), std::min(gain, gain_max()));
+
+ float pga_gain, agc_gain;
+
+ float maxgain = gain_max() - usrp()->pga_max();
+ float mingain = gain_min();
+ if(gain > maxgain) {
+ pga_gain = gain-maxgain;
+ assert(pga_gain <= usrp()->pga_max());
+ agc_gain = maxgain;
+ }
+ else {
+ pga_gain = 0;
+ agc_gain = gain;
+ }
+
+ return _set_attn(maxgain-agc_gain) && _set_pga(int(pga_gain));
+}
+
+bool
+wbxng_base_rx::_set_attn(float attn)
+{
+ int attn_code = int(floor(attn/0.5));
+ unsigned int iobits = (~attn_code) << ATTN_SHIFT;
+ fprintf(stderr, "Attenuation: %f dB, Code: %d, IO Bits %x, Mask: %x \n", attn, attn_code, iobits & ATTN_MASK, ATTN_MASK);
+ return usrp()->write_io(d_which, iobits, ATTN_MASK);
+}
+
+// ----------------------------------------------------------------
+
+db_wbxng_tx::db_wbxng_tx(usrp_basic_sptr usrp, int which)
+ : wbxng_base_tx(usrp, which)
+{
+}
+
+db_wbxng_tx::~db_wbxng_tx()
+{
+}
+
+db_wbxng_rx::db_wbxng_rx(usrp_basic_sptr usrp, int which)
+ : wbxng_base_rx(usrp, which)
+{
+ set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
+}
+
+db_wbxng_rx::~db_wbxng_rx()
+{
+}
+
+float
+db_wbxng_rx::gain_min()
+{
+ return usrp()->pga_min();
+}
+
+float
+db_wbxng_rx::gain_max()
+{
+ return usrp()->pga_max()+30.5;
+}
+
+float
+db_wbxng_rx::gain_db_per_step()
+{
+ return 0.05;
+}
+
+
+bool
+db_wbxng_rx::i_and_q_swapped()
+{
+ return false;
+}
--- /dev/null
+//
+// Copyright 2009 Free Software Foundation, Inc.
+//
+// This file is part of GNU Radio
+//
+// GNU Radio is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either asversion 3, or (at your option)
+// any later version.
+//
+// GNU Radio is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with GNU Radio; see the file COPYING. If not, write to
+// the Free Software Foundation, Inc., 51 Franklin Street,
+// Boston, MA 02110-1301, USA.
+
+#ifdef HAVE_CONFIG_H
+#include <config.h>
+#endif
+
+#include "db_wbxng_adf4350.h"
+#include <db_base_impl.h>
+#include <stdio.h>
+
+#define INPUT_REF_FREQ FREQ_C(64e6)
+#define DIV_ROUND(num, denom) (((num) + ((denom)/2))/(denom))
+#define FREQ_C(freq) uint64_t(freq)
+#define INPUT_REF_FREQ_2X (2*INPUT_REF_FREQ) /* input ref freq with doubler turned on */
+#define MIN_INT_DIV uint16_t(23) /* minimum int divider, prescaler 4/5 only */
+#define MAX_RF_DIV uint8_t(16) /* max rf divider, divides rf output */
+#define MIN_VCO_FREQ FREQ_C(2.2e9) /* minimum vco freq */
+#define MAX_VCO_FREQ FREQ_C(4.4e9) /* minimum vco freq */
+#define MAX_FREQ MAX_VCO_FREQ /* upper bound freq (rf div = 1) */
+#define MIN_FREQ DIV_ROUND(MIN_VCO_FREQ, MAX_RF_DIV) /* calculated lower bound freq */
+
+#define CE_PIN (1 << 3)
+#define PDB_RF_PIN (1 << 2)
+#define MUX_PIN (1 << 1)
+#define LD_PIN (1 << 0)
+
+adf4350::adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable)
+{
+ /* Initialize the pin directions. */
+
+ d_usrp = _usrp;
+ d_which = _which;
+ d_spi_enable = _spi_enable;
+ d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0;
+
+ d_regs = new adf4350_regs(this);
+
+ /* Outputs */
+ d_usrp->_write_oe(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
+ d_usrp->write_io(d_which, (0), (CE_PIN | PDB_RF_PIN));
+
+ /* Initialize the pin levels. */
+ _enable(true);
+ /* Initialize the registers. */
+ d_regs->_load_register(5);
+ d_regs->_load_register(4);
+ d_regs->_load_register(3);
+ d_regs->_load_register(2);
+ d_regs->_load_register(1);
+ d_regs->_load_register(0);
+}
+
+adf4350::~adf4350()
+{
+ delete d_regs;
+}
+
+freq_t
+adf4350::_get_max_freq(void)
+{
+ return MAX_FREQ;
+}
+
+freq_t
+adf4350::_get_min_freq(void)
+{
+ return MIN_FREQ;
+}
+
+bool
+adf4350::_get_locked(void)
+{
+ return d_usrp->read_io(d_which) & LD_PIN;
+}
+
+void
+adf4350::_enable(bool enable)
+{
+ if (enable){ /* chip enable */
+ d_usrp->write_io(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
+ }else{
+ d_usrp->write_io(d_which, 0, (CE_PIN | PDB_RF_PIN));
+ }
+}
+
+void
+adf4350::_write(uint8_t addr, uint32_t data)
+{
+ data |= addr;
+
+ // create str from data here
+ char s[4];
+ s[0] = (char)((data >> 24) & 0xff);
+ s[1] = (char)((data >> 16) & 0xff);
+ s[2] = (char)((data >> 8) & 0xff);
+ s[3] = (char)(data & 0xff);
+ std::string str(s, 4);
+
+ timespec t;
+ t.tv_sec = 0;
+ t.tv_nsec = 5e6;
+
+ nanosleep(&t, NULL);
+ d_usrp->_write_spi(0, d_spi_enable, d_spi_format, str);
+ nanosleep(&t, NULL);
+
+ //fprintf(stderr, "Wrote to WBXNG SPI address %d with data %8x\n", addr, data);
+ /* pulse latch */
+ //d_usrp->write_io(d_which, 1, LE_PIN);
+ //d_usrp->write_io(d_which, 0, LE_PIN);
+}
+
+bool
+adf4350::_set_freq(freq_t freq)
+{
+ /* Set the frequency by setting int, frac, mod, r, div */
+ if (freq > MAX_FREQ || freq < MIN_FREQ) return false;
+ /* Ramp up the RF divider until the VCO is within range. */
+ d_regs->d_divider_select = 0;
+ while (freq < MIN_VCO_FREQ){
+ freq <<= 1; //double the freq
+ d_regs->d_divider_select++; //double the divider
+ }
+ /* Ramp up the R divider until the N divider is at least the minimum. */
+ //d_regs->d_10_bit_r_counter = INPUT_REF_FREQ*MIN_INT_DIV/freq;
+ d_regs->d_10_bit_r_counter = 2;
+ uint64_t n_mod;
+ do{
+ d_regs->d_10_bit_r_counter++;
+ n_mod = freq;
+ n_mod *= d_regs->d_10_bit_r_counter;
+ n_mod *= d_regs->d_mod;
+ n_mod /= INPUT_REF_FREQ;
+ /* calculate int and frac */
+ d_regs->d_int = n_mod/d_regs->d_mod;
+ d_regs->d_frac = (n_mod - (freq_t)d_regs->d_int*d_regs->d_mod) & uint16_t(0xfff);
+ /*
+ fprintf(stderr,
+ "VCO %lu KHz, Int %u, Frac %u, Mod %u, R %u, Div %u\n",
+ freq, d_regs->d_int, d_regs->d_frac,
+ d_regs->d_mod, d_regs->d_10_bit_r_counter, (1 << d_regs->d_divider_select)
+ );
+ */
+ }while(d_regs->d_int < MIN_INT_DIV);
+ /* calculate the band select so PFD is under 125 KHz */
+ d_regs->d_8_bit_band_select_clock_divider_value = \
+ INPUT_REF_FREQ/(FREQ_C(30e3)*d_regs->d_10_bit_r_counter) + 1;
+ /*
+ fprintf(stderr, "Band Selection: Div %u, Freq %lu\n",
+ d_regs->d_8_bit_band_select_clock_divider_value,
+ INPUT_REF_FREQ/(d_regs->d_8_bit_band_select_clock_divider_value * d_regs->d_10_bit_r_counter) + 1
+ );
+ */
+ d_regs->_load_register(5);
+ d_regs->_load_register(3);
+ d_regs->_load_register(1);
+ /* load involved registers */
+ d_regs->_load_register(2);
+ d_regs->_load_register(4);
+ d_regs->_load_register(0); /* register 0 must be last */
+ return true;
+}
+
+freq_t
+adf4350::_get_freq(void)
+{
+ /* Calculate the freq from int, frac, mod, ref, r, div:
+ * freq = (int + frac/mod) * (ref/r)
+ * Keep precision by doing multiplies first:
+ * freq = (((((((int)*mod) + frac)*ref)/mod)/r)/div)
+ */
+ uint64_t temp;
+ temp = d_regs->d_int;
+ temp *= d_regs->d_mod;
+ temp += d_regs->d_frac;
+ temp *= INPUT_REF_FREQ;
+ temp /= d_regs->d_mod;
+ temp /= d_regs->d_10_bit_r_counter;
+ temp /= (1 << d_regs->d_divider_select);
+ return temp;
+}
--- /dev/null
+//
+// Copyright 2009 Free Software Foundation, Inc.
+//
+// This file is part of GNU Radio
+//
+// GNU Radio is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either asversion 3, or (at your option)
+// any later version.
+//
+// GNU Radio is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with GNU Radio; see the file COPYING. If not, write to
+// the Free Software Foundation, Inc., 51 Franklin Street,
+// Boston, MA 02110-1301, USA.
+
+#ifndef INCLUDED_ADF4350_H
+#define INCLUDED_ADF4350_H
+
+#include "db_wbxng_adf4350_regs.h"
+#include <usrp/db_base.h>
+#include <stdint.h>
+
+typedef uint64_t freq_t;
+class adf4350_regs;
+
+class adf4350
+{
+public:
+ adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable);
+ ~adf4350();
+ void _update();
+ bool _get_locked();
+ void _enable(bool enable);
+ void _write(uint8_t addr, uint32_t data);
+ bool _set_freq(freq_t freq);
+ freq_t _get_freq();
+ freq_t _get_max_freq();
+ freq_t _get_min_freq();
+
+protected:
+ usrp_basic_sptr d_usrp;
+ int d_which;
+ int d_spi_enable;
+ int d_spi_format;
+ adf4350_regs *d_regs;
+};
+
+#endif /* INCLUDED_ADF4350_H */
--- /dev/null
+/*
+ * Copyright 2009 Ettus Research LLC
+ */
+
+#include "db_wbxng_adf4350_regs.h"
+#include "db_wbxng_adf4350.h"
+
+//#include "cal_div.h"
+
+/* reg 0 */
+/* reg 1 */
+const uint8_t adf4350_regs::s_prescaler = 0;
+const uint16_t adf4350_regs::s_phase = 0;
+/* reg 2 */
+const uint8_t adf4350_regs::s_low_noise_and_low_spur_modes = 0;
+const uint8_t adf4350_regs::s_muxout = 6;
+const uint8_t adf4350_regs::s_reference_doubler = 0;
+const uint8_t adf4350_regs::s_rdiv2 = 0;
+const uint8_t adf4350_regs::s_double_buff = 0;
+const uint8_t adf4350_regs::s_charge_pump_setting = 5;
+const uint8_t adf4350_regs::s_ldf = 0;
+const uint8_t adf4350_regs::s_ldp = 0;
+const uint8_t adf4350_regs::s_pd_polarity = 1;
+const uint8_t adf4350_regs::s_power_down = 0;
+const uint8_t adf4350_regs::s_cp_three_state = 0;
+const uint8_t adf4350_regs::s_counter_reset = 0;
+/* reg 3 */
+const uint8_t adf4350_regs::s_csr = 0;
+const uint8_t adf4350_regs::s_clk_div_mode = 0;
+const uint16_t adf4350_regs::s_12_bit_clock_divider_value = 0;
+/* reg 4 */
+const uint8_t adf4350_regs::s_feedback_select = 1;
+const uint8_t adf4350_regs::s_vco_power_down = 0;
+const uint8_t adf4350_regs::s_mtld = 0;
+const uint8_t adf4350_regs::s_aux_output_select = 0;
+const uint8_t adf4350_regs::s_aux_output_enable = 1;
+const uint8_t adf4350_regs::s_aux_output_power = 3;
+const uint8_t adf4350_regs::s_rf_output_enable = 1;
+const uint8_t adf4350_regs::s_output_power = 3;
+/* reg 5 */
+const uint8_t adf4350_regs::s_ld_pin_mode = 1;
+
+adf4350_regs::adf4350_regs(adf4350* _adf4350){
+ d_adf4350 = _adf4350;
+
+ /* reg 0 */
+ d_int = uint16_t(100);
+ d_frac = 0;
+ /* reg 1 */
+ d_mod = uint16_t(0xfff); /* max fractional accuracy */
+ /* reg 2 */
+ d_10_bit_r_counter = uint16_t(2);
+ /* reg 3 */
+ /* reg 4 */
+ d_divider_select = 0;
+ d_8_bit_band_select_clock_divider_value = 0;
+ /* reg 5 */
+}
+
+adf4350_regs::~adf4350_regs(void){
+}
+
+uint32_t
+adf4350_regs::_reg_shift(uint32_t data, uint32_t shift){
+ return data << shift;
+ }
+
+void
+adf4350_regs::_load_register(uint8_t addr){
+ uint32_t data;
+ switch (addr){
+ case 0: data = (
+ _reg_shift(d_int, 15) |
+ _reg_shift(d_frac, 3)); break;
+ case 1: data = (
+ _reg_shift(s_prescaler, 27) |
+ _reg_shift(s_phase, 15) |
+ _reg_shift(d_mod, 3)); break;
+ case 2: data = (
+ _reg_shift(s_low_noise_and_low_spur_modes, 29) |
+ _reg_shift(s_muxout, 26) |
+ _reg_shift(s_reference_doubler, 25) |
+ _reg_shift(s_rdiv2, 24) |
+ _reg_shift(d_10_bit_r_counter, 14) |
+ _reg_shift(s_double_buff, 13) |
+ _reg_shift(s_charge_pump_setting, 9) |
+ _reg_shift(s_ldf, 8) |
+ _reg_shift(s_ldp, 7) |
+ _reg_shift(s_pd_polarity, 6) |
+ _reg_shift(s_power_down, 5) |
+ _reg_shift(s_cp_three_state, 4) |
+ _reg_shift(s_counter_reset, 3)); break;
+ case 3: data = (
+ _reg_shift(s_csr, 18) |
+ _reg_shift(s_clk_div_mode, 15) |
+ _reg_shift(s_12_bit_clock_divider_value, 3)); break;
+ case 4: data = (
+ _reg_shift(s_feedback_select, 23) |
+ _reg_shift(d_divider_select, 20) |
+ _reg_shift(d_8_bit_band_select_clock_divider_value, 12) |
+ _reg_shift(s_vco_power_down, 11) |
+ _reg_shift(s_mtld, 10) |
+ _reg_shift(s_aux_output_select, 9) |
+ _reg_shift(s_aux_output_enable, 8) |
+ _reg_shift(s_aux_output_power, 6) |
+ _reg_shift(s_rf_output_enable, 5) |
+ _reg_shift(s_output_power, 3)); break;
+ case 5: data = (
+ _reg_shift(s_ld_pin_mode, 22)); break;
+ default: return;
+ }
+ /* write the data out to spi */
+ d_adf4350->_write(addr, data);
+}
--- /dev/null
+/*
+ * Copyright 2009 Ettus Research LLC
+ */
+
+#ifndef ADF4350_REGS_H
+#define ADF4350_REGS_H
+
+#include <usrp/db_base.h>
+#include <stdint.h>
+
+class adf4350;
+
+class adf4350_regs
+{
+public:
+ adf4350_regs(adf4350* _adf4350);
+ ~adf4350_regs();
+
+ adf4350* d_adf4350;
+
+ uint32_t _reg_shift(uint32_t data, uint32_t shift);
+ void _load_register(uint8_t addr);
+
+ /* reg 0 */
+ uint16_t d_int;
+ uint16_t d_frac;
+ /* reg 1 */
+ static const uint8_t s_prescaler;
+ static const uint16_t s_phase;
+ uint16_t d_mod;
+ /* reg 2 */
+ static const uint8_t s_low_noise_and_low_spur_modes;
+ static const uint8_t s_muxout;
+ static const uint8_t s_reference_doubler;
+ static const uint8_t s_rdiv2;
+ uint16_t d_10_bit_r_counter;
+ static const uint8_t s_double_buff;
+ static const uint8_t s_charge_pump_setting;
+ static const uint8_t s_ldf;
+ static const uint8_t s_ldp;
+ static const uint8_t s_pd_polarity;
+ static const uint8_t s_power_down;
+ static const uint8_t s_cp_three_state;
+ static const uint8_t s_counter_reset;
+ /* reg 3 */
+ static const uint8_t s_csr;
+ static const uint8_t s_clk_div_mode;
+ static const uint16_t s_12_bit_clock_divider_value;
+ /* reg 4 */
+ static const uint8_t s_feedback_select;
+ uint8_t d_divider_select;
+ uint8_t d_8_bit_band_select_clock_divider_value;
+ static const uint8_t s_vco_power_down;
+ static const uint8_t s_mtld;
+ static const uint8_t s_aux_output_select;
+ static const uint8_t s_aux_output_enable;
+ static const uint8_t s_aux_output_power;
+ static const uint8_t s_rf_output_enable;
+ static const uint8_t s_output_power;
+ /* reg 5 */
+ static const uint8_t s_ld_pin_mode;
+};
+
+#endif /* ADF4350_REGS_H */
+++ /dev/null
-class fusb_devhandle;
-class fusb_ephandle;
-
-enum txrx_t {
- C_RX = 0,
- C_TX = 1
-};
-
-/*
- * ----------------------------------------------------------------------
- * Mid level interface to the Universal Software Radio Peripheral (Rev 1)
- *
- * These classes implement the basic functionality for talking to the
- * USRP. They try to be as independent of the signal processing code
- * in FPGA as possible. They implement access to the low level
- * peripherals on the board, provide a common way for reading and
- * writing registers in the FPGA, and provide the high speed interface
- * to streaming data across the USB.
- *
- * It is expected that subclasses will be derived that provide
- * access to the functionality to a particular FPGA configuration.
- * ----------------------------------------------------------------------
- */
-
-
-/*!
- * \brief abstract base class for usrp operations
- * \ingroup usrp
- */
-class usrp_basic : boost::noncopyable
-{
-protected:
- void shutdown_daughterboards();
-
-protected:
- libusb_device_handle *d_udh;
- struct libusb_context *d_ctx;
- int d_usb_data_rate; // bytes/sec
- int d_bytes_per_poll; // how often to poll for overruns
- bool d_verbose;
- long d_fpga_master_clock_freq;
-
- static const int MAX_REGS = 128;
- unsigned int d_fpga_shadows[MAX_REGS];
-
- int d_dbid[2]; // daughterboard ID's (side A, side B)
-
- /*!
- * Shared pointers to subclasses of db_base.
- *
- * The outer vector is of length 2 (0 = side A, 1 = side B). The
- * inner vectors are of length 1, 2 or 3 depending on the number of
- * subdevices implemented by the daugherboard. At this time, only
- * the Basic Rx and LF Rx implement more than 1 subdevice.
- */
- std::vector< std::vector<db_base_sptr> > d_db;
-
- //! One time call, made only only from usrp_standard_*::make after shared_ptr is created.
- void init_db(usrp_basic_sptr u);
-
-
- usrp_basic (int which_board,
- libusb_device_handle *open_interface (libusb_device *dev),
- const std::string fpga_filename = "",
- const std::string firmware_filename = "");
-
- /*!
- * \brief advise usrp_basic of usb data rate (bytes/sec)
- *
- * N.B., this doesn't tweak any hardware. Derived classes
- * should call this to inform us of the data rate whenever it's
- * first set or if it changes.
- *
- * \param usb_data_rate bytes/sec
- */
- void set_usb_data_rate (int usb_data_rate);
-
- /*!
- * \brief Write auxiliary digital to analog converter.
- *
- * \param slot Which Tx or Rx slot to write.
- * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
- * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
- * \param which_dac [0,3] RX slots must use only 0 and 1. TX slots must use only 2 and 3.
- * \param value [0,4095]
- * \returns true iff successful
- */
- bool _write_aux_dac (int slot, int which_dac, int value);
-
- /*!
- * \brief Read auxiliary analog to digital converter.
- *
- * \param slot 2-bit slot number. E.g., SLOT_TX_A
- * \param which_adc [0,1]
- * \param value return 12-bit value [0,4095]
- * \returns true iff successful
- */
- bool _read_aux_adc (int slot, int which_adc, int *value);
-
- /*!
- * \brief Read auxiliary analog to digital converter.
- *
- * \param slot 2-bit slot number. E.g., SLOT_TX_A
- * \param which_adc [0,1]
- * \returns value in the range [0,4095] if successful, else READ_FAILED.
- */
- int _read_aux_adc (int slot, int which_adc);
-
-
-public:
- virtual ~usrp_basic ();
-
-
- /*!
- * Return a vector of vectors that contain shared pointers
- * to the daughterboard instance(s) associated with the specified side.
- *
- * It is an error to use the returned objects after the usrp_basic
- * object has been destroyed.
- */
- std::vector<std::vector<db_base_sptr> > db() const { return d_db; }
-
- /*!
- * Return a vector of size >= 1 that contains shared pointers
- * to the daughterboard instance(s) associated with the specified side.
- *
- * \param which_side [0,1] which daughterboard
- *
- * It is an error to use the returned objects after the usrp_basic
- * object has been destroyed.
- */
- std::vector<db_base_sptr> db(int which_side);
-
- /*!
- * \brief is the subdev_spec valid?
- */
- bool is_valid(const usrp_subdev_spec &ss);
-
- /*!
- * \brief given a subdev_spec, return the corresponding daughterboard object.
- * \throws std::invalid_ argument if ss is invalid.
- *
- * \param ss specifies the side and subdevice
- */
- db_base_sptr selected_subdev(const usrp_subdev_spec &ss);
-
- /*!
- * \brief return frequency of master oscillator on USRP
- */
- long fpga_master_clock_freq () const { return d_fpga_master_clock_freq; }
-
- /*!
- * Tell API that the master oscillator on the USRP is operating at a non-standard
- * fixed frequency. This is only needed for custom USRP hardware modified to
- * operate at a different frequency from the default factory configuration. This
- * function must be called prior to any other API function.
- * \param master_clock USRP2 FPGA master clock frequency in Hz (10..64 MHz)
- */
- void set_fpga_master_clock_freq (long master_clock) { d_fpga_master_clock_freq = master_clock; }
-
- /*!
- * \returns usb data rate in bytes/sec
- */
- int usb_data_rate () const { return d_usb_data_rate; }
-
- void set_verbose (bool on) { d_verbose = on; }
-
- //! magic value used on alternate register read interfaces
- static const int READ_FAILED = -99999;
-
- /*!
- * \brief Write EEPROM on motherboard or any daughterboard.
- * \param i2c_addr I2C bus address of EEPROM
- * \param eeprom_offset byte offset in EEPROM to begin writing
- * \param buf the data to write
- * \returns true iff sucessful
- */
- bool write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf);
-
- /*!
- * \brief Read EEPROM on motherboard or any daughterboard.
- * \param i2c_addr I2C bus address of EEPROM
- * \param eeprom_offset byte offset in EEPROM to begin reading
- * \param len number of bytes to read
- * \returns the data read if successful, else a zero length string.
- */
- std::string read_eeprom (int i2c_addr, int eeprom_offset, int len);
-
- /*!
- * \brief Write to I2C peripheral
- * \param i2c_addr I2C bus address (7-bits)
- * \param buf the data to write
- * \returns true iff successful
- * Writes are limited to a maximum of of 64 bytes.
- */
- bool write_i2c (int i2c_addr, const std::string buf);
-
- /*!
- * \brief Read from I2C peripheral
- * \param i2c_addr I2C bus address (7-bits)
- * \param len number of bytes to read
- * \returns the data read if successful, else a zero length string.
- * Reads are limited to a maximum of 64 bytes.
- */
- std::string read_i2c (int i2c_addr, int len);
-
- /*!
- * \brief Set ADC offset correction
- * \param which_adc which ADC[0,3]: 0 = RX_A I, 1 = RX_A Q...
- * \param offset 16-bit value to subtract from raw ADC input.
- */
- bool set_adc_offset (int which_adc, int offset);
-
- /*!
- * \brief Set DAC offset correction
- * \param which_dac which DAC[0,3]: 0 = TX_A I, 1 = TX_A Q...
- * \param offset 10-bit offset value (ambiguous format: See AD9862 datasheet).
- * \param offset_pin 1-bit value. If 0 offset applied to -ve differential pin;
- * If 1 offset applied to +ve differential pin.
- */
- bool set_dac_offset (int which_dac, int offset, int offset_pin);
-
- /*!
- * \brief Control ADC input buffer
- * \param which_adc which ADC[0,3]
- * \param bypass if non-zero, bypass input buffer and connect input
- * directly to switched cap SHA input of RxPGA.
- */
- bool set_adc_buffer_bypass (int which_adc, bool bypass);
-
- /*!
- * \brief Enable/disable automatic DC offset removal control loop in FPGA
- *
- * \param bits which control loops to enable
- * \param mask which \p bits to pay attention to
- *
- * If the corresponding bit is set, enable the automatic DC
- * offset correction control loop.
- *
- * <pre>
- * The 4 low bits are significant:
- *
- * ADC0 = (1 << 0)
- * ADC1 = (1 << 1)
- * ADC2 = (1 << 2)
- * ADC3 = (1 << 3)
- * </pre>
- *
- * By default the control loop is enabled on all ADC's.
- */
- bool set_dc_offset_cl_enable(int bits, int mask);
-
- /*!
- * \brief return the usrp's serial number.
- *
- * \returns non-zero length string iff successful.
- */
- std::string serial_number();
-
- /*!
- * \brief Return daughterboard ID for given side [0,1].
- *
- * \param which_side [0,1] which daughterboard
- *
- * \return daughterboard id >= 0 if successful
- * \return -1 if no daugherboard
- * \return -2 if invalid EEPROM on daughterboard
- */
- virtual int daughterboard_id (int which_side) const = 0;
-
- /*!
- * \brief Clock ticks to delay rising of T/R signal
- * \sa write_atr_mask, write_atr_txval, write_atr_rxval
- */
- bool write_atr_tx_delay(int value);
-
- /*!
- * \brief Clock ticks to delay falling edge of T/R signal
- * \sa write_atr_mask, write_atr_txval, write_atr_rxval
- */
- bool write_atr_rx_delay(int value);
-
-
-\f // ================================================================
- // Routines to access and control daughterboard specific i/o
- //
- // Those with a common_ prefix access either the Tx or Rx side depending
- // on the txrx parameter. Those without the common_ prefix are virtual
- // and are overriden in usrp_basic_rx and usrp_basic_tx to access the
- // the Rx or Tx sides automatically. We provide the common_ versions
- // for those daughterboards such as the WBX and XCVR2450 that share
- // h/w resources (such as the LO) between the Tx and Rx sides.
-
- // ----------------------------------------------------------------
- // BEGIN common_ daughterboard control functions
-
- /*!
- * \brief Set Programmable Gain Amplifier(PGA)
- *
- * \param txrx Tx or Rx?
- * \param which_amp which amp [0,3]
- * \param gain_in_db gain value(linear in dB)
- *
- * gain is rounded to closest setting supported by hardware.
- *
- * \returns true iff sucessful.
- *
- * \sa pga_min(), pga_max(), pga_db_per_step()
- */
- bool common_set_pga(txrx_t txrx, int which_amp, double gain_in_db);
-
- /*!
- * \brief Return programmable gain amplifier gain setting in dB.
- *
- * \param txrx Tx or Rx?
- * \param which_amp which amp [0,3]
- */
- double common_pga(txrx_t txrx, int which_amp) const;
-
- /*!
- * \brief Return minimum legal PGA gain in dB.
- * \param txrx Tx or Rx?
- */
- double common_pga_min(txrx_t txrx) const;
-
- /*!
- * \brief Return maximum legal PGA gain in dB.
- * \param txrx Tx or Rx?
- */
- double common_pga_max(txrx_t txrx) const;
-
- /*!
- * \brief Return hardware step size of PGA(linear in dB).
- * \param txrx Tx or Rx?
- */
- double common_pga_db_per_step(txrx_t txrx) const;
-
- /*!
- * \brief Write direction register(output enables) for pins that go to daughterboard.
- *
- * \param txrx Tx or Rx?
- * \param which_side [0,1] which size
- * \param value value to write into register
- * \param mask which bits of value to write into reg
- *
- * Each d'board has 16-bits of general purpose i/o.
- * Setting the bit makes it an output from the FPGA to the d'board.
- *
- * This register is initialized based on a value stored in the
- * d'board EEPROM. In general, you shouldn't be using this routine
- * without a very good reason. Using this method incorrectly will
- * kill your USRP motherboard and/or daughterboard.
- */
- bool _common_write_oe(txrx_t txrx, int which_side, int value, int mask);
-
- /*!
- * \brief Write daughterboard i/o pin value
- *
- * \param txrx Tx or Rx?
- * \param which_side [0,1] which d'board
- * \param value value to write into register
- * \param mask which bits of value to write into reg
- */
- bool common_write_io(txrx_t txrx, int which_side, int value, int mask);
-
- /*!
- * \brief Read daughterboard i/o pin value
- *
- * \param txrx Tx or Rx?
- * \param which_side [0,1] which d'board
- * \param value output
- */
- bool common_read_io(txrx_t txrx, int which_side, int *value);
-
- /*!
- * \brief Read daughterboard i/o pin value
- *
- * \param txrx Tx or Rx?
- * \param which_side [0,1] which d'board
- * \returns register value if successful, else READ_FAILED
- */
- int common_read_io(txrx_t txrx, int which_side);
-
- /*!
- * \brief Write daughterboard refclk config register
- *
- * \param txrx Tx or Rx?
- * \param which_side [0,1] which d'board
- * \param value value to write into register, see below
- *
- * <pre>
- * Control whether a reference clock is sent to the daughterboards,
- * and what frequency. The refclk is sent on d'board i/o pin 0.
- *
- * 3 2 1
- * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-----------------------------------------------+-+------------+
- * | Reserved (Must be zero) |E| DIVISOR |
- * +-----------------------------------------------+-+------------+
- *
- * Bit 7 -- 1 turns on refclk, 0 allows IO use
- * Bits 6:0 Divider value
- * </pre>
- */
- bool common_write_refclk(txrx_t txrx, int which_side, int value);
-
- /*!
- * \brief Automatic Transmit/Receive switching
- * <pre>
- *
- * If automatic transmit/receive (ATR) switching is enabled in the
- * FR_ATR_CTL register, the presence or absence of data in the FPGA
- * transmit fifo selects between two sets of values for each of the 4
- * banks of daughterboard i/o pins.
- *
- * Each daughterboard slot has 3 16-bit registers associated with it:
- * FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
- *
- * FR_ATR_MASK_{0,1,2,3}:
- *
- * These registers determine which of the daugherboard i/o pins are
- * affected by ATR switching. If a bit in the mask is set, the
- * corresponding i/o bit is controlled by ATR, else it's output
- * value comes from the normal i/o pin output register:
- * FR_IO_{0,1,2,3}.
- *
- * FR_ATR_TXVAL_{0,1,2,3}:
- * FR_ATR_RXVAL_{0,1,2,3}:
- *
- * If the Tx fifo contains data, then the bits from TXVAL that are
- * selected by MASK are output. Otherwise, the bits from RXVAL that
- * are selected by MASK are output.
- * </pre>
- */
- bool common_write_atr_mask(txrx_t txrx, int which_side, int value);
- bool common_write_atr_txval(txrx_t txrx, int which_side, int value);
- bool common_write_atr_rxval(txrx_t txrx, int which_side, int value);
-
- /*!
- * \brief Write auxiliary digital to analog converter.
- *
- * \param txrx Tx or Rx?
- * \param which_side [0,1] which d'board
- * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
- * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
- * \param which_dac [2,3] TX slots must use only 2 and 3.
- * \param value [0,4095]
- * \returns true iff successful
- */
- bool common_write_aux_dac(txrx_t txrx, int which_side, int which_dac, int value);
-
- /*!
- * \brief Read auxiliary analog to digital converter.
- *
- * \param txrx Tx or Rx?
- * \param which_side [0,1] which d'board
- * \param which_adc [0,1]
- * \param value return 12-bit value [0,4095]
- * \returns true iff successful
- */
- bool common_read_aux_adc(txrx_t txrx, int which_side, int which_adc, int *value);
-
- /*!
- * \brief Read auxiliary analog to digital converter.
- *
- * \param txrx Tx or Rx?
- * \param which_side [0,1] which d'board
- * \param which_adc [0,1]
- * \returns value in the range [0,4095] if successful, else READ_FAILED.
- */
- int common_read_aux_adc(txrx_t txrx, int which_side, int which_adc);
-
- // END common_ daughterboard control functions\f
- // ----------------------------------------------------------------
- // BEGIN virtual daughterboard control functions
-
- /*!
- * \brief Set Programmable Gain Amplifier (PGA)
- *
- * \param which_amp which amp [0,3]
- * \param gain_in_db gain value (linear in dB)
- *
- * gain is rounded to closest setting supported by hardware.
- *
- * \returns true iff sucessful.
- *
- * \sa pga_min(), pga_max(), pga_db_per_step()
- */
- virtual bool set_pga (int which_amp, double gain_in_db) = 0;
-
- /*!
- * \brief Return programmable gain amplifier gain setting in dB.
- *
- * \param which_amp which amp [0,3]
- */
- virtual double pga (int which_amp) const = 0;
-
- /*!
- * \brief Return minimum legal PGA gain in dB.
- */
- virtual double pga_min () const = 0;
-
- /*!
- * \brief Return maximum legal PGA gain in dB.
- */
- virtual double pga_max () const = 0;
-
- /*!
- * \brief Return hardware step size of PGA (linear in dB).
- */
- virtual double pga_db_per_step () const = 0;
-
- /*!
- * \brief Write direction register (output enables) for pins that go to daughterboard.
- *
- * \param which_side [0,1] which size
- * \param value value to write into register
- * \param mask which bits of value to write into reg
- *
- * Each d'board has 16-bits of general purpose i/o.
- * Setting the bit makes it an output from the FPGA to the d'board.
- *
- * This register is initialized based on a value stored in the
- * d'board EEPROM. In general, you shouldn't be using this routine
- * without a very good reason. Using this method incorrectly will
- * kill your USRP motherboard and/or daughterboard.
- */
- virtual bool _write_oe (int which_side, int value, int mask) = 0;
-
- /*!
- * \brief Write daughterboard i/o pin value
- *
- * \param which_side [0,1] which d'board
- * \param value value to write into register
- * \param mask which bits of value to write into reg
- */
- virtual bool write_io (int which_side, int value, int mask) = 0;
-
- /*!
- * \brief Read daughterboard i/o pin value
- *
- * \param which_side [0,1] which d'board
- * \param value output
- */
- virtual bool read_io (int which_side, int *value) = 0;
-
- /*!
- * \brief Read daughterboard i/o pin value
- *
- * \param which_side [0,1] which d'board
- * \returns register value if successful, else READ_FAILED
- */
- virtual int read_io (int which_side) = 0;
-
- /*!
- * \brief Write daughterboard refclk config register
- *
- * \param which_side [0,1] which d'board
- * \param value value to write into register, see below
- *
- * <pre>
- * Control whether a reference clock is sent to the daughterboards,
- * and what frequency. The refclk is sent on d'board i/o pin 0.
- *
- * 3 2 1
- * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-----------------------------------------------+-+------------+
- * | Reserved (Must be zero) |E| DIVISOR |
- * +-----------------------------------------------+-+------------+
- *
- * Bit 7 -- 1 turns on refclk, 0 allows IO use
- * Bits 6:0 Divider value
- * </pre>
- */
- virtual bool write_refclk(int which_side, int value) = 0;
-
- virtual bool write_atr_mask(int which_side, int value) = 0;
- virtual bool write_atr_txval(int which_side, int value) = 0;
- virtual bool write_atr_rxval(int which_side, int value) = 0;
-
- /*!
- * \brief Write auxiliary digital to analog converter.
- *
- * \param which_side [0,1] which d'board
- * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
- * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
- * \param which_dac [2,3] TX slots must use only 2 and 3.
- * \param value [0,4095]
- * \returns true iff successful
- */
- virtual bool write_aux_dac (int which_side, int which_dac, int value) = 0;
-
- /*!
- * \brief Read auxiliary analog to digital converter.
- *
- * \param which_side [0,1] which d'board
- * \param which_adc [0,1]
- * \param value return 12-bit value [0,4095]
- * \returns true iff successful
- */
- virtual bool read_aux_adc (int which_side, int which_adc, int *value) = 0;
-
- /*!
- * \brief Read auxiliary analog to digital converter.
- *
- * \param which_side [0,1] which d'board
- * \param which_adc [0,1]
- * \returns value in the range [0,4095] if successful, else READ_FAILED.
- */
- virtual int read_aux_adc (int which_side, int which_adc) = 0;
-
- /*!
- * \brief returns current fusb block size
- */
- virtual int block_size() const = 0;
-
- /*!
- * \brief returns A/D or D/A converter rate in Hz
- */
- virtual long converter_rate() const = 0;
-
- // END virtual daughterboard control functions\f
-
- // ----------------------------------------------------------------
- // Low level implementation routines.
- // You probably shouldn't be using these...
- //
-
- bool _set_led (int which_led, bool on);
-
- /*!
- * \brief Write FPGA register.
- * \param regno 7-bit register number
- * \param value 32-bit value
- * \returns true iff successful
- */
- bool _write_fpga_reg (int regno, int value); //< 7-bit regno, 32-bit value
-
- /*!
- * \brief Read FPGA register.
- * \param regno 7-bit register number
- * \param value 32-bit value
- * \returns true iff successful
- */
- bool _read_fpga_reg (int regno, int *value); //< 7-bit regno, 32-bit value
-
- /*!
- * \brief Read FPGA register.
- * \param regno 7-bit register number
- * \returns register value if successful, else READ_FAILED
- */
- int _read_fpga_reg (int regno);
-
- /*!
- * \brief Write FPGA register with mask.
- * \param regno 7-bit register number
- * \param value 16-bit value
- * \param mask 16-bit value
- * \returns true if successful
- * Only use this for registers who actually implement a mask in the verilog firmware, like FR_RX_MASTER_SLAVE
- */
- bool _write_fpga_reg_masked (int regno, int value, int mask);
-
- /*!
- * \brief Write AD9862 register.
- * \param which_codec 0 or 1
- * \param regno 6-bit register number
- * \param value 8-bit value
- * \returns true iff successful
- */
- bool _write_9862 (int which_codec, int regno, unsigned char value);
-
- /*!
- * \brief Read AD9862 register.
- * \param which_codec 0 or 1
- * \param regno 6-bit register number
- * \param value 8-bit value
- * \returns true iff successful
- */
- bool _read_9862 (int which_codec, int regno, unsigned char *value) const;
-
- /*!
- * \brief Read AD9862 register.
- * \param which_codec 0 or 1
- * \param regno 6-bit register number
- * \returns register value if successful, else READ_FAILED
- */
- int _read_9862 (int which_codec, int regno) const;
-
- /*!
- * \brief Write data to SPI bus peripheral.
- *
- * \param optional_header 0,1 or 2 bytes to write before buf.
- * \param enables bitmask of peripherals to write. See usrp_spi_defs.h
- * \param format transaction format. See usrp_spi_defs.h SPI_FMT_*
- * \param buf the data to write
- * \returns true iff successful
- * Writes are limited to a maximum of 64 bytes.
- *
- * If \p format specifies that optional_header bytes are present, they are
- * written to the peripheral immediately prior to writing \p buf.
- */
- bool _write_spi (int optional_header, int enables, int format, std::string buf);
-
- /*
- * \brief Read data from SPI bus peripheral.
- *
- * \param optional_header 0,1 or 2 bytes to write before buf.
- * \param enables bitmask of peripheral to read. See usrp_spi_defs.h
- * \param format transaction format. See usrp_spi_defs.h SPI_FMT_*
- * \param len number of bytes to read. Must be in [0,64].
- * \returns the data read if sucessful, else a zero length string.
- *
- * Reads are limited to a maximum of 64 bytes.
- *
- * If \p format specifies that optional_header bytes are present, they
- * are written to the peripheral first. Then \p len bytes are read from
- * the peripheral and returned.
- */
- std::string _read_spi (int optional_header, int enables, int format, int len);
-
- /*!
- * \brief Start data transfers.
- * Called in base class to derived class order.
- */
- bool start ();
-
- /*!
- * \brief Stop data transfers.
- * Called in base class to derived class order.
- */
- bool stop ();
-};
-
-\f/*!
- * \brief class for accessing the receive side of the USRP
- * \ingroup usrp
- */
-class usrp_basic_rx : public usrp_basic
-{
-private:
- fusb_devhandle *d_devhandle;
- fusb_ephandle *d_ephandle;
- int d_bytes_seen; // how many bytes we've seen
- bool d_first_read;
- bool d_rx_enable;
-
-protected:
- /*!
- * \param which_board Which USRP board on usb (not particularly useful; use 0)
- * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
- * Use zero for a reasonable default.
- * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
- * \param fpga_filename name of the rbf file to load
- * \param firmware_filename name of ihx file to load
- */
- usrp_basic_rx (int which_board,
- int fusb_block_size=0,
- int fusb_nblocks=0,
- const std::string fpga_filename = "",
- const std::string firmware_filename = ""
- ); // throws if trouble
-
- bool set_rx_enable (bool on);
- bool rx_enable () const { return d_rx_enable; }
-
- bool disable_rx (); // conditional disable, return prev state
- void restore_rx (bool on); // conditional set
-
- void probe_rx_slots (bool verbose);
-
-public:
- ~usrp_basic_rx ();
-
- /*!
- * \brief invokes constructor, returns instance or 0 if trouble
- *
- * \param which_board Which USRP board on usb (not particularly useful; use 0)
- * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
- * Use zero for a reasonable default.
- * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
- * \param fpga_filename name of file that contains image to load into FPGA
- * \param firmware_filename name of file that contains image to load into FX2
- */
- static usrp_basic_rx *make (int which_board,
- int fusb_block_size=0,
- int fusb_nblocks=0,
- const std::string fpga_filename = "",
- const std::string firmware_filename = ""
- );
-
- /*!
- * \brief tell the fpga the rate rx samples are coming from the A/D's
- *
- * div = fpga_master_clock_freq () / sample_rate
- *
- * sample_rate is determined by a myriad of registers
- * in the 9862. That's why you have to tell us, so
- * we can tell the fpga.
- */
- bool set_fpga_rx_sample_rate_divisor (unsigned int div);
-
- /*!
- * \brief read data from the D/A's via the FPGA.
- * \p len must be a multiple of 512 bytes.
- *
- * \returns the number of bytes read, or -1 on error.
- *
- * If overrun is non-NULL it will be set true iff an RX overrun is detected.
- */
- int read (void *buf, int len, bool *overrun);
-
-
- //! sampling rate of A/D converter
- virtual long converter_rate() const { return fpga_master_clock_freq(); } // 64M
- long adc_rate() const { return converter_rate(); }
- int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; }
-
- bool set_pga (int which_amp, double gain_in_db);
- double pga (int which_amp) const;
- double pga_min () const;
- double pga_max () const;
- double pga_db_per_step () const;
-
- bool _write_oe (int which_side, int value, int mask);
- bool write_io (int which_side, int value, int mask);
- bool read_io (int which_side, int *value);
- int read_io (int which_side);
- bool write_refclk(int which_side, int value);
- bool write_atr_mask(int which_side, int value);
- bool write_atr_txval(int which_side, int value);
- bool write_atr_rxval(int which_side, int value);
-
- bool write_aux_dac (int which_side, int which_dac, int value);
- bool read_aux_adc (int which_side, int which_adc, int *value);
- int read_aux_adc (int which_side, int which_adc);
-
- int block_size() const;
-
- // called in base class to derived class order
- bool start ();
- bool stop ();
-};
-
-\f/*!
- * \brief class for accessing the transmit side of the USRP
- * \ingroup usrp
- */
-class usrp_basic_tx : public usrp_basic
-{
-private:
- fusb_devhandle *d_devhandle;
- fusb_ephandle *d_ephandle;
- int d_bytes_seen; // how many bytes we've seen
- bool d_first_write;
- bool d_tx_enable;
-
- protected:
- /*!
- * \param which_board Which USRP board on usb (not particularly useful; use 0)
- * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
- * Use zero for a reasonable default.
- * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
- * \param fpga_filename name of file that contains image to load into FPGA
- * \param firmware_filename name of file that contains image to load into FX2
- */
- usrp_basic_tx (int which_board,
- int fusb_block_size=0,
- int fusb_nblocks=0,
- const std::string fpga_filename = "",
- const std::string firmware_filename = ""
- ); // throws if trouble
-
- bool set_tx_enable (bool on);
- bool tx_enable () const { return d_tx_enable; }
-
- bool disable_tx (); // conditional disable, return prev state
- void restore_tx (bool on); // conditional set
-
- void probe_tx_slots (bool verbose);
-
-public:
-
- ~usrp_basic_tx ();
-
- /*!
- * \brief invokes constructor, returns instance or 0 if trouble
- *
- * \param which_board Which USRP board on usb (not particularly useful; use 0)
- * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
- * Use zero for a reasonable default.
- * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
- * \param fpga_filename name of file that contains image to load into FPGA
- * \param firmware_filename name of file that contains image to load into FX2
- */
- static usrp_basic_tx *make (int which_board, int fusb_block_size=0, int fusb_nblocks=0,
- const std::string fpga_filename = "",
- const std::string firmware_filename = ""
- );
-
- /*!
- * \brief tell the fpga the rate tx samples are going to the D/A's
- *
- * div = fpga_master_clock_freq () * 2
- *
- * sample_rate is determined by a myriad of registers
- * in the 9862. That's why you have to tell us, so
- * we can tell the fpga.
- */
- bool set_fpga_tx_sample_rate_divisor (unsigned int div);
-
- /*!
- * \brief Write data to the A/D's via the FPGA.
- *
- * \p len must be a multiple of 512 bytes.
- * \returns number of bytes written or -1 on error.
- *
- * if \p underrun is non-NULL, it will be set to true iff
- * a transmit underrun condition is detected.
- */
- int write (const void *buf, int len, bool *underrun);
-
- /*
- * Block until all outstanding writes have completed.
- * This is typically used to assist with benchmarking
- */
- void wait_for_completion ();
-
- //! sampling rate of D/A converter
- virtual long converter_rate() const { return fpga_master_clock_freq () * 2; } // 128M
- long dac_rate() const { return converter_rate(); }
- int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; }
-
- bool set_pga (int which_amp, double gain_in_db);
- double pga (int which_amp) const;
- double pga_min () const;
- double pga_max () const;
- double pga_db_per_step () const;
-
- bool _write_oe (int which_side, int value, int mask);
- bool write_io (int which_side, int value, int mask);
- bool read_io (int which_side, int *value);
- int read_io (int which_side);
- bool write_refclk(int which_side, int value);
- bool write_atr_mask(int which_side, int value);
- bool write_atr_txval(int which_side, int value);
- bool write_atr_rxval(int which_side, int value);
-
- bool write_aux_dac (int which_side, int which_dac, int value);
- bool read_aux_adc (int which_side, int which_adc, int *value);
- int read_aux_adc (int which_side, int which_adc);
-
- int block_size() const;
-
- // called in base class to derived class order
- bool start ();
- bool stop ();
-};
-
-#endif
#
# Copyright 2005,2009 Free Software Foundation, Inc.
-#
+#
# This file is part of GNU Radio
-#
+#
# GNU Radio is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
-#
+#
# GNU Radio is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
"WBX LO TX" 0x0050
"WBX LO RX" 0x0051
+"WBX NG TX" 0x0052
+"WBX NG RX" 0x0053
+
"XCVR2450 Tx" 0x0060
"XCVR2450 Rx" 0x0061
+++ /dev/null
-/templates
-/netgen
-/_ngo
-/_xmsgs
-/_pace.ucf
-/*.cmd
-/*.ibs
-/*.lfp
-/*.mfp
-/*.bit
-/*.bin
-/*.stx
-/*.par
-/*.unroutes
-/*.ntrc_log
-/*.ngr
-/*.mrp
-/*.html
-/*.lso
-/*.twr
-/*.bld
-/*.ncd
-/*.txt
-/*.cmd_log
-/*.drc
-/*.map
-/*.twr
-/*.xml
-/*.syr
-/*.ngm
-/*.xst
-/*.csv
-/*.html
-/*.lock
-/*.ncd
-/*.twx
-/*.ise_ISE_Backup
-/*.xml
-/*.ut
-/*.xpi
-/*.ngd
-/*.ncd
-/*.pad
-/*.bgn
-/*.ngc
-/*.pcf
-/*.ngd
-/xst
-/*.log
-/*.rpt
-/*.cel
-/*.restore
+++ /dev/null
-FILENAME=u2_fpga_top
-PARTNUM=xc3s1500-5fg456
-
-all: project command xst ngd ncd ncd2 bit
-
-xst:
- xst -ifn ${FILENAME}.cmd -ofn xst.log
-
-ngd:
- ngdbuild -nt timestamp -p ${PARTNUM} ${FILENAME}
-
-ncd:
- rm -rf ${FILENAME}.ncd
- map -detail -cm speed -k 8 -retiming on -equivalent_register_removal on -timing -ol high -pr b -p ${PARTNUM} ${FILENAME}.ngd -o ${FILENAME}.ncd ${FILENAME}.pcf
-
-# Place and route ncd file into new ncd file
-ncd2:
- par -ol high -xe n -w ${FILENAME}.ncd ${FILENAME} ${FILENAME}.pcf
-
-bit:
- bitgen -w ${FILENAME}.ncd -b ${FILENAME}.bit
-
-clean:
- @rm -rf ${FILENAME}.ngc *.lst *.bit *.lso *.xst *.stx *.syr \
- *.ngr *.cmd_log _ngc _xmsgs xst *.html *.srp \
- *.blc *.bld *.ise_ISE_Backup *~ \
- *.pad *.ngm *.ngd *.par *.pcf *.unroutes \
- *.xpi *.bgn *.drc *.bin *.mrp *.csv *.txt \
- *.rbt *.ncd ${FILENAME} *_cg templates/ tmp/ \
- output.dat coregen.log *.ngo *.log ${FILENAME}.map \
- ${FILENAME}_summary.xml ${FILENAME}_usage.xml ${FILENAME}.twr
-
-command:
- rm -rf ${FILENAME}.cmd
- @echo "identification" >> ${FILENAME}.cmd
- @echo "status" >> ${FILENAME}.cmd
- @echo "time short" >> ${FILENAME}.cmd
- @echo "memory on" >> ${FILENAME}.cmd
- @echo "run " >> ${FILENAME}.cmd
- @echo "-top ${FILENAME}" >> ${FILENAME}.cmd
- @echo "-ifn ${FILENAME}.prj" >> ${FILENAME}.cmd
- @echo "-ifmt Verilog " >> ${FILENAME}.cmd
- @echo "-ofn ${FILENAME} " >> ${FILENAME}.cmd
- @echo "-p ${PARTNUM}" >> ${FILENAME}.cmd
- @echo "-bufg 6" >> ${FILENAME}.cmd
- @echo "-vlgincdir { ../../opencores/i2c/rtl/verilog ../../eth/rtl/verilog/ ../../opencores/spi/rtl/verilog}" >> ${FILENAME}.cmd
-
-project:
- rm -f ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/TECH/duram.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/sign_extend.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/cordic_stage.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/cic_int_shifter.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/cic_dec_shifter.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_regfile.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_fetch.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_decode.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_control.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_aslu.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/miim/eth_shiftreg.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/miim/eth_outputcontrol.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/miim/eth_clockgen.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/TECH/eth_clk_switch.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/TECH/eth_clk_div2.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/Reg_int.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/RMON/RMON_dpram.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/RMON/RMON_ctrl.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/RMON/RMON_addr_gen.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx/flow_ctrl.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx/Ramdon_gen.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx/CRC_gen.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_rx/CRC_chk.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/ram_2port.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/cordic.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/cic_interp.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/cic_decim.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/spi/rtl/verilog/spi_shift.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/spi/rtl/verilog/spi_clgen.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/eth_miim.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/RMON.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/Phy_int.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_rx.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/Clk_ctrl.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/strobe_gen.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/ss_rcvr.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/shortfifo.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/setting_reg.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/mux8.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/mux4.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/longfifo.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/decoder_3_8.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/buffer_int.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/CRC16_D16.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/tx_control.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/rx_control.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/dsp_core_tx.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/dsp_core_rx.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/spi/rtl/verilog/spi_top.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/simple_pic/rtl/simple_pic.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_top.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_top.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/mac_txfifo_int.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/mac_rxfifo_int.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/wb_readback_mux.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/wb_1master.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/timer.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/system_control.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/settings_bus.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/serdes_tx.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/serdes_rx.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/ram_wb_harvard.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/ram_loader.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/nsgpio.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/buffer_pool.v" ' >> ${FILENAME}.prj
- @echo '`include "../u2_basic/u2_basic.v" ' >> ${FILENAME}.prj
- @echo '`include "u2_fpga_top.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/elastic_buffer.v" ' >> ${FILENAME}.prj
+++ /dev/null
-NET "adc_a[0]" LOC = "A14" ;
-NET "adc_a[10]" LOC = "D20" ;
-NET "adc_a[11]" LOC = "D19" ;
-NET "adc_a[12]" LOC = "D21" ;
-NET "adc_a[13]" LOC = "E18" ;
-NET "adc_a[1]" LOC = "B14" ;
-NET "adc_a[2]" LOC = "C13" ;
-NET "adc_a[3]" LOC = "D13" ;
-NET "adc_a[4]" LOC = "A13" ;
-NET "adc_a[5]" LOC = "B13" ;
-NET "adc_a[6]" LOC = "E12" ;
-NET "adc_a[7]" LOC = "C22" ;
-NET "adc_a[8]" LOC = "C20" ;
-NET "adc_a[9]" LOC = "C21" ;
-NET "adc_b[0]" LOC = "A12" ;
-NET "adc_b[10]" LOC = "D18" ;
-NET "adc_b[11]" LOC = "B18" ;
-NET "adc_b[12]" LOC = "D17" ;
-NET "adc_b[13]" LOC = "E17" ;
-NET "adc_b[1]" LOC = "E16" ;
-NET "adc_b[2]" LOC = "F12" ;
-NET "adc_b[3]" LOC = "F13" ;
-NET "adc_b[4]" LOC = "F16" ;
-NET "adc_b[5]" LOC = "F17" ;
-NET "adc_b[6]" LOC = "C19" ;
-NET "adc_b[7]" LOC = "B20" ;
-NET "adc_b[8]" LOC = "B19" ;
-NET "adc_b[9]" LOC = "C18" ;
-NET "clk_en[0]" LOC = "C4" ;
-NET "clk_en[1]" LOC = "D1" ;
-NET "clk_sel[0]" LOC = "C3" ;
-NET "clk_sel[1]" LOC = "C2" ;
-NET "dac_a[0]" LOC = "A5" ;
-NET "dac_a[10]" LOC = "L2" ;
-NET "dac_a[11]" LOC = "L4" ;
-NET "dac_a[12]" LOC = "L3" ;
-NET "dac_a[13]" LOC = "L6" ;
-NET "dac_a[14]" LOC = "L5" ;
-NET "dac_a[15]" LOC = "K2" ;
-NET "dac_a[1]" LOC = "B5" ;
-NET "dac_a[2]" LOC = "C5" ;
-NET "dac_a[3]" LOC = "D5" ;
-NET "dac_a[4]" LOC = "A4" ;
-NET "dac_a[5]" LOC = "B4" ;
-NET "dac_a[6]" LOC = "F6" ;
-NET "dac_a[7]" LOC = "D10" ;
-NET "dac_a[8]" LOC = "D9" ;
-NET "dac_a[9]" LOC = "A10" ;
-NET "dac_b[0]" LOC = "D11" ;
-NET "dac_b[10]" LOC = "F9" ;
-NET "dac_b[11]" LOC = "A8" ;
-NET "dac_b[12]" LOC = "B8" ;
-NET "dac_b[13]" LOC = "D7" ;
-NET "dac_b[14]" LOC = "E7" ;
-NET "dac_b[15]" LOC = "B6" ;
-NET "dac_b[1]" LOC = "E11" ;
-NET "dac_b[2]" LOC = "F11" ;
-NET "dac_b[3]" LOC = "B10" ;
-NET "dac_b[4]" LOC = "C10" ;
-NET "dac_b[5]" LOC = "E10" ;
-NET "dac_b[6]" LOC = "F10" ;
-NET "dac_b[7]" LOC = "A9" ;
-NET "dac_b[8]" LOC = "B9" ;
-NET "dac_b[9]" LOC = "E9" ;
-NET "debug[0]" LOC = "N5" ;
-NET "debug[10]" LOC = "R4" ;
-NET "debug[11]" LOC = "T3" ;
-NET "debug[12]" LOC = "U3" ;
-NET "debug[13]" LOC = "M2" ;
-NET "debug[14]" LOC = "M3" ;
-NET "debug[15]" LOC = "M4" ;
-NET "debug[16]" LOC = "M5" ;
-NET "debug[17]" LOC = "M6" ;
-NET "debug[18]" LOC = "N1" ;
-NET "debug[19]" LOC = "N2" ;
-NET "debug[1]" LOC = "N6" ;
-NET "debug[20]" LOC = "N3" ;
-NET "debug[21]" LOC = "T1" ;
-NET "debug[22]" LOC = "T2" ;
-NET "debug[23]" LOC = "U2" ;
-NET "debug[24]" LOC = "T4" ;
-NET "debug[25]" LOC = "U4" ;
-NET "debug[26]" LOC = "T5" ;
-NET "debug[27]" LOC = "T6" ;
-NET "debug[28]" LOC = "U5" ;
-NET "debug[29]" LOC = "V5" ;
-NET "debug[2]" LOC = "P1" ;
-NET "debug[30]" LOC = "W2" ;
-NET "debug[31]" LOC = "W3" ;
-NET "debug[3]" LOC = "P2" ;
-NET "debug[4]" LOC = "P4" ;
-NET "debug[5]" LOC = "P5" ;
-NET "debug[6]" LOC = "R1" ;
-NET "debug[7]" LOC = "R2" ;
-NET "debug[8]" LOC = "P6" ;
-NET "debug[9]" LOC = "R5" ;
-NET "debug_clk[0]" LOC = "N4" ;
-NET "debug_clk[1]" LOC = "M1" ;
-NET "GMII_RXD[0]" LOC = "AA15" ;
-NET "GMII_RXD[1]" LOC = "AB15" ;
-NET "GMII_RXD[2]" LOC = "U14" ;
-NET "GMII_RXD[3]" LOC = "V14" ;
-NET "GMII_RXD[4]" LOC = "U13" ;
-NET "GMII_RXD[5]" LOC = "V13" ;
-NET "GMII_RXD[6]" LOC = "Y13" ;
-NET "GMII_RXD[7]" LOC = "AA13" ;
-NET "GMII_TXD[0]" LOC = "W14" ;
-NET "GMII_TXD[1]" LOC = "AA20" ;
-NET "GMII_TXD[2]" LOC = "AB20" ;
-NET "GMII_TXD[3]" LOC = "Y18" ;
-NET "GMII_TXD[4]" LOC = "AA18" ;
-NET "GMII_TXD[5]" LOC = "AB18" ;
-NET "GMII_TXD[6]" LOC = "V17" ;
-NET "GMII_TXD[7]" LOC = "W17" ;
-NET "io_rx[0]" LOC = "L21" ;
-NET "io_rx[10]" LOC = "F21" ;
-NET "io_rx[11]" LOC = "F20" ;
-NET "io_rx[12]" LOC = "G19" ;
-NET "io_rx[13]" LOC = "G18" ;
-NET "io_rx[14]" LOC = "G17" ;
-NET "io_rx[15]" LOC = "E22" ;
-NET "io_rx[1]" LOC = "L20" ;
-NET "io_rx[2]" LOC = "L19" ;
-NET "io_rx[3]" LOC = "L18" ;
-NET "io_rx[4]" LOC = "L17" ;
-NET "io_rx[5]" LOC = "K22" ;
-NET "io_rx[6]" LOC = "K21" ;
-NET "io_rx[7]" LOC = "K20" ;
-NET "io_rx[8]" LOC = "G22" ;
-NET "io_rx[9]" LOC = "G21" ;
-NET "io_tx[0]" LOC = "K4" ;
-NET "io_tx[10]" LOC = "E1" ;
-NET "io_tx[11]" LOC = "E3" ;
-NET "io_tx[12]" LOC = "F4" ;
-NET "io_tx[13]" LOC = "D2" ;
-NET "io_tx[14]" LOC = "D4" ;
-NET "io_tx[15]" LOC = "E4" ;
-NET "io_tx[1]" LOC = "K3" ;
-NET "io_tx[2]" LOC = "G1" ;
-NET "io_tx[3]" LOC = "G5" ;
-NET "io_tx[4]" LOC = "H5" ;
-NET "io_tx[5]" LOC = "F3" ;
-NET "io_tx[6]" LOC = "F2" ;
-NET "io_tx[7]" LOC = "F5" ;
-NET "io_tx[8]" LOC = "G6" ;
-NET "io_tx[9]" LOC = "E2" ;
-NET "RAM_A[0]" LOC = "N22" ;
-NET "RAM_A[10]" LOC = "P18" ;
-NET "RAM_A[11]" LOC = "R19" ;
-NET "RAM_A[12]" LOC = "P19" ;
-NET "RAM_A[13]" LOC = "R21" ;
-NET "RAM_A[14]" LOC = "R22" ;
-NET "RAM_A[15]" LOC = "T19" ;
-NET "RAM_A[16]" LOC = "T20" ;
-NET "RAM_A[17]" LOC = "U20" ;
-NET "RAM_A[18]" LOC = "W19" ;
-NET "RAM_A[1]" LOC = "N20" ;
-NET "RAM_A[2]" LOC = "T21" ;
-NET "RAM_A[3]" LOC = "M22" ;
-NET "RAM_A[4]" LOC = "N19" ;
-NET "RAM_A[5]" LOC = "N17" ;
-NET "RAM_A[6]" LOC = "N18" ;
-NET "RAM_A[7]" LOC = "P21" ;
-NET "RAM_A[8]" LOC = "P22" ;
-NET "RAM_A[9]" LOC = "P17" ;
-NET "RAM_D[0]" LOC = "Y21" ;
-NET "RAM_D[10]" LOC = "V22" ;
-NET "RAM_D[11]" LOC = "V21" ;
-NET "RAM_D[12]" LOC = "T17" ;
-NET "RAM_D[13]" LOC = "U18" ;
-NET "RAM_D[14]" LOC = "U21" ;
-NET "RAM_D[15]" LOC = "R18" ;
-NET "RAM_D[16]" LOC = "T18" ;
-NET "RAM_D[17]" LOC = "T22" ;
-NET "RAM_D[1]" LOC = "Y20" ;
-NET "RAM_D[2]" LOC = "Y19" ;
-NET "RAM_D[3]" LOC = "W22" ;
-NET "RAM_D[4]" LOC = "Y22" ;
-NET "RAM_D[5]" LOC = "V19" ;
-NET "RAM_D[6]" LOC = "W21" ;
-NET "RAM_D[7]" LOC = "W20" ;
-NET "RAM_D[8]" LOC = "U19" ;
-NET "RAM_D[9]" LOC = "V20" ;
-NET "ser_r[0]" LOC = "AB10" ;
-NET "ser_r[10]" LOC = "W10" ;
-NET "ser_r[11]" LOC = "Y1" ;
-NET "ser_r[12]" LOC = "Y3" ;
-NET "ser_r[13]" LOC = "Y2" ;
-NET "ser_r[14]" LOC = "W4" ;
-NET "ser_r[15]" LOC = "W1" ;
-NET "ser_r[1]" LOC = "AA10" ;
-NET "ser_r[2]" LOC = "U9" ;
-NET "ser_r[3]" LOC = "U6" ;
-NET "ser_r[4]" LOC = "AB11" ;
-NET "ser_r[5]" LOC = "Y7" ;
-NET "ser_r[6]" LOC = "W7" ;
-NET "ser_r[7]" LOC = "AB7" ;
-NET "ser_r[8]" LOC = "AA7" ;
-NET "ser_r[9]" LOC = "W9" ;
-NET "ser_t[0]" LOC = "V7" ;
-NET "ser_t[10]" LOC = "AA6" ;
-NET "ser_t[11]" LOC = "Y6" ;
-NET "ser_t[12]" LOC = "W8" ;
-NET "ser_t[13]" LOC = "V8" ;
-NET "ser_t[14]" LOC = "AB8" ;
-NET "ser_t[15]" LOC = "AA8" ;
-NET "ser_t[1]" LOC = "V10" ;
-NET "ser_t[2]" LOC = "AB4" ;
-NET "ser_t[3]" LOC = "AA4" ;
-NET "ser_t[4]" LOC = "Y5" ;
-NET "ser_t[5]" LOC = "W5" ;
-NET "ser_t[6]" LOC = "AB5" ;
-NET "ser_t[7]" LOC = "AA5" ;
-NET "ser_t[8]" LOC = "W6" ;
-NET "ser_t[9]" LOC = "V6" ;
-NET "clk_muxed" TNM_NET = "clk_muxed";
-TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %;
-NET "clk_to_mac" TNM_NET = "clk_to_mac";
-TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
-NET "cpld_clk" TNM_NET = "cpld_clk";
-TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
-NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
-TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
-NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
-TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
-#PACE: Start of Constraints generated by PACE
-
-#PACE: Start of PACE I/O Pin Assignments
-NET "adc_oen_a" LOC = "E19" ;
-NET "adc_oen_b" LOC = "C17" ;
-NET "adc_ovf_a" LOC = "F18" ;
-NET "adc_ovf_b" LOC = "B17" ;
-NET "adc_pdn_a" LOC = "E20" ;
-NET "adc_pdn_b" LOC = "D15" ;
-NET "clk_fpga_n" LOC = "B11" ;
-NET "clk_fpga_p" LOC = "A11" ;
-NET "clk_func" LOC = "C12" ;
-NET "clk_status" LOC = "B12" ;
-NET "clk_to_mac" LOC = "AB12" ;
-NET "cpld_clk" LOC = "AB14" ;
-NET "cpld_din" LOC = "AA14" ;
-NET "cpld_done" LOC = "V12" ;
-NET "cpld_mode" LOC = "U12" ;
-NET "cpld_start" LOC = "AA9" ;
-NET "exp_pps_in_n" LOC = "V4" ;
-NET "exp_pps_in_p" LOC = "V3" ;
-NET "exp_pps_out_n" LOC = "V2" ;
-NET "exp_pps_out_p" LOC = "V1" ;
-NET "GMII_COL" LOC = "U16" ;
-NET "GMII_CRS" LOC = "U17" ;
-NET "GMII_GTX_CLK" LOC = "AA17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_RX_CLK" LOC = "W16" ;
-NET "GMII_RX_DV" LOC = "AB16" ;
-NET "GMII_RX_ER" LOC = "AA16" ;
-NET "GMII_TX_CLK" LOC = "W13" ;
-NET "GMII_TX_EN" LOC = "Y17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_TX_ER" LOC = "V16" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_TXD<0>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_TXD<1>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_TXD<2>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_TXD<3>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_TXD<4>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_TXD<5>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_TXD<6>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_TXD<7>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "led1" LOC = "V11" ;
-NET "led2" LOC = "Y12" ;
-NET "MDC" LOC = "V18" ;
-NET "MDIO" LOC = "Y16" | PULLUP ;
-NET "PHY_CLK" LOC = "V15" ;
-NET "PHY_INTn" LOC = "AB13" ;
-NET "PHY_RESETn" LOC = "AA19" ;
-NET "pps_in" LOC = "Y11" ;
-NET "RAM_CE1n" LOC = "N21" ;
-NET "RAM_CENn" LOC = "M18" ;
-NET "RAM_CLK" LOC = "M17" ;
-NET "RAM_LDn" LOC = "M21" ;
-NET "RAM_OEn" LOC = "M19" ;
-NET "RAM_WEn" LOC = "M20" ;
-NET "SCL" LOC = "A7" ;
-NET "SCL_force" LOC = "E8" ;
-NET "sclk" LOC = "K5" ;
-NET "sclk_rx_adc" LOC = "J17" ;
-NET "sclk_rx_dac" LOC = "J19" ;
-NET "sclk_rx_db" LOC = "F19" ;
-NET "sclk_tx_adc" LOC = "H1" ;
-NET "sclk_tx_dac" LOC = "J5" ;
-NET "sclk_tx_db" LOC = "D3" ;
-NET "SDA" LOC = "D8" ;
-NET "SDA_force" LOC = "C11" ;
-NET "sdi" LOC = "J1" ;
-NET "sdi_rx_adc" LOC = "H22" ;
-NET "sdi_rx_dac" LOC = "J21" ;
-NET "sdi_rx_db" LOC = "H19" ;
-NET "sdi_tx_adc" LOC = "J4" ;
-NET "sdi_tx_dac" LOC = "J6" ;
-NET "sdi_tx_db" LOC = "G4" ;
-NET "sdo" LOC = "J2" ;
-NET "sdo_rx_adc" LOC = "H21" ;
-NET "sdo_rx_db" LOC = "G20" ;
-NET "sdo_tx_adc" LOC = "H2" ;
-NET "sdo_tx_db" LOC = "G3" ;
-NET "sen_clk" LOC = "K6" ;
-NET "sen_dac" LOC = "L1" ;
-NET "sen_rx_adc" LOC = "H18" ;
-NET "sen_rx_dac" LOC = "J18" ;
-NET "sen_rx_db" LOC = "D22" ;
-NET "sen_tx_adc" LOC = "G2" ;
-NET "sen_tx_dac" LOC = "H4" ;
-NET "sen_tx_db" LOC = "C1" ;
-NET "ser_enable" LOC = "W11" ;
-NET "ser_loopen" LOC = "Y4" ;
-NET "ser_prbsen" LOC = "AA3" ;
-NET "ser_rklsb" LOC = "V9" ;
-NET "ser_rkmsb" LOC = "Y10" ;
-NET "ser_rx_clk" LOC = "AA11" ;
-NET "ser_rx_en" LOC = "AB9" ;
-NET "ser_tklsb" LOC = "U10" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_tkmsb" LOC = "U11" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_tx_clk" LOC = "U7" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<0>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<1>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<2>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<3>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<4>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<5>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<6>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<7>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<8>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<9>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<10>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<11>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<12>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<13>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<14>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<15>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-#PACE: Start of PACE Area Constraints
-
-#PACE: Start of PACE Prohibit Constraints
-
-#PACE: End of Constraints generated by PACE
+++ /dev/null
-verilog work "../../opencores/uart16550/rtl/verilog/raminfr.v"
-verilog work "../../control_lib/ram_2port.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_tfifo.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_rfifo.v"
-verilog work "../../coregen/fifo_generator_v4_1.v"
-verilog work "../../control_lib/shortfifo.v"
-verilog work "../../control_lib/longfifo.v"
-verilog work "../../sdr_lib/sign_extend.v"
-verilog work "../../sdr_lib/cordic_stage.v"
-verilog work "../../sdr_lib/cic_int_shifter.v"
-verilog work "../../sdr_lib/cic_dec_shifter.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_transmitter.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_sync_flops.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_receiver.v"
-verilog work "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_xecu.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_regf.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_ibuf.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_ctrl.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_bpcu.v"
-verilog work "../../opencores/8b10b/encode_8b10b.v"
-verilog work "../../opencores/8b10b/decode_8b10b.v"
-verilog work "../../eth/rtl/verilog/miim/eth_shiftreg.v"
-verilog work "../../eth/rtl/verilog/miim/eth_outputcontrol.v"
-verilog work "../../eth/rtl/verilog/miim/eth_clockgen.v"
-verilog work "../../eth/rtl/verilog/Reg_int.v"
-verilog work "../../eth/rtl/verilog/RMON/RMON_ctrl.v"
-verilog work "../../eth/rtl/verilog/RMON/RMON_addr_gen.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/Random_gen.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/CRC_gen.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v"
-verilog work "../../control_lib/ss_rcvr.v"
-verilog work "../../control_lib/cascadefifo2.v"
-verilog work "../../control_lib/CRC16_D16.v"
-verilog work "../../timing/time_sender.v"
-verilog work "../../timing/time_receiver.v"
-verilog work "../../serdes/serdes_tx.v"
-verilog work "../../serdes/serdes_rx.v"
-verilog work "../../serdes/serdes_fc_tx.v"
-verilog work "../../serdes/serdes_fc_rx.v"
-verilog work "../../sdr_lib/round.v"
-verilog work "../../sdr_lib/cordic.v"
-verilog work "../../sdr_lib/cic_interp.v"
-verilog work "../../sdr_lib/cic_decim.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_wb.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_regs.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_debug_if.v"
-verilog work "../../opencores/spi/rtl/verilog/spi_shift.v"
-verilog work "../../opencores/spi/rtl/verilog/spi_clgen.v"
-verilog work "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_edk32.v"
-verilog work "../../eth/rtl/verilog/flow_ctrl_tx.v"
-verilog work "../../eth/rtl/verilog/flow_ctrl_rx.v"
-verilog work "../../eth/rtl/verilog/eth_miim.v"
-verilog work "../../eth/rtl/verilog/RMON.v"
-verilog work "../../eth/rtl/verilog/Phy_int.v"
-verilog work "../../eth/rtl/verilog/MAC_tx.v"
-verilog work "../../eth/rtl/verilog/MAC_rx.v"
-verilog work "../../eth/rtl/verilog/Clk_ctrl.v"
-verilog work "../../control_lib/strobe_gen.v"
-verilog work "../../control_lib/setting_reg.v"
-verilog work "../../control_lib/mux8.v"
-verilog work "../../control_lib/mux4.v"
-verilog work "../../control_lib/icache.v"
-verilog work "../../control_lib/dpram32.v"
-verilog work "../../control_lib/decoder_3_8.v"
-verilog work "../../control_lib/dcache.v"
-verilog work "../../control_lib/buffer_int.v"
-verilog work "../../timing/timer.v"
-verilog work "../../timing/time_sync.v"
-verilog work "../../serdes/serdes.v"
-verilog work "../../sdr_lib/tx_control.v"
-verilog work "../../sdr_lib/rx_control.v"
-verilog work "../../sdr_lib/dsp_core_tx.v"
-verilog work "../../sdr_lib/dsp_core_rx.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_top.v"
-verilog work "../../opencores/spi/rtl/verilog/spi_top.v"
-verilog work "../../opencores/simple_pic/rtl/simple_pic.v"
-verilog work "../../opencores/i2c/rtl/verilog/i2c_master_top.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v"
-verilog work "../../eth/rtl/verilog/MAC_top.v"
-verilog work "../../eth/mac_txfifo_int.v"
-verilog work "../../eth/mac_rxfifo_int.v"
-verilog work "../../control_lib/wb_readback_mux.v"
-verilog work "../../control_lib/wb_1master.v"
-verilog work "../../control_lib/system_control.v"
-verilog work "../../control_lib/settings_bus.v"
-verilog work "../../control_lib/ram_loader.v"
-verilog work "../../control_lib/ram_harv_cache.v"
-verilog work "../../control_lib/nsgpio.v"
-verilog work "../../control_lib/extram_interface.v"
-verilog work "../../control_lib/buffer_pool.v"
-verilog work "../../control_lib/atr_controller.v"
-verilog work "../u2_basic/u2_basic.v"
-verilog work "u2_fpga_top.v"
+++ /dev/null
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-
-module u2_fpga_top
- (
- // Misc, debug
- output led1,
- output led2,
- output [31:0] debug,
- output [1:0] debug_clk,
-
- // Expansion
- input exp_pps_in_p, // Diff
- input exp_pps_in_n, // Diff
- output exp_pps_out_p, // Diff
- output exp_pps_out_n, // Diff
-
- // GMII
- // GMII-CTRL
- input GMII_COL,
- input GMII_CRS,
-
- // GMII-TX
- output reg [7:0] GMII_TXD,
- output reg GMII_TX_EN,
- output reg GMII_TX_ER,
- output GMII_GTX_CLK,
- input GMII_TX_CLK, // 100mbps clk
-
- // GMII-RX
- input [7:0] GMII_RXD,
- input GMII_RX_CLK,
- input GMII_RX_DV,
- input GMII_RX_ER,
-
- // GMII-Management
- inout MDIO,
- output MDC,
- input PHY_INTn, // open drain
- output PHY_RESETn,
- input PHY_CLK, // possibly use on-board osc
-
- // RAM
- inout [17:0] RAM_D,
- output [18:0] RAM_A,
- output RAM_CE1n,
- output RAM_CENn,
- output RAM_CLK,
- output RAM_WEn,
- output RAM_OEn,
- output RAM_LDn,
-
- // SERDES
- output ser_enable,
- output ser_prbsen,
- output ser_loopen,
- output ser_rx_en,
-
- output ser_tx_clk,
- output reg [15:0] ser_t,
- output reg ser_tklsb,
- output reg ser_tkmsb,
-
- input ser_rx_clk,
- input [15:0] ser_r,
- input ser_rklsb,
- input ser_rkmsb,
-
- // CPLD interface
- output cpld_start, // AA9
- output cpld_mode, // U12
- output cpld_done, // V12
- input cpld_din, // AA14 Now shared with CFG_Din
- input cpld_clk, // AB14 serial clock
-
- // ADC
- input [13:0] adc_a,
- input adc_ovf_a,
- output adc_oen_a,
- output adc_pdn_a,
-
- input [13:0] adc_b,
- input adc_ovf_b,
- output adc_oen_b,
- output adc_pdn_b,
-
- // DAC
- output [15:0] dac_a,
- output [15:0] dac_b,
-
- // I2C
- inout SCL,
- inout SDA,
- input SCL_force,
- input SDA_force,
-
- // Clock Gen Control
- output [1:0] clk_en,
- output [1:0] clk_sel,
- input clk_func, // FIXME is an input to control the 9510
- input clk_status,
-
- // Clocks
- input clk_fpga_p, // Diff
- input clk_fpga_n, // Diff
- input clk_to_mac,
- input pps_in,
-
- // Generic SPI
- output sclk,
- output sen_clk,
- output sen_dac,
- output sdi,
- input sdo,
-
- // TX DBoard
- output sen_tx_db,
- output sclk_tx_db,
- input sdo_tx_db,
- output sdi_tx_db,
-
- output sen_tx_adc,
- output sclk_tx_adc,
- input sdo_tx_adc,
- output sdi_tx_adc,
-
- output sen_tx_dac,
- output sclk_tx_dac,
- output sdi_tx_dac,
-
- inout [15:0] io_tx,
-
- // RX DBoard
- output sen_rx_db,
- output sclk_rx_db,
- input sdo_rx_db,
- output sdi_rx_db,
-
- output sen_rx_adc,
- output sclk_rx_adc,
- input sdo_rx_adc,
- output sdi_rx_adc,
-
- output sen_rx_dac,
- output sclk_rx_dac,
- output sdi_rx_dac,
-
- inout [15:0] io_rx
- );
-
- // FPGA-specific pins connections
- wire aux_clk = PHY_CLK;
- //wire cpld_detached = RAM_A[14]; // FIXME Hacked on with Blue Wire
- wire cpld_detached = SDA_force; // FIXME Hacked on with Blue Wire
-
- wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
-
- IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
- defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
-
- wire exp_pps_in;
- IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
- defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25";
-
- wire exp_pps_out;
- OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
- defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25";
-
- reg [5:0] clock_ready_d;
- always @(posedge aux_clk)
- clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
-
- wire dcm_rst = ~&clock_ready_d & |clock_ready_d;
- wire clk_muxed = clock_ready ? clk_fpga : aux_clk;
-
- wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
- assign adc_oen_a = ~adc_oe_a;
- assign adc_oen_b = ~adc_oe_b;
- assign adc_pdn_a = ~adc_on_a;
- assign adc_pdn_b = ~adc_on_b;
-
- // Handle Clocks
- DCM DCM_INST (.CLKFB(dsp_clk),
- .CLKIN(clk_muxed),
- .DSSEN(0),
- .PSCLK(0),
- .PSEN(0),
- .PSINCDEC(0),
- .RST(dcm_rst),
- .CLKDV(clk_div),
- .CLKFX(),
- .CLKFX180(),
- .CLK0(dcm_out),
- .CLK2X(),
- .CLK2X180(),
- .CLK90(),
- .CLK180(),
- .CLK270(),
- .LOCKED(LOCKED_OUT),
- .PSDONE(),
- .STATUS());
- defparam DCM_INST.CLK_FEEDBACK = "1X";
- defparam DCM_INST.CLKDV_DIVIDE = 2.0;
- defparam DCM_INST.CLKFX_DIVIDE = 1;
- defparam DCM_INST.CLKFX_MULTIPLY = 4;
- defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
- defparam DCM_INST.CLKIN_PERIOD = 10.000;
- defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
- defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
- defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
- defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
- defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
- defparam DCM_INST.FACTORY_JF = 16'h8080;
- defparam DCM_INST.PHASE_SHIFT = 0;
- defparam DCM_INST.STARTUP_WAIT = "FALSE";
-
- BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
- BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
-
- // I2C -- Don't use external transistors for open drain, the FPGA implements this
- IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
- IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
-
- // LEDs are active low outputs
- wire led1_int, led2_int;
- assign led1 = ~led1_int;
- assign led2 = ~led2_int;
-
- // SPI
- wire miso, mosi, sclk_int;
- assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
- assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
- assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
- assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
- assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
- assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
- assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
-
- assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) |
- (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
- (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
-
- wire GMII_TX_EN_unreg, GMII_TX_ER_unreg;
- wire [7:0] GMII_TXD_unreg;
- wire GMII_GTX_CLK_int;
-
- always @(posedge GMII_GTX_CLK_int)
- begin
- GMII_TX_EN <= GMII_TX_EN_unreg;
- GMII_TX_ER <= GMII_TX_ER_unreg;
- GMII_TXD <= GMII_TXD_unreg;
- end
-
- OFDDRRSE OFDDRRSE_gmii_inst
- (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port)
- .C0(GMII_GTX_CLK_int), // 0 degree clock input
- .C1(~GMII_GTX_CLK_int), // 180 degree clock input
- .CE(1), // Clock enable input
- .D0(0), // Posedge data input
- .D1(1), // Negedge data input
- .R(0), // Synchronous reset input
- .S(0) // Synchronous preset input
- );
-
- wire ser_tklsb_unreg, ser_tkmsb_unreg;
- wire [15:0] ser_t_unreg;
- wire ser_tx_clk_int;
-
- always @(posedge ser_tx_clk_int)
- begin
- ser_tklsb <= ser_tklsb_unreg;
- ser_tkmsb <= ser_tkmsb_unreg;
- ser_t <= ser_t_unreg;
- end
-
- assign ser_tx_clk = clk_fpga;
-
- reg [15:0] ser_r_int;
- reg ser_rklsb_int, ser_rkmsb_int;
-
- always @(posedge ser_rx_clk)
- begin
- ser_r_int <= ser_r;
- ser_rklsb_int <= ser_rklsb;
- ser_rkmsb_int <= ser_rkmsb;
- end
-
- /*
- OFDDRRSE OFDDRRSE_serdes_inst
- (.Q(ser_tx_clk), // Data output (connect directly to top-level port)
- .C0(ser_tx_clk_int), // 0 degree clock input
- .C1(~ser_tx_clk_int), // 180 degree clock input
- .CE(1), // Clock enable input
- .D0(0), // Posedge data input
- .D1(1), // Negedge data input
- .R(0), // Synchronous reset input
- .S(0) // Synchronous preset input
- );
- */
- u2_basic u2_basic(.dsp_clk (dsp_clk),
- .wb_clk (wb_clk),
- .clock_ready (clock_ready),
- .clk_to_mac (clk_to_mac),
- .pps_in (pps_in),
- .led1 (led1_int),
- .led2 (led2_int),
- .debug (debug[31:0]),
- .debug_clk (debug_clk[1:0]),
- .exp_pps_in (exp_pps_in),
- .exp_pps_out (exp_pps_out),
- .GMII_COL (GMII_COL),
- .GMII_CRS (GMII_CRS),
- .GMII_TXD (GMII_TXD_unreg[7:0]),
- .GMII_TX_EN (GMII_TX_EN_unreg),
- .GMII_TX_ER (GMII_TX_ER_unreg),
- .GMII_GTX_CLK (GMII_GTX_CLK_int),
- .GMII_TX_CLK (GMII_TX_CLK),
- .GMII_RXD (GMII_RXD[7:0]),
- .GMII_RX_CLK (GMII_RX_CLK),
- .GMII_RX_DV (GMII_RX_DV),
- .GMII_RX_ER (GMII_RX_ER),
- .MDIO (MDIO),
- .MDC (MDC),
- .PHY_INTn (PHY_INTn),
- .PHY_RESETn (PHY_RESETn),
- .PHY_CLK (PHY_CLK),
- .ser_enable (ser_enable),
- .ser_prbsen (ser_prbsen),
- .ser_loopen (ser_loopen),
- .ser_rx_en (ser_rx_en),
- .ser_tx_clk (ser_tx_clk_int),
- .ser_t (ser_t_unreg[15:0]),
- .ser_tklsb (ser_tklsb_unreg),
- .ser_tkmsb (ser_tkmsb_unreg),
- .ser_rx_clk (ser_rx_clk),
- .ser_r (ser_r_int[15:0]),
- .ser_rklsb (ser_rklsb_int),
- .ser_rkmsb (ser_rkmsb_int),
- .cpld_start (cpld_start),
- .cpld_mode (cpld_mode),
- .cpld_done (cpld_done),
- .cpld_din (cpld_din),
- .cpld_clk (cpld_clk),
- .cpld_detached (cpld_detached),
- .adc_a (adc_a[13:0]),
- .adc_ovf_a (adc_ovf_a),
- .adc_on_a (adc_on_a),
- .adc_oe_a (adc_oe_a),
- .adc_b (adc_b[13:0]),
- .adc_ovf_b (adc_ovf_b),
- .adc_on_b (adc_on_b),
- .adc_oe_b (adc_oe_b),
- .dac_a (dac_a[15:0]),
- .dac_b (dac_b[15:0]),
- .scl_pad_i (scl_pad_i),
- .scl_pad_o (scl_pad_o),
- .scl_pad_oen_o (scl_pad_oen_o),
- .sda_pad_i (sda_pad_i),
- .sda_pad_o (sda_pad_o),
- .sda_pad_oen_o (sda_pad_oen_o),
- .clk_en (clk_en[1:0]),
- .clk_sel (clk_sel[1:0]),
- .clk_func (clk_func),
- .clk_status (clk_status),
- .sclk (sclk_int),
- .mosi (mosi),
- .miso (miso),
- .sen_clk (sen_clk),
- .sen_dac (sen_dac),
- .sen_tx_db (sen_tx_db),
- .sen_tx_adc (sen_tx_adc),
- .sen_tx_dac (sen_tx_dac),
- .sen_rx_db (sen_rx_db),
- .sen_rx_adc (sen_rx_adc),
- .sen_rx_dac (sen_rx_dac),
- .io_tx (io_tx[15:0]),
- .io_rx (io_rx[15:0]),
- .RAM_D (RAM_D),
- .RAM_A (RAM_A),
- .RAM_CE1n (RAM_CE1n),
- .RAM_CENn (RAM_CENn),
- .RAM_CLK (RAM_CLK),
- .RAM_WEn (RAM_WEn),
- .RAM_OEn (RAM_OEn),
- .RAM_LDn (RAM_LDn),
- .uart_tx_o (),
- .uart_rx_i (),
- .uart_baud_o (),
- .sim_mode (1'b0),
- .clock_divider (2)
- );
-
-endmodule // u2_fpga_top
--- /dev/null
+/templates
+/netgen
+/_ngo
+/_xmsgs
+/_pace.ucf
+/*.cmd
+/*.ibs
+/*.lfp
+/*.mfp
+/*.bit
+/*.bin
+/*.stx
+/*.par
+/*.unroutes
+/*.ntrc_log
+/*.ngr
+/*.mrp
+/*.html
+/*.lso
+/*.twr
+/*.bld
+/*.ncd
+/*.txt
+/*.cmd_log
+/*.drc
+/*.map
+/*.twr
+/*.xml
+/*.syr
+/*.ngm
+/*.xst
+/*.csv
+/*.html
+/*.lock
+/*.ncd
+/*.twx
+/*.ise_ISE_Backup
+/*.xml
+/*.ut
+/*.xpi
+/*.ngd
+/*.ncd
+/*.pad
+/*.bgn
+/*.ngc
+/*.pcf
+/*.ngd
+/xst
+/*.log
+/*.rpt
+/*.cel
+/*.restore
--- /dev/null
+FILENAME=u2_fpga_top
+PARTNUM=xc3s1500-5fg456
+
+all: project command xst ngd ncd ncd2 bit
+
+xst:
+ xst -ifn ${FILENAME}.cmd -ofn xst.log
+
+ngd:
+ ngdbuild -nt timestamp -p ${PARTNUM} ${FILENAME}
+
+ncd:
+ rm -rf ${FILENAME}.ncd
+ map -detail -cm speed -k 8 -retiming on -equivalent_register_removal on -timing -ol high -pr b -p ${PARTNUM} ${FILENAME}.ngd -o ${FILENAME}.ncd ${FILENAME}.pcf
+
+# Place and route ncd file into new ncd file
+ncd2:
+ par -ol high -xe n -w ${FILENAME}.ncd ${FILENAME} ${FILENAME}.pcf
+
+bit:
+ bitgen -w ${FILENAME}.ncd -b ${FILENAME}.bit
+
+clean:
+ @rm -rf ${FILENAME}.ngc *.lst *.bit *.lso *.xst *.stx *.syr \
+ *.ngr *.cmd_log _ngc _xmsgs xst *.html *.srp \
+ *.blc *.bld *.ise_ISE_Backup *~ \
+ *.pad *.ngm *.ngd *.par *.pcf *.unroutes \
+ *.xpi *.bgn *.drc *.bin *.mrp *.csv *.txt \
+ *.rbt *.ncd ${FILENAME} *_cg templates/ tmp/ \
+ output.dat coregen.log *.ngo *.log ${FILENAME}.map \
+ ${FILENAME}_summary.xml ${FILENAME}_usage.xml ${FILENAME}.twr
+
+command:
+ rm -rf ${FILENAME}.cmd
+ @echo "identification" >> ${FILENAME}.cmd
+ @echo "status" >> ${FILENAME}.cmd
+ @echo "time short" >> ${FILENAME}.cmd
+ @echo "memory on" >> ${FILENAME}.cmd
+ @echo "run " >> ${FILENAME}.cmd
+ @echo "-top ${FILENAME}" >> ${FILENAME}.cmd
+ @echo "-ifn ${FILENAME}.prj" >> ${FILENAME}.cmd
+ @echo "-ifmt Verilog " >> ${FILENAME}.cmd
+ @echo "-ofn ${FILENAME} " >> ${FILENAME}.cmd
+ @echo "-p ${PARTNUM}" >> ${FILENAME}.cmd
+ @echo "-bufg 6" >> ${FILENAME}.cmd
+ @echo "-vlgincdir { ../../opencores/i2c/rtl/verilog ../../eth/rtl/verilog/ ../../opencores/spi/rtl/verilog}" >> ${FILENAME}.cmd
+
+project:
+ rm -f ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/TECH/duram.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/sign_extend.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/cordic_stage.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/cic_int_shifter.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/cic_dec_shifter.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_regfile.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_fetch.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_decode.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_control.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_aslu.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/miim/eth_shiftreg.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/miim/eth_outputcontrol.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/miim/eth_clockgen.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/TECH/eth_clk_switch.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/TECH/eth_clk_div2.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/Reg_int.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/RMON/RMON_dpram.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/RMON/RMON_ctrl.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/RMON/RMON_addr_gen.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_tx/flow_ctrl.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_tx/Ramdon_gen.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_tx/CRC_gen.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_rx/CRC_chk.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/ram_2port.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/cordic.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/cic_interp.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/cic_decim.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/spi/rtl/verilog/spi_shift.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/spi/rtl/verilog/spi_clgen.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/eth_miim.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/RMON.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/Phy_int.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_tx.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_rx.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/Clk_ctrl.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/strobe_gen.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/ss_rcvr.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/shortfifo.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/setting_reg.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/mux8.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/mux4.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/longfifo.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/decoder_3_8.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/buffer_int.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/CRC16_D16.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/tx_control.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/rx_control.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/dsp_core_tx.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/dsp_core_rx.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/spi/rtl/verilog/spi_top.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/simple_pic/rtl/simple_pic.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_top.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_top.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/mac_txfifo_int.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/mac_rxfifo_int.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/wb_readback_mux.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/wb_1master.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/timer.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/system_control.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/settings_bus.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/serdes_tx.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/serdes_rx.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/ram_wb_harvard.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/ram_loader.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/nsgpio.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/buffer_pool.v" ' >> ${FILENAME}.prj
+ @echo '`include "../u2_basic/u2_basic.v" ' >> ${FILENAME}.prj
+ @echo '`include "u2_fpga_top.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/elastic_buffer.v" ' >> ${FILENAME}.prj
--- /dev/null
+NET "adc_a[0]" LOC = "A14" ;
+NET "adc_a[10]" LOC = "D20" ;
+NET "adc_a[11]" LOC = "D19" ;
+NET "adc_a[12]" LOC = "D21" ;
+NET "adc_a[13]" LOC = "E18" ;
+NET "adc_a[1]" LOC = "B14" ;
+NET "adc_a[2]" LOC = "C13" ;
+NET "adc_a[3]" LOC = "D13" ;
+NET "adc_a[4]" LOC = "A13" ;
+NET "adc_a[5]" LOC = "B13" ;
+NET "adc_a[6]" LOC = "E12" ;
+NET "adc_a[7]" LOC = "C22" ;
+NET "adc_a[8]" LOC = "C20" ;
+NET "adc_a[9]" LOC = "C21" ;
+NET "adc_b[0]" LOC = "A12" ;
+NET "adc_b[10]" LOC = "D18" ;
+NET "adc_b[11]" LOC = "B18" ;
+NET "adc_b[12]" LOC = "D17" ;
+NET "adc_b[13]" LOC = "E17" ;
+NET "adc_b[1]" LOC = "E16" ;
+NET "adc_b[2]" LOC = "F12" ;
+NET "adc_b[3]" LOC = "F13" ;
+NET "adc_b[4]" LOC = "F16" ;
+NET "adc_b[5]" LOC = "F17" ;
+NET "adc_b[6]" LOC = "C19" ;
+NET "adc_b[7]" LOC = "B20" ;
+NET "adc_b[8]" LOC = "B19" ;
+NET "adc_b[9]" LOC = "C18" ;
+NET "clk_en[0]" LOC = "C4" ;
+NET "clk_en[1]" LOC = "D1" ;
+NET "clk_sel[0]" LOC = "C3" ;
+NET "clk_sel[1]" LOC = "C2" ;
+NET "dac_a[0]" LOC = "A5" ;
+NET "dac_a[10]" LOC = "L2" ;
+NET "dac_a[11]" LOC = "L4" ;
+NET "dac_a[12]" LOC = "L3" ;
+NET "dac_a[13]" LOC = "L6" ;
+NET "dac_a[14]" LOC = "L5" ;
+NET "dac_a[15]" LOC = "K2" ;
+NET "dac_a[1]" LOC = "B5" ;
+NET "dac_a[2]" LOC = "C5" ;
+NET "dac_a[3]" LOC = "D5" ;
+NET "dac_a[4]" LOC = "A4" ;
+NET "dac_a[5]" LOC = "B4" ;
+NET "dac_a[6]" LOC = "F6" ;
+NET "dac_a[7]" LOC = "D10" ;
+NET "dac_a[8]" LOC = "D9" ;
+NET "dac_a[9]" LOC = "A10" ;
+NET "dac_b[0]" LOC = "D11" ;
+NET "dac_b[10]" LOC = "F9" ;
+NET "dac_b[11]" LOC = "A8" ;
+NET "dac_b[12]" LOC = "B8" ;
+NET "dac_b[13]" LOC = "D7" ;
+NET "dac_b[14]" LOC = "E7" ;
+NET "dac_b[15]" LOC = "B6" ;
+NET "dac_b[1]" LOC = "E11" ;
+NET "dac_b[2]" LOC = "F11" ;
+NET "dac_b[3]" LOC = "B10" ;
+NET "dac_b[4]" LOC = "C10" ;
+NET "dac_b[5]" LOC = "E10" ;
+NET "dac_b[6]" LOC = "F10" ;
+NET "dac_b[7]" LOC = "A9" ;
+NET "dac_b[8]" LOC = "B9" ;
+NET "dac_b[9]" LOC = "E9" ;
+NET "debug[0]" LOC = "N5" ;
+NET "debug[10]" LOC = "R4" ;
+NET "debug[11]" LOC = "T3" ;
+NET "debug[12]" LOC = "U3" ;
+NET "debug[13]" LOC = "M2" ;
+NET "debug[14]" LOC = "M3" ;
+NET "debug[15]" LOC = "M4" ;
+NET "debug[16]" LOC = "M5" ;
+NET "debug[17]" LOC = "M6" ;
+NET "debug[18]" LOC = "N1" ;
+NET "debug[19]" LOC = "N2" ;
+NET "debug[1]" LOC = "N6" ;
+NET "debug[20]" LOC = "N3" ;
+NET "debug[21]" LOC = "T1" ;
+NET "debug[22]" LOC = "T2" ;
+NET "debug[23]" LOC = "U2" ;
+NET "debug[24]" LOC = "T4" ;
+NET "debug[25]" LOC = "U4" ;
+NET "debug[26]" LOC = "T5" ;
+NET "debug[27]" LOC = "T6" ;
+NET "debug[28]" LOC = "U5" ;
+NET "debug[29]" LOC = "V5" ;
+NET "debug[2]" LOC = "P1" ;
+NET "debug[30]" LOC = "W2" ;
+NET "debug[31]" LOC = "W3" ;
+NET "debug[3]" LOC = "P2" ;
+NET "debug[4]" LOC = "P4" ;
+NET "debug[5]" LOC = "P5" ;
+NET "debug[6]" LOC = "R1" ;
+NET "debug[7]" LOC = "R2" ;
+NET "debug[8]" LOC = "P6" ;
+NET "debug[9]" LOC = "R5" ;
+NET "debug_clk[0]" LOC = "N4" ;
+NET "debug_clk[1]" LOC = "M1" ;
+NET "GMII_RXD[0]" LOC = "AA15" ;
+NET "GMII_RXD[1]" LOC = "AB15" ;
+NET "GMII_RXD[2]" LOC = "U14" ;
+NET "GMII_RXD[3]" LOC = "V14" ;
+NET "GMII_RXD[4]" LOC = "U13" ;
+NET "GMII_RXD[5]" LOC = "V13" ;
+NET "GMII_RXD[6]" LOC = "Y13" ;
+NET "GMII_RXD[7]" LOC = "AA13" ;
+NET "GMII_TXD[0]" LOC = "W14" ;
+NET "GMII_TXD[1]" LOC = "AA20" ;
+NET "GMII_TXD[2]" LOC = "AB20" ;
+NET "GMII_TXD[3]" LOC = "Y18" ;
+NET "GMII_TXD[4]" LOC = "AA18" ;
+NET "GMII_TXD[5]" LOC = "AB18" ;
+NET "GMII_TXD[6]" LOC = "V17" ;
+NET "GMII_TXD[7]" LOC = "W17" ;
+NET "io_rx[0]" LOC = "L21" ;
+NET "io_rx[10]" LOC = "F21" ;
+NET "io_rx[11]" LOC = "F20" ;
+NET "io_rx[12]" LOC = "G19" ;
+NET "io_rx[13]" LOC = "G18" ;
+NET "io_rx[14]" LOC = "G17" ;
+NET "io_rx[15]" LOC = "E22" ;
+NET "io_rx[1]" LOC = "L20" ;
+NET "io_rx[2]" LOC = "L19" ;
+NET "io_rx[3]" LOC = "L18" ;
+NET "io_rx[4]" LOC = "L17" ;
+NET "io_rx[5]" LOC = "K22" ;
+NET "io_rx[6]" LOC = "K21" ;
+NET "io_rx[7]" LOC = "K20" ;
+NET "io_rx[8]" LOC = "G22" ;
+NET "io_rx[9]" LOC = "G21" ;
+NET "io_tx[0]" LOC = "K4" ;
+NET "io_tx[10]" LOC = "E1" ;
+NET "io_tx[11]" LOC = "E3" ;
+NET "io_tx[12]" LOC = "F4" ;
+NET "io_tx[13]" LOC = "D2" ;
+NET "io_tx[14]" LOC = "D4" ;
+NET "io_tx[15]" LOC = "E4" ;
+NET "io_tx[1]" LOC = "K3" ;
+NET "io_tx[2]" LOC = "G1" ;
+NET "io_tx[3]" LOC = "G5" ;
+NET "io_tx[4]" LOC = "H5" ;
+NET "io_tx[5]" LOC = "F3" ;
+NET "io_tx[6]" LOC = "F2" ;
+NET "io_tx[7]" LOC = "F5" ;
+NET "io_tx[8]" LOC = "G6" ;
+NET "io_tx[9]" LOC = "E2" ;
+NET "RAM_A[0]" LOC = "N22" ;
+NET "RAM_A[10]" LOC = "P18" ;
+NET "RAM_A[11]" LOC = "R19" ;
+NET "RAM_A[12]" LOC = "P19" ;
+NET "RAM_A[13]" LOC = "R21" ;
+NET "RAM_A[14]" LOC = "R22" ;
+NET "RAM_A[15]" LOC = "T19" ;
+NET "RAM_A[16]" LOC = "T20" ;
+NET "RAM_A[17]" LOC = "U20" ;
+NET "RAM_A[18]" LOC = "W19" ;
+NET "RAM_A[1]" LOC = "N20" ;
+NET "RAM_A[2]" LOC = "T21" ;
+NET "RAM_A[3]" LOC = "M22" ;
+NET "RAM_A[4]" LOC = "N19" ;
+NET "RAM_A[5]" LOC = "N17" ;
+NET "RAM_A[6]" LOC = "N18" ;
+NET "RAM_A[7]" LOC = "P21" ;
+NET "RAM_A[8]" LOC = "P22" ;
+NET "RAM_A[9]" LOC = "P17" ;
+NET "RAM_D[0]" LOC = "Y21" ;
+NET "RAM_D[10]" LOC = "V22" ;
+NET "RAM_D[11]" LOC = "V21" ;
+NET "RAM_D[12]" LOC = "T17" ;
+NET "RAM_D[13]" LOC = "U18" ;
+NET "RAM_D[14]" LOC = "U21" ;
+NET "RAM_D[15]" LOC = "R18" ;
+NET "RAM_D[16]" LOC = "T18" ;
+NET "RAM_D[17]" LOC = "T22" ;
+NET "RAM_D[1]" LOC = "Y20" ;
+NET "RAM_D[2]" LOC = "Y19" ;
+NET "RAM_D[3]" LOC = "W22" ;
+NET "RAM_D[4]" LOC = "Y22" ;
+NET "RAM_D[5]" LOC = "V19" ;
+NET "RAM_D[6]" LOC = "W21" ;
+NET "RAM_D[7]" LOC = "W20" ;
+NET "RAM_D[8]" LOC = "U19" ;
+NET "RAM_D[9]" LOC = "V20" ;
+NET "ser_r[0]" LOC = "AB10" ;
+NET "ser_r[10]" LOC = "W10" ;
+NET "ser_r[11]" LOC = "Y1" ;
+NET "ser_r[12]" LOC = "Y3" ;
+NET "ser_r[13]" LOC = "Y2" ;
+NET "ser_r[14]" LOC = "W4" ;
+NET "ser_r[15]" LOC = "W1" ;
+NET "ser_r[1]" LOC = "AA10" ;
+NET "ser_r[2]" LOC = "U9" ;
+NET "ser_r[3]" LOC = "U6" ;
+NET "ser_r[4]" LOC = "AB11" ;
+NET "ser_r[5]" LOC = "Y7" ;
+NET "ser_r[6]" LOC = "W7" ;
+NET "ser_r[7]" LOC = "AB7" ;
+NET "ser_r[8]" LOC = "AA7" ;
+NET "ser_r[9]" LOC = "W9" ;
+NET "ser_t[0]" LOC = "V7" ;
+NET "ser_t[10]" LOC = "AA6" ;
+NET "ser_t[11]" LOC = "Y6" ;
+NET "ser_t[12]" LOC = "W8" ;
+NET "ser_t[13]" LOC = "V8" ;
+NET "ser_t[14]" LOC = "AB8" ;
+NET "ser_t[15]" LOC = "AA8" ;
+NET "ser_t[1]" LOC = "V10" ;
+NET "ser_t[2]" LOC = "AB4" ;
+NET "ser_t[3]" LOC = "AA4" ;
+NET "ser_t[4]" LOC = "Y5" ;
+NET "ser_t[5]" LOC = "W5" ;
+NET "ser_t[6]" LOC = "AB5" ;
+NET "ser_t[7]" LOC = "AA5" ;
+NET "ser_t[8]" LOC = "W6" ;
+NET "ser_t[9]" LOC = "V6" ;
+NET "clk_muxed" TNM_NET = "clk_muxed";
+TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %;
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
+NET "adc_oen_a" LOC = "E19" ;
+NET "adc_oen_b" LOC = "C17" ;
+NET "adc_ovf_a" LOC = "F18" ;
+NET "adc_ovf_b" LOC = "B17" ;
+NET "adc_pdn_a" LOC = "E20" ;
+NET "adc_pdn_b" LOC = "D15" ;
+NET "clk_fpga_n" LOC = "B11" ;
+NET "clk_fpga_p" LOC = "A11" ;
+NET "clk_func" LOC = "C12" ;
+NET "clk_status" LOC = "B12" ;
+NET "clk_to_mac" LOC = "AB12" ;
+NET "cpld_clk" LOC = "AB14" ;
+NET "cpld_din" LOC = "AA14" ;
+NET "cpld_done" LOC = "V12" ;
+NET "cpld_mode" LOC = "U12" ;
+NET "cpld_start" LOC = "AA9" ;
+NET "exp_pps_in_n" LOC = "V4" ;
+NET "exp_pps_in_p" LOC = "V3" ;
+NET "exp_pps_out_n" LOC = "V2" ;
+NET "exp_pps_out_p" LOC = "V1" ;
+NET "GMII_COL" LOC = "U16" ;
+NET "GMII_CRS" LOC = "U17" ;
+NET "GMII_GTX_CLK" LOC = "AA17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_RX_CLK" LOC = "W16" ;
+NET "GMII_RX_DV" LOC = "AB16" ;
+NET "GMII_RX_ER" LOC = "AA16" ;
+NET "GMII_TX_CLK" LOC = "W13" ;
+NET "GMII_TX_EN" LOC = "Y17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TX_ER" LOC = "V16" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD<0>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD<1>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD<2>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD<3>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD<4>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD<5>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD<6>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD<7>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "led1" LOC = "V11" ;
+NET "led2" LOC = "Y12" ;
+NET "MDC" LOC = "V18" ;
+NET "MDIO" LOC = "Y16" | PULLUP ;
+NET "PHY_CLK" LOC = "V15" ;
+NET "PHY_INTn" LOC = "AB13" ;
+NET "PHY_RESETn" LOC = "AA19" ;
+NET "pps_in" LOC = "Y11" ;
+NET "RAM_CE1n" LOC = "N21" ;
+NET "RAM_CENn" LOC = "M18" ;
+NET "RAM_CLK" LOC = "M17" ;
+NET "RAM_LDn" LOC = "M21" ;
+NET "RAM_OEn" LOC = "M19" ;
+NET "RAM_WEn" LOC = "M20" ;
+NET "SCL" LOC = "A7" ;
+NET "SCL_force" LOC = "E8" ;
+NET "sclk" LOC = "K5" ;
+NET "sclk_rx_adc" LOC = "J17" ;
+NET "sclk_rx_dac" LOC = "J19" ;
+NET "sclk_rx_db" LOC = "F19" ;
+NET "sclk_tx_adc" LOC = "H1" ;
+NET "sclk_tx_dac" LOC = "J5" ;
+NET "sclk_tx_db" LOC = "D3" ;
+NET "SDA" LOC = "D8" ;
+NET "SDA_force" LOC = "C11" ;
+NET "sdi" LOC = "J1" ;
+NET "sdi_rx_adc" LOC = "H22" ;
+NET "sdi_rx_dac" LOC = "J21" ;
+NET "sdi_rx_db" LOC = "H19" ;
+NET "sdi_tx_adc" LOC = "J4" ;
+NET "sdi_tx_dac" LOC = "J6" ;
+NET "sdi_tx_db" LOC = "G4" ;
+NET "sdo" LOC = "J2" ;
+NET "sdo_rx_adc" LOC = "H21" ;
+NET "sdo_rx_db" LOC = "G20" ;
+NET "sdo_tx_adc" LOC = "H2" ;
+NET "sdo_tx_db" LOC = "G3" ;
+NET "sen_clk" LOC = "K6" ;
+NET "sen_dac" LOC = "L1" ;
+NET "sen_rx_adc" LOC = "H18" ;
+NET "sen_rx_dac" LOC = "J18" ;
+NET "sen_rx_db" LOC = "D22" ;
+NET "sen_tx_adc" LOC = "G2" ;
+NET "sen_tx_dac" LOC = "H4" ;
+NET "sen_tx_db" LOC = "C1" ;
+NET "ser_enable" LOC = "W11" ;
+NET "ser_loopen" LOC = "Y4" ;
+NET "ser_prbsen" LOC = "AA3" ;
+NET "ser_rklsb" LOC = "V9" ;
+NET "ser_rkmsb" LOC = "Y10" ;
+NET "ser_rx_clk" LOC = "AA11" ;
+NET "ser_rx_en" LOC = "AB9" ;
+NET "ser_tklsb" LOC = "U10" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_tkmsb" LOC = "U11" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_tx_clk" LOC = "U7" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<0>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<1>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<2>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<3>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<4>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<5>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<6>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<7>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<8>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<9>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<10>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<11>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<12>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<13>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<14>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<15>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
+#PACE: End of Constraints generated by PACE
--- /dev/null
+verilog work "../../opencores/uart16550/rtl/verilog/raminfr.v"
+verilog work "../../control_lib/ram_2port.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_tfifo.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_rfifo.v"
+verilog work "../../coregen/fifo_generator_v4_1.v"
+verilog work "../../control_lib/shortfifo.v"
+verilog work "../../control_lib/longfifo.v"
+verilog work "../../sdr_lib/sign_extend.v"
+verilog work "../../sdr_lib/cordic_stage.v"
+verilog work "../../sdr_lib/cic_int_shifter.v"
+verilog work "../../sdr_lib/cic_dec_shifter.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_transmitter.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_sync_flops.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_receiver.v"
+verilog work "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_xecu.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_regf.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_ibuf.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_ctrl.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_bpcu.v"
+verilog work "../../opencores/8b10b/encode_8b10b.v"
+verilog work "../../opencores/8b10b/decode_8b10b.v"
+verilog work "../../eth/rtl/verilog/miim/eth_shiftreg.v"
+verilog work "../../eth/rtl/verilog/miim/eth_outputcontrol.v"
+verilog work "../../eth/rtl/verilog/miim/eth_clockgen.v"
+verilog work "../../eth/rtl/verilog/Reg_int.v"
+verilog work "../../eth/rtl/verilog/RMON/RMON_ctrl.v"
+verilog work "../../eth/rtl/verilog/RMON/RMON_addr_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/Random_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/CRC_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v"
+verilog work "../../control_lib/ss_rcvr.v"
+verilog work "../../control_lib/cascadefifo2.v"
+verilog work "../../control_lib/CRC16_D16.v"
+verilog work "../../timing/time_sender.v"
+verilog work "../../timing/time_receiver.v"
+verilog work "../../serdes/serdes_tx.v"
+verilog work "../../serdes/serdes_rx.v"
+verilog work "../../serdes/serdes_fc_tx.v"
+verilog work "../../serdes/serdes_fc_rx.v"
+verilog work "../../sdr_lib/round.v"
+verilog work "../../sdr_lib/cordic.v"
+verilog work "../../sdr_lib/cic_interp.v"
+verilog work "../../sdr_lib/cic_decim.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_wb.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_regs.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_debug_if.v"
+verilog work "../../opencores/spi/rtl/verilog/spi_shift.v"
+verilog work "../../opencores/spi/rtl/verilog/spi_clgen.v"
+verilog work "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_edk32.v"
+verilog work "../../eth/rtl/verilog/flow_ctrl_tx.v"
+verilog work "../../eth/rtl/verilog/flow_ctrl_rx.v"
+verilog work "../../eth/rtl/verilog/eth_miim.v"
+verilog work "../../eth/rtl/verilog/RMON.v"
+verilog work "../../eth/rtl/verilog/Phy_int.v"
+verilog work "../../eth/rtl/verilog/MAC_tx.v"
+verilog work "../../eth/rtl/verilog/MAC_rx.v"
+verilog work "../../eth/rtl/verilog/Clk_ctrl.v"
+verilog work "../../control_lib/strobe_gen.v"
+verilog work "../../control_lib/setting_reg.v"
+verilog work "../../control_lib/mux8.v"
+verilog work "../../control_lib/mux4.v"
+verilog work "../../control_lib/icache.v"
+verilog work "../../control_lib/dpram32.v"
+verilog work "../../control_lib/decoder_3_8.v"
+verilog work "../../control_lib/dcache.v"
+verilog work "../../control_lib/buffer_int.v"
+verilog work "../../timing/timer.v"
+verilog work "../../timing/time_sync.v"
+verilog work "../../serdes/serdes.v"
+verilog work "../../sdr_lib/tx_control.v"
+verilog work "../../sdr_lib/rx_control.v"
+verilog work "../../sdr_lib/dsp_core_tx.v"
+verilog work "../../sdr_lib/dsp_core_rx.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_top.v"
+verilog work "../../opencores/spi/rtl/verilog/spi_top.v"
+verilog work "../../opencores/simple_pic/rtl/simple_pic.v"
+verilog work "../../opencores/i2c/rtl/verilog/i2c_master_top.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v"
+verilog work "../../eth/rtl/verilog/MAC_top.v"
+verilog work "../../eth/mac_txfifo_int.v"
+verilog work "../../eth/mac_rxfifo_int.v"
+verilog work "../../control_lib/wb_readback_mux.v"
+verilog work "../../control_lib/wb_1master.v"
+verilog work "../../control_lib/system_control.v"
+verilog work "../../control_lib/settings_bus.v"
+verilog work "../../control_lib/ram_loader.v"
+verilog work "../../control_lib/ram_harv_cache.v"
+verilog work "../../control_lib/nsgpio.v"
+verilog work "../../control_lib/extram_interface.v"
+verilog work "../../control_lib/buffer_pool.v"
+verilog work "../../control_lib/atr_controller.v"
+verilog work "../u2_basic/u2_basic.v"
+verilog work "u2_fpga_top.v"
--- /dev/null
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u2_fpga_top
+ (
+ // Misc, debug
+ output led1,
+ output led2,
+ output [31:0] debug,
+ output [1:0] debug_clk,
+
+ // Expansion
+ input exp_pps_in_p, // Diff
+ input exp_pps_in_n, // Diff
+ output exp_pps_out_p, // Diff
+ output exp_pps_out_n, // Diff
+
+ // GMII
+ // GMII-CTRL
+ input GMII_COL,
+ input GMII_CRS,
+
+ // GMII-TX
+ output reg [7:0] GMII_TXD,
+ output reg GMII_TX_EN,
+ output reg GMII_TX_ER,
+ output GMII_GTX_CLK,
+ input GMII_TX_CLK, // 100mbps clk
+
+ // GMII-RX
+ input [7:0] GMII_RXD,
+ input GMII_RX_CLK,
+ input GMII_RX_DV,
+ input GMII_RX_ER,
+
+ // GMII-Management
+ inout MDIO,
+ output MDC,
+ input PHY_INTn, // open drain
+ output PHY_RESETn,
+ input PHY_CLK, // possibly use on-board osc
+
+ // RAM
+ inout [17:0] RAM_D,
+ output [18:0] RAM_A,
+ output RAM_CE1n,
+ output RAM_CENn,
+ output RAM_CLK,
+ output RAM_WEn,
+ output RAM_OEn,
+ output RAM_LDn,
+
+ // SERDES
+ output ser_enable,
+ output ser_prbsen,
+ output ser_loopen,
+ output ser_rx_en,
+
+ output ser_tx_clk,
+ output reg [15:0] ser_t,
+ output reg ser_tklsb,
+ output reg ser_tkmsb,
+
+ input ser_rx_clk,
+ input [15:0] ser_r,
+ input ser_rklsb,
+ input ser_rkmsb,
+
+ // CPLD interface
+ output cpld_start, // AA9
+ output cpld_mode, // U12
+ output cpld_done, // V12
+ input cpld_din, // AA14 Now shared with CFG_Din
+ input cpld_clk, // AB14 serial clock
+
+ // ADC
+ input [13:0] adc_a,
+ input adc_ovf_a,
+ output adc_oen_a,
+ output adc_pdn_a,
+
+ input [13:0] adc_b,
+ input adc_ovf_b,
+ output adc_oen_b,
+ output adc_pdn_b,
+
+ // DAC
+ output [15:0] dac_a,
+ output [15:0] dac_b,
+
+ // I2C
+ inout SCL,
+ inout SDA,
+ input SCL_force,
+ input SDA_force,
+
+ // Clock Gen Control
+ output [1:0] clk_en,
+ output [1:0] clk_sel,
+ input clk_func, // FIXME is an input to control the 9510
+ input clk_status,
+
+ // Clocks
+ input clk_fpga_p, // Diff
+ input clk_fpga_n, // Diff
+ input clk_to_mac,
+ input pps_in,
+
+ // Generic SPI
+ output sclk,
+ output sen_clk,
+ output sen_dac,
+ output sdi,
+ input sdo,
+
+ // TX DBoard
+ output sen_tx_db,
+ output sclk_tx_db,
+ input sdo_tx_db,
+ output sdi_tx_db,
+
+ output sen_tx_adc,
+ output sclk_tx_adc,
+ input sdo_tx_adc,
+ output sdi_tx_adc,
+
+ output sen_tx_dac,
+ output sclk_tx_dac,
+ output sdi_tx_dac,
+
+ inout [15:0] io_tx,
+
+ // RX DBoard
+ output sen_rx_db,
+ output sclk_rx_db,
+ input sdo_rx_db,
+ output sdi_rx_db,
+
+ output sen_rx_adc,
+ output sclk_rx_adc,
+ input sdo_rx_adc,
+ output sdi_rx_adc,
+
+ output sen_rx_dac,
+ output sclk_rx_dac,
+ output sdi_rx_dac,
+
+ inout [15:0] io_rx
+ );
+
+ // FPGA-specific pins connections
+ wire aux_clk = PHY_CLK;
+ //wire cpld_detached = RAM_A[14]; // FIXME Hacked on with Blue Wire
+ wire cpld_detached = SDA_force; // FIXME Hacked on with Blue Wire
+
+ wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+
+ IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+ defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+
+ wire exp_pps_in;
+ IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
+ defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+
+ wire exp_pps_out;
+ OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
+ defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+
+ reg [5:0] clock_ready_d;
+ always @(posedge aux_clk)
+ clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
+
+ wire dcm_rst = ~&clock_ready_d & |clock_ready_d;
+ wire clk_muxed = clock_ready ? clk_fpga : aux_clk;
+
+ wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
+ assign adc_oen_a = ~adc_oe_a;
+ assign adc_oen_b = ~adc_oe_b;
+ assign adc_pdn_a = ~adc_on_a;
+ assign adc_pdn_b = ~adc_on_b;
+
+ // Handle Clocks
+ DCM DCM_INST (.CLKFB(dsp_clk),
+ .CLKIN(clk_muxed),
+ .DSSEN(0),
+ .PSCLK(0),
+ .PSEN(0),
+ .PSINCDEC(0),
+ .RST(dcm_rst),
+ .CLKDV(clk_div),
+ .CLKFX(),
+ .CLKFX180(),
+ .CLK0(dcm_out),
+ .CLK2X(),
+ .CLK2X180(),
+ .CLK90(),
+ .CLK180(),
+ .CLK270(),
+ .LOCKED(LOCKED_OUT),
+ .PSDONE(),
+ .STATUS());
+ defparam DCM_INST.CLK_FEEDBACK = "1X";
+ defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+ defparam DCM_INST.CLKFX_DIVIDE = 1;
+ defparam DCM_INST.CLKFX_MULTIPLY = 4;
+ defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+ defparam DCM_INST.CLKIN_PERIOD = 10.000;
+ defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+ defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+ defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+ defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+ defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+ defparam DCM_INST.FACTORY_JF = 16'h8080;
+ defparam DCM_INST.PHASE_SHIFT = 0;
+ defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+ BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
+ BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+
+ // I2C -- Don't use external transistors for open drain, the FPGA implements this
+ IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+ IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+ // LEDs are active low outputs
+ wire led1_int, led2_int;
+ assign led1 = ~led1_int;
+ assign led2 = ~led2_int;
+
+ // SPI
+ wire miso, mosi, sclk_int;
+ assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
+
+ assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) |
+ (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
+ (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+
+ wire GMII_TX_EN_unreg, GMII_TX_ER_unreg;
+ wire [7:0] GMII_TXD_unreg;
+ wire GMII_GTX_CLK_int;
+
+ always @(posedge GMII_GTX_CLK_int)
+ begin
+ GMII_TX_EN <= GMII_TX_EN_unreg;
+ GMII_TX_ER <= GMII_TX_ER_unreg;
+ GMII_TXD <= GMII_TXD_unreg;
+ end
+
+ OFDDRRSE OFDDRRSE_gmii_inst
+ (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port)
+ .C0(GMII_GTX_CLK_int), // 0 degree clock input
+ .C1(~GMII_GTX_CLK_int), // 180 degree clock input
+ .CE(1), // Clock enable input
+ .D0(0), // Posedge data input
+ .D1(1), // Negedge data input
+ .R(0), // Synchronous reset input
+ .S(0) // Synchronous preset input
+ );
+
+ wire ser_tklsb_unreg, ser_tkmsb_unreg;
+ wire [15:0] ser_t_unreg;
+ wire ser_tx_clk_int;
+
+ always @(posedge ser_tx_clk_int)
+ begin
+ ser_tklsb <= ser_tklsb_unreg;
+ ser_tkmsb <= ser_tkmsb_unreg;
+ ser_t <= ser_t_unreg;
+ end
+
+ assign ser_tx_clk = clk_fpga;
+
+ reg [15:0] ser_r_int;
+ reg ser_rklsb_int, ser_rkmsb_int;
+
+ always @(posedge ser_rx_clk)
+ begin
+ ser_r_int <= ser_r;
+ ser_rklsb_int <= ser_rklsb;
+ ser_rkmsb_int <= ser_rkmsb;
+ end
+
+ /*
+ OFDDRRSE OFDDRRSE_serdes_inst
+ (.Q(ser_tx_clk), // Data output (connect directly to top-level port)
+ .C0(ser_tx_clk_int), // 0 degree clock input
+ .C1(~ser_tx_clk_int), // 180 degree clock input
+ .CE(1), // Clock enable input
+ .D0(0), // Posedge data input
+ .D1(1), // Negedge data input
+ .R(0), // Synchronous reset input
+ .S(0) // Synchronous preset input
+ );
+ */
+ u2_basic u2_basic(.dsp_clk (dsp_clk),
+ .wb_clk (wb_clk),
+ .clock_ready (clock_ready),
+ .clk_to_mac (clk_to_mac),
+ .pps_in (pps_in),
+ .led1 (led1_int),
+ .led2 (led2_int),
+ .debug (debug[31:0]),
+ .debug_clk (debug_clk[1:0]),
+ .exp_pps_in (exp_pps_in),
+ .exp_pps_out (exp_pps_out),
+ .GMII_COL (GMII_COL),
+ .GMII_CRS (GMII_CRS),
+ .GMII_TXD (GMII_TXD_unreg[7:0]),
+ .GMII_TX_EN (GMII_TX_EN_unreg),
+ .GMII_TX_ER (GMII_TX_ER_unreg),
+ .GMII_GTX_CLK (GMII_GTX_CLK_int),
+ .GMII_TX_CLK (GMII_TX_CLK),
+ .GMII_RXD (GMII_RXD[7:0]),
+ .GMII_RX_CLK (GMII_RX_CLK),
+ .GMII_RX_DV (GMII_RX_DV),
+ .GMII_RX_ER (GMII_RX_ER),
+ .MDIO (MDIO),
+ .MDC (MDC),
+ .PHY_INTn (PHY_INTn),
+ .PHY_RESETn (PHY_RESETn),
+ .PHY_CLK (PHY_CLK),
+ .ser_enable (ser_enable),
+ .ser_prbsen (ser_prbsen),
+ .ser_loopen (ser_loopen),
+ .ser_rx_en (ser_rx_en),
+ .ser_tx_clk (ser_tx_clk_int),
+ .ser_t (ser_t_unreg[15:0]),
+ .ser_tklsb (ser_tklsb_unreg),
+ .ser_tkmsb (ser_tkmsb_unreg),
+ .ser_rx_clk (ser_rx_clk),
+ .ser_r (ser_r_int[15:0]),
+ .ser_rklsb (ser_rklsb_int),
+ .ser_rkmsb (ser_rkmsb_int),
+ .cpld_start (cpld_start),
+ .cpld_mode (cpld_mode),
+ .cpld_done (cpld_done),
+ .cpld_din (cpld_din),
+ .cpld_clk (cpld_clk),
+ .cpld_detached (cpld_detached),
+ .adc_a (adc_a[13:0]),
+ .adc_ovf_a (adc_ovf_a),
+ .adc_on_a (adc_on_a),
+ .adc_oe_a (adc_oe_a),
+ .adc_b (adc_b[13:0]),
+ .adc_ovf_b (adc_ovf_b),
+ .adc_on_b (adc_on_b),
+ .adc_oe_b (adc_oe_b),
+ .dac_a (dac_a[15:0]),
+ .dac_b (dac_b[15:0]),
+ .scl_pad_i (scl_pad_i),
+ .scl_pad_o (scl_pad_o),
+ .scl_pad_oen_o (scl_pad_oen_o),
+ .sda_pad_i (sda_pad_i),
+ .sda_pad_o (sda_pad_o),
+ .sda_pad_oen_o (sda_pad_oen_o),
+ .clk_en (clk_en[1:0]),
+ .clk_sel (clk_sel[1:0]),
+ .clk_func (clk_func),
+ .clk_status (clk_status),
+ .sclk (sclk_int),
+ .mosi (mosi),
+ .miso (miso),
+ .sen_clk (sen_clk),
+ .sen_dac (sen_dac),
+ .sen_tx_db (sen_tx_db),
+ .sen_tx_adc (sen_tx_adc),
+ .sen_tx_dac (sen_tx_dac),
+ .sen_rx_db (sen_rx_db),
+ .sen_rx_adc (sen_rx_adc),
+ .sen_rx_dac (sen_rx_dac),
+ .io_tx (io_tx[15:0]),
+ .io_rx (io_rx[15:0]),
+ .RAM_D (RAM_D),
+ .RAM_A (RAM_A),
+ .RAM_CE1n (RAM_CE1n),
+ .RAM_CENn (RAM_CENn),
+ .RAM_CLK (RAM_CLK),
+ .RAM_WEn (RAM_WEn),
+ .RAM_OEn (RAM_OEn),
+ .RAM_LDn (RAM_LDn),
+ .uart_tx_o (),
+ .uart_rx_i (),
+ .uart_baud_o (),
+ .sim_mode (1'b0),
+ .clock_divider (2)
+ );
+
+endmodule // u2_fpga_top
projects / debian / gnuradio / commitdiff