Document the mem_ap target type

Change-Id: I56e971b38f20db8c4ad0cdee5cc42b42a25319ea
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5029
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 027e6d2edbb9d915b7e41da99d989d0a1bb20872..f5852cc09eb02d164e678b4340967c0981f1cf80 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4367,6 +4367,7 @@ compact Thumb2 instruction set.
 The current implementation supports eSi-32xx cores.
 @item @code{fa526} -- resembles arm920 (w/o Thumb)
 @item @code{feroceon} -- resembles arm926
+@item @code{mem_ap} -- this is an ARM debug infrastructure Access Port without a CPU, through which bus read and write cycles can be generated; it may be useful for working with non-CPU hardware behind an AP or during development of support for new CPUs.
 @item @code{mips_m4k} -- a MIPS core
 @item @code{xscale} -- this is actually an architecture,
 not a CPU type. It is based on the ARMv5 architecture.